drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_gem_dmabuf.h"
  40 #include "intel_dsi.h"
  41 #include "i915_trace.h"
  42 #include <drm/drm_atomic.h>
  43 #include <drm/drm_atomic_helper.h>
  44 #include <drm/drm_dp_helper.h>
  45 #include <drm/drm_crtc_helper.h>
  46 #include <drm/drm_plane_helper.h>
  47 #include <drm/drm_rect.h>
  48 #include <linux/dma_remapping.h>
  49 #include <linux/reservation.h>
  50
  51 static bool is_mmio_work(struct intel_flip_work *work)
  52 {
  53         return work->mmio_work.func;
  54 }
  55
  56 /* Primary plane formats for gen <= 3 */
  57 static const uint32_t i8xx_primary_formats[] = {
  58         DRM_FORMAT_C8,
  59         DRM_FORMAT_RGB565,
  60         DRM_FORMAT_XRGB1555,
  61         DRM_FORMAT_XRGB8888,
  62 };
  63
  64 /* Primary plane formats for gen >= 4 */
  65 static const uint32_t i965_primary_formats[] = {
  66         DRM_FORMAT_C8,
  67         DRM_FORMAT_RGB565,
  68         DRM_FORMAT_XRGB8888,
  69         DRM_FORMAT_XBGR8888,
  70         DRM_FORMAT_XRGB2101010,
  71         DRM_FORMAT_XBGR2101010,
  72 };
  73
  74 static const uint32_t skl_primary_formats[] = {
  75         DRM_FORMAT_C8,
  76         DRM_FORMAT_RGB565,
  77         DRM_FORMAT_XRGB8888,
  78         DRM_FORMAT_XBGR8888,
  79         DRM_FORMAT_ARGB8888,
  80         DRM_FORMAT_ABGR8888,
  81         DRM_FORMAT_XRGB2101010,
  82         DRM_FORMAT_XBGR2101010,
  83         DRM_FORMAT_YUYV,
  84         DRM_FORMAT_YVYU,
  85         DRM_FORMAT_UYVY,
  86         DRM_FORMAT_VYUY,
  87 };
  88
  89 /* Cursor formats */
  90 static const uint32_t intel_cursor_formats[] = {
  91         DRM_FORMAT_ARGB8888,
  92 };
  93
  94 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  95                                 struct intel_crtc_state *pipe_config);
  96 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  97                                    struct intel_crtc_state *pipe_config);
  98
  99 static int intel_framebuffer_init(struct drm_device *dev,
 100                                   struct intel_framebuffer *ifb,
 101                                   struct drm_mode_fb_cmd2 *mode_cmd,
 102                                   struct drm_i915_gem_object *obj);
 103 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
 104 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
 105 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
 106 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
 107                                          struct intel_link_m_n *m_n,
 108                                          struct intel_link_m_n *m2_n2);
 109 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
 110 static void haswell_set_pipeconf(struct drm_crtc *crtc);
 111 static void haswell_set_pipemisc(struct drm_crtc *crtc);
 112 static void vlv_prepare_pll(struct intel_crtc *crtc,
 113                             const struct intel_crtc_state *pipe_config);
 114 static void chv_prepare_pll(struct intel_crtc *crtc,
 115                             const struct intel_crtc_state *pipe_config);
 116 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 117 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 118 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
 119         struct intel_crtc_state *crtc_state);
 120 static void skylake_pfit_enable(struct intel_crtc *crtc);
 121 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
 122 static void ironlake_pfit_enable(struct intel_crtc *crtc);
 123 static void intel_modeset_setup_hw_state(struct drm_device *dev);
 124 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
 125 static int ilk_max_pixel_rate(struct drm_atomic_state *state);
 126 static int bxt_calc_cdclk(int max_pixclk);
 127
 128 struct intel_limit {
 129         struct {
 130                 int min, max;
 131         } dot, vco, n, m, m1, m2, p, p1;
 132
 133         struct {
 134                 int dot_limit;
 135                 int p2_slow, p2_fast;
 136         } p2;
 137 };
 138
 139 /* returns HPLL frequency in kHz */
 140 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
 141 {
 142         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
 143
 144         /* Obtain SKU information */
 145         mutex_lock(&dev_priv->sb_lock);
 146         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
 147                 CCK_FUSE_HPLL_FREQ_MASK;
 148         mutex_unlock(&dev_priv->sb_lock);
 149
 150         return vco_freq[hpll_freq] * 1000;
 151 }
 152
 153 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
 154                       const char *name, u32 reg, int ref_freq)
 155 {
 156         u32 val;
 157         int divider;
 158
 159         mutex_lock(&dev_priv->sb_lock);
 160         val = vlv_cck_read(dev_priv, reg);
 161         mutex_unlock(&dev_priv->sb_lock);
 162
 163         divider = val & CCK_FREQUENCY_VALUES;
 164
 165         WARN((val & CCK_FREQUENCY_STATUS) !=
 166              (divider << CCK_FREQUENCY_STATUS_SHIFT),
 167              "%s change in progress\n", name);
 168
 169         return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
 170 }
 171
 172 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
 173                                   const char *name, u32 reg)
 174 {
 175         if (dev_priv->hpll_freq == 0)
 176                 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
 177
 178         return vlv_get_cck_clock(dev_priv, name, reg,
 179                                  dev_priv->hpll_freq);
 180 }
 181
 182 static int
 183 intel_pch_rawclk(struct drm_i915_private *dev_priv)
 184 {
 185         return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
 186 }
 187
 188 static int
 189 intel_vlv_hrawclk(struct drm_i915_private *dev_priv)
 190 {
 191         /* RAWCLK_FREQ_VLV register updated from power well code */
 192         return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
 193                                       CCK_DISPLAY_REF_CLOCK_CONTROL);
 194 }
 195
 196 static int
 197 intel_g4x_hrawclk(struct drm_i915_private *dev_priv)
 198 {
 199         uint32_t clkcfg;
 200
 201         /* hrawclock is 1/4 the FSB frequency */
 202         clkcfg = I915_READ(CLKCFG);
 203         switch (clkcfg & CLKCFG_FSB_MASK) {
 204         case CLKCFG_FSB_400:
 205                 return 100000;
 206         case CLKCFG_FSB_533:
 207                 return 133333;
 208         case CLKCFG_FSB_667:
 209                 return 166667;
 210         case CLKCFG_FSB_800:
 211                 return 200000;
 212         case CLKCFG_FSB_1067:
 213                 return 266667;
 214         case CLKCFG_FSB_1333:
 215                 return 333333;
 216         /* these two are just a guess; one of them might be right */
 217         case CLKCFG_FSB_1600:
 218         case CLKCFG_FSB_1600_ALT:
 219                 return 400000;
 220         default:
 221                 return 133333;
 222         }
 223 }
 224
 225 void intel_update_rawclk(struct drm_i915_private *dev_priv)
 226 {
 227         if (HAS_PCH_SPLIT(dev_priv))
 228                 dev_priv->rawclk_freq = intel_pch_rawclk(dev_priv);
 229         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 230                 dev_priv->rawclk_freq = intel_vlv_hrawclk(dev_priv);
 231         else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv))
 232                 dev_priv->rawclk_freq = intel_g4x_hrawclk(dev_priv);
 233         else
 234                 return; /* no rawclk on other platforms, or no need to know it */
 235
 236         DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq);
 237 }
 238
 239 static void intel_update_czclk(struct drm_i915_private *dev_priv)
 240 {
 241         if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
 242                 return;
 243
 244         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
 245                                                       CCK_CZ_CLOCK_CONTROL);
 246
 247         DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
 248 }
 249
 250 static inline u32 /* units of 100MHz */
 251 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
 252                     const struct intel_crtc_state *pipe_config)
 253 {
 254         if (HAS_DDI(dev_priv))
 255                 return pipe_config->port_clock; /* SPLL */
 256         else if (IS_GEN5(dev_priv))
 257                 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
 258         else
 259                 return 270000;
 260 }
 261
 262 static const struct intel_limit intel_limits_i8xx_dac = {
 263         .dot = { .min = 25000, .max = 350000 },
 264         .vco = { .min = 908000, .max = 1512000 },
 265         .n = { .min = 2, .max = 16 },
 266         .m = { .min = 96, .max = 140 },
 267         .m1 = { .min = 18, .max = 26 },
 268         .m2 = { .min = 6, .max = 16 },
 269         .p = { .min = 4, .max = 128 },
 270         .p1 = { .min = 2, .max = 33 },
 271         .p2 = { .dot_limit = 165000,
 272                 .p2_slow = 4, .p2_fast = 2 },
 273 };
 274
 275 static const struct intel_limit intel_limits_i8xx_dvo = {
 276         .dot = { .min = 25000, .max = 350000 },
 277         .vco = { .min = 908000, .max = 1512000 },
 278         .n = { .min = 2, .max = 16 },
 279         .m = { .min = 96, .max = 140 },
 280         .m1 = { .min = 18, .max = 26 },
 281         .m2 = { .min = 6, .max = 16 },
 282         .p = { .min = 4, .max = 128 },
 283         .p1 = { .min = 2, .max = 33 },
 284         .p2 = { .dot_limit = 165000,
 285                 .p2_slow = 4, .p2_fast = 4 },
 286 };
 287
 288 static const struct intel_limit intel_limits_i8xx_lvds = {
 289         .dot = { .min = 25000, .max = 350000 },
 290         .vco = { .min = 908000, .max = 1512000 },
 291         .n = { .min = 2, .max = 16 },
 292         .m = { .min = 96, .max = 140 },
 293         .m1 = { .min = 18, .max = 26 },
 294         .m2 = { .min = 6, .max = 16 },
 295         .p = { .min = 4, .max = 128 },
 296         .p1 = { .min = 1, .max = 6 },
 297         .p2 = { .dot_limit = 165000,
 298                 .p2_slow = 14, .p2_fast = 7 },
 299 };
 300
 301 static const struct intel_limit intel_limits_i9xx_sdvo = {
 302         .dot = { .min = 20000, .max = 400000 },
 303         .vco = { .min = 1400000, .max = 2800000 },
 304         .n = { .min = 1, .max = 6 },
 305         .m = { .min = 70, .max = 120 },
 306         .m1 = { .min = 8, .max = 18 },
 307         .m2 = { .min = 3, .max = 7 },
 308         .p = { .min = 5, .max = 80 },
 309         .p1 = { .min = 1, .max = 8 },
 310         .p2 = { .dot_limit = 200000,
 311                 .p2_slow = 10, .p2_fast = 5 },
 312 };
 313
 314 static const struct intel_limit intel_limits_i9xx_lvds = {
 315         .dot = { .min = 20000, .max = 400000 },
 316         .vco = { .min = 1400000, .max = 2800000 },
 317         .n = { .min = 1, .max = 6 },
 318         .m = { .min = 70, .max = 120 },
 319         .m1 = { .min = 8, .max = 18 },
 320         .m2 = { .min = 3, .max = 7 },
 321         .p = { .min = 7, .max = 98 },
 322         .p1 = { .min = 1, .max = 8 },
 323         .p2 = { .dot_limit = 112000,
 324                 .p2_slow = 14, .p2_fast = 7 },
 325 };
 326
 327
 328 static const struct intel_limit intel_limits_g4x_sdvo = {
 329         .dot = { .min = 25000, .max = 270000 },
 330         .vco = { .min = 1750000, .max = 3500000},
 331         .n = { .min = 1, .max = 4 },
 332         .m = { .min = 104, .max = 138 },
 333         .m1 = { .min = 17, .max = 23 },
 334         .m2 = { .min = 5, .max = 11 },
 335         .p = { .min = 10, .max = 30 },
 336         .p1 = { .min = 1, .max = 3},
 337         .p2 = { .dot_limit = 270000,
 338                 .p2_slow = 10,
 339                 .p2_fast = 10
 340         },
 341 };
 342
 343 static const struct intel_limit intel_limits_g4x_hdmi = {
 344         .dot = { .min = 22000, .max = 400000 },
 345         .vco = { .min = 1750000, .max = 3500000},
 346         .n = { .min = 1, .max = 4 },
 347         .m = { .min = 104, .max = 138 },
 348         .m1 = { .min = 16, .max = 23 },
 349         .m2 = { .min = 5, .max = 11 },
 350         .p = { .min = 5, .max = 80 },
 351         .p1 = { .min = 1, .max = 8},
 352         .p2 = { .dot_limit = 165000,
 353                 .p2_slow = 10, .p2_fast = 5 },
 354 };
 355
 356 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
 357         .dot = { .min = 20000, .max = 115000 },
 358         .vco = { .min = 1750000, .max = 3500000 },
 359         .n = { .min = 1, .max = 3 },
 360         .m = { .min = 104, .max = 138 },
 361         .m1 = { .min = 17, .max = 23 },
 362         .m2 = { .min = 5, .max = 11 },
 363         .p = { .min = 28, .max = 112 },
 364         .p1 = { .min = 2, .max = 8 },
 365         .p2 = { .dot_limit = 0,
 366                 .p2_slow = 14, .p2_fast = 14
 367         },
 368 };
 369
 370 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
 371         .dot = { .min = 80000, .max = 224000 },
 372         .vco = { .min = 1750000, .max = 3500000 },
 373         .n = { .min = 1, .max = 3 },
 374         .m = { .min = 104, .max = 138 },
 375         .m1 = { .min = 17, .max = 23 },
 376         .m2 = { .min = 5, .max = 11 },
 377         .p = { .min = 14, .max = 42 },
 378         .p1 = { .min = 2, .max = 6 },
 379         .p2 = { .dot_limit = 0,
 380                 .p2_slow = 7, .p2_fast = 7
 381         },
 382 };
 383
 384 static const struct intel_limit intel_limits_pineview_sdvo = {
 385         .dot = { .min = 20000, .max = 400000},
 386         .vco = { .min = 1700000, .max = 3500000 },
 387         /* Pineview's Ncounter is a ring counter */
 388         .n = { .min = 3, .max = 6 },
 389         .m = { .min = 2, .max = 256 },
 390         /* Pineview only has one combined m divider, which we treat as m2. */
 391         .m1 = { .min = 0, .max = 0 },
 392         .m2 = { .min = 0, .max = 254 },
 393         .p = { .min = 5, .max = 80 },
 394         .p1 = { .min = 1, .max = 8 },
 395         .p2 = { .dot_limit = 200000,
 396                 .p2_slow = 10, .p2_fast = 5 },
 397 };
 398
 399 static const struct intel_limit intel_limits_pineview_lvds = {
 400         .dot = { .min = 20000, .max = 400000 },
 401         .vco = { .min = 1700000, .max = 3500000 },
 402         .n = { .min = 3, .max = 6 },
 403         .m = { .min = 2, .max = 256 },
 404         .m1 = { .min = 0, .max = 0 },
 405         .m2 = { .min = 0, .max = 254 },
 406         .p = { .min = 7, .max = 112 },
 407         .p1 = { .min = 1, .max = 8 },
 408         .p2 = { .dot_limit = 112000,
 409                 .p2_slow = 14, .p2_fast = 14 },
 410 };
 411
 412 /* Ironlake / Sandybridge
 413  *
 414  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 415  * the range value for them is (actual_value - 2).
 416  */
 417 static const struct intel_limit intel_limits_ironlake_dac = {
 418         .dot = { .min = 25000, .max = 350000 },
 419         .vco = { .min = 1760000, .max = 3510000 },
 420         .n = { .min = 1, .max = 5 },
 421         .m = { .min = 79, .max = 127 },
 422         .m1 = { .min = 12, .max = 22 },
 423         .m2 = { .min = 5, .max = 9 },
 424         .p = { .min = 5, .max = 80 },
 425         .p1 = { .min = 1, .max = 8 },
 426         .p2 = { .dot_limit = 225000,
 427                 .p2_slow = 10, .p2_fast = 5 },
 428 };
 429
 430 static const struct intel_limit intel_limits_ironlake_single_lvds = {
 431         .dot = { .min = 25000, .max = 350000 },
 432         .vco = { .min = 1760000, .max = 3510000 },
 433         .n = { .min = 1, .max = 3 },
 434         .m = { .min = 79, .max = 118 },
 435         .m1 = { .min = 12, .max = 22 },
 436         .m2 = { .min = 5, .max = 9 },
 437         .p = { .min = 28, .max = 112 },
 438         .p1 = { .min = 2, .max = 8 },
 439         .p2 = { .dot_limit = 225000,
 440                 .p2_slow = 14, .p2_fast = 14 },
 441 };
 442
 443 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
 444         .dot = { .min = 25000, .max = 350000 },
 445         .vco = { .min = 1760000, .max = 3510000 },
 446         .n = { .min = 1, .max = 3 },
 447         .m = { .min = 79, .max = 127 },
 448         .m1 = { .min = 12, .max = 22 },
 449         .m2 = { .min = 5, .max = 9 },
 450         .p = { .min = 14, .max = 56 },
 451         .p1 = { .min = 2, .max = 8 },
 452         .p2 = { .dot_limit = 225000,
 453                 .p2_slow = 7, .p2_fast = 7 },
 454 };
 455
 456 /* LVDS 100mhz refclk limits. */
 457 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
 458         .dot = { .min = 25000, .max = 350000 },
 459         .vco = { .min = 1760000, .max = 3510000 },
 460         .n = { .min = 1, .max = 2 },
 461         .m = { .min = 79, .max = 126 },
 462         .m1 = { .min = 12, .max = 22 },
 463         .m2 = { .min = 5, .max = 9 },
 464         .p = { .min = 28, .max = 112 },
 465         .p1 = { .min = 2, .max = 8 },
 466         .p2 = { .dot_limit = 225000,
 467                 .p2_slow = 14, .p2_fast = 14 },
 468 };
 469
 470 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
 471         .dot = { .min = 25000, .max = 350000 },
 472         .vco = { .min = 1760000, .max = 3510000 },
 473         .n = { .min = 1, .max = 3 },
 474         .m = { .min = 79, .max = 126 },
 475         .m1 = { .min = 12, .max = 22 },
 476         .m2 = { .min = 5, .max = 9 },
 477         .p = { .min = 14, .max = 42 },
 478         .p1 = { .min = 2, .max = 6 },
 479         .p2 = { .dot_limit = 225000,
 480                 .p2_slow = 7, .p2_fast = 7 },
 481 };
 482
 483 static const struct intel_limit intel_limits_vlv = {
 484          /*
 485           * These are the data rate limits (measured in fast clocks)
 486           * since those are the strictest limits we have. The fast
 487           * clock and actual rate limits are more relaxed, so checking
 488           * them would make no difference.
 489           */
 490         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 491         .vco = { .min = 4000000, .max = 6000000 },
 492         .n = { .min = 1, .max = 7 },
 493         .m1 = { .min = 2, .max = 3 },
 494         .m2 = { .min = 11, .max = 156 },
 495         .p1 = { .min = 2, .max = 3 },
 496         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 497 };
 498
 499 static const struct intel_limit intel_limits_chv = {
 500         /*
 501          * These are the data rate limits (measured in fast clocks)
 502          * since those are the strictest limits we have.  The fast
 503          * clock and actual rate limits are more relaxed, so checking
 504          * them would make no difference.
 505          */
 506         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 507         .vco = { .min = 4800000, .max = 6480000 },
 508         .n = { .min = 1, .max = 1 },
 509         .m1 = { .min = 2, .max = 2 },
 510         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 511         .p1 = { .min = 2, .max = 4 },
 512         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 513 };
 514
 515 static const struct intel_limit intel_limits_bxt = {
 516         /* FIXME: find real dot limits */
 517         .dot = { .min = 0, .max = INT_MAX },
 518         .vco = { .min = 4800000, .max = 6700000 },
 519         .n = { .min = 1, .max = 1 },
 520         .m1 = { .min = 2, .max = 2 },
 521         /* FIXME: find real m2 limits */
 522         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 523         .p1 = { .min = 2, .max = 4 },
 524         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 525 };
 526
 527 static bool
 528 needs_modeset(struct drm_crtc_state *state)
 529 {
 530         return drm_atomic_crtc_needs_modeset(state);
 531 }
 532
 533 /**
 534  * Returns whether any output on the specified pipe is of the specified type
 535  */
 536 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
 537 {
 538         struct drm_device *dev = crtc->base.dev;
 539         struct intel_encoder *encoder;
 540
 541         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
 542                 if (encoder->type == type)
 543                         return true;
 544
 545         return false;
 546 }
 547
 548 /**
 549  * Returns whether any output on the specified pipe will have the specified
 550  * type after a staged modeset is complete, i.e., the same as
 551  * intel_pipe_has_type() but looking at encoder->new_crtc instead of
 552  * encoder->crtc.
 553  */
 554 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
 555                                       int type)
 556 {
 557         struct drm_atomic_state *state = crtc_state->base.state;
 558         struct drm_connector *connector;
 559         struct drm_connector_state *connector_state;
 560         struct intel_encoder *encoder;
 561         int i, num_connectors = 0;
 562
 563         for_each_connector_in_state(state, connector, connector_state, i) {
 564                 if (connector_state->crtc != crtc_state->base.crtc)
 565                         continue;
 566
 567                 num_connectors++;
 568
 569                 encoder = to_intel_encoder(connector_state->best_encoder);
 570                 if (encoder->type == type)
 571                         return true;
 572         }
 573
 574         WARN_ON(num_connectors == 0);
 575
 576         return false;
 577 }
 578
 579 /*
 580  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
 581  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
 582  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
 583  * The helpers' return value is the rate of the clock that is fed to the
 584  * display engine's pipe which can be the above fast dot clock rate or a
 585  * divided-down version of it.
 586  */
 587 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 588 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
 589 {
 590         clock->m = clock->m2 + 2;
 591         clock->p = clock->p1 * clock->p2;
 592         if (WARN_ON(clock->n == 0 || clock->p == 0))
 593                 return 0;
 594         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 595         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 596
 597         return clock->dot;
 598 }
 599
 600 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 601 {
 602         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 603 }
 604
 605 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
 606 {
 607         clock->m = i9xx_dpll_compute_m(clock);
 608         clock->p = clock->p1 * clock->p2;
 609         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 610                 return 0;
 611         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 612         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 613
 614         return clock->dot;
 615 }
 616
 617 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
 618 {
 619         clock->m = clock->m1 * clock->m2;
 620         clock->p = clock->p1 * clock->p2;
 621         if (WARN_ON(clock->n == 0 || clock->p == 0))
 622                 return 0;
 623         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 624         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 625
 626         return clock->dot / 5;
 627 }
 628
 629 int chv_calc_dpll_params(int refclk, struct dpll *clock)
 630 {
 631         clock->m = clock->m1 * clock->m2;
 632         clock->p = clock->p1 * clock->p2;
 633         if (WARN_ON(clock->n == 0 || clock->p == 0))
 634                 return 0;
 635         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 636                         clock->n << 22);
 637         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 638
 639         return clock->dot / 5;
 640 }
 641
 642 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 643 /**
 644  * Returns whether the given set of divisors are valid for a given refclk with
 645  * the given connectors.
 646  */
 647
 648 static bool intel_PLL_is_valid(struct drm_device *dev,
 649                                const struct intel_limit *limit,
 650                                const struct dpll *clock)
 651 {
 652         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 653                 INTELPllInvalid("n out of range\n");
 654         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 655                 INTELPllInvalid("p1 out of range\n");
 656         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 657                 INTELPllInvalid("m2 out of range\n");
 658         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 659                 INTELPllInvalid("m1 out of range\n");
 660
 661         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) &&
 662             !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev))
 663                 if (clock->m1 <= clock->m2)
 664                         INTELPllInvalid("m1 <= m2\n");
 665
 666         if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) {
 667                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 668                         INTELPllInvalid("p out of range\n");
 669                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 670                         INTELPllInvalid("m out of range\n");
 671         }
 672
 673         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 674                 INTELPllInvalid("vco out of range\n");
 675         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 676          * connector, etc., rather than just a single range.
 677          */
 678         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 679                 INTELPllInvalid("dot out of range\n");
 680
 681         return true;
 682 }
 683
 684 static int
 685 i9xx_select_p2_div(const struct intel_limit *limit,
 686                    const struct intel_crtc_state *crtc_state,
 687                    int target)
 688 {
 689         struct drm_device *dev = crtc_state->base.crtc->dev;
 690
 691         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 692                 /*
 693                  * For LVDS just rely on its current settings for dual-channel.
 694                  * We haven't figured out how to reliably set up different
 695                  * single/dual channel state, if we even can.
 696                  */
 697                 if (intel_is_dual_link_lvds(dev))
 698                         return limit->p2.p2_fast;
 699                 else
 700                         return limit->p2.p2_slow;
 701         } else {
 702                 if (target < limit->p2.dot_limit)
 703                         return limit->p2.p2_slow;
 704                 else
 705                         return limit->p2.p2_fast;
 706         }
 707 }
 708
 709 /*
 710  * Returns a set of divisors for the desired target clock with the given
 711  * refclk, or FALSE.  The returned values represent the clock equation:
 712  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 713  *
 714  * Target and reference clocks are specified in kHz.
 715  *
 716  * If match_clock is provided, then best_clock P divider must match the P
 717  * divider from @match_clock used for LVDS downclocking.
 718  */
 719 static bool
 720 i9xx_find_best_dpll(const struct intel_limit *limit,
 721                     struct intel_crtc_state *crtc_state,
 722                     int target, int refclk, struct dpll *match_clock,
 723                     struct dpll *best_clock)
 724 {
 725         struct drm_device *dev = crtc_state->base.crtc->dev;
 726         struct dpll clock;
 727         int err = target;
 728
 729         memset(best_clock, 0, sizeof(*best_clock));
 730
 731         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 732
 733         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 734              clock.m1++) {
 735                 for (clock.m2 = limit->m2.min;
 736                      clock.m2 <= limit->m2.max; clock.m2++) {
 737                         if (clock.m2 >= clock.m1)
 738                                 break;
 739                         for (clock.n = limit->n.min;
 740                              clock.n <= limit->n.max; clock.n++) {
 741                                 for (clock.p1 = limit->p1.min;
 742                                         clock.p1 <= limit->p1.max; clock.p1++) {
 743                                         int this_err;
 744
 745                                         i9xx_calc_dpll_params(refclk, &clock);
 746                                         if (!intel_PLL_is_valid(dev, limit,
 747                                                                 &clock))
 748                                                 continue;
 749                                         if (match_clock &&
 750                                             clock.p != match_clock->p)
 751                                                 continue;
 752
 753                                         this_err = abs(clock.dot - target);
 754                                         if (this_err < err) {
 755                                                 *best_clock = clock;
 756                                                 err = this_err;
 757                                         }
 758                                 }
 759                         }
 760                 }
 761         }
 762
 763         return (err != target);
 764 }
 765
 766 /*
 767  * Returns a set of divisors for the desired target clock with the given
 768  * refclk, or FALSE.  The returned values represent the clock equation:
 769  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 770  *
 771  * Target and reference clocks are specified in kHz.
 772  *
 773  * If match_clock is provided, then best_clock P divider must match the P
 774  * divider from @match_clock used for LVDS downclocking.
 775  */
 776 static bool
 777 pnv_find_best_dpll(const struct intel_limit *limit,
 778                    struct intel_crtc_state *crtc_state,
 779                    int target, int refclk, struct dpll *match_clock,
 780                    struct dpll *best_clock)
 781 {
 782         struct drm_device *dev = crtc_state->base.crtc->dev;
 783         struct dpll clock;
 784         int err = target;
 785
 786         memset(best_clock, 0, sizeof(*best_clock));
 787
 788         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 789
 790         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 791              clock.m1++) {
 792                 for (clock.m2 = limit->m2.min;
 793                      clock.m2 <= limit->m2.max; clock.m2++) {
 794                         for (clock.n = limit->n.min;
 795                              clock.n <= limit->n.max; clock.n++) {
 796                                 for (clock.p1 = limit->p1.min;
 797                                         clock.p1 <= limit->p1.max; clock.p1++) {
 798                                         int this_err;
 799
 800                                         pnv_calc_dpll_params(refclk, &clock);
 801                                         if (!intel_PLL_is_valid(dev, limit,
 802                                                                 &clock))
 803                                                 continue;
 804                                         if (match_clock &&
 805                                             clock.p != match_clock->p)
 806                                                 continue;
 807
 808                                         this_err = abs(clock.dot - target);
 809                                         if (this_err < err) {
 810                                                 *best_clock = clock;
 811                                                 err = this_err;
 812                                         }
 813                                 }
 814                         }
 815                 }
 816         }
 817
 818         return (err != target);
 819 }
 820
 821 /*
 822  * Returns a set of divisors for the desired target clock with the given
 823  * refclk, or FALSE.  The returned values represent the clock equation:
 824  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 825  *
 826  * Target and reference clocks are specified in kHz.
 827  *
 828  * If match_clock is provided, then best_clock P divider must match the P
 829  * divider from @match_clock used for LVDS downclocking.
 830  */
 831 static bool
 832 g4x_find_best_dpll(const struct intel_limit *limit,
 833                    struct intel_crtc_state *crtc_state,
 834                    int target, int refclk, struct dpll *match_clock,
 835                    struct dpll *best_clock)
 836 {
 837         struct drm_device *dev = crtc_state->base.crtc->dev;
 838         struct dpll clock;
 839         int max_n;
 840         bool found = false;
 841         /* approximately equals target * 0.00585 */
 842         int err_most = (target >> 8) + (target >> 9);
 843
 844         memset(best_clock, 0, sizeof(*best_clock));
 845
 846         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 847
 848         max_n = limit->n.max;
 849         /* based on hardware requirement, prefer smaller n to precision */
 850         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 851                 /* based on hardware requirement, prefere larger m1,m2 */
 852                 for (clock.m1 = limit->m1.max;
 853                      clock.m1 >= limit->m1.min; clock.m1--) {
 854                         for (clock.m2 = limit->m2.max;
 855                              clock.m2 >= limit->m2.min; clock.m2--) {
 856                                 for (clock.p1 = limit->p1.max;
 857                                      clock.p1 >= limit->p1.min; clock.p1--) {
 858                                         int this_err;
 859
 860                                         i9xx_calc_dpll_params(refclk, &clock);
 861                                         if (!intel_PLL_is_valid(dev, limit,
 862                                                                 &clock))
 863                                                 continue;
 864
 865                                         this_err = abs(clock.dot - target);
 866                                         if (this_err < err_most) {
 867                                                 *best_clock = clock;
 868                                                 err_most = this_err;
 869                                                 max_n = clock.n;
 870                                                 found = true;
 871                                         }
 872                                 }
 873                         }
 874                 }
 875         }
 876         return found;
 877 }
 878
 879 /*
 880  * Check if the calculated PLL configuration is more optimal compared to the
 881  * best configuration and error found so far. Return the calculated error.
 882  */
 883 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 884                                const struct dpll *calculated_clock,
 885                                const struct dpll *best_clock,
 886                                unsigned int best_error_ppm,
 887                                unsigned int *error_ppm)
 888 {
 889         /*
 890          * For CHV ignore the error and consider only the P value.
 891          * Prefer a bigger P value based on HW requirements.
 892          */
 893         if (IS_CHERRYVIEW(dev)) {
 894                 *error_ppm = 0;
 895
 896                 return calculated_clock->p > best_clock->p;
 897         }
 898
 899         if (WARN_ON_ONCE(!target_freq))
 900                 return false;
 901
 902         *error_ppm = div_u64(1000000ULL *
 903                                 abs(target_freq - calculated_clock->dot),
 904                              target_freq);
 905         /*
 906          * Prefer a better P value over a better (smaller) error if the error
 907          * is small. Ensure this preference for future configurations too by
 908          * setting the error to 0.
 909          */
 910         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 911                 *error_ppm = 0;
 912
 913                 return true;
 914         }
 915
 916         return *error_ppm + 10 < best_error_ppm;
 917 }
 918
 919 /*
 920  * Returns a set of divisors for the desired target clock with the given
 921  * refclk, or FALSE.  The returned values represent the clock equation:
 922  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 923  */
 924 static bool
 925 vlv_find_best_dpll(const struct intel_limit *limit,
 926                    struct intel_crtc_state *crtc_state,
 927                    int target, int refclk, struct dpll *match_clock,
 928                    struct dpll *best_clock)
 929 {
 930         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 931         struct drm_device *dev = crtc->base.dev;
 932         struct dpll clock;
 933         unsigned int bestppm = 1000000;
 934         /* min update 19.2 MHz */
 935         int max_n = min(limit->n.max, refclk / 19200);
 936         bool found = false;
 937
 938         target *= 5; /* fast clock */
 939
 940         memset(best_clock, 0, sizeof(*best_clock));
 941
 942         /* based on hardware requirement, prefer smaller n to precision */
 943         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 944                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 945                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 946                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 947                                 clock.p = clock.p1 * clock.p2;
 948                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 949                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 950                                         unsigned int ppm;
 951
 952                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 953                                                                      refclk * clock.m1);
 954
 955                                         vlv_calc_dpll_params(refclk, &clock);
 956
 957                                         if (!intel_PLL_is_valid(dev, limit,
 958                                                                 &clock))
 959                                                 continue;
 960
 961                                         if (!vlv_PLL_is_optimal(dev, target,
 962                                                                 &clock,
 963                                                                 best_clock,
 964                                                                 bestppm, &ppm))
 965                                                 continue;
 966
 967                                         *best_clock = clock;
 968                                         bestppm = ppm;
 969                                         found = true;
 970                                 }
 971                         }
 972                 }
 973         }
 974
 975         return found;
 976 }
 977
 978 /*
 979  * Returns a set of divisors for the desired target clock with the given
 980  * refclk, or FALSE.  The returned values represent the clock equation:
 981  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 982  */
 983 static bool
 984 chv_find_best_dpll(const struct intel_limit *limit,
 985                    struct intel_crtc_state *crtc_state,
 986                    int target, int refclk, struct dpll *match_clock,
 987                    struct dpll *best_clock)
 988 {
 989         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 990         struct drm_device *dev = crtc->base.dev;
 991         unsigned int best_error_ppm;
 992         struct dpll clock;
 993         uint64_t m2;
 994         int found = false;
 995
 996         memset(best_clock, 0, sizeof(*best_clock));
 997         best_error_ppm = 1000000;
 998
 999         /*
1000          * Based on hardware doc, the n always set to 1, and m1 always
1001          * set to 2.  If requires to support 200Mhz refclk, we need to
1002          * revisit this because n may not 1 anymore.
1003          */
1004         clock.n = 1, clock.m1 = 2;
1005         target *= 5;    /* fast clock */
1006
1007         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
1008                 for (clock.p2 = limit->p2.p2_fast;
1009                                 clock.p2 >= limit->p2.p2_slow;
1010                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
1011                         unsigned int error_ppm;
1012
1013                         clock.p = clock.p1 * clock.p2;
1014
1015                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
1016                                         clock.n) << 22, refclk * clock.m1);
1017
1018                         if (m2 > INT_MAX/clock.m1)
1019                                 continue;
1020
1021                         clock.m2 = m2;
1022
1023                         chv_calc_dpll_params(refclk, &clock);
1024
1025                         if (!intel_PLL_is_valid(dev, limit, &clock))
1026                                 continue;
1027
1028                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1029                                                 best_error_ppm, &error_ppm))
1030                                 continue;
1031
1032                         *best_clock = clock;
1033                         best_error_ppm = error_ppm;
1034                         found = true;
1035                 }
1036         }
1037
1038         return found;
1039 }
1040
1041 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1042                         struct dpll *best_clock)
1043 {
1044         int refclk = 100000;
1045         const struct intel_limit *limit = &intel_limits_bxt;
1046
1047         return chv_find_best_dpll(limit, crtc_state,
1048                                   target_clock, refclk, NULL, best_clock);
1049 }
1050
1051 bool intel_crtc_active(struct drm_crtc *crtc)
1052 {
1053         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1054
1055         /* Be paranoid as we can arrive here with only partial
1056          * state retrieved from the hardware during setup.
1057          *
1058          * We can ditch the adjusted_mode.crtc_clock check as soon
1059          * as Haswell has gained clock readout/fastboot support.
1060          *
1061          * We can ditch the crtc->primary->fb check as soon as we can
1062          * properly reconstruct framebuffers.
1063          *
1064          * FIXME: The intel_crtc->active here should be switched to
1065          * crtc->state->active once we have proper CRTC states wired up
1066          * for atomic.
1067          */
1068         return intel_crtc->active && crtc->primary->state->fb &&
1069                 intel_crtc->config->base.adjusted_mode.crtc_clock;
1070 }
1071
1072 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1073                                              enum pipe pipe)
1074 {
1075         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1076         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1077
1078         return intel_crtc->config->cpu_transcoder;
1079 }
1080
1081 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1082 {
1083         struct drm_i915_private *dev_priv = dev->dev_private;
1084         i915_reg_t reg = PIPEDSL(pipe);
1085         u32 line1, line2;
1086         u32 line_mask;
1087
1088         if (IS_GEN2(dev))
1089                 line_mask = DSL_LINEMASK_GEN2;
1090         else
1091                 line_mask = DSL_LINEMASK_GEN3;
1092
1093         line1 = I915_READ(reg) & line_mask;
1094         msleep(5);
1095         line2 = I915_READ(reg) & line_mask;
1096
1097         return line1 == line2;
1098 }
1099
1100 /*
1101  * intel_wait_for_pipe_off - wait for pipe to turn off
1102  * @crtc: crtc whose pipe to wait for
1103  *
1104  * After disabling a pipe, we can't wait for vblank in the usual way,
1105  * spinning on the vblank interrupt status bit, since we won't actually
1106  * see an interrupt when the pipe is disabled.
1107  *
1108  * On Gen4 and above:
1109  *   wait for the pipe register state bit to turn off
1110  *
1111  * Otherwise:
1112  *   wait for the display line value to settle (it usually
1113  *   ends up stopping at the start of the next frame).
1114  *
1115  */
1116 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1117 {
1118         struct drm_device *dev = crtc->base.dev;
1119         struct drm_i915_private *dev_priv = dev->dev_private;
1120         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1121         enum pipe pipe = crtc->pipe;
1122
1123         if (INTEL_INFO(dev)->gen >= 4) {
1124                 i915_reg_t reg = PIPECONF(cpu_transcoder);
1125
1126                 /* Wait for the Pipe State to go off */
1127                 if (intel_wait_for_register(dev_priv,
1128                                             reg, I965_PIPECONF_ACTIVE, 0,
1129                                             100))
1130                         WARN(1, "pipe_off wait timed out\n");
1131         } else {
1132                 /* Wait for the display line to settle */
1133                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1134                         WARN(1, "pipe_off wait timed out\n");
1135         }
1136 }
1137
1138 /* Only for pre-ILK configs */
1139 void assert_pll(struct drm_i915_private *dev_priv,
1140                 enum pipe pipe, bool state)
1141 {
1142         u32 val;
1143         bool cur_state;
1144
1145         val = I915_READ(DPLL(pipe));
1146         cur_state = !!(val & DPLL_VCO_ENABLE);
1147         I915_STATE_WARN(cur_state != state,
1148              "PLL state assertion failure (expected %s, current %s)\n",
1149                         onoff(state), onoff(cur_state));
1150 }
1151
1152 /* XXX: the dsi pll is shared between MIPI DSI ports */
1153 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1154 {
1155         u32 val;
1156         bool cur_state;
1157
1158         mutex_lock(&dev_priv->sb_lock);
1159         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1160         mutex_unlock(&dev_priv->sb_lock);
1161
1162         cur_state = val & DSI_PLL_VCO_EN;
1163         I915_STATE_WARN(cur_state != state,
1164              "DSI PLL state assertion failure (expected %s, current %s)\n",
1165                         onoff(state), onoff(cur_state));
1166 }
1167
1168 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1169                           enum pipe pipe, bool state)
1170 {
1171         bool cur_state;
1172         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1173                                                                       pipe);
1174
1175         if (HAS_DDI(dev_priv)) {
1176                 /* DDI does not have a specific FDI_TX register */
1177                 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1178                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1179         } else {
1180                 u32 val = I915_READ(FDI_TX_CTL(pipe));
1181                 cur_state = !!(val & FDI_TX_ENABLE);
1182         }
1183         I915_STATE_WARN(cur_state != state,
1184              "FDI TX state assertion failure (expected %s, current %s)\n",
1185                         onoff(state), onoff(cur_state));
1186 }
1187 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1188 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1189
1190 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1191                           enum pipe pipe, bool state)
1192 {
1193         u32 val;
1194         bool cur_state;
1195
1196         val = I915_READ(FDI_RX_CTL(pipe));
1197         cur_state = !!(val & FDI_RX_ENABLE);
1198         I915_STATE_WARN(cur_state != state,
1199              "FDI RX state assertion failure (expected %s, current %s)\n",
1200                         onoff(state), onoff(cur_state));
1201 }
1202 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1203 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1204
1205 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1206                                       enum pipe pipe)
1207 {
1208         u32 val;
1209
1210         /* ILK FDI PLL is always enabled */
1211         if (IS_GEN5(dev_priv))
1212                 return;
1213
1214         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1215         if (HAS_DDI(dev_priv))
1216                 return;
1217
1218         val = I915_READ(FDI_TX_CTL(pipe));
1219         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1220 }
1221
1222 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1223                        enum pipe pipe, bool state)
1224 {
1225         u32 val;
1226         bool cur_state;
1227
1228         val = I915_READ(FDI_RX_CTL(pipe));
1229         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1230         I915_STATE_WARN(cur_state != state,
1231              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1232                         onoff(state), onoff(cur_state));
1233 }
1234
1235 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1236                            enum pipe pipe)
1237 {
1238         struct drm_device *dev = dev_priv->dev;
1239         i915_reg_t pp_reg;
1240         u32 val;
1241         enum pipe panel_pipe = PIPE_A;
1242         bool locked = true;
1243
1244         if (WARN_ON(HAS_DDI(dev)))
1245                 return;
1246
1247         if (HAS_PCH_SPLIT(dev)) {
1248                 u32 port_sel;
1249
1250                 pp_reg = PCH_PP_CONTROL;
1251                 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1252
1253                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1254                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1255                         panel_pipe = PIPE_B;
1256                 /* XXX: else fix for eDP */
1257         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1258                 /* presumably write lock depends on pipe, not port select */
1259                 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1260                 panel_pipe = pipe;
1261         } else {
1262                 pp_reg = PP_CONTROL;
1263                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1264                         panel_pipe = PIPE_B;
1265         }
1266
1267         val = I915_READ(pp_reg);
1268         if (!(val & PANEL_POWER_ON) ||
1269             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1270                 locked = false;
1271
1272         I915_STATE_WARN(panel_pipe == pipe && locked,
1273              "panel assertion failure, pipe %c regs locked\n",
1274              pipe_name(pipe));
1275 }
1276
1277 static void assert_cursor(struct drm_i915_private *dev_priv,
1278                           enum pipe pipe, bool state)
1279 {
1280         struct drm_device *dev = dev_priv->dev;
1281         bool cur_state;
1282
1283         if (IS_845G(dev) || IS_I865G(dev))
1284                 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1285         else
1286                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1287
1288         I915_STATE_WARN(cur_state != state,
1289              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1290                         pipe_name(pipe), onoff(state), onoff(cur_state));
1291 }
1292 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1293 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1294
1295 void assert_pipe(struct drm_i915_private *dev_priv,
1296                  enum pipe pipe, bool state)
1297 {
1298         bool cur_state;
1299         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1300                                                                       pipe);
1301         enum intel_display_power_domain power_domain;
1302
1303         /* if we need the pipe quirk it must be always on */
1304         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1305             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1306                 state = true;
1307
1308         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1309         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1310                 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1311                 cur_state = !!(val & PIPECONF_ENABLE);
1312
1313                 intel_display_power_put(dev_priv, power_domain);
1314         } else {
1315                 cur_state = false;
1316         }
1317
1318         I915_STATE_WARN(cur_state != state,
1319              "pipe %c assertion failure (expected %s, current %s)\n",
1320                         pipe_name(pipe), onoff(state), onoff(cur_state));
1321 }
1322
1323 static void assert_plane(struct drm_i915_private *dev_priv,
1324                          enum plane plane, bool state)
1325 {
1326         u32 val;
1327         bool cur_state;
1328
1329         val = I915_READ(DSPCNTR(plane));
1330         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1331         I915_STATE_WARN(cur_state != state,
1332              "plane %c assertion failure (expected %s, current %s)\n",
1333                         plane_name(plane), onoff(state), onoff(cur_state));
1334 }
1335
1336 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1337 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1338
1339 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1340                                    enum pipe pipe)
1341 {
1342         struct drm_device *dev = dev_priv->dev;
1343         int i;
1344
1345         /* Primary planes are fixed to pipes on gen4+ */
1346         if (INTEL_INFO(dev)->gen >= 4) {
1347                 u32 val = I915_READ(DSPCNTR(pipe));
1348                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1349                      "plane %c assertion failure, should be disabled but not\n",
1350                      plane_name(pipe));
1351                 return;
1352         }
1353
1354         /* Need to check both planes against the pipe */
1355         for_each_pipe(dev_priv, i) {
1356                 u32 val = I915_READ(DSPCNTR(i));
1357                 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1358                         DISPPLANE_SEL_PIPE_SHIFT;
1359                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1360                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1361                      plane_name(i), pipe_name(pipe));
1362         }
1363 }
1364
1365 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1366                                     enum pipe pipe)
1367 {
1368         struct drm_device *dev = dev_priv->dev;
1369         int sprite;
1370
1371         if (INTEL_INFO(dev)->gen >= 9) {
1372                 for_each_sprite(dev_priv, pipe, sprite) {
1373                         u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1374                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1375                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1376                              sprite, pipe_name(pipe));
1377                 }
1378         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1379                 for_each_sprite(dev_priv, pipe, sprite) {
1380                         u32 val = I915_READ(SPCNTR(pipe, sprite));
1381                         I915_STATE_WARN(val & SP_ENABLE,
1382                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1383                              sprite_name(pipe, sprite), pipe_name(pipe));
1384                 }
1385         } else if (INTEL_INFO(dev)->gen >= 7) {
1386                 u32 val = I915_READ(SPRCTL(pipe));
1387                 I915_STATE_WARN(val & SPRITE_ENABLE,
1388                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1389                      plane_name(pipe), pipe_name(pipe));
1390         } else if (INTEL_INFO(dev)->gen >= 5) {
1391                 u32 val = I915_READ(DVSCNTR(pipe));
1392                 I915_STATE_WARN(val & DVS_ENABLE,
1393                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1394                      plane_name(pipe), pipe_name(pipe));
1395         }
1396 }
1397
1398 static void assert_vblank_disabled(struct drm_crtc *crtc)
1399 {
1400         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1401                 drm_crtc_vblank_put(crtc);
1402 }
1403
1404 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1405                                     enum pipe pipe)
1406 {
1407         u32 val;
1408         bool enabled;
1409
1410         val = I915_READ(PCH_TRANSCONF(pipe));
1411         enabled = !!(val & TRANS_ENABLE);
1412         I915_STATE_WARN(enabled,
1413              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1414              pipe_name(pipe));
1415 }
1416
1417 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1418                             enum pipe pipe, u32 port_sel, u32 val)
1419 {
1420         if ((val & DP_PORT_EN) == 0)
1421                 return false;
1422
1423         if (HAS_PCH_CPT(dev_priv)) {
1424                 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1425                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1426                         return false;
1427         } else if (IS_CHERRYVIEW(dev_priv)) {
1428                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1429                         return false;
1430         } else {
1431                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1432                         return false;
1433         }
1434         return true;
1435 }
1436
1437 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1438                               enum pipe pipe, u32 val)
1439 {
1440         if ((val & SDVO_ENABLE) == 0)
1441                 return false;
1442
1443         if (HAS_PCH_CPT(dev_priv)) {
1444                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1445                         return false;
1446         } else if (IS_CHERRYVIEW(dev_priv)) {
1447                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1448                         return false;
1449         } else {
1450                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1451                         return false;
1452         }
1453         return true;
1454 }
1455
1456 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1457                               enum pipe pipe, u32 val)
1458 {
1459         if ((val & LVDS_PORT_EN) == 0)
1460                 return false;
1461
1462         if (HAS_PCH_CPT(dev_priv)) {
1463                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1464                         return false;
1465         } else {
1466                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1467                         return false;
1468         }
1469         return true;
1470 }
1471
1472 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1473                               enum pipe pipe, u32 val)
1474 {
1475         if ((val & ADPA_DAC_ENABLE) == 0)
1476                 return false;
1477         if (HAS_PCH_CPT(dev_priv)) {
1478                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1479                         return false;
1480         } else {
1481                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1482                         return false;
1483         }
1484         return true;
1485 }
1486
1487 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1488                                    enum pipe pipe, i915_reg_t reg,
1489                                    u32 port_sel)
1490 {
1491         u32 val = I915_READ(reg);
1492         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1493              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1494              i915_mmio_reg_offset(reg), pipe_name(pipe));
1495
1496         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
1497              && (val & DP_PIPEB_SELECT),
1498              "IBX PCH dp port still using transcoder B\n");
1499 }
1500
1501 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1502                                      enum pipe pipe, i915_reg_t reg)
1503 {
1504         u32 val = I915_READ(reg);
1505         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1506              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1507              i915_mmio_reg_offset(reg), pipe_name(pipe));
1508
1509         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
1510              && (val & SDVO_PIPE_B_SELECT),
1511              "IBX PCH hdmi port still using transcoder B\n");
1512 }
1513
1514 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1515                                       enum pipe pipe)
1516 {
1517         u32 val;
1518
1519         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1520         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1521         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1522
1523         val = I915_READ(PCH_ADPA);
1524         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1525              "PCH VGA enabled on transcoder %c, should be disabled\n",
1526              pipe_name(pipe));
1527
1528         val = I915_READ(PCH_LVDS);
1529         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1530              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1531              pipe_name(pipe));
1532
1533         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1534         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1535         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1536 }
1537
1538 static void _vlv_enable_pll(struct intel_crtc *crtc,
1539                             const struct intel_crtc_state *pipe_config)
1540 {
1541         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1542         enum pipe pipe = crtc->pipe;
1543
1544         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1545         POSTING_READ(DPLL(pipe));
1546         udelay(150);
1547
1548         if (intel_wait_for_register(dev_priv,
1549                                     DPLL(pipe),
1550                                     DPLL_LOCK_VLV,
1551                                     DPLL_LOCK_VLV,
1552                                     1))
1553                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1554 }
1555
1556 static void vlv_enable_pll(struct intel_crtc *crtc,
1557                            const struct intel_crtc_state *pipe_config)
1558 {
1559         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1560         enum pipe pipe = crtc->pipe;
1561
1562         assert_pipe_disabled(dev_priv, pipe);
1563
1564         /* PLL is protected by panel, make sure we can write it */
1565         assert_panel_unlocked(dev_priv, pipe);
1566
1567         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1568                 _vlv_enable_pll(crtc, pipe_config);
1569
1570         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1571         POSTING_READ(DPLL_MD(pipe));
1572 }
1573
1574
1575 static void _chv_enable_pll(struct intel_crtc *crtc,
1576                             const struct intel_crtc_state *pipe_config)
1577 {
1578         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1579         enum pipe pipe = crtc->pipe;
1580         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1581         u32 tmp;
1582
1583         mutex_lock(&dev_priv->sb_lock);
1584
1585         /* Enable back the 10bit clock to display controller */
1586         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1587         tmp |= DPIO_DCLKP_EN;
1588         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1589
1590         mutex_unlock(&dev_priv->sb_lock);
1591
1592         /*
1593          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1594          */
1595         udelay(1);
1596
1597         /* Enable PLL */
1598         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1599
1600         /* Check PLL is locked */
1601         if (intel_wait_for_register(dev_priv,
1602                                     DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV,
1603                                     1))
1604                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1605 }
1606
1607 static void chv_enable_pll(struct intel_crtc *crtc,
1608                            const struct intel_crtc_state *pipe_config)
1609 {
1610         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1611         enum pipe pipe = crtc->pipe;
1612
1613         assert_pipe_disabled(dev_priv, pipe);
1614
1615         /* PLL is protected by panel, make sure we can write it */
1616         assert_panel_unlocked(dev_priv, pipe);
1617
1618         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1619                 _chv_enable_pll(crtc, pipe_config);
1620
1621         if (pipe != PIPE_A) {
1622                 /*
1623                  * WaPixelRepeatModeFixForC0:chv
1624                  *
1625                  * DPLLCMD is AWOL. Use chicken bits to propagate
1626                  * the value from DPLLBMD to either pipe B or C.
1627                  */
1628                 I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C);
1629                 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1630                 I915_WRITE(CBR4_VLV, 0);
1631                 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1632
1633                 /*
1634                  * DPLLB VGA mode also seems to cause problems.
1635                  * We should always have it disabled.
1636                  */
1637                 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1638         } else {
1639                 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1640                 POSTING_READ(DPLL_MD(pipe));
1641         }
1642 }
1643
1644 static int intel_num_dvo_pipes(struct drm_device *dev)
1645 {
1646         struct intel_crtc *crtc;
1647         int count = 0;
1648
1649         for_each_intel_crtc(dev, crtc)
1650                 count += crtc->base.state->active &&
1651                         intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1652
1653         return count;
1654 }
1655
1656 static void i9xx_enable_pll(struct intel_crtc *crtc)
1657 {
1658         struct drm_device *dev = crtc->base.dev;
1659         struct drm_i915_private *dev_priv = dev->dev_private;
1660         i915_reg_t reg = DPLL(crtc->pipe);
1661         u32 dpll = crtc->config->dpll_hw_state.dpll;
1662
1663         assert_pipe_disabled(dev_priv, crtc->pipe);
1664
1665         /* PLL is protected by panel, make sure we can write it */
1666         if (IS_MOBILE(dev) && !IS_I830(dev))
1667                 assert_panel_unlocked(dev_priv, crtc->pipe);
1668
1669         /* Enable DVO 2x clock on both PLLs if necessary */
1670         if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1671                 /*
1672                  * It appears to be important that we don't enable this
1673                  * for the current pipe before otherwise configuring the
1674                  * PLL. No idea how this should be handled if multiple
1675                  * DVO outputs are enabled simultaneosly.
1676                  */
1677                 dpll |= DPLL_DVO_2X_MODE;
1678                 I915_WRITE(DPLL(!crtc->pipe),
1679                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1680         }
1681
1682         /*
1683          * Apparently we need to have VGA mode enabled prior to changing
1684          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1685          * dividers, even though the register value does change.
1686          */
1687         I915_WRITE(reg, 0);
1688
1689         I915_WRITE(reg, dpll);
1690
1691         /* Wait for the clocks to stabilize. */
1692         POSTING_READ(reg);
1693         udelay(150);
1694
1695         if (INTEL_INFO(dev)->gen >= 4) {
1696                 I915_WRITE(DPLL_MD(crtc->pipe),
1697                            crtc->config->dpll_hw_state.dpll_md);
1698         } else {
1699                 /* The pixel multiplier can only be updated once the
1700                  * DPLL is enabled and the clocks are stable.
1701                  *
1702                  * So write it again.
1703                  */
1704                 I915_WRITE(reg, dpll);
1705         }
1706
1707         /* We do this three times for luck */
1708         I915_WRITE(reg, dpll);
1709         POSTING_READ(reg);
1710         udelay(150); /* wait for warmup */
1711         I915_WRITE(reg, dpll);
1712         POSTING_READ(reg);
1713         udelay(150); /* wait for warmup */
1714         I915_WRITE(reg, dpll);
1715         POSTING_READ(reg);
1716         udelay(150); /* wait for warmup */
1717 }
1718
1719 /**
1720  * i9xx_disable_pll - disable a PLL
1721  * @dev_priv: i915 private structure
1722  * @pipe: pipe PLL to disable
1723  *
1724  * Disable the PLL for @pipe, making sure the pipe is off first.
1725  *
1726  * Note!  This is for pre-ILK only.
1727  */
1728 static void i9xx_disable_pll(struct intel_crtc *crtc)
1729 {
1730         struct drm_device *dev = crtc->base.dev;
1731         struct drm_i915_private *dev_priv = dev->dev_private;
1732         enum pipe pipe = crtc->pipe;
1733
1734         /* Disable DVO 2x clock on both PLLs if necessary */
1735         if (IS_I830(dev) &&
1736             intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1737             !intel_num_dvo_pipes(dev)) {
1738                 I915_WRITE(DPLL(PIPE_B),
1739                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1740                 I915_WRITE(DPLL(PIPE_A),
1741                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1742         }
1743
1744         /* Don't disable pipe or pipe PLLs if needed */
1745         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1746             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1747                 return;
1748
1749         /* Make sure the pipe isn't still relying on us */
1750         assert_pipe_disabled(dev_priv, pipe);
1751
1752         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1753         POSTING_READ(DPLL(pipe));
1754 }
1755
1756 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1757 {
1758         u32 val;
1759
1760         /* Make sure the pipe isn't still relying on us */
1761         assert_pipe_disabled(dev_priv, pipe);
1762
1763         val = DPLL_INTEGRATED_REF_CLK_VLV |
1764                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1765         if (pipe != PIPE_A)
1766                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1767
1768         I915_WRITE(DPLL(pipe), val);
1769         POSTING_READ(DPLL(pipe));
1770 }
1771
1772 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1773 {
1774         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1775         u32 val;
1776
1777         /* Make sure the pipe isn't still relying on us */
1778         assert_pipe_disabled(dev_priv, pipe);
1779
1780         val = DPLL_SSC_REF_CLK_CHV |
1781                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1782         if (pipe != PIPE_A)
1783                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1784
1785         I915_WRITE(DPLL(pipe), val);
1786         POSTING_READ(DPLL(pipe));
1787
1788         mutex_lock(&dev_priv->sb_lock);
1789
1790         /* Disable 10bit clock to display controller */
1791         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1792         val &= ~DPIO_DCLKP_EN;
1793         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1794
1795         mutex_unlock(&dev_priv->sb_lock);
1796 }
1797
1798 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1799                          struct intel_digital_port *dport,
1800                          unsigned int expected_mask)
1801 {
1802         u32 port_mask;
1803         i915_reg_t dpll_reg;
1804
1805         switch (dport->port) {
1806         case PORT_B:
1807                 port_mask = DPLL_PORTB_READY_MASK;
1808                 dpll_reg = DPLL(0);
1809                 break;
1810         case PORT_C:
1811                 port_mask = DPLL_PORTC_READY_MASK;
1812                 dpll_reg = DPLL(0);
1813                 expected_mask <<= 4;
1814                 break;
1815         case PORT_D:
1816                 port_mask = DPLL_PORTD_READY_MASK;
1817                 dpll_reg = DPIO_PHY_STATUS;
1818                 break;
1819         default:
1820                 BUG();
1821         }
1822
1823         if (intel_wait_for_register(dev_priv,
1824                                     dpll_reg, port_mask, expected_mask,
1825                                     1000))
1826                 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1827                      port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1828 }
1829
1830 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1831                                            enum pipe pipe)
1832 {
1833         struct drm_device *dev = dev_priv->dev;
1834         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1835         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1836         i915_reg_t reg;
1837         uint32_t val, pipeconf_val;
1838
1839         /* Make sure PCH DPLL is enabled */
1840         assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1841
1842         /* FDI must be feeding us bits for PCH ports */
1843         assert_fdi_tx_enabled(dev_priv, pipe);
1844         assert_fdi_rx_enabled(dev_priv, pipe);
1845
1846         if (HAS_PCH_CPT(dev)) {
1847                 /* Workaround: Set the timing override bit before enabling the
1848                  * pch transcoder. */
1849                 reg = TRANS_CHICKEN2(pipe);
1850                 val = I915_READ(reg);
1851                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1852                 I915_WRITE(reg, val);
1853         }
1854
1855         reg = PCH_TRANSCONF(pipe);
1856         val = I915_READ(reg);
1857         pipeconf_val = I915_READ(PIPECONF(pipe));
1858
1859         if (HAS_PCH_IBX(dev_priv)) {
1860                 /*
1861                  * Make the BPC in transcoder be consistent with
1862                  * that in pipeconf reg. For HDMI we must use 8bpc
1863                  * here for both 8bpc and 12bpc.
1864                  */
1865                 val &= ~PIPECONF_BPC_MASK;
1866                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
1867                         val |= PIPECONF_8BPC;
1868                 else
1869                         val |= pipeconf_val & PIPECONF_BPC_MASK;
1870         }
1871
1872         val &= ~TRANS_INTERLACE_MASK;
1873         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1874                 if (HAS_PCH_IBX(dev_priv) &&
1875                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1876                         val |= TRANS_LEGACY_INTERLACED_ILK;
1877                 else
1878                         val |= TRANS_INTERLACED;
1879         else
1880                 val |= TRANS_PROGRESSIVE;
1881
1882         I915_WRITE(reg, val | TRANS_ENABLE);
1883         if (intel_wait_for_register(dev_priv,
1884                                     reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE,
1885                                     100))
1886                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1887 }
1888
1889 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1890                                       enum transcoder cpu_transcoder)
1891 {
1892         u32 val, pipeconf_val;
1893
1894         /* FDI must be feeding us bits for PCH ports */
1895         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1896         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1897
1898         /* Workaround: set timing override bit. */
1899         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1900         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1901         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1902
1903         val = TRANS_ENABLE;
1904         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1905
1906         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1907             PIPECONF_INTERLACED_ILK)
1908                 val |= TRANS_INTERLACED;
1909         else
1910                 val |= TRANS_PROGRESSIVE;
1911
1912         I915_WRITE(LPT_TRANSCONF, val);
1913         if (intel_wait_for_register(dev_priv,
1914                                     LPT_TRANSCONF,
1915                                     TRANS_STATE_ENABLE,
1916                                     TRANS_STATE_ENABLE,
1917                                     100))
1918                 DRM_ERROR("Failed to enable PCH transcoder\n");
1919 }
1920
1921 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1922                                             enum pipe pipe)
1923 {
1924         struct drm_device *dev = dev_priv->dev;
1925         i915_reg_t reg;
1926         uint32_t val;
1927
1928         /* FDI relies on the transcoder */
1929         assert_fdi_tx_disabled(dev_priv, pipe);
1930         assert_fdi_rx_disabled(dev_priv, pipe);
1931
1932         /* Ports must be off as well */
1933         assert_pch_ports_disabled(dev_priv, pipe);
1934
1935         reg = PCH_TRANSCONF(pipe);
1936         val = I915_READ(reg);
1937         val &= ~TRANS_ENABLE;
1938         I915_WRITE(reg, val);
1939         /* wait for PCH transcoder off, transcoder state */
1940         if (intel_wait_for_register(dev_priv,
1941                                     reg, TRANS_STATE_ENABLE, 0,
1942                                     50))
1943                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1944
1945         if (HAS_PCH_CPT(dev)) {
1946                 /* Workaround: Clear the timing override chicken bit again. */
1947                 reg = TRANS_CHICKEN2(pipe);
1948                 val = I915_READ(reg);
1949                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1950                 I915_WRITE(reg, val);
1951         }
1952 }
1953
1954 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1955 {
1956         u32 val;
1957
1958         val = I915_READ(LPT_TRANSCONF);
1959         val &= ~TRANS_ENABLE;
1960         I915_WRITE(LPT_TRANSCONF, val);
1961         /* wait for PCH transcoder off, transcoder state */
1962         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1963                 DRM_ERROR("Failed to disable PCH transcoder\n");
1964
1965         /* Workaround: clear timing override bit. */
1966         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1967         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1968         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1969 }
1970
1971 /**
1972  * intel_enable_pipe - enable a pipe, asserting requirements
1973  * @crtc: crtc responsible for the pipe
1974  *
1975  * Enable @crtc's pipe, making sure that various hardware specific requirements
1976  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1977  */
1978 static void intel_enable_pipe(struct intel_crtc *crtc)
1979 {
1980         struct drm_device *dev = crtc->base.dev;
1981         struct drm_i915_private *dev_priv = dev->dev_private;
1982         enum pipe pipe = crtc->pipe;
1983         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1984         enum pipe pch_transcoder;
1985         i915_reg_t reg;
1986         u32 val;
1987
1988         DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1989
1990         assert_planes_disabled(dev_priv, pipe);
1991         assert_cursor_disabled(dev_priv, pipe);
1992         assert_sprites_disabled(dev_priv, pipe);
1993
1994         if (HAS_PCH_LPT(dev_priv))
1995                 pch_transcoder = TRANSCODER_A;
1996         else
1997                 pch_transcoder = pipe;
1998
1999         /*
2000          * A pipe without a PLL won't actually be able to drive bits from
2001          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
2002          * need the check.
2003          */
2004         if (HAS_GMCH_DISPLAY(dev_priv))
2005                 if (crtc->config->has_dsi_encoder)
2006                         assert_dsi_pll_enabled(dev_priv);
2007                 else
2008                         assert_pll_enabled(dev_priv, pipe);
2009         else {
2010                 if (crtc->config->has_pch_encoder) {
2011                         /* if driving the PCH, we need FDI enabled */
2012                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2013                         assert_fdi_tx_pll_enabled(dev_priv,
2014                                                   (enum pipe) cpu_transcoder);
2015                 }
2016                 /* FIXME: assert CPU port conditions for SNB+ */
2017         }
2018
2019         reg = PIPECONF(cpu_transcoder);
2020         val = I915_READ(reg);
2021         if (val & PIPECONF_ENABLE) {
2022                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2023                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2024                 return;
2025         }
2026
2027         I915_WRITE(reg, val | PIPECONF_ENABLE);
2028         POSTING_READ(reg);
2029
2030         /*
2031          * Until the pipe starts DSL will read as 0, which would cause
2032          * an apparent vblank timestamp jump, which messes up also the
2033          * frame count when it's derived from the timestamps. So let's
2034          * wait for the pipe to start properly before we call
2035          * drm_crtc_vblank_on()
2036          */
2037         if (dev->max_vblank_count == 0 &&
2038             wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
2039                 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
2040 }
2041
2042 /**
2043  * intel_disable_pipe - disable a pipe, asserting requirements
2044  * @crtc: crtc whose pipes is to be disabled
2045  *
2046  * Disable the pipe of @crtc, making sure that various hardware
2047  * specific requirements are met, if applicable, e.g. plane
2048  * disabled, panel fitter off, etc.
2049  *
2050  * Will wait until the pipe has shut down before returning.
2051  */
2052 static void intel_disable_pipe(struct intel_crtc *crtc)
2053 {
2054         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2055         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2056         enum pipe pipe = crtc->pipe;
2057         i915_reg_t reg;
2058         u32 val;
2059
2060         DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2061
2062         /*
2063          * Make sure planes won't keep trying to pump pixels to us,
2064          * or we might hang the display.
2065          */
2066         assert_planes_disabled(dev_priv, pipe);
2067         assert_cursor_disabled(dev_priv, pipe);
2068         assert_sprites_disabled(dev_priv, pipe);
2069
2070         reg = PIPECONF(cpu_transcoder);
2071         val = I915_READ(reg);
2072         if ((val & PIPECONF_ENABLE) == 0)
2073                 return;
2074
2075         /*
2076          * Double wide has implications for planes
2077          * so best keep it disabled when not needed.
2078          */
2079         if (crtc->config->double_wide)
2080                 val &= ~PIPECONF_DOUBLE_WIDE;
2081
2082         /* Don't disable pipe or pipe PLLs if needed */
2083         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2084             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2085                 val &= ~PIPECONF_ENABLE;
2086
2087         I915_WRITE(reg, val);
2088         if ((val & PIPECONF_ENABLE) == 0)
2089                 intel_wait_for_pipe_off(crtc);
2090 }
2091
2092 static bool need_vtd_wa(struct drm_device *dev)
2093 {
2094 #ifdef CONFIG_INTEL_IOMMU
2095         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2096                 return true;
2097 #endif
2098         return false;
2099 }
2100
2101 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
2102 {
2103         return IS_GEN2(dev_priv) ? 2048 : 4096;
2104 }
2105
2106 static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv,
2107                                            uint64_t fb_modifier, unsigned int cpp)
2108 {
2109         switch (fb_modifier) {
2110         case DRM_FORMAT_MOD_NONE:
2111                 return cpp;
2112         case I915_FORMAT_MOD_X_TILED:
2113                 if (IS_GEN2(dev_priv))
2114                         return 128;
2115                 else
2116                         return 512;
2117         case I915_FORMAT_MOD_Y_TILED:
2118                 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2119                         return 128;
2120                 else
2121                         return 512;
2122         case I915_FORMAT_MOD_Yf_TILED:
2123                 switch (cpp) {
2124                 case 1:
2125                         return 64;
2126                 case 2:
2127                 case 4:
2128                         return 128;
2129                 case 8:
2130                 case 16:
2131                         return 256;
2132                 default:
2133                         MISSING_CASE(cpp);
2134                         return cpp;
2135                 }
2136                 break;
2137         default:
2138                 MISSING_CASE(fb_modifier);
2139                 return cpp;
2140         }
2141 }
2142
2143 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
2144                                uint64_t fb_modifier, unsigned int cpp)
2145 {
2146         if (fb_modifier == DRM_FORMAT_MOD_NONE)
2147                 return 1;
2148         else
2149                 return intel_tile_size(dev_priv) /
2150                         intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2151 }
2152
2153 /* Return the tile dimensions in pixel units */
2154 static void intel_tile_dims(const struct drm_i915_private *dev_priv,
2155                             unsigned int *tile_width,
2156                             unsigned int *tile_height,
2157                             uint64_t fb_modifier,
2158                             unsigned int cpp)
2159 {
2160         unsigned int tile_width_bytes =
2161                 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2162
2163         *tile_width = tile_width_bytes / cpp;
2164         *tile_height = intel_tile_size(dev_priv) / tile_width_bytes;
2165 }
2166
2167 unsigned int
2168 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2169                       uint32_t pixel_format, uint64_t fb_modifier)
2170 {
2171         unsigned int cpp = drm_format_plane_cpp(pixel_format, 0);
2172         unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp);
2173
2174         return ALIGN(height, tile_height);
2175 }
2176
2177 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2178 {
2179         unsigned int size = 0;
2180         int i;
2181
2182         for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2183                 size += rot_info->plane[i].width * rot_info->plane[i].height;
2184
2185         return size;
2186 }
2187
2188 static void
2189 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2190                         const struct drm_framebuffer *fb,
2191                         unsigned int rotation)
2192 {
2193         if (intel_rotation_90_or_270(rotation)) {
2194                 *view = i915_ggtt_view_rotated;
2195                 view->params.rotated = to_intel_framebuffer(fb)->rot_info;
2196         } else {
2197                 *view = i915_ggtt_view_normal;
2198         }
2199 }
2200
2201 static void
2202 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2203                    struct drm_framebuffer *fb)
2204 {
2205         struct intel_rotation_info *info = &to_intel_framebuffer(fb)->rot_info;
2206         unsigned int tile_size, tile_width, tile_height, cpp;
2207
2208         tile_size = intel_tile_size(dev_priv);
2209
2210         cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2211         intel_tile_dims(dev_priv, &tile_width, &tile_height,
2212                         fb->modifier[0], cpp);
2213
2214         info->plane[0].width = DIV_ROUND_UP(fb->pitches[0], tile_width * cpp);
2215         info->plane[0].height = DIV_ROUND_UP(fb->height, tile_height);
2216
2217         if (info->pixel_format == DRM_FORMAT_NV12) {
2218                 cpp = drm_format_plane_cpp(fb->pixel_format, 1);
2219                 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2220                                 fb->modifier[1], cpp);
2221
2222                 info->uv_offset = fb->offsets[1];
2223                 info->plane[1].width = DIV_ROUND_UP(fb->pitches[1], tile_width * cpp);
2224                 info->plane[1].height = DIV_ROUND_UP(fb->height / 2, tile_height);
2225         }
2226 }
2227
2228 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2229 {
2230         if (INTEL_INFO(dev_priv)->gen >= 9)
2231                 return 256 * 1024;
2232         else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2233                  IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2234                 return 128 * 1024;
2235         else if (INTEL_INFO(dev_priv)->gen >= 4)
2236                 return 4 * 1024;
2237         else
2238                 return 0;
2239 }
2240
2241 static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv,
2242                                          uint64_t fb_modifier)
2243 {
2244         switch (fb_modifier) {
2245         case DRM_FORMAT_MOD_NONE:
2246                 return intel_linear_alignment(dev_priv);
2247         case I915_FORMAT_MOD_X_TILED:
2248                 if (INTEL_INFO(dev_priv)->gen >= 9)
2249                         return 256 * 1024;
2250                 return 0;
2251         case I915_FORMAT_MOD_Y_TILED:
2252         case I915_FORMAT_MOD_Yf_TILED:
2253                 return 1 * 1024 * 1024;
2254         default:
2255                 MISSING_CASE(fb_modifier);
2256                 return 0;
2257         }
2258 }
2259
2260 int
2261 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
2262                            unsigned int rotation)
2263 {
2264         struct drm_device *dev = fb->dev;
2265         struct drm_i915_private *dev_priv = dev->dev_private;
2266         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2267         struct i915_ggtt_view view;
2268         u32 alignment;
2269         int ret;
2270
2271         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2272
2273         alignment = intel_surf_alignment(dev_priv, fb->modifier[0]);
2274
2275         intel_fill_fb_ggtt_view(&view, fb, rotation);
2276
2277         /* Note that the w/a also requires 64 PTE of padding following the
2278          * bo. We currently fill all unused PTE with the shadow page and so
2279          * we should always have valid PTE following the scanout preventing
2280          * the VT-d warning.
2281          */
2282         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2283                 alignment = 256 * 1024;
2284
2285         /*
2286          * Global gtt pte registers are special registers which actually forward
2287          * writes to a chunk of system memory. Which means that there is no risk
2288          * that the register values disappear as soon as we call
2289          * intel_runtime_pm_put(), so it is correct to wrap only the
2290          * pin/unpin/fence and not more.
2291          */
2292         intel_runtime_pm_get(dev_priv);
2293
2294         ret = i915_gem_object_pin_to_display_plane(obj, alignment,
2295                                                    &view);
2296         if (ret)
2297                 goto err_pm;
2298
2299         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2300          * fence, whereas 965+ only requires a fence if using
2301          * framebuffer compression.  For simplicity, we always install
2302          * a fence as the cost is not that onerous.
2303          */
2304         if (view.type == I915_GGTT_VIEW_NORMAL) {
2305                 ret = i915_gem_object_get_fence(obj);
2306                 if (ret == -EDEADLK) {
2307                         /*
2308                          * -EDEADLK means there are no free fences
2309                          * no pending flips.
2310                          *
2311                          * This is propagated to atomic, but it uses
2312                          * -EDEADLK to force a locking recovery, so
2313                          * change the returned error to -EBUSY.
2314                          */
2315                         ret = -EBUSY;
2316                         goto err_unpin;
2317                 } else if (ret)
2318                         goto err_unpin;
2319
2320                 i915_gem_object_pin_fence(obj);
2321         }
2322
2323         intel_runtime_pm_put(dev_priv);
2324         return 0;
2325
2326 err_unpin:
2327         i915_gem_object_unpin_from_display_plane(obj, &view);
2328 err_pm:
2329         intel_runtime_pm_put(dev_priv);
2330         return ret;
2331 }
2332
2333 void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2334 {
2335         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2336         struct i915_ggtt_view view;
2337
2338         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2339
2340         intel_fill_fb_ggtt_view(&view, fb, rotation);
2341
2342         if (view.type == I915_GGTT_VIEW_NORMAL)
2343                 i915_gem_object_unpin_fence(obj);
2344
2345         i915_gem_object_unpin_from_display_plane(obj, &view);
2346 }
2347
2348 /*
2349  * Adjust the tile offset by moving the difference into
2350  * the x/y offsets.
2351  *
2352  * Input tile dimensions and pitch must already be
2353  * rotated to match x and y, and in pixel units.
2354  */
2355 static u32 intel_adjust_tile_offset(int *x, int *y,
2356                                     unsigned int tile_width,
2357                                     unsigned int tile_height,
2358                                     unsigned int tile_size,
2359                                     unsigned int pitch_tiles,
2360                                     u32 old_offset,
2361                                     u32 new_offset)
2362 {
2363         unsigned int tiles;
2364
2365         WARN_ON(old_offset & (tile_size - 1));
2366         WARN_ON(new_offset & (tile_size - 1));
2367         WARN_ON(new_offset > old_offset);
2368
2369         tiles = (old_offset - new_offset) / tile_size;
2370
2371         *y += tiles / pitch_tiles * tile_height;
2372         *x += tiles % pitch_tiles * tile_width;
2373
2374         return new_offset;
2375 }
2376
2377 /*
2378  * Computes the linear offset to the base tile and adjusts
2379  * x, y. bytes per pixel is assumed to be a power-of-two.
2380  *
2381  * In the 90/270 rotated case, x and y are assumed
2382  * to be already rotated to match the rotated GTT view, and
2383  * pitch is the tile_height aligned framebuffer height.
2384  */
2385 u32 intel_compute_tile_offset(int *x, int *y,
2386                               const struct drm_framebuffer *fb, int plane,
2387                               unsigned int pitch,
2388                               unsigned int rotation)
2389 {
2390         const struct drm_i915_private *dev_priv = to_i915(fb->dev);
2391         uint64_t fb_modifier = fb->modifier[plane];
2392         unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2393         u32 offset, offset_aligned, alignment;
2394
2395         alignment = intel_surf_alignment(dev_priv, fb_modifier);
2396         if (alignment)
2397                 alignment--;
2398
2399         if (fb_modifier != DRM_FORMAT_MOD_NONE) {
2400                 unsigned int tile_size, tile_width, tile_height;
2401                 unsigned int tile_rows, tiles, pitch_tiles;
2402
2403                 tile_size = intel_tile_size(dev_priv);
2404                 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2405                                 fb_modifier, cpp);
2406
2407                 if (intel_rotation_90_or_270(rotation)) {
2408                         pitch_tiles = pitch / tile_height;
2409                         swap(tile_width, tile_height);
2410                 } else {
2411                         pitch_tiles = pitch / (tile_width * cpp);
2412                 }
2413
2414                 tile_rows = *y / tile_height;
2415                 *y %= tile_height;
2416
2417                 tiles = *x / tile_width;
2418                 *x %= tile_width;
2419
2420                 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2421                 offset_aligned = offset & ~alignment;
2422
2423                 intel_adjust_tile_offset(x, y, tile_width, tile_height,
2424                                          tile_size, pitch_tiles,
2425                                          offset, offset_aligned);
2426         } else {
2427                 offset = *y * pitch + *x * cpp;
2428                 offset_aligned = offset & ~alignment;
2429
2430                 *y = (offset & alignment) / pitch;
2431                 *x = ((offset & alignment) - *y * pitch) / cpp;
2432         }
2433
2434         return offset_aligned;
2435 }
2436
2437 static int i9xx_format_to_fourcc(int format)
2438 {
2439         switch (format) {
2440         case DISPPLANE_8BPP:
2441                 return DRM_FORMAT_C8;
2442         case DISPPLANE_BGRX555:
2443                 return DRM_FORMAT_XRGB1555;
2444         case DISPPLANE_BGRX565:
2445                 return DRM_FORMAT_RGB565;
2446         default:
2447         case DISPPLANE_BGRX888:
2448                 return DRM_FORMAT_XRGB8888;
2449         case DISPPLANE_RGBX888:
2450                 return DRM_FORMAT_XBGR8888;
2451         case DISPPLANE_BGRX101010:
2452                 return DRM_FORMAT_XRGB2101010;
2453         case DISPPLANE_RGBX101010:
2454                 return DRM_FORMAT_XBGR2101010;
2455         }
2456 }
2457
2458 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2459 {
2460         switch (format) {
2461         case PLANE_CTL_FORMAT_RGB_565:
2462                 return DRM_FORMAT_RGB565;
2463         default:
2464         case PLANE_CTL_FORMAT_XRGB_8888:
2465                 if (rgb_order) {
2466                         if (alpha)
2467                                 return DRM_FORMAT_ABGR8888;
2468                         else
2469                                 return DRM_FORMAT_XBGR8888;
2470                 } else {
2471                         if (alpha)
2472                                 return DRM_FORMAT_ARGB8888;
2473                         else
2474                                 return DRM_FORMAT_XRGB8888;
2475                 }
2476         case PLANE_CTL_FORMAT_XRGB_2101010:
2477                 if (rgb_order)
2478                         return DRM_FORMAT_XBGR2101010;
2479                 else
2480                         return DRM_FORMAT_XRGB2101010;
2481         }
2482 }
2483
2484 static bool
2485 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2486                               struct intel_initial_plane_config *plane_config)
2487 {
2488         struct drm_device *dev = crtc->base.dev;
2489         struct drm_i915_private *dev_priv = to_i915(dev);
2490         struct i915_ggtt *ggtt = &dev_priv->ggtt;
2491         struct drm_i915_gem_object *obj = NULL;
2492         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2493         struct drm_framebuffer *fb = &plane_config->fb->base;
2494         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2495         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2496                                     PAGE_SIZE);
2497
2498         size_aligned -= base_aligned;
2499
2500         if (plane_config->size == 0)
2501                 return false;
2502
2503         /* If the FB is too big, just don't use it since fbdev is not very
2504          * important and we should probably use that space with FBC or other
2505          * features. */
2506         if (size_aligned * 2 > ggtt->stolen_usable_size)
2507                 return false;
2508
2509         mutex_lock(&dev->struct_mutex);
2510
2511         obj = i915_gem_object_create_stolen_for_preallocated(dev,
2512                                                              base_aligned,
2513                                                              base_aligned,
2514                                                              size_aligned);
2515         if (!obj) {
2516                 mutex_unlock(&dev->struct_mutex);
2517                 return false;
2518         }
2519
2520         obj->tiling_mode = plane_config->tiling;
2521         if (obj->tiling_mode == I915_TILING_X)
2522                 obj->stride = fb->pitches[0];
2523
2524         mode_cmd.pixel_format = fb->pixel_format;
2525         mode_cmd.width = fb->width;
2526         mode_cmd.height = fb->height;
2527         mode_cmd.pitches[0] = fb->pitches[0];
2528         mode_cmd.modifier[0] = fb->modifier[0];
2529         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2530
2531         if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2532                                    &mode_cmd, obj)) {
2533                 DRM_DEBUG_KMS("intel fb init failed\n");
2534                 goto out_unref_obj;
2535         }
2536
2537         mutex_unlock(&dev->struct_mutex);
2538
2539         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2540         return true;
2541
2542 out_unref_obj:
2543         drm_gem_object_unreference(&obj->base);
2544         mutex_unlock(&dev->struct_mutex);
2545         return false;
2546 }
2547
2548 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2549 static void
2550 update_state_fb(struct drm_plane *plane)
2551 {
2552         if (plane->fb == plane->state->fb)
2553                 return;
2554
2555         if (plane->state->fb)
2556                 drm_framebuffer_unreference(plane->state->fb);
2557         plane->state->fb = plane->fb;
2558         if (plane->state->fb)
2559                 drm_framebuffer_reference(plane->state->fb);
2560 }
2561
2562 static void
2563 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2564                              struct intel_initial_plane_config *plane_config)
2565 {
2566         struct drm_device *dev = intel_crtc->base.dev;
2567         struct drm_i915_private *dev_priv = dev->dev_private;
2568         struct drm_crtc *c;
2569         struct intel_crtc *i;
2570         struct drm_i915_gem_object *obj;
2571         struct drm_plane *primary = intel_crtc->base.primary;
2572         struct drm_plane_state *plane_state = primary->state;
2573         struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2574         struct intel_plane *intel_plane = to_intel_plane(primary);
2575         struct intel_plane_state *intel_state =
2576                 to_intel_plane_state(plane_state);
2577         struct drm_framebuffer *fb;
2578
2579         if (!plane_config->fb)
2580                 return;
2581
2582         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2583                 fb = &plane_config->fb->base;
2584                 goto valid_fb;
2585         }
2586
2587         kfree(plane_config->fb);
2588
2589         /*
2590          * Failed to alloc the obj, check to see if we should share
2591          * an fb with another CRTC instead
2592          */
2593         for_each_crtc(dev, c) {
2594                 i = to_intel_crtc(c);
2595
2596                 if (c == &intel_crtc->base)
2597                         continue;
2598
2599                 if (!i->active)
2600                         continue;
2601
2602                 fb = c->primary->fb;
2603                 if (!fb)
2604                         continue;
2605
2606                 obj = intel_fb_obj(fb);
2607                 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2608                         drm_framebuffer_reference(fb);
2609                         goto valid_fb;
2610                 }
2611         }
2612
2613         /*
2614          * We've failed to reconstruct the BIOS FB.  Current display state
2615          * indicates that the primary plane is visible, but has a NULL FB,
2616          * which will lead to problems later if we don't fix it up.  The
2617          * simplest solution is to just disable the primary plane now and
2618          * pretend the BIOS never had it enabled.
2619          */
2620         to_intel_plane_state(plane_state)->visible = false;
2621         crtc_state->plane_mask &= ~(1 << drm_plane_index(primary));
2622         intel_pre_disable_primary_noatomic(&intel_crtc->base);
2623         intel_plane->disable_plane(primary, &intel_crtc->base);
2624
2625         return;
2626
2627 valid_fb:
2628         plane_state->src_x = 0;
2629         plane_state->src_y = 0;
2630         plane_state->src_w = fb->width << 16;
2631         plane_state->src_h = fb->height << 16;
2632
2633         plane_state->crtc_x = 0;
2634         plane_state->crtc_y = 0;
2635         plane_state->crtc_w = fb->width;
2636         plane_state->crtc_h = fb->height;
2637
2638         intel_state->src.x1 = plane_state->src_x;
2639         intel_state->src.y1 = plane_state->src_y;
2640         intel_state->src.x2 = plane_state->src_x + plane_state->src_w;
2641         intel_state->src.y2 = plane_state->src_y + plane_state->src_h;
2642         intel_state->dst.x1 = plane_state->crtc_x;
2643         intel_state->dst.y1 = plane_state->crtc_y;
2644         intel_state->dst.x2 = plane_state->crtc_x + plane_state->crtc_w;
2645         intel_state->dst.y2 = plane_state->crtc_y + plane_state->crtc_h;
2646
2647         obj = intel_fb_obj(fb);
2648         if (obj->tiling_mode != I915_TILING_NONE)
2649                 dev_priv->preserve_bios_swizzle = true;
2650
2651         drm_framebuffer_reference(fb);
2652         primary->fb = primary->state->fb = fb;
2653         primary->crtc = primary->state->crtc = &intel_crtc->base;
2654         intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2655         obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2656 }
2657
2658 static void i9xx_update_primary_plane(struct drm_plane *primary,
2659                                       const struct intel_crtc_state *crtc_state,
2660                                       const struct intel_plane_state *plane_state)
2661 {
2662         struct drm_device *dev = primary->dev;
2663         struct drm_i915_private *dev_priv = dev->dev_private;
2664         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2665         struct drm_framebuffer *fb = plane_state->base.fb;
2666         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2667         int plane = intel_crtc->plane;
2668         u32 linear_offset;
2669         u32 dspcntr;
2670         i915_reg_t reg = DSPCNTR(plane);
2671         unsigned int rotation = plane_state->base.rotation;
2672         int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2673         int x = plane_state->src.x1 >> 16;
2674         int y = plane_state->src.y1 >> 16;
2675
2676         dspcntr = DISPPLANE_GAMMA_ENABLE;
2677
2678         dspcntr |= DISPLAY_PLANE_ENABLE;
2679
2680         if (INTEL_INFO(dev)->gen < 4) {
2681                 if (intel_crtc->pipe == PIPE_B)
2682                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2683
2684                 /* pipesrc and dspsize control the size that is scaled from,
2685                  * which should always be the user's requested size.
2686                  */
2687                 I915_WRITE(DSPSIZE(plane),
2688                            ((crtc_state->pipe_src_h - 1) << 16) |
2689                            (crtc_state->pipe_src_w - 1));
2690                 I915_WRITE(DSPPOS(plane), 0);
2691         } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2692                 I915_WRITE(PRIMSIZE(plane),
2693                            ((crtc_state->pipe_src_h - 1) << 16) |
2694                            (crtc_state->pipe_src_w - 1));
2695                 I915_WRITE(PRIMPOS(plane), 0);
2696                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2697         }
2698
2699         switch (fb->pixel_format) {
2700         case DRM_FORMAT_C8:
2701                 dspcntr |= DISPPLANE_8BPP;
2702                 break;
2703         case DRM_FORMAT_XRGB1555:
2704                 dspcntr |= DISPPLANE_BGRX555;
2705                 break;
2706         case DRM_FORMAT_RGB565:
2707                 dspcntr |= DISPPLANE_BGRX565;
2708                 break;
2709         case DRM_FORMAT_XRGB8888:
2710                 dspcntr |= DISPPLANE_BGRX888;
2711                 break;
2712         case DRM_FORMAT_XBGR8888:
2713                 dspcntr |= DISPPLANE_RGBX888;
2714                 break;
2715         case DRM_FORMAT_XRGB2101010:
2716                 dspcntr |= DISPPLANE_BGRX101010;
2717                 break;
2718         case DRM_FORMAT_XBGR2101010:
2719                 dspcntr |= DISPPLANE_RGBX101010;
2720                 break;
2721         default:
2722                 BUG();
2723         }
2724
2725         if (INTEL_INFO(dev)->gen >= 4 &&
2726             obj->tiling_mode != I915_TILING_NONE)
2727                 dspcntr |= DISPPLANE_TILED;
2728
2729         if (IS_G4X(dev))
2730                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2731
2732         linear_offset = y * fb->pitches[0] + x * cpp;
2733
2734         if (INTEL_INFO(dev)->gen >= 4) {
2735                 intel_crtc->dspaddr_offset =
2736                         intel_compute_tile_offset(&x, &y, fb, 0,
2737                                                   fb->pitches[0], rotation);
2738                 linear_offset -= intel_crtc->dspaddr_offset;
2739         } else {
2740                 intel_crtc->dspaddr_offset = linear_offset;
2741         }
2742
2743         if (rotation == BIT(DRM_ROTATE_180)) {
2744                 dspcntr |= DISPPLANE_ROTATE_180;
2745
2746                 x += (crtc_state->pipe_src_w - 1);
2747                 y += (crtc_state->pipe_src_h - 1);
2748
2749                 /* Finding the last pixel of the last line of the display
2750                 data and adding to linear_offset*/
2751                 linear_offset +=
2752                         (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
2753                         (crtc_state->pipe_src_w - 1) * cpp;
2754         }
2755
2756         intel_crtc->adjusted_x = x;
2757         intel_crtc->adjusted_y = y;
2758
2759         I915_WRITE(reg, dspcntr);
2760
2761         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2762         if (INTEL_INFO(dev)->gen >= 4) {
2763                 I915_WRITE(DSPSURF(plane),
2764                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2765                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2766                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2767         } else
2768                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2769         POSTING_READ(reg);
2770 }
2771
2772 static void i9xx_disable_primary_plane(struct drm_plane *primary,
2773                                        struct drm_crtc *crtc)
2774 {
2775         struct drm_device *dev = crtc->dev;
2776         struct drm_i915_private *dev_priv = dev->dev_private;
2777         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2778         int plane = intel_crtc->plane;
2779
2780         I915_WRITE(DSPCNTR(plane), 0);
2781         if (INTEL_INFO(dev_priv)->gen >= 4)
2782                 I915_WRITE(DSPSURF(plane), 0);
2783         else
2784                 I915_WRITE(DSPADDR(plane), 0);
2785         POSTING_READ(DSPCNTR(plane));
2786 }
2787
2788 static void ironlake_update_primary_plane(struct drm_plane *primary,
2789                                           const struct intel_crtc_state *crtc_state,
2790                                           const struct intel_plane_state *plane_state)
2791 {
2792         struct drm_device *dev = primary->dev;
2793         struct drm_i915_private *dev_priv = dev->dev_private;
2794         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2795         struct drm_framebuffer *fb = plane_state->base.fb;
2796         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2797         int plane = intel_crtc->plane;
2798         u32 linear_offset;
2799         u32 dspcntr;
2800         i915_reg_t reg = DSPCNTR(plane);
2801         unsigned int rotation = plane_state->base.rotation;
2802         int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2803         int x = plane_state->src.x1 >> 16;
2804         int y = plane_state->src.y1 >> 16;
2805
2806         dspcntr = DISPPLANE_GAMMA_ENABLE;
2807         dspcntr |= DISPLAY_PLANE_ENABLE;
2808
2809         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2810                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2811
2812         switch (fb->pixel_format) {
2813         case DRM_FORMAT_C8:
2814                 dspcntr |= DISPPLANE_8BPP;
2815                 break;
2816         case DRM_FORMAT_RGB565:
2817                 dspcntr |= DISPPLANE_BGRX565;
2818                 break;
2819         case DRM_FORMAT_XRGB8888:
2820                 dspcntr |= DISPPLANE_BGRX888;
2821                 break;
2822         case DRM_FORMAT_XBGR8888:
2823                 dspcntr |= DISPPLANE_RGBX888;
2824                 break;
2825         case DRM_FORMAT_XRGB2101010:
2826                 dspcntr |= DISPPLANE_BGRX101010;
2827                 break;
2828         case DRM_FORMAT_XBGR2101010:
2829                 dspcntr |= DISPPLANE_RGBX101010;
2830                 break;
2831         default:
2832                 BUG();
2833         }
2834
2835         if (obj->tiling_mode != I915_TILING_NONE)
2836                 dspcntr |= DISPPLANE_TILED;
2837
2838         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2839                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2840
2841         linear_offset = y * fb->pitches[0] + x * cpp;
2842         intel_crtc->dspaddr_offset =
2843                 intel_compute_tile_offset(&x, &y, fb, 0,
2844                                           fb->pitches[0], rotation);
2845         linear_offset -= intel_crtc->dspaddr_offset;
2846         if (rotation == BIT(DRM_ROTATE_180)) {
2847                 dspcntr |= DISPPLANE_ROTATE_180;
2848
2849                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2850                         x += (crtc_state->pipe_src_w - 1);
2851                         y += (crtc_state->pipe_src_h - 1);
2852
2853                         /* Finding the last pixel of the last line of the display
2854                         data and adding to linear_offset*/
2855                         linear_offset +=
2856                                 (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
2857                                 (crtc_state->pipe_src_w - 1) * cpp;
2858                 }
2859         }
2860
2861         intel_crtc->adjusted_x = x;
2862         intel_crtc->adjusted_y = y;
2863
2864         I915_WRITE(reg, dspcntr);
2865
2866         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2867         I915_WRITE(DSPSURF(plane),
2868                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2869         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2870                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2871         } else {
2872                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2873                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2874         }
2875         POSTING_READ(reg);
2876 }
2877
2878 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
2879                               uint64_t fb_modifier, uint32_t pixel_format)
2880 {
2881         if (fb_modifier == DRM_FORMAT_MOD_NONE) {
2882                 return 64;
2883         } else {
2884                 int cpp = drm_format_plane_cpp(pixel_format, 0);
2885
2886                 return intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2887         }
2888 }
2889
2890 u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
2891                            struct drm_i915_gem_object *obj,
2892                            unsigned int plane)
2893 {
2894         struct i915_ggtt_view view;
2895         struct i915_vma *vma;
2896         u64 offset;
2897
2898         intel_fill_fb_ggtt_view(&view, intel_plane->base.state->fb,
2899                                 intel_plane->base.state->rotation);
2900
2901         vma = i915_gem_obj_to_ggtt_view(obj, &view);
2902         if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
2903                 view.type))
2904                 return -1;
2905
2906         offset = vma->node.start;
2907
2908         if (plane == 1) {
2909                 offset += vma->ggtt_view.params.rotated.uv_start_page *
2910                           PAGE_SIZE;
2911         }
2912
2913         WARN_ON(upper_32_bits(offset));
2914
2915         return lower_32_bits(offset);
2916 }
2917
2918 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2919 {
2920         struct drm_device *dev = intel_crtc->base.dev;
2921         struct drm_i915_private *dev_priv = dev->dev_private;
2922
2923         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2924         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2925         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
2926 }
2927
2928 /*
2929  * This function detaches (aka. unbinds) unused scalers in hardware
2930  */
2931 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2932 {
2933         struct intel_crtc_scaler_state *scaler_state;
2934         int i;
2935
2936         scaler_state = &intel_crtc->config->scaler_state;
2937
2938         /* loop through and disable scalers that aren't in use */
2939         for (i = 0; i < intel_crtc->num_scalers; i++) {
2940                 if (!scaler_state->scalers[i].in_use)
2941                         skl_detach_scaler(intel_crtc, i);
2942         }
2943 }
2944
2945 u32 skl_plane_ctl_format(uint32_t pixel_format)
2946 {
2947         switch (pixel_format) {
2948         case DRM_FORMAT_C8:
2949                 return PLANE_CTL_FORMAT_INDEXED;
2950         case DRM_FORMAT_RGB565:
2951                 return PLANE_CTL_FORMAT_RGB_565;
2952         case DRM_FORMAT_XBGR8888:
2953                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2954         case DRM_FORMAT_XRGB8888:
2955                 return PLANE_CTL_FORMAT_XRGB_8888;
2956         /*
2957          * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2958          * to be already pre-multiplied. We need to add a knob (or a different
2959          * DRM_FORMAT) for user-space to configure that.
2960          */
2961         case DRM_FORMAT_ABGR8888:
2962                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2963                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2964         case DRM_FORMAT_ARGB8888:
2965                 return PLANE_CTL_FORMAT_XRGB_8888 |
2966                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2967         case DRM_FORMAT_XRGB2101010:
2968                 return PLANE_CTL_FORMAT_XRGB_2101010;
2969         case DRM_FORMAT_XBGR2101010:
2970                 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
2971         case DRM_FORMAT_YUYV:
2972                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
2973         case DRM_FORMAT_YVYU:
2974                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
2975         case DRM_FORMAT_UYVY:
2976                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
2977         case DRM_FORMAT_VYUY:
2978                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
2979         default:
2980                 MISSING_CASE(pixel_format);
2981         }
2982
2983         return 0;
2984 }
2985
2986 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2987 {
2988         switch (fb_modifier) {
2989         case DRM_FORMAT_MOD_NONE:
2990                 break;
2991         case I915_FORMAT_MOD_X_TILED:
2992                 return PLANE_CTL_TILED_X;
2993         case I915_FORMAT_MOD_Y_TILED:
2994                 return PLANE_CTL_TILED_Y;
2995         case I915_FORMAT_MOD_Yf_TILED:
2996                 return PLANE_CTL_TILED_YF;
2997         default:
2998                 MISSING_CASE(fb_modifier);
2999         }
3000
3001         return 0;
3002 }
3003
3004 u32 skl_plane_ctl_rotation(unsigned int rotation)
3005 {
3006         switch (rotation) {
3007         case BIT(DRM_ROTATE_0):
3008                 break;
3009         /*
3010          * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3011          * while i915 HW rotation is clockwise, thats why this swapping.
3012          */
3013         case BIT(DRM_ROTATE_90):
3014                 return PLANE_CTL_ROTATE_270;
3015         case BIT(DRM_ROTATE_180):
3016                 return PLANE_CTL_ROTATE_180;
3017         case BIT(DRM_ROTATE_270):
3018                 return PLANE_CTL_ROTATE_90;
3019         default:
3020                 MISSING_CASE(rotation);
3021         }
3022
3023         return 0;
3024 }
3025
3026 static void skylake_update_primary_plane(struct drm_plane *plane,
3027                                          const struct intel_crtc_state *crtc_state,
3028                                          const struct intel_plane_state *plane_state)
3029 {
3030         struct drm_device *dev = plane->dev;
3031         struct drm_i915_private *dev_priv = dev->dev_private;
3032         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3033         struct drm_framebuffer *fb = plane_state->base.fb;
3034         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
3035         int pipe = intel_crtc->pipe;
3036         u32 plane_ctl, stride_div, stride;
3037         u32 tile_height, plane_offset, plane_size;
3038         unsigned int rotation = plane_state->base.rotation;
3039         int x_offset, y_offset;
3040         u32 surf_addr;
3041         int scaler_id = plane_state->scaler_id;
3042         int src_x = plane_state->src.x1 >> 16;
3043         int src_y = plane_state->src.y1 >> 16;
3044         int src_w = drm_rect_width(&plane_state->src) >> 16;
3045         int src_h = drm_rect_height(&plane_state->src) >> 16;
3046         int dst_x = plane_state->dst.x1;
3047         int dst_y = plane_state->dst.y1;
3048         int dst_w = drm_rect_width(&plane_state->dst);
3049         int dst_h = drm_rect_height(&plane_state->dst);
3050
3051         plane_ctl = PLANE_CTL_ENABLE |
3052                     PLANE_CTL_PIPE_GAMMA_ENABLE |
3053                     PLANE_CTL_PIPE_CSC_ENABLE;
3054
3055         plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3056         plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3057         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3058         plane_ctl |= skl_plane_ctl_rotation(rotation);
3059
3060         stride_div = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
3061                                                fb->pixel_format);
3062         surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
3063
3064         WARN_ON(drm_rect_width(&plane_state->src) == 0);
3065
3066         if (intel_rotation_90_or_270(rotation)) {
3067                 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
3068
3069                 /* stride = Surface height in tiles */
3070                 tile_height = intel_tile_height(dev_priv, fb->modifier[0], cpp);
3071                 stride = DIV_ROUND_UP(fb->height, tile_height);
3072                 x_offset = stride * tile_height - src_y - src_h;
3073                 y_offset = src_x;
3074                 plane_size = (src_w - 1) << 16 | (src_h - 1);
3075         } else {
3076                 stride = fb->pitches[0] / stride_div;
3077                 x_offset = src_x;
3078                 y_offset = src_y;
3079                 plane_size = (src_h - 1) << 16 | (src_w - 1);
3080         }
3081         plane_offset = y_offset << 16 | x_offset;
3082
3083         intel_crtc->adjusted_x = x_offset;
3084         intel_crtc->adjusted_y = y_offset;
3085
3086         I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3087         I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3088         I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3089         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3090
3091         if (scaler_id >= 0) {
3092                 uint32_t ps_ctrl = 0;
3093
3094                 WARN_ON(!dst_w || !dst_h);
3095                 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3096                         crtc_state->scaler_state.scalers[scaler_id].mode;
3097                 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3098                 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3099                 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3100                 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3101                 I915_WRITE(PLANE_POS(pipe, 0), 0);
3102         } else {
3103                 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3104         }
3105
3106         I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3107
3108         POSTING_READ(PLANE_SURF(pipe, 0));
3109 }
3110
3111 static void skylake_disable_primary_plane(struct drm_plane *primary,
3112                                           struct drm_crtc *crtc)
3113 {
3114         struct drm_device *dev = crtc->dev;
3115         struct drm_i915_private *dev_priv = dev->dev_private;
3116         int pipe = to_intel_crtc(crtc)->pipe;
3117
3118         I915_WRITE(PLANE_CTL(pipe, 0), 0);
3119         I915_WRITE(PLANE_SURF(pipe, 0), 0);
3120         POSTING_READ(PLANE_SURF(pipe, 0));
3121 }
3122
3123 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3124 static int
3125 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3126                            int x, int y, enum mode_set_atomic state)
3127 {
3128         /* Support for kgdboc is disabled, this needs a major rework. */
3129         DRM_ERROR("legacy panic handler not supported any more.\n");
3130
3131         return -ENODEV;
3132 }
3133
3134 static void intel_complete_page_flips(struct drm_i915_private *dev_priv)
3135 {
3136         struct intel_crtc *crtc;
3137
3138         for_each_intel_crtc(dev_priv->dev, crtc)
3139                 intel_finish_page_flip_cs(dev_priv, crtc->pipe);
3140 }
3141
3142 static void intel_update_primary_planes(struct drm_device *dev)
3143 {
3144         struct drm_crtc *crtc;
3145
3146         for_each_crtc(dev, crtc) {
3147                 struct intel_plane *plane = to_intel_plane(crtc->primary);
3148                 struct intel_plane_state *plane_state;
3149
3150                 drm_modeset_lock_crtc(crtc, &plane->base);
3151                 plane_state = to_intel_plane_state(plane->base.state);
3152
3153                 if (plane_state->visible)
3154                         plane->update_plane(&plane->base,
3155                                             to_intel_crtc_state(crtc->state),
3156                                             plane_state);
3157
3158                 drm_modeset_unlock_crtc(crtc);
3159         }
3160 }
3161
3162 void intel_prepare_reset(struct drm_i915_private *dev_priv)
3163 {
3164         /* no reset support for gen2 */
3165         if (IS_GEN2(dev_priv))
3166                 return;
3167
3168         /* reset doesn't touch the display */
3169         if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
3170                 return;
3171
3172         drm_modeset_lock_all(dev_priv->dev);
3173         /*
3174          * Disabling the crtcs gracefully seems nicer. Also the
3175          * g33 docs say we should at least disable all the planes.
3176          */
3177         intel_display_suspend(dev_priv->dev);
3178 }
3179
3180 void intel_finish_reset(struct drm_i915_private *dev_priv)
3181 {
3182         /*
3183          * Flips in the rings will be nuked by the reset,
3184          * so complete all pending flips so that user space
3185          * will get its events and not get stuck.
3186          */
3187         intel_complete_page_flips(dev_priv);
3188
3189         /* no reset support for gen2 */
3190         if (IS_GEN2(dev_priv))
3191                 return;
3192
3193         /* reset doesn't touch the display */
3194         if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) {
3195                 /*
3196                  * Flips in the rings have been nuked by the reset,
3197                  * so update the base address of all primary
3198                  * planes to the the last fb to make sure we're
3199                  * showing the correct fb after a reset.
3200                  *
3201                  * FIXME: Atomic will make this obsolete since we won't schedule
3202                  * CS-based flips (which might get lost in gpu resets) any more.
3203                  */
3204                 intel_update_primary_planes(dev_priv->dev);
3205                 return;
3206         }
3207
3208         /*
3209          * The display has been reset as well,
3210          * so need a full re-initialization.
3211          */
3212         intel_runtime_pm_disable_interrupts(dev_priv);
3213         intel_runtime_pm_enable_interrupts(dev_priv);
3214
3215         intel_modeset_init_hw(dev_priv->dev);
3216
3217         spin_lock_irq(&dev_priv->irq_lock);
3218         if (dev_priv->display.hpd_irq_setup)
3219                 dev_priv->display.hpd_irq_setup(dev_priv);
3220         spin_unlock_irq(&dev_priv->irq_lock);
3221
3222         intel_display_resume(dev_priv->dev);
3223
3224         intel_hpd_init(dev_priv);
3225
3226         drm_modeset_unlock_all(dev_priv->dev);
3227 }
3228
3229 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3230 {
3231         struct drm_device *dev = crtc->dev;
3232         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3233         unsigned reset_counter;
3234         bool pending;
3235
3236         reset_counter = i915_reset_counter(&to_i915(dev)->gpu_error);
3237         if (intel_crtc->reset_counter != reset_counter)
3238                 return false;
3239
3240         spin_lock_irq(&dev->event_lock);
3241         pending = to_intel_crtc(crtc)->flip_work != NULL;
3242         spin_unlock_irq(&dev->event_lock);
3243
3244         return pending;
3245 }
3246
3247 static void intel_update_pipe_config(struct intel_crtc *crtc,
3248                                      struct intel_crtc_state *old_crtc_state)
3249 {
3250         struct drm_device *dev = crtc->base.dev;
3251         struct drm_i915_private *dev_priv = dev->dev_private;
3252         struct intel_crtc_state *pipe_config =
3253                 to_intel_crtc_state(crtc->base.state);
3254
3255         /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3256         crtc->base.mode = crtc->base.state->mode;
3257
3258         DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3259                       old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3260                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3261
3262         /*
3263          * Update pipe size and adjust fitter if needed: the reason for this is
3264          * that in compute_mode_changes we check the native mode (not the pfit
3265          * mode) to see if we can flip rather than do a full mode set. In the
3266          * fastboot case, we'll flip, but if we don't update the pipesrc and
3267          * pfit state, we'll end up with a big fb scanned out into the wrong
3268          * sized surface.
3269          */
3270
3271         I915_WRITE(PIPESRC(crtc->pipe),
3272                    ((pipe_config->pipe_src_w - 1) << 16) |
3273                    (pipe_config->pipe_src_h - 1));
3274
3275         /* on skylake this is done by detaching scalers */
3276         if (INTEL_INFO(dev)->gen >= 9) {
3277                 skl_detach_scalers(crtc);
3278
3279                 if (pipe_config->pch_pfit.enabled)
3280                         skylake_pfit_enable(crtc);
3281         } else if (HAS_PCH_SPLIT(dev)) {
3282                 if (pipe_config->pch_pfit.enabled)
3283                         ironlake_pfit_enable(crtc);
3284                 else if (old_crtc_state->pch_pfit.enabled)
3285                         ironlake_pfit_disable(crtc, true);
3286         }
3287 }
3288
3289 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3290 {
3291         struct drm_device *dev = crtc->dev;
3292         struct drm_i915_private *dev_priv = dev->dev_private;
3293         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3294         int pipe = intel_crtc->pipe;
3295         i915_reg_t reg;
3296         u32 temp;
3297
3298         /* enable normal train */
3299         reg = FDI_TX_CTL(pipe);
3300         temp = I915_READ(reg);
3301         if (IS_IVYBRIDGE(dev)) {
3302                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3303                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3304         } else {
3305                 temp &= ~FDI_LINK_TRAIN_NONE;
3306                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3307         }
3308         I915_WRITE(reg, temp);
3309
3310         reg = FDI_RX_CTL(pipe);
3311         temp = I915_READ(reg);
3312         if (HAS_PCH_CPT(dev)) {
3313                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3314                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3315         } else {
3316                 temp &= ~FDI_LINK_TRAIN_NONE;
3317                 temp |= FDI_LINK_TRAIN_NONE;
3318         }
3319         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3320
3321         /* wait one idle pattern time */
3322         POSTING_READ(reg);
3323         udelay(1000);
3324
3325         /* IVB wants error correction enabled */
3326         if (IS_IVYBRIDGE(dev))
3327                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3328                            FDI_FE_ERRC_ENABLE);
3329 }
3330
3331 /* The FDI link training functions for ILK/Ibexpeak. */
3332 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3333 {
3334         struct drm_device *dev = crtc->dev;
3335         struct drm_i915_private *dev_priv = dev->dev_private;
3336         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3337         int pipe = intel_crtc->pipe;
3338         i915_reg_t reg;
3339         u32 temp, tries;
3340
3341         /* FDI needs bits from pipe first */
3342         assert_pipe_enabled(dev_priv, pipe);
3343
3344         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3345            for train result */
3346         reg = FDI_RX_IMR(pipe);
3347         temp = I915_READ(reg);
3348         temp &= ~FDI_RX_SYMBOL_LOCK;
3349         temp &= ~FDI_RX_BIT_LOCK;
3350         I915_WRITE(reg, temp);
3351         I915_READ(reg);
3352         udelay(150);
3353
3354         /* enable CPU FDI TX and PCH FDI RX */
3355         reg = FDI_TX_CTL(pipe);
3356         temp = I915_READ(reg);
3357         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3358         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3359         temp &= ~FDI_LINK_TRAIN_NONE;
3360         temp |= FDI_LINK_TRAIN_PATTERN_1;
3361         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3362
3363         reg = FDI_RX_CTL(pipe);
3364         temp = I915_READ(reg);
3365         temp &= ~FDI_LINK_TRAIN_NONE;
3366         temp |= FDI_LINK_TRAIN_PATTERN_1;
3367         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3368
3369         POSTING_READ(reg);
3370         udelay(150);
3371
3372         /* Ironlake workaround, enable clock pointer after FDI enable*/
3373         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3374         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3375                    FDI_RX_PHASE_SYNC_POINTER_EN);
3376
3377         reg = FDI_RX_IIR(pipe);
3378         for (tries = 0; tries < 5; tries++) {
3379                 temp = I915_READ(reg);
3380                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3381
3382                 if ((temp & FDI_RX_BIT_LOCK)) {
3383                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3384                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3385                         break;
3386                 }
3387         }
3388         if (tries == 5)
3389                 DRM_ERROR("FDI train 1 fail!\n");
3390
3391         /* Train 2 */
3392         reg = FDI_TX_CTL(pipe);
3393         temp = I915_READ(reg);
3394         temp &= ~FDI_LINK_TRAIN_NONE;
3395         temp |= FDI_LINK_TRAIN_PATTERN_2;
3396         I915_WRITE(reg, temp);
3397
3398         reg = FDI_RX_CTL(pipe);
3399         temp = I915_READ(reg);
3400         temp &= ~FDI_LINK_TRAIN_NONE;
3401         temp |= FDI_LINK_TRAIN_PATTERN_2;
3402         I915_WRITE(reg, temp);
3403
3404         POSTING_READ(reg);
3405         udelay(150);
3406
3407         reg = FDI_RX_IIR(pipe);
3408         for (tries = 0; tries < 5; tries++) {
3409                 temp = I915_READ(reg);
3410                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3411
3412                 if (temp & FDI_RX_SYMBOL_LOCK) {
3413                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3414                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3415                         break;
3416                 }
3417         }
3418         if (tries == 5)
3419                 DRM_ERROR("FDI train 2 fail!\n");
3420
3421         DRM_DEBUG_KMS("FDI train done\n");
3422
3423 }
3424
3425 static const int snb_b_fdi_train_param[] = {
3426         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3427         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3428         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3429         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3430 };
3431
3432 /* The FDI link training functions for SNB/Cougarpoint. */
3433 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3434 {
3435         struct drm_device *dev = crtc->dev;
3436         struct drm_i915_private *dev_priv = dev->dev_private;
3437         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3438         int pipe = intel_crtc->pipe;
3439         i915_reg_t reg;
3440         u32 temp, i, retry;
3441
3442         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3443            for train result */
3444         reg = FDI_RX_IMR(pipe);
3445         temp = I915_READ(reg);
3446         temp &= ~FDI_RX_SYMBOL_LOCK;
3447         temp &= ~FDI_RX_BIT_LOCK;
3448         I915_WRITE(reg, temp);
3449
3450         POSTING_READ(reg);
3451         udelay(150);
3452
3453         /* enable CPU FDI TX and PCH FDI RX */
3454         reg = FDI_TX_CTL(pipe);
3455         temp = I915_READ(reg);
3456         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3457         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3458         temp &= ~FDI_LINK_TRAIN_NONE;
3459         temp |= FDI_LINK_TRAIN_PATTERN_1;
3460         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3461         /* SNB-B */
3462         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3463         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3464
3465         I915_WRITE(FDI_RX_MISC(pipe),
3466                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3467
3468         reg = FDI_RX_CTL(pipe);
3469         temp = I915_READ(reg);
3470         if (HAS_PCH_CPT(dev)) {
3471                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3472                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3473         } else {
3474                 temp &= ~FDI_LINK_TRAIN_NONE;
3475                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3476         }
3477         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3478
3479         POSTING_READ(reg);
3480         udelay(150);
3481
3482         for (i = 0; i < 4; i++) {
3483                 reg = FDI_TX_CTL(pipe);
3484                 temp = I915_READ(reg);
3485                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3486                 temp |= snb_b_fdi_train_param[i];
3487                 I915_WRITE(reg, temp);
3488
3489                 POSTING_READ(reg);
3490                 udelay(500);
3491
3492                 for (retry = 0; retry < 5; retry++) {
3493                         reg = FDI_RX_IIR(pipe);
3494                         temp = I915_READ(reg);
3495                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3496                         if (temp & FDI_RX_BIT_LOCK) {
3497                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3498                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3499                                 break;
3500                         }
3501                         udelay(50);
3502                 }
3503                 if (retry < 5)
3504                         break;
3505         }
3506         if (i == 4)
3507                 DRM_ERROR("FDI train 1 fail!\n");
3508
3509         /* Train 2 */
3510         reg = FDI_TX_CTL(pipe);
3511         temp = I915_READ(reg);
3512         temp &= ~FDI_LINK_TRAIN_NONE;
3513         temp |= FDI_LINK_TRAIN_PATTERN_2;
3514         if (IS_GEN6(dev)) {
3515                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3516                 /* SNB-B */
3517                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3518         }
3519         I915_WRITE(reg, temp);
3520
3521         reg = FDI_RX_CTL(pipe);
3522         temp = I915_READ(reg);
3523         if (HAS_PCH_CPT(dev)) {
3524                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3525                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3526         } else {
3527                 temp &= ~FDI_LINK_TRAIN_NONE;
3528                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3529         }
3530         I915_WRITE(reg, temp);
3531
3532         POSTING_READ(reg);
3533         udelay(150);
3534
3535         for (i = 0; i < 4; i++) {
3536                 reg = FDI_TX_CTL(pipe);
3537                 temp = I915_READ(reg);
3538                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3539                 temp |= snb_b_fdi_train_param[i];
3540                 I915_WRITE(reg, temp);
3541
3542                 POSTING_READ(reg);
3543                 udelay(500);
3544
3545                 for (retry = 0; retry < 5; retry++) {
3546                         reg = FDI_RX_IIR(pipe);
3547                         temp = I915_READ(reg);
3548                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3549                         if (temp & FDI_RX_SYMBOL_LOCK) {
3550                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3551                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3552                                 break;
3553                         }
3554                         udelay(50);
3555                 }
3556                 if (retry < 5)
3557                         break;
3558         }
3559         if (i == 4)
3560                 DRM_ERROR("FDI train 2 fail!\n");
3561
3562         DRM_DEBUG_KMS("FDI train done.\n");
3563 }
3564
3565 /* Manual link training for Ivy Bridge A0 parts */
3566 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3567 {
3568         struct drm_device *dev = crtc->dev;
3569         struct drm_i915_private *dev_priv = dev->dev_private;
3570         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3571         int pipe = intel_crtc->pipe;
3572         i915_reg_t reg;
3573         u32 temp, i, j;
3574
3575         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3576            for train result */
3577         reg = FDI_RX_IMR(pipe);
3578         temp = I915_READ(reg);
3579         temp &= ~FDI_RX_SYMBOL_LOCK;
3580         temp &= ~FDI_RX_BIT_LOCK;
3581         I915_WRITE(reg, temp);
3582
3583         POSTING_READ(reg);
3584         udelay(150);
3585
3586         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3587                       I915_READ(FDI_RX_IIR(pipe)));
3588
3589         /* Try each vswing and preemphasis setting twice before moving on */
3590         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3591                 /* disable first in case we need to retry */
3592                 reg = FDI_TX_CTL(pipe);
3593                 temp = I915_READ(reg);
3594                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3595                 temp &= ~FDI_TX_ENABLE;
3596                 I915_WRITE(reg, temp);
3597
3598                 reg = FDI_RX_CTL(pipe);
3599                 temp = I915_READ(reg);
3600                 temp &= ~FDI_LINK_TRAIN_AUTO;
3601                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3602                 temp &= ~FDI_RX_ENABLE;
3603                 I915_WRITE(reg, temp);
3604
3605                 /* enable CPU FDI TX and PCH FDI RX */
3606                 reg = FDI_TX_CTL(pipe);
3607                 temp = I915_READ(reg);
3608                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3609                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3610                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3611                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3612                 temp |= snb_b_fdi_train_param[j/2];
3613                 temp |= FDI_COMPOSITE_SYNC;
3614                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3615
3616                 I915_WRITE(FDI_RX_MISC(pipe),
3617                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3618
3619                 reg = FDI_RX_CTL(pipe);
3620                 temp = I915_READ(reg);
3621                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3622                 temp |= FDI_COMPOSITE_SYNC;
3623                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3624
3625                 POSTING_READ(reg);
3626                 udelay(1); /* should be 0.5us */
3627
3628                 for (i = 0; i < 4; i++) {
3629                         reg = FDI_RX_IIR(pipe);
3630                         temp = I915_READ(reg);
3631                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3632
3633                         if (temp & FDI_RX_BIT_LOCK ||
3634                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3635                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3636                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3637                                               i);
3638                                 break;
3639                         }
3640                         udelay(1); /* should be 0.5us */
3641                 }
3642                 if (i == 4) {
3643                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3644                         continue;
3645                 }
3646
3647                 /* Train 2 */
3648                 reg = FDI_TX_CTL(pipe);
3649                 temp = I915_READ(reg);
3650                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3651                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3652                 I915_WRITE(reg, temp);
3653
3654                 reg = FDI_RX_CTL(pipe);
3655                 temp = I915_READ(reg);
3656                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3657                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3658                 I915_WRITE(reg, temp);
3659
3660                 POSTING_READ(reg);
3661                 udelay(2); /* should be 1.5us */
3662
3663                 for (i = 0; i < 4; i++) {
3664                         reg = FDI_RX_IIR(pipe);
3665                         temp = I915_READ(reg);
3666                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3667
3668                         if (temp & FDI_RX_SYMBOL_LOCK ||
3669                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3670                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3671                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3672                                               i);
3673                                 goto train_done;
3674                         }
3675                         udelay(2); /* should be 1.5us */
3676                 }
3677                 if (i == 4)
3678                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3679         }
3680
3681 train_done:
3682         DRM_DEBUG_KMS("FDI train done.\n");
3683 }
3684
3685 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3686 {
3687         struct drm_device *dev = intel_crtc->base.dev;
3688         struct drm_i915_private *dev_priv = dev->dev_private;
3689         int pipe = intel_crtc->pipe;
3690         i915_reg_t reg;
3691         u32 temp;
3692
3693         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3694         reg = FDI_RX_CTL(pipe);
3695         temp = I915_READ(reg);
3696         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3697         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3698         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3699         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3700
3701         POSTING_READ(reg);
3702         udelay(200);
3703
3704         /* Switch from Rawclk to PCDclk */
3705         temp = I915_READ(reg);
3706         I915_WRITE(reg, temp | FDI_PCDCLK);
3707
3708         POSTING_READ(reg);
3709         udelay(200);
3710
3711         /* Enable CPU FDI TX PLL, always on for Ironlake */
3712         reg = FDI_TX_CTL(pipe);
3713         temp = I915_READ(reg);
3714         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3715                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3716
3717                 POSTING_READ(reg);
3718                 udelay(100);
3719         }
3720 }
3721
3722 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3723 {
3724         struct drm_device *dev = intel_crtc->base.dev;
3725         struct drm_i915_private *dev_priv = dev->dev_private;
3726         int pipe = intel_crtc->pipe;
3727         i915_reg_t reg;
3728         u32 temp;
3729
3730         /* Switch from PCDclk to Rawclk */
3731         reg = FDI_RX_CTL(pipe);
3732         temp = I915_READ(reg);
3733         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3734
3735         /* Disable CPU FDI TX PLL */
3736         reg = FDI_TX_CTL(pipe);
3737         temp = I915_READ(reg);
3738         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3739
3740         POSTING_READ(reg);
3741         udelay(100);
3742
3743         reg = FDI_RX_CTL(pipe);
3744         temp = I915_READ(reg);
3745         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3746
3747         /* Wait for the clocks to turn off. */
3748         POSTING_READ(reg);
3749         udelay(100);
3750 }
3751
3752 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3753 {
3754         struct drm_device *dev = crtc->dev;
3755         struct drm_i915_private *dev_priv = dev->dev_private;
3756         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3757         int pipe = intel_crtc->pipe;
3758         i915_reg_t reg;
3759         u32 temp;
3760
3761         /* disable CPU FDI tx and PCH FDI rx */
3762         reg = FDI_TX_CTL(pipe);
3763         temp = I915_READ(reg);
3764         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3765         POSTING_READ(reg);
3766
3767         reg = FDI_RX_CTL(pipe);
3768         temp = I915_READ(reg);
3769         temp &= ~(0x7 << 16);
3770         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3771         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3772
3773         POSTING_READ(reg);
3774         udelay(100);
3775
3776         /* Ironlake workaround, disable clock pointer after downing FDI */
3777         if (HAS_PCH_IBX(dev))
3778                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3779
3780         /* still set train pattern 1 */
3781         reg = FDI_TX_CTL(pipe);
3782         temp = I915_READ(reg);
3783         temp &= ~FDI_LINK_TRAIN_NONE;
3784         temp |= FDI_LINK_TRAIN_PATTERN_1;
3785         I915_WRITE(reg, temp);
3786
3787         reg = FDI_RX_CTL(pipe);
3788         temp = I915_READ(reg);
3789         if (HAS_PCH_CPT(dev)) {
3790                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3791                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3792         } else {
3793                 temp &= ~FDI_LINK_TRAIN_NONE;
3794                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3795         }
3796         /* BPC in FDI rx is consistent with that in PIPECONF */
3797         temp &= ~(0x07 << 16);
3798         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3799         I915_WRITE(reg, temp);
3800
3801         POSTING_READ(reg);
3802         udelay(100);
3803 }
3804
3805 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3806 {
3807         struct intel_crtc *crtc;
3808
3809         /* Note that we don't need to be called with mode_config.lock here
3810          * as our list of CRTC objects is static for the lifetime of the
3811          * device and so cannot disappear as we iterate. Similarly, we can
3812          * happily treat the predicates as racy, atomic checks as userspace
3813          * cannot claim and pin a new fb without at least acquring the
3814          * struct_mutex and so serialising with us.
3815          */
3816         for_each_intel_crtc(dev, crtc) {
3817                 if (atomic_read(&crtc->unpin_work_count) == 0)
3818                         continue;
3819
3820                 if (crtc->flip_work)
3821                         intel_wait_for_vblank(dev, crtc->pipe);
3822
3823                 return true;
3824         }
3825
3826         return false;
3827 }
3828
3829 static void page_flip_completed(struct intel_crtc *intel_crtc)
3830 {
3831         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3832         struct intel_flip_work *work = intel_crtc->flip_work;
3833
3834         intel_crtc->flip_work = NULL;
3835
3836         if (work->event)
3837                 drm_crtc_send_vblank_event(&intel_crtc->base, work->event);
3838
3839         drm_crtc_vblank_put(&intel_crtc->base);
3840
3841         wake_up_all(&dev_priv->pending_flip_queue);
3842         queue_work(dev_priv->wq, &work->unpin_work);
3843
3844         trace_i915_flip_complete(intel_crtc->plane,
3845                                  work->pending_flip_obj);
3846 }
3847
3848 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3849 {
3850         struct drm_device *dev = crtc->dev;
3851         struct drm_i915_private *dev_priv = dev->dev_private;
3852         long ret;
3853
3854         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3855
3856         ret = wait_event_interruptible_timeout(
3857                                         dev_priv->pending_flip_queue,
3858                                         !intel_crtc_has_pending_flip(crtc),
3859                                         60*HZ);
3860
3861         if (ret < 0)
3862                 return ret;
3863
3864         if (ret == 0) {
3865                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3866                 struct intel_flip_work *work;
3867
3868                 spin_lock_irq(&dev->event_lock);
3869                 work = intel_crtc->flip_work;
3870                 if (work && !is_mmio_work(work)) {
3871                         WARN_ONCE(1, "Removing stuck page flip\n");
3872                         page_flip_completed(intel_crtc);
3873                 }
3874                 spin_unlock_irq(&dev->event_lock);
3875         }
3876
3877         return 0;
3878 }
3879
3880 static void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
3881 {
3882         u32 temp;
3883
3884         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3885
3886         mutex_lock(&dev_priv->sb_lock);
3887
3888         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3889         temp |= SBI_SSCCTL_DISABLE;
3890         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3891
3892         mutex_unlock(&dev_priv->sb_lock);
3893 }
3894
3895 /* Program iCLKIP clock to the desired frequency */
3896 static void lpt_program_iclkip(struct drm_crtc *crtc)
3897 {
3898         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
3899         int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3900         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3901         u32 temp;
3902
3903         lpt_disable_iclkip(dev_priv);
3904
3905         /* The iCLK virtual clock root frequency is in MHz,
3906          * but the adjusted_mode->crtc_clock in in KHz. To get the
3907          * divisors, it is necessary to divide one by another, so we
3908          * convert the virtual clock precision to KHz here for higher
3909          * precision.
3910          */
3911         for (auxdiv = 0; auxdiv < 2; auxdiv++) {
3912                 u32 iclk_virtual_root_freq = 172800 * 1000;
3913                 u32 iclk_pi_range = 64;
3914                 u32 desired_divisor;
3915
3916                 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
3917                                                     clock << auxdiv);
3918                 divsel = (desired_divisor / iclk_pi_range) - 2;
3919                 phaseinc = desired_divisor % iclk_pi_range;
3920
3921                 /*
3922                  * Near 20MHz is a corner case which is
3923                  * out of range for the 7-bit divisor
3924                  */
3925                 if (divsel <= 0x7f)
3926                         break;
3927         }
3928
3929         /* This should not happen with any sane values */
3930         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3931                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3932         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3933                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3934
3935         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3936                         clock,
3937                         auxdiv,
3938                         divsel,
3939                         phasedir,
3940                         phaseinc);
3941
3942         mutex_lock(&dev_priv->sb_lock);
3943
3944         /* Program SSCDIVINTPHASE6 */
3945         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3946         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3947         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3948         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3949         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3950         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3951         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3952         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3953
3954         /* Program SSCAUXDIV */
3955         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3956         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3957         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3958         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3959
3960         /* Enable modulator and associated divider */
3961         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3962         temp &= ~SBI_SSCCTL_DISABLE;
3963         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3964
3965         mutex_unlock(&dev_priv->sb_lock);
3966
3967         /* Wait for initialization time */
3968         udelay(24);
3969
3970         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3971 }
3972
3973 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
3974 {
3975         u32 divsel, phaseinc, auxdiv;
3976         u32 iclk_virtual_root_freq = 172800 * 1000;
3977         u32 iclk_pi_range = 64;
3978         u32 desired_divisor;
3979         u32 temp;
3980
3981         if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
3982                 return 0;
3983
3984         mutex_lock(&dev_priv->sb_lock);
3985
3986         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3987         if (temp & SBI_SSCCTL_DISABLE) {
3988                 mutex_unlock(&dev_priv->sb_lock);
3989                 return 0;
3990         }
3991
3992         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3993         divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
3994                 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
3995         phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
3996                 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
3997
3998         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3999         auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
4000                 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
4001
4002         mutex_unlock(&dev_priv->sb_lock);
4003
4004         desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
4005
4006         return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4007                                  desired_divisor << auxdiv);
4008 }
4009
4010 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4011                                                 enum pipe pch_transcoder)
4012 {
4013         struct drm_device *dev = crtc->base.dev;
4014         struct drm_i915_private *dev_priv = dev->dev_private;
4015         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4016
4017         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4018                    I915_READ(HTOTAL(cpu_transcoder)));
4019         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4020                    I915_READ(HBLANK(cpu_transcoder)));
4021         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4022                    I915_READ(HSYNC(cpu_transcoder)));
4023
4024         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4025                    I915_READ(VTOTAL(cpu_transcoder)));
4026         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4027                    I915_READ(VBLANK(cpu_transcoder)));
4028         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4029                    I915_READ(VSYNC(cpu_transcoder)));
4030         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4031                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
4032 }
4033
4034 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4035 {
4036         struct drm_i915_private *dev_priv = dev->dev_private;
4037         uint32_t temp;
4038
4039         temp = I915_READ(SOUTH_CHICKEN1);
4040         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4041                 return;
4042
4043         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4044         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4045
4046         temp &= ~FDI_BC_BIFURCATION_SELECT;
4047         if (enable)
4048                 temp |= FDI_BC_BIFURCATION_SELECT;
4049
4050         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4051         I915_WRITE(SOUTH_CHICKEN1, temp);
4052         POSTING_READ(SOUTH_CHICKEN1);
4053 }
4054
4055 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4056 {
4057         struct drm_device *dev = intel_crtc->base.dev;
4058
4059         switch (intel_crtc->pipe) {
4060         case PIPE_A:
4061                 break;
4062         case PIPE_B:
4063                 if (intel_crtc->config->fdi_lanes > 2)
4064                         cpt_set_fdi_bc_bifurcation(dev, false);
4065                 else
4066                         cpt_set_fdi_bc_bifurcation(dev, true);
4067
4068                 break;
4069         case PIPE_C:
4070                 cpt_set_fdi_bc_bifurcation(dev, true);
4071
4072                 break;
4073         default:
4074                 BUG();
4075         }
4076 }
4077
4078 /* Return which DP Port should be selected for Transcoder DP control */
4079 static enum port
4080 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4081 {
4082         struct drm_device *dev = crtc->dev;
4083         struct intel_encoder *encoder;
4084
4085         for_each_encoder_on_crtc(dev, crtc, encoder) {
4086                 if (encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4087                     encoder->type == INTEL_OUTPUT_EDP)
4088                         return enc_to_dig_port(&encoder->base)->port;
4089         }
4090
4091         return -1;
4092 }
4093
4094 /*
4095  * Enable PCH resources required for PCH ports:
4096  *   - PCH PLLs
4097  *   - FDI training & RX/TX
4098  *   - update transcoder timings
4099  *   - DP transcoding bits
4100  *   - transcoder
4101  */
4102 static void ironlake_pch_enable(struct drm_crtc *crtc)
4103 {
4104         struct drm_device *dev = crtc->dev;
4105         struct drm_i915_private *dev_priv = dev->dev_private;
4106         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4107         int pipe = intel_crtc->pipe;
4108         u32 temp;
4109
4110         assert_pch_transcoder_disabled(dev_priv, pipe);
4111
4112         if (IS_IVYBRIDGE(dev))
4113                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4114
4115         /* Write the TU size bits before fdi link training, so that error
4116          * detection works. */
4117         I915_WRITE(FDI_RX_TUSIZE1(pipe),
4118                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4119
4120         /* For PCH output, training FDI link */
4121         dev_priv->display.fdi_link_train(crtc);
4122
4123         /* We need to program the right clock selection before writing the pixel
4124          * mutliplier into the DPLL. */
4125         if (HAS_PCH_CPT(dev)) {
4126                 u32 sel;
4127
4128                 temp = I915_READ(PCH_DPLL_SEL);
4129                 temp |= TRANS_DPLL_ENABLE(pipe);
4130                 sel = TRANS_DPLLB_SEL(pipe);
4131                 if (intel_crtc->config->shared_dpll ==
4132                     intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4133                         temp |= sel;
4134                 else
4135                         temp &= ~sel;
4136                 I915_WRITE(PCH_DPLL_SEL, temp);
4137         }
4138
4139         /* XXX: pch pll's can be enabled any time before we enable the PCH
4140          * transcoder, and we actually should do this to not upset any PCH
4141          * transcoder that already use the clock when we share it.
4142          *
4143          * Note that enable_shared_dpll tries to do the right thing, but
4144          * get_shared_dpll unconditionally resets the pll - we need that to have
4145          * the right LVDS enable sequence. */
4146         intel_enable_shared_dpll(intel_crtc);
4147
4148         /* set transcoder timing, panel must allow it */
4149         assert_panel_unlocked(dev_priv, pipe);
4150         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4151
4152         intel_fdi_normal_train(crtc);
4153
4154         /* For PCH DP, enable TRANS_DP_CTL */
4155         if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4156                 const struct drm_display_mode *adjusted_mode =
4157                         &intel_crtc->config->base.adjusted_mode;
4158                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4159                 i915_reg_t reg = TRANS_DP_CTL(pipe);
4160                 temp = I915_READ(reg);
4161                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4162                           TRANS_DP_SYNC_MASK |
4163                           TRANS_DP_BPC_MASK);
4164                 temp |= TRANS_DP_OUTPUT_ENABLE;
4165                 temp |= bpc << 9; /* same format but at 11:9 */
4166
4167                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4168                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4169                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4170                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4171
4172                 switch (intel_trans_dp_port_sel(crtc)) {
4173                 case PORT_B:
4174                         temp |= TRANS_DP_PORT_SEL_B;
4175                         break;
4176                 case PORT_C:
4177                         temp |= TRANS_DP_PORT_SEL_C;
4178                         break;
4179                 case PORT_D:
4180                         temp |= TRANS_DP_PORT_SEL_D;
4181                         break;
4182                 default:
4183                         BUG();
4184                 }
4185
4186                 I915_WRITE(reg, temp);
4187         }
4188
4189         ironlake_enable_pch_transcoder(dev_priv, pipe);
4190 }
4191
4192 static void lpt_pch_enable(struct drm_crtc *crtc)
4193 {
4194         struct drm_device *dev = crtc->dev;
4195         struct drm_i915_private *dev_priv = dev->dev_private;
4196         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4197         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4198
4199         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4200
4201         lpt_program_iclkip(crtc);
4202
4203         /* Set transcoder timing. */
4204         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4205
4206         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4207 }
4208
4209 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4210 {
4211         struct drm_i915_private *dev_priv = dev->dev_private;
4212         i915_reg_t dslreg = PIPEDSL(pipe);
4213         u32 temp;
4214
4215         temp = I915_READ(dslreg);
4216         udelay(500);
4217         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4218                 if (wait_for(I915_READ(dslreg) != temp, 5))
4219                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4220         }
4221 }
4222
4223 static int
4224 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4225                   unsigned scaler_user, int *scaler_id, unsigned int rotation,
4226                   int src_w, int src_h, int dst_w, int dst_h)
4227 {
4228         struct intel_crtc_scaler_state *scaler_state =
4229                 &crtc_state->scaler_state;
4230         struct intel_crtc *intel_crtc =
4231                 to_intel_crtc(crtc_state->base.crtc);
4232         int need_scaling;
4233
4234         need_scaling = intel_rotation_90_or_270(rotation) ?
4235                 (src_h != dst_w || src_w != dst_h):
4236                 (src_w != dst_w || src_h != dst_h);
4237
4238         /*
4239          * if plane is being disabled or scaler is no more required or force detach
4240          *  - free scaler binded to this plane/crtc
4241          *  - in order to do this, update crtc->scaler_usage
4242          *
4243          * Here scaler state in crtc_state is set free so that
4244          * scaler can be assigned to other user. Actual register
4245          * update to free the scaler is done in plane/panel-fit programming.
4246          * For this purpose crtc/plane_state->scaler_id isn't reset here.
4247          */
4248         if (force_detach || !need_scaling) {
4249                 if (*scaler_id >= 0) {
4250                         scaler_state->scaler_users &= ~(1 << scaler_user);
4251                         scaler_state->scalers[*scaler_id].in_use = 0;
4252
4253                         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4254                                 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4255                                 intel_crtc->pipe, scaler_user, *scaler_id,
4256                                 scaler_state->scaler_users);
4257                         *scaler_id = -1;
4258                 }
4259                 return 0;
4260         }
4261
4262         /* range checks */
4263         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4264                 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4265
4266                 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4267                 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4268                 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4269                         "size is out of scaler range\n",
4270                         intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4271                 return -EINVAL;
4272         }
4273
4274         /* mark this plane as a scaler user in crtc_state */
4275         scaler_state->scaler_users |= (1 << scaler_user);
4276         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4277                 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4278                 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4279                 scaler_state->scaler_users);
4280
4281         return 0;
4282 }
4283
4284 /**
4285  * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4286  *
4287  * @state: crtc's scaler state
4288  *
4289  * Return
4290  *     0 - scaler_usage updated successfully
4291  *    error - requested scaling cannot be supported or other error condition
4292  */
4293 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4294 {
4295         struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4296         const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4297
4298         DRM_DEBUG_KMS("Updating scaler for [CRTC:%d:%s] scaler_user index %u.%u\n",
4299                       intel_crtc->base.base.id, intel_crtc->base.name,
4300                       intel_crtc->pipe, SKL_CRTC_INDEX);
4301
4302         return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4303                 &state->scaler_state.scaler_id, BIT(DRM_ROTATE_0),
4304                 state->pipe_src_w, state->pipe_src_h,
4305                 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4306 }
4307
4308 /**
4309  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4310  *
4311  * @state: crtc's scaler state
4312  * @plane_state: atomic plane state to update
4313  *
4314  * Return
4315  *     0 - scaler_usage updated successfully
4316  *    error - requested scaling cannot be supported or other error condition
4317  */
4318 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4319                                    struct intel_plane_state *plane_state)
4320 {
4321
4322         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4323         struct intel_plane *intel_plane =
4324                 to_intel_plane(plane_state->base.plane);
4325         struct drm_framebuffer *fb = plane_state->base.fb;
4326         int ret;
4327
4328         bool force_detach = !fb || !plane_state->visible;
4329
4330         DRM_DEBUG_KMS("Updating scaler for [PLANE:%d:%s] scaler_user index %u.%u\n",
4331                       intel_plane->base.base.id, intel_plane->base.name,
4332                       intel_crtc->pipe, drm_plane_index(&intel_plane->base));
4333
4334         ret = skl_update_scaler(crtc_state, force_detach,
4335                                 drm_plane_index(&intel_plane->base),
4336                                 &plane_state->scaler_id,
4337                                 plane_state->base.rotation,
4338                                 drm_rect_width(&plane_state->src) >> 16,
4339                                 drm_rect_height(&plane_state->src) >> 16,
4340                                 drm_rect_width(&plane_state->dst),
4341                                 drm_rect_height(&plane_state->dst));
4342
4343         if (ret || plane_state->scaler_id < 0)
4344                 return ret;
4345
4346         /* check colorkey */
4347         if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4348                 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
4349                               intel_plane->base.base.id,
4350                               intel_plane->base.name);
4351                 return -EINVAL;
4352         }
4353
4354         /* Check src format */
4355         switch (fb->pixel_format) {
4356         case DRM_FORMAT_RGB565:
4357         case DRM_FORMAT_XBGR8888:
4358         case DRM_FORMAT_XRGB8888:
4359         case DRM_FORMAT_ABGR8888:
4360         case DRM_FORMAT_ARGB8888:
4361         case DRM_FORMAT_XRGB2101010:
4362         case DRM_FORMAT_XBGR2101010:
4363         case DRM_FORMAT_YUYV:
4364         case DRM_FORMAT_YVYU:
4365         case DRM_FORMAT_UYVY:
4366         case DRM_FORMAT_VYUY:
4367                 break;
4368         default:
4369                 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
4370                               intel_plane->base.base.id, intel_plane->base.name,
4371                               fb->base.id, fb->pixel_format);
4372                 return -EINVAL;
4373         }
4374
4375         return 0;
4376 }
4377
4378 static void skylake_scaler_disable(struct intel_crtc *crtc)
4379 {
4380         int i;
4381
4382         for (i = 0; i < crtc->num_scalers; i++)
4383                 skl_detach_scaler(crtc, i);
4384 }
4385
4386 static void skylake_pfit_enable(struct intel_crtc *crtc)
4387 {
4388         struct drm_device *dev = crtc->base.dev;
4389         struct drm_i915_private *dev_priv = dev->dev_private;
4390         int pipe = crtc->pipe;
4391         struct intel_crtc_scaler_state *scaler_state =
4392                 &crtc->config->scaler_state;
4393
4394         DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4395
4396         if (crtc->config->pch_pfit.enabled) {
4397                 int id;
4398
4399                 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4400                         DRM_ERROR("Requesting pfit without getting a scaler first\n");
4401                         return;
4402                 }
4403
4404                 id = scaler_state->scaler_id;
4405                 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4406                         PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4407                 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4408                 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4409
4410                 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4411         }
4412 }
4413
4414 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4415 {
4416         struct drm_device *dev = crtc->base.dev;
4417         struct drm_i915_private *dev_priv = dev->dev_private;
4418         int pipe = crtc->pipe;
4419
4420         if (crtc->config->pch_pfit.enabled) {
4421                 /* Force use of hard-coded filter coefficients
4422                  * as some pre-programmed values are broken,
4423                  * e.g. x201.
4424                  */
4425                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4426                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4427                                                  PF_PIPE_SEL_IVB(pipe));
4428                 else
4429                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4430                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4431                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4432         }
4433 }
4434
4435 void hsw_enable_ips(struct intel_crtc *crtc)
4436 {
4437         struct drm_device *dev = crtc->base.dev;
4438         struct drm_i915_private *dev_priv = dev->dev_private;
4439
4440         if (!crtc->config->ips_enabled)
4441                 return;
4442
4443         /*
4444          * We can only enable IPS after we enable a plane and wait for a vblank
4445          * This function is called from post_plane_update, which is run after
4446          * a vblank wait.
4447          */
4448
4449         assert_plane_enabled(dev_priv, crtc->plane);
4450         if (IS_BROADWELL(dev)) {
4451                 mutex_lock(&dev_priv->rps.hw_lock);
4452                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4453                 mutex_unlock(&dev_priv->rps.hw_lock);
4454                 /* Quoting Art Runyan: "its not safe to expect any particular
4455                  * value in IPS_CTL bit 31 after enabling IPS through the
4456                  * mailbox." Moreover, the mailbox may return a bogus state,
4457                  * so we need to just enable it and continue on.
4458                  */
4459         } else {
4460                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4461                 /* The bit only becomes 1 in the next vblank, so this wait here
4462                  * is essentially intel_wait_for_vblank. If we don't have this
4463                  * and don't wait for vblanks until the end of crtc_enable, then
4464                  * the HW state readout code will complain that the expected
4465                  * IPS_CTL value is not the one we read. */
4466                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4467                         DRM_ERROR("Timed out waiting for IPS enable\n");
4468         }
4469 }
4470
4471 void hsw_disable_ips(struct intel_crtc *crtc)
4472 {
4473         struct drm_device *dev = crtc->base.dev;
4474         struct drm_i915_private *dev_priv = dev->dev_private;
4475
4476         if (!crtc->config->ips_enabled)
4477                 return;
4478
4479         assert_plane_enabled(dev_priv, crtc->plane);
4480         if (IS_BROADWELL(dev)) {
4481                 mutex_lock(&dev_priv->rps.hw_lock);
4482                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4483                 mutex_unlock(&dev_priv->rps.hw_lock);
4484                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4485                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4486                         DRM_ERROR("Timed out waiting for IPS disable\n");
4487         } else {
4488                 I915_WRITE(IPS_CTL, 0);
4489                 POSTING_READ(IPS_CTL);
4490         }
4491
4492         /* We need to wait for a vblank before we can disable the plane. */
4493         intel_wait_for_vblank(dev, crtc->pipe);
4494 }
4495
4496 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4497 {
4498         if (intel_crtc->overlay) {
4499                 struct drm_device *dev = intel_crtc->base.dev;
4500                 struct drm_i915_private *dev_priv = dev->dev_private;
4501
4502                 mutex_lock(&dev->struct_mutex);
4503                 dev_priv->mm.interruptible = false;
4504                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4505                 dev_priv->mm.interruptible = true;
4506                 mutex_unlock(&dev->struct_mutex);
4507         }
4508
4509         /* Let userspace switch the overlay on again. In most cases userspace
4510          * has to recompute where to put it anyway.
4511          */
4512 }
4513
4514 /**
4515  * intel_post_enable_primary - Perform operations after enabling primary plane
4516  * @crtc: the CRTC whose primary plane was just enabled
4517  *
4518  * Performs potentially sleeping operations that must be done after the primary
4519  * plane is enabled, such as updating FBC and IPS.  Note that this may be
4520  * called due to an explicit primary plane update, or due to an implicit
4521  * re-enable that is caused when a sprite plane is updated to no longer
4522  * completely hide the primary plane.
4523  */
4524 static void
4525 intel_post_enable_primary(struct drm_crtc *crtc)
4526 {
4527         struct drm_device *dev = crtc->dev;
4528         struct drm_i915_private *dev_priv = dev->dev_private;
4529         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4530         int pipe = intel_crtc->pipe;
4531
4532         /*
4533          * FIXME IPS should be fine as long as one plane is
4534          * enabled, but in practice it seems to have problems
4535          * when going from primary only to sprite only and vice
4536          * versa.
4537          */
4538         hsw_enable_ips(intel_crtc);
4539
4540         /*
4541          * Gen2 reports pipe underruns whenever all planes are disabled.
4542          * So don't enable underrun reporting before at least some planes
4543          * are enabled.
4544          * FIXME: Need to fix the logic to work when we turn off all planes
4545          * but leave the pipe running.
4546          */
4547         if (IS_GEN2(dev))
4548                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4549
4550         /* Underruns don't always raise interrupts, so check manually. */
4551         intel_check_cpu_fifo_underruns(dev_priv);
4552         intel_check_pch_fifo_underruns(dev_priv);
4553 }
4554
4555 /* FIXME move all this to pre_plane_update() with proper state tracking */
4556 static void
4557 intel_pre_disable_primary(struct drm_crtc *crtc)
4558 {
4559         struct drm_device *dev = crtc->dev;
4560         struct drm_i915_private *dev_priv = dev->dev_private;
4561         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4562         int pipe = intel_crtc->pipe;
4563
4564         /*
4565          * Gen2 reports pipe underruns whenever all planes are disabled.
4566          * So diasble underrun reporting before all the planes get disabled.
4567          * FIXME: Need to fix the logic to work when we turn off all planes
4568          * but leave the pipe running.
4569          */
4570         if (IS_GEN2(dev))
4571                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4572
4573         /*
4574          * FIXME IPS should be fine as long as one plane is
4575          * enabled, but in practice it seems to have problems
4576          * when going from primary only to sprite only and vice
4577          * versa.
4578          */
4579         hsw_disable_ips(intel_crtc);
4580 }
4581
4582 /* FIXME get rid of this and use pre_plane_update */
4583 static void
4584 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
4585 {
4586         struct drm_device *dev = crtc->dev;
4587         struct drm_i915_private *dev_priv = dev->dev_private;
4588         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4589         int pipe = intel_crtc->pipe;
4590
4591         intel_pre_disable_primary(crtc);
4592
4593         /*
4594          * Vblank time updates from the shadow to live plane control register
4595          * are blocked if the memory self-refresh mode is active at that
4596          * moment. So to make sure the plane gets truly disabled, disable
4597          * first the self-refresh mode. The self-refresh enable bit in turn
4598          * will be checked/applied by the HW only at the next frame start
4599          * event which is after the vblank start event, so we need to have a
4600          * wait-for-vblank between disabling the plane and the pipe.
4601          */
4602         if (HAS_GMCH_DISPLAY(dev)) {
4603                 intel_set_memory_cxsr(dev_priv, false);
4604                 dev_priv->wm.vlv.cxsr = false;
4605                 intel_wait_for_vblank(dev, pipe);
4606         }
4607 }
4608
4609 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
4610 {
4611         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4612         struct drm_atomic_state *old_state = old_crtc_state->base.state;
4613         struct intel_crtc_state *pipe_config =
4614                 to_intel_crtc_state(crtc->base.state);
4615         struct drm_device *dev = crtc->base.dev;
4616         struct drm_plane *primary = crtc->base.primary;
4617         struct drm_plane_state *old_pri_state =
4618                 drm_atomic_get_existing_plane_state(old_state, primary);
4619
4620         intel_frontbuffer_flip(dev, pipe_config->fb_bits);
4621
4622         crtc->wm.cxsr_allowed = true;
4623
4624         if (pipe_config->update_wm_post && pipe_config->base.active)
4625                 intel_update_watermarks(&crtc->base);
4626
4627         if (old_pri_state) {
4628                 struct intel_plane_state *primary_state =
4629                         to_intel_plane_state(primary->state);
4630                 struct intel_plane_state *old_primary_state =
4631                         to_intel_plane_state(old_pri_state);
4632
4633                 intel_fbc_post_update(crtc);
4634
4635                 if (primary_state->visible &&
4636                     (needs_modeset(&pipe_config->base) ||
4637                      !old_primary_state->visible))
4638                         intel_post_enable_primary(&crtc->base);
4639         }
4640 }
4641
4642 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state)
4643 {
4644         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4645         struct drm_device *dev = crtc->base.dev;
4646         struct drm_i915_private *dev_priv = dev->dev_private;
4647         struct intel_crtc_state *pipe_config =
4648                 to_intel_crtc_state(crtc->base.state);
4649         struct drm_atomic_state *old_state = old_crtc_state->base.state;
4650         struct drm_plane *primary = crtc->base.primary;
4651         struct drm_plane_state *old_pri_state =
4652                 drm_atomic_get_existing_plane_state(old_state, primary);
4653         bool modeset = needs_modeset(&pipe_config->base);
4654
4655         if (old_pri_state) {
4656                 struct intel_plane_state *primary_state =
4657                         to_intel_plane_state(primary->state);
4658                 struct intel_plane_state *old_primary_state =
4659                         to_intel_plane_state(old_pri_state);
4660
4661                 intel_fbc_pre_update(crtc, pipe_config, primary_state);
4662
4663                 if (old_primary_state->visible &&
4664                     (modeset || !primary_state->visible))
4665                         intel_pre_disable_primary(&crtc->base);
4666         }
4667
4668         if (pipe_config->disable_cxsr && HAS_GMCH_DISPLAY(dev)) {
4669                 crtc->wm.cxsr_allowed = false;
4670
4671                 /*
4672                  * Vblank time updates from the shadow to live plane control register
4673                  * are blocked if the memory self-refresh mode is active at that
4674                  * moment. So to make sure the plane gets truly disabled, disable
4675                  * first the self-refresh mode. The self-refresh enable bit in turn
4676                  * will be checked/applied by the HW only at the next frame start
4677                  * event which is after the vblank start event, so we need to have a
4678                  * wait-for-vblank between disabling the plane and the pipe.
4679                  */
4680                 if (old_crtc_state->base.active) {
4681                         intel_set_memory_cxsr(dev_priv, false);
4682                         dev_priv->wm.vlv.cxsr = false;
4683                         intel_wait_for_vblank(dev, crtc->pipe);
4684                 }
4685         }
4686
4687         /*
4688          * IVB workaround: must disable low power watermarks for at least
4689          * one frame before enabling scaling.  LP watermarks can be re-enabled
4690          * when scaling is disabled.
4691          *
4692          * WaCxSRDisabledForSpriteScaling:ivb
4693          */
4694         if (pipe_config->disable_lp_wm) {
4695                 ilk_disable_lp_wm(dev);
4696                 intel_wait_for_vblank(dev, crtc->pipe);
4697         }
4698
4699         /*
4700          * If we're doing a modeset, we're done.  No need to do any pre-vblank
4701          * watermark programming here.
4702          */
4703         if (needs_modeset(&pipe_config->base))
4704                 return;
4705
4706         /*
4707          * For platforms that support atomic watermarks, program the
4708          * 'intermediate' watermarks immediately.  On pre-gen9 platforms, these
4709          * will be the intermediate values that are safe for both pre- and
4710          * post- vblank; when vblank happens, the 'active' values will be set
4711          * to the final 'target' values and we'll do this again to get the
4712          * optimal watermarks.  For gen9+ platforms, the values we program here
4713          * will be the final target values which will get automatically latched
4714          * at vblank time; no further programming will be necessary.
4715          *
4716          * If a platform hasn't been transitioned to atomic watermarks yet,
4717          * we'll continue to update watermarks the old way, if flags tell
4718          * us to.
4719          */
4720         if (dev_priv->display.initial_watermarks != NULL)
4721                 dev_priv->display.initial_watermarks(pipe_config);
4722         else if (pipe_config->update_wm_pre)
4723                 intel_update_watermarks(&crtc->base);
4724 }
4725
4726 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4727 {
4728         struct drm_device *dev = crtc->dev;
4729         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4730         struct drm_plane *p;
4731         int pipe = intel_crtc->pipe;
4732
4733         intel_crtc_dpms_overlay_disable(intel_crtc);
4734
4735         drm_for_each_plane_mask(p, dev, plane_mask)
4736                 to_intel_plane(p)->disable_plane(p, crtc);
4737
4738         /*
4739          * FIXME: Once we grow proper nuclear flip support out of this we need
4740          * to compute the mask of flip planes precisely. For the time being
4741          * consider this a flip to a NULL plane.
4742          */
4743         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4744 }
4745
4746 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4747 {
4748         struct drm_device *dev = crtc->dev;
4749         struct drm_i915_private *dev_priv = dev->dev_private;
4750         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4751         struct intel_encoder *encoder;
4752         int pipe = intel_crtc->pipe;
4753         struct intel_crtc_state *pipe_config =
4754                 to_intel_crtc_state(crtc->state);
4755
4756         if (WARN_ON(intel_crtc->active))
4757                 return;
4758
4759         /*
4760          * Sometimes spurious CPU pipe underruns happen during FDI
4761          * training, at least with VGA+HDMI cloning. Suppress them.
4762          *
4763          * On ILK we get an occasional spurious CPU pipe underruns
4764          * between eDP port A enable and vdd enable. Also PCH port
4765          * enable seems to result in the occasional CPU pipe underrun.
4766          *
4767          * Spurious PCH underruns also occur during PCH enabling.
4768          */
4769         if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
4770                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4771         if (intel_crtc->config->has_pch_encoder)
4772                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4773
4774         if (intel_crtc->config->has_pch_encoder)
4775                 intel_prepare_shared_dpll(intel_crtc);
4776
4777         if (intel_crtc->config->has_dp_encoder)
4778                 intel_dp_set_m_n(intel_crtc, M1_N1);
4779
4780         intel_set_pipe_timings(intel_crtc);
4781         intel_set_pipe_src_size(intel_crtc);
4782
4783         if (intel_crtc->config->has_pch_encoder) {
4784                 intel_cpu_transcoder_set_m_n(intel_crtc,
4785                                      &intel_crtc->config->fdi_m_n, NULL);
4786         }
4787
4788         ironlake_set_pipeconf(crtc);
4789
4790         intel_crtc->active = true;
4791
4792         for_each_encoder_on_crtc(dev, crtc, encoder)
4793                 if (encoder->pre_enable)
4794                         encoder->pre_enable(encoder);
4795
4796         if (intel_crtc->config->has_pch_encoder) {
4797                 /* Note: FDI PLL enabling _must_ be done before we enable the
4798                  * cpu pipes, hence this is separate from all the other fdi/pch
4799                  * enabling. */
4800                 ironlake_fdi_pll_enable(intel_crtc);
4801         } else {
4802                 assert_fdi_tx_disabled(dev_priv, pipe);
4803                 assert_fdi_rx_disabled(dev_priv, pipe);
4804         }
4805
4806         ironlake_pfit_enable(intel_crtc);
4807
4808         /*
4809          * On ILK+ LUT must be loaded before the pipe is running but with
4810          * clocks enabled
4811          */
4812         intel_color_load_luts(&pipe_config->base);
4813
4814         if (dev_priv->display.initial_watermarks != NULL)
4815                 dev_priv->display.initial_watermarks(intel_crtc->config);
4816         intel_enable_pipe(intel_crtc);
4817
4818         if (intel_crtc->config->has_pch_encoder)
4819                 ironlake_pch_enable(crtc);
4820
4821         assert_vblank_disabled(crtc);
4822         drm_crtc_vblank_on(crtc);
4823
4824         for_each_encoder_on_crtc(dev, crtc, encoder)
4825                 encoder->enable(encoder);
4826
4827         if (HAS_PCH_CPT(dev))
4828                 cpt_verify_modeset(dev, intel_crtc->pipe);
4829
4830         /* Must wait for vblank to avoid spurious PCH FIFO underruns */
4831         if (intel_crtc->config->has_pch_encoder)
4832                 intel_wait_for_vblank(dev, pipe);
4833         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4834         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4835 }
4836
4837 /* IPS only exists on ULT machines and is tied to pipe A. */
4838 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4839 {
4840         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4841 }
4842
4843 static void haswell_crtc_enable(struct drm_crtc *crtc)
4844 {
4845         struct drm_device *dev = crtc->dev;
4846         struct drm_i915_private *dev_priv = dev->dev_private;
4847         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4848         struct intel_encoder *encoder;
4849         int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4850         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4851         struct intel_crtc_state *pipe_config =
4852                 to_intel_crtc_state(crtc->state);
4853
4854         if (WARN_ON(intel_crtc->active))
4855                 return;
4856
4857         if (intel_crtc->config->has_pch_encoder)
4858                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4859                                                       false);
4860
4861         for_each_encoder_on_crtc(dev, crtc, encoder)
4862                 if (encoder->pre_pll_enable)
4863                         encoder->pre_pll_enable(encoder);
4864
4865         if (intel_crtc->config->shared_dpll)
4866                 intel_enable_shared_dpll(intel_crtc);
4867
4868         if (intel_crtc->config->has_dp_encoder)
4869                 intel_dp_set_m_n(intel_crtc, M1_N1);
4870
4871         if (!intel_crtc->config->has_dsi_encoder)
4872                 intel_set_pipe_timings(intel_crtc);
4873
4874         intel_set_pipe_src_size(intel_crtc);
4875
4876         if (cpu_transcoder != TRANSCODER_EDP &&
4877             !transcoder_is_dsi(cpu_transcoder)) {
4878                 I915_WRITE(PIPE_MULT(cpu_transcoder),
4879                            intel_crtc->config->pixel_multiplier - 1);
4880         }
4881
4882         if (intel_crtc->config->has_pch_encoder) {
4883                 intel_cpu_transcoder_set_m_n(intel_crtc,
4884                                      &intel_crtc->config->fdi_m_n, NULL);
4885         }
4886
4887         if (!intel_crtc->config->has_dsi_encoder)
4888                 haswell_set_pipeconf(crtc);
4889
4890         haswell_set_pipemisc(crtc);
4891
4892         intel_color_set_csc(&pipe_config->base);
4893
4894         intel_crtc->active = true;
4895
4896         if (intel_crtc->config->has_pch_encoder)
4897                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4898         else
4899                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4900
4901         for_each_encoder_on_crtc(dev, crtc, encoder) {
4902                 if (encoder->pre_enable)
4903                         encoder->pre_enable(encoder);
4904         }
4905
4906         if (intel_crtc->config->has_pch_encoder)
4907                 dev_priv->display.fdi_link_train(crtc);
4908
4909         if (!intel_crtc->config->has_dsi_encoder)
4910                 intel_ddi_enable_pipe_clock(intel_crtc);
4911
4912         if (INTEL_INFO(dev)->gen >= 9)
4913                 skylake_pfit_enable(intel_crtc);
4914         else
4915                 ironlake_pfit_enable(intel_crtc);
4916
4917         /*
4918          * On ILK+ LUT must be loaded before the pipe is running but with
4919          * clocks enabled
4920          */
4921         intel_color_load_luts(&pipe_config->base);
4922
4923         intel_ddi_set_pipe_settings(crtc);
4924         if (!intel_crtc->config->has_dsi_encoder)
4925                 intel_ddi_enable_transcoder_func(crtc);
4926
4927         if (dev_priv->display.initial_watermarks != NULL)
4928                 dev_priv->display.initial_watermarks(pipe_config);
4929         else
4930                 intel_update_watermarks(crtc);
4931
4932         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
4933         if (!intel_crtc->config->has_dsi_encoder)
4934                 intel_enable_pipe(intel_crtc);
4935
4936         if (intel_crtc->config->has_pch_encoder)
4937                 lpt_pch_enable(crtc);
4938
4939         if (intel_crtc->config->dp_encoder_is_mst)
4940                 intel_ddi_set_vc_payload_alloc(crtc, true);
4941
4942         assert_vblank_disabled(crtc);
4943         drm_crtc_vblank_on(crtc);
4944
4945         for_each_encoder_on_crtc(dev, crtc, encoder) {
4946                 encoder->enable(encoder);
4947                 intel_opregion_notify_encoder(encoder, true);
4948         }
4949
4950         if (intel_crtc->config->has_pch_encoder) {
4951                 intel_wait_for_vblank(dev, pipe);
4952                 intel_wait_for_vblank(dev, pipe);
4953                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4954                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4955                                                       true);
4956         }
4957
4958         /* If we change the relative order between pipe/planes enabling, we need
4959          * to change the workaround. */
4960         hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
4961         if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
4962                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4963                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4964         }
4965 }
4966
4967 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
4968 {
4969         struct drm_device *dev = crtc->base.dev;
4970         struct drm_i915_private *dev_priv = dev->dev_private;
4971         int pipe = crtc->pipe;
4972
4973         /* To avoid upsetting the power well on haswell only disable the pfit if
4974          * it's in use. The hw state code will make sure we get this right. */
4975         if (force || crtc->config->pch_pfit.enabled) {
4976                 I915_WRITE(PF_CTL(pipe), 0);
4977                 I915_WRITE(PF_WIN_POS(pipe), 0);
4978                 I915_WRITE(PF_WIN_SZ(pipe), 0);
4979         }
4980 }
4981
4982 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4983 {
4984         struct drm_device *dev = crtc->dev;
4985         struct drm_i915_private *dev_priv = dev->dev_private;
4986         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4987         struct intel_encoder *encoder;
4988         int pipe = intel_crtc->pipe;
4989
4990         /*
4991          * Sometimes spurious CPU pipe underruns happen when the
4992          * pipe is already disabled, but FDI RX/TX is still enabled.
4993          * Happens at least with VGA+HDMI cloning. Suppress them.
4994          */
4995         if (intel_crtc->config->has_pch_encoder) {
4996                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4997                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4998         }
4999
5000         for_each_encoder_on_crtc(dev, crtc, encoder)
5001                 encoder->disable(encoder);
5002
5003         drm_crtc_vblank_off(crtc);
5004         assert_vblank_disabled(crtc);
5005
5006         intel_disable_pipe(intel_crtc);
5007
5008         ironlake_pfit_disable(intel_crtc, false);
5009
5010         if (intel_crtc->config->has_pch_encoder)
5011                 ironlake_fdi_disable(crtc);
5012
5013         for_each_encoder_on_crtc(dev, crtc, encoder)
5014                 if (encoder->post_disable)
5015                         encoder->post_disable(encoder);
5016
5017         if (intel_crtc->config->has_pch_encoder) {
5018                 ironlake_disable_pch_transcoder(dev_priv, pipe);
5019
5020                 if (HAS_PCH_CPT(dev)) {
5021                         i915_reg_t reg;
5022                         u32 temp;
5023
5024                         /* disable TRANS_DP_CTL */
5025                         reg = TRANS_DP_CTL(pipe);
5026                         temp = I915_READ(reg);
5027                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5028                                   TRANS_DP_PORT_SEL_MASK);
5029                         temp |= TRANS_DP_PORT_SEL_NONE;
5030                         I915_WRITE(reg, temp);
5031
5032                         /* disable DPLL_SEL */
5033                         temp = I915_READ(PCH_DPLL_SEL);
5034                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5035                         I915_WRITE(PCH_DPLL_SEL, temp);
5036                 }
5037
5038                 ironlake_fdi_pll_disable(intel_crtc);
5039         }
5040
5041         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5042         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5043 }
5044
5045 static void haswell_crtc_disable(struct drm_crtc *crtc)
5046 {
5047         struct drm_device *dev = crtc->dev;
5048         struct drm_i915_private *dev_priv = dev->dev_private;
5049         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5050         struct intel_encoder *encoder;
5051         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5052
5053         if (intel_crtc->config->has_pch_encoder)
5054                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5055                                                       false);
5056
5057         for_each_encoder_on_crtc(dev, crtc, encoder) {
5058                 intel_opregion_notify_encoder(encoder, false);
5059                 encoder->disable(encoder);
5060         }
5061
5062         drm_crtc_vblank_off(crtc);
5063         assert_vblank_disabled(crtc);
5064
5065         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5066         if (!intel_crtc->config->has_dsi_encoder)
5067                 intel_disable_pipe(intel_crtc);
5068
5069         if (intel_crtc->config->dp_encoder_is_mst)
5070                 intel_ddi_set_vc_payload_alloc(crtc, false);
5071
5072         if (!intel_crtc->config->has_dsi_encoder)
5073                 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5074
5075         if (INTEL_INFO(dev)->gen >= 9)
5076                 skylake_scaler_disable(intel_crtc);
5077         else
5078                 ironlake_pfit_disable(intel_crtc, false);
5079
5080         if (!intel_crtc->config->has_dsi_encoder)
5081                 intel_ddi_disable_pipe_clock(intel_crtc);
5082
5083         for_each_encoder_on_crtc(dev, crtc, encoder)
5084                 if (encoder->post_disable)
5085                         encoder->post_disable(encoder);
5086
5087         if (intel_crtc->config->has_pch_encoder) {
5088                 lpt_disable_pch_transcoder(dev_priv);
5089                 lpt_disable_iclkip(dev_priv);
5090                 intel_ddi_fdi_disable(crtc);
5091
5092                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5093                                                       true);
5094         }
5095 }
5096
5097 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5098 {
5099         struct drm_device *dev = crtc->base.dev;
5100         struct drm_i915_private *dev_priv = dev->dev_private;
5101         struct intel_crtc_state *pipe_config = crtc->config;
5102
5103         if (!pipe_config->gmch_pfit.control)
5104                 return;
5105
5106         /*
5107          * The panel fitter should only be adjusted whilst the pipe is disabled,
5108          * according to register description and PRM.
5109          */
5110         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5111         assert_pipe_disabled(dev_priv, crtc->pipe);
5112
5113         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5114         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5115
5116         /* Border color in case we don't scale up to the full screen. Black by
5117          * default, change to something else for debugging. */
5118         I915_WRITE(BCLRPAT(crtc->pipe), 0);
5119 }
5120
5121 static enum intel_display_power_domain port_to_power_domain(enum port port)
5122 {
5123         switch (port) {
5124         case PORT_A:
5125                 return POWER_DOMAIN_PORT_DDI_A_LANES;
5126         case PORT_B:
5127                 return POWER_DOMAIN_PORT_DDI_B_LANES;
5128         case PORT_C:
5129                 return POWER_DOMAIN_PORT_DDI_C_LANES;
5130         case PORT_D:
5131                 return POWER_DOMAIN_PORT_DDI_D_LANES;
5132         case PORT_E:
5133                 return POWER_DOMAIN_PORT_DDI_E_LANES;
5134         default:
5135                 MISSING_CASE(port);
5136                 return POWER_DOMAIN_PORT_OTHER;
5137         }
5138 }
5139
5140 static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
5141 {
5142         switch (port) {
5143         case PORT_A:
5144                 return POWER_DOMAIN_AUX_A;
5145         case PORT_B:
5146                 return POWER_DOMAIN_AUX_B;
5147         case PORT_C:
5148                 return POWER_DOMAIN_AUX_C;
5149         case PORT_D:
5150                 return POWER_DOMAIN_AUX_D;
5151         case PORT_E:
5152                 /* FIXME: Check VBT for actual wiring of PORT E */
5153                 return POWER_DOMAIN_AUX_D;
5154         default:
5155                 MISSING_CASE(port);
5156                 return POWER_DOMAIN_AUX_A;
5157         }
5158 }
5159
5160 enum intel_display_power_domain
5161 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5162 {
5163         struct drm_device *dev = intel_encoder->base.dev;
5164         struct intel_digital_port *intel_dig_port;
5165
5166         switch (intel_encoder->type) {
5167         case INTEL_OUTPUT_UNKNOWN:
5168                 /* Only DDI platforms should ever use this output type */
5169                 WARN_ON_ONCE(!HAS_DDI(dev));
5170         case INTEL_OUTPUT_DISPLAYPORT:
5171         case INTEL_OUTPUT_HDMI:
5172         case INTEL_OUTPUT_EDP:
5173                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5174                 return port_to_power_domain(intel_dig_port->port);
5175         case INTEL_OUTPUT_DP_MST:
5176                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5177                 return port_to_power_domain(intel_dig_port->port);
5178         case INTEL_OUTPUT_ANALOG:
5179                 return POWER_DOMAIN_PORT_CRT;
5180         case INTEL_OUTPUT_DSI:
5181                 return POWER_DOMAIN_PORT_DSI;
5182         default:
5183                 return POWER_DOMAIN_PORT_OTHER;
5184         }
5185 }
5186
5187 enum intel_display_power_domain
5188 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
5189 {
5190         struct drm_device *dev = intel_encoder->base.dev;
5191         struct intel_digital_port *intel_dig_port;
5192
5193         switch (intel_encoder->type) {
5194         case INTEL_OUTPUT_UNKNOWN:
5195         case INTEL_OUTPUT_HDMI:
5196                 /*
5197                  * Only DDI platforms should ever use these output types.
5198                  * We can get here after the HDMI detect code has already set
5199                  * the type of the shared encoder. Since we can't be sure
5200                  * what's the status of the given connectors, play safe and
5201                  * run the DP detection too.
5202                  */
5203                 WARN_ON_ONCE(!HAS_DDI(dev));
5204         case INTEL_OUTPUT_DISPLAYPORT:
5205         case INTEL_OUTPUT_EDP:
5206                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5207                 return port_to_aux_power_domain(intel_dig_port->port);
5208         case INTEL_OUTPUT_DP_MST:
5209                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5210                 return port_to_aux_power_domain(intel_dig_port->port);
5211         default:
5212                 MISSING_CASE(intel_encoder->type);
5213                 return POWER_DOMAIN_AUX_A;
5214         }
5215 }
5216
5217 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc,
5218                                             struct intel_crtc_state *crtc_state)
5219 {
5220         struct drm_device *dev = crtc->dev;
5221         struct drm_encoder *encoder;
5222         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5223         enum pipe pipe = intel_crtc->pipe;
5224         unsigned long mask;
5225         enum transcoder transcoder = crtc_state->cpu_transcoder;
5226
5227         if (!crtc_state->base.active)
5228                 return 0;
5229
5230         mask = BIT(POWER_DOMAIN_PIPE(pipe));
5231         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5232         if (crtc_state->pch_pfit.enabled ||
5233             crtc_state->pch_pfit.force_thru)
5234                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5235
5236         drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5237                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5238
5239                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5240         }
5241
5242         if (crtc_state->shared_dpll)
5243                 mask |= BIT(POWER_DOMAIN_PLLS);
5244
5245         return mask;
5246 }
5247
5248 static unsigned long
5249 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5250                                struct intel_crtc_state *crtc_state)
5251 {
5252         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5253         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5254         enum intel_display_power_domain domain;
5255         unsigned long domains, new_domains, old_domains;
5256
5257         old_domains = intel_crtc->enabled_power_domains;
5258         intel_crtc->enabled_power_domains = new_domains =
5259                 get_crtc_power_domains(crtc, crtc_state);
5260
5261         domains = new_domains & ~old_domains;
5262
5263         for_each_power_domain(domain, domains)
5264                 intel_display_power_get(dev_priv, domain);
5265
5266         return old_domains & ~new_domains;
5267 }
5268
5269 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5270                                       unsigned long domains)
5271 {
5272         enum intel_display_power_domain domain;
5273
5274         for_each_power_domain(domain, domains)
5275                 intel_display_power_put(dev_priv, domain);
5276 }
5277
5278 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5279 {
5280         int max_cdclk_freq = dev_priv->max_cdclk_freq;
5281
5282         if (INTEL_INFO(dev_priv)->gen >= 9 ||
5283             IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5284                 return max_cdclk_freq;
5285         else if (IS_CHERRYVIEW(dev_priv))
5286                 return max_cdclk_freq*95/100;
5287         else if (INTEL_INFO(dev_priv)->gen < 4)
5288                 return 2*max_cdclk_freq*90/100;
5289         else
5290                 return max_cdclk_freq*90/100;
5291 }
5292
5293 static int skl_calc_cdclk(int max_pixclk, int vco);
5294
5295 static void intel_update_max_cdclk(struct drm_device *dev)
5296 {
5297         struct drm_i915_private *dev_priv = dev->dev_private;
5298
5299         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
5300                 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5301                 int max_cdclk, vco;
5302
5303                 vco = dev_priv->skl_preferred_vco_freq;
5304                 WARN_ON(vco != 8100000 && vco != 8640000);
5305
5306                 /*
5307                  * Use the lower (vco 8640) cdclk values as a
5308                  * first guess. skl_calc_cdclk() will correct it
5309                  * if the preferred vco is 8100 instead.
5310                  */
5311                 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5312                         max_cdclk = 617143;
5313                 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5314                         max_cdclk = 540000;
5315                 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5316                         max_cdclk = 432000;
5317                 else
5318                         max_cdclk = 308571;
5319
5320                 dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
5321         } else if (IS_BROXTON(dev)) {
5322                 dev_priv->max_cdclk_freq = 624000;
5323         } else if (IS_BROADWELL(dev))  {
5324                 /*
5325                  * FIXME with extra cooling we can allow
5326                  * 540 MHz for ULX and 675 Mhz for ULT.
5327                  * How can we know if extra cooling is
5328                  * available? PCI ID, VTB, something else?
5329                  */
5330                 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5331                         dev_priv->max_cdclk_freq = 450000;
5332                 else if (IS_BDW_ULX(dev))
5333                         dev_priv->max_cdclk_freq = 450000;
5334                 else if (IS_BDW_ULT(dev))
5335                         dev_priv->max_cdclk_freq = 540000;
5336                 else
5337                         dev_priv->max_cdclk_freq = 675000;
5338         } else if (IS_CHERRYVIEW(dev)) {
5339                 dev_priv->max_cdclk_freq = 320000;
5340         } else if (IS_VALLEYVIEW(dev)) {
5341                 dev_priv->max_cdclk_freq = 400000;
5342         } else {
5343                 /* otherwise assume cdclk is fixed */
5344                 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5345         }
5346
5347         dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5348
5349         DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5350                          dev_priv->max_cdclk_freq);
5351
5352         DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5353                          dev_priv->max_dotclk_freq);
5354 }
5355
5356 static void intel_update_cdclk(struct drm_device *dev)
5357 {
5358         struct drm_i915_private *dev_priv = dev->dev_private;
5359
5360         dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5361
5362         if (INTEL_GEN(dev_priv) >= 9)
5363                 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz, ref: %d kHz\n",
5364                                  dev_priv->cdclk_freq, dev_priv->cdclk_pll.vco,
5365                                  dev_priv->cdclk_pll.ref);
5366         else
5367                 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5368                                  dev_priv->cdclk_freq);
5369
5370         /*
5371          * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
5372          * Programmng [sic] note: bit[9:2] should be programmed to the number
5373          * of cdclk that generates 4MHz reference clock freq which is used to
5374          * generate GMBus clock. This will vary with the cdclk freq.
5375          */
5376         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5377                 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5378 }
5379
5380 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5381 static int skl_cdclk_decimal(int cdclk)
5382 {
5383         return DIV_ROUND_CLOSEST(cdclk - 1000, 500);
5384 }
5385
5386 static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
5387 {
5388         int ratio;
5389
5390         if (cdclk == dev_priv->cdclk_pll.ref)
5391                 return 0;
5392
5393         switch (cdclk) {
5394         default:
5395                 MISSING_CASE(cdclk);
5396         case 144000:
5397         case 288000:
5398         case 384000:
5399         case 576000:
5400                 ratio = 60;
5401                 break;
5402         case 624000:
5403                 ratio = 65;
5404                 break;
5405         }
5406
5407         return dev_priv->cdclk_pll.ref * ratio;
5408 }
5409
5410 static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
5411 {
5412         I915_WRITE(BXT_DE_PLL_ENABLE, 0);
5413
5414         /* Timeout 200us */
5415         if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) == 0, 1))
5416                 DRM_ERROR("timeout waiting for DE PLL unlock\n");
5417
5418         dev_priv->cdclk_pll.vco = 0;
5419 }
5420
5421 static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)
5422 {
5423         int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk_pll.ref);
5424         u32 val;
5425
5426         val = I915_READ(BXT_DE_PLL_CTL);
5427         val &= ~BXT_DE_PLL_RATIO_MASK;
5428         val |= BXT_DE_PLL_RATIO(ratio);
5429         I915_WRITE(BXT_DE_PLL_CTL, val);
5430
5431         I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5432
5433         /* Timeout 200us */
5434         if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) != 0, 1))
5435                 DRM_ERROR("timeout waiting for DE PLL lock\n");
5436
5437         dev_priv->cdclk_pll.vco = vco;
5438 }
5439
5440 static void bxt_set_cdclk(struct drm_i915_private *dev_priv, int cdclk)
5441 {
5442         u32 val, divider;
5443         int vco, ret;
5444
5445         vco = bxt_de_pll_vco(dev_priv, cdclk);
5446
5447         DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco);
5448
5449         /* cdclk = vco / 2 / div{1,1.5,2,4} */
5450         switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
5451         case 8:
5452                 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5453                 break;
5454         case 4:
5455                 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5456                 break;
5457         case 3:
5458                 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5459                 break;
5460         case 2:
5461                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5462                 break;
5463         default:
5464                 WARN_ON(cdclk != dev_priv->cdclk_pll.ref);
5465                 WARN_ON(vco != 0);
5466
5467                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5468                 break;
5469         }
5470
5471         /* Inform power controller of upcoming frequency change */
5472         mutex_lock(&dev_priv->rps.hw_lock);
5473         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5474                                       0x80000000);
5475         mutex_unlock(&dev_priv->rps.hw_lock);
5476
5477         if (ret) {
5478                 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5479                           ret, cdclk);
5480                 return;
5481         }
5482
5483         if (dev_priv->cdclk_pll.vco != 0 &&
5484             dev_priv->cdclk_pll.vco != vco)
5485                 bxt_de_pll_disable(dev_priv);
5486
5487         if (dev_priv->cdclk_pll.vco != vco)
5488                 bxt_de_pll_enable(dev_priv, vco);
5489
5490         val = divider | skl_cdclk_decimal(cdclk);
5491         /*
5492          * FIXME if only the cd2x divider needs changing, it could be done
5493          * without shutting off the pipe (if only one pipe is active).
5494          */
5495         val |= BXT_CDCLK_CD2X_PIPE_NONE;
5496         /*
5497          * Disable SSA Precharge when CD clock frequency < 500 MHz,
5498          * enable otherwise.
5499          */
5500         if (cdclk >= 500000)
5501                 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5502         I915_WRITE(CDCLK_CTL, val);
5503
5504         mutex_lock(&dev_priv->rps.hw_lock);
5505         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5506                                       DIV_ROUND_UP(cdclk, 25000));
5507         mutex_unlock(&dev_priv->rps.hw_lock);
5508
5509         if (ret) {
5510                 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5511                           ret, cdclk);
5512                 return;
5513         }
5514
5515         intel_update_cdclk(dev_priv->dev);
5516 }
5517
5518 static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
5519 {
5520         u32 cdctl, expected;
5521
5522         intel_update_cdclk(dev_priv->dev);
5523
5524         if (dev_priv->cdclk_pll.vco == 0 ||
5525             dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref)
5526                 goto sanitize;
5527
5528         /* DPLL okay; verify the cdclock
5529          *
5530          * Some BIOS versions leave an incorrect decimal frequency value and
5531          * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
5532          * so sanitize this register.
5533          */
5534         cdctl = I915_READ(CDCLK_CTL);
5535         /*
5536          * Let's ignore the pipe field, since BIOS could have configured the
5537          * dividers both synching to an active pipe, or asynchronously
5538          * (PIPE_NONE).
5539          */
5540         cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
5541
5542         expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) |
5543                    skl_cdclk_decimal(dev_priv->cdclk_freq);
5544         /*
5545          * Disable SSA Precharge when CD clock frequency < 500 MHz,
5546          * enable otherwise.
5547          */
5548         if (dev_priv->cdclk_freq >= 500000)
5549                 expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5550
5551         if (cdctl == expected)
5552                 /* All well; nothing to sanitize */
5553                 return;
5554
5555 sanitize:
5556         DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
5557
5558         /* force cdclk programming */
5559         dev_priv->cdclk_freq = 0;
5560
5561         /* force full PLL disable + enable */
5562         dev_priv->cdclk_pll.vco = -1;
5563 }
5564
5565 void bxt_init_cdclk(struct drm_i915_private *dev_priv)
5566 {
5567         bxt_sanitize_cdclk(dev_priv);
5568
5569         if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0)
5570                 return;
5571
5572         /*
5573          * FIXME:
5574          * - The initial CDCLK needs to be read from VBT.
5575          *   Need to make this change after VBT has changes for BXT.
5576          */
5577         bxt_set_cdclk(dev_priv, bxt_calc_cdclk(0));
5578 }
5579
5580 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
5581 {
5582         bxt_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref);
5583 }
5584
5585 static int skl_calc_cdclk(int max_pixclk, int vco)
5586 {
5587         if (vco == 8640000) {
5588                 if (max_pixclk > 540000)
5589                         return 617143;
5590                 else if (max_pixclk > 432000)
5591                         return 540000;
5592                 else if (max_pixclk > 308571)
5593                         return 432000;
5594                 else
5595                         return 308571;
5596         } else {
5597                 if (max_pixclk > 540000)
5598                         return 675000;
5599                 else if (max_pixclk > 450000)
5600                         return 540000;
5601                 else if (max_pixclk > 337500)
5602                         return 450000;
5603                 else
5604                         return 337500;
5605         }
5606 }
5607
5608 static void
5609 skl_dpll0_update(struct drm_i915_private *dev_priv)
5610 {
5611         u32 val;
5612
5613         dev_priv->cdclk_pll.ref = 24000;
5614         dev_priv->cdclk_pll.vco = 0;
5615
5616         val = I915_READ(LCPLL1_CTL);
5617         if ((val & LCPLL_PLL_ENABLE) == 0)
5618                 return;
5619
5620         if (WARN_ON((val & LCPLL_PLL_LOCK) == 0))
5621                 return;
5622
5623         val = I915_READ(DPLL_CTRL1);
5624
5625         if (WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
5626                             DPLL_CTRL1_SSC(SKL_DPLL0) |
5627                             DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=
5628                     DPLL_CTRL1_OVERRIDE(SKL_DPLL0)))
5629                 return;
5630
5631         switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) {
5632         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0):
5633         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0):
5634         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0):
5635         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0):
5636                 dev_priv->cdclk_pll.vco = 8100000;
5637                 break;
5638         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0):
5639         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0):
5640                 dev_priv->cdclk_pll.vco = 8640000;
5641                 break;
5642         default:
5643                 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5644                 break;
5645         }
5646 }
5647
5648 void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, int vco)
5649 {
5650         bool changed = dev_priv->skl_preferred_vco_freq != vco;
5651
5652         dev_priv->skl_preferred_vco_freq = vco;
5653
5654         if (changed)
5655                 intel_update_max_cdclk(dev_priv->dev);
5656 }
5657
5658 static void
5659 skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
5660 {
5661         int min_cdclk = skl_calc_cdclk(0, vco);
5662         u32 val;
5663
5664         WARN_ON(vco != 8100000 && vco != 8640000);
5665
5666         /* select the minimum CDCLK before enabling DPLL 0 */
5667         val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_cdclk);
5668         I915_WRITE(CDCLK_CTL, val);
5669         POSTING_READ(CDCLK_CTL);
5670
5671         /*
5672          * We always enable DPLL0 with the lowest link rate possible, but still
5673          * taking into account the VCO required to operate the eDP panel at the
5674          * desired frequency. The usual DP link rates operate with a VCO of
5675          * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5676          * The modeset code is responsible for the selection of the exact link
5677          * rate later on, with the constraint of choosing a frequency that
5678          * works with vco.
5679          */
5680         val = I915_READ(DPLL_CTRL1);
5681
5682         val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5683                  DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5684         val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5685         if (vco == 8640000)
5686                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5687                                             SKL_DPLL0);
5688         else
5689                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5690                                             SKL_DPLL0);
5691
5692         I915_WRITE(DPLL_CTRL1, val);
5693         POSTING_READ(DPLL_CTRL1);
5694
5695         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5696
5697         if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5698                 DRM_ERROR("DPLL0 not locked\n");
5699
5700         dev_priv->cdclk_pll.vco = vco;
5701
5702         /* We'll want to keep using the current vco from now on. */
5703         skl_set_preferred_cdclk_vco(dev_priv, vco);
5704 }
5705
5706 static void
5707 skl_dpll0_disable(struct drm_i915_private *dev_priv)
5708 {
5709         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5710         if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5711                 DRM_ERROR("Couldn't disable DPLL0\n");
5712
5713         dev_priv->cdclk_pll.vco = 0;
5714 }
5715
5716 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5717 {
5718         int ret;
5719         u32 val;
5720
5721         /* inform PCU we want to change CDCLK */
5722         val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5723         mutex_lock(&dev_priv->rps.hw_lock);
5724         ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5725         mutex_unlock(&dev_priv->rps.hw_lock);
5726
5727         return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5728 }
5729
5730 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5731 {
5732         unsigned int i;
5733
5734         for (i = 0; i < 15; i++) {
5735                 if (skl_cdclk_pcu_ready(dev_priv))
5736                         return true;
5737                 udelay(10);
5738         }
5739
5740         return false;
5741 }
5742
5743 static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk, int vco)
5744 {
5745         struct drm_device *dev = dev_priv->dev;
5746         u32 freq_select, pcu_ack;
5747
5748         WARN_ON((cdclk == 24000) != (vco == 0));
5749
5750         DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco);
5751
5752         if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5753                 DRM_ERROR("failed to inform PCU about cdclk change\n");
5754                 return;
5755         }
5756
5757         /* set CDCLK_CTL */
5758         switch (cdclk) {
5759         case 450000:
5760         case 432000:
5761                 freq_select = CDCLK_FREQ_450_432;
5762                 pcu_ack = 1;
5763                 break;
5764         case 540000:
5765                 freq_select = CDCLK_FREQ_540;
5766                 pcu_ack = 2;
5767                 break;
5768         case 308571:
5769         case 337500:
5770         default:
5771                 freq_select = CDCLK_FREQ_337_308;
5772                 pcu_ack = 0;
5773                 break;
5774         case 617143:
5775         case 675000:
5776                 freq_select = CDCLK_FREQ_675_617;
5777                 pcu_ack = 3;
5778                 break;
5779         }
5780
5781         if (dev_priv->cdclk_pll.vco != 0 &&
5782             dev_priv->cdclk_pll.vco != vco)
5783                 skl_dpll0_disable(dev_priv);
5784
5785         if (dev_priv->cdclk_pll.vco != vco)
5786                 skl_dpll0_enable(dev_priv, vco);
5787
5788         I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(cdclk));
5789         POSTING_READ(CDCLK_CTL);
5790
5791         /* inform PCU of the change */
5792         mutex_lock(&dev_priv->rps.hw_lock);
5793         sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5794         mutex_unlock(&dev_priv->rps.hw_lock);
5795
5796         intel_update_cdclk(dev);
5797 }
5798
5799 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
5800
5801 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5802 {
5803         skl_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref, 0);
5804 }
5805
5806 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5807 {
5808         int cdclk, vco;
5809
5810         skl_sanitize_cdclk(dev_priv);
5811
5812         if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0) {
5813                 /*
5814                  * Use the current vco as our initial
5815                  * guess as to what the preferred vco is.
5816                  */
5817                 if (dev_priv->skl_preferred_vco_freq == 0)
5818                         skl_set_preferred_cdclk_vco(dev_priv,
5819                                                     dev_priv->cdclk_pll.vco);
5820                 return;
5821         }
5822
5823         vco = dev_priv->skl_preferred_vco_freq;
5824         if (vco == 0)
5825                 vco = 8100000;
5826         cdclk = skl_calc_cdclk(0, vco);
5827
5828         skl_set_cdclk(dev_priv, cdclk, vco);
5829 }
5830
5831 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
5832 {
5833         uint32_t cdctl, expected;
5834
5835         /*
5836          * check if the pre-os intialized the display
5837          * There is SWF18 scratchpad register defined which is set by the
5838          * pre-os which can be used by the OS drivers to check the status
5839          */
5840         if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
5841                 goto sanitize;
5842
5843         intel_update_cdclk(dev_priv->dev);
5844         /* Is PLL enabled and locked ? */
5845         if (dev_priv->cdclk_pll.vco == 0 ||
5846             dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref)
5847                 goto sanitize;
5848
5849         /* DPLL okay; verify the cdclock
5850          *
5851          * Noticed in some instances that the freq selection is correct but
5852          * decimal part is programmed wrong from BIOS where pre-os does not
5853          * enable display. Verify the same as well.
5854          */
5855         cdctl = I915_READ(CDCLK_CTL);
5856         expected = (cdctl & CDCLK_FREQ_SEL_MASK) |
5857                 skl_cdclk_decimal(dev_priv->cdclk_freq);
5858         if (cdctl == expected)
5859                 /* All well; nothing to sanitize */
5860                 return;
5861
5862 sanitize:
5863         DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
5864
5865         /* force cdclk programming */
5866         dev_priv->cdclk_freq = 0;
5867         /* force full PLL disable + enable */
5868         dev_priv->cdclk_pll.vco = -1;
5869 }
5870
5871 /* Adjust CDclk dividers to allow high res or save power if possible */
5872 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5873 {
5874         struct drm_i915_private *dev_priv = dev->dev_private;
5875         u32 val, cmd;
5876
5877         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5878                                         != dev_priv->cdclk_freq);
5879
5880         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5881                 cmd = 2;
5882         else if (cdclk == 266667)
5883                 cmd = 1;
5884         else
5885                 cmd = 0;
5886
5887         mutex_lock(&dev_priv->rps.hw_lock);
5888         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5889         val &= ~DSPFREQGUAR_MASK;
5890         val |= (cmd << DSPFREQGUAR_SHIFT);
5891         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5892         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5893                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5894                      50)) {
5895                 DRM_ERROR("timed out waiting for CDclk change\n");
5896         }
5897         mutex_unlock(&dev_priv->rps.hw_lock);
5898
5899         mutex_lock(&dev_priv->sb_lock);
5900
5901         if (cdclk == 400000) {
5902                 u32 divider;
5903
5904                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5905
5906                 /* adjust cdclk divider */
5907                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5908                 val &= ~CCK_FREQUENCY_VALUES;
5909                 val |= divider;
5910                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5911
5912                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5913                               CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
5914                              50))
5915                         DRM_ERROR("timed out waiting for CDclk change\n");
5916         }
5917
5918         /* adjust self-refresh exit latency value */
5919         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5920         val &= ~0x7f;
5921
5922         /*
5923          * For high bandwidth configs, we set a higher latency in the bunit
5924          * so that the core display fetch happens in time to avoid underruns.
5925          */
5926         if (cdclk == 400000)
5927                 val |= 4500 / 250; /* 4.5 usec */
5928         else
5929                 val |= 3000 / 250; /* 3.0 usec */
5930         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5931
5932         mutex_unlock(&dev_priv->sb_lock);
5933
5934         intel_update_cdclk(dev);
5935 }
5936
5937 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5938 {
5939         struct drm_i915_private *dev_priv = dev->dev_private;
5940         u32 val, cmd;
5941
5942         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5943                                                 != dev_priv->cdclk_freq);
5944
5945         switch (cdclk) {
5946         case 333333:
5947         case 320000:
5948         case 266667:
5949         case 200000:
5950                 break;
5951         default:
5952                 MISSING_CASE(cdclk);
5953                 return;
5954         }
5955
5956         /*
5957          * Specs are full of misinformation, but testing on actual
5958          * hardware has shown that we just need to write the desired
5959          * CCK divider into the Punit register.
5960          */
5961         cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5962
5963         mutex_lock(&dev_priv->rps.hw_lock);
5964         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5965         val &= ~DSPFREQGUAR_MASK_CHV;
5966         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5967         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5968         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5969                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5970                      50)) {
5971                 DRM_ERROR("timed out waiting for CDclk change\n");
5972         }
5973         mutex_unlock(&dev_priv->rps.hw_lock);
5974
5975         intel_update_cdclk(dev);
5976 }
5977
5978 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5979                                  int max_pixclk)
5980 {
5981         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
5982         int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5983
5984         /*
5985          * Really only a few cases to deal with, as only 4 CDclks are supported:
5986          *   200MHz
5987          *   267MHz
5988          *   320/333MHz (depends on HPLL freq)
5989          *   400MHz (VLV only)
5990          * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5991          * of the lower bin and adjust if needed.
5992          *
5993          * We seem to get an unstable or solid color picture at 200MHz.
5994          * Not sure what's wrong. For now use 200MHz only when all pipes
5995          * are off.
5996          */
5997         if (!IS_CHERRYVIEW(dev_priv) &&
5998             max_pixclk > freq_320*limit/100)
5999                 return 400000;
6000         else if (max_pixclk > 266667*limit/100)
6001                 return freq_320;
6002         else if (max_pixclk > 0)
6003                 return 266667;
6004         else
6005                 return 200000;
6006 }
6007
6008 static int bxt_calc_cdclk(int max_pixclk)
6009 {
6010         if (max_pixclk > 576000)
6011                 return 624000;
6012         else if (max_pixclk > 384000)
6013                 return 576000;
6014         else if (max_pixclk > 288000)
6015                 return 384000;
6016         else if (max_pixclk > 144000)
6017                 return 288000;
6018         else
6019                 return 144000;
6020 }
6021
6022 /* Compute the max pixel clock for new configuration. */
6023 static int intel_mode_max_pixclk(struct drm_device *dev,
6024                                  struct drm_atomic_state *state)
6025 {
6026         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
6027         struct drm_i915_private *dev_priv = dev->dev_private;
6028         struct drm_crtc *crtc;
6029         struct drm_crtc_state *crtc_state;
6030         unsigned max_pixclk = 0, i;
6031         enum pipe pipe;
6032
6033         memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
6034                sizeof(intel_state->min_pixclk));
6035
6036         for_each_crtc_in_state(state, crtc, crtc_state, i) {
6037                 int pixclk = 0;
6038
6039                 if (crtc_state->enable)
6040                         pixclk = crtc_state->adjusted_mode.crtc_clock;
6041
6042                 intel_state->min_pixclk[i] = pixclk;
6043         }
6044
6045         for_each_pipe(dev_priv, pipe)
6046                 max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk);
6047
6048         return max_pixclk;
6049 }
6050
6051 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
6052 {
6053         struct drm_device *dev = state->dev;
6054         struct drm_i915_private *dev_priv = dev->dev_private;
6055         int max_pixclk = intel_mode_max_pixclk(dev, state);
6056         struct intel_atomic_state *intel_state =
6057                 to_intel_atomic_state(state);
6058
6059         intel_state->cdclk = intel_state->dev_cdclk =
6060                 valleyview_calc_cdclk(dev_priv, max_pixclk);
6061
6062         if (!intel_state->active_crtcs)
6063                 intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0);
6064
6065         return 0;
6066 }
6067
6068 static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
6069 {
6070         int max_pixclk = ilk_max_pixel_rate(state);
6071         struct intel_atomic_state *intel_state =
6072                 to_intel_atomic_state(state);
6073
6074         intel_state->cdclk = intel_state->dev_cdclk =
6075                 bxt_calc_cdclk(max_pixclk);
6076
6077         if (!intel_state->active_crtcs)
6078                 intel_state->dev_cdclk = bxt_calc_cdclk(0);
6079
6080         return 0;
6081 }
6082
6083 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
6084 {
6085         unsigned int credits, default_credits;
6086
6087         if (IS_CHERRYVIEW(dev_priv))
6088                 default_credits = PFI_CREDIT(12);
6089         else
6090                 default_credits = PFI_CREDIT(8);
6091
6092         if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
6093                 /* CHV suggested value is 31 or 63 */
6094                 if (IS_CHERRYVIEW(dev_priv))
6095                         credits = PFI_CREDIT_63;
6096                 else
6097                         credits = PFI_CREDIT(15);
6098         } else {
6099                 credits = default_credits;
6100         }
6101
6102         /*
6103          * WA - write default credits before re-programming
6104          * FIXME: should we also set the resend bit here?
6105          */
6106         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6107                    default_credits);
6108
6109         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6110                    credits | PFI_CREDIT_RESEND);
6111
6112         /*
6113          * FIXME is this guaranteed to clear
6114          * immediately or should we poll for it?
6115          */
6116         WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6117 }
6118
6119 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6120 {
6121         struct drm_device *dev = old_state->dev;
6122         struct drm_i915_private *dev_priv = dev->dev_private;
6123         struct intel_atomic_state *old_intel_state =
6124                 to_intel_atomic_state(old_state);
6125         unsigned req_cdclk = old_intel_state->dev_cdclk;
6126
6127         /*
6128          * FIXME: We can end up here with all power domains off, yet
6129          * with a CDCLK frequency other than the minimum. To account
6130          * for this take the PIPE-A power domain, which covers the HW
6131          * blocks needed for the following programming. This can be
6132          * removed once it's guaranteed that we get here either with
6133          * the minimum CDCLK set, or the required power domains
6134          * enabled.
6135          */
6136         intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6137
6138         if (IS_CHERRYVIEW(dev))
6139                 cherryview_set_cdclk(dev, req_cdclk);
6140         else
6141                 valleyview_set_cdclk(dev, req_cdclk);
6142
6143         vlv_program_pfi_credits(dev_priv);
6144
6145         intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6146 }
6147
6148 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6149 {
6150         struct drm_device *dev = crtc->dev;
6151         struct drm_i915_private *dev_priv = to_i915(dev);
6152         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6153         struct intel_encoder *encoder;
6154         struct intel_crtc_state *pipe_config =
6155                 to_intel_crtc_state(crtc->state);
6156         int pipe = intel_crtc->pipe;
6157
6158         if (WARN_ON(intel_crtc->active))
6159                 return;
6160
6161         if (intel_crtc->config->has_dp_encoder)
6162                 intel_dp_set_m_n(intel_crtc, M1_N1);
6163
6164         intel_set_pipe_timings(intel_crtc);
6165         intel_set_pipe_src_size(intel_crtc);
6166
6167         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6168                 struct drm_i915_private *dev_priv = dev->dev_private;
6169
6170                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6171                 I915_WRITE(CHV_CANVAS(pipe), 0);
6172         }
6173
6174         i9xx_set_pipeconf(intel_crtc);
6175
6176         intel_crtc->active = true;
6177
6178         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6179
6180         for_each_encoder_on_crtc(dev, crtc, encoder)
6181                 if (encoder->pre_pll_enable)
6182                         encoder->pre_pll_enable(encoder);
6183
6184         if (IS_CHERRYVIEW(dev)) {
6185                 chv_prepare_pll(intel_crtc, intel_crtc->config);
6186                 chv_enable_pll(intel_crtc, intel_crtc->config);
6187         } else {
6188                 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6189                 vlv_enable_pll(intel_crtc, intel_crtc->config);
6190         }
6191
6192         for_each_encoder_on_crtc(dev, crtc, encoder)
6193                 if (encoder->pre_enable)
6194                         encoder->pre_enable(encoder);
6195
6196         i9xx_pfit_enable(intel_crtc);
6197
6198         intel_color_load_luts(&pipe_config->base);
6199
6200         intel_update_watermarks(crtc);
6201         intel_enable_pipe(intel_crtc);
6202
6203         assert_vblank_disabled(crtc);
6204         drm_crtc_vblank_on(crtc);
6205
6206         for_each_encoder_on_crtc(dev, crtc, encoder)
6207                 encoder->enable(encoder);
6208 }
6209
6210 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6211 {
6212         struct drm_device *dev = crtc->base.dev;
6213         struct drm_i915_private *dev_priv = dev->dev_private;
6214
6215         I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6216         I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6217 }
6218
6219 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6220 {
6221         struct drm_device *dev = crtc->dev;
6222         struct drm_i915_private *dev_priv = to_i915(dev);
6223         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6224         struct intel_encoder *encoder;
6225         struct intel_crtc_state *pipe_config =
6226                 to_intel_crtc_state(crtc->state);
6227         enum pipe pipe = intel_crtc->pipe;
6228
6229         if (WARN_ON(intel_crtc->active))
6230                 return;
6231
6232         i9xx_set_pll_dividers(intel_crtc);
6233
6234         if (intel_crtc->config->has_dp_encoder)
6235                 intel_dp_set_m_n(intel_crtc, M1_N1);
6236
6237         intel_set_pipe_timings(intel_crtc);
6238         intel_set_pipe_src_size(intel_crtc);
6239
6240         i9xx_set_pipeconf(intel_crtc);
6241
6242         intel_crtc->active = true;
6243
6244         if (!IS_GEN2(dev))
6245                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6246
6247         for_each_encoder_on_crtc(dev, crtc, encoder)
6248                 if (encoder->pre_enable)
6249                         encoder->pre_enable(encoder);
6250
6251         i9xx_enable_pll(intel_crtc);
6252
6253         i9xx_pfit_enable(intel_crtc);
6254
6255         intel_color_load_luts(&pipe_config->base);
6256
6257         intel_update_watermarks(crtc);
6258         intel_enable_pipe(intel_crtc);
6259
6260         assert_vblank_disabled(crtc);
6261         drm_crtc_vblank_on(crtc);
6262
6263         for_each_encoder_on_crtc(dev, crtc, encoder)
6264                 encoder->enable(encoder);
6265 }
6266
6267 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6268 {
6269         struct drm_device *dev = crtc->base.dev;
6270         struct drm_i915_private *dev_priv = dev->dev_private;
6271
6272         if (!crtc->config->gmch_pfit.control)
6273                 return;
6274
6275         assert_pipe_disabled(dev_priv, crtc->pipe);
6276
6277         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6278                          I915_READ(PFIT_CONTROL));
6279         I915_WRITE(PFIT_CONTROL, 0);
6280 }
6281
6282 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6283 {
6284         struct drm_device *dev = crtc->dev;
6285         struct drm_i915_private *dev_priv = dev->dev_private;
6286         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6287         struct intel_encoder *encoder;
6288         int pipe = intel_crtc->pipe;
6289
6290         /*
6291          * On gen2 planes are double buffered but the pipe isn't, so we must
6292          * wait for planes to fully turn off before disabling the pipe.
6293          */
6294         if (IS_GEN2(dev))
6295                 intel_wait_for_vblank(dev, pipe);
6296
6297         for_each_encoder_on_crtc(dev, crtc, encoder)
6298                 encoder->disable(encoder);
6299
6300         drm_crtc_vblank_off(crtc);
6301         assert_vblank_disabled(crtc);
6302
6303         intel_disable_pipe(intel_crtc);
6304
6305         i9xx_pfit_disable(intel_crtc);
6306
6307         for_each_encoder_on_crtc(dev, crtc, encoder)
6308                 if (encoder->post_disable)
6309                         encoder->post_disable(encoder);
6310
6311         if (!intel_crtc->config->has_dsi_encoder) {
6312                 if (IS_CHERRYVIEW(dev))
6313                         chv_disable_pll(dev_priv, pipe);
6314                 else if (IS_VALLEYVIEW(dev))
6315                         vlv_disable_pll(dev_priv, pipe);
6316                 else
6317                         i9xx_disable_pll(intel_crtc);
6318         }
6319
6320         for_each_encoder_on_crtc(dev, crtc, encoder)
6321                 if (encoder->post_pll_disable)
6322                         encoder->post_pll_disable(encoder);
6323
6324         if (!IS_GEN2(dev))
6325                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6326 }
6327
6328 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6329 {
6330         struct intel_encoder *encoder;
6331         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6332         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6333         enum intel_display_power_domain domain;
6334         unsigned long domains;
6335
6336         if (!intel_crtc->active)
6337                 return;
6338
6339         if (to_intel_plane_state(crtc->primary->state)->visible) {
6340                 WARN_ON(intel_crtc->flip_work);
6341
6342                 intel_pre_disable_primary_noatomic(crtc);
6343
6344                 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
6345                 to_intel_plane_state(crtc->primary->state)->visible = false;
6346         }
6347
6348         dev_priv->display.crtc_disable(crtc);
6349
6350         DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
6351                       crtc->base.id, crtc->name);
6352
6353         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
6354         crtc->state->active = false;
6355         intel_crtc->active = false;
6356         crtc->enabled = false;
6357         crtc->state->connector_mask = 0;
6358         crtc->state->encoder_mask = 0;
6359
6360         for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
6361                 encoder->base.crtc = NULL;
6362
6363         intel_fbc_disable(intel_crtc);
6364         intel_update_watermarks(crtc);
6365         intel_disable_shared_dpll(intel_crtc);
6366
6367         domains = intel_crtc->enabled_power_domains;
6368         for_each_power_domain(domain, domains)
6369                 intel_display_power_put(dev_priv, domain);
6370         intel_crtc->enabled_power_domains = 0;
6371
6372         dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
6373         dev_priv->min_pixclk[intel_crtc->pipe] = 0;
6374 }
6375
6376 /*
6377  * turn all crtc's off, but do not adjust state
6378  * This has to be paired with a call to intel_modeset_setup_hw_state.
6379  */
6380 int intel_display_suspend(struct drm_device *dev)
6381 {
6382         struct drm_i915_private *dev_priv = to_i915(dev);
6383         struct drm_atomic_state *state;
6384         int ret;
6385
6386         state = drm_atomic_helper_suspend(dev);
6387         ret = PTR_ERR_OR_ZERO(state);
6388         if (ret)
6389                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6390         else
6391                 dev_priv->modeset_restore_state = state;
6392         return ret;
6393 }
6394
6395 void intel_encoder_destroy(struct drm_encoder *encoder)
6396 {
6397         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6398
6399         drm_encoder_cleanup(encoder);
6400         kfree(intel_encoder);
6401 }
6402
6403 /* Cross check the actual hw state with our own modeset state tracking (and it's
6404  * internal consistency). */
6405 static void intel_connector_verify_state(struct intel_connector *connector)
6406 {
6407         struct drm_crtc *crtc = connector->base.state->crtc;
6408
6409         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6410                       connector->base.base.id,
6411                       connector->base.name);
6412
6413         if (connector->get_hw_state(connector)) {
6414                 struct intel_encoder *encoder = connector->encoder;
6415                 struct drm_connector_state *conn_state = connector->base.state;
6416
6417                 I915_STATE_WARN(!crtc,
6418                          "connector enabled without attached crtc\n");
6419
6420                 if (!crtc)
6421                         return;
6422
6423                 I915_STATE_WARN(!crtc->state->active,
6424                       "connector is active, but attached crtc isn't\n");
6425
6426                 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6427                         return;
6428
6429                 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6430                         "atomic encoder doesn't match attached encoder\n");
6431
6432                 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6433                         "attached encoder crtc differs from connector crtc\n");
6434         } else {
6435                 I915_STATE_WARN(crtc && crtc->state->active,
6436                         "attached crtc is active, but connector isn't\n");
6437                 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6438                         "best encoder set without crtc!\n");
6439         }
6440 }
6441
6442 int intel_connector_init(struct intel_connector *connector)
6443 {
6444         drm_atomic_helper_connector_reset(&connector->base);
6445
6446         if (!connector->base.state)
6447                 return -ENOMEM;
6448
6449         return 0;
6450 }
6451
6452 struct intel_connector *intel_connector_alloc(void)
6453 {
6454         struct intel_connector *connector;
6455
6456         connector = kzalloc(sizeof *connector, GFP_KERNEL);
6457         if (!connector)
6458                 return NULL;
6459
6460         if (intel_connector_init(connector) < 0) {
6461                 kfree(connector);
6462                 return NULL;
6463         }
6464
6465         return connector;
6466 }
6467
6468 /* Simple connector->get_hw_state implementation for encoders that support only
6469  * one connector and no cloning and hence the encoder state determines the state
6470  * of the connector. */
6471 bool intel_connector_get_hw_state(struct intel_connector *connector)
6472 {
6473         enum pipe pipe = 0;
6474         struct intel_encoder *encoder = connector->encoder;
6475
6476         return encoder->get_hw_state(encoder, &pipe);
6477 }
6478
6479 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6480 {
6481         if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6482                 return crtc_state->fdi_lanes;
6483
6484         return 0;
6485 }
6486
6487 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6488                                      struct intel_crtc_state *pipe_config)
6489 {
6490         struct drm_atomic_state *state = pipe_config->base.state;
6491         struct intel_crtc *other_crtc;
6492         struct intel_crtc_state *other_crtc_state;
6493
6494         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6495                       pipe_name(pipe), pipe_config->fdi_lanes);
6496         if (pipe_config->fdi_lanes > 4) {
6497                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6498                               pipe_name(pipe), pipe_config->fdi_lanes);
6499                 return -EINVAL;
6500         }
6501
6502         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6503                 if (pipe_config->fdi_lanes > 2) {
6504                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6505                                       pipe_config->fdi_lanes);
6506                         return -EINVAL;
6507                 } else {
6508                         return 0;
6509                 }
6510         }
6511
6512         if (INTEL_INFO(dev)->num_pipes == 2)
6513                 return 0;
6514
6515         /* Ivybridge 3 pipe is really complicated */
6516         switch (pipe) {
6517         case PIPE_A:
6518                 return 0;
6519         case PIPE_B:
6520                 if (pipe_config->fdi_lanes <= 2)
6521                         return 0;
6522
6523                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6524                 other_crtc_state =
6525                         intel_atomic_get_crtc_state(state, other_crtc);
6526                 if (IS_ERR(other_crtc_state))
6527                         return PTR_ERR(other_crtc_state);
6528
6529                 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6530                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6531                                       pipe_name(pipe), pipe_config->fdi_lanes);
6532                         return -EINVAL;
6533                 }
6534                 return 0;
6535         case PIPE_C:
6536                 if (pipe_config->fdi_lanes > 2) {
6537                         DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6538                                       pipe_name(pipe), pipe_config->fdi_lanes);
6539                         return -EINVAL;
6540                 }
6541
6542                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6543                 other_crtc_state =
6544                         intel_atomic_get_crtc_state(state, other_crtc);
6545                 if (IS_ERR(other_crtc_state))
6546                         return PTR_ERR(other_crtc_state);
6547
6548                 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6549                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6550                         return -EINVAL;
6551                 }
6552                 return 0;
6553         default:
6554                 BUG();
6555         }
6556 }
6557
6558 #define RETRY 1
6559 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6560                                        struct intel_crtc_state *pipe_config)
6561 {
6562         struct drm_device *dev = intel_crtc->base.dev;
6563         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6564         int lane, link_bw, fdi_dotclock, ret;
6565         bool needs_recompute = false;
6566
6567 retry:
6568         /* FDI is a binary signal running at ~2.7GHz, encoding
6569          * each output octet as 10 bits. The actual frequency
6570          * is stored as a divider into a 100MHz clock, and the
6571          * mode pixel clock is stored in units of 1KHz.
6572          * Hence the bw of each lane in terms of the mode signal
6573          * is:
6574          */
6575         link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
6576
6577         fdi_dotclock = adjusted_mode->crtc_clock;
6578
6579         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6580                                            pipe_config->pipe_bpp);
6581
6582         pipe_config->fdi_lanes = lane;
6583
6584         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6585                                link_bw, &pipe_config->fdi_m_n);
6586
6587         ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
6588         if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6589                 pipe_config->pipe_bpp -= 2*3;
6590                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6591                               pipe_config->pipe_bpp);
6592                 needs_recompute = true;
6593                 pipe_config->bw_constrained = true;
6594
6595                 goto retry;
6596         }
6597
6598         if (needs_recompute)
6599                 return RETRY;
6600
6601         return ret;
6602 }
6603
6604 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6605                                      struct intel_crtc_state *pipe_config)
6606 {
6607         if (pipe_config->pipe_bpp > 24)
6608                 return false;
6609
6610         /* HSW can handle pixel rate up to cdclk? */
6611         if (IS_HASWELL(dev_priv))
6612                 return true;
6613
6614         /*
6615          * We compare against max which means we must take
6616          * the increased cdclk requirement into account when
6617          * calculating the new cdclk.
6618          *
6619          * Should measure whether using a lower cdclk w/o IPS
6620          */
6621         return ilk_pipe_pixel_rate(pipe_config) <=
6622                 dev_priv->max_cdclk_freq * 95 / 100;
6623 }
6624
6625 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6626                                    struct intel_crtc_state *pipe_config)
6627 {
6628         struct drm_device *dev = crtc->base.dev;
6629         struct drm_i915_private *dev_priv = dev->dev_private;
6630
6631         pipe_config->ips_enabled = i915.enable_ips &&
6632                 hsw_crtc_supports_ips(crtc) &&
6633                 pipe_config_supports_ips(dev_priv, pipe_config);
6634 }
6635
6636 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6637 {
6638         const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6639
6640         /* GDG double wide on either pipe, otherwise pipe A only */
6641         return INTEL_INFO(dev_priv)->gen < 4 &&
6642                 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6643 }
6644
6645 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6646                                      struct intel_crtc_state *pipe_config)
6647 {
6648         struct drm_device *dev = crtc->base.dev;
6649         struct drm_i915_private *dev_priv = dev->dev_private;
6650         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6651         int clock_limit = dev_priv->max_dotclk_freq;
6652
6653         if (INTEL_INFO(dev)->gen < 4) {
6654                 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6655
6656                 /*
6657                  * Enable double wide mode when the dot clock
6658                  * is > 90% of the (display) core speed.
6659                  */
6660                 if (intel_crtc_supports_double_wide(crtc) &&
6661                     adjusted_mode->crtc_clock > clock_limit) {
6662                         clock_limit = dev_priv->max_dotclk_freq;
6663                         pipe_config->double_wide = true;
6664                 }
6665         }
6666
6667         if (adjusted_mode->crtc_clock > clock_limit) {
6668                 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6669                               adjusted_mode->crtc_clock, clock_limit,
6670                               yesno(pipe_config->double_wide));
6671                 return -EINVAL;
6672         }
6673
6674         /*
6675          * Pipe horizontal size must be even in:
6676          * - DVO ganged mode
6677          * - LVDS dual channel mode
6678          * - Double wide pipe
6679          */
6680         if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6681              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6682                 pipe_config->pipe_src_w &= ~1;
6683
6684         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6685          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6686          */
6687         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6688                 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6689                 return -EINVAL;
6690
6691         if (HAS_IPS(dev))
6692                 hsw_compute_ips_config(crtc, pipe_config);
6693
6694         if (pipe_config->has_pch_encoder)
6695                 return ironlake_fdi_compute_config(crtc, pipe_config);
6696
6697         return 0;
6698 }
6699
6700 static int skylake_get_display_clock_speed(struct drm_device *dev)
6701 {
6702         struct drm_i915_private *dev_priv = to_i915(dev);
6703         uint32_t cdctl;
6704
6705         skl_dpll0_update(dev_priv);
6706
6707         if (dev_priv->cdclk_pll.vco == 0)
6708                 return dev_priv->cdclk_pll.ref;
6709
6710         cdctl = I915_READ(CDCLK_CTL);
6711
6712         if (dev_priv->cdclk_pll.vco == 8640000) {
6713                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6714                 case CDCLK_FREQ_450_432:
6715                         return 432000;
6716                 case CDCLK_FREQ_337_308:
6717                         return 308571;
6718                 case CDCLK_FREQ_540:
6719                         return 540000;
6720                 case CDCLK_FREQ_675_617:
6721                         return 617143;
6722                 default:
6723                         MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
6724                 }
6725         } else {
6726                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6727                 case CDCLK_FREQ_450_432:
6728                         return 450000;
6729                 case CDCLK_FREQ_337_308:
6730                         return 337500;
6731                 case CDCLK_FREQ_540:
6732                         return 540000;
6733                 case CDCLK_FREQ_675_617:
6734                         return 675000;
6735                 default:
6736                         MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
6737                 }
6738         }
6739
6740         return dev_priv->cdclk_pll.ref;
6741 }
6742
6743 static void bxt_de_pll_update(struct drm_i915_private *dev_priv)
6744 {
6745         u32 val;
6746
6747         dev_priv->cdclk_pll.ref = 19200;
6748         dev_priv->cdclk_pll.vco = 0;
6749
6750         val = I915_READ(BXT_DE_PLL_ENABLE);
6751         if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
6752                 return;
6753
6754         if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
6755                 return;
6756
6757         val = I915_READ(BXT_DE_PLL_CTL);
6758         dev_priv->cdclk_pll.vco = (val & BXT_DE_PLL_RATIO_MASK) *
6759                 dev_priv->cdclk_pll.ref;
6760 }
6761
6762 static int broxton_get_display_clock_speed(struct drm_device *dev)
6763 {
6764         struct drm_i915_private *dev_priv = to_i915(dev);
6765         u32 divider;
6766         int div, vco;
6767
6768         bxt_de_pll_update(dev_priv);
6769
6770         vco = dev_priv->cdclk_pll.vco;
6771         if (vco == 0)
6772                 return dev_priv->cdclk_pll.ref;
6773
6774         divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
6775
6776         switch (divider) {
6777         case BXT_CDCLK_CD2X_DIV_SEL_1:
6778                 div = 2;
6779                 break;
6780         case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6781                 div = 3;
6782                 break;
6783         case BXT_CDCLK_CD2X_DIV_SEL_2:
6784                 div = 4;
6785                 break;
6786         case BXT_CDCLK_CD2X_DIV_SEL_4:
6787                 div = 8;
6788                 break;
6789         default:
6790                 MISSING_CASE(divider);
6791                 return dev_priv->cdclk_pll.ref;
6792         }
6793
6794         return DIV_ROUND_CLOSEST(vco, div);
6795 }
6796
6797 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6798 {
6799         struct drm_i915_private *dev_priv = dev->dev_private;
6800         uint32_t lcpll = I915_READ(LCPLL_CTL);
6801         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6802
6803         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6804                 return 800000;
6805         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6806                 return 450000;
6807         else if (freq == LCPLL_CLK_FREQ_450)
6808                 return 450000;
6809         else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6810                 return 540000;
6811         else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6812                 return 337500;
6813         else
6814                 return 675000;
6815 }
6816
6817 static int haswell_get_display_clock_speed(struct drm_device *dev)
6818 {
6819         struct drm_i915_private *dev_priv = dev->dev_private;
6820         uint32_t lcpll = I915_READ(LCPLL_CTL);
6821         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6822
6823         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6824                 return 800000;
6825         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6826                 return 450000;
6827         else if (freq == LCPLL_CLK_FREQ_450)
6828                 return 450000;
6829         else if (IS_HSW_ULT(dev))
6830                 return 337500;
6831         else
6832                 return 540000;
6833 }
6834
6835 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6836 {
6837         return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
6838                                       CCK_DISPLAY_CLOCK_CONTROL);
6839 }
6840
6841 static int ilk_get_display_clock_speed(struct drm_device *dev)
6842 {
6843         return 450000;
6844 }
6845
6846 static int i945_get_display_clock_speed(struct drm_device *dev)
6847 {
6848         return 400000;
6849 }
6850
6851 static int i915_get_display_clock_speed(struct drm_device *dev)
6852 {
6853         return 333333;
6854 }
6855
6856 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6857 {
6858         return 200000;
6859 }
6860
6861 static int pnv_get_display_clock_speed(struct drm_device *dev)
6862 {
6863         u16 gcfgc = 0;
6864
6865         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6866
6867         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6868         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6869                 return 266667;
6870         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6871                 return 333333;
6872         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6873                 return 444444;
6874         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6875                 return 200000;
6876         default:
6877                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6878         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6879                 return 133333;
6880         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6881                 return 166667;
6882         }
6883 }
6884
6885 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6886 {
6887         u16 gcfgc = 0;
6888
6889         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6890
6891         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6892                 return 133333;
6893         else {
6894                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6895                 case GC_DISPLAY_CLOCK_333_MHZ:
6896                         return 333333;
6897                 default:
6898                 case GC_DISPLAY_CLOCK_190_200_MHZ:
6899                         return 190000;
6900                 }
6901         }
6902 }
6903
6904 static int i865_get_display_clock_speed(struct drm_device *dev)
6905 {
6906         return 266667;
6907 }
6908
6909 static int i85x_get_display_clock_speed(struct drm_device *dev)
6910 {
6911         u16 hpllcc = 0;
6912
6913         /*
6914          * 852GM/852GMV only supports 133 MHz and the HPLLCC
6915          * encoding is different :(
6916          * FIXME is this the right way to detect 852GM/852GMV?
6917          */
6918         if (dev->pdev->revision == 0x1)
6919                 return 133333;
6920
6921         pci_bus_read_config_word(dev->pdev->bus,
6922                                  PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6923
6924         /* Assume that the hardware is in the high speed state.  This
6925          * should be the default.
6926          */
6927         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6928         case GC_CLOCK_133_200:
6929         case GC_CLOCK_133_200_2:
6930         case GC_CLOCK_100_200:
6931                 return 200000;
6932         case GC_CLOCK_166_250:
6933                 return 250000;
6934         case GC_CLOCK_100_133:
6935                 return 133333;
6936         case GC_CLOCK_133_266:
6937         case GC_CLOCK_133_266_2:
6938         case GC_CLOCK_166_266:
6939                 return 266667;
6940         }
6941
6942         /* Shouldn't happen */
6943         return 0;
6944 }
6945
6946 static int i830_get_display_clock_speed(struct drm_device *dev)
6947 {
6948         return 133333;
6949 }
6950
6951 static unsigned int intel_hpll_vco(struct drm_device *dev)
6952 {
6953         struct drm_i915_private *dev_priv = dev->dev_private;
6954         static const unsigned int blb_vco[8] = {
6955                 [0] = 3200000,
6956                 [1] = 4000000,
6957                 [2] = 5333333,
6958                 [3] = 4800000,
6959                 [4] = 6400000,
6960         };
6961         static const unsigned int pnv_vco[8] = {
6962                 [0] = 3200000,
6963                 [1] = 4000000,
6964                 [2] = 5333333,
6965                 [3] = 4800000,
6966                 [4] = 2666667,
6967         };
6968         static const unsigned int cl_vco[8] = {
6969                 [0] = 3200000,
6970                 [1] = 4000000,
6971                 [2] = 5333333,
6972                 [3] = 6400000,
6973                 [4] = 3333333,
6974                 [5] = 3566667,
6975                 [6] = 4266667,
6976         };
6977         static const unsigned int elk_vco[8] = {
6978                 [0] = 3200000,
6979                 [1] = 4000000,
6980                 [2] = 5333333,
6981                 [3] = 4800000,
6982         };
6983         static const unsigned int ctg_vco[8] = {
6984                 [0] = 3200000,
6985                 [1] = 4000000,
6986                 [2] = 5333333,
6987                 [3] = 6400000,
6988                 [4] = 2666667,
6989                 [5] = 4266667,
6990         };
6991         const unsigned int *vco_table;
6992         unsigned int vco;
6993         uint8_t tmp = 0;
6994
6995         /* FIXME other chipsets? */
6996         if (IS_GM45(dev))
6997                 vco_table = ctg_vco;
6998         else if (IS_G4X(dev))
6999                 vco_table = elk_vco;
7000         else if (IS_CRESTLINE(dev))
7001                 vco_table = cl_vco;
7002         else if (IS_PINEVIEW(dev))
7003                 vco_table = pnv_vco;
7004         else if (IS_G33(dev))
7005                 vco_table = blb_vco;
7006         else
7007                 return 0;
7008
7009         tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
7010
7011         vco = vco_table[tmp & 0x7];
7012         if (vco == 0)
7013                 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
7014         else
7015                 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
7016
7017         return vco;
7018 }
7019
7020 static int gm45_get_display_clock_speed(struct drm_device *dev)
7021 {
7022         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7023         uint16_t tmp = 0;
7024
7025         pci_read_config_word(dev->pdev, GCFGC, &tmp);
7026
7027         cdclk_sel = (tmp >> 12) & 0x1;
7028
7029         switch (vco) {
7030         case 2666667:
7031         case 4000000:
7032         case 5333333:
7033                 return cdclk_sel ? 333333 : 222222;
7034         case 3200000:
7035                 return cdclk_sel ? 320000 : 228571;
7036         default:
7037                 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
7038                 return 222222;
7039         }
7040 }
7041
7042 static int i965gm_get_display_clock_speed(struct drm_device *dev)
7043 {
7044         static const uint8_t div_3200[] = { 16, 10,  8 };
7045         static const uint8_t div_4000[] = { 20, 12, 10 };
7046         static const uint8_t div_5333[] = { 24, 16, 14 };
7047         const uint8_t *div_table;
7048         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7049         uint16_t tmp = 0;
7050
7051         pci_read_config_word(dev->pdev, GCFGC, &tmp);
7052
7053         cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
7054
7055         if (cdclk_sel >= ARRAY_SIZE(div_3200))
7056                 goto fail;
7057
7058         switch (vco) {
7059         case 3200000:
7060                 div_table = div_3200;
7061                 break;
7062         case 4000000:
7063                 div_table = div_4000;
7064                 break;
7065         case 5333333:
7066                 div_table = div_5333;
7067                 break;
7068         default:
7069                 goto fail;
7070         }
7071
7072         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7073
7074 fail:
7075         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
7076         return 200000;
7077 }
7078
7079 static int g33_get_display_clock_speed(struct drm_device *dev)
7080 {
7081         static const uint8_t div_3200[] = { 12, 10,  8,  7, 5, 16 };
7082         static const uint8_t div_4000[] = { 14, 12, 10,  8, 6, 20 };
7083         static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
7084         static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
7085         const uint8_t *div_table;
7086         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7087         uint16_t tmp = 0;
7088
7089         pci_read_config_word(dev->pdev, GCFGC, &tmp);
7090
7091         cdclk_sel = (tmp >> 4) & 0x7;
7092
7093         if (cdclk_sel >= ARRAY_SIZE(div_3200))
7094                 goto fail;
7095
7096         switch (vco) {
7097         case 3200000:
7098                 div_table = div_3200;
7099                 break;
7100         case 4000000:
7101                 div_table = div_4000;
7102                 break;
7103         case 4800000:
7104                 div_table = div_4800;
7105                 break;
7106         case 5333333:
7107                 div_table = div_5333;
7108                 break;
7109         default:
7110                 goto fail;
7111         }
7112
7113         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7114
7115 fail:
7116         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7117         return 190476;
7118 }
7119
7120 static void
7121 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7122 {
7123         while (*num > DATA_LINK_M_N_MASK ||
7124                *den > DATA_LINK_M_N_MASK) {
7125                 *num >>= 1;
7126                 *den >>= 1;
7127         }
7128 }
7129
7130 static void compute_m_n(unsigned int m, unsigned int n,
7131                         uint32_t *ret_m, uint32_t *ret_n)
7132 {
7133         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7134         *ret_m = div_u64((uint64_t) m * *ret_n, n);
7135         intel_reduce_m_n_ratio(ret_m, ret_n);
7136 }
7137
7138 void
7139 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7140                        int pixel_clock, int link_clock,
7141                        struct intel_link_m_n *m_n)
7142 {
7143         m_n->tu = 64;
7144
7145         compute_m_n(bits_per_pixel * pixel_clock,
7146                     link_clock * nlanes * 8,
7147                     &m_n->gmch_m, &m_n->gmch_n);
7148
7149         compute_m_n(pixel_clock, link_clock,
7150                     &m_n->link_m, &m_n->link_n);
7151 }
7152
7153 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7154 {
7155         if (i915.panel_use_ssc >= 0)
7156                 return i915.panel_use_ssc != 0;
7157         return dev_priv->vbt.lvds_use_ssc
7158                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7159 }
7160
7161 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7162 {
7163         return (1 << dpll->n) << 16 | dpll->m2;
7164 }
7165
7166 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7167 {
7168         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7169 }
7170
7171 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7172                                      struct intel_crtc_state *crtc_state,
7173                                      struct dpll *reduced_clock)
7174 {
7175         struct drm_device *dev = crtc->base.dev;
7176         u32 fp, fp2 = 0;
7177
7178         if (IS_PINEVIEW(dev)) {
7179                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7180                 if (reduced_clock)
7181                         fp2 = pnv_dpll_compute_fp(reduced_clock);
7182         } else {
7183                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7184                 if (reduced_clock)
7185                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
7186         }
7187
7188         crtc_state->dpll_hw_state.fp0 = fp;
7189
7190         crtc->lowfreq_avail = false;
7191         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7192             reduced_clock) {
7193                 crtc_state->dpll_hw_state.fp1 = fp2;
7194                 crtc->lowfreq_avail = true;
7195         } else {
7196                 crtc_state->dpll_hw_state.fp1 = fp;
7197         }
7198 }
7199
7200 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7201                 pipe)
7202 {
7203         u32 reg_val;
7204
7205         /*
7206          * PLLB opamp always calibrates to max value of 0x3f, force enable it
7207          * and set it to a reasonable value instead.
7208          */
7209         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7210         reg_val &= 0xffffff00;
7211         reg_val |= 0x00000030;
7212         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7213
7214         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7215         reg_val &= 0x8cffffff;
7216         reg_val = 0x8c000000;
7217         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7218
7219         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7220         reg_val &= 0xffffff00;
7221         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7222
7223         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7224         reg_val &= 0x00ffffff;
7225         reg_val |= 0xb0000000;
7226         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7227 }
7228
7229 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7230                                          struct intel_link_m_n *m_n)
7231 {
7232         struct drm_device *dev = crtc->base.dev;
7233         struct drm_i915_private *dev_priv = dev->dev_private;
7234         int pipe = crtc->pipe;
7235
7236         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7237         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7238         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7239         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7240 }
7241
7242 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7243                                          struct intel_link_m_n *m_n,
7244                                          struct intel_link_m_n *m2_n2)
7245 {
7246         struct drm_device *dev = crtc->base.dev;
7247         struct drm_i915_private *dev_priv = dev->dev_private;
7248         int pipe = crtc->pipe;
7249         enum transcoder transcoder = crtc->config->cpu_transcoder;
7250
7251         if (INTEL_INFO(dev)->gen >= 5) {
7252                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7253                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7254                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7255                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7256                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7257                  * for gen < 8) and if DRRS is supported (to make sure the
7258                  * registers are not unnecessarily accessed).
7259                  */
7260                 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7261                         crtc->config->has_drrs) {
7262                         I915_WRITE(PIPE_DATA_M2(transcoder),
7263                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7264                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7265                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7266                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7267                 }
7268         } else {
7269                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7270                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7271                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7272                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7273         }
7274 }
7275
7276 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7277 {
7278         struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7279
7280         if (m_n == M1_N1) {
7281                 dp_m_n = &crtc->config->dp_m_n;
7282                 dp_m2_n2 = &crtc->config->dp_m2_n2;
7283         } else if (m_n == M2_N2) {
7284
7285                 /*
7286                  * M2_N2 registers are not supported. Hence m2_n2 divider value
7287                  * needs to be programmed into M1_N1.
7288                  */
7289                 dp_m_n = &crtc->config->dp_m2_n2;
7290         } else {
7291                 DRM_ERROR("Unsupported divider value\n");
7292                 return;
7293         }
7294
7295         if (crtc->config->has_pch_encoder)
7296                 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7297         else
7298                 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7299 }
7300
7301 static void vlv_compute_dpll(struct intel_crtc *crtc,
7302                              struct intel_crtc_state *pipe_config)
7303 {
7304         pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
7305                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7306         if (crtc->pipe != PIPE_A)
7307                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7308
7309         /* DPLL not used with DSI, but still need the rest set up */
7310         if (!pipe_config->has_dsi_encoder)
7311                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
7312                         DPLL_EXT_BUFFER_ENABLE_VLV;
7313
7314         pipe_config->dpll_hw_state.dpll_md =
7315                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7316 }
7317
7318 static void chv_compute_dpll(struct intel_crtc *crtc,
7319                              struct intel_crtc_state *pipe_config)
7320 {
7321         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7322                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7323         if (crtc->pipe != PIPE_A)
7324                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7325
7326         /* DPLL not used with DSI, but still need the rest set up */
7327         if (!pipe_config->has_dsi_encoder)
7328                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
7329
7330         pipe_config->dpll_hw_state.dpll_md =
7331                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7332 }
7333
7334 static void vlv_prepare_pll(struct intel_crtc *crtc,
7335                             const struct intel_crtc_state *pipe_config)
7336 {
7337         struct drm_device *dev = crtc->base.dev;
7338         struct drm_i915_private *dev_priv = dev->dev_private;
7339         enum pipe pipe = crtc->pipe;
7340         u32 mdiv;
7341         u32 bestn, bestm1, bestm2, bestp1, bestp2;
7342         u32 coreclk, reg_val;
7343
7344         /* Enable Refclk */
7345         I915_WRITE(DPLL(pipe),
7346                    pipe_config->dpll_hw_state.dpll &
7347                    ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
7348
7349         /* No need to actually set up the DPLL with DSI */
7350         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7351                 return;
7352
7353         mutex_lock(&dev_priv->sb_lock);
7354
7355         bestn = pipe_config->dpll.n;
7356         bestm1 = pipe_config->dpll.m1;
7357         bestm2 = pipe_config->dpll.m2;
7358         bestp1 = pipe_config->dpll.p1;
7359         bestp2 = pipe_config->dpll.p2;
7360
7361         /* See eDP HDMI DPIO driver vbios notes doc */
7362
7363         /* PLL B needs special handling */
7364         if (pipe == PIPE_B)
7365                 vlv_pllb_recal_opamp(dev_priv, pipe);
7366
7367         /* Set up Tx target for periodic Rcomp update */
7368         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7369
7370         /* Disable target IRef on PLL */
7371         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7372         reg_val &= 0x00ffffff;
7373         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7374
7375         /* Disable fast lock */
7376         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7377
7378         /* Set idtafcrecal before PLL is enabled */
7379         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7380         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7381         mdiv |= ((bestn << DPIO_N_SHIFT));
7382         mdiv |= (1 << DPIO_K_SHIFT);
7383
7384         /*
7385          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7386          * but we don't support that).
7387          * Note: don't use the DAC post divider as it seems unstable.
7388          */
7389         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7390         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7391
7392         mdiv |= DPIO_ENABLE_CALIBRATION;
7393         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7394
7395         /* Set HBR and RBR LPF coefficients */
7396         if (pipe_config->port_clock == 162000 ||
7397             intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7398             intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7399                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7400                                  0x009f0003);
7401         else
7402                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7403                                  0x00d0000f);
7404
7405         if (pipe_config->has_dp_encoder) {
7406                 /* Use SSC source */
7407                 if (pipe == PIPE_A)
7408                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7409                                          0x0df40000);
7410                 else
7411                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7412                                          0x0df70000);
7413         } else { /* HDMI or VGA */
7414                 /* Use bend source */
7415                 if (pipe == PIPE_A)
7416                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7417                                          0x0df70000);
7418                 else
7419                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7420                                          0x0df40000);
7421         }
7422
7423         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7424         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7425         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7426             intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7427                 coreclk |= 0x01000000;
7428         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7429
7430         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7431         mutex_unlock(&dev_priv->sb_lock);
7432 }
7433
7434 static void chv_prepare_pll(struct intel_crtc *crtc,
7435                             const struct intel_crtc_state *pipe_config)
7436 {
7437         struct drm_device *dev = crtc->base.dev;
7438         struct drm_i915_private *dev_priv = dev->dev_private;
7439         enum pipe pipe = crtc->pipe;
7440         enum dpio_channel port = vlv_pipe_to_channel(pipe);
7441         u32 loopfilter, tribuf_calcntr;
7442         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7443         u32 dpio_val;
7444         int vco;
7445
7446         /* Enable Refclk and SSC */
7447         I915_WRITE(DPLL(pipe),
7448                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7449
7450         /* No need to actually set up the DPLL with DSI */
7451         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7452                 return;
7453
7454         bestn = pipe_config->dpll.n;
7455         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7456         bestm1 = pipe_config->dpll.m1;
7457         bestm2 = pipe_config->dpll.m2 >> 22;
7458         bestp1 = pipe_config->dpll.p1;
7459         bestp2 = pipe_config->dpll.p2;
7460         vco = pipe_config->dpll.vco;
7461         dpio_val = 0;
7462         loopfilter = 0;
7463
7464         mutex_lock(&dev_priv->sb_lock);
7465
7466         /* p1 and p2 divider */
7467         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7468                         5 << DPIO_CHV_S1_DIV_SHIFT |
7469                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7470                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7471                         1 << DPIO_CHV_K_DIV_SHIFT);
7472
7473         /* Feedback post-divider - m2 */
7474         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7475
7476         /* Feedback refclk divider - n and m1 */
7477         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7478                         DPIO_CHV_M1_DIV_BY_2 |
7479                         1 << DPIO_CHV_N_DIV_SHIFT);
7480
7481         /* M2 fraction division */
7482         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7483
7484         /* M2 fraction division enable */
7485         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7486         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7487         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7488         if (bestm2_frac)
7489                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7490         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7491
7492         /* Program digital lock detect threshold */
7493         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7494         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7495                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7496         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7497         if (!bestm2_frac)
7498                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7499         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7500
7501         /* Loop filter */
7502         if (vco == 5400000) {
7503                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7504                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7505                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7506                 tribuf_calcntr = 0x9;
7507         } else if (vco <= 6200000) {
7508                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7509                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7510                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7511                 tribuf_calcntr = 0x9;
7512         } else if (vco <= 6480000) {
7513                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7514                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7515                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7516                 tribuf_calcntr = 0x8;
7517         } else {
7518                 /* Not supported. Apply the same limits as in the max case */
7519                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7520                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7521                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7522                 tribuf_calcntr = 0;
7523         }
7524         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7525
7526         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7527         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7528         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7529         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7530
7531         /* AFC Recal */
7532         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7533                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7534                         DPIO_AFC_RECAL);
7535
7536         mutex_unlock(&dev_priv->sb_lock);
7537 }
7538
7539 /**
7540  * vlv_force_pll_on - forcibly enable just the PLL
7541  * @dev_priv: i915 private structure
7542  * @pipe: pipe PLL to enable
7543  * @dpll: PLL configuration
7544  *
7545  * Enable the PLL for @pipe using the supplied @dpll config. To be used
7546  * in cases where we need the PLL enabled even when @pipe is not going to
7547  * be enabled.
7548  */
7549 int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7550                      const struct dpll *dpll)
7551 {
7552         struct intel_crtc *crtc =
7553                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7554         struct intel_crtc_state *pipe_config;
7555
7556         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7557         if (!pipe_config)
7558                 return -ENOMEM;
7559
7560         pipe_config->base.crtc = &crtc->base;
7561         pipe_config->pixel_multiplier = 1;
7562         pipe_config->dpll = *dpll;
7563
7564         if (IS_CHERRYVIEW(dev)) {
7565                 chv_compute_dpll(crtc, pipe_config);
7566                 chv_prepare_pll(crtc, pipe_config);
7567                 chv_enable_pll(crtc, pipe_config);
7568         } else {
7569                 vlv_compute_dpll(crtc, pipe_config);
7570                 vlv_prepare_pll(crtc, pipe_config);
7571                 vlv_enable_pll(crtc, pipe_config);
7572         }
7573
7574         kfree(pipe_config);
7575
7576         return 0;
7577 }
7578
7579 /**
7580  * vlv_force_pll_off - forcibly disable just the PLL
7581  * @dev_priv: i915 private structure
7582  * @pipe: pipe PLL to disable
7583  *
7584  * Disable the PLL for @pipe. To be used in cases where we need
7585  * the PLL enabled even when @pipe is not going to be enabled.
7586  */
7587 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7588 {
7589         if (IS_CHERRYVIEW(dev))
7590                 chv_disable_pll(to_i915(dev), pipe);
7591         else
7592                 vlv_disable_pll(to_i915(dev), pipe);
7593 }
7594
7595 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7596                               struct intel_crtc_state *crtc_state,
7597                               struct dpll *reduced_clock)
7598 {
7599         struct drm_device *dev = crtc->base.dev;
7600         struct drm_i915_private *dev_priv = dev->dev_private;
7601         u32 dpll;
7602         bool is_sdvo;
7603         struct dpll *clock = &crtc_state->dpll;
7604
7605         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7606
7607         is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7608                 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7609
7610         dpll = DPLL_VGA_MODE_DIS;
7611
7612         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7613                 dpll |= DPLLB_MODE_LVDS;
7614         else
7615                 dpll |= DPLLB_MODE_DAC_SERIAL;
7616
7617         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7618                 dpll |= (crtc_state->pixel_multiplier - 1)
7619                         << SDVO_MULTIPLIER_SHIFT_HIRES;
7620         }
7621
7622         if (is_sdvo)
7623                 dpll |= DPLL_SDVO_HIGH_SPEED;
7624
7625         if (crtc_state->has_dp_encoder)
7626                 dpll |= DPLL_SDVO_HIGH_SPEED;
7627
7628         /* compute bitmask from p1 value */
7629         if (IS_PINEVIEW(dev))
7630                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7631         else {
7632                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7633                 if (IS_G4X(dev) && reduced_clock)
7634                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7635         }
7636         switch (clock->p2) {
7637         case 5:
7638                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7639                 break;
7640         case 7:
7641                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7642                 break;
7643         case 10:
7644                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7645                 break;
7646         case 14:
7647                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7648                 break;
7649         }
7650         if (INTEL_INFO(dev)->gen >= 4)
7651                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7652
7653         if (crtc_state->sdvo_tv_clock)
7654                 dpll |= PLL_REF_INPUT_TVCLKINBC;
7655         else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7656                  intel_panel_use_ssc(dev_priv))
7657                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7658         else
7659                 dpll |= PLL_REF_INPUT_DREFCLK;
7660
7661         dpll |= DPLL_VCO_ENABLE;
7662         crtc_state->dpll_hw_state.dpll = dpll;
7663
7664         if (INTEL_INFO(dev)->gen >= 4) {
7665                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7666                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7667                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7668         }
7669 }
7670
7671 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7672                               struct intel_crtc_state *crtc_state,
7673                               struct dpll *reduced_clock)
7674 {
7675         struct drm_device *dev = crtc->base.dev;
7676         struct drm_i915_private *dev_priv = dev->dev_private;
7677         u32 dpll;
7678         struct dpll *clock = &crtc_state->dpll;
7679
7680         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7681
7682         dpll = DPLL_VGA_MODE_DIS;
7683
7684         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7685                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7686         } else {
7687                 if (clock->p1 == 2)
7688                         dpll |= PLL_P1_DIVIDE_BY_TWO;
7689                 else
7690                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7691                 if (clock->p2 == 4)
7692                         dpll |= PLL_P2_DIVIDE_BY_4;
7693         }
7694
7695         if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7696                 dpll |= DPLL_DVO_2X_MODE;
7697
7698         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7699             intel_panel_use_ssc(dev_priv))
7700                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7701         else
7702                 dpll |= PLL_REF_INPUT_DREFCLK;
7703
7704         dpll |= DPLL_VCO_ENABLE;
7705         crtc_state->dpll_hw_state.dpll = dpll;
7706 }
7707
7708 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7709 {
7710         struct drm_device *dev = intel_crtc->base.dev;
7711         struct drm_i915_private *dev_priv = dev->dev_private;
7712         enum pipe pipe = intel_crtc->pipe;
7713         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7714         const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
7715         uint32_t crtc_vtotal, crtc_vblank_end;
7716         int vsyncshift = 0;
7717
7718         /* We need to be careful not to changed the adjusted mode, for otherwise
7719          * the hw state checker will get angry at the mismatch. */
7720         crtc_vtotal = adjusted_mode->crtc_vtotal;
7721         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7722
7723         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7724                 /* the chip adds 2 halflines automatically */
7725                 crtc_vtotal -= 1;
7726                 crtc_vblank_end -= 1;
7727
7728                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7729                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7730                 else
7731                         vsyncshift = adjusted_mode->crtc_hsync_start -
7732                                 adjusted_mode->crtc_htotal / 2;
7733                 if (vsyncshift < 0)
7734                         vsyncshift += adjusted_mode->crtc_htotal;
7735         }
7736
7737         if (INTEL_INFO(dev)->gen > 3)
7738                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7739
7740         I915_WRITE(HTOTAL(cpu_transcoder),
7741                    (adjusted_mode->crtc_hdisplay - 1) |
7742                    ((adjusted_mode->crtc_htotal - 1) << 16));
7743         I915_WRITE(HBLANK(cpu_transcoder),
7744                    (adjusted_mode->crtc_hblank_start - 1) |
7745                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
7746         I915_WRITE(HSYNC(cpu_transcoder),
7747                    (adjusted_mode->crtc_hsync_start - 1) |
7748                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
7749
7750         I915_WRITE(VTOTAL(cpu_transcoder),
7751                    (adjusted_mode->crtc_vdisplay - 1) |
7752                    ((crtc_vtotal - 1) << 16));
7753         I915_WRITE(VBLANK(cpu_transcoder),
7754                    (adjusted_mode->crtc_vblank_start - 1) |
7755                    ((crtc_vblank_end - 1) << 16));
7756         I915_WRITE(VSYNC(cpu_transcoder),
7757                    (adjusted_mode->crtc_vsync_start - 1) |
7758                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
7759
7760         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7761          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7762          * documented on the DDI_FUNC_CTL register description, EDP Input Select
7763          * bits. */
7764         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7765             (pipe == PIPE_B || pipe == PIPE_C))
7766                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7767
7768 }
7769
7770 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
7771 {
7772         struct drm_device *dev = intel_crtc->base.dev;
7773         struct drm_i915_private *dev_priv = dev->dev_private;
7774         enum pipe pipe = intel_crtc->pipe;
7775
7776         /* pipesrc controls the size that is scaled from, which should
7777          * always be the user's requested size.
7778          */
7779         I915_WRITE(PIPESRC(pipe),
7780                    ((intel_crtc->config->pipe_src_w - 1) << 16) |
7781                    (intel_crtc->config->pipe_src_h - 1));
7782 }
7783
7784 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7785                                    struct intel_crtc_state *pipe_config)
7786 {
7787         struct drm_device *dev = crtc->base.dev;
7788         struct drm_i915_private *dev_priv = dev->dev_private;
7789         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7790         uint32_t tmp;
7791
7792         tmp = I915_READ(HTOTAL(cpu_transcoder));
7793         pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7794         pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7795         tmp = I915_READ(HBLANK(cpu_transcoder));
7796         pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7797         pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7798         tmp = I915_READ(HSYNC(cpu_transcoder));
7799         pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7800         pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7801
7802         tmp = I915_READ(VTOTAL(cpu_transcoder));
7803         pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7804         pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7805         tmp = I915_READ(VBLANK(cpu_transcoder));
7806         pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7807         pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7808         tmp = I915_READ(VSYNC(cpu_transcoder));
7809         pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7810         pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7811
7812         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7813                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7814                 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7815                 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7816         }
7817 }
7818
7819 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
7820                                     struct intel_crtc_state *pipe_config)
7821 {
7822         struct drm_device *dev = crtc->base.dev;
7823         struct drm_i915_private *dev_priv = dev->dev_private;
7824         u32 tmp;
7825
7826         tmp = I915_READ(PIPESRC(crtc->pipe));
7827         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7828         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7829
7830         pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7831         pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7832 }
7833
7834 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7835                                  struct intel_crtc_state *pipe_config)
7836 {
7837         mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7838         mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7839         mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7840         mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7841
7842         mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7843         mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7844         mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7845         mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7846
7847         mode->flags = pipe_config->base.adjusted_mode.flags;
7848         mode->type = DRM_MODE_TYPE_DRIVER;
7849
7850         mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7851         mode->flags |= pipe_config->base.adjusted_mode.flags;
7852
7853         mode->hsync = drm_mode_hsync(mode);
7854         mode->vrefresh = drm_mode_vrefresh(mode);
7855         drm_mode_set_name(mode);
7856 }
7857
7858 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7859 {
7860         struct drm_device *dev = intel_crtc->base.dev;
7861         struct drm_i915_private *dev_priv = dev->dev_private;
7862         uint32_t pipeconf;
7863
7864         pipeconf = 0;
7865
7866         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7867             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7868                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7869
7870         if (intel_crtc->config->double_wide)
7871                 pipeconf |= PIPECONF_DOUBLE_WIDE;
7872
7873         /* only g4x and later have fancy bpc/dither controls */
7874         if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
7875                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7876                 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7877                         pipeconf |= PIPECONF_DITHER_EN |
7878                                     PIPECONF_DITHER_TYPE_SP;
7879
7880                 switch (intel_crtc->config->pipe_bpp) {
7881                 case 18:
7882                         pipeconf |= PIPECONF_6BPC;
7883                         break;
7884                 case 24:
7885                         pipeconf |= PIPECONF_8BPC;
7886                         break;
7887                 case 30:
7888                         pipeconf |= PIPECONF_10BPC;
7889                         break;
7890                 default:
7891                         /* Case prevented by intel_choose_pipe_bpp_dither. */
7892                         BUG();
7893                 }
7894         }
7895
7896         if (HAS_PIPE_CXSR(dev)) {
7897                 if (intel_crtc->lowfreq_avail) {
7898                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7899                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7900                 } else {
7901                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7902                 }
7903         }
7904
7905         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7906                 if (INTEL_INFO(dev)->gen < 4 ||
7907                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7908                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7909                 else
7910                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7911         } else
7912                 pipeconf |= PIPECONF_PROGRESSIVE;
7913
7914         if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
7915              intel_crtc->config->limited_color_range)
7916                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7917
7918         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7919         POSTING_READ(PIPECONF(intel_crtc->pipe));
7920 }
7921
7922 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
7923                                    struct intel_crtc_state *crtc_state)
7924 {
7925         struct drm_device *dev = crtc->base.dev;
7926         struct drm_i915_private *dev_priv = dev->dev_private;
7927         const struct intel_limit *limit;
7928         int refclk = 48000;
7929
7930         memset(&crtc_state->dpll_hw_state, 0,
7931                sizeof(crtc_state->dpll_hw_state));
7932
7933         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7934                 if (intel_panel_use_ssc(dev_priv)) {
7935                         refclk = dev_priv->vbt.lvds_ssc_freq;
7936                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7937                 }
7938
7939                 limit = &intel_limits_i8xx_lvds;
7940         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) {
7941                 limit = &intel_limits_i8xx_dvo;
7942         } else {
7943                 limit = &intel_limits_i8xx_dac;
7944         }
7945
7946         if (!crtc_state->clock_set &&
7947             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7948                                  refclk, NULL, &crtc_state->dpll)) {
7949                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7950                 return -EINVAL;
7951         }
7952
7953         i8xx_compute_dpll(crtc, crtc_state, NULL);
7954
7955         return 0;
7956 }
7957
7958 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
7959                                   struct intel_crtc_state *crtc_state)
7960 {
7961         struct drm_device *dev = crtc->base.dev;
7962         struct drm_i915_private *dev_priv = dev->dev_private;
7963         const struct intel_limit *limit;
7964         int refclk = 96000;
7965
7966         memset(&crtc_state->dpll_hw_state, 0,
7967                sizeof(crtc_state->dpll_hw_state));
7968
7969         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7970                 if (intel_panel_use_ssc(dev_priv)) {
7971                         refclk = dev_priv->vbt.lvds_ssc_freq;
7972                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7973                 }
7974
7975                 if (intel_is_dual_link_lvds(dev))
7976                         limit = &intel_limits_g4x_dual_channel_lvds;
7977                 else
7978                         limit = &intel_limits_g4x_single_channel_lvds;
7979         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
7980                    intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
7981                 limit = &intel_limits_g4x_hdmi;
7982         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
7983                 limit = &intel_limits_g4x_sdvo;
7984         } else {
7985                 /* The option is for other outputs */
7986                 limit = &intel_limits_i9xx_sdvo;
7987         }
7988
7989         if (!crtc_state->clock_set &&
7990             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7991                                 refclk, NULL, &crtc_state->dpll)) {
7992                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7993                 return -EINVAL;
7994         }
7995
7996         i9xx_compute_dpll(crtc, crtc_state, NULL);
7997
7998         return 0;
7999 }
8000
8001 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
8002                                   struct intel_crtc_state *crtc_state)
8003 {
8004         struct drm_device *dev = crtc->base.dev;
8005         struct drm_i915_private *dev_priv = dev->dev_private;
8006         const struct intel_limit *limit;
8007         int refclk = 96000;
8008
8009         memset(&crtc_state->dpll_hw_state, 0,
8010                sizeof(crtc_state->dpll_hw_state));
8011
8012         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8013                 if (intel_panel_use_ssc(dev_priv)) {
8014                         refclk = dev_priv->vbt.lvds_ssc_freq;
8015                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8016                 }
8017
8018                 limit = &intel_limits_pineview_lvds;
8019         } else {
8020                 limit = &intel_limits_pineview_sdvo;
8021         }
8022
8023         if (!crtc_state->clock_set &&
8024             !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8025                                 refclk, NULL, &crtc_state->dpll)) {
8026                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8027                 return -EINVAL;
8028         }
8029
8030         i9xx_compute_dpll(crtc, crtc_state, NULL);
8031
8032         return 0;
8033 }
8034
8035 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
8036                                    struct intel_crtc_state *crtc_state)
8037 {
8038         struct drm_device *dev = crtc->base.dev;
8039         struct drm_i915_private *dev_priv = dev->dev_private;
8040         const struct intel_limit *limit;
8041         int refclk = 96000;
8042
8043         memset(&crtc_state->dpll_hw_state, 0,
8044                sizeof(crtc_state->dpll_hw_state));
8045
8046         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8047                 if (intel_panel_use_ssc(dev_priv)) {
8048                         refclk = dev_priv->vbt.lvds_ssc_freq;
8049                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8050                 }
8051
8052                 limit = &intel_limits_i9xx_lvds;
8053         } else {
8054                 limit = &intel_limits_i9xx_sdvo;
8055         }
8056
8057         if (!crtc_state->clock_set &&
8058             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8059                                  refclk, NULL, &crtc_state->dpll)) {
8060                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8061                 return -EINVAL;
8062         }
8063
8064         i9xx_compute_dpll(crtc, crtc_state, NULL);
8065
8066         return 0;
8067 }
8068
8069 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
8070                                   struct intel_crtc_state *crtc_state)
8071 {
8072         int refclk = 100000;
8073         const struct intel_limit *limit = &intel_limits_chv;
8074
8075         memset(&crtc_state->dpll_hw_state, 0,
8076                sizeof(crtc_state->dpll_hw_state));
8077
8078         if (!crtc_state->clock_set &&
8079             !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8080                                 refclk, NULL, &crtc_state->dpll)) {
8081                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8082                 return -EINVAL;
8083         }
8084
8085         chv_compute_dpll(crtc, crtc_state);
8086
8087         return 0;
8088 }
8089
8090 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
8091                                   struct intel_crtc_state *crtc_state)
8092 {
8093         int refclk = 100000;
8094         const struct intel_limit *limit = &intel_limits_vlv;
8095
8096         memset(&crtc_state->dpll_hw_state, 0,
8097                sizeof(crtc_state->dpll_hw_state));
8098
8099         if (!crtc_state->clock_set &&
8100             !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8101                                 refclk, NULL, &crtc_state->dpll)) {
8102                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8103                 return -EINVAL;
8104         }
8105
8106         vlv_compute_dpll(crtc, crtc_state);
8107
8108         return 0;
8109 }
8110
8111 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
8112                                  struct intel_crtc_state *pipe_config)
8113 {
8114         struct drm_device *dev = crtc->base.dev;
8115         struct drm_i915_private *dev_priv = dev->dev_private;
8116         uint32_t tmp;
8117
8118         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
8119                 return;
8120
8121         tmp = I915_READ(PFIT_CONTROL);
8122         if (!(tmp & PFIT_ENABLE))
8123                 return;
8124
8125         /* Check whether the pfit is attached to our pipe. */
8126         if (INTEL_INFO(dev)->gen < 4) {
8127                 if (crtc->pipe != PIPE_B)
8128                         return;
8129         } else {
8130                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
8131                         return;
8132         }
8133
8134         pipe_config->gmch_pfit.control = tmp;
8135         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
8136 }
8137
8138 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
8139                                struct intel_crtc_state *pipe_config)
8140 {
8141         struct drm_device *dev = crtc->base.dev;
8142         struct drm_i915_private *dev_priv = dev->dev_private;
8143         int pipe = pipe_config->cpu_transcoder;
8144         struct dpll clock;
8145         u32 mdiv;
8146         int refclk = 100000;
8147
8148         /* In case of DSI, DPLL will not be used */
8149         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8150                 return;
8151
8152         mutex_lock(&dev_priv->sb_lock);
8153         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
8154         mutex_unlock(&dev_priv->sb_lock);
8155
8156         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8157         clock.m2 = mdiv & DPIO_M2DIV_MASK;
8158         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8159         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8160         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8161
8162         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
8163 }
8164
8165 static void
8166 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8167                               struct intel_initial_plane_config *plane_config)
8168 {
8169         struct drm_device *dev = crtc->base.dev;
8170         struct drm_i915_private *dev_priv = dev->dev_private;
8171         u32 val, base, offset;
8172         int pipe = crtc->pipe, plane = crtc->plane;
8173         int fourcc, pixel_format;
8174         unsigned int aligned_height;
8175         struct drm_framebuffer *fb;
8176         struct intel_framebuffer *intel_fb;
8177
8178         val = I915_READ(DSPCNTR(plane));
8179         if (!(val & DISPLAY_PLANE_ENABLE))
8180                 return;
8181
8182         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8183         if (!intel_fb) {
8184                 DRM_DEBUG_KMS("failed to alloc fb\n");
8185                 return;
8186         }
8187
8188         fb = &intel_fb->base;
8189
8190         if (INTEL_INFO(dev)->gen >= 4) {
8191                 if (val & DISPPLANE_TILED) {
8192                         plane_config->tiling = I915_TILING_X;
8193                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8194                 }
8195         }
8196
8197         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8198         fourcc = i9xx_format_to_fourcc(pixel_format);
8199         fb->pixel_format = fourcc;
8200         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8201
8202         if (INTEL_INFO(dev)->gen >= 4) {
8203                 if (plane_config->tiling)
8204                         offset = I915_READ(DSPTILEOFF(plane));
8205                 else
8206                         offset = I915_READ(DSPLINOFF(plane));
8207                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8208         } else {
8209                 base = I915_READ(DSPADDR(plane));
8210         }
8211         plane_config->base = base;
8212
8213         val = I915_READ(PIPESRC(pipe));
8214         fb->width = ((val >> 16) & 0xfff) + 1;
8215         fb->height = ((val >> 0) & 0xfff) + 1;
8216
8217         val = I915_READ(DSPSTRIDE(pipe));
8218         fb->pitches[0] = val & 0xffffffc0;
8219
8220         aligned_height = intel_fb_align_height(dev, fb->height,
8221                                                fb->pixel_format,
8222                                                fb->modifier[0]);
8223
8224         plane_config->size = fb->pitches[0] * aligned_height;
8225
8226         DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8227                       pipe_name(pipe), plane, fb->width, fb->height,
8228                       fb->bits_per_pixel, base, fb->pitches[0],
8229                       plane_config->size);
8230
8231         plane_config->fb = intel_fb;
8232 }
8233
8234 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8235                                struct intel_crtc_state *pipe_config)
8236 {
8237         struct drm_device *dev = crtc->base.dev;
8238         struct drm_i915_private *dev_priv = dev->dev_private;
8239         int pipe = pipe_config->cpu_transcoder;
8240         enum dpio_channel port = vlv_pipe_to_channel(pipe);
8241         struct dpll clock;
8242         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8243         int refclk = 100000;
8244
8245         /* In case of DSI, DPLL will not be used */
8246         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8247                 return;
8248
8249         mutex_lock(&dev_priv->sb_lock);
8250         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8251         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8252         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8253         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8254         pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8255         mutex_unlock(&dev_priv->sb_lock);
8256
8257         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8258         clock.m2 = (pll_dw0 & 0xff) << 22;
8259         if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8260                 clock.m2 |= pll_dw2 & 0x3fffff;
8261         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8262         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8263         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8264
8265         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8266 }
8267
8268 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8269                                  struct intel_crtc_state *pipe_config)
8270 {
8271         struct drm_device *dev = crtc->base.dev;
8272         struct drm_i915_private *dev_priv = dev->dev_private;
8273         enum intel_display_power_domain power_domain;
8274         uint32_t tmp;
8275         bool ret;
8276
8277         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8278         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8279                 return false;
8280
8281         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8282         pipe_config->shared_dpll = NULL;
8283
8284         ret = false;
8285
8286         tmp = I915_READ(PIPECONF(crtc->pipe));
8287         if (!(tmp & PIPECONF_ENABLE))
8288                 goto out;
8289
8290         if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
8291                 switch (tmp & PIPECONF_BPC_MASK) {
8292                 case PIPECONF_6BPC:
8293                         pipe_config->pipe_bpp = 18;
8294                         break;
8295                 case PIPECONF_8BPC:
8296                         pipe_config->pipe_bpp = 24;
8297                         break;
8298                 case PIPECONF_10BPC:
8299                         pipe_config->pipe_bpp = 30;
8300                         break;
8301                 default:
8302                         break;
8303                 }
8304         }
8305
8306         if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
8307             (tmp & PIPECONF_COLOR_RANGE_SELECT))
8308                 pipe_config->limited_color_range = true;
8309
8310         if (INTEL_INFO(dev)->gen < 4)
8311                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8312
8313         intel_get_pipe_timings(crtc, pipe_config);
8314         intel_get_pipe_src_size(crtc, pipe_config);
8315
8316         i9xx_get_pfit_config(crtc, pipe_config);
8317
8318         if (INTEL_INFO(dev)->gen >= 4) {
8319                 /* No way to read it out on pipes B and C */
8320                 if (IS_CHERRYVIEW(dev) && crtc->pipe != PIPE_A)
8321                         tmp = dev_priv->chv_dpll_md[crtc->pipe];
8322                 else
8323                         tmp = I915_READ(DPLL_MD(crtc->pipe));
8324                 pipe_config->pixel_multiplier =
8325                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8326                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8327                 pipe_config->dpll_hw_state.dpll_md = tmp;
8328         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8329                 tmp = I915_READ(DPLL(crtc->pipe));
8330                 pipe_config->pixel_multiplier =
8331                         ((tmp & SDVO_MULTIPLIER_MASK)
8332                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8333         } else {
8334                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8335                  * port and will be fixed up in the encoder->get_config
8336                  * function. */
8337                 pipe_config->pixel_multiplier = 1;
8338         }
8339         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8340         if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
8341                 /*
8342                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8343                  * on 830. Filter it out here so that we don't
8344                  * report errors due to that.
8345                  */
8346                 if (IS_I830(dev))
8347                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8348
8349                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8350                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8351         } else {
8352                 /* Mask out read-only status bits. */
8353                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8354                                                      DPLL_PORTC_READY_MASK |
8355                                                      DPLL_PORTB_READY_MASK);
8356         }
8357
8358         if (IS_CHERRYVIEW(dev))
8359                 chv_crtc_clock_get(crtc, pipe_config);
8360         else if (IS_VALLEYVIEW(dev))
8361                 vlv_crtc_clock_get(crtc, pipe_config);
8362         else
8363                 i9xx_crtc_clock_get(crtc, pipe_config);
8364
8365         /*
8366          * Normally the dotclock is filled in by the encoder .get_config()
8367          * but in case the pipe is enabled w/o any ports we need a sane
8368          * default.
8369          */
8370         pipe_config->base.adjusted_mode.crtc_clock =
8371                 pipe_config->port_clock / pipe_config->pixel_multiplier;
8372
8373         ret = true;
8374
8375 out:
8376         intel_display_power_put(dev_priv, power_domain);
8377
8378         return ret;
8379 }
8380
8381 static void ironlake_init_pch_refclk(struct drm_device *dev)
8382 {
8383         struct drm_i915_private *dev_priv = dev->dev_private;
8384         struct intel_encoder *encoder;
8385         int i;
8386         u32 val, final;
8387         bool has_lvds = false;
8388         bool has_cpu_edp = false;
8389         bool has_panel = false;
8390         bool has_ck505 = false;
8391         bool can_ssc = false;
8392         bool using_ssc_source = false;
8393
8394         /* We need to take the global config into account */
8395         for_each_intel_encoder(dev, encoder) {
8396                 switch (encoder->type) {
8397                 case INTEL_OUTPUT_LVDS:
8398                         has_panel = true;
8399                         has_lvds = true;
8400                         break;
8401                 case INTEL_OUTPUT_EDP:
8402                         has_panel = true;
8403                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8404                                 has_cpu_edp = true;
8405                         break;
8406                 default:
8407                         break;
8408                 }
8409         }
8410
8411         if (HAS_PCH_IBX(dev)) {
8412                 has_ck505 = dev_priv->vbt.display_clock_mode;
8413                 can_ssc = has_ck505;
8414         } else {
8415                 has_ck505 = false;
8416                 can_ssc = true;
8417         }
8418
8419         /* Check if any DPLLs are using the SSC source */
8420         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8421                 u32 temp = I915_READ(PCH_DPLL(i));
8422
8423                 if (!(temp & DPLL_VCO_ENABLE))
8424                         continue;
8425
8426                 if ((temp & PLL_REF_INPUT_MASK) ==
8427                     PLLB_REF_INPUT_SPREADSPECTRUMIN) {
8428                         using_ssc_source = true;
8429                         break;
8430                 }
8431         }
8432
8433         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
8434                       has_panel, has_lvds, has_ck505, using_ssc_source);
8435
8436         /* Ironlake: try to setup display ref clock before DPLL
8437          * enabling. This is only under driver's control after
8438          * PCH B stepping, previous chipset stepping should be
8439          * ignoring this setting.
8440          */
8441         val = I915_READ(PCH_DREF_CONTROL);
8442
8443         /* As we must carefully and slowly disable/enable each source in turn,
8444          * compute the final state we want first and check if we need to
8445          * make any changes at all.
8446          */
8447         final = val;
8448         final &= ~DREF_NONSPREAD_SOURCE_MASK;
8449         if (has_ck505)
8450                 final |= DREF_NONSPREAD_CK505_ENABLE;
8451         else
8452                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8453
8454         final &= ~DREF_SSC_SOURCE_MASK;
8455         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8456         final &= ~DREF_SSC1_ENABLE;
8457
8458         if (has_panel) {
8459                 final |= DREF_SSC_SOURCE_ENABLE;
8460
8461                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8462                         final |= DREF_SSC1_ENABLE;
8463
8464                 if (has_cpu_edp) {
8465                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
8466                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8467                         else
8468                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8469                 } else
8470                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8471         } else if (using_ssc_source) {
8472                 final |= DREF_SSC_SOURCE_ENABLE;
8473                 final |= DREF_SSC1_ENABLE;
8474         }
8475
8476         if (final == val)
8477                 return;
8478
8479         /* Always enable nonspread source */
8480         val &= ~DREF_NONSPREAD_SOURCE_MASK;
8481
8482         if (has_ck505)
8483                 val |= DREF_NONSPREAD_CK505_ENABLE;
8484         else
8485                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8486
8487         if (has_panel) {
8488                 val &= ~DREF_SSC_SOURCE_MASK;
8489                 val |= DREF_SSC_SOURCE_ENABLE;
8490
8491                 /* SSC must be turned on before enabling the CPU output  */
8492                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8493                         DRM_DEBUG_KMS("Using SSC on panel\n");
8494                         val |= DREF_SSC1_ENABLE;
8495                 } else
8496                         val &= ~DREF_SSC1_ENABLE;
8497
8498                 /* Get SSC going before enabling the outputs */
8499                 I915_WRITE(PCH_DREF_CONTROL, val);
8500                 POSTING_READ(PCH_DREF_CONTROL);
8501                 udelay(200);
8502
8503                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8504
8505                 /* Enable CPU source on CPU attached eDP */
8506                 if (has_cpu_edp) {
8507                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8508                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
8509                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8510                         } else
8511                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8512                 } else
8513                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8514
8515                 I915_WRITE(PCH_DREF_CONTROL, val);
8516                 POSTING_READ(PCH_DREF_CONTROL);
8517                 udelay(200);
8518         } else {
8519                 DRM_DEBUG_KMS("Disabling CPU source output\n");
8520
8521                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8522
8523                 /* Turn off CPU output */
8524                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8525
8526                 I915_WRITE(PCH_DREF_CONTROL, val);
8527                 POSTING_READ(PCH_DREF_CONTROL);
8528                 udelay(200);
8529
8530                 if (!using_ssc_source) {
8531                         DRM_DEBUG_KMS("Disabling SSC source\n");
8532
8533                         /* Turn off the SSC source */
8534                         val &= ~DREF_SSC_SOURCE_MASK;
8535                         val |= DREF_SSC_SOURCE_DISABLE;
8536
8537                         /* Turn off SSC1 */
8538                         val &= ~DREF_SSC1_ENABLE;
8539
8540                         I915_WRITE(PCH_DREF_CONTROL, val);
8541                         POSTING_READ(PCH_DREF_CONTROL);
8542                         udelay(200);
8543                 }
8544         }
8545
8546         BUG_ON(val != final);
8547 }
8548
8549 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8550 {
8551         uint32_t tmp;
8552
8553         tmp = I915_READ(SOUTH_CHICKEN2);
8554         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8555         I915_WRITE(SOUTH_CHICKEN2, tmp);
8556
8557         if (wait_for_us(I915_READ(SOUTH_CHICKEN2) &
8558                         FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8559                 DRM_ERROR("FDI mPHY reset assert timeout\n");
8560
8561         tmp = I915_READ(SOUTH_CHICKEN2);
8562         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8563         I915_WRITE(SOUTH_CHICKEN2, tmp);
8564
8565         if (wait_for_us((I915_READ(SOUTH_CHICKEN2) &
8566                          FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8567                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8568 }
8569
8570 /* WaMPhyProgramming:hsw */
8571 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8572 {
8573         uint32_t tmp;
8574
8575         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8576         tmp &= ~(0xFF << 24);
8577         tmp |= (0x12 << 24);
8578         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8579
8580         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8581         tmp |= (1 << 11);
8582         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8583
8584         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8585         tmp |= (1 << 11);
8586         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8587
8588         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8589         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8590         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8591
8592         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8593         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8594         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8595
8596         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8597         tmp &= ~(7 << 13);
8598         tmp |= (5 << 13);
8599         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8600
8601         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8602         tmp &= ~(7 << 13);
8603         tmp |= (5 << 13);
8604         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8605
8606         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8607         tmp &= ~0xFF;
8608         tmp |= 0x1C;
8609         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8610
8611         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8612         tmp &= ~0xFF;
8613         tmp |= 0x1C;
8614         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8615
8616         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8617         tmp &= ~(0xFF << 16);
8618         tmp |= (0x1C << 16);
8619         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8620
8621         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8622         tmp &= ~(0xFF << 16);
8623         tmp |= (0x1C << 16);
8624         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8625
8626         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8627         tmp |= (1 << 27);
8628         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8629
8630         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8631         tmp |= (1 << 27);
8632         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8633
8634         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8635         tmp &= ~(0xF << 28);
8636         tmp |= (4 << 28);
8637         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8638
8639         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8640         tmp &= ~(0xF << 28);
8641         tmp |= (4 << 28);
8642         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8643 }
8644
8645 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8646  * Programming" based on the parameters passed:
8647  * - Sequence to enable CLKOUT_DP
8648  * - Sequence to enable CLKOUT_DP without spread
8649  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8650  */
8651 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8652                                  bool with_fdi)
8653 {
8654         struct drm_i915_private *dev_priv = dev->dev_private;
8655         uint32_t reg, tmp;
8656
8657         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8658                 with_spread = true;
8659         if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
8660                 with_fdi = false;
8661
8662         mutex_lock(&dev_priv->sb_lock);
8663
8664         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8665         tmp &= ~SBI_SSCCTL_DISABLE;
8666         tmp |= SBI_SSCCTL_PATHALT;
8667         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8668
8669         udelay(24);
8670
8671         if (with_spread) {
8672                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8673                 tmp &= ~SBI_SSCCTL_PATHALT;
8674                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8675
8676                 if (with_fdi) {
8677                         lpt_reset_fdi_mphy(dev_priv);
8678                         lpt_program_fdi_mphy(dev_priv);
8679                 }
8680         }
8681
8682         reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8683         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8684         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8685         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8686
8687         mutex_unlock(&dev_priv->sb_lock);
8688 }
8689
8690 /* Sequence to disable CLKOUT_DP */
8691 static void lpt_disable_clkout_dp(struct drm_device *dev)
8692 {
8693         struct drm_i915_private *dev_priv = dev->dev_private;
8694         uint32_t reg, tmp;
8695
8696         mutex_lock(&dev_priv->sb_lock);
8697
8698         reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8699         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8700         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8701         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8702
8703         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8704         if (!(tmp & SBI_SSCCTL_DISABLE)) {
8705                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8706                         tmp |= SBI_SSCCTL_PATHALT;
8707                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8708                         udelay(32);
8709                 }
8710                 tmp |= SBI_SSCCTL_DISABLE;
8711                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8712         }
8713
8714         mutex_unlock(&dev_priv->sb_lock);
8715 }
8716
8717 #define BEND_IDX(steps) ((50 + (steps)) / 5)
8718
8719 static const uint16_t sscdivintphase[] = {
8720         [BEND_IDX( 50)] = 0x3B23,
8721         [BEND_IDX( 45)] = 0x3B23,
8722         [BEND_IDX( 40)] = 0x3C23,
8723         [BEND_IDX( 35)] = 0x3C23,
8724         [BEND_IDX( 30)] = 0x3D23,
8725         [BEND_IDX( 25)] = 0x3D23,
8726         [BEND_IDX( 20)] = 0x3E23,
8727         [BEND_IDX( 15)] = 0x3E23,
8728         [BEND_IDX( 10)] = 0x3F23,
8729         [BEND_IDX(  5)] = 0x3F23,
8730         [BEND_IDX(  0)] = 0x0025,
8731         [BEND_IDX( -5)] = 0x0025,
8732         [BEND_IDX(-10)] = 0x0125,
8733         [BEND_IDX(-15)] = 0x0125,
8734         [BEND_IDX(-20)] = 0x0225,
8735         [BEND_IDX(-25)] = 0x0225,
8736         [BEND_IDX(-30)] = 0x0325,
8737         [BEND_IDX(-35)] = 0x0325,
8738         [BEND_IDX(-40)] = 0x0425,
8739         [BEND_IDX(-45)] = 0x0425,
8740         [BEND_IDX(-50)] = 0x0525,
8741 };
8742
8743 /*
8744  * Bend CLKOUT_DP
8745  * steps -50 to 50 inclusive, in steps of 5
8746  * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
8747  * change in clock period = -(steps / 10) * 5.787 ps
8748  */
8749 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
8750 {
8751         uint32_t tmp;
8752         int idx = BEND_IDX(steps);
8753
8754         if (WARN_ON(steps % 5 != 0))
8755                 return;
8756
8757         if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
8758                 return;
8759
8760         mutex_lock(&dev_priv->sb_lock);
8761
8762         if (steps % 10 != 0)
8763                 tmp = 0xAAAAAAAB;
8764         else
8765                 tmp = 0x00000000;
8766         intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
8767
8768         tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
8769         tmp &= 0xffff0000;
8770         tmp |= sscdivintphase[idx];
8771         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
8772
8773         mutex_unlock(&dev_priv->sb_lock);
8774 }
8775
8776 #undef BEND_IDX
8777
8778 static void lpt_init_pch_refclk(struct drm_device *dev)
8779 {
8780         struct intel_encoder *encoder;
8781         bool has_vga = false;
8782
8783         for_each_intel_encoder(dev, encoder) {
8784                 switch (encoder->type) {
8785                 case INTEL_OUTPUT_ANALOG:
8786                         has_vga = true;
8787                         break;
8788                 default:
8789                         break;
8790                 }
8791         }
8792
8793         if (has_vga) {
8794                 lpt_bend_clkout_dp(to_i915(dev), 0);
8795                 lpt_enable_clkout_dp(dev, true, true);
8796         } else {
8797                 lpt_disable_clkout_dp(dev);
8798         }
8799 }
8800
8801 /*
8802  * Initialize reference clocks when the driver loads
8803  */
8804 void intel_init_pch_refclk(struct drm_device *dev)
8805 {
8806         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8807                 ironlake_init_pch_refclk(dev);
8808         else if (HAS_PCH_LPT(dev))
8809                 lpt_init_pch_refclk(dev);
8810 }
8811
8812 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8813 {
8814         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8815         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8816         int pipe = intel_crtc->pipe;
8817         uint32_t val;
8818
8819         val = 0;
8820
8821         switch (intel_crtc->config->pipe_bpp) {
8822         case 18:
8823                 val |= PIPECONF_6BPC;
8824                 break;
8825         case 24:
8826                 val |= PIPECONF_8BPC;
8827                 break;
8828         case 30:
8829                 val |= PIPECONF_10BPC;
8830                 break;
8831         case 36:
8832                 val |= PIPECONF_12BPC;
8833                 break;
8834         default:
8835                 /* Case prevented by intel_choose_pipe_bpp_dither. */
8836                 BUG();
8837         }
8838
8839         if (intel_crtc->config->dither)
8840                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8841
8842         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8843                 val |= PIPECONF_INTERLACED_ILK;
8844         else
8845                 val |= PIPECONF_PROGRESSIVE;
8846
8847         if (intel_crtc->config->limited_color_range)
8848                 val |= PIPECONF_COLOR_RANGE_SELECT;
8849
8850         I915_WRITE(PIPECONF(pipe), val);
8851         POSTING_READ(PIPECONF(pipe));
8852 }
8853
8854 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8855 {
8856         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8857         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8858         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8859         u32 val = 0;
8860
8861         if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
8862                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8863
8864         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8865                 val |= PIPECONF_INTERLACED_ILK;
8866         else
8867                 val |= PIPECONF_PROGRESSIVE;
8868
8869         I915_WRITE(PIPECONF(cpu_transcoder), val);
8870         POSTING_READ(PIPECONF(cpu_transcoder));
8871 }
8872
8873 static void haswell_set_pipemisc(struct drm_crtc *crtc)
8874 {
8875         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8876         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8877
8878         if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
8879                 u32 val = 0;
8880
8881                 switch (intel_crtc->config->pipe_bpp) {
8882                 case 18:
8883                         val |= PIPEMISC_DITHER_6_BPC;
8884                         break;
8885                 case 24:
8886                         val |= PIPEMISC_DITHER_8_BPC;
8887                         break;
8888                 case 30:
8889                         val |= PIPEMISC_DITHER_10_BPC;
8890                         break;
8891                 case 36:
8892                         val |= PIPEMISC_DITHER_12_BPC;
8893                         break;
8894                 default:
8895                         /* Case prevented by pipe_config_set_bpp. */
8896                         BUG();
8897                 }
8898
8899                 if (intel_crtc->config->dither)
8900                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8901
8902                 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
8903         }
8904 }
8905
8906 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8907 {
8908         /*
8909          * Account for spread spectrum to avoid
8910          * oversubscribing the link. Max center spread
8911          * is 2.5%; use 5% for safety's sake.
8912          */
8913         u32 bps = target_clock * bpp * 21 / 20;
8914         return DIV_ROUND_UP(bps, link_bw * 8);
8915 }
8916
8917 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8918 {
8919         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8920 }
8921
8922 static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8923                                   struct intel_crtc_state *crtc_state,
8924                                   struct dpll *reduced_clock)
8925 {
8926         struct drm_crtc *crtc = &intel_crtc->base;
8927         struct drm_device *dev = crtc->dev;
8928         struct drm_i915_private *dev_priv = dev->dev_private;
8929         struct drm_atomic_state *state = crtc_state->base.state;
8930         struct drm_connector *connector;
8931         struct drm_connector_state *connector_state;
8932         struct intel_encoder *encoder;
8933         u32 dpll, fp, fp2;
8934         int factor, i;
8935         bool is_lvds = false, is_sdvo = false;
8936
8937         for_each_connector_in_state(state, connector, connector_state, i) {
8938                 if (connector_state->crtc != crtc_state->base.crtc)
8939                         continue;
8940
8941                 encoder = to_intel_encoder(connector_state->best_encoder);
8942
8943                 switch (encoder->type) {
8944                 case INTEL_OUTPUT_LVDS:
8945                         is_lvds = true;
8946                         break;
8947                 case INTEL_OUTPUT_SDVO:
8948                 case INTEL_OUTPUT_HDMI:
8949                         is_sdvo = true;
8950                         break;
8951                 default:
8952                         break;
8953                 }
8954         }
8955
8956         /* Enable autotuning of the PLL clock (if permissible) */
8957         factor = 21;
8958         if (is_lvds) {
8959                 if ((intel_panel_use_ssc(dev_priv) &&
8960                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
8961                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8962                         factor = 25;
8963         } else if (crtc_state->sdvo_tv_clock)
8964                 factor = 20;
8965
8966         fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8967
8968         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8969                 fp |= FP_CB_TUNE;
8970
8971         if (reduced_clock) {
8972                 fp2 = i9xx_dpll_compute_fp(reduced_clock);
8973
8974                 if (reduced_clock->m < factor * reduced_clock->n)
8975                         fp2 |= FP_CB_TUNE;
8976         } else {
8977                 fp2 = fp;
8978         }
8979
8980         dpll = 0;
8981
8982         if (is_lvds)
8983                 dpll |= DPLLB_MODE_LVDS;
8984         else
8985                 dpll |= DPLLB_MODE_DAC_SERIAL;
8986
8987         dpll |= (crtc_state->pixel_multiplier - 1)
8988                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8989
8990         if (is_sdvo)
8991                 dpll |= DPLL_SDVO_HIGH_SPEED;
8992         if (crtc_state->has_dp_encoder)
8993                 dpll |= DPLL_SDVO_HIGH_SPEED;
8994
8995         /* compute bitmask from p1 value */
8996         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8997         /* also FPA1 */
8998         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8999
9000         switch (crtc_state->dpll.p2) {
9001         case 5:
9002                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
9003                 break;
9004         case 7:
9005                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
9006                 break;
9007         case 10:
9008                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
9009                 break;
9010         case 14:
9011                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
9012                 break;
9013         }
9014
9015         if (is_lvds && intel_panel_use_ssc(dev_priv))
9016                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
9017         else
9018                 dpll |= PLL_REF_INPUT_DREFCLK;
9019
9020         dpll |= DPLL_VCO_ENABLE;
9021
9022         crtc_state->dpll_hw_state.dpll = dpll;
9023         crtc_state->dpll_hw_state.fp0 = fp;
9024         crtc_state->dpll_hw_state.fp1 = fp2;
9025 }
9026
9027 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
9028                                        struct intel_crtc_state *crtc_state)
9029 {
9030         struct drm_device *dev = crtc->base.dev;
9031         struct drm_i915_private *dev_priv = dev->dev_private;
9032         struct dpll reduced_clock;
9033         bool has_reduced_clock = false;
9034         struct intel_shared_dpll *pll;
9035         const struct intel_limit *limit;
9036         int refclk = 120000;
9037
9038         memset(&crtc_state->dpll_hw_state, 0,
9039                sizeof(crtc_state->dpll_hw_state));
9040
9041         crtc->lowfreq_avail = false;
9042
9043         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
9044         if (!crtc_state->has_pch_encoder)
9045                 return 0;
9046
9047         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9048                 if (intel_panel_use_ssc(dev_priv)) {
9049                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
9050                                       dev_priv->vbt.lvds_ssc_freq);
9051                         refclk = dev_priv->vbt.lvds_ssc_freq;
9052                 }
9053
9054                 if (intel_is_dual_link_lvds(dev)) {
9055                         if (refclk == 100000)
9056                                 limit = &intel_limits_ironlake_dual_lvds_100m;
9057                         else
9058                                 limit = &intel_limits_ironlake_dual_lvds;
9059                 } else {
9060                         if (refclk == 100000)
9061                                 limit = &intel_limits_ironlake_single_lvds_100m;
9062                         else
9063                                 limit = &intel_limits_ironlake_single_lvds;
9064                 }
9065         } else {
9066                 limit = &intel_limits_ironlake_dac;
9067         }
9068
9069         if (!crtc_state->clock_set &&
9070             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9071                                 refclk, NULL, &crtc_state->dpll)) {
9072                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
9073                 return -EINVAL;
9074         }
9075
9076         ironlake_compute_dpll(crtc, crtc_state,
9077                               has_reduced_clock ? &reduced_clock : NULL);
9078
9079         pll = intel_get_shared_dpll(crtc, crtc_state, NULL);
9080         if (pll == NULL) {
9081                 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
9082                                  pipe_name(crtc->pipe));
9083                 return -EINVAL;
9084         }
9085
9086         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
9087             has_reduced_clock)
9088                 crtc->lowfreq_avail = true;
9089
9090         return 0;
9091 }
9092
9093 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
9094                                          struct intel_link_m_n *m_n)
9095 {
9096         struct drm_device *dev = crtc->base.dev;
9097         struct drm_i915_private *dev_priv = dev->dev_private;
9098         enum pipe pipe = crtc->pipe;
9099
9100         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
9101         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
9102         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
9103                 & ~TU_SIZE_MASK;
9104         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
9105         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
9106                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9107 }
9108
9109 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
9110                                          enum transcoder transcoder,
9111                                          struct intel_link_m_n *m_n,
9112                                          struct intel_link_m_n *m2_n2)
9113 {
9114         struct drm_device *dev = crtc->base.dev;
9115         struct drm_i915_private *dev_priv = dev->dev_private;
9116         enum pipe pipe = crtc->pipe;
9117
9118         if (INTEL_INFO(dev)->gen >= 5) {
9119                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
9120                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
9121                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
9122                         & ~TU_SIZE_MASK;
9123                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
9124                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
9125                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9126                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
9127                  * gen < 8) and if DRRS is supported (to make sure the
9128                  * registers are not unnecessarily read).
9129                  */
9130                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
9131                         crtc->config->has_drrs) {
9132                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9133                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9134                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9135                                         & ~TU_SIZE_MASK;
9136                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9137                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9138                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9139                 }
9140         } else {
9141                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9142                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9143                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9144                         & ~TU_SIZE_MASK;
9145                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9146                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9147                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9148         }
9149 }
9150
9151 void intel_dp_get_m_n(struct intel_crtc *crtc,
9152                       struct intel_crtc_state *pipe_config)
9153 {
9154         if (pipe_config->has_pch_encoder)
9155                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9156         else
9157                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9158                                              &pipe_config->dp_m_n,
9159                                              &pipe_config->dp_m2_n2);
9160 }
9161
9162 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9163                                         struct intel_crtc_state *pipe_config)
9164 {
9165         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9166                                      &pipe_config->fdi_m_n, NULL);
9167 }
9168
9169 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9170                                     struct intel_crtc_state *pipe_config)
9171 {
9172         struct drm_device *dev = crtc->base.dev;
9173         struct drm_i915_private *dev_priv = dev->dev_private;
9174         struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9175         uint32_t ps_ctrl = 0;
9176         int id = -1;
9177         int i;
9178
9179         /* find scaler attached to this pipe */
9180         for (i = 0; i < crtc->num_scalers; i++) {
9181                 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9182                 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9183                         id = i;
9184                         pipe_config->pch_pfit.enabled = true;
9185                         pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9186                         pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9187                         break;
9188                 }
9189         }
9190
9191         scaler_state->scaler_id = id;
9192         if (id >= 0) {
9193                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9194         } else {
9195                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9196         }
9197 }
9198
9199 static void
9200 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9201                                  struct intel_initial_plane_config *plane_config)
9202 {
9203         struct drm_device *dev = crtc->base.dev;
9204         struct drm_i915_private *dev_priv = dev->dev_private;
9205         u32 val, base, offset, stride_mult, tiling;
9206         int pipe = crtc->pipe;
9207         int fourcc, pixel_format;
9208         unsigned int aligned_height;
9209         struct drm_framebuffer *fb;
9210         struct intel_framebuffer *intel_fb;
9211
9212         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9213         if (!intel_fb) {
9214                 DRM_DEBUG_KMS("failed to alloc fb\n");
9215                 return;
9216         }
9217
9218         fb = &intel_fb->base;
9219
9220         val = I915_READ(PLANE_CTL(pipe, 0));
9221         if (!(val & PLANE_CTL_ENABLE))
9222                 goto error;
9223
9224         pixel_format = val & PLANE_CTL_FORMAT_MASK;
9225         fourcc = skl_format_to_fourcc(pixel_format,
9226                                       val & PLANE_CTL_ORDER_RGBX,
9227                                       val & PLANE_CTL_ALPHA_MASK);
9228         fb->pixel_format = fourcc;
9229         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9230
9231         tiling = val & PLANE_CTL_TILED_MASK;
9232         switch (tiling) {
9233         case PLANE_CTL_TILED_LINEAR:
9234                 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9235                 break;
9236         case PLANE_CTL_TILED_X:
9237                 plane_config->tiling = I915_TILING_X;
9238                 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9239                 break;
9240         case PLANE_CTL_TILED_Y:
9241                 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9242                 break;
9243         case PLANE_CTL_TILED_YF:
9244                 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9245                 break;
9246         default:
9247                 MISSING_CASE(tiling);
9248                 goto error;
9249         }
9250
9251         base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9252         plane_config->base = base;
9253
9254         offset = I915_READ(PLANE_OFFSET(pipe, 0));
9255
9256         val = I915_READ(PLANE_SIZE(pipe, 0));
9257         fb->height = ((val >> 16) & 0xfff) + 1;
9258         fb->width = ((val >> 0) & 0x1fff) + 1;
9259
9260         val = I915_READ(PLANE_STRIDE(pipe, 0));
9261         stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
9262                                                 fb->pixel_format);
9263         fb->pitches[0] = (val & 0x3ff) * stride_mult;
9264
9265         aligned_height = intel_fb_align_height(dev, fb->height,
9266                                                fb->pixel_format,
9267                                                fb->modifier[0]);
9268
9269         plane_config->size = fb->pitches[0] * aligned_height;
9270
9271         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9272                       pipe_name(pipe), fb->width, fb->height,
9273                       fb->bits_per_pixel, base, fb->pitches[0],
9274                       plane_config->size);
9275
9276         plane_config->fb = intel_fb;
9277         return;
9278
9279 error:
9280         kfree(fb);
9281 }
9282
9283 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9284                                      struct intel_crtc_state *pipe_config)
9285 {
9286         struct drm_device *dev = crtc->base.dev;
9287         struct drm_i915_private *dev_priv = dev->dev_private;
9288         uint32_t tmp;
9289
9290         tmp = I915_READ(PF_CTL(crtc->pipe));
9291
9292         if (tmp & PF_ENABLE) {
9293                 pipe_config->pch_pfit.enabled = true;
9294                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9295                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9296
9297                 /* We currently do not free assignements of panel fitters on
9298                  * ivb/hsw (since we don't use the higher upscaling modes which
9299                  * differentiates them) so just WARN about this case for now. */
9300                 if (IS_GEN7(dev)) {
9301                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9302                                 PF_PIPE_SEL_IVB(crtc->pipe));
9303                 }
9304         }
9305 }
9306
9307 static void
9308 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9309                                   struct intel_initial_plane_config *plane_config)
9310 {
9311         struct drm_device *dev = crtc->base.dev;
9312         struct drm_i915_private *dev_priv = dev->dev_private;
9313         u32 val, base, offset;
9314         int pipe = crtc->pipe;
9315         int fourcc, pixel_format;
9316         unsigned int aligned_height;
9317         struct drm_framebuffer *fb;
9318         struct intel_framebuffer *intel_fb;
9319
9320         val = I915_READ(DSPCNTR(pipe));
9321         if (!(val & DISPLAY_PLANE_ENABLE))
9322                 return;
9323
9324         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9325         if (!intel_fb) {
9326                 DRM_DEBUG_KMS("failed to alloc fb\n");
9327                 return;
9328         }
9329
9330         fb = &intel_fb->base;
9331
9332         if (INTEL_INFO(dev)->gen >= 4) {
9333                 if (val & DISPPLANE_TILED) {
9334                         plane_config->tiling = I915_TILING_X;
9335                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9336                 }
9337         }
9338
9339         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9340         fourcc = i9xx_format_to_fourcc(pixel_format);
9341         fb->pixel_format = fourcc;
9342         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9343
9344         base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9345         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9346                 offset = I915_READ(DSPOFFSET(pipe));
9347         } else {
9348                 if (plane_config->tiling)
9349                         offset = I915_READ(DSPTILEOFF(pipe));
9350                 else
9351                         offset = I915_READ(DSPLINOFF(pipe));
9352         }
9353         plane_config->base = base;
9354
9355         val = I915_READ(PIPESRC(pipe));
9356         fb->width = ((val >> 16) & 0xfff) + 1;
9357         fb->height = ((val >> 0) & 0xfff) + 1;
9358
9359         val = I915_READ(DSPSTRIDE(pipe));
9360         fb->pitches[0] = val & 0xffffffc0;
9361
9362         aligned_height = intel_fb_align_height(dev, fb->height,
9363                                                fb->pixel_format,
9364                                                fb->modifier[0]);
9365
9366         plane_config->size = fb->pitches[0] * aligned_height;
9367
9368         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9369                       pipe_name(pipe), fb->width, fb->height,
9370                       fb->bits_per_pixel, base, fb->pitches[0],
9371                       plane_config->size);
9372
9373         plane_config->fb = intel_fb;
9374 }
9375
9376 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9377                                      struct intel_crtc_state *pipe_config)
9378 {
9379         struct drm_device *dev = crtc->base.dev;
9380         struct drm_i915_private *dev_priv = dev->dev_private;
9381         enum intel_display_power_domain power_domain;
9382         uint32_t tmp;
9383         bool ret;
9384
9385         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9386         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9387                 return false;
9388
9389         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9390         pipe_config->shared_dpll = NULL;
9391
9392         ret = false;
9393         tmp = I915_READ(PIPECONF(crtc->pipe));
9394         if (!(tmp & PIPECONF_ENABLE))
9395                 goto out;
9396
9397         switch (tmp & PIPECONF_BPC_MASK) {
9398         case PIPECONF_6BPC:
9399                 pipe_config->pipe_bpp = 18;
9400                 break;
9401         case PIPECONF_8BPC:
9402                 pipe_config->pipe_bpp = 24;
9403                 break;
9404         case PIPECONF_10BPC:
9405                 pipe_config->pipe_bpp = 30;
9406                 break;
9407         case PIPECONF_12BPC:
9408                 pipe_config->pipe_bpp = 36;
9409                 break;
9410         default:
9411                 break;
9412         }
9413
9414         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9415                 pipe_config->limited_color_range = true;
9416
9417         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9418                 struct intel_shared_dpll *pll;
9419                 enum intel_dpll_id pll_id;
9420
9421                 pipe_config->has_pch_encoder = true;
9422
9423                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9424                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9425                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9426
9427                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9428
9429                 if (HAS_PCH_IBX(dev_priv)) {
9430                         /*
9431                          * The pipe->pch transcoder and pch transcoder->pll
9432                          * mapping is fixed.
9433                          */
9434                         pll_id = (enum intel_dpll_id) crtc->pipe;
9435                 } else {
9436                         tmp = I915_READ(PCH_DPLL_SEL);
9437                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9438                                 pll_id = DPLL_ID_PCH_PLL_B;
9439                         else
9440                                 pll_id= DPLL_ID_PCH_PLL_A;
9441                 }
9442
9443                 pipe_config->shared_dpll =
9444                         intel_get_shared_dpll_by_id(dev_priv, pll_id);
9445                 pll = pipe_config->shared_dpll;
9446
9447                 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9448                                                  &pipe_config->dpll_hw_state));
9449
9450                 tmp = pipe_config->dpll_hw_state.dpll;
9451                 pipe_config->pixel_multiplier =
9452                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9453                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9454
9455                 ironlake_pch_clock_get(crtc, pipe_config);
9456         } else {
9457                 pipe_config->pixel_multiplier = 1;
9458         }
9459
9460         intel_get_pipe_timings(crtc, pipe_config);
9461         intel_get_pipe_src_size(crtc, pipe_config);
9462
9463         ironlake_get_pfit_config(crtc, pipe_config);
9464
9465         ret = true;
9466
9467 out:
9468         intel_display_power_put(dev_priv, power_domain);
9469
9470         return ret;
9471 }
9472
9473 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9474 {
9475         struct drm_device *dev = dev_priv->dev;
9476         struct intel_crtc *crtc;
9477
9478         for_each_intel_crtc(dev, crtc)
9479                 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9480                      pipe_name(crtc->pipe));
9481
9482         I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9483         I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9484         I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9485         I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9486         I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9487         I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9488              "CPU PWM1 enabled\n");
9489         if (IS_HASWELL(dev))
9490                 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9491                      "CPU PWM2 enabled\n");
9492         I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9493              "PCH PWM1 enabled\n");
9494         I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9495              "Utility pin enabled\n");
9496         I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9497
9498         /*
9499          * In theory we can still leave IRQs enabled, as long as only the HPD
9500          * interrupts remain enabled. We used to check for that, but since it's
9501          * gen-specific and since we only disable LCPLL after we fully disable
9502          * the interrupts, the check below should be enough.
9503          */
9504         I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9505 }
9506
9507 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9508 {
9509         struct drm_device *dev = dev_priv->dev;
9510
9511         if (IS_HASWELL(dev))
9512                 return I915_READ(D_COMP_HSW);
9513         else
9514                 return I915_READ(D_COMP_BDW);
9515 }
9516
9517 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9518 {
9519         struct drm_device *dev = dev_priv->dev;
9520
9521         if (IS_HASWELL(dev)) {
9522                 mutex_lock(&dev_priv->rps.hw_lock);
9523                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9524                                             val))
9525                         DRM_ERROR("Failed to write to D_COMP\n");
9526                 mutex_unlock(&dev_priv->rps.hw_lock);
9527         } else {
9528                 I915_WRITE(D_COMP_BDW, val);
9529                 POSTING_READ(D_COMP_BDW);
9530         }
9531 }
9532
9533 /*
9534  * This function implements pieces of two sequences from BSpec:
9535  * - Sequence for display software to disable LCPLL
9536  * - Sequence for display software to allow package C8+
9537  * The steps implemented here are just the steps that actually touch the LCPLL
9538  * register. Callers should take care of disabling all the display engine
9539  * functions, doing the mode unset, fixing interrupts, etc.
9540  */
9541 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9542                               bool switch_to_fclk, bool allow_power_down)
9543 {
9544         uint32_t val;
9545
9546         assert_can_disable_lcpll(dev_priv);
9547
9548         val = I915_READ(LCPLL_CTL);
9549
9550         if (switch_to_fclk) {
9551                 val |= LCPLL_CD_SOURCE_FCLK;
9552                 I915_WRITE(LCPLL_CTL, val);
9553
9554                 if (wait_for_us(I915_READ(LCPLL_CTL) &
9555                                 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9556                         DRM_ERROR("Switching to FCLK failed\n");
9557
9558                 val = I915_READ(LCPLL_CTL);
9559         }
9560
9561         val |= LCPLL_PLL_DISABLE;
9562         I915_WRITE(LCPLL_CTL, val);
9563         POSTING_READ(LCPLL_CTL);
9564
9565         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9566                 DRM_ERROR("LCPLL still locked\n");
9567
9568         val = hsw_read_dcomp(dev_priv);
9569         val |= D_COMP_COMP_DISABLE;
9570         hsw_write_dcomp(dev_priv, val);
9571         ndelay(100);
9572
9573         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9574                      1))
9575                 DRM_ERROR("D_COMP RCOMP still in progress\n");
9576
9577         if (allow_power_down) {
9578                 val = I915_READ(LCPLL_CTL);
9579                 val |= LCPLL_POWER_DOWN_ALLOW;
9580                 I915_WRITE(LCPLL_CTL, val);
9581                 POSTING_READ(LCPLL_CTL);
9582         }
9583 }
9584
9585 /*
9586  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9587  * source.
9588  */
9589 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9590 {
9591         uint32_t val;
9592
9593         val = I915_READ(LCPLL_CTL);
9594
9595         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9596                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9597                 return;
9598
9599         /*
9600          * Make sure we're not on PC8 state before disabling PC8, otherwise
9601          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9602          */
9603         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9604
9605         if (val & LCPLL_POWER_DOWN_ALLOW) {
9606                 val &= ~LCPLL_POWER_DOWN_ALLOW;
9607                 I915_WRITE(LCPLL_CTL, val);
9608                 POSTING_READ(LCPLL_CTL);
9609         }
9610
9611         val = hsw_read_dcomp(dev_priv);
9612         val |= D_COMP_COMP_FORCE;
9613         val &= ~D_COMP_COMP_DISABLE;
9614         hsw_write_dcomp(dev_priv, val);
9615
9616         val = I915_READ(LCPLL_CTL);
9617         val &= ~LCPLL_PLL_DISABLE;
9618         I915_WRITE(LCPLL_CTL, val);
9619
9620         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9621                 DRM_ERROR("LCPLL not locked yet\n");
9622
9623         if (val & LCPLL_CD_SOURCE_FCLK) {
9624                 val = I915_READ(LCPLL_CTL);
9625                 val &= ~LCPLL_CD_SOURCE_FCLK;
9626                 I915_WRITE(LCPLL_CTL, val);
9627
9628                 if (wait_for_us((I915_READ(LCPLL_CTL) &
9629                                  LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9630                         DRM_ERROR("Switching back to LCPLL failed\n");
9631         }
9632
9633         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9634         intel_update_cdclk(dev_priv->dev);
9635 }
9636
9637 /*
9638  * Package states C8 and deeper are really deep PC states that can only be
9639  * reached when all the devices on the system allow it, so even if the graphics
9640  * device allows PC8+, it doesn't mean the system will actually get to these
9641  * states. Our driver only allows PC8+ when going into runtime PM.
9642  *
9643  * The requirements for PC8+ are that all the outputs are disabled, the power
9644  * well is disabled and most interrupts are disabled, and these are also
9645  * requirements for runtime PM. When these conditions are met, we manually do
9646  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9647  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9648  * hang the machine.
9649  *
9650  * When we really reach PC8 or deeper states (not just when we allow it) we lose
9651  * the state of some registers, so when we come back from PC8+ we need to
9652  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9653  * need to take care of the registers kept by RC6. Notice that this happens even
9654  * if we don't put the device in PCI D3 state (which is what currently happens
9655  * because of the runtime PM support).
9656  *
9657  * For more, read "Display Sequences for Package C8" on the hardware
9658  * documentation.
9659  */
9660 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9661 {
9662         struct drm_device *dev = dev_priv->dev;
9663         uint32_t val;
9664
9665         DRM_DEBUG_KMS("Enabling package C8+\n");
9666
9667         if (HAS_PCH_LPT_LP(dev)) {
9668                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9669                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9670                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9671         }
9672
9673         lpt_disable_clkout_dp(dev);
9674         hsw_disable_lcpll(dev_priv, true, true);
9675 }
9676
9677 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9678 {
9679         struct drm_device *dev = dev_priv->dev;
9680         uint32_t val;
9681
9682         DRM_DEBUG_KMS("Disabling package C8+\n");
9683
9684         hsw_restore_lcpll(dev_priv);
9685         lpt_init_pch_refclk(dev);
9686
9687         if (HAS_PCH_LPT_LP(dev)) {
9688                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9689                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9690                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9691         }
9692 }
9693
9694 static void bxt_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9695 {
9696         struct drm_device *dev = old_state->dev;
9697         struct intel_atomic_state *old_intel_state =
9698                 to_intel_atomic_state(old_state);
9699         unsigned int req_cdclk = old_intel_state->dev_cdclk;
9700
9701         bxt_set_cdclk(to_i915(dev), req_cdclk);
9702 }
9703
9704 /* compute the max rate for new configuration */
9705 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9706 {
9707         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9708         struct drm_i915_private *dev_priv = state->dev->dev_private;
9709         struct drm_crtc *crtc;
9710         struct drm_crtc_state *cstate;
9711         struct intel_crtc_state *crtc_state;
9712         unsigned max_pixel_rate = 0, i;
9713         enum pipe pipe;
9714
9715         memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
9716                sizeof(intel_state->min_pixclk));
9717
9718         for_each_crtc_in_state(state, crtc, cstate, i) {
9719                 int pixel_rate;
9720
9721                 crtc_state = to_intel_crtc_state(cstate);
9722                 if (!crtc_state->base.enable) {
9723                         intel_state->min_pixclk[i] = 0;
9724                         continue;
9725                 }
9726
9727                 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
9728
9729                 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9730                 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
9731                         pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9732
9733                 intel_state->min_pixclk[i] = pixel_rate;
9734         }
9735
9736         for_each_pipe(dev_priv, pipe)
9737                 max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate);
9738
9739         return max_pixel_rate;
9740 }
9741
9742 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9743 {
9744         struct drm_i915_private *dev_priv = dev->dev_private;
9745         uint32_t val, data;
9746         int ret;
9747
9748         if (WARN((I915_READ(LCPLL_CTL) &
9749                   (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9750                    LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9751                    LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9752                    LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9753                  "trying to change cdclk frequency with cdclk not enabled\n"))
9754                 return;
9755
9756         mutex_lock(&dev_priv->rps.hw_lock);
9757         ret = sandybridge_pcode_write(dev_priv,
9758                                       BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9759         mutex_unlock(&dev_priv->rps.hw_lock);
9760         if (ret) {
9761                 DRM_ERROR("failed to inform pcode about cdclk change\n");
9762                 return;
9763         }
9764
9765         val = I915_READ(LCPLL_CTL);
9766         val |= LCPLL_CD_SOURCE_FCLK;
9767         I915_WRITE(LCPLL_CTL, val);
9768
9769         if (wait_for_us(I915_READ(LCPLL_CTL) &
9770                         LCPLL_CD_SOURCE_FCLK_DONE, 1))
9771                 DRM_ERROR("Switching to FCLK failed\n");
9772
9773         val = I915_READ(LCPLL_CTL);
9774         val &= ~LCPLL_CLK_FREQ_MASK;
9775
9776         switch (cdclk) {
9777         case 450000:
9778                 val |= LCPLL_CLK_FREQ_450;
9779                 data = 0;
9780                 break;
9781         case 540000:
9782                 val |= LCPLL_CLK_FREQ_54O_BDW;
9783                 data = 1;
9784                 break;
9785         case 337500:
9786                 val |= LCPLL_CLK_FREQ_337_5_BDW;
9787                 data = 2;
9788                 break;
9789         case 675000:
9790                 val |= LCPLL_CLK_FREQ_675_BDW;
9791                 data = 3;
9792                 break;
9793         default:
9794                 WARN(1, "invalid cdclk frequency\n");
9795                 return;
9796         }
9797
9798         I915_WRITE(LCPLL_CTL, val);
9799
9800         val = I915_READ(LCPLL_CTL);
9801         val &= ~LCPLL_CD_SOURCE_FCLK;
9802         I915_WRITE(LCPLL_CTL, val);
9803
9804         if (wait_for_us((I915_READ(LCPLL_CTL) &
9805                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9806                 DRM_ERROR("Switching back to LCPLL failed\n");
9807
9808         mutex_lock(&dev_priv->rps.hw_lock);
9809         sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9810         mutex_unlock(&dev_priv->rps.hw_lock);
9811
9812         I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
9813
9814         intel_update_cdclk(dev);
9815
9816         WARN(cdclk != dev_priv->cdclk_freq,
9817              "cdclk requested %d kHz but got %d kHz\n",
9818              cdclk, dev_priv->cdclk_freq);
9819 }
9820
9821 static int broadwell_calc_cdclk(int max_pixclk)
9822 {
9823         if (max_pixclk > 540000)
9824                 return 675000;
9825         else if (max_pixclk > 450000)
9826                 return 540000;
9827         else if (max_pixclk > 337500)
9828                 return 450000;
9829         else
9830                 return 337500;
9831 }
9832
9833 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
9834 {
9835         struct drm_i915_private *dev_priv = to_i915(state->dev);
9836         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9837         int max_pixclk = ilk_max_pixel_rate(state);
9838         int cdclk;
9839
9840         /*
9841          * FIXME should also account for plane ratio
9842          * once 64bpp pixel formats are supported.
9843          */
9844         cdclk = broadwell_calc_cdclk(max_pixclk);
9845
9846         if (cdclk > dev_priv->max_cdclk_freq) {
9847                 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9848                               cdclk, dev_priv->max_cdclk_freq);
9849                 return -EINVAL;
9850         }
9851
9852         intel_state->cdclk = intel_state->dev_cdclk = cdclk;
9853         if (!intel_state->active_crtcs)
9854                 intel_state->dev_cdclk = broadwell_calc_cdclk(0);
9855
9856         return 0;
9857 }
9858
9859 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9860 {
9861         struct drm_device *dev = old_state->dev;
9862         struct intel_atomic_state *old_intel_state =
9863                 to_intel_atomic_state(old_state);
9864         unsigned req_cdclk = old_intel_state->dev_cdclk;
9865
9866         broadwell_set_cdclk(dev, req_cdclk);
9867 }
9868
9869 static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
9870 {
9871         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9872         struct drm_i915_private *dev_priv = to_i915(state->dev);
9873         const int max_pixclk = ilk_max_pixel_rate(state);
9874         int vco = intel_state->cdclk_pll_vco;
9875         int cdclk;
9876
9877         /*
9878          * FIXME should also account for plane ratio
9879          * once 64bpp pixel formats are supported.
9880          */
9881         cdclk = skl_calc_cdclk(max_pixclk, vco);
9882
9883         /*
9884          * FIXME move the cdclk caclulation to
9885          * compute_config() so we can fail gracegully.
9886          */
9887         if (cdclk > dev_priv->max_cdclk_freq) {
9888                 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9889                           cdclk, dev_priv->max_cdclk_freq);
9890                 cdclk = dev_priv->max_cdclk_freq;
9891         }
9892
9893         intel_state->cdclk = intel_state->dev_cdclk = cdclk;
9894         if (!intel_state->active_crtcs)
9895                 intel_state->dev_cdclk = skl_calc_cdclk(0, vco);
9896
9897         return 0;
9898 }
9899
9900 static void skl_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9901 {
9902         struct drm_i915_private *dev_priv = to_i915(old_state->dev);
9903         struct intel_atomic_state *intel_state = to_intel_atomic_state(old_state);
9904         unsigned int req_cdclk = intel_state->dev_cdclk;
9905         unsigned int req_vco = intel_state->cdclk_pll_vco;
9906
9907         skl_set_cdclk(dev_priv, req_cdclk, req_vco);
9908 }
9909
9910 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9911                                       struct intel_crtc_state *crtc_state)
9912 {
9913         struct intel_encoder *intel_encoder =
9914                 intel_ddi_get_crtc_new_encoder(crtc_state);
9915
9916         if (intel_encoder->type != INTEL_OUTPUT_DSI) {
9917                 if (!intel_ddi_pll_select(crtc, crtc_state))
9918                         return -EINVAL;
9919         }
9920
9921         crtc->lowfreq_avail = false;
9922
9923         return 0;
9924 }
9925
9926 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9927                                 enum port port,
9928                                 struct intel_crtc_state *pipe_config)
9929 {
9930         enum intel_dpll_id id;
9931
9932         switch (port) {
9933         case PORT_A:
9934                 pipe_config->ddi_pll_sel = SKL_DPLL0;
9935                 id = DPLL_ID_SKL_DPLL0;
9936                 break;
9937         case PORT_B:
9938                 pipe_config->ddi_pll_sel = SKL_DPLL1;
9939                 id = DPLL_ID_SKL_DPLL1;
9940                 break;
9941         case PORT_C:
9942                 pipe_config->ddi_pll_sel = SKL_DPLL2;
9943                 id = DPLL_ID_SKL_DPLL2;
9944                 break;
9945         default:
9946                 DRM_ERROR("Incorrect port type\n");
9947                 return;
9948         }
9949
9950         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9951 }
9952
9953 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9954                                 enum port port,
9955                                 struct intel_crtc_state *pipe_config)
9956 {
9957         enum intel_dpll_id id;
9958         u32 temp;
9959
9960         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9961         pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9962
9963         switch (pipe_config->ddi_pll_sel) {
9964         case SKL_DPLL0:
9965                 id = DPLL_ID_SKL_DPLL0;
9966                 break;
9967         case SKL_DPLL1:
9968                 id = DPLL_ID_SKL_DPLL1;
9969                 break;
9970         case SKL_DPLL2:
9971                 id = DPLL_ID_SKL_DPLL2;
9972                 break;
9973         case SKL_DPLL3:
9974                 id = DPLL_ID_SKL_DPLL3;
9975                 break;
9976         default:
9977                 MISSING_CASE(pipe_config->ddi_pll_sel);
9978                 return;
9979         }
9980
9981         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9982 }
9983
9984 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9985                                 enum port port,
9986                                 struct intel_crtc_state *pipe_config)
9987 {
9988         enum intel_dpll_id id;
9989
9990         pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9991
9992         switch (pipe_config->ddi_pll_sel) {
9993         case PORT_CLK_SEL_WRPLL1:
9994                 id = DPLL_ID_WRPLL1;
9995                 break;
9996         case PORT_CLK_SEL_WRPLL2:
9997                 id = DPLL_ID_WRPLL2;
9998                 break;
9999         case PORT_CLK_SEL_SPLL:
10000                 id = DPLL_ID_SPLL;
10001                 break;
10002         case PORT_CLK_SEL_LCPLL_810:
10003                 id = DPLL_ID_LCPLL_810;
10004                 break;
10005         case PORT_CLK_SEL_LCPLL_1350:
10006                 id = DPLL_ID_LCPLL_1350;
10007                 break;
10008         case PORT_CLK_SEL_LCPLL_2700:
10009                 id = DPLL_ID_LCPLL_2700;
10010                 break;
10011         default:
10012                 MISSING_CASE(pipe_config->ddi_pll_sel);
10013                 /* fall through */
10014         case PORT_CLK_SEL_NONE:
10015                 return;
10016         }
10017
10018         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10019 }
10020
10021 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
10022                                      struct intel_crtc_state *pipe_config,
10023                                      unsigned long *power_domain_mask)
10024 {
10025         struct drm_device *dev = crtc->base.dev;
10026         struct drm_i915_private *dev_priv = dev->dev_private;
10027         enum intel_display_power_domain power_domain;
10028         u32 tmp;
10029
10030         /*
10031          * The pipe->transcoder mapping is fixed with the exception of the eDP
10032          * transcoder handled below.
10033          */
10034         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
10035
10036         /*
10037          * XXX: Do intel_display_power_get_if_enabled before reading this (for
10038          * consistency and less surprising code; it's in always on power).
10039          */
10040         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
10041         if (tmp & TRANS_DDI_FUNC_ENABLE) {
10042                 enum pipe trans_edp_pipe;
10043                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
10044                 default:
10045                         WARN(1, "unknown pipe linked to edp transcoder\n");
10046                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
10047                 case TRANS_DDI_EDP_INPUT_A_ON:
10048                         trans_edp_pipe = PIPE_A;
10049                         break;
10050                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
10051                         trans_edp_pipe = PIPE_B;
10052                         break;
10053                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
10054                         trans_edp_pipe = PIPE_C;
10055                         break;
10056                 }
10057
10058                 if (trans_edp_pipe == crtc->pipe)
10059                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
10060         }
10061
10062         power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
10063         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10064                 return false;
10065         *power_domain_mask |= BIT(power_domain);
10066
10067         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
10068
10069         return tmp & PIPECONF_ENABLE;
10070 }
10071
10072 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
10073                                          struct intel_crtc_state *pipe_config,
10074                                          unsigned long *power_domain_mask)
10075 {
10076         struct drm_device *dev = crtc->base.dev;
10077         struct drm_i915_private *dev_priv = dev->dev_private;
10078         enum intel_display_power_domain power_domain;
10079         enum port port;
10080         enum transcoder cpu_transcoder;
10081         u32 tmp;
10082
10083         pipe_config->has_dsi_encoder = false;
10084
10085         for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
10086                 if (port == PORT_A)
10087                         cpu_transcoder = TRANSCODER_DSI_A;
10088                 else
10089                         cpu_transcoder = TRANSCODER_DSI_C;
10090
10091                 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
10092                 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10093                         continue;
10094                 *power_domain_mask |= BIT(power_domain);
10095
10096                 /*
10097                  * The PLL needs to be enabled with a valid divider
10098                  * configuration, otherwise accessing DSI registers will hang
10099                  * the machine. See BSpec North Display Engine
10100                  * registers/MIPI[BXT]. We can break out here early, since we
10101                  * need the same DSI PLL to be enabled for both DSI ports.
10102                  */
10103                 if (!intel_dsi_pll_is_enabled(dev_priv))
10104                         break;
10105
10106                 /* XXX: this works for video mode only */
10107                 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
10108                 if (!(tmp & DPI_ENABLE))
10109                         continue;
10110
10111                 tmp = I915_READ(MIPI_CTRL(port));
10112                 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
10113                         continue;
10114
10115                 pipe_config->cpu_transcoder = cpu_transcoder;
10116                 pipe_config->has_dsi_encoder = true;
10117                 break;
10118         }
10119
10120         return pipe_config->has_dsi_encoder;
10121 }
10122
10123 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
10124                                        struct intel_crtc_state *pipe_config)
10125 {
10126         struct drm_device *dev = crtc->base.dev;
10127         struct drm_i915_private *dev_priv = dev->dev_private;
10128         struct intel_shared_dpll *pll;
10129         enum port port;
10130         uint32_t tmp;
10131
10132         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
10133
10134         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
10135
10136         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
10137                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
10138         else if (IS_BROXTON(dev))
10139                 bxt_get_ddi_pll(dev_priv, port, pipe_config);
10140         else
10141                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
10142
10143         pll = pipe_config->shared_dpll;
10144         if (pll) {
10145                 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
10146                                                  &pipe_config->dpll_hw_state));
10147         }
10148
10149         /*
10150          * Haswell has only FDI/PCH transcoder A. It is which is connected to
10151          * DDI E. So just check whether this pipe is wired to DDI E and whether
10152          * the PCH transcoder is on.
10153          */
10154         if (INTEL_INFO(dev)->gen < 9 &&
10155             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
10156                 pipe_config->has_pch_encoder = true;
10157
10158                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
10159                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
10160                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
10161
10162                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
10163         }
10164 }
10165
10166 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
10167                                     struct intel_crtc_state *pipe_config)
10168 {
10169         struct drm_device *dev = crtc->base.dev;
10170         struct drm_i915_private *dev_priv = dev->dev_private;
10171         enum intel_display_power_domain power_domain;
10172         unsigned long power_domain_mask;
10173         bool active;
10174
10175         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
10176         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10177                 return false;
10178         power_domain_mask = BIT(power_domain);
10179
10180         pipe_config->shared_dpll = NULL;
10181
10182         active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
10183
10184         if (IS_BROXTON(dev_priv)) {
10185                 bxt_get_dsi_transcoder_state(crtc, pipe_config,
10186                                              &power_domain_mask);
10187                 WARN_ON(active && pipe_config->has_dsi_encoder);
10188                 if (pipe_config->has_dsi_encoder)
10189                         active = true;
10190         }
10191
10192         if (!active)
10193                 goto out;
10194
10195         if (!pipe_config->has_dsi_encoder) {
10196                 haswell_get_ddi_port_state(crtc, pipe_config);
10197                 intel_get_pipe_timings(crtc, pipe_config);
10198         }
10199
10200         intel_get_pipe_src_size(crtc, pipe_config);
10201
10202         pipe_config->gamma_mode =
10203                 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
10204
10205         if (INTEL_INFO(dev)->gen >= 9) {
10206                 skl_init_scalers(dev, crtc, pipe_config);
10207         }
10208
10209         if (INTEL_INFO(dev)->gen >= 9) {
10210                 pipe_config->scaler_state.scaler_id = -1;
10211                 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
10212         }
10213
10214         power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
10215         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
10216                 power_domain_mask |= BIT(power_domain);
10217                 if (INTEL_INFO(dev)->gen >= 9)
10218                         skylake_get_pfit_config(crtc, pipe_config);
10219                 else
10220                         ironlake_get_pfit_config(crtc, pipe_config);
10221         }
10222
10223         if (IS_HASWELL(dev))
10224                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
10225                         (I915_READ(IPS_CTL) & IPS_ENABLE);
10226
10227         if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
10228             !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
10229                 pipe_config->pixel_multiplier =
10230                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
10231         } else {
10232                 pipe_config->pixel_multiplier = 1;
10233         }
10234
10235 out:
10236         for_each_power_domain(power_domain, power_domain_mask)
10237                 intel_display_power_put(dev_priv, power_domain);
10238
10239         return active;
10240 }
10241
10242 static void i845_update_cursor(struct drm_crtc *crtc, u32 base,
10243                                const struct intel_plane_state *plane_state)
10244 {
10245         struct drm_device *dev = crtc->dev;
10246         struct drm_i915_private *dev_priv = dev->dev_private;
10247         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10248         uint32_t cntl = 0, size = 0;
10249
10250         if (plane_state && plane_state->visible) {
10251                 unsigned int width = plane_state->base.crtc_w;
10252                 unsigned int height = plane_state->base.crtc_h;
10253                 unsigned int stride = roundup_pow_of_two(width) * 4;
10254
10255                 switch (stride) {
10256                 default:
10257                         WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
10258                                   width, stride);
10259                         stride = 256;
10260                         /* fallthrough */
10261                 case 256:
10262                 case 512:
10263                 case 1024:
10264                 case 2048:
10265                         break;
10266                 }
10267
10268                 cntl |= CURSOR_ENABLE |
10269                         CURSOR_GAMMA_ENABLE |
10270                         CURSOR_FORMAT_ARGB |
10271                         CURSOR_STRIDE(stride);
10272
10273                 size = (height << 12) | width;
10274         }
10275
10276         if (intel_crtc->cursor_cntl != 0 &&
10277             (intel_crtc->cursor_base != base ||
10278              intel_crtc->cursor_size != size ||
10279              intel_crtc->cursor_cntl != cntl)) {
10280                 /* On these chipsets we can only modify the base/size/stride
10281                  * whilst the cursor is disabled.
10282                  */
10283                 I915_WRITE(CURCNTR(PIPE_A), 0);
10284                 POSTING_READ(CURCNTR(PIPE_A));
10285                 intel_crtc->cursor_cntl = 0;
10286         }
10287
10288         if (intel_crtc->cursor_base != base) {
10289                 I915_WRITE(CURBASE(PIPE_A), base);
10290                 intel_crtc->cursor_base = base;
10291         }
10292
10293         if (intel_crtc->cursor_size != size) {
10294                 I915_WRITE(CURSIZE, size);
10295                 intel_crtc->cursor_size = size;
10296         }
10297
10298         if (intel_crtc->cursor_cntl != cntl) {
10299                 I915_WRITE(CURCNTR(PIPE_A), cntl);
10300                 POSTING_READ(CURCNTR(PIPE_A));
10301                 intel_crtc->cursor_cntl = cntl;
10302         }
10303 }
10304
10305 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base,
10306                                const struct intel_plane_state *plane_state)
10307 {
10308         struct drm_device *dev = crtc->dev;
10309         struct drm_i915_private *dev_priv = dev->dev_private;
10310         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10311         int pipe = intel_crtc->pipe;
10312         uint32_t cntl = 0;
10313
10314         if (plane_state && plane_state->visible) {
10315                 cntl = MCURSOR_GAMMA_ENABLE;
10316                 switch (plane_state->base.crtc_w) {
10317                         case 64:
10318                                 cntl |= CURSOR_MODE_64_ARGB_AX;
10319                                 break;
10320                         case 128:
10321                                 cntl |= CURSOR_MODE_128_ARGB_AX;
10322                                 break;
10323                         case 256:
10324                                 cntl |= CURSOR_MODE_256_ARGB_AX;
10325                                 break;
10326                         default:
10327                                 MISSING_CASE(plane_state->base.crtc_w);
10328                                 return;
10329                 }
10330                 cntl |= pipe << 28; /* Connect to correct pipe */
10331
10332                 if (HAS_DDI(dev))
10333                         cntl |= CURSOR_PIPE_CSC_ENABLE;
10334
10335                 if (plane_state->base.rotation == BIT(DRM_ROTATE_180))
10336                         cntl |= CURSOR_ROTATE_180;
10337         }
10338
10339         if (intel_crtc->cursor_cntl != cntl) {
10340                 I915_WRITE(CURCNTR(pipe), cntl);
10341                 POSTING_READ(CURCNTR(pipe));
10342                 intel_crtc->cursor_cntl = cntl;
10343         }
10344
10345         /* and commit changes on next vblank */
10346         I915_WRITE(CURBASE(pipe), base);
10347         POSTING_READ(CURBASE(pipe));
10348
10349         intel_crtc->cursor_base = base;
10350 }
10351
10352 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10353 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10354                                      const struct intel_plane_state *plane_state)
10355 {
10356         struct drm_device *dev = crtc->dev;
10357         struct drm_i915_private *dev_priv = dev->dev_private;
10358         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10359         int pipe = intel_crtc->pipe;
10360         u32 base = intel_crtc->cursor_addr;
10361         u32 pos = 0;
10362
10363         if (plane_state) {
10364                 int x = plane_state->base.crtc_x;
10365                 int y = plane_state->base.crtc_y;
10366
10367                 if (x < 0) {
10368                         pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10369                         x = -x;
10370                 }
10371                 pos |= x << CURSOR_X_SHIFT;
10372
10373                 if (y < 0) {
10374                         pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10375                         y = -y;
10376                 }
10377                 pos |= y << CURSOR_Y_SHIFT;
10378
10379                 /* ILK+ do this automagically */
10380                 if (HAS_GMCH_DISPLAY(dev) &&
10381                     plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
10382                         base += (plane_state->base.crtc_h *
10383                                  plane_state->base.crtc_w - 1) * 4;
10384                 }
10385         }
10386
10387         I915_WRITE(CURPOS(pipe), pos);
10388
10389         if (IS_845G(dev) || IS_I865G(dev))
10390                 i845_update_cursor(crtc, base, plane_state);
10391         else
10392                 i9xx_update_cursor(crtc, base, plane_state);
10393 }
10394
10395 static bool cursor_size_ok(struct drm_device *dev,
10396                            uint32_t width, uint32_t height)
10397 {
10398         if (width == 0 || height == 0)
10399                 return false;
10400
10401         /*
10402          * 845g/865g are special in that they are only limited by
10403          * the width of their cursors, the height is arbitrary up to
10404          * the precision of the register. Everything else requires
10405          * square cursors, limited to a few power-of-two sizes.
10406          */
10407         if (IS_845G(dev) || IS_I865G(dev)) {
10408                 if ((width & 63) != 0)
10409                         return false;
10410
10411                 if (width > (IS_845G(dev) ? 64 : 512))
10412                         return false;
10413
10414                 if (height > 1023)
10415                         return false;
10416         } else {
10417                 switch (width | height) {
10418                 case 256:
10419                 case 128:
10420                         if (IS_GEN2(dev))
10421                                 return false;
10422                 case 64:
10423                         break;
10424                 default:
10425                         return false;
10426                 }
10427         }
10428
10429         return true;
10430 }
10431
10432 /* VESA 640x480x72Hz mode to set on the pipe */
10433 static struct drm_display_mode load_detect_mode = {
10434         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10435                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10436 };
10437
10438 struct drm_framebuffer *
10439 __intel_framebuffer_create(struct drm_device *dev,
10440                            struct drm_mode_fb_cmd2 *mode_cmd,
10441                            struct drm_i915_gem_object *obj)
10442 {
10443         struct intel_framebuffer *intel_fb;
10444         int ret;
10445
10446         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10447         if (!intel_fb)
10448                 return ERR_PTR(-ENOMEM);
10449
10450         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10451         if (ret)
10452                 goto err;
10453
10454         return &intel_fb->base;
10455
10456 err:
10457         kfree(intel_fb);
10458         return ERR_PTR(ret);
10459 }
10460
10461 static struct drm_framebuffer *
10462 intel_framebuffer_create(struct drm_device *dev,
10463                          struct drm_mode_fb_cmd2 *mode_cmd,
10464                          struct drm_i915_gem_object *obj)
10465 {
10466         struct drm_framebuffer *fb;
10467         int ret;
10468
10469         ret = i915_mutex_lock_interruptible(dev);
10470         if (ret)
10471                 return ERR_PTR(ret);
10472         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10473         mutex_unlock(&dev->struct_mutex);
10474
10475         return fb;
10476 }
10477
10478 static u32
10479 intel_framebuffer_pitch_for_width(int width, int bpp)
10480 {
10481         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10482         return ALIGN(pitch, 64);
10483 }
10484
10485 static u32
10486 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10487 {
10488         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10489         return PAGE_ALIGN(pitch * mode->vdisplay);
10490 }
10491
10492 static struct drm_framebuffer *
10493 intel_framebuffer_create_for_mode(struct drm_device *dev,
10494                                   struct drm_display_mode *mode,
10495                                   int depth, int bpp)
10496 {
10497         struct drm_framebuffer *fb;
10498         struct drm_i915_gem_object *obj;
10499         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10500
10501         obj = i915_gem_object_create(dev,
10502                                     intel_framebuffer_size_for_mode(mode, bpp));
10503         if (IS_ERR(obj))
10504                 return ERR_CAST(obj);
10505
10506         mode_cmd.width = mode->hdisplay;
10507         mode_cmd.height = mode->vdisplay;
10508         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10509                                                                 bpp);
10510         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10511
10512         fb = intel_framebuffer_create(dev, &mode_cmd, obj);
10513         if (IS_ERR(fb))
10514                 drm_gem_object_unreference_unlocked(&obj->base);
10515
10516         return fb;
10517 }
10518
10519 static struct drm_framebuffer *
10520 mode_fits_in_fbdev(struct drm_device *dev,
10521                    struct drm_display_mode *mode)
10522 {
10523 #ifdef CONFIG_DRM_FBDEV_EMULATION
10524         struct drm_i915_private *dev_priv = dev->dev_private;
10525         struct drm_i915_gem_object *obj;
10526         struct drm_framebuffer *fb;
10527
10528         if (!dev_priv->fbdev)
10529                 return NULL;
10530
10531         if (!dev_priv->fbdev->fb)
10532                 return NULL;
10533
10534         obj = dev_priv->fbdev->fb->obj;
10535         BUG_ON(!obj);
10536
10537         fb = &dev_priv->fbdev->fb->base;
10538         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10539                                                                fb->bits_per_pixel))
10540                 return NULL;
10541
10542         if (obj->base.size < mode->vdisplay * fb->pitches[0])
10543                 return NULL;
10544
10545         drm_framebuffer_reference(fb);
10546         return fb;
10547 #else
10548         return NULL;
10549 #endif
10550 }
10551
10552 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10553                                            struct drm_crtc *crtc,
10554                                            struct drm_display_mode *mode,
10555                                            struct drm_framebuffer *fb,
10556                                            int x, int y)
10557 {
10558         struct drm_plane_state *plane_state;
10559         int hdisplay, vdisplay;
10560         int ret;
10561
10562         plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10563         if (IS_ERR(plane_state))
10564                 return PTR_ERR(plane_state);
10565
10566         if (mode)
10567                 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10568         else
10569                 hdisplay = vdisplay = 0;
10570
10571         ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10572         if (ret)
10573                 return ret;
10574         drm_atomic_set_fb_for_plane(plane_state, fb);
10575         plane_state->crtc_x = 0;
10576         plane_state->crtc_y = 0;
10577         plane_state->crtc_w = hdisplay;
10578         plane_state->crtc_h = vdisplay;
10579         plane_state->src_x = x << 16;
10580         plane_state->src_y = y << 16;
10581         plane_state->src_w = hdisplay << 16;
10582         plane_state->src_h = vdisplay << 16;
10583
10584         return 0;
10585 }
10586
10587 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10588                                 struct drm_display_mode *mode,
10589                                 struct intel_load_detect_pipe *old,
10590                                 struct drm_modeset_acquire_ctx *ctx)
10591 {
10592         struct intel_crtc *intel_crtc;
10593         struct intel_encoder *intel_encoder =
10594                 intel_attached_encoder(connector);
10595         struct drm_crtc *possible_crtc;
10596         struct drm_encoder *encoder = &intel_encoder->base;
10597         struct drm_crtc *crtc = NULL;
10598         struct drm_device *dev = encoder->dev;
10599         struct drm_framebuffer *fb;
10600         struct drm_mode_config *config = &dev->mode_config;
10601         struct drm_atomic_state *state = NULL, *restore_state = NULL;
10602         struct drm_connector_state *connector_state;
10603         struct intel_crtc_state *crtc_state;
10604         int ret, i = -1;
10605
10606         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10607                       connector->base.id, connector->name,
10608                       encoder->base.id, encoder->name);
10609
10610         old->restore_state = NULL;
10611
10612 retry:
10613         ret = drm_modeset_lock(&config->connection_mutex, ctx);
10614         if (ret)
10615                 goto fail;
10616
10617         /*
10618          * Algorithm gets a little messy:
10619          *
10620          *   - if the connector already has an assigned crtc, use it (but make
10621          *     sure it's on first)
10622          *
10623          *   - try to find the first unused crtc that can drive this connector,
10624          *     and use that if we find one
10625          */
10626
10627         /* See if we already have a CRTC for this connector */
10628         if (connector->state->crtc) {
10629                 crtc = connector->state->crtc;
10630
10631                 ret = drm_modeset_lock(&crtc->mutex, ctx);
10632                 if (ret)
10633                         goto fail;
10634
10635                 /* Make sure the crtc and connector are running */
10636                 goto found;
10637         }
10638
10639         /* Find an unused one (if possible) */
10640         for_each_crtc(dev, possible_crtc) {
10641                 i++;
10642                 if (!(encoder->possible_crtcs & (1 << i)))
10643                         continue;
10644
10645                 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
10646                 if (ret)
10647                         goto fail;
10648
10649                 if (possible_crtc->state->enable) {
10650                         drm_modeset_unlock(&possible_crtc->mutex);
10651                         continue;
10652                 }
10653
10654                 crtc = possible_crtc;
10655                 break;
10656         }
10657
10658         /*
10659          * If we didn't find an unused CRTC, don't use any.
10660          */
10661         if (!crtc) {
10662                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10663                 goto fail;
10664         }
10665
10666 found:
10667         intel_crtc = to_intel_crtc(crtc);
10668
10669         ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10670         if (ret)
10671                 goto fail;
10672
10673         state = drm_atomic_state_alloc(dev);
10674         restore_state = drm_atomic_state_alloc(dev);
10675         if (!state || !restore_state) {
10676                 ret = -ENOMEM;
10677                 goto fail;
10678         }
10679
10680         state->acquire_ctx = ctx;
10681         restore_state->acquire_ctx = ctx;
10682
10683         connector_state = drm_atomic_get_connector_state(state, connector);
10684         if (IS_ERR(connector_state)) {
10685                 ret = PTR_ERR(connector_state);
10686                 goto fail;
10687         }
10688
10689         ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
10690         if (ret)
10691                 goto fail;
10692
10693         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10694         if (IS_ERR(crtc_state)) {
10695                 ret = PTR_ERR(crtc_state);
10696                 goto fail;
10697         }
10698
10699         crtc_state->base.active = crtc_state->base.enable = true;
10700
10701         if (!mode)
10702                 mode = &load_detect_mode;
10703
10704         /* We need a framebuffer large enough to accommodate all accesses
10705          * that the plane may generate whilst we perform load detection.
10706          * We can not rely on the fbcon either being present (we get called
10707          * during its initialisation to detect all boot displays, or it may
10708          * not even exist) or that it is large enough to satisfy the
10709          * requested mode.
10710          */
10711         fb = mode_fits_in_fbdev(dev, mode);
10712         if (fb == NULL) {
10713                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10714                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10715         } else
10716                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10717         if (IS_ERR(fb)) {
10718                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10719                 goto fail;
10720         }
10721
10722         ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10723         if (ret)
10724                 goto fail;
10725
10726         drm_framebuffer_unreference(fb);
10727
10728         ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
10729         if (ret)
10730                 goto fail;
10731
10732         ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
10733         if (!ret)
10734                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
10735         if (!ret)
10736                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
10737         if (ret) {
10738                 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
10739                 goto fail;
10740         }
10741
10742         ret = drm_atomic_commit(state);
10743         if (ret) {
10744                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10745                 goto fail;
10746         }
10747
10748         old->restore_state = restore_state;
10749
10750         /* let the connector get through one full cycle before testing */
10751         intel_wait_for_vblank(dev, intel_crtc->pipe);
10752         return true;
10753
10754 fail:
10755         drm_atomic_state_free(state);
10756         drm_atomic_state_free(restore_state);
10757         restore_state = state = NULL;
10758
10759         if (ret == -EDEADLK) {
10760                 drm_modeset_backoff(ctx);
10761                 goto retry;
10762         }
10763
10764         return false;
10765 }
10766
10767 void intel_release_load_detect_pipe(struct drm_connector *connector,
10768                                     struct intel_load_detect_pipe *old,
10769                                     struct drm_modeset_acquire_ctx *ctx)
10770 {
10771         struct intel_encoder *intel_encoder =
10772                 intel_attached_encoder(connector);
10773         struct drm_encoder *encoder = &intel_encoder->base;
10774         struct drm_atomic_state *state = old->restore_state;
10775         int ret;
10776
10777         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10778                       connector->base.id, connector->name,
10779                       encoder->base.id, encoder->name);
10780
10781         if (!state)
10782                 return;
10783
10784         ret = drm_atomic_commit(state);
10785         if (ret) {
10786                 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
10787                 drm_atomic_state_free(state);
10788         }
10789 }
10790
10791 static int i9xx_pll_refclk(struct drm_device *dev,
10792                            const struct intel_crtc_state *pipe_config)
10793 {
10794         struct drm_i915_private *dev_priv = dev->dev_private;
10795         u32 dpll = pipe_config->dpll_hw_state.dpll;
10796
10797         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10798                 return dev_priv->vbt.lvds_ssc_freq;
10799         else if (HAS_PCH_SPLIT(dev))
10800                 return 120000;
10801         else if (!IS_GEN2(dev))
10802                 return 96000;
10803         else
10804                 return 48000;
10805 }
10806
10807 /* Returns the clock of the currently programmed mode of the given pipe. */
10808 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10809                                 struct intel_crtc_state *pipe_config)
10810 {
10811         struct drm_device *dev = crtc->base.dev;
10812         struct drm_i915_private *dev_priv = dev->dev_private;
10813         int pipe = pipe_config->cpu_transcoder;
10814         u32 dpll = pipe_config->dpll_hw_state.dpll;
10815         u32 fp;
10816         struct dpll clock;
10817         int port_clock;
10818         int refclk = i9xx_pll_refclk(dev, pipe_config);
10819
10820         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10821                 fp = pipe_config->dpll_hw_state.fp0;
10822         else
10823                 fp = pipe_config->dpll_hw_state.fp1;
10824
10825         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10826         if (IS_PINEVIEW(dev)) {
10827                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10828                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10829         } else {
10830                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10831                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10832         }
10833
10834         if (!IS_GEN2(dev)) {
10835                 if (IS_PINEVIEW(dev))
10836                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10837                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10838                 else
10839                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10840                                DPLL_FPA01_P1_POST_DIV_SHIFT);
10841
10842                 switch (dpll & DPLL_MODE_MASK) {
10843                 case DPLLB_MODE_DAC_SERIAL:
10844                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10845                                 5 : 10;
10846                         break;
10847                 case DPLLB_MODE_LVDS:
10848                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10849                                 7 : 14;
10850                         break;
10851                 default:
10852                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10853                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
10854                         return;
10855                 }
10856
10857                 if (IS_PINEVIEW(dev))
10858                         port_clock = pnv_calc_dpll_params(refclk, &clock);
10859                 else
10860                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
10861         } else {
10862                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10863                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10864
10865                 if (is_lvds) {
10866                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10867                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
10868
10869                         if (lvds & LVDS_CLKB_POWER_UP)
10870                                 clock.p2 = 7;
10871                         else
10872                                 clock.p2 = 14;
10873                 } else {
10874                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
10875                                 clock.p1 = 2;
10876                         else {
10877                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10878                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10879                         }
10880                         if (dpll & PLL_P2_DIVIDE_BY_4)
10881                                 clock.p2 = 4;
10882                         else
10883                                 clock.p2 = 2;
10884                 }
10885
10886                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10887         }
10888
10889         /*
10890          * This value includes pixel_multiplier. We will use
10891          * port_clock to compute adjusted_mode.crtc_clock in the
10892          * encoder's get_config() function.
10893          */
10894         pipe_config->port_clock = port_clock;
10895 }
10896
10897 int intel_dotclock_calculate(int link_freq,
10898                              const struct intel_link_m_n *m_n)
10899 {
10900         /*
10901          * The calculation for the data clock is:
10902          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10903          * But we want to avoid losing precison if possible, so:
10904          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10905          *
10906          * and the link clock is simpler:
10907          * link_clock = (m * link_clock) / n
10908          */
10909
10910         if (!m_n->link_n)
10911                 return 0;
10912
10913         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10914 }
10915
10916 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10917                                    struct intel_crtc_state *pipe_config)
10918 {
10919         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10920
10921         /* read out port_clock from the DPLL */
10922         i9xx_crtc_clock_get(crtc, pipe_config);
10923
10924         /*
10925          * In case there is an active pipe without active ports,
10926          * we may need some idea for the dotclock anyway.
10927          * Calculate one based on the FDI configuration.
10928          */
10929         pipe_config->base.adjusted_mode.crtc_clock =
10930                 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
10931                                          &pipe_config->fdi_m_n);
10932 }
10933
10934 /** Returns the currently programmed mode of the given pipe. */
10935 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10936                                              struct drm_crtc *crtc)
10937 {
10938         struct drm_i915_private *dev_priv = dev->dev_private;
10939         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10940         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10941         struct drm_display_mode *mode;
10942         struct intel_crtc_state *pipe_config;
10943         int htot = I915_READ(HTOTAL(cpu_transcoder));
10944         int hsync = I915_READ(HSYNC(cpu_transcoder));
10945         int vtot = I915_READ(VTOTAL(cpu_transcoder));
10946         int vsync = I915_READ(VSYNC(cpu_transcoder));
10947         enum pipe pipe = intel_crtc->pipe;
10948
10949         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10950         if (!mode)
10951                 return NULL;
10952
10953         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10954         if (!pipe_config) {
10955                 kfree(mode);
10956                 return NULL;
10957         }
10958
10959         /*
10960          * Construct a pipe_config sufficient for getting the clock info
10961          * back out of crtc_clock_get.
10962          *
10963          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10964          * to use a real value here instead.
10965          */
10966         pipe_config->cpu_transcoder = (enum transcoder) pipe;
10967         pipe_config->pixel_multiplier = 1;
10968         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10969         pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10970         pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10971         i9xx_crtc_clock_get(intel_crtc, pipe_config);
10972
10973         mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
10974         mode->hdisplay = (htot & 0xffff) + 1;
10975         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10976         mode->hsync_start = (hsync & 0xffff) + 1;
10977         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10978         mode->vdisplay = (vtot & 0xffff) + 1;
10979         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10980         mode->vsync_start = (vsync & 0xffff) + 1;
10981         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10982
10983         drm_mode_set_name(mode);
10984
10985         kfree(pipe_config);
10986
10987         return mode;
10988 }
10989
10990 void intel_mark_busy(struct drm_i915_private *dev_priv)
10991 {
10992         if (dev_priv->mm.busy)
10993                 return;
10994
10995         intel_runtime_pm_get(dev_priv);
10996         i915_update_gfx_val(dev_priv);
10997         if (INTEL_GEN(dev_priv) >= 6)
10998                 gen6_rps_busy(dev_priv);
10999         dev_priv->mm.busy = true;
11000 }
11001
11002 void intel_mark_idle(struct drm_i915_private *dev_priv)
11003 {
11004         if (!dev_priv->mm.busy)
11005                 return;
11006
11007         dev_priv->mm.busy = false;
11008
11009         if (INTEL_GEN(dev_priv) >= 6)
11010                 gen6_rps_idle(dev_priv);
11011
11012         intel_runtime_pm_put(dev_priv);
11013 }
11014
11015 static void intel_crtc_destroy(struct drm_crtc *crtc)
11016 {
11017         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11018         struct drm_device *dev = crtc->dev;
11019         struct intel_flip_work *work;
11020
11021         spin_lock_irq(&dev->event_lock);
11022         work = intel_crtc->flip_work;
11023         intel_crtc->flip_work = NULL;
11024         spin_unlock_irq(&dev->event_lock);
11025
11026         if (work) {
11027                 cancel_work_sync(&work->mmio_work);
11028                 cancel_work_sync(&work->unpin_work);
11029                 kfree(work);
11030         }
11031
11032         drm_crtc_cleanup(crtc);
11033
11034         kfree(intel_crtc);
11035 }
11036
11037 static void intel_unpin_work_fn(struct work_struct *__work)
11038 {
11039         struct intel_flip_work *work =
11040                 container_of(__work, struct intel_flip_work, unpin_work);
11041         struct intel_crtc *crtc = to_intel_crtc(work->crtc);
11042         struct drm_device *dev = crtc->base.dev;
11043         struct drm_plane *primary = crtc->base.primary;
11044
11045         if (is_mmio_work(work))
11046                 flush_work(&work->mmio_work);
11047
11048         mutex_lock(&dev->struct_mutex);
11049         intel_unpin_fb_obj(work->old_fb, primary->state->rotation);
11050         drm_gem_object_unreference(&work->pending_flip_obj->base);
11051
11052         if (work->flip_queued_req)
11053                 i915_gem_request_assign(&work->flip_queued_req, NULL);
11054         mutex_unlock(&dev->struct_mutex);
11055
11056         intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
11057         intel_fbc_post_update(crtc);
11058         drm_framebuffer_unreference(work->old_fb);
11059
11060         BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
11061         atomic_dec(&crtc->unpin_work_count);
11062
11063         kfree(work);
11064 }
11065
11066 /* Is 'a' after or equal to 'b'? */
11067 static bool g4x_flip_count_after_eq(u32 a, u32 b)
11068 {
11069         return !((a - b) & 0x80000000);
11070 }
11071
11072 static bool __pageflip_finished_cs(struct intel_crtc *crtc,
11073                                    struct intel_flip_work *work)
11074 {
11075         struct drm_device *dev = crtc->base.dev;
11076         struct drm_i915_private *dev_priv = dev->dev_private;
11077         unsigned reset_counter;
11078
11079         reset_counter = i915_reset_counter(&dev_priv->gpu_error);
11080         if (crtc->reset_counter != reset_counter)
11081                 return true;
11082
11083         /*
11084          * The relevant registers doen't exist on pre-ctg.
11085          * As the flip done interrupt doesn't trigger for mmio
11086          * flips on gmch platforms, a flip count check isn't
11087          * really needed there. But since ctg has the registers,
11088          * include it in the check anyway.
11089          */
11090         if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
11091                 return true;
11092
11093         /*
11094          * BDW signals flip done immediately if the plane
11095          * is disabled, even if the plane enable is already
11096          * armed to occur at the next vblank :(
11097          */
11098
11099         /*
11100          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
11101          * used the same base address. In that case the mmio flip might
11102          * have completed, but the CS hasn't even executed the flip yet.
11103          *
11104          * A flip count check isn't enough as the CS might have updated
11105          * the base address just after start of vblank, but before we
11106          * managed to process the interrupt. This means we'd complete the
11107          * CS flip too soon.
11108          *
11109          * Combining both checks should get us a good enough result. It may
11110          * still happen that the CS flip has been executed, but has not
11111          * yet actually completed. But in case the base address is the same
11112          * anyway, we don't really care.
11113          */
11114         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
11115                 crtc->flip_work->gtt_offset &&
11116                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
11117                                     crtc->flip_work->flip_count);
11118 }
11119
11120 static bool
11121 __pageflip_finished_mmio(struct intel_crtc *crtc,
11122                                struct intel_flip_work *work)
11123 {
11124         /*
11125          * MMIO work completes when vblank is different from
11126          * flip_queued_vblank.
11127          *
11128          * Reset counter value doesn't matter, this is handled by
11129          * i915_wait_request finishing early, so no need to handle
11130          * reset here.
11131          */
11132         return intel_crtc_get_vblank_counter(crtc) != work->flip_queued_vblank;
11133 }
11134
11135
11136 static bool pageflip_finished(struct intel_crtc *crtc,
11137                               struct intel_flip_work *work)
11138 {
11139         if (!atomic_read(&work->pending))
11140                 return false;
11141
11142         smp_rmb();
11143
11144         if (is_mmio_work(work))
11145                 return __pageflip_finished_mmio(crtc, work);
11146         else
11147                 return __pageflip_finished_cs(crtc, work);
11148 }
11149
11150 void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe)
11151 {
11152         struct drm_device *dev = dev_priv->dev;
11153         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11154         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11155         struct intel_flip_work *work;
11156         unsigned long flags;
11157
11158         /* Ignore early vblank irqs */
11159         if (!crtc)
11160                 return;
11161
11162         /*
11163          * This is called both by irq handlers and the reset code (to complete
11164          * lost pageflips) so needs the full irqsave spinlocks.
11165          */
11166         spin_lock_irqsave(&dev->event_lock, flags);
11167         work = intel_crtc->flip_work;
11168
11169         if (work != NULL &&
11170             !is_mmio_work(work) &&
11171             pageflip_finished(intel_crtc, work))
11172                 page_flip_completed(intel_crtc);
11173
11174         spin_unlock_irqrestore(&dev->event_lock, flags);
11175 }
11176
11177 void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe)
11178 {
11179         struct drm_device *dev = dev_priv->dev;
11180         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11181         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11182         struct intel_flip_work *work;
11183         unsigned long flags;
11184
11185         /* Ignore early vblank irqs */
11186         if (!crtc)
11187                 return;
11188
11189         /*
11190          * This is called both by irq handlers and the reset code (to complete
11191          * lost pageflips) so needs the full irqsave spinlocks.
11192          */
11193         spin_lock_irqsave(&dev->event_lock, flags);
11194         work = intel_crtc->flip_work;
11195
11196         if (work != NULL &&
11197             is_mmio_work(work) &&
11198             pageflip_finished(intel_crtc, work))
11199                 page_flip_completed(intel_crtc);
11200
11201         spin_unlock_irqrestore(&dev->event_lock, flags);
11202 }
11203
11204 static inline void intel_mark_page_flip_active(struct intel_crtc *crtc,
11205                                                struct intel_flip_work *work)
11206 {
11207         work->flip_queued_vblank = intel_crtc_get_vblank_counter(crtc);
11208
11209         /* Ensure that the work item is consistent when activating it ... */
11210         smp_mb__before_atomic();
11211         atomic_set(&work->pending, 1);
11212 }
11213
11214 static int intel_gen2_queue_flip(struct drm_device *dev,
11215                                  struct drm_crtc *crtc,
11216                                  struct drm_framebuffer *fb,
11217                                  struct drm_i915_gem_object *obj,
11218                                  struct drm_i915_gem_request *req,
11219                                  uint32_t flags)
11220 {
11221         struct intel_engine_cs *engine = req->engine;
11222         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11223         u32 flip_mask;
11224         int ret;
11225
11226         ret = intel_ring_begin(req, 6);
11227         if (ret)
11228                 return ret;
11229
11230         /* Can't queue multiple flips, so wait for the previous
11231          * one to finish before executing the next.
11232          */
11233         if (intel_crtc->plane)
11234                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11235         else
11236                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11237         intel_ring_emit(engine, MI_WAIT_FOR_EVENT | flip_mask);
11238         intel_ring_emit(engine, MI_NOOP);
11239         intel_ring_emit(engine, MI_DISPLAY_FLIP |
11240                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11241         intel_ring_emit(engine, fb->pitches[0]);
11242         intel_ring_emit(engine, intel_crtc->flip_work->gtt_offset);
11243         intel_ring_emit(engine, 0); /* aux display base address, unused */
11244
11245         return 0;
11246 }
11247
11248 static int intel_gen3_queue_flip(struct drm_device *dev,
11249                                  struct drm_crtc *crtc,
11250                                  struct drm_framebuffer *fb,
11251                                  struct drm_i915_gem_object *obj,
11252                                  struct drm_i915_gem_request *req,
11253                                  uint32_t flags)
11254 {
11255         struct intel_engine_cs *engine = req->engine;
11256         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11257         u32 flip_mask;
11258         int ret;
11259
11260         ret = intel_ring_begin(req, 6);
11261         if (ret)
11262                 return ret;
11263
11264         if (intel_crtc->plane)
11265                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11266         else
11267                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11268         intel_ring_emit(engine, MI_WAIT_FOR_EVENT | flip_mask);
11269         intel_ring_emit(engine, MI_NOOP);
11270         intel_ring_emit(engine, MI_DISPLAY_FLIP_I915 |
11271                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11272         intel_ring_emit(engine, fb->pitches[0]);
11273         intel_ring_emit(engine, intel_crtc->flip_work->gtt_offset);
11274         intel_ring_emit(engine, MI_NOOP);
11275
11276         return 0;
11277 }
11278
11279 static int intel_gen4_queue_flip(struct drm_device *dev,
11280                                  struct drm_crtc *crtc,
11281                                  struct drm_framebuffer *fb,
11282                                  struct drm_i915_gem_object *obj,
11283                                  struct drm_i915_gem_request *req,
11284                                  uint32_t flags)
11285 {
11286         struct intel_engine_cs *engine = req->engine;
11287         struct drm_i915_private *dev_priv = dev->dev_private;
11288         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11289         uint32_t pf, pipesrc;
11290         int ret;
11291
11292         ret = intel_ring_begin(req, 4);
11293         if (ret)
11294                 return ret;
11295
11296         /* i965+ uses the linear or tiled offsets from the
11297          * Display Registers (which do not change across a page-flip)
11298          * so we need only reprogram the base address.
11299          */
11300         intel_ring_emit(engine, MI_DISPLAY_FLIP |
11301                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11302         intel_ring_emit(engine, fb->pitches[0]);
11303         intel_ring_emit(engine, intel_crtc->flip_work->gtt_offset |
11304                         obj->tiling_mode);
11305
11306         /* XXX Enabling the panel-fitter across page-flip is so far
11307          * untested on non-native modes, so ignore it for now.
11308          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11309          */
11310         pf = 0;
11311         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11312         intel_ring_emit(engine, pf | pipesrc);
11313
11314         return 0;
11315 }
11316
11317 static int intel_gen6_queue_flip(struct drm_device *dev,
11318                                  struct drm_crtc *crtc,
11319                                  struct drm_framebuffer *fb,
11320                                  struct drm_i915_gem_object *obj,
11321                                  struct drm_i915_gem_request *req,
11322                                  uint32_t flags)
11323 {
11324         struct intel_engine_cs *engine = req->engine;
11325         struct drm_i915_private *dev_priv = dev->dev_private;
11326         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11327         uint32_t pf, pipesrc;
11328         int ret;
11329
11330         ret = intel_ring_begin(req, 4);
11331         if (ret)
11332                 return ret;
11333
11334         intel_ring_emit(engine, MI_DISPLAY_FLIP |
11335                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11336         intel_ring_emit(engine, fb->pitches[0] | obj->tiling_mode);
11337         intel_ring_emit(engine, intel_crtc->flip_work->gtt_offset);
11338
11339         /* Contrary to the suggestions in the documentation,
11340          * "Enable Panel Fitter" does not seem to be required when page
11341          * flipping with a non-native mode, and worse causes a normal
11342          * modeset to fail.
11343          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11344          */
11345         pf = 0;
11346         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11347         intel_ring_emit(engine, pf | pipesrc);
11348
11349         return 0;
11350 }
11351
11352 static int intel_gen7_queue_flip(struct drm_device *dev,
11353                                  struct drm_crtc *crtc,
11354                                  struct drm_framebuffer *fb,
11355                                  struct drm_i915_gem_object *obj,
11356                                  struct drm_i915_gem_request *req,
11357                                  uint32_t flags)
11358 {
11359         struct intel_engine_cs *engine = req->engine;
11360         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11361         uint32_t plane_bit = 0;
11362         int len, ret;
11363
11364         switch (intel_crtc->plane) {
11365         case PLANE_A:
11366                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11367                 break;
11368         case PLANE_B:
11369                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11370                 break;
11371         case PLANE_C:
11372                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11373                 break;
11374         default:
11375                 WARN_ONCE(1, "unknown plane in flip command\n");
11376                 return -ENODEV;
11377         }
11378
11379         len = 4;
11380         if (engine->id == RCS) {
11381                 len += 6;
11382                 /*
11383                  * On Gen 8, SRM is now taking an extra dword to accommodate
11384                  * 48bits addresses, and we need a NOOP for the batch size to
11385                  * stay even.
11386                  */
11387                 if (IS_GEN8(dev))
11388                         len += 2;
11389         }
11390
11391         /*
11392          * BSpec MI_DISPLAY_FLIP for IVB:
11393          * "The full packet must be contained within the same cache line."
11394          *
11395          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11396          * cacheline, if we ever start emitting more commands before
11397          * the MI_DISPLAY_FLIP we may need to first emit everything else,
11398          * then do the cacheline alignment, and finally emit the
11399          * MI_DISPLAY_FLIP.
11400          */
11401         ret = intel_ring_cacheline_align(req);
11402         if (ret)
11403                 return ret;
11404
11405         ret = intel_ring_begin(req, len);
11406         if (ret)
11407                 return ret;
11408
11409         /* Unmask the flip-done completion message. Note that the bspec says that
11410          * we should do this for both the BCS and RCS, and that we must not unmask
11411          * more than one flip event at any time (or ensure that one flip message
11412          * can be sent by waiting for flip-done prior to queueing new flips).
11413          * Experimentation says that BCS works despite DERRMR masking all
11414          * flip-done completion events and that unmasking all planes at once
11415          * for the RCS also doesn't appear to drop events. Setting the DERRMR
11416          * to zero does lead to lockups within MI_DISPLAY_FLIP.
11417          */
11418         if (engine->id == RCS) {
11419                 intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(1));
11420                 intel_ring_emit_reg(engine, DERRMR);
11421                 intel_ring_emit(engine, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11422                                           DERRMR_PIPEB_PRI_FLIP_DONE |
11423                                           DERRMR_PIPEC_PRI_FLIP_DONE));
11424                 if (IS_GEN8(dev))
11425                         intel_ring_emit(engine, MI_STORE_REGISTER_MEM_GEN8 |
11426                                               MI_SRM_LRM_GLOBAL_GTT);
11427                 else
11428                         intel_ring_emit(engine, MI_STORE_REGISTER_MEM |
11429                                               MI_SRM_LRM_GLOBAL_GTT);
11430                 intel_ring_emit_reg(engine, DERRMR);
11431                 intel_ring_emit(engine, engine->scratch.gtt_offset + 256);
11432                 if (IS_GEN8(dev)) {
11433                         intel_ring_emit(engine, 0);
11434                         intel_ring_emit(engine, MI_NOOP);
11435                 }
11436         }
11437
11438         intel_ring_emit(engine, MI_DISPLAY_FLIP_I915 | plane_bit);
11439         intel_ring_emit(engine, (fb->pitches[0] | obj->tiling_mode));
11440         intel_ring_emit(engine, intel_crtc->flip_work->gtt_offset);
11441         intel_ring_emit(engine, (MI_NOOP));
11442
11443         return 0;
11444 }
11445
11446 static bool use_mmio_flip(struct intel_engine_cs *engine,
11447                           struct drm_i915_gem_object *obj)
11448 {
11449         struct reservation_object *resv;
11450
11451         /*
11452          * This is not being used for older platforms, because
11453          * non-availability of flip done interrupt forces us to use
11454          * CS flips. Older platforms derive flip done using some clever
11455          * tricks involving the flip_pending status bits and vblank irqs.
11456          * So using MMIO flips there would disrupt this mechanism.
11457          */
11458
11459         if (engine == NULL)
11460                 return true;
11461
11462         if (INTEL_GEN(engine->i915) < 5)
11463                 return false;
11464
11465         if (i915.use_mmio_flip < 0)
11466                 return false;
11467         else if (i915.use_mmio_flip > 0)
11468                 return true;
11469         else if (i915.enable_execlists)
11470                 return true;
11471
11472         resv = i915_gem_object_get_dmabuf_resv(obj);
11473         if (resv && !reservation_object_test_signaled_rcu(resv, false))
11474                 return true;
11475
11476         return engine != i915_gem_request_get_engine(obj->last_write_req);
11477 }
11478
11479 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
11480                              unsigned int rotation,
11481                              struct intel_flip_work *work)
11482 {
11483         struct drm_device *dev = intel_crtc->base.dev;
11484         struct drm_i915_private *dev_priv = dev->dev_private;
11485         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11486         const enum pipe pipe = intel_crtc->pipe;
11487         u32 ctl, stride, tile_height;
11488
11489         ctl = I915_READ(PLANE_CTL(pipe, 0));
11490         ctl &= ~PLANE_CTL_TILED_MASK;
11491         switch (fb->modifier[0]) {
11492         case DRM_FORMAT_MOD_NONE:
11493                 break;
11494         case I915_FORMAT_MOD_X_TILED:
11495                 ctl |= PLANE_CTL_TILED_X;
11496                 break;
11497         case I915_FORMAT_MOD_Y_TILED:
11498                 ctl |= PLANE_CTL_TILED_Y;
11499                 break;
11500         case I915_FORMAT_MOD_Yf_TILED:
11501                 ctl |= PLANE_CTL_TILED_YF;
11502                 break;
11503         default:
11504                 MISSING_CASE(fb->modifier[0]);
11505         }
11506
11507         /*
11508          * The stride is either expressed as a multiple of 64 bytes chunks for
11509          * linear buffers or in number of tiles for tiled buffers.
11510          */
11511         if (intel_rotation_90_or_270(rotation)) {
11512                 /* stride = Surface height in tiles */
11513                 tile_height = intel_tile_height(dev_priv, fb->modifier[0], 0);
11514                 stride = DIV_ROUND_UP(fb->height, tile_height);
11515         } else {
11516                 stride = fb->pitches[0] /
11517                         intel_fb_stride_alignment(dev_priv, fb->modifier[0],
11518                                                   fb->pixel_format);
11519         }
11520
11521         /*
11522          * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11523          * PLANE_SURF updates, the update is then guaranteed to be atomic.
11524          */
11525         I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11526         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11527
11528         I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
11529         POSTING_READ(PLANE_SURF(pipe, 0));
11530 }
11531
11532 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
11533                              struct intel_flip_work *work)
11534 {
11535         struct drm_device *dev = intel_crtc->base.dev;
11536         struct drm_i915_private *dev_priv = dev->dev_private;
11537         struct intel_framebuffer *intel_fb =
11538                 to_intel_framebuffer(intel_crtc->base.primary->fb);
11539         struct drm_i915_gem_object *obj = intel_fb->obj;
11540         i915_reg_t reg = DSPCNTR(intel_crtc->plane);
11541         u32 dspcntr;
11542
11543         dspcntr = I915_READ(reg);
11544
11545         if (obj->tiling_mode != I915_TILING_NONE)
11546                 dspcntr |= DISPPLANE_TILED;
11547         else
11548                 dspcntr &= ~DISPPLANE_TILED;
11549
11550         I915_WRITE(reg, dspcntr);
11551
11552         I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
11553         POSTING_READ(DSPSURF(intel_crtc->plane));
11554 }
11555
11556 static void intel_mmio_flip_work_func(struct work_struct *w)
11557 {
11558         struct intel_flip_work *work =
11559                 container_of(w, struct intel_flip_work, mmio_work);
11560         struct intel_crtc *crtc = to_intel_crtc(work->crtc);
11561         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11562         struct intel_framebuffer *intel_fb =
11563                 to_intel_framebuffer(crtc->base.primary->fb);
11564         struct drm_i915_gem_object *obj = intel_fb->obj;
11565         struct reservation_object *resv;
11566
11567         if (work->flip_queued_req)
11568                 WARN_ON(__i915_wait_request(work->flip_queued_req,
11569                                             false, NULL,
11570                                             &dev_priv->rps.mmioflips));
11571
11572         /* For framebuffer backed by dmabuf, wait for fence */
11573         resv = i915_gem_object_get_dmabuf_resv(obj);
11574         if (resv)
11575                 WARN_ON(reservation_object_wait_timeout_rcu(resv, false, false,
11576                                                             MAX_SCHEDULE_TIMEOUT) < 0);
11577
11578         intel_pipe_update_start(crtc);
11579
11580         if (INTEL_GEN(dev_priv) >= 9)
11581                 skl_do_mmio_flip(crtc, work->rotation, work);
11582         else
11583                 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11584                 ilk_do_mmio_flip(crtc, work);
11585
11586         intel_pipe_update_end(crtc, work);
11587 }
11588
11589 static int intel_default_queue_flip(struct drm_device *dev,
11590                                     struct drm_crtc *crtc,
11591                                     struct drm_framebuffer *fb,
11592                                     struct drm_i915_gem_object *obj,
11593                                     struct drm_i915_gem_request *req,
11594                                     uint32_t flags)
11595 {
11596         return -ENODEV;
11597 }
11598
11599 static bool __pageflip_stall_check_cs(struct drm_i915_private *dev_priv,
11600                                       struct intel_crtc *intel_crtc,
11601                                       struct intel_flip_work *work)
11602 {
11603         u32 addr, vblank;
11604
11605         if (!atomic_read(&work->pending))
11606                 return false;
11607
11608         smp_rmb();
11609
11610         vblank = intel_crtc_get_vblank_counter(intel_crtc);
11611         if (work->flip_ready_vblank == 0) {
11612                 if (work->flip_queued_req &&
11613                     !i915_gem_request_completed(work->flip_queued_req, true))
11614                         return false;
11615
11616                 work->flip_ready_vblank = vblank;
11617         }
11618
11619         if (vblank - work->flip_ready_vblank < 3)
11620                 return false;
11621
11622         /* Potential stall - if we see that the flip has happened,
11623          * assume a missed interrupt. */
11624         if (INTEL_GEN(dev_priv) >= 4)
11625                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11626         else
11627                 addr = I915_READ(DSPADDR(intel_crtc->plane));
11628
11629         /* There is a potential issue here with a false positive after a flip
11630          * to the same address. We could address this by checking for a
11631          * non-incrementing frame counter.
11632          */
11633         return addr == work->gtt_offset;
11634 }
11635
11636 void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe)
11637 {
11638         struct drm_device *dev = dev_priv->dev;
11639         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11640         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11641         struct intel_flip_work *work;
11642
11643         WARN_ON(!in_interrupt());
11644
11645         if (crtc == NULL)
11646                 return;
11647
11648         spin_lock(&dev->event_lock);
11649         work = intel_crtc->flip_work;
11650
11651         if (work != NULL && !is_mmio_work(work) &&
11652             __pageflip_stall_check_cs(dev_priv, intel_crtc, work)) {
11653                 WARN_ONCE(1,
11654                           "Kicking stuck page flip: queued at %d, now %d\n",
11655                         work->flip_queued_vblank, intel_crtc_get_vblank_counter(intel_crtc));
11656                 page_flip_completed(intel_crtc);
11657                 work = NULL;
11658         }
11659
11660         if (work != NULL && !is_mmio_work(work) &&
11661             intel_crtc_get_vblank_counter(intel_crtc) - work->flip_queued_vblank > 1)
11662                 intel_queue_rps_boost_for_request(work->flip_queued_req);
11663         spin_unlock(&dev->event_lock);
11664 }
11665
11666 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11667                                 struct drm_framebuffer *fb,
11668                                 struct drm_pending_vblank_event *event,
11669                                 uint32_t page_flip_flags)
11670 {
11671         struct drm_device *dev = crtc->dev;
11672         struct drm_i915_private *dev_priv = dev->dev_private;
11673         struct drm_framebuffer *old_fb = crtc->primary->fb;
11674         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11675         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11676         struct drm_plane *primary = crtc->primary;
11677         enum pipe pipe = intel_crtc->pipe;
11678         struct intel_flip_work *work;
11679         struct intel_engine_cs *engine;
11680         bool mmio_flip;
11681         struct drm_i915_gem_request *request = NULL;
11682         int ret;
11683
11684         /*
11685          * drm_mode_page_flip_ioctl() should already catch this, but double
11686          * check to be safe.  In the future we may enable pageflipping from
11687          * a disabled primary plane.
11688          */
11689         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11690                 return -EBUSY;
11691
11692         /* Can't change pixel format via MI display flips. */
11693         if (fb->pixel_format != crtc->primary->fb->pixel_format)
11694                 return -EINVAL;
11695
11696         /*
11697          * TILEOFF/LINOFF registers can't be changed via MI display flips.
11698          * Note that pitch changes could also affect these register.
11699          */
11700         if (INTEL_INFO(dev)->gen > 3 &&
11701             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11702              fb->pitches[0] != crtc->primary->fb->pitches[0]))
11703                 return -EINVAL;
11704
11705         if (i915_terminally_wedged(&dev_priv->gpu_error))
11706                 goto out_hang;
11707
11708         work = kzalloc(sizeof(*work), GFP_KERNEL);
11709         if (work == NULL)
11710                 return -ENOMEM;
11711
11712         work->event = event;
11713         work->crtc = crtc;
11714         work->old_fb = old_fb;
11715         INIT_WORK(&work->unpin_work, intel_unpin_work_fn);
11716
11717         ret = drm_crtc_vblank_get(crtc);
11718         if (ret)
11719                 goto free_work;
11720
11721         /* We borrow the event spin lock for protecting flip_work */
11722         spin_lock_irq(&dev->event_lock);
11723         if (intel_crtc->flip_work) {
11724                 /* Before declaring the flip queue wedged, check if
11725                  * the hardware completed the operation behind our backs.
11726                  */
11727                 if (pageflip_finished(intel_crtc, intel_crtc->flip_work)) {
11728                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11729                         page_flip_completed(intel_crtc);
11730                 } else {
11731                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11732                         spin_unlock_irq(&dev->event_lock);
11733
11734                         drm_crtc_vblank_put(crtc);
11735                         kfree(work);
11736                         return -EBUSY;
11737                 }
11738         }
11739         intel_crtc->flip_work = work;
11740         spin_unlock_irq(&dev->event_lock);
11741
11742         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11743                 flush_workqueue(dev_priv->wq);
11744
11745         /* Reference the objects for the scheduled work. */
11746         drm_framebuffer_reference(work->old_fb);
11747         drm_gem_object_reference(&obj->base);
11748
11749         crtc->primary->fb = fb;
11750         update_state_fb(crtc->primary);
11751
11752         intel_fbc_pre_update(intel_crtc, intel_crtc->config,
11753                              to_intel_plane_state(primary->state));
11754
11755         work->pending_flip_obj = obj;
11756
11757         ret = i915_mutex_lock_interruptible(dev);
11758         if (ret)
11759                 goto cleanup;
11760
11761         intel_crtc->reset_counter = i915_reset_counter(&dev_priv->gpu_error);
11762         if (__i915_reset_in_progress_or_wedged(intel_crtc->reset_counter)) {
11763                 ret = -EIO;
11764                 goto cleanup;
11765         }
11766
11767         atomic_inc(&intel_crtc->unpin_work_count);
11768
11769         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11770                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
11771
11772         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
11773                 engine = &dev_priv->engine[BCS];
11774                 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11775                         /* vlv: DISPLAY_FLIP fails to change tiling */
11776                         engine = NULL;
11777         } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11778                 engine = &dev_priv->engine[BCS];
11779         } else if (INTEL_INFO(dev)->gen >= 7) {
11780                 engine = i915_gem_request_get_engine(obj->last_write_req);
11781                 if (engine == NULL || engine->id != RCS)
11782                         engine = &dev_priv->engine[BCS];
11783         } else {
11784                 engine = &dev_priv->engine[RCS];
11785         }
11786
11787         mmio_flip = use_mmio_flip(engine, obj);
11788
11789         /* When using CS flips, we want to emit semaphores between rings.
11790          * However, when using mmio flips we will create a task to do the
11791          * synchronisation, so all we want here is to pin the framebuffer
11792          * into the display plane and skip any waits.
11793          */
11794         if (!mmio_flip) {
11795                 ret = i915_gem_object_sync(obj, engine, &request);
11796                 if (!ret && !request) {
11797                         request = i915_gem_request_alloc(engine, NULL);
11798                         ret = PTR_ERR_OR_ZERO(request);
11799                 }
11800
11801                 if (ret)
11802                         goto cleanup_pending;
11803         }
11804
11805         ret = intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
11806         if (ret)
11807                 goto cleanup_pending;
11808
11809         work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary),
11810                                                   obj, 0);
11811         work->gtt_offset += intel_crtc->dspaddr_offset;
11812         work->rotation = crtc->primary->state->rotation;
11813
11814         if (mmio_flip) {
11815                 INIT_WORK(&work->mmio_work, intel_mmio_flip_work_func);
11816
11817                 i915_gem_request_assign(&work->flip_queued_req,
11818                                         obj->last_write_req);
11819
11820                 schedule_work(&work->mmio_work);
11821         } else {
11822                 i915_gem_request_assign(&work->flip_queued_req, request);
11823                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
11824                                                    page_flip_flags);
11825                 if (ret)
11826                         goto cleanup_unpin;
11827
11828                 intel_mark_page_flip_active(intel_crtc, work);
11829
11830                 i915_add_request_no_flush(request);
11831         }
11832
11833         i915_gem_track_fb(intel_fb_obj(old_fb), obj,
11834                           to_intel_plane(primary)->frontbuffer_bit);
11835         mutex_unlock(&dev->struct_mutex);
11836
11837         intel_frontbuffer_flip_prepare(dev,
11838                                        to_intel_plane(primary)->frontbuffer_bit);
11839
11840         trace_i915_flip_request(intel_crtc->plane, obj);
11841
11842         return 0;
11843
11844 cleanup_unpin:
11845         intel_unpin_fb_obj(fb, crtc->primary->state->rotation);
11846 cleanup_pending:
11847         if (!IS_ERR_OR_NULL(request))
11848                 i915_add_request_no_flush(request);
11849         atomic_dec(&intel_crtc->unpin_work_count);
11850         mutex_unlock(&dev->struct_mutex);
11851 cleanup:
11852         crtc->primary->fb = old_fb;
11853         update_state_fb(crtc->primary);
11854
11855         drm_gem_object_unreference_unlocked(&obj->base);
11856         drm_framebuffer_unreference(work->old_fb);
11857
11858         spin_lock_irq(&dev->event_lock);
11859         intel_crtc->flip_work = NULL;
11860         spin_unlock_irq(&dev->event_lock);
11861
11862         drm_crtc_vblank_put(crtc);
11863 free_work:
11864         kfree(work);
11865
11866         if (ret == -EIO) {
11867                 struct drm_atomic_state *state;
11868                 struct drm_plane_state *plane_state;
11869
11870 out_hang:
11871                 state = drm_atomic_state_alloc(dev);
11872                 if (!state)
11873                         return -ENOMEM;
11874                 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11875
11876 retry:
11877                 plane_state = drm_atomic_get_plane_state(state, primary);
11878                 ret = PTR_ERR_OR_ZERO(plane_state);
11879                 if (!ret) {
11880                         drm_atomic_set_fb_for_plane(plane_state, fb);
11881
11882                         ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11883                         if (!ret)
11884                                 ret = drm_atomic_commit(state);
11885                 }
11886
11887                 if (ret == -EDEADLK) {
11888                         drm_modeset_backoff(state->acquire_ctx);
11889                         drm_atomic_state_clear(state);
11890                         goto retry;
11891                 }
11892
11893                 if (ret)
11894                         drm_atomic_state_free(state);
11895
11896                 if (ret == 0 && event) {
11897                         spin_lock_irq(&dev->event_lock);
11898                         drm_crtc_send_vblank_event(crtc, event);
11899                         spin_unlock_irq(&dev->event_lock);
11900                 }
11901         }
11902         return ret;
11903 }
11904
11905
11906 /**
11907  * intel_wm_need_update - Check whether watermarks need updating
11908  * @plane: drm plane
11909  * @state: new plane state
11910  *
11911  * Check current plane state versus the new one to determine whether
11912  * watermarks need to be recalculated.
11913  *
11914  * Returns true or false.
11915  */
11916 static bool intel_wm_need_update(struct drm_plane *plane,
11917                                  struct drm_plane_state *state)
11918 {
11919         struct intel_plane_state *new = to_intel_plane_state(state);
11920         struct intel_plane_state *cur = to_intel_plane_state(plane->state);
11921
11922         /* Update watermarks on tiling or size changes. */
11923         if (new->visible != cur->visible)
11924                 return true;
11925
11926         if (!cur->base.fb || !new->base.fb)
11927                 return false;
11928
11929         if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] ||
11930             cur->base.rotation != new->base.rotation ||
11931             drm_rect_width(&new->src) != drm_rect_width(&cur->src) ||
11932             drm_rect_height(&new->src) != drm_rect_height(&cur->src) ||
11933             drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) ||
11934             drm_rect_height(&new->dst) != drm_rect_height(&cur->dst))
11935                 return true;
11936
11937         return false;
11938 }
11939
11940 static bool needs_scaling(struct intel_plane_state *state)
11941 {
11942         int src_w = drm_rect_width(&state->src) >> 16;
11943         int src_h = drm_rect_height(&state->src) >> 16;
11944         int dst_w = drm_rect_width(&state->dst);
11945         int dst_h = drm_rect_height(&state->dst);
11946
11947         return (src_w != dst_w || src_h != dst_h);
11948 }
11949
11950 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11951                                     struct drm_plane_state *plane_state)
11952 {
11953         struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
11954         struct drm_crtc *crtc = crtc_state->crtc;
11955         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11956         struct drm_plane *plane = plane_state->plane;
11957         struct drm_device *dev = crtc->dev;
11958         struct drm_i915_private *dev_priv = to_i915(dev);
11959         struct intel_plane_state *old_plane_state =
11960                 to_intel_plane_state(plane->state);
11961         bool mode_changed = needs_modeset(crtc_state);
11962         bool was_crtc_enabled = crtc->state->active;
11963         bool is_crtc_enabled = crtc_state->active;
11964         bool turn_off, turn_on, visible, was_visible;
11965         struct drm_framebuffer *fb = plane_state->fb;
11966         int ret;
11967
11968         if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11969             plane->type != DRM_PLANE_TYPE_CURSOR) {
11970                 ret = skl_update_scaler_plane(
11971                         to_intel_crtc_state(crtc_state),
11972                         to_intel_plane_state(plane_state));
11973                 if (ret)
11974                         return ret;
11975         }
11976
11977         was_visible = old_plane_state->visible;
11978         visible = to_intel_plane_state(plane_state)->visible;
11979
11980         if (!was_crtc_enabled && WARN_ON(was_visible))
11981                 was_visible = false;
11982
11983         /*
11984          * Visibility is calculated as if the crtc was on, but
11985          * after scaler setup everything depends on it being off
11986          * when the crtc isn't active.
11987          *
11988          * FIXME this is wrong for watermarks. Watermarks should also
11989          * be computed as if the pipe would be active. Perhaps move
11990          * per-plane wm computation to the .check_plane() hook, and
11991          * only combine the results from all planes in the current place?
11992          */
11993         if (!is_crtc_enabled)
11994                 to_intel_plane_state(plane_state)->visible = visible = false;
11995
11996         if (!was_visible && !visible)
11997                 return 0;
11998
11999         if (fb != old_plane_state->base.fb)
12000                 pipe_config->fb_changed = true;
12001
12002         turn_off = was_visible && (!visible || mode_changed);
12003         turn_on = visible && (!was_visible || mode_changed);
12004
12005         DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
12006                          intel_crtc->base.base.id,
12007                          intel_crtc->base.name,
12008                          plane->base.id, plane->name,
12009                          fb ? fb->base.id : -1);
12010
12011         DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
12012                          plane->base.id, plane->name,
12013                          was_visible, visible,
12014                          turn_off, turn_on, mode_changed);
12015
12016         if (turn_on) {
12017                 pipe_config->update_wm_pre = true;
12018
12019                 /* must disable cxsr around plane enable/disable */
12020                 if (plane->type != DRM_PLANE_TYPE_CURSOR)
12021                         pipe_config->disable_cxsr = true;
12022         } else if (turn_off) {
12023                 pipe_config->update_wm_post = true;
12024
12025                 /* must disable cxsr around plane enable/disable */
12026                 if (plane->type != DRM_PLANE_TYPE_CURSOR)
12027                         pipe_config->disable_cxsr = true;
12028         } else if (intel_wm_need_update(plane, plane_state)) {
12029                 /* FIXME bollocks */
12030                 pipe_config->update_wm_pre = true;
12031                 pipe_config->update_wm_post = true;
12032         }
12033
12034         /* Pre-gen9 platforms need two-step watermark updates */
12035         if ((pipe_config->update_wm_pre || pipe_config->update_wm_post) &&
12036             INTEL_INFO(dev)->gen < 9 && dev_priv->display.optimize_watermarks)
12037                 to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true;
12038
12039         if (visible || was_visible)
12040                 pipe_config->fb_bits |= to_intel_plane(plane)->frontbuffer_bit;
12041
12042         /*
12043          * WaCxSRDisabledForSpriteScaling:ivb
12044          *
12045          * cstate->update_wm was already set above, so this flag will
12046          * take effect when we commit and program watermarks.
12047          */
12048         if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev) &&
12049             needs_scaling(to_intel_plane_state(plane_state)) &&
12050             !needs_scaling(old_plane_state))
12051                 pipe_config->disable_lp_wm = true;
12052
12053         return 0;
12054 }
12055
12056 static bool encoders_cloneable(const struct intel_encoder *a,
12057                                const struct intel_encoder *b)
12058 {
12059         /* masks could be asymmetric, so check both ways */
12060         return a == b || (a->cloneable & (1 << b->type) &&
12061                           b->cloneable & (1 << a->type));
12062 }
12063
12064 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
12065                                          struct intel_crtc *crtc,
12066                                          struct intel_encoder *encoder)
12067 {
12068         struct intel_encoder *source_encoder;
12069         struct drm_connector *connector;
12070         struct drm_connector_state *connector_state;
12071         int i;
12072
12073         for_each_connector_in_state(state, connector, connector_state, i) {
12074                 if (connector_state->crtc != &crtc->base)
12075                         continue;
12076
12077                 source_encoder =
12078                         to_intel_encoder(connector_state->best_encoder);
12079                 if (!encoders_cloneable(encoder, source_encoder))
12080                         return false;
12081         }
12082
12083         return true;
12084 }
12085
12086 static bool check_encoder_cloning(struct drm_atomic_state *state,
12087                                   struct intel_crtc *crtc)
12088 {
12089         struct intel_encoder *encoder;
12090         struct drm_connector *connector;
12091         struct drm_connector_state *connector_state;
12092         int i;
12093
12094         for_each_connector_in_state(state, connector, connector_state, i) {
12095                 if (connector_state->crtc != &crtc->base)
12096                         continue;
12097
12098                 encoder = to_intel_encoder(connector_state->best_encoder);
12099                 if (!check_single_encoder_cloning(state, crtc, encoder))
12100                         return false;
12101         }
12102
12103         return true;
12104 }
12105
12106 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
12107                                    struct drm_crtc_state *crtc_state)
12108 {
12109         struct drm_device *dev = crtc->dev;
12110         struct drm_i915_private *dev_priv = dev->dev_private;
12111         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12112         struct intel_crtc_state *pipe_config =
12113                 to_intel_crtc_state(crtc_state);
12114         struct drm_atomic_state *state = crtc_state->state;
12115         int ret;
12116         bool mode_changed = needs_modeset(crtc_state);
12117
12118         if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
12119                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
12120                 return -EINVAL;
12121         }
12122
12123         if (mode_changed && !crtc_state->active)
12124                 pipe_config->update_wm_post = true;
12125
12126         if (mode_changed && crtc_state->enable &&
12127             dev_priv->display.crtc_compute_clock &&
12128             !WARN_ON(pipe_config->shared_dpll)) {
12129                 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
12130                                                            pipe_config);
12131                 if (ret)
12132                         return ret;
12133         }
12134
12135         if (crtc_state->color_mgmt_changed) {
12136                 ret = intel_color_check(crtc, crtc_state);
12137                 if (ret)
12138                         return ret;
12139         }
12140
12141         ret = 0;
12142         if (dev_priv->display.compute_pipe_wm) {
12143                 ret = dev_priv->display.compute_pipe_wm(pipe_config);
12144                 if (ret) {
12145                         DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
12146                         return ret;
12147                 }
12148         }
12149
12150         if (dev_priv->display.compute_intermediate_wm &&
12151             !to_intel_atomic_state(state)->skip_intermediate_wm) {
12152                 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
12153                         return 0;
12154
12155                 /*
12156                  * Calculate 'intermediate' watermarks that satisfy both the
12157                  * old state and the new state.  We can program these
12158                  * immediately.
12159                  */
12160                 ret = dev_priv->display.compute_intermediate_wm(crtc->dev,
12161                                                                 intel_crtc,
12162                                                                 pipe_config);
12163                 if (ret) {
12164                         DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
12165                         return ret;
12166                 }
12167         } else if (dev_priv->display.compute_intermediate_wm) {
12168                 if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9)
12169                         pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal;
12170         }
12171
12172         if (INTEL_INFO(dev)->gen >= 9) {
12173                 if (mode_changed)
12174                         ret = skl_update_scaler_crtc(pipe_config);
12175
12176                 if (!ret)
12177                         ret = intel_atomic_setup_scalers(dev, intel_crtc,
12178                                                          pipe_config);
12179         }
12180
12181         return ret;
12182 }
12183
12184 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
12185         .mode_set_base_atomic = intel_pipe_set_base_atomic,
12186         .atomic_begin = intel_begin_crtc_commit,
12187         .atomic_flush = intel_finish_crtc_commit,
12188         .atomic_check = intel_crtc_atomic_check,
12189 };
12190
12191 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
12192 {
12193         struct intel_connector *connector;
12194
12195         for_each_intel_connector(dev, connector) {
12196                 if (connector->base.state->crtc)
12197                         drm_connector_unreference(&connector->base);
12198
12199                 if (connector->base.encoder) {
12200                         connector->base.state->best_encoder =
12201                                 connector->base.encoder;
12202                         connector->base.state->crtc =
12203                                 connector->base.encoder->crtc;
12204
12205                         drm_connector_reference(&connector->base);
12206                 } else {
12207                         connector->base.state->best_encoder = NULL;
12208                         connector->base.state->crtc = NULL;
12209                 }
12210         }
12211 }
12212
12213 static void
12214 connected_sink_compute_bpp(struct intel_connector *connector,
12215                            struct intel_crtc_state *pipe_config)
12216 {
12217         int bpp = pipe_config->pipe_bpp;
12218
12219         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
12220                 connector->base.base.id,
12221                 connector->base.name);
12222
12223         /* Don't use an invalid EDID bpc value */
12224         if (connector->base.display_info.bpc &&
12225             connector->base.display_info.bpc * 3 < bpp) {
12226                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
12227                               bpp, connector->base.display_info.bpc*3);
12228                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
12229         }
12230
12231         /* Clamp bpp to default limit on screens without EDID 1.4 */
12232         if (connector->base.display_info.bpc == 0) {
12233                 int type = connector->base.connector_type;
12234                 int clamp_bpp = 24;
12235
12236                 /* Fall back to 18 bpp when DP sink capability is unknown. */
12237                 if (type == DRM_MODE_CONNECTOR_DisplayPort ||
12238                     type == DRM_MODE_CONNECTOR_eDP)
12239                         clamp_bpp = 18;
12240
12241                 if (bpp > clamp_bpp) {
12242                         DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of %d\n",
12243                                       bpp, clamp_bpp);
12244                         pipe_config->pipe_bpp = clamp_bpp;
12245                 }
12246         }
12247 }
12248
12249 static int
12250 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
12251                           struct intel_crtc_state *pipe_config)
12252 {
12253         struct drm_device *dev = crtc->base.dev;
12254         struct drm_atomic_state *state;
12255         struct drm_connector *connector;
12256         struct drm_connector_state *connector_state;
12257         int bpp, i;
12258
12259         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)))
12260                 bpp = 10*3;
12261         else if (INTEL_INFO(dev)->gen >= 5)
12262                 bpp = 12*3;
12263         else
12264                 bpp = 8*3;
12265
12266
12267         pipe_config->pipe_bpp = bpp;
12268
12269         state = pipe_config->base.state;
12270
12271         /* Clamp display bpp to EDID value */
12272         for_each_connector_in_state(state, connector, connector_state, i) {
12273                 if (connector_state->crtc != &crtc->base)
12274                         continue;
12275
12276                 connected_sink_compute_bpp(to_intel_connector(connector),
12277                                            pipe_config);
12278         }
12279
12280         return bpp;
12281 }
12282
12283 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
12284 {
12285         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12286                         "type: 0x%x flags: 0x%x\n",
12287                 mode->crtc_clock,
12288                 mode->crtc_hdisplay, mode->crtc_hsync_start,
12289                 mode->crtc_hsync_end, mode->crtc_htotal,
12290                 mode->crtc_vdisplay, mode->crtc_vsync_start,
12291                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
12292 }
12293
12294 static void intel_dump_pipe_config(struct intel_crtc *crtc,
12295                                    struct intel_crtc_state *pipe_config,
12296                                    const char *context)
12297 {
12298         struct drm_device *dev = crtc->base.dev;
12299         struct drm_plane *plane;
12300         struct intel_plane *intel_plane;
12301         struct intel_plane_state *state;
12302         struct drm_framebuffer *fb;
12303
12304         DRM_DEBUG_KMS("[CRTC:%d:%s]%s config %p for pipe %c\n",
12305                       crtc->base.base.id, crtc->base.name,
12306                       context, pipe_config, pipe_name(crtc->pipe));
12307
12308         DRM_DEBUG_KMS("cpu_transcoder: %s\n", transcoder_name(pipe_config->cpu_transcoder));
12309         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
12310                       pipe_config->pipe_bpp, pipe_config->dither);
12311         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12312                       pipe_config->has_pch_encoder,
12313                       pipe_config->fdi_lanes,
12314                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
12315                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
12316                       pipe_config->fdi_m_n.tu);
12317         DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12318                       pipe_config->has_dp_encoder,
12319                       pipe_config->lane_count,
12320                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
12321                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
12322                       pipe_config->dp_m_n.tu);
12323
12324         DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
12325                       pipe_config->has_dp_encoder,
12326                       pipe_config->lane_count,
12327                       pipe_config->dp_m2_n2.gmch_m,
12328                       pipe_config->dp_m2_n2.gmch_n,
12329                       pipe_config->dp_m2_n2.link_m,
12330                       pipe_config->dp_m2_n2.link_n,
12331                       pipe_config->dp_m2_n2.tu);
12332
12333         DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12334                       pipe_config->has_audio,
12335                       pipe_config->has_infoframe);
12336
12337         DRM_DEBUG_KMS("requested mode:\n");
12338         drm_mode_debug_printmodeline(&pipe_config->base.mode);
12339         DRM_DEBUG_KMS("adjusted mode:\n");
12340         drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12341         intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
12342         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
12343         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12344                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
12345         DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12346                       crtc->num_scalers,
12347                       pipe_config->scaler_state.scaler_users,
12348                       pipe_config->scaler_state.scaler_id);
12349         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12350                       pipe_config->gmch_pfit.control,
12351                       pipe_config->gmch_pfit.pgm_ratios,
12352                       pipe_config->gmch_pfit.lvds_border_bits);
12353         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12354                       pipe_config->pch_pfit.pos,
12355                       pipe_config->pch_pfit.size,
12356                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
12357         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
12358         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
12359
12360         if (IS_BROXTON(dev)) {
12361                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
12362                               "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12363                               "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
12364                               pipe_config->ddi_pll_sel,
12365                               pipe_config->dpll_hw_state.ebb0,
12366                               pipe_config->dpll_hw_state.ebb4,
12367                               pipe_config->dpll_hw_state.pll0,
12368                               pipe_config->dpll_hw_state.pll1,
12369                               pipe_config->dpll_hw_state.pll2,
12370                               pipe_config->dpll_hw_state.pll3,
12371                               pipe_config->dpll_hw_state.pll6,
12372                               pipe_config->dpll_hw_state.pll8,
12373                               pipe_config->dpll_hw_state.pll9,
12374                               pipe_config->dpll_hw_state.pll10,
12375                               pipe_config->dpll_hw_state.pcsdw12);
12376         } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
12377                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12378                               "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12379                               pipe_config->ddi_pll_sel,
12380                               pipe_config->dpll_hw_state.ctrl1,
12381                               pipe_config->dpll_hw_state.cfgcr1,
12382                               pipe_config->dpll_hw_state.cfgcr2);
12383         } else if (HAS_DDI(dev)) {
12384                 DRM_DEBUG_KMS("ddi_pll_sel: 0x%x; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
12385                               pipe_config->ddi_pll_sel,
12386                               pipe_config->dpll_hw_state.wrpll,
12387                               pipe_config->dpll_hw_state.spll);
12388         } else {
12389                 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12390                               "fp0: 0x%x, fp1: 0x%x\n",
12391                               pipe_config->dpll_hw_state.dpll,
12392                               pipe_config->dpll_hw_state.dpll_md,
12393                               pipe_config->dpll_hw_state.fp0,
12394                               pipe_config->dpll_hw_state.fp1);
12395         }
12396
12397         DRM_DEBUG_KMS("planes on this crtc\n");
12398         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12399                 intel_plane = to_intel_plane(plane);
12400                 if (intel_plane->pipe != crtc->pipe)
12401                         continue;
12402
12403                 state = to_intel_plane_state(plane->state);
12404                 fb = state->base.fb;
12405                 if (!fb) {
12406                         DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n",
12407                                       plane->base.id, plane->name, state->scaler_id);
12408                         continue;
12409                 }
12410
12411                 DRM_DEBUG_KMS("[PLANE:%d:%s] enabled",
12412                               plane->base.id, plane->name);
12413                 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = %s",
12414                               fb->base.id, fb->width, fb->height,
12415                               drm_get_format_name(fb->pixel_format));
12416                 DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n",
12417                               state->scaler_id,
12418                               state->src.x1 >> 16, state->src.y1 >> 16,
12419                               drm_rect_width(&state->src) >> 16,
12420                               drm_rect_height(&state->src) >> 16,
12421                               state->dst.x1, state->dst.y1,
12422                               drm_rect_width(&state->dst),
12423                               drm_rect_height(&state->dst));
12424         }
12425 }
12426
12427 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12428 {
12429         struct drm_device *dev = state->dev;
12430         struct drm_connector *connector;
12431         unsigned int used_ports = 0;
12432
12433         /*
12434          * Walk the connector list instead of the encoder
12435          * list to detect the problem on ddi platforms
12436          * where there's just one encoder per digital port.
12437          */
12438         drm_for_each_connector(connector, dev) {
12439                 struct drm_connector_state *connector_state;
12440                 struct intel_encoder *encoder;
12441
12442                 connector_state = drm_atomic_get_existing_connector_state(state, connector);
12443                 if (!connector_state)
12444                         connector_state = connector->state;
12445
12446                 if (!connector_state->best_encoder)
12447                         continue;
12448
12449                 encoder = to_intel_encoder(connector_state->best_encoder);
12450
12451                 WARN_ON(!connector_state->crtc);
12452
12453                 switch (encoder->type) {
12454                         unsigned int port_mask;
12455                 case INTEL_OUTPUT_UNKNOWN:
12456                         if (WARN_ON(!HAS_DDI(dev)))
12457                                 break;
12458                 case INTEL_OUTPUT_DISPLAYPORT:
12459                 case INTEL_OUTPUT_HDMI:
12460                 case INTEL_OUTPUT_EDP:
12461                         port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12462
12463                         /* the same port mustn't appear more than once */
12464                         if (used_ports & port_mask)
12465                                 return false;
12466
12467                         used_ports |= port_mask;
12468                 default:
12469                         break;
12470                 }
12471         }
12472
12473         return true;
12474 }
12475
12476 static void
12477 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12478 {
12479         struct drm_crtc_state tmp_state;
12480         struct intel_crtc_scaler_state scaler_state;
12481         struct intel_dpll_hw_state dpll_hw_state;
12482         struct intel_shared_dpll *shared_dpll;
12483         uint32_t ddi_pll_sel;
12484         bool force_thru;
12485
12486         /* FIXME: before the switch to atomic started, a new pipe_config was
12487          * kzalloc'd. Code that depends on any field being zero should be
12488          * fixed, so that the crtc_state can be safely duplicated. For now,
12489          * only fields that are know to not cause problems are preserved. */
12490
12491         tmp_state = crtc_state->base;
12492         scaler_state = crtc_state->scaler_state;
12493         shared_dpll = crtc_state->shared_dpll;
12494         dpll_hw_state = crtc_state->dpll_hw_state;
12495         ddi_pll_sel = crtc_state->ddi_pll_sel;
12496         force_thru = crtc_state->pch_pfit.force_thru;
12497
12498         memset(crtc_state, 0, sizeof *crtc_state);
12499
12500         crtc_state->base = tmp_state;
12501         crtc_state->scaler_state = scaler_state;
12502         crtc_state->shared_dpll = shared_dpll;
12503         crtc_state->dpll_hw_state = dpll_hw_state;
12504         crtc_state->ddi_pll_sel = ddi_pll_sel;
12505         crtc_state->pch_pfit.force_thru = force_thru;
12506 }
12507
12508 static int
12509 intel_modeset_pipe_config(struct drm_crtc *crtc,
12510                           struct intel_crtc_state *pipe_config)
12511 {
12512         struct drm_atomic_state *state = pipe_config->base.state;
12513         struct intel_encoder *encoder;
12514         struct drm_connector *connector;
12515         struct drm_connector_state *connector_state;
12516         int base_bpp, ret = -EINVAL;
12517         int i;
12518         bool retry = true;
12519
12520         clear_intel_crtc_state(pipe_config);
12521
12522         pipe_config->cpu_transcoder =
12523                 (enum transcoder) to_intel_crtc(crtc)->pipe;
12524
12525         /*
12526          * Sanitize sync polarity flags based on requested ones. If neither
12527          * positive or negative polarity is requested, treat this as meaning
12528          * negative polarity.
12529          */
12530         if (!(pipe_config->base.adjusted_mode.flags &
12531               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12532                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12533
12534         if (!(pipe_config->base.adjusted_mode.flags &
12535               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12536                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12537
12538         base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12539                                              pipe_config);
12540         if (base_bpp < 0)
12541                 goto fail;
12542
12543         /*
12544          * Determine the real pipe dimensions. Note that stereo modes can
12545          * increase the actual pipe size due to the frame doubling and
12546          * insertion of additional space for blanks between the frame. This
12547          * is stored in the crtc timings. We use the requested mode to do this
12548          * computation to clearly distinguish it from the adjusted mode, which
12549          * can be changed by the connectors in the below retry loop.
12550          */
12551         drm_crtc_get_hv_timing(&pipe_config->base.mode,
12552                                &pipe_config->pipe_src_w,
12553                                &pipe_config->pipe_src_h);
12554
12555 encoder_retry:
12556         /* Ensure the port clock defaults are reset when retrying. */
12557         pipe_config->port_clock = 0;
12558         pipe_config->pixel_multiplier = 1;
12559
12560         /* Fill in default crtc timings, allow encoders to overwrite them. */
12561         drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12562                               CRTC_STEREO_DOUBLE);
12563
12564         /* Pass our mode to the connectors and the CRTC to give them a chance to
12565          * adjust it according to limitations or connector properties, and also
12566          * a chance to reject the mode entirely.
12567          */
12568         for_each_connector_in_state(state, connector, connector_state, i) {
12569                 if (connector_state->crtc != crtc)
12570                         continue;
12571
12572                 encoder = to_intel_encoder(connector_state->best_encoder);
12573
12574                 if (!(encoder->compute_config(encoder, pipe_config))) {
12575                         DRM_DEBUG_KMS("Encoder config failure\n");
12576                         goto fail;
12577                 }
12578         }
12579
12580         /* Set default port clock if not overwritten by the encoder. Needs to be
12581          * done afterwards in case the encoder adjusts the mode. */
12582         if (!pipe_config->port_clock)
12583                 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12584                         * pipe_config->pixel_multiplier;
12585
12586         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12587         if (ret < 0) {
12588                 DRM_DEBUG_KMS("CRTC fixup failed\n");
12589                 goto fail;
12590         }
12591
12592         if (ret == RETRY) {
12593                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12594                         ret = -EINVAL;
12595                         goto fail;
12596                 }
12597
12598                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12599                 retry = false;
12600                 goto encoder_retry;
12601         }
12602
12603         /* Dithering seems to not pass-through bits correctly when it should, so
12604          * only enable it on 6bpc panels. */
12605         pipe_config->dither = pipe_config->pipe_bpp == 6*3;
12606         DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
12607                       base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12608
12609 fail:
12610         return ret;
12611 }
12612
12613 static void
12614 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
12615 {
12616         struct drm_crtc *crtc;
12617         struct drm_crtc_state *crtc_state;
12618         int i;
12619
12620         /* Double check state. */
12621         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12622                 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12623
12624                 /* Update hwmode for vblank functions */
12625                 if (crtc->state->active)
12626                         crtc->hwmode = crtc->state->adjusted_mode;
12627                 else
12628                         crtc->hwmode.crtc_clock = 0;
12629
12630                 /*
12631                  * Update legacy state to satisfy fbc code. This can
12632                  * be removed when fbc uses the atomic state.
12633                  */
12634                 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12635                         struct drm_plane_state *plane_state = crtc->primary->state;
12636
12637                         crtc->primary->fb = plane_state->fb;
12638                         crtc->x = plane_state->src_x >> 16;
12639                         crtc->y = plane_state->src_y >> 16;
12640                 }
12641         }
12642 }
12643
12644 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12645 {
12646         int diff;
12647
12648         if (clock1 == clock2)
12649                 return true;
12650
12651         if (!clock1 || !clock2)
12652                 return false;
12653
12654         diff = abs(clock1 - clock2);
12655
12656         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12657                 return true;
12658
12659         return false;
12660 }
12661
12662 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12663         list_for_each_entry((intel_crtc), \
12664                             &(dev)->mode_config.crtc_list, \
12665                             base.head) \
12666                 for_each_if (mask & (1 <<(intel_crtc)->pipe))
12667
12668 static bool
12669 intel_compare_m_n(unsigned int m, unsigned int n,
12670                   unsigned int m2, unsigned int n2,
12671                   bool exact)
12672 {
12673         if (m == m2 && n == n2)
12674                 return true;
12675
12676         if (exact || !m || !n || !m2 || !n2)
12677                 return false;
12678
12679         BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12680
12681         if (n > n2) {
12682                 while (n > n2) {
12683                         m2 <<= 1;
12684                         n2 <<= 1;
12685                 }
12686         } else if (n < n2) {
12687                 while (n < n2) {
12688                         m <<= 1;
12689                         n <<= 1;
12690                 }
12691         }
12692
12693         if (n != n2)
12694                 return false;
12695
12696         return intel_fuzzy_clock_check(m, m2);
12697 }
12698
12699 static bool
12700 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12701                        struct intel_link_m_n *m2_n2,
12702                        bool adjust)
12703 {
12704         if (m_n->tu == m2_n2->tu &&
12705             intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12706                               m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12707             intel_compare_m_n(m_n->link_m, m_n->link_n,
12708                               m2_n2->link_m, m2_n2->link_n, !adjust)) {
12709                 if (adjust)
12710                         *m2_n2 = *m_n;
12711
12712                 return true;
12713         }
12714
12715         return false;
12716 }
12717
12718 static bool
12719 intel_pipe_config_compare(struct drm_device *dev,
12720                           struct intel_crtc_state *current_config,
12721                           struct intel_crtc_state *pipe_config,
12722                           bool adjust)
12723 {
12724         bool ret = true;
12725
12726 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12727         do { \
12728                 if (!adjust) \
12729                         DRM_ERROR(fmt, ##__VA_ARGS__); \
12730                 else \
12731                         DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12732         } while (0)
12733
12734 #define PIPE_CONF_CHECK_X(name) \
12735         if (current_config->name != pipe_config->name) { \
12736                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12737                           "(expected 0x%08x, found 0x%08x)\n", \
12738                           current_config->name, \
12739                           pipe_config->name); \
12740                 ret = false; \
12741         }
12742
12743 #define PIPE_CONF_CHECK_I(name) \
12744         if (current_config->name != pipe_config->name) { \
12745                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12746                           "(expected %i, found %i)\n", \
12747                           current_config->name, \
12748                           pipe_config->name); \
12749                 ret = false; \
12750         }
12751
12752 #define PIPE_CONF_CHECK_P(name) \
12753         if (current_config->name != pipe_config->name) { \
12754                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12755                           "(expected %p, found %p)\n", \
12756                           current_config->name, \
12757                           pipe_config->name); \
12758                 ret = false; \
12759         }
12760
12761 #define PIPE_CONF_CHECK_M_N(name) \
12762         if (!intel_compare_link_m_n(&current_config->name, \
12763                                     &pipe_config->name,\
12764                                     adjust)) { \
12765                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12766                           "(expected tu %i gmch %i/%i link %i/%i, " \
12767                           "found tu %i, gmch %i/%i link %i/%i)\n", \
12768                           current_config->name.tu, \
12769                           current_config->name.gmch_m, \
12770                           current_config->name.gmch_n, \
12771                           current_config->name.link_m, \
12772                           current_config->name.link_n, \
12773                           pipe_config->name.tu, \
12774                           pipe_config->name.gmch_m, \
12775                           pipe_config->name.gmch_n, \
12776                           pipe_config->name.link_m, \
12777                           pipe_config->name.link_n); \
12778                 ret = false; \
12779         }
12780
12781 /* This is required for BDW+ where there is only one set of registers for
12782  * switching between high and low RR.
12783  * This macro can be used whenever a comparison has to be made between one
12784  * hw state and multiple sw state variables.
12785  */
12786 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12787         if (!intel_compare_link_m_n(&current_config->name, \
12788                                     &pipe_config->name, adjust) && \
12789             !intel_compare_link_m_n(&current_config->alt_name, \
12790                                     &pipe_config->name, adjust)) { \
12791                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12792                           "(expected tu %i gmch %i/%i link %i/%i, " \
12793                           "or tu %i gmch %i/%i link %i/%i, " \
12794                           "found tu %i, gmch %i/%i link %i/%i)\n", \
12795                           current_config->name.tu, \
12796                           current_config->name.gmch_m, \
12797                           current_config->name.gmch_n, \
12798                           current_config->name.link_m, \
12799                           current_config->name.link_n, \
12800                           current_config->alt_name.tu, \
12801                           current_config->alt_name.gmch_m, \
12802                           current_config->alt_name.gmch_n, \
12803                           current_config->alt_name.link_m, \
12804                           current_config->alt_name.link_n, \
12805                           pipe_config->name.tu, \
12806                           pipe_config->name.gmch_m, \
12807                           pipe_config->name.gmch_n, \
12808                           pipe_config->name.link_m, \
12809                           pipe_config->name.link_n); \
12810                 ret = false; \
12811         }
12812
12813 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
12814         if ((current_config->name ^ pipe_config->name) & (mask)) { \
12815                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
12816                           "(expected %i, found %i)\n", \
12817                           current_config->name & (mask), \
12818                           pipe_config->name & (mask)); \
12819                 ret = false; \
12820         }
12821
12822 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12823         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12824                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12825                           "(expected %i, found %i)\n", \
12826                           current_config->name, \
12827                           pipe_config->name); \
12828                 ret = false; \
12829         }
12830
12831 #define PIPE_CONF_QUIRK(quirk)  \
12832         ((current_config->quirks | pipe_config->quirks) & (quirk))
12833
12834         PIPE_CONF_CHECK_I(cpu_transcoder);
12835
12836         PIPE_CONF_CHECK_I(has_pch_encoder);
12837         PIPE_CONF_CHECK_I(fdi_lanes);
12838         PIPE_CONF_CHECK_M_N(fdi_m_n);
12839
12840         PIPE_CONF_CHECK_I(has_dp_encoder);
12841         PIPE_CONF_CHECK_I(lane_count);
12842         PIPE_CONF_CHECK_X(lane_lat_optim_mask);
12843
12844         if (INTEL_INFO(dev)->gen < 8) {
12845                 PIPE_CONF_CHECK_M_N(dp_m_n);
12846
12847                 if (current_config->has_drrs)
12848                         PIPE_CONF_CHECK_M_N(dp_m2_n2);
12849         } else
12850                 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
12851
12852         PIPE_CONF_CHECK_I(has_dsi_encoder);
12853
12854         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12855         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12856         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12857         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12858         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12859         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12860
12861         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12862         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12863         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12864         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12865         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12866         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12867
12868         PIPE_CONF_CHECK_I(pixel_multiplier);
12869         PIPE_CONF_CHECK_I(has_hdmi_sink);
12870         if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12871             IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
12872                 PIPE_CONF_CHECK_I(limited_color_range);
12873         PIPE_CONF_CHECK_I(has_infoframe);
12874
12875         PIPE_CONF_CHECK_I(has_audio);
12876
12877         PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12878                               DRM_MODE_FLAG_INTERLACE);
12879
12880         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12881                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12882                                       DRM_MODE_FLAG_PHSYNC);
12883                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12884                                       DRM_MODE_FLAG_NHSYNC);
12885                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12886                                       DRM_MODE_FLAG_PVSYNC);
12887                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12888                                       DRM_MODE_FLAG_NVSYNC);
12889         }
12890
12891         PIPE_CONF_CHECK_X(gmch_pfit.control);
12892         /* pfit ratios are autocomputed by the hw on gen4+ */
12893         if (INTEL_INFO(dev)->gen < 4)
12894                 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
12895         PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
12896
12897         if (!adjust) {
12898                 PIPE_CONF_CHECK_I(pipe_src_w);
12899                 PIPE_CONF_CHECK_I(pipe_src_h);
12900
12901                 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12902                 if (current_config->pch_pfit.enabled) {
12903                         PIPE_CONF_CHECK_X(pch_pfit.pos);
12904                         PIPE_CONF_CHECK_X(pch_pfit.size);
12905                 }
12906
12907                 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12908         }
12909
12910         /* BDW+ don't expose a synchronous way to read the state */
12911         if (IS_HASWELL(dev))
12912                 PIPE_CONF_CHECK_I(ips_enabled);
12913
12914         PIPE_CONF_CHECK_I(double_wide);
12915
12916         PIPE_CONF_CHECK_X(ddi_pll_sel);
12917
12918         PIPE_CONF_CHECK_P(shared_dpll);
12919         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12920         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12921         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12922         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12923         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12924         PIPE_CONF_CHECK_X(dpll_hw_state.spll);
12925         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12926         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12927         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12928
12929         PIPE_CONF_CHECK_X(dsi_pll.ctrl);
12930         PIPE_CONF_CHECK_X(dsi_pll.div);
12931
12932         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12933                 PIPE_CONF_CHECK_I(pipe_bpp);
12934
12935         PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12936         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12937
12938 #undef PIPE_CONF_CHECK_X
12939 #undef PIPE_CONF_CHECK_I
12940 #undef PIPE_CONF_CHECK_P
12941 #undef PIPE_CONF_CHECK_FLAGS
12942 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12943 #undef PIPE_CONF_QUIRK
12944 #undef INTEL_ERR_OR_DBG_KMS
12945
12946         return ret;
12947 }
12948
12949 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
12950                                            const struct intel_crtc_state *pipe_config)
12951 {
12952         if (pipe_config->has_pch_encoder) {
12953                 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
12954                                                             &pipe_config->fdi_m_n);
12955                 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
12956
12957                 /*
12958                  * FDI already provided one idea for the dotclock.
12959                  * Yell if the encoder disagrees.
12960                  */
12961                 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
12962                      "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12963                      fdi_dotclock, dotclock);
12964         }
12965 }
12966
12967 static void verify_wm_state(struct drm_crtc *crtc,
12968                             struct drm_crtc_state *new_state)
12969 {
12970         struct drm_device *dev = crtc->dev;
12971         struct drm_i915_private *dev_priv = dev->dev_private;
12972         struct skl_ddb_allocation hw_ddb, *sw_ddb;
12973         struct skl_ddb_entry *hw_entry, *sw_entry;
12974         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12975         const enum pipe pipe = intel_crtc->pipe;
12976         int plane;
12977
12978         if (INTEL_INFO(dev)->gen < 9 || !new_state->active)
12979                 return;
12980
12981         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12982         sw_ddb = &dev_priv->wm.skl_hw.ddb;
12983
12984         /* planes */
12985         for_each_plane(dev_priv, pipe, plane) {
12986                 hw_entry = &hw_ddb.plane[pipe][plane];
12987                 sw_entry = &sw_ddb->plane[pipe][plane];
12988
12989                 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12990                         continue;
12991
12992                 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12993                           "(expected (%u,%u), found (%u,%u))\n",
12994                           pipe_name(pipe), plane + 1,
12995                           sw_entry->start, sw_entry->end,
12996                           hw_entry->start, hw_entry->end);
12997         }
12998
12999         /* cursor */
13000         hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
13001         sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
13002
13003         if (!skl_ddb_entry_equal(hw_entry, sw_entry)) {
13004                 DRM_ERROR("mismatch in DDB state pipe %c cursor "
13005                           "(expected (%u,%u), found (%u,%u))\n",
13006                           pipe_name(pipe),
13007                           sw_entry->start, sw_entry->end,
13008                           hw_entry->start, hw_entry->end);
13009         }
13010 }
13011
13012 static void
13013 verify_connector_state(struct drm_device *dev, struct drm_crtc *crtc)
13014 {
13015         struct drm_connector *connector;
13016
13017         drm_for_each_connector(connector, dev) {
13018                 struct drm_encoder *encoder = connector->encoder;
13019                 struct drm_connector_state *state = connector->state;
13020
13021                 if (state->crtc != crtc)
13022                         continue;
13023
13024                 intel_connector_verify_state(to_intel_connector(connector));
13025
13026                 I915_STATE_WARN(state->best_encoder != encoder,
13027                      "connector's atomic encoder doesn't match legacy encoder\n");
13028         }
13029 }
13030
13031 static void
13032 verify_encoder_state(struct drm_device *dev)
13033 {
13034         struct intel_encoder *encoder;
13035         struct intel_connector *connector;
13036
13037         for_each_intel_encoder(dev, encoder) {
13038                 bool enabled = false;
13039                 enum pipe pipe;
13040
13041                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
13042                               encoder->base.base.id,
13043                               encoder->base.name);
13044
13045                 for_each_intel_connector(dev, connector) {
13046                         if (connector->base.state->best_encoder != &encoder->base)
13047                                 continue;
13048                         enabled = true;
13049
13050                         I915_STATE_WARN(connector->base.state->crtc !=
13051                                         encoder->base.crtc,
13052                              "connector's crtc doesn't match encoder crtc\n");
13053                 }
13054
13055                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
13056                      "encoder's enabled state mismatch "
13057                      "(expected %i, found %i)\n",
13058                      !!encoder->base.crtc, enabled);
13059
13060                 if (!encoder->base.crtc) {
13061                         bool active;
13062
13063                         active = encoder->get_hw_state(encoder, &pipe);
13064                         I915_STATE_WARN(active,
13065                              "encoder detached but still enabled on pipe %c.\n",
13066                              pipe_name(pipe));
13067                 }
13068         }
13069 }
13070
13071 static void
13072 verify_crtc_state(struct drm_crtc *crtc,
13073                   struct drm_crtc_state *old_crtc_state,
13074                   struct drm_crtc_state *new_crtc_state)
13075 {
13076         struct drm_device *dev = crtc->dev;
13077         struct drm_i915_private *dev_priv = dev->dev_private;
13078         struct intel_encoder *encoder;
13079         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13080         struct intel_crtc_state *pipe_config, *sw_config;
13081         struct drm_atomic_state *old_state;
13082         bool active;
13083
13084         old_state = old_crtc_state->state;
13085         __drm_atomic_helper_crtc_destroy_state(old_crtc_state);
13086         pipe_config = to_intel_crtc_state(old_crtc_state);
13087         memset(pipe_config, 0, sizeof(*pipe_config));
13088         pipe_config->base.crtc = crtc;
13089         pipe_config->base.state = old_state;
13090
13091         DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
13092
13093         active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
13094
13095         /* hw state is inconsistent with the pipe quirk */
13096         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
13097             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
13098                 active = new_crtc_state->active;
13099
13100         I915_STATE_WARN(new_crtc_state->active != active,
13101              "crtc active state doesn't match with hw state "
13102              "(expected %i, found %i)\n", new_crtc_state->active, active);
13103
13104         I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
13105              "transitional active state does not match atomic hw state "
13106              "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
13107
13108         for_each_encoder_on_crtc(dev, crtc, encoder) {
13109                 enum pipe pipe;
13110
13111                 active = encoder->get_hw_state(encoder, &pipe);
13112                 I915_STATE_WARN(active != new_crtc_state->active,
13113                         "[ENCODER:%i] active %i with crtc active %i\n",
13114                         encoder->base.base.id, active, new_crtc_state->active);
13115
13116                 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
13117                                 "Encoder connected to wrong pipe %c\n",
13118                                 pipe_name(pipe));
13119
13120                 if (active)
13121                         encoder->get_config(encoder, pipe_config);
13122         }
13123
13124         if (!new_crtc_state->active)
13125                 return;
13126
13127         intel_pipe_config_sanity_check(dev_priv, pipe_config);
13128
13129         sw_config = to_intel_crtc_state(crtc->state);
13130         if (!intel_pipe_config_compare(dev, sw_config,
13131                                        pipe_config, false)) {
13132                 I915_STATE_WARN(1, "pipe state doesn't match!\n");
13133                 intel_dump_pipe_config(intel_crtc, pipe_config,
13134                                        "[hw state]");
13135                 intel_dump_pipe_config(intel_crtc, sw_config,
13136                                        "[sw state]");
13137         }
13138 }
13139
13140 static void
13141 verify_single_dpll_state(struct drm_i915_private *dev_priv,
13142                          struct intel_shared_dpll *pll,
13143                          struct drm_crtc *crtc,
13144                          struct drm_crtc_state *new_state)
13145 {
13146         struct intel_dpll_hw_state dpll_hw_state;
13147         unsigned crtc_mask;
13148         bool active;
13149
13150         memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
13151
13152         DRM_DEBUG_KMS("%s\n", pll->name);
13153
13154         active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
13155
13156         if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
13157                 I915_STATE_WARN(!pll->on && pll->active_mask,
13158                      "pll in active use but not on in sw tracking\n");
13159                 I915_STATE_WARN(pll->on && !pll->active_mask,
13160                      "pll is on but not used by any active crtc\n");
13161                 I915_STATE_WARN(pll->on != active,
13162                      "pll on state mismatch (expected %i, found %i)\n",
13163                      pll->on, active);
13164         }
13165
13166         if (!crtc) {
13167                 I915_STATE_WARN(pll->active_mask & ~pll->config.crtc_mask,
13168                                 "more active pll users than references: %x vs %x\n",
13169                                 pll->active_mask, pll->config.crtc_mask);
13170
13171                 return;
13172         }
13173
13174         crtc_mask = 1 << drm_crtc_index(crtc);
13175
13176         if (new_state->active)
13177                 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
13178                                 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
13179                                 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
13180         else
13181                 I915_STATE_WARN(pll->active_mask & crtc_mask,
13182                                 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
13183                                 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
13184
13185         I915_STATE_WARN(!(pll->config.crtc_mask & crtc_mask),
13186                         "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
13187                         crtc_mask, pll->config.crtc_mask);
13188
13189         I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state,
13190                                           &dpll_hw_state,
13191                                           sizeof(dpll_hw_state)),
13192                         "pll hw state mismatch\n");
13193 }
13194
13195 static void
13196 verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
13197                          struct drm_crtc_state *old_crtc_state,
13198                          struct drm_crtc_state *new_crtc_state)
13199 {
13200         struct drm_i915_private *dev_priv = dev->dev_private;
13201         struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
13202         struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
13203
13204         if (new_state->shared_dpll)
13205                 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
13206
13207         if (old_state->shared_dpll &&
13208             old_state->shared_dpll != new_state->shared_dpll) {
13209                 unsigned crtc_mask = 1 << drm_crtc_index(crtc);
13210                 struct intel_shared_dpll *pll = old_state->shared_dpll;
13211
13212                 I915_STATE_WARN(pll->active_mask & crtc_mask,
13213                                 "pll active mismatch (didn't expect pipe %c in active mask)\n",
13214                                 pipe_name(drm_crtc_index(crtc)));
13215                 I915_STATE_WARN(pll->config.crtc_mask & crtc_mask,
13216                                 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
13217                                 pipe_name(drm_crtc_index(crtc)));
13218         }
13219 }
13220
13221 static void
13222 intel_modeset_verify_crtc(struct drm_crtc *crtc,
13223                          struct drm_crtc_state *old_state,
13224                          struct drm_crtc_state *new_state)
13225 {
13226         if (!needs_modeset(new_state) &&
13227             !to_intel_crtc_state(new_state)->update_pipe)
13228                 return;
13229
13230         verify_wm_state(crtc, new_state);
13231         verify_connector_state(crtc->dev, crtc);
13232         verify_crtc_state(crtc, old_state, new_state);
13233         verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
13234 }
13235
13236 static void
13237 verify_disabled_dpll_state(struct drm_device *dev)
13238 {
13239         struct drm_i915_private *dev_priv = dev->dev_private;
13240         int i;
13241
13242         for (i = 0; i < dev_priv->num_shared_dpll; i++)
13243                 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
13244 }
13245
13246 static void
13247 intel_modeset_verify_disabled(struct drm_device *dev)
13248 {
13249         verify_encoder_state(dev);
13250         verify_connector_state(dev, NULL);
13251         verify_disabled_dpll_state(dev);
13252 }
13253
13254 static void update_scanline_offset(struct intel_crtc *crtc)
13255 {
13256         struct drm_device *dev = crtc->base.dev;
13257
13258         /*
13259          * The scanline counter increments at the leading edge of hsync.
13260          *
13261          * On most platforms it starts counting from vtotal-1 on the
13262          * first active line. That means the scanline counter value is
13263          * always one less than what we would expect. Ie. just after
13264          * start of vblank, which also occurs at start of hsync (on the
13265          * last active line), the scanline counter will read vblank_start-1.
13266          *
13267          * On gen2 the scanline counter starts counting from 1 instead
13268          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
13269          * to keep the value positive), instead of adding one.
13270          *
13271          * On HSW+ the behaviour of the scanline counter depends on the output
13272          * type. For DP ports it behaves like most other platforms, but on HDMI
13273          * there's an extra 1 line difference. So we need to add two instead of
13274          * one to the value.
13275          */
13276         if (IS_GEN2(dev)) {
13277                 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
13278                 int vtotal;
13279
13280                 vtotal = adjusted_mode->crtc_vtotal;
13281                 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
13282                         vtotal /= 2;
13283
13284                 crtc->scanline_offset = vtotal - 1;
13285         } else if (HAS_DDI(dev) &&
13286                    intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
13287                 crtc->scanline_offset = 2;
13288         } else
13289                 crtc->scanline_offset = 1;
13290 }
13291
13292 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
13293 {
13294         struct drm_device *dev = state->dev;
13295         struct drm_i915_private *dev_priv = to_i915(dev);
13296         struct intel_shared_dpll_config *shared_dpll = NULL;
13297         struct drm_crtc *crtc;
13298         struct drm_crtc_state *crtc_state;
13299         int i;
13300
13301         if (!dev_priv->display.crtc_compute_clock)
13302                 return;
13303
13304         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13305                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13306                 struct intel_shared_dpll *old_dpll =
13307                         to_intel_crtc_state(crtc->state)->shared_dpll;
13308
13309                 if (!needs_modeset(crtc_state))
13310                         continue;
13311
13312                 to_intel_crtc_state(crtc_state)->shared_dpll = NULL;
13313
13314                 if (!old_dpll)
13315                         continue;
13316
13317                 if (!shared_dpll)
13318                         shared_dpll = intel_atomic_get_shared_dpll_state(state);
13319
13320                 intel_shared_dpll_config_put(shared_dpll, old_dpll, intel_crtc);
13321         }
13322 }
13323
13324 /*
13325  * This implements the workaround described in the "notes" section of the mode
13326  * set sequence documentation. When going from no pipes or single pipe to
13327  * multiple pipes, and planes are enabled after the pipe, we need to wait at
13328  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13329  */
13330 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
13331 {
13332         struct drm_crtc_state *crtc_state;
13333         struct intel_crtc *intel_crtc;
13334         struct drm_crtc *crtc;
13335         struct intel_crtc_state *first_crtc_state = NULL;
13336         struct intel_crtc_state *other_crtc_state = NULL;
13337         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13338         int i;
13339
13340         /* look at all crtc's that are going to be enabled in during modeset */
13341         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13342                 intel_crtc = to_intel_crtc(crtc);
13343
13344                 if (!crtc_state->active || !needs_modeset(crtc_state))
13345                         continue;
13346
13347                 if (first_crtc_state) {
13348                         other_crtc_state = to_intel_crtc_state(crtc_state);
13349                         break;
13350                 } else {
13351                         first_crtc_state = to_intel_crtc_state(crtc_state);
13352                         first_pipe = intel_crtc->pipe;
13353                 }
13354         }
13355
13356         /* No workaround needed? */
13357         if (!first_crtc_state)
13358                 return 0;
13359
13360         /* w/a possibly needed, check how many crtc's are already enabled. */
13361         for_each_intel_crtc(state->dev, intel_crtc) {
13362                 struct intel_crtc_state *pipe_config;
13363
13364                 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
13365                 if (IS_ERR(pipe_config))
13366                         return PTR_ERR(pipe_config);
13367
13368                 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
13369
13370                 if (!pipe_config->base.active ||
13371                     needs_modeset(&pipe_config->base))
13372                         continue;
13373
13374                 /* 2 or more enabled crtcs means no need for w/a */
13375                 if (enabled_pipe != INVALID_PIPE)
13376                         return 0;
13377
13378                 enabled_pipe = intel_crtc->pipe;
13379         }
13380
13381         if (enabled_pipe != INVALID_PIPE)
13382                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13383         else if (other_crtc_state)
13384                 other_crtc_state->hsw_workaround_pipe = first_pipe;
13385
13386         return 0;
13387 }
13388
13389 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
13390 {
13391         struct drm_crtc *crtc;
13392         struct drm_crtc_state *crtc_state;
13393         int ret = 0;
13394
13395         /* add all active pipes to the state */
13396         for_each_crtc(state->dev, crtc) {
13397                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13398                 if (IS_ERR(crtc_state))
13399                         return PTR_ERR(crtc_state);
13400
13401                 if (!crtc_state->active || needs_modeset(crtc_state))
13402                         continue;
13403
13404                 crtc_state->mode_changed = true;
13405
13406                 ret = drm_atomic_add_affected_connectors(state, crtc);
13407                 if (ret)
13408                         break;
13409
13410                 ret = drm_atomic_add_affected_planes(state, crtc);
13411                 if (ret)
13412                         break;
13413         }
13414
13415         return ret;
13416 }
13417
13418 static int intel_modeset_checks(struct drm_atomic_state *state)
13419 {
13420         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13421         struct drm_i915_private *dev_priv = state->dev->dev_private;
13422         struct drm_crtc *crtc;
13423         struct drm_crtc_state *crtc_state;
13424         int ret = 0, i;
13425
13426         if (!check_digital_port_conflicts(state)) {
13427                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13428                 return -EINVAL;
13429         }
13430
13431         intel_state->modeset = true;
13432         intel_state->active_crtcs = dev_priv->active_crtcs;
13433
13434         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13435                 if (crtc_state->active)
13436                         intel_state->active_crtcs |= 1 << i;
13437                 else
13438                         intel_state->active_crtcs &= ~(1 << i);
13439
13440                 if (crtc_state->active != crtc->state->active)
13441                         intel_state->active_pipe_changes |= drm_crtc_mask(crtc);
13442         }
13443
13444         /*
13445          * See if the config requires any additional preparation, e.g.
13446          * to adjust global state with pipes off.  We need to do this
13447          * here so we can get the modeset_pipe updated config for the new
13448          * mode set on this crtc.  For other crtcs we need to use the
13449          * adjusted_mode bits in the crtc directly.
13450          */
13451         if (dev_priv->display.modeset_calc_cdclk) {
13452                 if (!intel_state->cdclk_pll_vco)
13453                         intel_state->cdclk_pll_vco = dev_priv->cdclk_pll.vco;
13454                 if (!intel_state->cdclk_pll_vco)
13455                         intel_state->cdclk_pll_vco = dev_priv->skl_preferred_vco_freq;
13456
13457                 ret = dev_priv->display.modeset_calc_cdclk(state);
13458                 if (ret < 0)
13459                         return ret;
13460
13461                 if (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
13462                     intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco)
13463                         ret = intel_modeset_all_pipes(state);
13464
13465                 if (ret < 0)
13466                         return ret;
13467
13468                 DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n",
13469                               intel_state->cdclk, intel_state->dev_cdclk);
13470         } else
13471                 to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq;
13472
13473         intel_modeset_clear_plls(state);
13474
13475         if (IS_HASWELL(dev_priv))
13476                 return haswell_mode_set_planes_workaround(state);
13477
13478         return 0;
13479 }
13480
13481 /*
13482  * Handle calculation of various watermark data at the end of the atomic check
13483  * phase.  The code here should be run after the per-crtc and per-plane 'check'
13484  * handlers to ensure that all derived state has been updated.
13485  */
13486 static int calc_watermark_data(struct drm_atomic_state *state)
13487 {
13488         struct drm_device *dev = state->dev;
13489         struct drm_i915_private *dev_priv = to_i915(dev);
13490
13491         /* Is there platform-specific watermark information to calculate? */
13492         if (dev_priv->display.compute_global_watermarks)
13493                 return dev_priv->display.compute_global_watermarks(state);
13494
13495         return 0;
13496 }
13497
13498 /**
13499  * intel_atomic_check - validate state object
13500  * @dev: drm device
13501  * @state: state to validate
13502  */
13503 static int intel_atomic_check(struct drm_device *dev,
13504                               struct drm_atomic_state *state)
13505 {
13506         struct drm_i915_private *dev_priv = to_i915(dev);
13507         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13508         struct drm_crtc *crtc;
13509         struct drm_crtc_state *crtc_state;
13510         int ret, i;
13511         bool any_ms = false;
13512
13513         ret = drm_atomic_helper_check_modeset(dev, state);
13514         if (ret)
13515                 return ret;
13516
13517         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13518                 struct intel_crtc_state *pipe_config =
13519                         to_intel_crtc_state(crtc_state);
13520
13521                 /* Catch I915_MODE_FLAG_INHERITED */
13522                 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13523                         crtc_state->mode_changed = true;
13524
13525                 if (!needs_modeset(crtc_state))
13526                         continue;
13527
13528                 if (!crtc_state->enable) {
13529                         any_ms = true;
13530                         continue;
13531                 }
13532
13533                 /* FIXME: For only active_changed we shouldn't need to do any
13534                  * state recomputation at all. */
13535
13536                 ret = drm_atomic_add_affected_connectors(state, crtc);
13537                 if (ret)
13538                         return ret;
13539
13540                 ret = intel_modeset_pipe_config(crtc, pipe_config);
13541                 if (ret) {
13542                         intel_dump_pipe_config(to_intel_crtc(crtc),
13543                                                pipe_config, "[failed]");
13544                         return ret;
13545                 }
13546
13547                 if (i915.fastboot &&
13548                     intel_pipe_config_compare(dev,
13549                                         to_intel_crtc_state(crtc->state),
13550                                         pipe_config, true)) {
13551                         crtc_state->mode_changed = false;
13552                         to_intel_crtc_state(crtc_state)->update_pipe = true;
13553                 }
13554
13555                 if (needs_modeset(crtc_state))
13556                         any_ms = true;
13557
13558                 ret = drm_atomic_add_affected_planes(state, crtc);
13559                 if (ret)
13560                         return ret;
13561
13562                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13563                                        needs_modeset(crtc_state) ?
13564                                        "[modeset]" : "[fastset]");
13565         }
13566
13567         if (any_ms) {
13568                 ret = intel_modeset_checks(state);
13569
13570                 if (ret)
13571                         return ret;
13572         } else
13573                 intel_state->cdclk = dev_priv->cdclk_freq;
13574
13575         ret = drm_atomic_helper_check_planes(dev, state);
13576         if (ret)
13577                 return ret;
13578
13579         intel_fbc_choose_crtc(dev_priv, state);
13580         return calc_watermark_data(state);
13581 }
13582
13583 static int intel_atomic_prepare_commit(struct drm_device *dev,
13584                                        struct drm_atomic_state *state,
13585                                        bool nonblock)
13586 {
13587         struct drm_i915_private *dev_priv = dev->dev_private;
13588         struct drm_plane_state *plane_state;
13589         struct drm_crtc_state *crtc_state;
13590         struct drm_plane *plane;
13591         struct drm_crtc *crtc;
13592         int i, ret;
13593
13594         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13595                 if (state->legacy_cursor_update)
13596                         continue;
13597
13598                 ret = intel_crtc_wait_for_pending_flips(crtc);
13599                 if (ret)
13600                         return ret;
13601
13602                 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
13603                         flush_workqueue(dev_priv->wq);
13604         }
13605
13606         ret = mutex_lock_interruptible(&dev->struct_mutex);
13607         if (ret)
13608                 return ret;
13609
13610         ret = drm_atomic_helper_prepare_planes(dev, state);
13611         mutex_unlock(&dev->struct_mutex);
13612
13613         if (!ret && !nonblock) {
13614                 for_each_plane_in_state(state, plane, plane_state, i) {
13615                         struct intel_plane_state *intel_plane_state =
13616                                 to_intel_plane_state(plane_state);
13617
13618                         if (!intel_plane_state->wait_req)
13619                                 continue;
13620
13621                         ret = __i915_wait_request(intel_plane_state->wait_req,
13622                                                   true, NULL, NULL);
13623                         if (ret) {
13624                                 /* Any hang should be swallowed by the wait */
13625                                 WARN_ON(ret == -EIO);
13626                                 mutex_lock(&dev->struct_mutex);
13627                                 drm_atomic_helper_cleanup_planes(dev, state);
13628                                 mutex_unlock(&dev->struct_mutex);
13629                                 break;
13630                         }
13631                 }
13632         }
13633
13634         return ret;
13635 }
13636
13637 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
13638 {
13639         struct drm_device *dev = crtc->base.dev;
13640
13641         if (!dev->max_vblank_count)
13642                 return drm_accurate_vblank_count(&crtc->base);
13643
13644         return dev->driver->get_vblank_counter(dev, crtc->pipe);
13645 }
13646
13647 static void intel_atomic_wait_for_vblanks(struct drm_device *dev,
13648                                           struct drm_i915_private *dev_priv,
13649                                           unsigned crtc_mask)
13650 {
13651         unsigned last_vblank_count[I915_MAX_PIPES];
13652         enum pipe pipe;
13653         int ret;
13654
13655         if (!crtc_mask)
13656                 return;
13657
13658         for_each_pipe(dev_priv, pipe) {
13659                 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
13660
13661                 if (!((1 << pipe) & crtc_mask))
13662                         continue;
13663
13664                 ret = drm_crtc_vblank_get(crtc);
13665                 if (WARN_ON(ret != 0)) {
13666                         crtc_mask &= ~(1 << pipe);
13667                         continue;
13668                 }
13669
13670                 last_vblank_count[pipe] = drm_crtc_vblank_count(crtc);
13671         }
13672
13673         for_each_pipe(dev_priv, pipe) {
13674                 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
13675                 long lret;
13676
13677                 if (!((1 << pipe) & crtc_mask))
13678                         continue;
13679
13680                 lret = wait_event_timeout(dev->vblank[pipe].queue,
13681                                 last_vblank_count[pipe] !=
13682                                         drm_crtc_vblank_count(crtc),
13683                                 msecs_to_jiffies(50));
13684
13685                 WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe));
13686
13687                 drm_crtc_vblank_put(crtc);
13688         }
13689 }
13690
13691 static bool needs_vblank_wait(struct intel_crtc_state *crtc_state)
13692 {
13693         /* fb updated, need to unpin old fb */
13694         if (crtc_state->fb_changed)
13695                 return true;
13696
13697         /* wm changes, need vblank before final wm's */
13698         if (crtc_state->update_wm_post)
13699                 return true;
13700
13701         /*
13702          * cxsr is re-enabled after vblank.
13703          * This is already handled by crtc_state->update_wm_post,
13704          * but added for clarity.
13705          */
13706         if (crtc_state->disable_cxsr)
13707                 return true;
13708
13709         return false;
13710 }
13711
13712 static void intel_atomic_commit_tail(struct drm_atomic_state *state)
13713 {
13714         struct drm_device *dev = state->dev;
13715         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13716         struct drm_i915_private *dev_priv = dev->dev_private;
13717         struct drm_crtc_state *old_crtc_state;
13718         struct drm_crtc *crtc;
13719         struct intel_crtc_state *intel_cstate;
13720         struct drm_plane *plane;
13721         struct drm_plane_state *plane_state;
13722         bool hw_check = intel_state->modeset;
13723         unsigned long put_domains[I915_MAX_PIPES] = {};
13724         unsigned crtc_vblank_mask = 0;
13725         int i, ret;
13726
13727         for_each_plane_in_state(state, plane, plane_state, i) {
13728                 struct intel_plane_state *intel_plane_state =
13729                         to_intel_plane_state(plane_state);
13730
13731                 if (!intel_plane_state->wait_req)
13732                         continue;
13733
13734                 ret = __i915_wait_request(intel_plane_state->wait_req,
13735                                           true, NULL, NULL);
13736                 /* EIO should be eaten, and we can't get interrupted in the
13737                  * worker, and blocking commits have waited already. */
13738                 WARN_ON(ret);
13739         }
13740
13741         drm_atomic_helper_wait_for_dependencies(state);
13742
13743         if (intel_state->modeset) {
13744                 memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
13745                        sizeof(intel_state->min_pixclk));
13746                 dev_priv->active_crtcs = intel_state->active_crtcs;
13747                 dev_priv->atomic_cdclk_freq = intel_state->cdclk;
13748
13749                 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
13750         }
13751
13752         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13753                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13754
13755                 if (needs_modeset(crtc->state) ||
13756                     to_intel_crtc_state(crtc->state)->update_pipe) {
13757                         hw_check = true;
13758
13759                         put_domains[to_intel_crtc(crtc)->pipe] =
13760                                 modeset_get_crtc_power_domains(crtc,
13761                                         to_intel_crtc_state(crtc->state));
13762                 }
13763
13764                 if (!needs_modeset(crtc->state))
13765                         continue;
13766
13767                 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
13768
13769                 if (old_crtc_state->active) {
13770                         intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
13771                         dev_priv->display.crtc_disable(crtc);
13772                         intel_crtc->active = false;
13773                         intel_fbc_disable(intel_crtc);
13774                         intel_disable_shared_dpll(intel_crtc);
13775
13776                         /*
13777                          * Underruns don't always raise
13778                          * interrupts, so check manually.
13779                          */
13780                         intel_check_cpu_fifo_underruns(dev_priv);
13781                         intel_check_pch_fifo_underruns(dev_priv);
13782
13783                         if (!crtc->state->active)
13784                                 intel_update_watermarks(crtc);
13785                 }
13786         }
13787
13788         /* Only after disabling all output pipelines that will be changed can we
13789          * update the the output configuration. */
13790         intel_modeset_update_crtc_state(state);
13791
13792         if (intel_state->modeset) {
13793                 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
13794
13795                 if (dev_priv->display.modeset_commit_cdclk &&
13796                     (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
13797                      intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco))
13798                         dev_priv->display.modeset_commit_cdclk(state);
13799
13800                 intel_modeset_verify_disabled(dev);
13801         }
13802
13803         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13804         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13805                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13806                 bool modeset = needs_modeset(crtc->state);
13807                 struct intel_crtc_state *pipe_config =
13808                         to_intel_crtc_state(crtc->state);
13809
13810                 if (modeset && crtc->state->active) {
13811                         update_scanline_offset(to_intel_crtc(crtc));
13812                         dev_priv->display.crtc_enable(crtc);
13813                 }
13814
13815                 /* Complete events for now disable pipes here. */
13816                 if (modeset && !crtc->state->active && crtc->state->event) {
13817                         spin_lock_irq(&dev->event_lock);
13818                         drm_crtc_send_vblank_event(crtc, crtc->state->event);
13819                         spin_unlock_irq(&dev->event_lock);
13820
13821                         crtc->state->event = NULL;
13822                 }
13823
13824                 if (!modeset)
13825                         intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
13826
13827                 if (crtc->state->active &&
13828                     drm_atomic_get_existing_plane_state(state, crtc->primary))
13829                         intel_fbc_enable(intel_crtc, pipe_config, to_intel_plane_state(crtc->primary->state));
13830
13831                 if (crtc->state->active)
13832                         drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
13833
13834                 if (pipe_config->base.active && needs_vblank_wait(pipe_config))
13835                         crtc_vblank_mask |= 1 << i;
13836         }
13837
13838         /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
13839          * already, but still need the state for the delayed optimization. To
13840          * fix this:
13841          * - wrap the optimization/post_plane_update stuff into a per-crtc work.
13842          * - schedule that vblank worker _before_ calling hw_done
13843          * - at the start of commit_tail, cancel it _synchrously
13844          * - switch over to the vblank wait helper in the core after that since
13845          *   we don't need out special handling any more.
13846          */
13847         if (!state->legacy_cursor_update)
13848                 intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask);
13849
13850         /*
13851          * Now that the vblank has passed, we can go ahead and program the
13852          * optimal watermarks on platforms that need two-step watermark
13853          * programming.
13854          *
13855          * TODO: Move this (and other cleanup) to an async worker eventually.
13856          */
13857         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13858                 intel_cstate = to_intel_crtc_state(crtc->state);
13859
13860                 if (dev_priv->display.optimize_watermarks)
13861                         dev_priv->display.optimize_watermarks(intel_cstate);
13862         }
13863
13864         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13865                 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
13866
13867                 if (put_domains[i])
13868                         modeset_put_power_domains(dev_priv, put_domains[i]);
13869
13870                 intel_modeset_verify_crtc(crtc, old_crtc_state, crtc->state);
13871         }
13872
13873         drm_atomic_helper_commit_hw_done(state);
13874
13875         if (intel_state->modeset)
13876                 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
13877
13878         mutex_lock(&dev->struct_mutex);
13879         drm_atomic_helper_cleanup_planes(dev, state);
13880         mutex_unlock(&dev->struct_mutex);
13881
13882         drm_atomic_helper_commit_cleanup_done(state);
13883
13884         drm_atomic_state_free(state);
13885
13886         /* As one of the primary mmio accessors, KMS has a high likelihood
13887          * of triggering bugs in unclaimed access. After we finish
13888          * modesetting, see if an error has been flagged, and if so
13889          * enable debugging for the next modeset - and hope we catch
13890          * the culprit.
13891          *
13892          * XXX note that we assume display power is on at this point.
13893          * This might hold true now but we need to add pm helper to check
13894          * unclaimed only when the hardware is on, as atomic commits
13895          * can happen also when the device is completely off.
13896          */
13897         intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
13898 }
13899
13900 static void intel_atomic_commit_work(struct work_struct *work)
13901 {
13902         struct drm_atomic_state *state = container_of(work,
13903                                                       struct drm_atomic_state,
13904                                                       commit_work);
13905         intel_atomic_commit_tail(state);
13906 }
13907
13908 static void intel_atomic_track_fbs(struct drm_atomic_state *state)
13909 {
13910         struct drm_plane_state *old_plane_state;
13911         struct drm_plane *plane;
13912         struct drm_i915_gem_object *obj, *old_obj;
13913         struct intel_plane *intel_plane;
13914         int i;
13915
13916         mutex_lock(&state->dev->struct_mutex);
13917         for_each_plane_in_state(state, plane, old_plane_state, i) {
13918                 obj = intel_fb_obj(plane->state->fb);
13919                 old_obj = intel_fb_obj(old_plane_state->fb);
13920                 intel_plane = to_intel_plane(plane);
13921
13922                 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13923         }
13924         mutex_unlock(&state->dev->struct_mutex);
13925 }
13926
13927 /**
13928  * intel_atomic_commit - commit validated state object
13929  * @dev: DRM device
13930  * @state: the top-level driver state object
13931  * @nonblock: nonblocking commit
13932  *
13933  * This function commits a top-level state object that has been validated
13934  * with drm_atomic_helper_check().
13935  *
13936  * FIXME:  Atomic modeset support for i915 is not yet complete.  At the moment
13937  * nonblocking commits are only safe for pure plane updates. Everything else
13938  * should work though.
13939  *
13940  * RETURNS
13941  * Zero for success or -errno.
13942  */
13943 static int intel_atomic_commit(struct drm_device *dev,
13944                                struct drm_atomic_state *state,
13945                                bool nonblock)
13946 {
13947         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13948         struct drm_i915_private *dev_priv = dev->dev_private;
13949         int ret = 0;
13950
13951         if (intel_state->modeset && nonblock) {
13952                 DRM_DEBUG_KMS("nonblocking commit for modeset not yet implemented.\n");
13953                 return -EINVAL;
13954         }
13955
13956         ret = drm_atomic_helper_setup_commit(state, nonblock);
13957         if (ret)
13958                 return ret;
13959
13960         INIT_WORK(&state->commit_work, intel_atomic_commit_work);
13961
13962         ret = intel_atomic_prepare_commit(dev, state, nonblock);
13963         if (ret) {
13964                 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
13965                 return ret;
13966         }
13967
13968         drm_atomic_helper_swap_state(state, true);
13969         dev_priv->wm.distrust_bios_wm = false;
13970         dev_priv->wm.skl_results = intel_state->wm_results;
13971         intel_shared_dpll_commit(state);
13972         intel_atomic_track_fbs(state);
13973
13974         if (nonblock)
13975                 queue_work(system_unbound_wq, &state->commit_work);
13976         else
13977                 intel_atomic_commit_tail(state);
13978
13979         return 0;
13980 }
13981
13982 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13983 {
13984         struct drm_device *dev = crtc->dev;
13985         struct drm_atomic_state *state;
13986         struct drm_crtc_state *crtc_state;
13987         int ret;
13988
13989         state = drm_atomic_state_alloc(dev);
13990         if (!state) {
13991                 DRM_DEBUG_KMS("[CRTC:%d:%s] crtc restore failed, out of memory",
13992                               crtc->base.id, crtc->name);
13993                 return;
13994         }
13995
13996         state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
13997
13998 retry:
13999         crtc_state = drm_atomic_get_crtc_state(state, crtc);
14000         ret = PTR_ERR_OR_ZERO(crtc_state);
14001         if (!ret) {
14002                 if (!crtc_state->active)
14003                         goto out;
14004
14005                 crtc_state->mode_changed = true;
14006                 ret = drm_atomic_commit(state);
14007         }
14008
14009         if (ret == -EDEADLK) {
14010                 drm_atomic_state_clear(state);
14011                 drm_modeset_backoff(state->acquire_ctx);
14012                 goto retry;
14013         }
14014
14015         if (ret)
14016 out:
14017                 drm_atomic_state_free(state);
14018 }
14019
14020 #undef for_each_intel_crtc_masked
14021
14022 static const struct drm_crtc_funcs intel_crtc_funcs = {
14023         .gamma_set = drm_atomic_helper_legacy_gamma_set,
14024         .set_config = drm_atomic_helper_set_config,
14025         .set_property = drm_atomic_helper_crtc_set_property,
14026         .destroy = intel_crtc_destroy,
14027         .page_flip = intel_crtc_page_flip,
14028         .atomic_duplicate_state = intel_crtc_duplicate_state,
14029         .atomic_destroy_state = intel_crtc_destroy_state,
14030 };
14031
14032 /**
14033  * intel_prepare_plane_fb - Prepare fb for usage on plane
14034  * @plane: drm plane to prepare for
14035  * @fb: framebuffer to prepare for presentation
14036  *
14037  * Prepares a framebuffer for usage on a display plane.  Generally this
14038  * involves pinning the underlying object and updating the frontbuffer tracking
14039  * bits.  Some older platforms need special physical address handling for
14040  * cursor planes.
14041  *
14042  * Must be called with struct_mutex held.
14043  *
14044  * Returns 0 on success, negative error code on failure.
14045  */
14046 int
14047 intel_prepare_plane_fb(struct drm_plane *plane,
14048                        const struct drm_plane_state *new_state)
14049 {
14050         struct drm_device *dev = plane->dev;
14051         struct drm_framebuffer *fb = new_state->fb;
14052         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14053         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
14054         struct reservation_object *resv;
14055         int ret = 0;
14056
14057         if (!obj && !old_obj)
14058                 return 0;
14059
14060         if (old_obj) {
14061                 struct drm_crtc_state *crtc_state =
14062                         drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc);
14063
14064                 /* Big Hammer, we also need to ensure that any pending
14065                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
14066                  * current scanout is retired before unpinning the old
14067                  * framebuffer. Note that we rely on userspace rendering
14068                  * into the buffer attached to the pipe they are waiting
14069                  * on. If not, userspace generates a GPU hang with IPEHR
14070                  * point to the MI_WAIT_FOR_EVENT.
14071                  *
14072                  * This should only fail upon a hung GPU, in which case we
14073                  * can safely continue.
14074                  */
14075                 if (needs_modeset(crtc_state))
14076                         ret = i915_gem_object_wait_rendering(old_obj, true);
14077                 if (ret) {
14078                         /* GPU hangs should have been swallowed by the wait */
14079                         WARN_ON(ret == -EIO);
14080                         return ret;
14081                 }
14082         }
14083
14084         if (!obj)
14085                 return 0;
14086
14087         /* For framebuffer backed by dmabuf, wait for fence */
14088         resv = i915_gem_object_get_dmabuf_resv(obj);
14089         if (resv) {
14090                 long lret;
14091
14092                 lret = reservation_object_wait_timeout_rcu(resv, false, true,
14093                                                            MAX_SCHEDULE_TIMEOUT);
14094                 if (lret == -ERESTARTSYS)
14095                         return lret;
14096
14097                 WARN(lret < 0, "waiting returns %li\n", lret);
14098         }
14099
14100         if (plane->type == DRM_PLANE_TYPE_CURSOR &&
14101             INTEL_INFO(dev)->cursor_needs_physical) {
14102                 int align = IS_I830(dev) ? 16 * 1024 : 256;
14103                 ret = i915_gem_object_attach_phys(obj, align);
14104                 if (ret)
14105                         DRM_DEBUG_KMS("failed to attach phys object\n");
14106         } else {
14107                 ret = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
14108         }
14109
14110         if (ret == 0) {
14111                 struct intel_plane_state *plane_state =
14112                         to_intel_plane_state(new_state);
14113
14114                 i915_gem_request_assign(&plane_state->wait_req,
14115                                         obj->last_write_req);
14116         }
14117
14118         return ret;
14119 }
14120
14121 /**
14122  * intel_cleanup_plane_fb - Cleans up an fb after plane use
14123  * @plane: drm plane to clean up for
14124  * @fb: old framebuffer that was on plane
14125  *
14126  * Cleans up a framebuffer that has just been removed from a plane.
14127  *
14128  * Must be called with struct_mutex held.
14129  */
14130 void
14131 intel_cleanup_plane_fb(struct drm_plane *plane,
14132                        const struct drm_plane_state *old_state)
14133 {
14134         struct drm_device *dev = plane->dev;
14135         struct intel_plane_state *old_intel_state;
14136         struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
14137         struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
14138
14139         old_intel_state = to_intel_plane_state(old_state);
14140
14141         if (!obj && !old_obj)
14142                 return;
14143
14144         if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
14145             !INTEL_INFO(dev)->cursor_needs_physical))
14146                 intel_unpin_fb_obj(old_state->fb, old_state->rotation);
14147
14148         i915_gem_request_assign(&old_intel_state->wait_req, NULL);
14149 }
14150
14151 int
14152 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
14153 {
14154         int max_scale;
14155         struct drm_device *dev;
14156         struct drm_i915_private *dev_priv;
14157         int crtc_clock, cdclk;
14158
14159         if (!intel_crtc || !crtc_state->base.enable)
14160                 return DRM_PLANE_HELPER_NO_SCALING;
14161
14162         dev = intel_crtc->base.dev;
14163         dev_priv = dev->dev_private;
14164         crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
14165         cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
14166
14167         if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock))
14168                 return DRM_PLANE_HELPER_NO_SCALING;
14169
14170         /*
14171          * skl max scale is lower of:
14172          *    close to 3 but not 3, -1 is for that purpose
14173          *            or
14174          *    cdclk/crtc_clock
14175          */
14176         max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
14177
14178         return max_scale;
14179 }
14180
14181 static int
14182 intel_check_primary_plane(struct drm_plane *plane,
14183                           struct intel_crtc_state *crtc_state,
14184                           struct intel_plane_state *state)
14185 {
14186         struct drm_crtc *crtc = state->base.crtc;
14187         struct drm_framebuffer *fb = state->base.fb;
14188         int min_scale = DRM_PLANE_HELPER_NO_SCALING;
14189         int max_scale = DRM_PLANE_HELPER_NO_SCALING;
14190         bool can_position = false;
14191
14192         if (INTEL_INFO(plane->dev)->gen >= 9) {
14193                 /* use scaler when colorkey is not required */
14194                 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
14195                         min_scale = 1;
14196                         max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
14197                 }
14198                 can_position = true;
14199         }
14200
14201         return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
14202                                              &state->dst, &state->clip,
14203                                              state->base.rotation,
14204                                              min_scale, max_scale,
14205                                              can_position, true,
14206                                              &state->visible);
14207 }
14208
14209 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
14210                                     struct drm_crtc_state *old_crtc_state)
14211 {
14212         struct drm_device *dev = crtc->dev;
14213         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14214         struct intel_crtc_state *old_intel_state =
14215                 to_intel_crtc_state(old_crtc_state);
14216         bool modeset = needs_modeset(crtc->state);
14217
14218         /* Perform vblank evasion around commit operation */
14219         intel_pipe_update_start(intel_crtc);
14220
14221         if (modeset)
14222                 return;
14223
14224         if (crtc->state->color_mgmt_changed || to_intel_crtc_state(crtc->state)->update_pipe) {
14225                 intel_color_set_csc(crtc->state);
14226                 intel_color_load_luts(crtc->state);
14227         }
14228
14229         if (to_intel_crtc_state(crtc->state)->update_pipe)
14230                 intel_update_pipe_config(intel_crtc, old_intel_state);
14231         else if (INTEL_INFO(dev)->gen >= 9)
14232                 skl_detach_scalers(intel_crtc);
14233 }
14234
14235 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
14236                                      struct drm_crtc_state *old_crtc_state)
14237 {
14238         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14239
14240         intel_pipe_update_end(intel_crtc, NULL);
14241 }
14242
14243 /**
14244  * intel_plane_destroy - destroy a plane
14245  * @plane: plane to destroy
14246  *
14247  * Common destruction function for all types of planes (primary, cursor,
14248  * sprite).
14249  */
14250 void intel_plane_destroy(struct drm_plane *plane)
14251 {
14252         if (!plane)
14253                 return;
14254
14255         drm_plane_cleanup(plane);
14256         kfree(to_intel_plane(plane));
14257 }
14258
14259 const struct drm_plane_funcs intel_plane_funcs = {
14260         .update_plane = drm_atomic_helper_update_plane,
14261         .disable_plane = drm_atomic_helper_disable_plane,
14262         .destroy = intel_plane_destroy,
14263         .set_property = drm_atomic_helper_plane_set_property,
14264         .atomic_get_property = intel_plane_atomic_get_property,
14265         .atomic_set_property = intel_plane_atomic_set_property,
14266         .atomic_duplicate_state = intel_plane_duplicate_state,
14267         .atomic_destroy_state = intel_plane_destroy_state,
14268
14269 };
14270
14271 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
14272                                                     int pipe)
14273 {
14274         struct intel_plane *primary = NULL;
14275         struct intel_plane_state *state = NULL;
14276         const uint32_t *intel_primary_formats;
14277         unsigned int num_formats;
14278         int ret;
14279
14280         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
14281         if (!primary)
14282                 goto fail;
14283
14284         state = intel_create_plane_state(&primary->base);
14285         if (!state)
14286                 goto fail;
14287         primary->base.state = &state->base;
14288
14289         primary->can_scale = false;
14290         primary->max_downscale = 1;
14291         if (INTEL_INFO(dev)->gen >= 9) {
14292                 primary->can_scale = true;
14293                 state->scaler_id = -1;
14294         }
14295         primary->pipe = pipe;
14296         primary->plane = pipe;
14297         primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
14298         primary->check_plane = intel_check_primary_plane;
14299         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
14300                 primary->plane = !pipe;
14301
14302         if (INTEL_INFO(dev)->gen >= 9) {
14303                 intel_primary_formats = skl_primary_formats;
14304                 num_formats = ARRAY_SIZE(skl_primary_formats);
14305
14306                 primary->update_plane = skylake_update_primary_plane;
14307                 primary->disable_plane = skylake_disable_primary_plane;
14308         } else if (HAS_PCH_SPLIT(dev)) {
14309                 intel_primary_formats = i965_primary_formats;
14310                 num_formats = ARRAY_SIZE(i965_primary_formats);
14311
14312                 primary->update_plane = ironlake_update_primary_plane;
14313                 primary->disable_plane = i9xx_disable_primary_plane;
14314         } else if (INTEL_INFO(dev)->gen >= 4) {
14315                 intel_primary_formats = i965_primary_formats;
14316                 num_formats = ARRAY_SIZE(i965_primary_formats);
14317
14318                 primary->update_plane = i9xx_update_primary_plane;
14319                 primary->disable_plane = i9xx_disable_primary_plane;
14320         } else {
14321                 intel_primary_formats = i8xx_primary_formats;
14322                 num_formats = ARRAY_SIZE(i8xx_primary_formats);
14323
14324                 primary->update_plane = i9xx_update_primary_plane;
14325                 primary->disable_plane = i9xx_disable_primary_plane;
14326         }
14327
14328         if (INTEL_INFO(dev)->gen >= 9)
14329                 ret = drm_universal_plane_init(dev, &primary->base, 0,
14330                                                &intel_plane_funcs,
14331                                                intel_primary_formats, num_formats,
14332                                                DRM_PLANE_TYPE_PRIMARY,
14333                                                "plane 1%c", pipe_name(pipe));
14334         else if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
14335                 ret = drm_universal_plane_init(dev, &primary->base, 0,
14336                                                &intel_plane_funcs,
14337                                                intel_primary_formats, num_formats,
14338                                                DRM_PLANE_TYPE_PRIMARY,
14339                                                "primary %c", pipe_name(pipe));
14340         else
14341                 ret = drm_universal_plane_init(dev, &primary->base, 0,
14342                                                &intel_plane_funcs,
14343                                                intel_primary_formats, num_formats,
14344                                                DRM_PLANE_TYPE_PRIMARY,
14345                                                "plane %c", plane_name(primary->plane));
14346         if (ret)
14347                 goto fail;
14348
14349         if (INTEL_INFO(dev)->gen >= 4)
14350                 intel_create_rotation_property(dev, primary);
14351
14352         drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
14353
14354         return &primary->base;
14355
14356 fail:
14357         kfree(state);
14358         kfree(primary);
14359
14360         return NULL;
14361 }
14362
14363 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
14364 {
14365         if (!dev->mode_config.rotation_property) {
14366                 unsigned long flags = BIT(DRM_ROTATE_0) |
14367                         BIT(DRM_ROTATE_180);
14368
14369                 if (INTEL_INFO(dev)->gen >= 9)
14370                         flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
14371
14372                 dev->mode_config.rotation_property =
14373                         drm_mode_create_rotation_property(dev, flags);
14374         }
14375         if (dev->mode_config.rotation_property)
14376                 drm_object_attach_property(&plane->base.base,
14377                                 dev->mode_config.rotation_property,
14378                                 plane->base.state->rotation);
14379 }
14380
14381 static int
14382 intel_check_cursor_plane(struct drm_plane *plane,
14383                          struct intel_crtc_state *crtc_state,
14384                          struct intel_plane_state *state)
14385 {
14386         struct drm_crtc *crtc = crtc_state->base.crtc;
14387         struct drm_framebuffer *fb = state->base.fb;
14388         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14389         enum pipe pipe = to_intel_plane(plane)->pipe;
14390         unsigned stride;
14391         int ret;
14392
14393         ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
14394                                             &state->dst, &state->clip,
14395                                             state->base.rotation,
14396                                             DRM_PLANE_HELPER_NO_SCALING,
14397                                             DRM_PLANE_HELPER_NO_SCALING,
14398                                             true, true, &state->visible);
14399         if (ret)
14400                 return ret;
14401
14402         /* if we want to turn off the cursor ignore width and height */
14403         if (!obj)
14404                 return 0;
14405
14406         /* Check for which cursor types we support */
14407         if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
14408                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
14409                           state->base.crtc_w, state->base.crtc_h);
14410                 return -EINVAL;
14411         }
14412
14413         stride = roundup_pow_of_two(state->base.crtc_w) * 4;
14414         if (obj->base.size < stride * state->base.crtc_h) {
14415                 DRM_DEBUG_KMS("buffer is too small\n");
14416                 return -ENOMEM;
14417         }
14418
14419         if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
14420                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
14421                 return -EINVAL;
14422         }
14423
14424         /*
14425          * There's something wrong with the cursor on CHV pipe C.
14426          * If it straddles the left edge of the screen then
14427          * moving it away from the edge or disabling it often
14428          * results in a pipe underrun, and often that can lead to
14429          * dead pipe (constant underrun reported, and it scans
14430          * out just a solid color). To recover from that, the
14431          * display power well must be turned off and on again.
14432          * Refuse the put the cursor into that compromised position.
14433          */
14434         if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C &&
14435             state->visible && state->base.crtc_x < 0) {
14436                 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
14437                 return -EINVAL;
14438         }
14439
14440         return 0;
14441 }
14442
14443 static void
14444 intel_disable_cursor_plane(struct drm_plane *plane,
14445                            struct drm_crtc *crtc)
14446 {
14447         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14448
14449         intel_crtc->cursor_addr = 0;
14450         intel_crtc_update_cursor(crtc, NULL);
14451 }
14452
14453 static void
14454 intel_update_cursor_plane(struct drm_plane *plane,
14455                           const struct intel_crtc_state *crtc_state,
14456                           const struct intel_plane_state *state)
14457 {
14458         struct drm_crtc *crtc = crtc_state->base.crtc;
14459         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14460         struct drm_device *dev = plane->dev;
14461         struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
14462         uint32_t addr;
14463
14464         if (!obj)
14465                 addr = 0;
14466         else if (!INTEL_INFO(dev)->cursor_needs_physical)
14467                 addr = i915_gem_obj_ggtt_offset(obj);
14468         else
14469                 addr = obj->phys_handle->busaddr;
14470
14471         intel_crtc->cursor_addr = addr;
14472         intel_crtc_update_cursor(crtc, state);
14473 }
14474
14475 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
14476                                                    int pipe)
14477 {
14478         struct intel_plane *cursor = NULL;
14479         struct intel_plane_state *state = NULL;
14480         int ret;
14481
14482         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
14483         if (!cursor)
14484                 goto fail;
14485
14486         state = intel_create_plane_state(&cursor->base);
14487         if (!state)
14488                 goto fail;
14489         cursor->base.state = &state->base;
14490
14491         cursor->can_scale = false;
14492         cursor->max_downscale = 1;
14493         cursor->pipe = pipe;
14494         cursor->plane = pipe;
14495         cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
14496         cursor->check_plane = intel_check_cursor_plane;
14497         cursor->update_plane = intel_update_cursor_plane;
14498         cursor->disable_plane = intel_disable_cursor_plane;
14499
14500         ret = drm_universal_plane_init(dev, &cursor->base, 0,
14501                                        &intel_plane_funcs,
14502                                        intel_cursor_formats,
14503                                        ARRAY_SIZE(intel_cursor_formats),
14504                                        DRM_PLANE_TYPE_CURSOR,
14505                                        "cursor %c", pipe_name(pipe));
14506         if (ret)
14507                 goto fail;
14508
14509         if (INTEL_INFO(dev)->gen >= 4) {
14510                 if (!dev->mode_config.rotation_property)
14511                         dev->mode_config.rotation_property =
14512                                 drm_mode_create_rotation_property(dev,
14513                                                         BIT(DRM_ROTATE_0) |
14514                                                         BIT(DRM_ROTATE_180));
14515                 if (dev->mode_config.rotation_property)
14516                         drm_object_attach_property(&cursor->base.base,
14517                                 dev->mode_config.rotation_property,
14518                                 state->base.rotation);
14519         }
14520
14521         if (INTEL_INFO(dev)->gen >=9)
14522                 state->scaler_id = -1;
14523
14524         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
14525
14526         return &cursor->base;
14527
14528 fail:
14529         kfree(state);
14530         kfree(cursor);
14531
14532         return NULL;
14533 }
14534
14535 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
14536         struct intel_crtc_state *crtc_state)
14537 {
14538         int i;
14539         struct intel_scaler *intel_scaler;
14540         struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
14541
14542         for (i = 0; i < intel_crtc->num_scalers; i++) {
14543                 intel_scaler = &scaler_state->scalers[i];
14544                 intel_scaler->in_use = 0;
14545                 intel_scaler->mode = PS_SCALER_MODE_DYN;
14546         }
14547
14548         scaler_state->scaler_id = -1;
14549 }
14550
14551 static void intel_crtc_init(struct drm_device *dev, int pipe)
14552 {
14553         struct drm_i915_private *dev_priv = dev->dev_private;
14554         struct intel_crtc *intel_crtc;
14555         struct intel_crtc_state *crtc_state = NULL;
14556         struct drm_plane *primary = NULL;
14557         struct drm_plane *cursor = NULL;
14558         int ret;
14559
14560         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
14561         if (intel_crtc == NULL)
14562                 return;
14563
14564         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
14565         if (!crtc_state)
14566                 goto fail;
14567         intel_crtc->config = crtc_state;
14568         intel_crtc->base.state = &crtc_state->base;
14569         crtc_state->base.crtc = &intel_crtc->base;
14570
14571         /* initialize shared scalers */
14572         if (INTEL_INFO(dev)->gen >= 9) {
14573                 if (pipe == PIPE_C)
14574                         intel_crtc->num_scalers = 1;
14575                 else
14576                         intel_crtc->num_scalers = SKL_NUM_SCALERS;
14577
14578                 skl_init_scalers(dev, intel_crtc, crtc_state);
14579         }
14580
14581         primary = intel_primary_plane_create(dev, pipe);
14582         if (!primary)
14583                 goto fail;
14584
14585         cursor = intel_cursor_plane_create(dev, pipe);
14586         if (!cursor)
14587                 goto fail;
14588
14589         ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
14590                                         cursor, &intel_crtc_funcs,
14591                                         "pipe %c", pipe_name(pipe));
14592         if (ret)
14593                 goto fail;
14594
14595         /*
14596          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
14597          * is hooked to pipe B. Hence we want plane A feeding pipe B.
14598          */
14599         intel_crtc->pipe = pipe;
14600         intel_crtc->plane = pipe;
14601         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
14602                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
14603                 intel_crtc->plane = !pipe;
14604         }
14605
14606         intel_crtc->cursor_base = ~0;
14607         intel_crtc->cursor_cntl = ~0;
14608         intel_crtc->cursor_size = ~0;
14609
14610         intel_crtc->wm.cxsr_allowed = true;
14611
14612         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14613                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
14614         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
14615         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
14616
14617         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
14618
14619         intel_color_init(&intel_crtc->base);
14620
14621         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
14622         return;
14623
14624 fail:
14625         intel_plane_destroy(primary);
14626         intel_plane_destroy(cursor);
14627         kfree(crtc_state);
14628         kfree(intel_crtc);
14629 }
14630
14631 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14632 {
14633         struct drm_encoder *encoder = connector->base.encoder;
14634         struct drm_device *dev = connector->base.dev;
14635
14636         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
14637
14638         if (!encoder || WARN_ON(!encoder->crtc))
14639                 return INVALID_PIPE;
14640
14641         return to_intel_crtc(encoder->crtc)->pipe;
14642 }
14643
14644 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
14645                                 struct drm_file *file)
14646 {
14647         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
14648         struct drm_crtc *drmmode_crtc;
14649         struct intel_crtc *crtc;
14650
14651         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
14652         if (!drmmode_crtc)
14653                 return -ENOENT;
14654
14655         crtc = to_intel_crtc(drmmode_crtc);
14656         pipe_from_crtc_id->pipe = crtc->pipe;
14657
14658         return 0;
14659 }
14660
14661 static int intel_encoder_clones(struct intel_encoder *encoder)
14662 {
14663         struct drm_device *dev = encoder->base.dev;
14664         struct intel_encoder *source_encoder;
14665         int index_mask = 0;
14666         int entry = 0;
14667
14668         for_each_intel_encoder(dev, source_encoder) {
14669                 if (encoders_cloneable(encoder, source_encoder))
14670                         index_mask |= (1 << entry);
14671
14672                 entry++;
14673         }
14674
14675         return index_mask;
14676 }
14677
14678 static bool has_edp_a(struct drm_device *dev)
14679 {
14680         struct drm_i915_private *dev_priv = dev->dev_private;
14681
14682         if (!IS_MOBILE(dev))
14683                 return false;
14684
14685         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14686                 return false;
14687
14688         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14689                 return false;
14690
14691         return true;
14692 }
14693
14694 static bool intel_crt_present(struct drm_device *dev)
14695 {
14696         struct drm_i915_private *dev_priv = dev->dev_private;
14697
14698         if (INTEL_INFO(dev)->gen >= 9)
14699                 return false;
14700
14701         if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
14702                 return false;
14703
14704         if (IS_CHERRYVIEW(dev))
14705                 return false;
14706
14707         if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
14708                 return false;
14709
14710         /* DDI E can't be used if DDI A requires 4 lanes */
14711         if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
14712                 return false;
14713
14714         if (!dev_priv->vbt.int_crt_support)
14715                 return false;
14716
14717         return true;
14718 }
14719
14720 static void intel_setup_outputs(struct drm_device *dev)
14721 {
14722         struct drm_i915_private *dev_priv = dev->dev_private;
14723         struct intel_encoder *encoder;
14724         bool dpd_is_edp = false;
14725
14726         /*
14727          * intel_edp_init_connector() depends on this completing first, to
14728          * prevent the registeration of both eDP and LVDS and the incorrect
14729          * sharing of the PPS.
14730          */
14731         intel_lvds_init(dev);
14732
14733         if (intel_crt_present(dev))
14734                 intel_crt_init(dev);
14735
14736         if (IS_BROXTON(dev)) {
14737                 /*
14738                  * FIXME: Broxton doesn't support port detection via the
14739                  * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14740                  * detect the ports.
14741                  */
14742                 intel_ddi_init(dev, PORT_A);
14743                 intel_ddi_init(dev, PORT_B);
14744                 intel_ddi_init(dev, PORT_C);
14745
14746                 intel_dsi_init(dev);
14747         } else if (HAS_DDI(dev)) {
14748                 int found;
14749
14750                 /*
14751                  * Haswell uses DDI functions to detect digital outputs.
14752                  * On SKL pre-D0 the strap isn't connected, so we assume
14753                  * it's there.
14754                  */
14755                 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
14756                 /* WaIgnoreDDIAStrap: skl */
14757                 if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
14758                         intel_ddi_init(dev, PORT_A);
14759
14760                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14761                  * register */
14762                 found = I915_READ(SFUSE_STRAP);
14763
14764                 if (found & SFUSE_STRAP_DDIB_DETECTED)
14765                         intel_ddi_init(dev, PORT_B);
14766                 if (found & SFUSE_STRAP_DDIC_DETECTED)
14767                         intel_ddi_init(dev, PORT_C);
14768                 if (found & SFUSE_STRAP_DDID_DETECTED)
14769                         intel_ddi_init(dev, PORT_D);
14770                 /*
14771                  * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14772                  */
14773                 if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
14774                     (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14775                      dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14776                      dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14777                         intel_ddi_init(dev, PORT_E);
14778
14779         } else if (HAS_PCH_SPLIT(dev)) {
14780                 int found;
14781                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
14782
14783                 if (has_edp_a(dev))
14784                         intel_dp_init(dev, DP_A, PORT_A);
14785
14786                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14787                         /* PCH SDVOB multiplex with HDMIB */
14788                         found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B);
14789                         if (!found)
14790                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14791                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14792                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
14793                 }
14794
14795                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14796                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14797
14798                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14799                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14800
14801                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14802                         intel_dp_init(dev, PCH_DP_C, PORT_C);
14803
14804                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14805                         intel_dp_init(dev, PCH_DP_D, PORT_D);
14806         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
14807                 bool has_edp, has_port;
14808
14809                 /*
14810                  * The DP_DETECTED bit is the latched state of the DDC
14811                  * SDA pin at boot. However since eDP doesn't require DDC
14812                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
14813                  * eDP ports may have been muxed to an alternate function.
14814                  * Thus we can't rely on the DP_DETECTED bit alone to detect
14815                  * eDP ports. Consult the VBT as well as DP_DETECTED to
14816                  * detect eDP ports.
14817                  *
14818                  * Sadly the straps seem to be missing sometimes even for HDMI
14819                  * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
14820                  * and VBT for the presence of the port. Additionally we can't
14821                  * trust the port type the VBT declares as we've seen at least
14822                  * HDMI ports that the VBT claim are DP or eDP.
14823                  */
14824                 has_edp = intel_dp_is_edp(dev, PORT_B);
14825                 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
14826                 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
14827                         has_edp &= intel_dp_init(dev, VLV_DP_B, PORT_B);
14828                 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
14829                         intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
14830
14831                 has_edp = intel_dp_is_edp(dev, PORT_C);
14832                 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
14833                 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
14834                         has_edp &= intel_dp_init(dev, VLV_DP_C, PORT_C);
14835                 if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
14836                         intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
14837
14838                 if (IS_CHERRYVIEW(dev)) {
14839                         /*
14840                          * eDP not supported on port D,
14841                          * so no need to worry about it
14842                          */
14843                         has_port = intel_bios_is_port_present(dev_priv, PORT_D);
14844                         if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port)
14845                                 intel_dp_init(dev, CHV_DP_D, PORT_D);
14846                         if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port)
14847                                 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
14848                 }
14849
14850                 intel_dsi_init(dev);
14851         } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
14852                 bool found = false;
14853
14854                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14855                         DRM_DEBUG_KMS("probing SDVOB\n");
14856                         found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B);
14857                         if (!found && IS_G4X(dev)) {
14858                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14859                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14860                         }
14861
14862                         if (!found && IS_G4X(dev))
14863                                 intel_dp_init(dev, DP_B, PORT_B);
14864                 }
14865
14866                 /* Before G4X SDVOC doesn't have its own detect register */
14867
14868                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14869                         DRM_DEBUG_KMS("probing SDVOC\n");
14870                         found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C);
14871                 }
14872
14873                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14874
14875                         if (IS_G4X(dev)) {
14876                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14877                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14878                         }
14879                         if (IS_G4X(dev))
14880                                 intel_dp_init(dev, DP_C, PORT_C);
14881                 }
14882
14883                 if (IS_G4X(dev) &&
14884                     (I915_READ(DP_D) & DP_DETECTED))
14885                         intel_dp_init(dev, DP_D, PORT_D);
14886         } else if (IS_GEN2(dev))
14887                 intel_dvo_init(dev);
14888
14889         if (SUPPORTS_TV(dev))
14890                 intel_tv_init(dev);
14891
14892         intel_psr_init(dev);
14893
14894         for_each_intel_encoder(dev, encoder) {
14895                 encoder->base.possible_crtcs = encoder->crtc_mask;
14896                 encoder->base.possible_clones =
14897                         intel_encoder_clones(encoder);
14898         }
14899
14900         intel_init_pch_refclk(dev);
14901
14902         drm_helper_move_panel_connectors_to_head(dev);
14903 }
14904
14905 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14906 {
14907         struct drm_device *dev = fb->dev;
14908         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14909
14910         drm_framebuffer_cleanup(fb);
14911         mutex_lock(&dev->struct_mutex);
14912         WARN_ON(!intel_fb->obj->framebuffer_references--);
14913         drm_gem_object_unreference(&intel_fb->obj->base);
14914         mutex_unlock(&dev->struct_mutex);
14915         kfree(intel_fb);
14916 }
14917
14918 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14919                                                 struct drm_file *file,
14920                                                 unsigned int *handle)
14921 {
14922         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14923         struct drm_i915_gem_object *obj = intel_fb->obj;
14924
14925         if (obj->userptr.mm) {
14926                 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14927                 return -EINVAL;
14928         }
14929
14930         return drm_gem_handle_create(file, &obj->base, handle);
14931 }
14932
14933 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14934                                         struct drm_file *file,
14935                                         unsigned flags, unsigned color,
14936                                         struct drm_clip_rect *clips,
14937                                         unsigned num_clips)
14938 {
14939         struct drm_device *dev = fb->dev;
14940         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14941         struct drm_i915_gem_object *obj = intel_fb->obj;
14942
14943         mutex_lock(&dev->struct_mutex);
14944         intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
14945         mutex_unlock(&dev->struct_mutex);
14946
14947         return 0;
14948 }
14949
14950 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14951         .destroy = intel_user_framebuffer_destroy,
14952         .create_handle = intel_user_framebuffer_create_handle,
14953         .dirty = intel_user_framebuffer_dirty,
14954 };
14955
14956 static
14957 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14958                          uint32_t pixel_format)
14959 {
14960         u32 gen = INTEL_INFO(dev)->gen;
14961
14962         if (gen >= 9) {
14963                 int cpp = drm_format_plane_cpp(pixel_format, 0);
14964
14965                 /* "The stride in bytes must not exceed the of the size of 8K
14966                  *  pixels and 32K bytes."
14967                  */
14968                 return min(8192 * cpp, 32768);
14969         } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
14970                 return 32*1024;
14971         } else if (gen >= 4) {
14972                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14973                         return 16*1024;
14974                 else
14975                         return 32*1024;
14976         } else if (gen >= 3) {
14977                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14978                         return 8*1024;
14979                 else
14980                         return 16*1024;
14981         } else {
14982                 /* XXX DSPC is limited to 4k tiled */
14983                 return 8*1024;
14984         }
14985 }
14986
14987 static int intel_framebuffer_init(struct drm_device *dev,
14988                                   struct intel_framebuffer *intel_fb,
14989                                   struct drm_mode_fb_cmd2 *mode_cmd,
14990                                   struct drm_i915_gem_object *obj)
14991 {
14992         struct drm_i915_private *dev_priv = to_i915(dev);
14993         unsigned int aligned_height;
14994         int ret;
14995         u32 pitch_limit, stride_alignment;
14996
14997         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14998
14999         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
15000                 /* Enforce that fb modifier and tiling mode match, but only for
15001                  * X-tiled. This is needed for FBC. */
15002                 if (!!(obj->tiling_mode == I915_TILING_X) !=
15003                     !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
15004                         DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
15005                         return -EINVAL;
15006                 }
15007         } else {
15008                 if (obj->tiling_mode == I915_TILING_X)
15009                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
15010                 else if (obj->tiling_mode == I915_TILING_Y) {
15011                         DRM_DEBUG("No Y tiling for legacy addfb\n");
15012                         return -EINVAL;
15013                 }
15014         }
15015
15016         /* Passed in modifier sanity checking. */
15017         switch (mode_cmd->modifier[0]) {
15018         case I915_FORMAT_MOD_Y_TILED:
15019         case I915_FORMAT_MOD_Yf_TILED:
15020                 if (INTEL_INFO(dev)->gen < 9) {
15021                         DRM_DEBUG("Unsupported tiling 0x%llx!\n",
15022                                   mode_cmd->modifier[0]);
15023                         return -EINVAL;
15024                 }
15025         case DRM_FORMAT_MOD_NONE:
15026         case I915_FORMAT_MOD_X_TILED:
15027                 break;
15028         default:
15029                 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
15030                           mode_cmd->modifier[0]);
15031                 return -EINVAL;
15032         }
15033
15034         stride_alignment = intel_fb_stride_alignment(dev_priv,
15035                                                      mode_cmd->modifier[0],
15036                                                      mode_cmd->pixel_format);
15037         if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
15038                 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
15039                           mode_cmd->pitches[0], stride_alignment);
15040                 return -EINVAL;
15041         }
15042
15043         pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
15044                                            mode_cmd->pixel_format);
15045         if (mode_cmd->pitches[0] > pitch_limit) {
15046                 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
15047                           mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
15048                           "tiled" : "linear",
15049                           mode_cmd->pitches[0], pitch_limit);
15050                 return -EINVAL;
15051         }
15052
15053         if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
15054             mode_cmd->pitches[0] != obj->stride) {
15055                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
15056                           mode_cmd->pitches[0], obj->stride);
15057                 return -EINVAL;
15058         }
15059
15060         /* Reject formats not supported by any plane early. */
15061         switch (mode_cmd->pixel_format) {
15062         case DRM_FORMAT_C8:
15063         case DRM_FORMAT_RGB565:
15064         case DRM_FORMAT_XRGB8888:
15065         case DRM_FORMAT_ARGB8888:
15066                 break;
15067         case DRM_FORMAT_XRGB1555:
15068                 if (INTEL_INFO(dev)->gen > 3) {
15069                         DRM_DEBUG("unsupported pixel format: %s\n",
15070                                   drm_get_format_name(mode_cmd->pixel_format));
15071                         return -EINVAL;
15072                 }
15073                 break;
15074         case DRM_FORMAT_ABGR8888:
15075                 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
15076                     INTEL_INFO(dev)->gen < 9) {
15077                         DRM_DEBUG("unsupported pixel format: %s\n",
15078                                   drm_get_format_name(mode_cmd->pixel_format));
15079                         return -EINVAL;
15080                 }
15081                 break;
15082         case DRM_FORMAT_XBGR8888:
15083         case DRM_FORMAT_XRGB2101010:
15084         case DRM_FORMAT_XBGR2101010:
15085                 if (INTEL_INFO(dev)->gen < 4) {
15086                         DRM_DEBUG("unsupported pixel format: %s\n",
15087                                   drm_get_format_name(mode_cmd->pixel_format));
15088                         return -EINVAL;
15089                 }
15090                 break;
15091         case DRM_FORMAT_ABGR2101010:
15092                 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
15093                         DRM_DEBUG("unsupported pixel format: %s\n",
15094                                   drm_get_format_name(mode_cmd->pixel_format));
15095                         return -EINVAL;
15096                 }
15097                 break;
15098         case DRM_FORMAT_YUYV:
15099         case DRM_FORMAT_UYVY:
15100         case DRM_FORMAT_YVYU:
15101         case DRM_FORMAT_VYUY:
15102                 if (INTEL_INFO(dev)->gen < 5) {
15103                         DRM_DEBUG("unsupported pixel format: %s\n",
15104                                   drm_get_format_name(mode_cmd->pixel_format));
15105                         return -EINVAL;
15106                 }
15107                 break;
15108         default:
15109                 DRM_DEBUG("unsupported pixel format: %s\n",
15110                           drm_get_format_name(mode_cmd->pixel_format));
15111                 return -EINVAL;
15112         }
15113
15114         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
15115         if (mode_cmd->offsets[0] != 0)
15116                 return -EINVAL;
15117
15118         aligned_height = intel_fb_align_height(dev, mode_cmd->height,
15119                                                mode_cmd->pixel_format,
15120                                                mode_cmd->modifier[0]);
15121         /* FIXME drm helper for size checks (especially planar formats)? */
15122         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
15123                 return -EINVAL;
15124
15125         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
15126         intel_fb->obj = obj;
15127
15128         intel_fill_fb_info(dev_priv, &intel_fb->base);
15129
15130         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
15131         if (ret) {
15132                 DRM_ERROR("framebuffer init failed %d\n", ret);
15133                 return ret;
15134         }
15135
15136         intel_fb->obj->framebuffer_references++;
15137
15138         return 0;
15139 }
15140
15141 static struct drm_framebuffer *
15142 intel_user_framebuffer_create(struct drm_device *dev,
15143                               struct drm_file *filp,
15144                               const struct drm_mode_fb_cmd2 *user_mode_cmd)
15145 {
15146         struct drm_framebuffer *fb;
15147         struct drm_i915_gem_object *obj;
15148         struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
15149
15150         obj = to_intel_bo(drm_gem_object_lookup(filp, mode_cmd.handles[0]));
15151         if (&obj->base == NULL)
15152                 return ERR_PTR(-ENOENT);
15153
15154         fb = intel_framebuffer_create(dev, &mode_cmd, obj);
15155         if (IS_ERR(fb))
15156                 drm_gem_object_unreference_unlocked(&obj->base);
15157
15158         return fb;
15159 }
15160
15161 #ifndef CONFIG_DRM_FBDEV_EMULATION
15162 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
15163 {
15164 }
15165 #endif
15166
15167 static const struct drm_mode_config_funcs intel_mode_funcs = {
15168         .fb_create = intel_user_framebuffer_create,
15169         .output_poll_changed = intel_fbdev_output_poll_changed,
15170         .atomic_check = intel_atomic_check,
15171         .atomic_commit = intel_atomic_commit,
15172         .atomic_state_alloc = intel_atomic_state_alloc,
15173         .atomic_state_clear = intel_atomic_state_clear,
15174 };
15175
15176 /**
15177  * intel_init_display_hooks - initialize the display modesetting hooks
15178  * @dev_priv: device private
15179  */
15180 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
15181 {
15182         if (INTEL_INFO(dev_priv)->gen >= 9) {
15183                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
15184                 dev_priv->display.get_initial_plane_config =
15185                         skylake_get_initial_plane_config;
15186                 dev_priv->display.crtc_compute_clock =
15187                         haswell_crtc_compute_clock;
15188                 dev_priv->display.crtc_enable = haswell_crtc_enable;
15189                 dev_priv->display.crtc_disable = haswell_crtc_disable;
15190         } else if (HAS_DDI(dev_priv)) {
15191                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
15192                 dev_priv->display.get_initial_plane_config =
15193                         ironlake_get_initial_plane_config;
15194                 dev_priv->display.crtc_compute_clock =
15195                         haswell_crtc_compute_clock;
15196                 dev_priv->display.crtc_enable = haswell_crtc_enable;
15197                 dev_priv->display.crtc_disable = haswell_crtc_disable;
15198         } else if (HAS_PCH_SPLIT(dev_priv)) {
15199                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
15200                 dev_priv->display.get_initial_plane_config =
15201                         ironlake_get_initial_plane_config;
15202                 dev_priv->display.crtc_compute_clock =
15203                         ironlake_crtc_compute_clock;
15204                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
15205                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
15206         } else if (IS_CHERRYVIEW(dev_priv)) {
15207                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15208                 dev_priv->display.get_initial_plane_config =
15209                         i9xx_get_initial_plane_config;
15210                 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
15211                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
15212                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15213         } else if (IS_VALLEYVIEW(dev_priv)) {
15214                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15215                 dev_priv->display.get_initial_plane_config =
15216                         i9xx_get_initial_plane_config;
15217                 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
15218                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
15219                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15220         } else if (IS_G4X(dev_priv)) {
15221                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15222                 dev_priv->display.get_initial_plane_config =
15223                         i9xx_get_initial_plane_config;
15224                 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
15225                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15226                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15227         } else if (IS_PINEVIEW(dev_priv)) {
15228                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15229                 dev_priv->display.get_initial_plane_config =
15230                         i9xx_get_initial_plane_config;
15231                 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
15232                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15233                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15234         } else if (!IS_GEN2(dev_priv)) {
15235                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15236                 dev_priv->display.get_initial_plane_config =
15237                         i9xx_get_initial_plane_config;
15238                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
15239                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15240                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15241         } else {
15242                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15243                 dev_priv->display.get_initial_plane_config =
15244                         i9xx_get_initial_plane_config;
15245                 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
15246                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15247                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15248         }
15249
15250         /* Returns the core display clock speed */
15251         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
15252                 dev_priv->display.get_display_clock_speed =
15253                         skylake_get_display_clock_speed;
15254         else if (IS_BROXTON(dev_priv))
15255                 dev_priv->display.get_display_clock_speed =
15256                         broxton_get_display_clock_speed;
15257         else if (IS_BROADWELL(dev_priv))
15258                 dev_priv->display.get_display_clock_speed =
15259                         broadwell_get_display_clock_speed;
15260         else if (IS_HASWELL(dev_priv))
15261                 dev_priv->display.get_display_clock_speed =
15262                         haswell_get_display_clock_speed;
15263         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15264                 dev_priv->display.get_display_clock_speed =
15265                         valleyview_get_display_clock_speed;
15266         else if (IS_GEN5(dev_priv))
15267                 dev_priv->display.get_display_clock_speed =
15268                         ilk_get_display_clock_speed;
15269         else if (IS_I945G(dev_priv) || IS_BROADWATER(dev_priv) ||
15270                  IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
15271                 dev_priv->display.get_display_clock_speed =
15272                         i945_get_display_clock_speed;
15273         else if (IS_GM45(dev_priv))
15274                 dev_priv->display.get_display_clock_speed =
15275                         gm45_get_display_clock_speed;
15276         else if (IS_CRESTLINE(dev_priv))
15277                 dev_priv->display.get_display_clock_speed =
15278                         i965gm_get_display_clock_speed;
15279         else if (IS_PINEVIEW(dev_priv))
15280                 dev_priv->display.get_display_clock_speed =
15281                         pnv_get_display_clock_speed;
15282         else if (IS_G33(dev_priv) || IS_G4X(dev_priv))
15283                 dev_priv->display.get_display_clock_speed =
15284                         g33_get_display_clock_speed;
15285         else if (IS_I915G(dev_priv))
15286                 dev_priv->display.get_display_clock_speed =
15287                         i915_get_display_clock_speed;
15288         else if (IS_I945GM(dev_priv) || IS_845G(dev_priv))
15289                 dev_priv->display.get_display_clock_speed =
15290                         i9xx_misc_get_display_clock_speed;
15291         else if (IS_I915GM(dev_priv))
15292                 dev_priv->display.get_display_clock_speed =
15293                         i915gm_get_display_clock_speed;
15294         else if (IS_I865G(dev_priv))
15295                 dev_priv->display.get_display_clock_speed =
15296                         i865_get_display_clock_speed;
15297         else if (IS_I85X(dev_priv))
15298                 dev_priv->display.get_display_clock_speed =
15299                         i85x_get_display_clock_speed;
15300         else { /* 830 */
15301                 WARN(!IS_I830(dev_priv), "Unknown platform. Assuming 133 MHz CDCLK\n");
15302                 dev_priv->display.get_display_clock_speed =
15303                         i830_get_display_clock_speed;
15304         }
15305
15306         if (IS_GEN5(dev_priv)) {
15307                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
15308         } else if (IS_GEN6(dev_priv)) {
15309                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
15310         } else if (IS_IVYBRIDGE(dev_priv)) {
15311                 /* FIXME: detect B0+ stepping and use auto training */
15312                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
15313         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
15314                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
15315         }
15316
15317         if (IS_BROADWELL(dev_priv)) {
15318                 dev_priv->display.modeset_commit_cdclk =
15319                         broadwell_modeset_commit_cdclk;
15320                 dev_priv->display.modeset_calc_cdclk =
15321                         broadwell_modeset_calc_cdclk;
15322         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
15323                 dev_priv->display.modeset_commit_cdclk =
15324                         valleyview_modeset_commit_cdclk;
15325                 dev_priv->display.modeset_calc_cdclk =
15326                         valleyview_modeset_calc_cdclk;
15327         } else if (IS_BROXTON(dev_priv)) {
15328                 dev_priv->display.modeset_commit_cdclk =
15329                         bxt_modeset_commit_cdclk;
15330                 dev_priv->display.modeset_calc_cdclk =
15331                         bxt_modeset_calc_cdclk;
15332         } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
15333                 dev_priv->display.modeset_commit_cdclk =
15334                         skl_modeset_commit_cdclk;
15335                 dev_priv->display.modeset_calc_cdclk =
15336                         skl_modeset_calc_cdclk;
15337         }
15338
15339         switch (INTEL_INFO(dev_priv)->gen) {
15340         case 2:
15341                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
15342                 break;
15343
15344         case 3:
15345                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
15346                 break;
15347
15348         case 4:
15349         case 5:
15350                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
15351                 break;
15352
15353         case 6:
15354                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
15355                 break;
15356         case 7:
15357         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
15358                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
15359                 break;
15360         case 9:
15361                 /* Drop through - unsupported since execlist only. */
15362         default:
15363                 /* Default just returns -ENODEV to indicate unsupported */
15364                 dev_priv->display.queue_flip = intel_default_queue_flip;
15365         }
15366 }
15367
15368 /*
15369  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
15370  * resume, or other times.  This quirk makes sure that's the case for
15371  * affected systems.
15372  */
15373 static void quirk_pipea_force(struct drm_device *dev)
15374 {
15375         struct drm_i915_private *dev_priv = dev->dev_private;
15376
15377         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
15378         DRM_INFO("applying pipe a force quirk\n");
15379 }
15380
15381 static void quirk_pipeb_force(struct drm_device *dev)
15382 {
15383         struct drm_i915_private *dev_priv = dev->dev_private;
15384
15385         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
15386         DRM_INFO("applying pipe b force quirk\n");
15387 }
15388
15389 /*
15390  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
15391  */
15392 static void quirk_ssc_force_disable(struct drm_device *dev)
15393 {
15394         struct drm_i915_private *dev_priv = dev->dev_private;
15395         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
15396         DRM_INFO("applying lvds SSC disable quirk\n");
15397 }
15398
15399 /*
15400  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
15401  * brightness value
15402  */
15403 static void quirk_invert_brightness(struct drm_device *dev)
15404 {
15405         struct drm_i915_private *dev_priv = dev->dev_private;
15406         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
15407         DRM_INFO("applying inverted panel brightness quirk\n");
15408 }
15409
15410 /* Some VBT's incorrectly indicate no backlight is present */
15411 static void quirk_backlight_present(struct drm_device *dev)
15412 {
15413         struct drm_i915_private *dev_priv = dev->dev_private;
15414         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
15415         DRM_INFO("applying backlight present quirk\n");
15416 }
15417
15418 struct intel_quirk {
15419         int device;
15420         int subsystem_vendor;
15421         int subsystem_device;
15422         void (*hook)(struct drm_device *dev);
15423 };
15424
15425 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
15426 struct intel_dmi_quirk {
15427         void (*hook)(struct drm_device *dev);
15428         const struct dmi_system_id (*dmi_id_list)[];
15429 };
15430
15431 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
15432 {
15433         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
15434         return 1;
15435 }
15436
15437 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
15438         {
15439                 .dmi_id_list = &(const struct dmi_system_id[]) {
15440                         {
15441                                 .callback = intel_dmi_reverse_brightness,
15442                                 .ident = "NCR Corporation",
15443                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
15444                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
15445                                 },
15446                         },
15447                         { }  /* terminating entry */
15448                 },
15449                 .hook = quirk_invert_brightness,
15450         },
15451 };
15452
15453 static struct intel_quirk intel_quirks[] = {
15454         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
15455         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
15456
15457         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
15458         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
15459
15460         /* 830 needs to leave pipe A & dpll A up */
15461         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
15462
15463         /* 830 needs to leave pipe B & dpll B up */
15464         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
15465
15466         /* Lenovo U160 cannot use SSC on LVDS */
15467         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
15468
15469         /* Sony Vaio Y cannot use SSC on LVDS */
15470         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
15471
15472         /* Acer Aspire 5734Z must invert backlight brightness */
15473         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
15474
15475         /* Acer/eMachines G725 */
15476         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
15477
15478         /* Acer/eMachines e725 */
15479         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
15480
15481         /* Acer/Packard Bell NCL20 */
15482         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
15483
15484         /* Acer Aspire 4736Z */
15485         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
15486
15487         /* Acer Aspire 5336 */
15488         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
15489
15490         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
15491         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
15492
15493         /* Acer C720 Chromebook (Core i3 4005U) */
15494         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
15495
15496         /* Apple Macbook 2,1 (Core 2 T7400) */
15497         { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
15498
15499         /* Apple Macbook 4,1 */
15500         { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
15501
15502         /* Toshiba CB35 Chromebook (Celeron 2955U) */
15503         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
15504
15505         /* HP Chromebook 14 (Celeron 2955U) */
15506         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
15507
15508         /* Dell Chromebook 11 */
15509         { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
15510
15511         /* Dell Chromebook 11 (2015 version) */
15512         { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
15513 };
15514
15515 static void intel_init_quirks(struct drm_device *dev)
15516 {
15517         struct pci_dev *d = dev->pdev;
15518         int i;
15519
15520         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
15521                 struct intel_quirk *q = &intel_quirks[i];
15522
15523                 if (d->device == q->device &&
15524                     (d->subsystem_vendor == q->subsystem_vendor ||
15525                      q->subsystem_vendor == PCI_ANY_ID) &&
15526                     (d->subsystem_device == q->subsystem_device ||
15527                      q->subsystem_device == PCI_ANY_ID))
15528                         q->hook(dev);
15529         }
15530         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
15531                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
15532                         intel_dmi_quirks[i].hook(dev);
15533         }
15534 }
15535
15536 /* Disable the VGA plane that we never use */
15537 static void i915_disable_vga(struct drm_device *dev)
15538 {
15539         struct drm_i915_private *dev_priv = dev->dev_private;
15540         u8 sr1;
15541         i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15542
15543         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
15544         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
15545         outb(SR01, VGA_SR_INDEX);
15546         sr1 = inb(VGA_SR_DATA);
15547         outb(sr1 | 1<<5, VGA_SR_DATA);
15548         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
15549         udelay(300);
15550
15551         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
15552         POSTING_READ(vga_reg);
15553 }
15554
15555 void intel_modeset_init_hw(struct drm_device *dev)
15556 {
15557         struct drm_i915_private *dev_priv = dev->dev_private;
15558
15559         intel_update_cdclk(dev);
15560
15561         dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq;
15562
15563         intel_init_clock_gating(dev);
15564         intel_enable_gt_powersave(dev_priv);
15565 }
15566
15567 /*
15568  * Calculate what we think the watermarks should be for the state we've read
15569  * out of the hardware and then immediately program those watermarks so that
15570  * we ensure the hardware settings match our internal state.
15571  *
15572  * We can calculate what we think WM's should be by creating a duplicate of the
15573  * current state (which was constructed during hardware readout) and running it
15574  * through the atomic check code to calculate new watermark values in the
15575  * state object.
15576  */
15577 static void sanitize_watermarks(struct drm_device *dev)
15578 {
15579         struct drm_i915_private *dev_priv = to_i915(dev);
15580         struct drm_atomic_state *state;
15581         struct drm_crtc *crtc;
15582         struct drm_crtc_state *cstate;
15583         struct drm_modeset_acquire_ctx ctx;
15584         int ret;
15585         int i;
15586
15587         /* Only supported on platforms that use atomic watermark design */
15588         if (!dev_priv->display.optimize_watermarks)
15589                 return;
15590
15591         /*
15592          * We need to hold connection_mutex before calling duplicate_state so
15593          * that the connector loop is protected.
15594          */
15595         drm_modeset_acquire_init(&ctx, 0);
15596 retry:
15597         ret = drm_modeset_lock_all_ctx(dev, &ctx);
15598         if (ret == -EDEADLK) {
15599                 drm_modeset_backoff(&ctx);
15600                 goto retry;
15601         } else if (WARN_ON(ret)) {
15602                 goto fail;
15603         }
15604
15605         state = drm_atomic_helper_duplicate_state(dev, &ctx);
15606         if (WARN_ON(IS_ERR(state)))
15607                 goto fail;
15608
15609         /*
15610          * Hardware readout is the only time we don't want to calculate
15611          * intermediate watermarks (since we don't trust the current
15612          * watermarks).
15613          */
15614         to_intel_atomic_state(state)->skip_intermediate_wm = true;
15615
15616         ret = intel_atomic_check(dev, state);
15617         if (ret) {
15618                 /*
15619                  * If we fail here, it means that the hardware appears to be
15620                  * programmed in a way that shouldn't be possible, given our
15621                  * understanding of watermark requirements.  This might mean a
15622                  * mistake in the hardware readout code or a mistake in the
15623                  * watermark calculations for a given platform.  Raise a WARN
15624                  * so that this is noticeable.
15625                  *
15626                  * If this actually happens, we'll have to just leave the
15627                  * BIOS-programmed watermarks untouched and hope for the best.
15628                  */
15629                 WARN(true, "Could not determine valid watermarks for inherited state\n");
15630                 goto fail;
15631         }
15632
15633         /* Write calculated watermark values back */
15634         for_each_crtc_in_state(state, crtc, cstate, i) {
15635                 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
15636
15637                 cs->wm.need_postvbl_update = true;
15638                 dev_priv->display.optimize_watermarks(cs);
15639         }
15640
15641         drm_atomic_state_free(state);
15642 fail:
15643         drm_modeset_drop_locks(&ctx);
15644         drm_modeset_acquire_fini(&ctx);
15645 }
15646
15647 void intel_modeset_init(struct drm_device *dev)
15648 {
15649         struct drm_i915_private *dev_priv = to_i915(dev);
15650         struct i915_ggtt *ggtt = &dev_priv->ggtt;
15651         int sprite, ret;
15652         enum pipe pipe;
15653         struct intel_crtc *crtc;
15654
15655         drm_mode_config_init(dev);
15656
15657         dev->mode_config.min_width = 0;
15658         dev->mode_config.min_height = 0;
15659
15660         dev->mode_config.preferred_depth = 24;
15661         dev->mode_config.prefer_shadow = 1;
15662
15663         dev->mode_config.allow_fb_modifiers = true;
15664
15665         dev->mode_config.funcs = &intel_mode_funcs;
15666
15667         intel_init_quirks(dev);
15668
15669         intel_init_pm(dev);
15670
15671         if (INTEL_INFO(dev)->num_pipes == 0)
15672                 return;
15673
15674         /*
15675          * There may be no VBT; and if the BIOS enabled SSC we can
15676          * just keep using it to avoid unnecessary flicker.  Whereas if the
15677          * BIOS isn't using it, don't assume it will work even if the VBT
15678          * indicates as much.
15679          */
15680         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
15681                 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15682                                             DREF_SSC1_ENABLE);
15683
15684                 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
15685                         DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
15686                                      bios_lvds_use_ssc ? "en" : "dis",
15687                                      dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
15688                         dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
15689                 }
15690         }
15691
15692         if (IS_GEN2(dev)) {
15693                 dev->mode_config.max_width = 2048;
15694                 dev->mode_config.max_height = 2048;
15695         } else if (IS_GEN3(dev)) {
15696                 dev->mode_config.max_width = 4096;
15697                 dev->mode_config.max_height = 4096;
15698         } else {
15699                 dev->mode_config.max_width = 8192;
15700                 dev->mode_config.max_height = 8192;
15701         }
15702
15703         if (IS_845G(dev) || IS_I865G(dev)) {
15704                 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
15705                 dev->mode_config.cursor_height = 1023;
15706         } else if (IS_GEN2(dev)) {
15707                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
15708                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
15709         } else {
15710                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
15711                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15712         }
15713
15714         dev->mode_config.fb_base = ggtt->mappable_base;
15715
15716         DRM_DEBUG_KMS("%d display pipe%s available.\n",
15717                       INTEL_INFO(dev)->num_pipes,
15718                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
15719
15720         for_each_pipe(dev_priv, pipe) {
15721                 intel_crtc_init(dev, pipe);
15722                 for_each_sprite(dev_priv, pipe, sprite) {
15723                         ret = intel_plane_init(dev, pipe, sprite);
15724                         if (ret)
15725                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
15726                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
15727                 }
15728         }
15729
15730         intel_update_czclk(dev_priv);
15731         intel_update_cdclk(dev);
15732
15733         intel_shared_dpll_init(dev);
15734
15735         if (dev_priv->max_cdclk_freq == 0)
15736                 intel_update_max_cdclk(dev);
15737
15738         /* Just disable it once at startup */
15739         i915_disable_vga(dev);
15740         intel_setup_outputs(dev);
15741
15742         drm_modeset_lock_all(dev);
15743         intel_modeset_setup_hw_state(dev);
15744         drm_modeset_unlock_all(dev);
15745
15746         for_each_intel_crtc(dev, crtc) {
15747                 struct intel_initial_plane_config plane_config = {};
15748
15749                 if (!crtc->active)
15750                         continue;
15751
15752                 /*
15753                  * Note that reserving the BIOS fb up front prevents us
15754                  * from stuffing other stolen allocations like the ring
15755                  * on top.  This prevents some ugliness at boot time, and
15756                  * can even allow for smooth boot transitions if the BIOS
15757                  * fb is large enough for the active pipe configuration.
15758                  */
15759                 dev_priv->display.get_initial_plane_config(crtc,
15760                                                            &plane_config);
15761
15762                 /*
15763                  * If the fb is shared between multiple heads, we'll
15764                  * just get the first one.
15765                  */
15766                 intel_find_initial_plane_obj(crtc, &plane_config);
15767         }
15768
15769         /*
15770          * Make sure hardware watermarks really match the state we read out.
15771          * Note that we need to do this after reconstructing the BIOS fb's
15772          * since the watermark calculation done here will use pstate->fb.
15773          */
15774         sanitize_watermarks(dev);
15775 }
15776
15777 static void intel_enable_pipe_a(struct drm_device *dev)
15778 {
15779         struct intel_connector *connector;
15780         struct drm_connector *crt = NULL;
15781         struct intel_load_detect_pipe load_detect_temp;
15782         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
15783
15784         /* We can't just switch on the pipe A, we need to set things up with a
15785          * proper mode and output configuration. As a gross hack, enable pipe A
15786          * by enabling the load detect pipe once. */
15787         for_each_intel_connector(dev, connector) {
15788                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15789                         crt = &connector->base;
15790                         break;
15791                 }
15792         }
15793
15794         if (!crt)
15795                 return;
15796
15797         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
15798                 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
15799 }
15800
15801 static bool
15802 intel_check_plane_mapping(struct intel_crtc *crtc)
15803 {
15804         struct drm_device *dev = crtc->base.dev;
15805         struct drm_i915_private *dev_priv = dev->dev_private;
15806         u32 val;
15807
15808         if (INTEL_INFO(dev)->num_pipes == 1)
15809                 return true;
15810
15811         val = I915_READ(DSPCNTR(!crtc->plane));
15812
15813         if ((val & DISPLAY_PLANE_ENABLE) &&
15814             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15815                 return false;
15816
15817         return true;
15818 }
15819
15820 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15821 {
15822         struct drm_device *dev = crtc->base.dev;
15823         struct intel_encoder *encoder;
15824
15825         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15826                 return true;
15827
15828         return false;
15829 }
15830
15831 static bool intel_encoder_has_connectors(struct intel_encoder *encoder)
15832 {
15833         struct drm_device *dev = encoder->base.dev;
15834         struct intel_connector *connector;
15835
15836         for_each_connector_on_encoder(dev, &encoder->base, connector)
15837                 return true;
15838
15839         return false;
15840 }
15841
15842 static void intel_sanitize_crtc(struct intel_crtc *crtc)
15843 {
15844         struct drm_device *dev = crtc->base.dev;
15845         struct drm_i915_private *dev_priv = dev->dev_private;
15846         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
15847
15848         /* Clear any frame start delays used for debugging left by the BIOS */
15849         if (!transcoder_is_dsi(cpu_transcoder)) {
15850                 i915_reg_t reg = PIPECONF(cpu_transcoder);
15851
15852                 I915_WRITE(reg,
15853                            I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15854         }
15855
15856         /* restore vblank interrupts to correct state */
15857         drm_crtc_vblank_reset(&crtc->base);
15858         if (crtc->active) {
15859                 struct intel_plane *plane;
15860
15861                 drm_crtc_vblank_on(&crtc->base);
15862
15863                 /* Disable everything but the primary plane */
15864                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15865                         if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
15866                                 continue;
15867
15868                         plane->disable_plane(&plane->base, &crtc->base);
15869                 }
15870         }
15871
15872         /* We need to sanitize the plane -> pipe mapping first because this will
15873          * disable the crtc (and hence change the state) if it is wrong. Note
15874          * that gen4+ has a fixed plane -> pipe mapping.  */
15875         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
15876                 bool plane;
15877
15878                 DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n",
15879                               crtc->base.base.id, crtc->base.name);
15880
15881                 /* Pipe has the wrong plane attached and the plane is active.
15882                  * Temporarily change the plane mapping and disable everything
15883                  * ...  */
15884                 plane = crtc->plane;
15885                 to_intel_plane_state(crtc->base.primary->state)->visible = true;
15886                 crtc->plane = !plane;
15887                 intel_crtc_disable_noatomic(&crtc->base);
15888                 crtc->plane = plane;
15889         }
15890
15891         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15892             crtc->pipe == PIPE_A && !crtc->active) {
15893                 /* BIOS forgot to enable pipe A, this mostly happens after
15894                  * resume. Force-enable the pipe to fix this, the update_dpms
15895                  * call below we restore the pipe to the right state, but leave
15896                  * the required bits on. */
15897                 intel_enable_pipe_a(dev);
15898         }
15899
15900         /* Adjust the state of the output pipe according to whether we
15901          * have active connectors/encoders. */
15902         if (crtc->active && !intel_crtc_has_encoders(crtc))
15903                 intel_crtc_disable_noatomic(&crtc->base);
15904
15905         if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
15906                 /*
15907                  * We start out with underrun reporting disabled to avoid races.
15908                  * For correct bookkeeping mark this on active crtcs.
15909                  *
15910                  * Also on gmch platforms we dont have any hardware bits to
15911                  * disable the underrun reporting. Which means we need to start
15912                  * out with underrun reporting disabled also on inactive pipes,
15913                  * since otherwise we'll complain about the garbage we read when
15914                  * e.g. coming up after runtime pm.
15915                  *
15916                  * No protection against concurrent access is required - at
15917                  * worst a fifo underrun happens which also sets this to false.
15918                  */
15919                 crtc->cpu_fifo_underrun_disabled = true;
15920                 crtc->pch_fifo_underrun_disabled = true;
15921         }
15922 }
15923
15924 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15925 {
15926         struct intel_connector *connector;
15927         struct drm_device *dev = encoder->base.dev;
15928
15929         /* We need to check both for a crtc link (meaning that the
15930          * encoder is active and trying to read from a pipe) and the
15931          * pipe itself being active. */
15932         bool has_active_crtc = encoder->base.crtc &&
15933                 to_intel_crtc(encoder->base.crtc)->active;
15934
15935         if (intel_encoder_has_connectors(encoder) && !has_active_crtc) {
15936                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15937                               encoder->base.base.id,
15938                               encoder->base.name);
15939
15940                 /* Connector is active, but has no active pipe. This is
15941                  * fallout from our resume register restoring. Disable
15942                  * the encoder manually again. */
15943                 if (encoder->base.crtc) {
15944                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15945                                       encoder->base.base.id,
15946                                       encoder->base.name);
15947                         encoder->disable(encoder);
15948                         if (encoder->post_disable)
15949                                 encoder->post_disable(encoder);
15950                 }
15951                 encoder->base.crtc = NULL;
15952
15953                 /* Inconsistent output/port/pipe state happens presumably due to
15954                  * a bug in one of the get_hw_state functions. Or someplace else
15955                  * in our code, like the register restore mess on resume. Clamp
15956                  * things to off as a safer default. */
15957                 for_each_intel_connector(dev, connector) {
15958                         if (connector->encoder != encoder)
15959                                 continue;
15960                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15961                         connector->base.encoder = NULL;
15962                 }
15963         }
15964         /* Enabled encoders without active connectors will be fixed in
15965          * the crtc fixup. */
15966 }
15967
15968 void i915_redisable_vga_power_on(struct drm_device *dev)
15969 {
15970         struct drm_i915_private *dev_priv = dev->dev_private;
15971         i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15972
15973         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15974                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15975                 i915_disable_vga(dev);
15976         }
15977 }
15978
15979 void i915_redisable_vga(struct drm_device *dev)
15980 {
15981         struct drm_i915_private *dev_priv = dev->dev_private;
15982
15983         /* This function can be called both from intel_modeset_setup_hw_state or
15984          * at a very early point in our resume sequence, where the power well
15985          * structures are not yet restored. Since this function is at a very
15986          * paranoid "someone might have enabled VGA while we were not looking"
15987          * level, just check if the power well is enabled instead of trying to
15988          * follow the "don't touch the power well if we don't need it" policy
15989          * the rest of the driver uses. */
15990         if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
15991                 return;
15992
15993         i915_redisable_vga_power_on(dev);
15994
15995         intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
15996 }
15997
15998 static bool primary_get_hw_state(struct intel_plane *plane)
15999 {
16000         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
16001
16002         return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
16003 }
16004
16005 /* FIXME read out full plane state for all planes */
16006 static void readout_plane_state(struct intel_crtc *crtc)
16007 {
16008         struct drm_plane *primary = crtc->base.primary;
16009         struct intel_plane_state *plane_state =
16010                 to_intel_plane_state(primary->state);
16011
16012         plane_state->visible = crtc->active &&
16013                 primary_get_hw_state(to_intel_plane(primary));
16014
16015         if (plane_state->visible)
16016                 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
16017 }
16018
16019 static void intel_modeset_readout_hw_state(struct drm_device *dev)
16020 {
16021         struct drm_i915_private *dev_priv = dev->dev_private;
16022         enum pipe pipe;
16023         struct intel_crtc *crtc;
16024         struct intel_encoder *encoder;
16025         struct intel_connector *connector;
16026         int i;
16027
16028         dev_priv->active_crtcs = 0;
16029
16030         for_each_intel_crtc(dev, crtc) {
16031                 struct intel_crtc_state *crtc_state = crtc->config;
16032                 int pixclk = 0;
16033
16034                 __drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
16035                 memset(crtc_state, 0, sizeof(*crtc_state));
16036                 crtc_state->base.crtc = &crtc->base;
16037
16038                 crtc_state->base.active = crtc_state->base.enable =
16039                         dev_priv->display.get_pipe_config(crtc, crtc_state);
16040
16041                 crtc->base.enabled = crtc_state->base.enable;
16042                 crtc->active = crtc_state->base.active;
16043
16044                 if (crtc_state->base.active) {
16045                         dev_priv->active_crtcs |= 1 << crtc->pipe;
16046
16047                         if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
16048                                 pixclk = ilk_pipe_pixel_rate(crtc_state);
16049                         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
16050                                 pixclk = crtc_state->base.adjusted_mode.crtc_clock;
16051                         else
16052                                 WARN_ON(dev_priv->display.modeset_calc_cdclk);
16053
16054                         /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
16055                         if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
16056                                 pixclk = DIV_ROUND_UP(pixclk * 100, 95);
16057                 }
16058
16059                 dev_priv->min_pixclk[crtc->pipe] = pixclk;
16060
16061                 readout_plane_state(crtc);
16062
16063                 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
16064                               crtc->base.base.id, crtc->base.name,
16065                               crtc->active ? "enabled" : "disabled");
16066         }
16067
16068         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
16069                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
16070
16071                 pll->on = pll->funcs.get_hw_state(dev_priv, pll,
16072                                                   &pll->config.hw_state);
16073                 pll->config.crtc_mask = 0;
16074                 for_each_intel_crtc(dev, crtc) {
16075                         if (crtc->active && crtc->config->shared_dpll == pll)
16076                                 pll->config.crtc_mask |= 1 << crtc->pipe;
16077                 }
16078                 pll->active_mask = pll->config.crtc_mask;
16079
16080                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
16081                               pll->name, pll->config.crtc_mask, pll->on);
16082         }
16083
16084         for_each_intel_encoder(dev, encoder) {
16085                 pipe = 0;
16086
16087                 if (encoder->get_hw_state(encoder, &pipe)) {
16088                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
16089                         encoder->base.crtc = &crtc->base;
16090                         encoder->get_config(encoder, crtc->config);
16091                 } else {
16092                         encoder->base.crtc = NULL;
16093                 }
16094
16095                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
16096                               encoder->base.base.id,
16097                               encoder->base.name,
16098                               encoder->base.crtc ? "enabled" : "disabled",
16099                               pipe_name(pipe));
16100         }
16101
16102         for_each_intel_connector(dev, connector) {
16103                 if (connector->get_hw_state(connector)) {
16104                         connector->base.dpms = DRM_MODE_DPMS_ON;
16105
16106                         encoder = connector->encoder;
16107                         connector->base.encoder = &encoder->base;
16108
16109                         if (encoder->base.crtc &&
16110                             encoder->base.crtc->state->active) {
16111                                 /*
16112                                  * This has to be done during hardware readout
16113                                  * because anything calling .crtc_disable may
16114                                  * rely on the connector_mask being accurate.
16115                                  */
16116                                 encoder->base.crtc->state->connector_mask |=
16117                                         1 << drm_connector_index(&connector->base);
16118                                 encoder->base.crtc->state->encoder_mask |=
16119                                         1 << drm_encoder_index(&encoder->base);
16120                         }
16121
16122                 } else {
16123                         connector->base.dpms = DRM_MODE_DPMS_OFF;
16124                         connector->base.encoder = NULL;
16125                 }
16126                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
16127                               connector->base.base.id,
16128                               connector->base.name,
16129                               connector->base.encoder ? "enabled" : "disabled");
16130         }
16131
16132         for_each_intel_crtc(dev, crtc) {
16133                 crtc->base.hwmode = crtc->config->base.adjusted_mode;
16134
16135                 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
16136                 if (crtc->base.state->active) {
16137                         intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
16138                         intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
16139                         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
16140
16141                         /*
16142                          * The initial mode needs to be set in order to keep
16143                          * the atomic core happy. It wants a valid mode if the
16144                          * crtc's enabled, so we do the above call.
16145                          *
16146                          * At this point some state updated by the connectors
16147                          * in their ->detect() callback has not run yet, so
16148                          * no recalculation can be done yet.
16149                          *
16150                          * Even if we could do a recalculation and modeset
16151                          * right now it would cause a double modeset if
16152                          * fbdev or userspace chooses a different initial mode.
16153                          *
16154                          * If that happens, someone indicated they wanted a
16155                          * mode change, which means it's safe to do a full
16156                          * recalculation.
16157                          */
16158                         crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
16159
16160                         drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
16161                         update_scanline_offset(crtc);
16162                 }
16163
16164                 intel_pipe_config_sanity_check(dev_priv, crtc->config);
16165         }
16166 }
16167
16168 /* Scan out the current hw modeset state,
16169  * and sanitizes it to the current state
16170  */
16171 static void
16172 intel_modeset_setup_hw_state(struct drm_device *dev)
16173 {
16174         struct drm_i915_private *dev_priv = dev->dev_private;
16175         enum pipe pipe;
16176         struct intel_crtc *crtc;
16177         struct intel_encoder *encoder;
16178         int i;
16179
16180         intel_modeset_readout_hw_state(dev);
16181
16182         /* HW state is read out, now we need to sanitize this mess. */
16183         for_each_intel_encoder(dev, encoder) {
16184                 intel_sanitize_encoder(encoder);
16185         }
16186
16187         for_each_pipe(dev_priv, pipe) {
16188                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
16189                 intel_sanitize_crtc(crtc);
16190                 intel_dump_pipe_config(crtc, crtc->config,
16191                                        "[setup_hw_state]");
16192         }
16193
16194         intel_modeset_update_connector_atomic_state(dev);
16195
16196         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
16197                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
16198
16199                 if (!pll->on || pll->active_mask)
16200                         continue;
16201
16202                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
16203
16204                 pll->funcs.disable(dev_priv, pll);
16205                 pll->on = false;
16206         }
16207
16208         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
16209                 vlv_wm_get_hw_state(dev);
16210         else if (IS_GEN9(dev))
16211                 skl_wm_get_hw_state(dev);
16212         else if (HAS_PCH_SPLIT(dev))
16213                 ilk_wm_get_hw_state(dev);
16214
16215         for_each_intel_crtc(dev, crtc) {
16216                 unsigned long put_domains;
16217
16218                 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
16219                 if (WARN_ON(put_domains))
16220                         modeset_put_power_domains(dev_priv, put_domains);
16221         }
16222         intel_display_set_init_power(dev_priv, false);
16223
16224         intel_fbc_init_pipe_state(dev_priv);
16225 }
16226
16227 void intel_display_resume(struct drm_device *dev)
16228 {
16229         struct drm_i915_private *dev_priv = to_i915(dev);
16230         struct drm_atomic_state *state = dev_priv->modeset_restore_state;
16231         struct drm_modeset_acquire_ctx ctx;
16232         int ret;
16233         bool setup = false;
16234
16235         dev_priv->modeset_restore_state = NULL;
16236
16237         /*
16238          * This is a cludge because with real atomic modeset mode_config.mutex
16239          * won't be taken. Unfortunately some probed state like
16240          * audio_codec_enable is still protected by mode_config.mutex, so lock
16241          * it here for now.
16242          */
16243         mutex_lock(&dev->mode_config.mutex);
16244         drm_modeset_acquire_init(&ctx, 0);
16245
16246 retry:
16247         ret = drm_modeset_lock_all_ctx(dev, &ctx);
16248
16249         if (ret == 0 && !setup) {
16250                 setup = true;
16251
16252                 intel_modeset_setup_hw_state(dev);
16253                 i915_redisable_vga(dev);
16254         }
16255
16256         if (ret == 0 && state) {
16257                 struct drm_crtc_state *crtc_state;
16258                 struct drm_crtc *crtc;
16259                 int i;
16260
16261                 state->acquire_ctx = &ctx;
16262
16263                 /* ignore any reset values/BIOS leftovers in the WM registers */
16264                 to_intel_atomic_state(state)->skip_intermediate_wm = true;
16265
16266                 for_each_crtc_in_state(state, crtc, crtc_state, i) {
16267                         /*
16268                          * Force recalculation even if we restore
16269                          * current state. With fast modeset this may not result
16270                          * in a modeset when the state is compatible.
16271                          */
16272                         crtc_state->mode_changed = true;
16273                 }
16274
16275                 ret = drm_atomic_commit(state);
16276         }
16277
16278         if (ret == -EDEADLK) {
16279                 drm_modeset_backoff(&ctx);
16280                 goto retry;
16281         }
16282
16283         drm_modeset_drop_locks(&ctx);
16284         drm_modeset_acquire_fini(&ctx);
16285         mutex_unlock(&dev->mode_config.mutex);
16286
16287         if (ret) {
16288                 DRM_ERROR("Restoring old state failed with %i\n", ret);
16289                 drm_atomic_state_free(state);
16290         }
16291 }
16292
16293 void intel_modeset_gem_init(struct drm_device *dev)
16294 {
16295         struct drm_i915_private *dev_priv = to_i915(dev);
16296         struct drm_crtc *c;
16297         struct drm_i915_gem_object *obj;
16298         int ret;
16299
16300         intel_init_gt_powersave(dev_priv);
16301
16302         intel_modeset_init_hw(dev);
16303
16304         intel_setup_overlay(dev_priv);
16305
16306         /*
16307          * Make sure any fbs we allocated at startup are properly
16308          * pinned & fenced.  When we do the allocation it's too early
16309          * for this.
16310          */
16311         for_each_crtc(dev, c) {
16312                 obj = intel_fb_obj(c->primary->fb);
16313                 if (obj == NULL)
16314                         continue;
16315
16316                 mutex_lock(&dev->struct_mutex);
16317                 ret = intel_pin_and_fence_fb_obj(c->primary->fb,
16318                                                  c->primary->state->rotation);
16319                 mutex_unlock(&dev->struct_mutex);
16320                 if (ret) {
16321                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
16322                                   to_intel_crtc(c)->pipe);
16323                         drm_framebuffer_unreference(c->primary->fb);
16324                         c->primary->fb = NULL;
16325                         c->primary->crtc = c->primary->state->crtc = NULL;
16326                         update_state_fb(c->primary);
16327                         c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
16328                 }
16329         }
16330 }
16331
16332 int intel_connector_register(struct drm_connector *connector)
16333 {
16334         struct intel_connector *intel_connector = to_intel_connector(connector);
16335         int ret;
16336
16337         ret = intel_backlight_device_register(intel_connector);
16338         if (ret)
16339                 goto err;
16340
16341         return 0;
16342
16343 err:
16344         return ret;
16345 }
16346
16347 void intel_connector_unregister(struct drm_connector *connector)
16348 {
16349         struct intel_connector *intel_connector = to_intel_connector(connector);
16350
16351         intel_backlight_device_unregister(intel_connector);
16352         intel_panel_destroy_backlight(connector);
16353 }
16354
16355 void intel_modeset_cleanup(struct drm_device *dev)
16356 {
16357         struct drm_i915_private *dev_priv = dev->dev_private;
16358
16359         intel_disable_gt_powersave(dev_priv);
16360
16361         /*
16362          * Interrupts and polling as the first thing to avoid creating havoc.
16363          * Too much stuff here (turning of connectors, ...) would
16364          * experience fancy races otherwise.
16365          */
16366         intel_irq_uninstall(dev_priv);
16367
16368         /*
16369          * Due to the hpd irq storm handling the hotplug work can re-arm the
16370          * poll handlers. Hence disable polling after hpd handling is shut down.
16371          */
16372         drm_kms_helper_poll_fini(dev);
16373
16374         intel_unregister_dsm_handler();
16375
16376         intel_fbc_global_disable(dev_priv);
16377
16378         /* flush any delayed tasks or pending work */
16379         flush_scheduled_work();
16380
16381         drm_mode_config_cleanup(dev);
16382
16383         intel_cleanup_overlay(dev_priv);
16384
16385         intel_cleanup_gt_powersave(dev_priv);
16386
16387         intel_teardown_gmbus(dev);
16388 }
16389
16390 void intel_connector_attach_encoder(struct intel_connector *connector,
16391                                     struct intel_encoder *encoder)
16392 {
16393         connector->encoder = encoder;
16394         drm_mode_connector_attach_encoder(&connector->base,
16395                                           &encoder->base);
16396 }
16397
16398 /*
16399  * set vga decode state - true == enable VGA decode
16400  */
16401 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
16402 {
16403         struct drm_i915_private *dev_priv = dev->dev_private;
16404         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
16405         u16 gmch_ctrl;
16406
16407         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
16408                 DRM_ERROR("failed to read control word\n");
16409                 return -EIO;
16410         }
16411
16412         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
16413                 return 0;
16414
16415         if (state)
16416                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
16417         else
16418                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
16419
16420         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
16421                 DRM_ERROR("failed to write control word\n");
16422                 return -EIO;
16423         }
16424
16425         return 0;
16426 }
16427
16428 struct intel_display_error_state {
16429
16430         u32 power_well_driver;
16431
16432         int num_transcoders;
16433
16434         struct intel_cursor_error_state {
16435                 u32 control;
16436                 u32 position;
16437                 u32 base;
16438                 u32 size;
16439         } cursor[I915_MAX_PIPES];
16440
16441         struct intel_pipe_error_state {
16442                 bool power_domain_on;
16443                 u32 source;
16444                 u32 stat;
16445         } pipe[I915_MAX_PIPES];
16446
16447         struct intel_plane_error_state {
16448                 u32 control;
16449                 u32 stride;
16450                 u32 size;
16451                 u32 pos;
16452                 u32 addr;
16453                 u32 surface;
16454                 u32 tile_offset;
16455         } plane[I915_MAX_PIPES];
16456
16457         struct intel_transcoder_error_state {
16458                 bool power_domain_on;
16459                 enum transcoder cpu_transcoder;
16460
16461                 u32 conf;
16462
16463                 u32 htotal;
16464                 u32 hblank;
16465                 u32 hsync;
16466                 u32 vtotal;
16467                 u32 vblank;
16468                 u32 vsync;
16469         } transcoder[4];
16470 };
16471
16472 struct intel_display_error_state *
16473 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
16474 {
16475         struct intel_display_error_state *error;
16476         int transcoders[] = {
16477                 TRANSCODER_A,
16478                 TRANSCODER_B,
16479                 TRANSCODER_C,
16480                 TRANSCODER_EDP,
16481         };
16482         int i;
16483
16484         if (INTEL_INFO(dev_priv)->num_pipes == 0)
16485                 return NULL;
16486
16487         error = kzalloc(sizeof(*error), GFP_ATOMIC);
16488         if (error == NULL)
16489                 return NULL;
16490
16491         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
16492                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
16493
16494         for_each_pipe(dev_priv, i) {
16495                 error->pipe[i].power_domain_on =
16496                         __intel_display_power_is_enabled(dev_priv,
16497                                                          POWER_DOMAIN_PIPE(i));
16498                 if (!error->pipe[i].power_domain_on)
16499                         continue;
16500
16501                 error->cursor[i].control = I915_READ(CURCNTR(i));
16502                 error->cursor[i].position = I915_READ(CURPOS(i));
16503                 error->cursor[i].base = I915_READ(CURBASE(i));
16504
16505                 error->plane[i].control = I915_READ(DSPCNTR(i));
16506                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
16507                 if (INTEL_GEN(dev_priv) <= 3) {
16508                         error->plane[i].size = I915_READ(DSPSIZE(i));
16509                         error->plane[i].pos = I915_READ(DSPPOS(i));
16510                 }
16511                 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
16512                         error->plane[i].addr = I915_READ(DSPADDR(i));
16513                 if (INTEL_GEN(dev_priv) >= 4) {
16514                         error->plane[i].surface = I915_READ(DSPSURF(i));
16515                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
16516                 }
16517
16518                 error->pipe[i].source = I915_READ(PIPESRC(i));
16519
16520                 if (HAS_GMCH_DISPLAY(dev_priv))
16521                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
16522         }
16523
16524         /* Note: this does not include DSI transcoders. */
16525         error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;
16526         if (HAS_DDI(dev_priv))
16527                 error->num_transcoders++; /* Account for eDP. */
16528
16529         for (i = 0; i < error->num_transcoders; i++) {
16530                 enum transcoder cpu_transcoder = transcoders[i];
16531
16532                 error->transcoder[i].power_domain_on =
16533                         __intel_display_power_is_enabled(dev_priv,
16534                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
16535                 if (!error->transcoder[i].power_domain_on)
16536                         continue;
16537
16538                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
16539
16540                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
16541                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
16542                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
16543                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
16544                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
16545                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
16546                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
16547         }
16548
16549         return error;
16550 }
16551
16552 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
16553
16554 void
16555 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
16556                                 struct drm_device *dev,
16557                                 struct intel_display_error_state *error)
16558 {
16559         struct drm_i915_private *dev_priv = dev->dev_private;
16560         int i;
16561
16562         if (!error)
16563                 return;
16564
16565         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
16566         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
16567                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
16568                            error->power_well_driver);
16569         for_each_pipe(dev_priv, i) {
16570                 err_printf(m, "Pipe [%d]:\n", i);
16571                 err_printf(m, "  Power: %s\n",
16572                            onoff(error->pipe[i].power_domain_on));
16573                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
16574                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
16575
16576                 err_printf(m, "Plane [%d]:\n", i);
16577                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
16578                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
16579                 if (INTEL_INFO(dev)->gen <= 3) {
16580                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
16581                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
16582                 }
16583                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
16584                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
16585                 if (INTEL_INFO(dev)->gen >= 4) {
16586                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
16587                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
16588                 }
16589
16590                 err_printf(m, "Cursor [%d]:\n", i);
16591                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
16592                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
16593                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
16594         }
16595
16596         for (i = 0; i < error->num_transcoders; i++) {
16597                 err_printf(m, "CPU transcoder: %s\n",
16598                            transcoder_name(error->transcoder[i].cpu_transcoder));
16599                 err_printf(m, "  Power: %s\n",
16600                            onoff(error->transcoder[i].power_domain_on));
16601                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
16602                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
16603                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
16604                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
16605                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
16606                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
16607                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
16608         }
16609 }