drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  45 static void intel_increase_pllclock(struct drm_crtc *crtc);
  46 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  47
  48 typedef struct {
  49         int     min, max;
  50 } intel_range_t;
  51
  52 typedef struct {
  53         int     dot_limit;
  54         int     p2_slow, p2_fast;
  55 } intel_p2_t;
  56
  57 #define INTEL_P2_NUM                  2
  58 typedef struct intel_limit intel_limit_t;
  59 struct intel_limit {
  60         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  61         intel_p2_t          p2;
  62 };
  63
  64 /* FDI */
  65 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  66
  67 int
  68 intel_pch_rawclk(struct drm_device *dev)
  69 {
  70         struct drm_i915_private *dev_priv = dev->dev_private;
  71
  72         WARN_ON(!HAS_PCH_SPLIT(dev));
  73
  74         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  75 }
  76
  77 static inline u32 /* units of 100MHz */
  78 intel_fdi_link_freq(struct drm_device *dev)
  79 {
  80         if (IS_GEN5(dev)) {
  81                 struct drm_i915_private *dev_priv = dev->dev_private;
  82                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
  83         } else
  84                 return 27;
  85 }
  86
  87 static const intel_limit_t intel_limits_i8xx_dvo = {
  88         .dot = { .min = 25000, .max = 350000 },
  89         .vco = { .min = 930000, .max = 1400000 },
  90         .n = { .min = 3, .max = 16 },
  91         .m = { .min = 96, .max = 140 },
  92         .m1 = { .min = 18, .max = 26 },
  93         .m2 = { .min = 6, .max = 16 },
  94         .p = { .min = 4, .max = 128 },
  95         .p1 = { .min = 2, .max = 33 },
  96         .p2 = { .dot_limit = 165000,
  97                 .p2_slow = 4, .p2_fast = 2 },
  98 };
  99
 100 static const intel_limit_t intel_limits_i8xx_lvds = {
 101         .dot = { .min = 25000, .max = 350000 },
 102         .vco = { .min = 930000, .max = 1400000 },
 103         .n = { .min = 3, .max = 16 },
 104         .m = { .min = 96, .max = 140 },
 105         .m1 = { .min = 18, .max = 26 },
 106         .m2 = { .min = 6, .max = 16 },
 107         .p = { .min = 4, .max = 128 },
 108         .p1 = { .min = 1, .max = 6 },
 109         .p2 = { .dot_limit = 165000,
 110                 .p2_slow = 14, .p2_fast = 7 },
 111 };
 112
 113 static const intel_limit_t intel_limits_i9xx_sdvo = {
 114         .dot = { .min = 20000, .max = 400000 },
 115         .vco = { .min = 1400000, .max = 2800000 },
 116         .n = { .min = 1, .max = 6 },
 117         .m = { .min = 70, .max = 120 },
 118         .m1 = { .min = 8, .max = 18 },
 119         .m2 = { .min = 3, .max = 7 },
 120         .p = { .min = 5, .max = 80 },
 121         .p1 = { .min = 1, .max = 8 },
 122         .p2 = { .dot_limit = 200000,
 123                 .p2_slow = 10, .p2_fast = 5 },
 124 };
 125
 126 static const intel_limit_t intel_limits_i9xx_lvds = {
 127         .dot = { .min = 20000, .max = 400000 },
 128         .vco = { .min = 1400000, .max = 2800000 },
 129         .n = { .min = 1, .max = 6 },
 130         .m = { .min = 70, .max = 120 },
 131         .m1 = { .min = 8, .max = 18 },
 132         .m2 = { .min = 3, .max = 7 },
 133         .p = { .min = 7, .max = 98 },
 134         .p1 = { .min = 1, .max = 8 },
 135         .p2 = { .dot_limit = 112000,
 136                 .p2_slow = 14, .p2_fast = 7 },
 137 };
 138
 139
 140 static const intel_limit_t intel_limits_g4x_sdvo = {
 141         .dot = { .min = 25000, .max = 270000 },
 142         .vco = { .min = 1750000, .max = 3500000},
 143         .n = { .min = 1, .max = 4 },
 144         .m = { .min = 104, .max = 138 },
 145         .m1 = { .min = 17, .max = 23 },
 146         .m2 = { .min = 5, .max = 11 },
 147         .p = { .min = 10, .max = 30 },
 148         .p1 = { .min = 1, .max = 3},
 149         .p2 = { .dot_limit = 270000,
 150                 .p2_slow = 10,
 151                 .p2_fast = 10
 152         },
 153 };
 154
 155 static const intel_limit_t intel_limits_g4x_hdmi = {
 156         .dot = { .min = 22000, .max = 400000 },
 157         .vco = { .min = 1750000, .max = 3500000},
 158         .n = { .min = 1, .max = 4 },
 159         .m = { .min = 104, .max = 138 },
 160         .m1 = { .min = 16, .max = 23 },
 161         .m2 = { .min = 5, .max = 11 },
 162         .p = { .min = 5, .max = 80 },
 163         .p1 = { .min = 1, .max = 8},
 164         .p2 = { .dot_limit = 165000,
 165                 .p2_slow = 10, .p2_fast = 5 },
 166 };
 167
 168 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 169         .dot = { .min = 20000, .max = 115000 },
 170         .vco = { .min = 1750000, .max = 3500000 },
 171         .n = { .min = 1, .max = 3 },
 172         .m = { .min = 104, .max = 138 },
 173         .m1 = { .min = 17, .max = 23 },
 174         .m2 = { .min = 5, .max = 11 },
 175         .p = { .min = 28, .max = 112 },
 176         .p1 = { .min = 2, .max = 8 },
 177         .p2 = { .dot_limit = 0,
 178                 .p2_slow = 14, .p2_fast = 14
 179         },
 180 };
 181
 182 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 183         .dot = { .min = 80000, .max = 224000 },
 184         .vco = { .min = 1750000, .max = 3500000 },
 185         .n = { .min = 1, .max = 3 },
 186         .m = { .min = 104, .max = 138 },
 187         .m1 = { .min = 17, .max = 23 },
 188         .m2 = { .min = 5, .max = 11 },
 189         .p = { .min = 14, .max = 42 },
 190         .p1 = { .min = 2, .max = 6 },
 191         .p2 = { .dot_limit = 0,
 192                 .p2_slow = 7, .p2_fast = 7
 193         },
 194 };
 195
 196 static const intel_limit_t intel_limits_pineview_sdvo = {
 197         .dot = { .min = 20000, .max = 400000},
 198         .vco = { .min = 1700000, .max = 3500000 },
 199         /* Pineview's Ncounter is a ring counter */
 200         .n = { .min = 3, .max = 6 },
 201         .m = { .min = 2, .max = 256 },
 202         /* Pineview only has one combined m divider, which we treat as m2. */
 203         .m1 = { .min = 0, .max = 0 },
 204         .m2 = { .min = 0, .max = 254 },
 205         .p = { .min = 5, .max = 80 },
 206         .p1 = { .min = 1, .max = 8 },
 207         .p2 = { .dot_limit = 200000,
 208                 .p2_slow = 10, .p2_fast = 5 },
 209 };
 210
 211 static const intel_limit_t intel_limits_pineview_lvds = {
 212         .dot = { .min = 20000, .max = 400000 },
 213         .vco = { .min = 1700000, .max = 3500000 },
 214         .n = { .min = 3, .max = 6 },
 215         .m = { .min = 2, .max = 256 },
 216         .m1 = { .min = 0, .max = 0 },
 217         .m2 = { .min = 0, .max = 254 },
 218         .p = { .min = 7, .max = 112 },
 219         .p1 = { .min = 1, .max = 8 },
 220         .p2 = { .dot_limit = 112000,
 221                 .p2_slow = 14, .p2_fast = 14 },
 222 };
 223
 224 /* Ironlake / Sandybridge
 225  *
 226  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 227  * the range value for them is (actual_value - 2).
 228  */
 229 static const intel_limit_t intel_limits_ironlake_dac = {
 230         .dot = { .min = 25000, .max = 350000 },
 231         .vco = { .min = 1760000, .max = 3510000 },
 232         .n = { .min = 1, .max = 5 },
 233         .m = { .min = 79, .max = 127 },
 234         .m1 = { .min = 12, .max = 22 },
 235         .m2 = { .min = 5, .max = 9 },
 236         .p = { .min = 5, .max = 80 },
 237         .p1 = { .min = 1, .max = 8 },
 238         .p2 = { .dot_limit = 225000,
 239                 .p2_slow = 10, .p2_fast = 5 },
 240 };
 241
 242 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 243         .dot = { .min = 25000, .max = 350000 },
 244         .vco = { .min = 1760000, .max = 3510000 },
 245         .n = { .min = 1, .max = 3 },
 246         .m = { .min = 79, .max = 118 },
 247         .m1 = { .min = 12, .max = 22 },
 248         .m2 = { .min = 5, .max = 9 },
 249         .p = { .min = 28, .max = 112 },
 250         .p1 = { .min = 2, .max = 8 },
 251         .p2 = { .dot_limit = 225000,
 252                 .p2_slow = 14, .p2_fast = 14 },
 253 };
 254
 255 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 256         .dot = { .min = 25000, .max = 350000 },
 257         .vco = { .min = 1760000, .max = 3510000 },
 258         .n = { .min = 1, .max = 3 },
 259         .m = { .min = 79, .max = 127 },
 260         .m1 = { .min = 12, .max = 22 },
 261         .m2 = { .min = 5, .max = 9 },
 262         .p = { .min = 14, .max = 56 },
 263         .p1 = { .min = 2, .max = 8 },
 264         .p2 = { .dot_limit = 225000,
 265                 .p2_slow = 7, .p2_fast = 7 },
 266 };
 267
 268 /* LVDS 100mhz refclk limits. */
 269 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 270         .dot = { .min = 25000, .max = 350000 },
 271         .vco = { .min = 1760000, .max = 3510000 },
 272         .n = { .min = 1, .max = 2 },
 273         .m = { .min = 79, .max = 126 },
 274         .m1 = { .min = 12, .max = 22 },
 275         .m2 = { .min = 5, .max = 9 },
 276         .p = { .min = 28, .max = 112 },
 277         .p1 = { .min = 2, .max = 8 },
 278         .p2 = { .dot_limit = 225000,
 279                 .p2_slow = 14, .p2_fast = 14 },
 280 };
 281
 282 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 283         .dot = { .min = 25000, .max = 350000 },
 284         .vco = { .min = 1760000, .max = 3510000 },
 285         .n = { .min = 1, .max = 3 },
 286         .m = { .min = 79, .max = 126 },
 287         .m1 = { .min = 12, .max = 22 },
 288         .m2 = { .min = 5, .max = 9 },
 289         .p = { .min = 14, .max = 42 },
 290         .p1 = { .min = 2, .max = 6 },
 291         .p2 = { .dot_limit = 225000,
 292                 .p2_slow = 7, .p2_fast = 7 },
 293 };
 294
 295 static const intel_limit_t intel_limits_vlv_dac = {
 296         .dot = { .min = 25000, .max = 270000 },
 297         .vco = { .min = 4000000, .max = 6000000 },
 298         .n = { .min = 1, .max = 7 },
 299         .m = { .min = 22, .max = 450 }, /* guess */
 300         .m1 = { .min = 2, .max = 3 },
 301         .m2 = { .min = 11, .max = 156 },
 302         .p = { .min = 10, .max = 30 },
 303         .p1 = { .min = 1, .max = 3 },
 304         .p2 = { .dot_limit = 270000,
 305                 .p2_slow = 2, .p2_fast = 20 },
 306 };
 307
 308 static const intel_limit_t intel_limits_vlv_hdmi = {
 309         .dot = { .min = 25000, .max = 270000 },
 310         .vco = { .min = 4000000, .max = 6000000 },
 311         .n = { .min = 1, .max = 7 },
 312         .m = { .min = 60, .max = 300 }, /* guess */
 313         .m1 = { .min = 2, .max = 3 },
 314         .m2 = { .min = 11, .max = 156 },
 315         .p = { .min = 10, .max = 30 },
 316         .p1 = { .min = 2, .max = 3 },
 317         .p2 = { .dot_limit = 270000,
 318                 .p2_slow = 2, .p2_fast = 20 },
 319 };
 320
 321 static const intel_limit_t intel_limits_vlv_dp = {
 322         .dot = { .min = 25000, .max = 270000 },
 323         .vco = { .min = 4000000, .max = 6000000 },
 324         .n = { .min = 1, .max = 7 },
 325         .m = { .min = 22, .max = 450 },
 326         .m1 = { .min = 2, .max = 3 },
 327         .m2 = { .min = 11, .max = 156 },
 328         .p = { .min = 10, .max = 30 },
 329         .p1 = { .min = 1, .max = 3 },
 330         .p2 = { .dot_limit = 270000,
 331                 .p2_slow = 2, .p2_fast = 20 },
 332 };
 333
 334 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 335                                                 int refclk)
 336 {
 337         struct drm_device *dev = crtc->dev;
 338         const intel_limit_t *limit;
 339
 340         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 341                 if (intel_is_dual_link_lvds(dev)) {
 342                         if (refclk == 100000)
 343                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 344                         else
 345                                 limit = &intel_limits_ironlake_dual_lvds;
 346                 } else {
 347                         if (refclk == 100000)
 348                                 limit = &intel_limits_ironlake_single_lvds_100m;
 349                         else
 350                                 limit = &intel_limits_ironlake_single_lvds;
 351                 }
 352         } else
 353                 limit = &intel_limits_ironlake_dac;
 354
 355         return limit;
 356 }
 357
 358 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 359 {
 360         struct drm_device *dev = crtc->dev;
 361         const intel_limit_t *limit;
 362
 363         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 364                 if (intel_is_dual_link_lvds(dev))
 365                         limit = &intel_limits_g4x_dual_channel_lvds;
 366                 else
 367                         limit = &intel_limits_g4x_single_channel_lvds;
 368         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 369                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 370                 limit = &intel_limits_g4x_hdmi;
 371         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 372                 limit = &intel_limits_g4x_sdvo;
 373         } else /* The option is for other outputs */
 374                 limit = &intel_limits_i9xx_sdvo;
 375
 376         return limit;
 377 }
 378
 379 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 380 {
 381         struct drm_device *dev = crtc->dev;
 382         const intel_limit_t *limit;
 383
 384         if (HAS_PCH_SPLIT(dev))
 385                 limit = intel_ironlake_limit(crtc, refclk);
 386         else if (IS_G4X(dev)) {
 387                 limit = intel_g4x_limit(crtc);
 388         } else if (IS_PINEVIEW(dev)) {
 389                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 390                         limit = &intel_limits_pineview_lvds;
 391                 else
 392                         limit = &intel_limits_pineview_sdvo;
 393         } else if (IS_VALLEYVIEW(dev)) {
 394                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
 395                         limit = &intel_limits_vlv_dac;
 396                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
 397                         limit = &intel_limits_vlv_hdmi;
 398                 else
 399                         limit = &intel_limits_vlv_dp;
 400         } else if (!IS_GEN2(dev)) {
 401                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 402                         limit = &intel_limits_i9xx_lvds;
 403                 else
 404                         limit = &intel_limits_i9xx_sdvo;
 405         } else {
 406                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 407                         limit = &intel_limits_i8xx_lvds;
 408                 else
 409                         limit = &intel_limits_i8xx_dvo;
 410         }
 411         return limit;
 412 }
 413
 414 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 415 static void pineview_clock(int refclk, intel_clock_t *clock)
 416 {
 417         clock->m = clock->m2 + 2;
 418         clock->p = clock->p1 * clock->p2;
 419         clock->vco = refclk * clock->m / clock->n;
 420         clock->dot = clock->vco / clock->p;
 421 }
 422
 423 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 424 {
 425         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 426 }
 427
 428 static void i9xx_clock(int refclk, intel_clock_t *clock)
 429 {
 430         clock->m = i9xx_dpll_compute_m(clock);
 431         clock->p = clock->p1 * clock->p2;
 432         clock->vco = refclk * clock->m / (clock->n + 2);
 433         clock->dot = clock->vco / clock->p;
 434 }
 435
 436 /**
 437  * Returns whether any output on the specified pipe is of the specified type
 438  */
 439 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 440 {
 441         struct drm_device *dev = crtc->dev;
 442         struct intel_encoder *encoder;
 443
 444         for_each_encoder_on_crtc(dev, crtc, encoder)
 445                 if (encoder->type == type)
 446                         return true;
 447
 448         return false;
 449 }
 450
 451 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 452 /**
 453  * Returns whether the given set of divisors are valid for a given refclk with
 454  * the given connectors.
 455  */
 456
 457 static bool intel_PLL_is_valid(struct drm_device *dev,
 458                                const intel_limit_t *limit,
 459                                const intel_clock_t *clock)
 460 {
 461         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 462                 INTELPllInvalid("p1 out of range\n");
 463         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 464                 INTELPllInvalid("p out of range\n");
 465         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 466                 INTELPllInvalid("m2 out of range\n");
 467         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 468                 INTELPllInvalid("m1 out of range\n");
 469         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 470                 INTELPllInvalid("m1 <= m2\n");
 471         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 472                 INTELPllInvalid("m out of range\n");
 473         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 474                 INTELPllInvalid("n out of range\n");
 475         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 476                 INTELPllInvalid("vco out of range\n");
 477         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 478          * connector, etc., rather than just a single range.
 479          */
 480         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 481                 INTELPllInvalid("dot out of range\n");
 482
 483         return true;
 484 }
 485
 486 static bool
 487 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 488                     int target, int refclk, intel_clock_t *match_clock,
 489                     intel_clock_t *best_clock)
 490 {
 491         struct drm_device *dev = crtc->dev;
 492         intel_clock_t clock;
 493         int err = target;
 494
 495         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 496                 /*
 497                  * For LVDS just rely on its current settings for dual-channel.
 498                  * We haven't figured out how to reliably set up different
 499                  * single/dual channel state, if we even can.
 500                  */
 501                 if (intel_is_dual_link_lvds(dev))
 502                         clock.p2 = limit->p2.p2_fast;
 503                 else
 504                         clock.p2 = limit->p2.p2_slow;
 505         } else {
 506                 if (target < limit->p2.dot_limit)
 507                         clock.p2 = limit->p2.p2_slow;
 508                 else
 509                         clock.p2 = limit->p2.p2_fast;
 510         }
 511
 512         memset(best_clock, 0, sizeof(*best_clock));
 513
 514         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 515              clock.m1++) {
 516                 for (clock.m2 = limit->m2.min;
 517                      clock.m2 <= limit->m2.max; clock.m2++) {
 518                         if (clock.m2 >= clock.m1)
 519                                 break;
 520                         for (clock.n = limit->n.min;
 521                              clock.n <= limit->n.max; clock.n++) {
 522                                 for (clock.p1 = limit->p1.min;
 523                                         clock.p1 <= limit->p1.max; clock.p1++) {
 524                                         int this_err;
 525
 526                                         i9xx_clock(refclk, &clock);
 527                                         if (!intel_PLL_is_valid(dev, limit,
 528                                                                 &clock))
 529                                                 continue;
 530                                         if (match_clock &&
 531                                             clock.p != match_clock->p)
 532                                                 continue;
 533
 534                                         this_err = abs(clock.dot - target);
 535                                         if (this_err < err) {
 536                                                 *best_clock = clock;
 537                                                 err = this_err;
 538                                         }
 539                                 }
 540                         }
 541                 }
 542         }
 543
 544         return (err != target);
 545 }
 546
 547 static bool
 548 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 549                    int target, int refclk, intel_clock_t *match_clock,
 550                    intel_clock_t *best_clock)
 551 {
 552         struct drm_device *dev = crtc->dev;
 553         intel_clock_t clock;
 554         int err = target;
 555
 556         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 557                 /*
 558                  * For LVDS just rely on its current settings for dual-channel.
 559                  * We haven't figured out how to reliably set up different
 560                  * single/dual channel state, if we even can.
 561                  */
 562                 if (intel_is_dual_link_lvds(dev))
 563                         clock.p2 = limit->p2.p2_fast;
 564                 else
 565                         clock.p2 = limit->p2.p2_slow;
 566         } else {
 567                 if (target < limit->p2.dot_limit)
 568                         clock.p2 = limit->p2.p2_slow;
 569                 else
 570                         clock.p2 = limit->p2.p2_fast;
 571         }
 572
 573         memset(best_clock, 0, sizeof(*best_clock));
 574
 575         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 576              clock.m1++) {
 577                 for (clock.m2 = limit->m2.min;
 578                      clock.m2 <= limit->m2.max; clock.m2++) {
 579                         for (clock.n = limit->n.min;
 580                              clock.n <= limit->n.max; clock.n++) {
 581                                 for (clock.p1 = limit->p1.min;
 582                                         clock.p1 <= limit->p1.max; clock.p1++) {
 583                                         int this_err;
 584
 585                                         pineview_clock(refclk, &clock);
 586                                         if (!intel_PLL_is_valid(dev, limit,
 587                                                                 &clock))
 588                                                 continue;
 589                                         if (match_clock &&
 590                                             clock.p != match_clock->p)
 591                                                 continue;
 592
 593                                         this_err = abs(clock.dot - target);
 594                                         if (this_err < err) {
 595                                                 *best_clock = clock;
 596                                                 err = this_err;
 597                                         }
 598                                 }
 599                         }
 600                 }
 601         }
 602
 603         return (err != target);
 604 }
 605
 606 static bool
 607 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 608                    int target, int refclk, intel_clock_t *match_clock,
 609                    intel_clock_t *best_clock)
 610 {
 611         struct drm_device *dev = crtc->dev;
 612         intel_clock_t clock;
 613         int max_n;
 614         bool found;
 615         /* approximately equals target * 0.00585 */
 616         int err_most = (target >> 8) + (target >> 9);
 617         found = false;
 618
 619         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 620                 if (intel_is_dual_link_lvds(dev))
 621                         clock.p2 = limit->p2.p2_fast;
 622                 else
 623                         clock.p2 = limit->p2.p2_slow;
 624         } else {
 625                 if (target < limit->p2.dot_limit)
 626                         clock.p2 = limit->p2.p2_slow;
 627                 else
 628                         clock.p2 = limit->p2.p2_fast;
 629         }
 630
 631         memset(best_clock, 0, sizeof(*best_clock));
 632         max_n = limit->n.max;
 633         /* based on hardware requirement, prefer smaller n to precision */
 634         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 635                 /* based on hardware requirement, prefere larger m1,m2 */
 636                 for (clock.m1 = limit->m1.max;
 637                      clock.m1 >= limit->m1.min; clock.m1--) {
 638                         for (clock.m2 = limit->m2.max;
 639                              clock.m2 >= limit->m2.min; clock.m2--) {
 640                                 for (clock.p1 = limit->p1.max;
 641                                      clock.p1 >= limit->p1.min; clock.p1--) {
 642                                         int this_err;
 643
 644                                         i9xx_clock(refclk, &clock);
 645                                         if (!intel_PLL_is_valid(dev, limit,
 646                                                                 &clock))
 647                                                 continue;
 648
 649                                         this_err = abs(clock.dot - target);
 650                                         if (this_err < err_most) {
 651                                                 *best_clock = clock;
 652                                                 err_most = this_err;
 653                                                 max_n = clock.n;
 654                                                 found = true;
 655                                         }
 656                                 }
 657                         }
 658                 }
 659         }
 660         return found;
 661 }
 662
 663 static bool
 664 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 665                    int target, int refclk, intel_clock_t *match_clock,
 666                    intel_clock_t *best_clock)
 667 {
 668         u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
 669         u32 m, n, fastclk;
 670         u32 updrate, minupdate, fracbits, p;
 671         unsigned long bestppm, ppm, absppm;
 672         int dotclk, flag;
 673
 674         flag = 0;
 675         dotclk = target * 1000;
 676         bestppm = 1000000;
 677         ppm = absppm = 0;
 678         fastclk = dotclk / (2*100);
 679         updrate = 0;
 680         minupdate = 19200;
 681         fracbits = 1;
 682         n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
 683         bestm1 = bestm2 = bestp1 = bestp2 = 0;
 684
 685         /* based on hardware requirement, prefer smaller n to precision */
 686         for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
 687                 updrate = refclk / n;
 688                 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
 689                         for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
 690                                 if (p2 > 10)
 691                                         p2 = p2 - 1;
 692                                 p = p1 * p2;
 693                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 694                                 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
 695                                         m2 = (((2*(fastclk * p * n / m1 )) +
 696                                                refclk) / (2*refclk));
 697                                         m = m1 * m2;
 698                                         vco = updrate * m;
 699                                         if (vco >= limit->vco.min && vco < limit->vco.max) {
 700                                                 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
 701                                                 absppm = (ppm > 0) ? ppm : (-ppm);
 702                                                 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
 703                                                         bestppm = 0;
 704                                                         flag = 1;
 705                                                 }
 706                                                 if (absppm < bestppm - 10) {
 707                                                         bestppm = absppm;
 708                                                         flag = 1;
 709                                                 }
 710                                                 if (flag) {
 711                                                         bestn = n;
 712                                                         bestm1 = m1;
 713                                                         bestm2 = m2;
 714                                                         bestp1 = p1;
 715                                                         bestp2 = p2;
 716                                                         flag = 0;
 717                                                 }
 718                                         }
 719                                 }
 720                         }
 721                 }
 722         }
 723         best_clock->n = bestn;
 724         best_clock->m1 = bestm1;
 725         best_clock->m2 = bestm2;
 726         best_clock->p1 = bestp1;
 727         best_clock->p2 = bestp2;
 728
 729         return true;
 730 }
 731
 732 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 733                                              enum pipe pipe)
 734 {
 735         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 736         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 737
 738         return intel_crtc->config.cpu_transcoder;
 739 }
 740
 741 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 742 {
 743         struct drm_i915_private *dev_priv = dev->dev_private;
 744         u32 frame, frame_reg = PIPEFRAME(pipe);
 745
 746         frame = I915_READ(frame_reg);
 747
 748         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 749                 DRM_DEBUG_KMS("vblank wait timed out\n");
 750 }
 751
 752 /**
 753  * intel_wait_for_vblank - wait for vblank on a given pipe
 754  * @dev: drm device
 755  * @pipe: pipe to wait for
 756  *
 757  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 758  * mode setting code.
 759  */
 760 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 761 {
 762         struct drm_i915_private *dev_priv = dev->dev_private;
 763         int pipestat_reg = PIPESTAT(pipe);
 764
 765         if (INTEL_INFO(dev)->gen >= 5) {
 766                 ironlake_wait_for_vblank(dev, pipe);
 767                 return;
 768         }
 769
 770         /* Clear existing vblank status. Note this will clear any other
 771          * sticky status fields as well.
 772          *
 773          * This races with i915_driver_irq_handler() with the result
 774          * that either function could miss a vblank event.  Here it is not
 775          * fatal, as we will either wait upon the next vblank interrupt or
 776          * timeout.  Generally speaking intel_wait_for_vblank() is only
 777          * called during modeset at which time the GPU should be idle and
 778          * should *not* be performing page flips and thus not waiting on
 779          * vblanks...
 780          * Currently, the result of us stealing a vblank from the irq
 781          * handler is that a single frame will be skipped during swapbuffers.
 782          */
 783         I915_WRITE(pipestat_reg,
 784                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 785
 786         /* Wait for vblank interrupt bit to set */
 787         if (wait_for(I915_READ(pipestat_reg) &
 788                      PIPE_VBLANK_INTERRUPT_STATUS,
 789                      50))
 790                 DRM_DEBUG_KMS("vblank wait timed out\n");
 791 }
 792
 793 /*
 794  * intel_wait_for_pipe_off - wait for pipe to turn off
 795  * @dev: drm device
 796  * @pipe: pipe to wait for
 797  *
 798  * After disabling a pipe, we can't wait for vblank in the usual way,
 799  * spinning on the vblank interrupt status bit, since we won't actually
 800  * see an interrupt when the pipe is disabled.
 801  *
 802  * On Gen4 and above:
 803  *   wait for the pipe register state bit to turn off
 804  *
 805  * Otherwise:
 806  *   wait for the display line value to settle (it usually
 807  *   ends up stopping at the start of the next frame).
 808  *
 809  */
 810 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 811 {
 812         struct drm_i915_private *dev_priv = dev->dev_private;
 813         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 814                                                                       pipe);
 815
 816         if (INTEL_INFO(dev)->gen >= 4) {
 817                 int reg = PIPECONF(cpu_transcoder);
 818
 819                 /* Wait for the Pipe State to go off */
 820                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 821                              100))
 822                         WARN(1, "pipe_off wait timed out\n");
 823         } else {
 824                 u32 last_line, line_mask;
 825                 int reg = PIPEDSL(pipe);
 826                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
 827
 828                 if (IS_GEN2(dev))
 829                         line_mask = DSL_LINEMASK_GEN2;
 830                 else
 831                         line_mask = DSL_LINEMASK_GEN3;
 832
 833                 /* Wait for the display line to settle */
 834                 do {
 835                         last_line = I915_READ(reg) & line_mask;
 836                         mdelay(5);
 837                 } while (((I915_READ(reg) & line_mask) != last_line) &&
 838                          time_after(timeout, jiffies));
 839                 if (time_after(jiffies, timeout))
 840                         WARN(1, "pipe_off wait timed out\n");
 841         }
 842 }
 843
 844 /*
 845  * ibx_digital_port_connected - is the specified port connected?
 846  * @dev_priv: i915 private structure
 847  * @port: the port to test
 848  *
 849  * Returns true if @port is connected, false otherwise.
 850  */
 851 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 852                                 struct intel_digital_port *port)
 853 {
 854         u32 bit;
 855
 856         if (HAS_PCH_IBX(dev_priv->dev)) {
 857                 switch(port->port) {
 858                 case PORT_B:
 859                         bit = SDE_PORTB_HOTPLUG;
 860                         break;
 861                 case PORT_C:
 862                         bit = SDE_PORTC_HOTPLUG;
 863                         break;
 864                 case PORT_D:
 865                         bit = SDE_PORTD_HOTPLUG;
 866                         break;
 867                 default:
 868                         return true;
 869                 }
 870         } else {
 871                 switch(port->port) {
 872                 case PORT_B:
 873                         bit = SDE_PORTB_HOTPLUG_CPT;
 874                         break;
 875                 case PORT_C:
 876                         bit = SDE_PORTC_HOTPLUG_CPT;
 877                         break;
 878                 case PORT_D:
 879                         bit = SDE_PORTD_HOTPLUG_CPT;
 880                         break;
 881                 default:
 882                         return true;
 883                 }
 884         }
 885
 886         return I915_READ(SDEISR) & bit;
 887 }
 888
 889 static const char *state_string(bool enabled)
 890 {
 891         return enabled ? "on" : "off";
 892 }
 893
 894 /* Only for pre-ILK configs */
 895 static void assert_pll(struct drm_i915_private *dev_priv,
 896                        enum pipe pipe, bool state)
 897 {
 898         int reg;
 899         u32 val;
 900         bool cur_state;
 901
 902         reg = DPLL(pipe);
 903         val = I915_READ(reg);
 904         cur_state = !!(val & DPLL_VCO_ENABLE);
 905         WARN(cur_state != state,
 906              "PLL state assertion failure (expected %s, current %s)\n",
 907              state_string(state), state_string(cur_state));
 908 }
 909 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
 910 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
 911
 912 static struct intel_shared_dpll *
 913 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
 914 {
 915         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 916
 917         if (crtc->config.shared_dpll < 0)
 918                 return NULL;
 919
 920         return &dev_priv->shared_dplls[crtc->config.shared_dpll];
 921 }
 922
 923 /* For ILK+ */
 924 static void assert_shared_dpll(struct drm_i915_private *dev_priv,
 925                                struct intel_shared_dpll *pll,
 926                                bool state)
 927 {
 928         bool cur_state;
 929         struct intel_dpll_hw_state hw_state;
 930
 931         if (HAS_PCH_LPT(dev_priv->dev)) {
 932                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
 933                 return;
 934         }
 935
 936         if (WARN (!pll,
 937                   "asserting DPLL %s with no DPLL\n", state_string(state)))
 938                 return;
 939
 940         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
 941         WARN(cur_state != state,
 942              "%s assertion failure (expected %s, current %s)\n",
 943              pll->name, state_string(state), state_string(cur_state));
 944 }
 945 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
 946 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
 947
 948 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 949                           enum pipe pipe, bool state)
 950 {
 951         int reg;
 952         u32 val;
 953         bool cur_state;
 954         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 955                                                                       pipe);
 956
 957         if (HAS_DDI(dev_priv->dev)) {
 958                 /* DDI does not have a specific FDI_TX register */
 959                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
 960                 val = I915_READ(reg);
 961                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
 962         } else {
 963                 reg = FDI_TX_CTL(pipe);
 964                 val = I915_READ(reg);
 965                 cur_state = !!(val & FDI_TX_ENABLE);
 966         }
 967         WARN(cur_state != state,
 968              "FDI TX state assertion failure (expected %s, current %s)\n",
 969              state_string(state), state_string(cur_state));
 970 }
 971 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
 972 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
 973
 974 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
 975                           enum pipe pipe, bool state)
 976 {
 977         int reg;
 978         u32 val;
 979         bool cur_state;
 980
 981         reg = FDI_RX_CTL(pipe);
 982         val = I915_READ(reg);
 983         cur_state = !!(val & FDI_RX_ENABLE);
 984         WARN(cur_state != state,
 985              "FDI RX state assertion failure (expected %s, current %s)\n",
 986              state_string(state), state_string(cur_state));
 987 }
 988 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
 989 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
 990
 991 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
 992                                       enum pipe pipe)
 993 {
 994         int reg;
 995         u32 val;
 996
 997         /* ILK FDI PLL is always enabled */
 998         if (dev_priv->info->gen == 5)
 999                 return;
1000
1001         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1002         if (HAS_DDI(dev_priv->dev))
1003                 return;
1004
1005         reg = FDI_TX_CTL(pipe);
1006         val = I915_READ(reg);
1007         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1008 }
1009
1010 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1011                                       enum pipe pipe)
1012 {
1013         int reg;
1014         u32 val;
1015
1016         reg = FDI_RX_CTL(pipe);
1017         val = I915_READ(reg);
1018         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1019 }
1020
1021 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1022                                   enum pipe pipe)
1023 {
1024         int pp_reg, lvds_reg;
1025         u32 val;
1026         enum pipe panel_pipe = PIPE_A;
1027         bool locked = true;
1028
1029         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1030                 pp_reg = PCH_PP_CONTROL;
1031                 lvds_reg = PCH_LVDS;
1032         } else {
1033                 pp_reg = PP_CONTROL;
1034                 lvds_reg = LVDS;
1035         }
1036
1037         val = I915_READ(pp_reg);
1038         if (!(val & PANEL_POWER_ON) ||
1039             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1040                 locked = false;
1041
1042         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1043                 panel_pipe = PIPE_B;
1044
1045         WARN(panel_pipe == pipe && locked,
1046              "panel assertion failure, pipe %c regs locked\n",
1047              pipe_name(pipe));
1048 }
1049
1050 void assert_pipe(struct drm_i915_private *dev_priv,
1051                  enum pipe pipe, bool state)
1052 {
1053         int reg;
1054         u32 val;
1055         bool cur_state;
1056         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1057                                                                       pipe);
1058
1059         /* if we need the pipe A quirk it must be always on */
1060         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1061                 state = true;
1062
1063         if (!intel_display_power_enabled(dev_priv->dev,
1064                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1065                 cur_state = false;
1066         } else {
1067                 reg = PIPECONF(cpu_transcoder);
1068                 val = I915_READ(reg);
1069                 cur_state = !!(val & PIPECONF_ENABLE);
1070         }
1071
1072         WARN(cur_state != state,
1073              "pipe %c assertion failure (expected %s, current %s)\n",
1074              pipe_name(pipe), state_string(state), state_string(cur_state));
1075 }
1076
1077 static void assert_plane(struct drm_i915_private *dev_priv,
1078                          enum plane plane, bool state)
1079 {
1080         int reg;
1081         u32 val;
1082         bool cur_state;
1083
1084         reg = DSPCNTR(plane);
1085         val = I915_READ(reg);
1086         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1087         WARN(cur_state != state,
1088              "plane %c assertion failure (expected %s, current %s)\n",
1089              plane_name(plane), state_string(state), state_string(cur_state));
1090 }
1091
1092 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1093 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1094
1095 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1096                                    enum pipe pipe)
1097 {
1098         struct drm_device *dev = dev_priv->dev;
1099         int reg, i;
1100         u32 val;
1101         int cur_pipe;
1102
1103         /* Primary planes are fixed to pipes on gen4+ */
1104         if (INTEL_INFO(dev)->gen >= 4) {
1105                 reg = DSPCNTR(pipe);
1106                 val = I915_READ(reg);
1107                 WARN((val & DISPLAY_PLANE_ENABLE),
1108                      "plane %c assertion failure, should be disabled but not\n",
1109                      plane_name(pipe));
1110                 return;
1111         }
1112
1113         /* Need to check both planes against the pipe */
1114         for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
1115                 reg = DSPCNTR(i);
1116                 val = I915_READ(reg);
1117                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1118                         DISPPLANE_SEL_PIPE_SHIFT;
1119                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1120                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1121                      plane_name(i), pipe_name(pipe));
1122         }
1123 }
1124
1125 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1126                                     enum pipe pipe)
1127 {
1128         struct drm_device *dev = dev_priv->dev;
1129         int reg, i;
1130         u32 val;
1131
1132         if (IS_VALLEYVIEW(dev)) {
1133                 for (i = 0; i < dev_priv->num_plane; i++) {
1134                         reg = SPCNTR(pipe, i);
1135                         val = I915_READ(reg);
1136                         WARN((val & SP_ENABLE),
1137                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1138                              sprite_name(pipe, i), pipe_name(pipe));
1139                 }
1140         } else if (INTEL_INFO(dev)->gen >= 7) {
1141                 reg = SPRCTL(pipe);
1142                 val = I915_READ(reg);
1143                 WARN((val & SPRITE_ENABLE),
1144                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1145                      plane_name(pipe), pipe_name(pipe));
1146         } else if (INTEL_INFO(dev)->gen >= 5) {
1147                 reg = DVSCNTR(pipe);
1148                 val = I915_READ(reg);
1149                 WARN((val & DVS_ENABLE),
1150                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1151                      plane_name(pipe), pipe_name(pipe));
1152         }
1153 }
1154
1155 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1156 {
1157         u32 val;
1158         bool enabled;
1159
1160         if (HAS_PCH_LPT(dev_priv->dev)) {
1161                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1162                 return;
1163         }
1164
1165         val = I915_READ(PCH_DREF_CONTROL);
1166         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1167                             DREF_SUPERSPREAD_SOURCE_MASK));
1168         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1169 }
1170
1171 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1172                                            enum pipe pipe)
1173 {
1174         int reg;
1175         u32 val;
1176         bool enabled;
1177
1178         reg = PCH_TRANSCONF(pipe);
1179         val = I915_READ(reg);
1180         enabled = !!(val & TRANS_ENABLE);
1181         WARN(enabled,
1182              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1183              pipe_name(pipe));
1184 }
1185
1186 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1187                             enum pipe pipe, u32 port_sel, u32 val)
1188 {
1189         if ((val & DP_PORT_EN) == 0)
1190                 return false;
1191
1192         if (HAS_PCH_CPT(dev_priv->dev)) {
1193                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1194                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1195                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1196                         return false;
1197         } else {
1198                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1199                         return false;
1200         }
1201         return true;
1202 }
1203
1204 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1205                               enum pipe pipe, u32 val)
1206 {
1207         if ((val & SDVO_ENABLE) == 0)
1208                 return false;
1209
1210         if (HAS_PCH_CPT(dev_priv->dev)) {
1211                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1212                         return false;
1213         } else {
1214                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1215                         return false;
1216         }
1217         return true;
1218 }
1219
1220 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1221                               enum pipe pipe, u32 val)
1222 {
1223         if ((val & LVDS_PORT_EN) == 0)
1224                 return false;
1225
1226         if (HAS_PCH_CPT(dev_priv->dev)) {
1227                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1228                         return false;
1229         } else {
1230                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1231                         return false;
1232         }
1233         return true;
1234 }
1235
1236 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1237                               enum pipe pipe, u32 val)
1238 {
1239         if ((val & ADPA_DAC_ENABLE) == 0)
1240                 return false;
1241         if (HAS_PCH_CPT(dev_priv->dev)) {
1242                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1243                         return false;
1244         } else {
1245                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1246                         return false;
1247         }
1248         return true;
1249 }
1250
1251 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1252                                    enum pipe pipe, int reg, u32 port_sel)
1253 {
1254         u32 val = I915_READ(reg);
1255         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1256              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1257              reg, pipe_name(pipe));
1258
1259         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1260              && (val & DP_PIPEB_SELECT),
1261              "IBX PCH dp port still using transcoder B\n");
1262 }
1263
1264 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1265                                      enum pipe pipe, int reg)
1266 {
1267         u32 val = I915_READ(reg);
1268         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1269              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1270              reg, pipe_name(pipe));
1271
1272         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1273              && (val & SDVO_PIPE_B_SELECT),
1274              "IBX PCH hdmi port still using transcoder B\n");
1275 }
1276
1277 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1278                                       enum pipe pipe)
1279 {
1280         int reg;
1281         u32 val;
1282
1283         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1284         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1285         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1286
1287         reg = PCH_ADPA;
1288         val = I915_READ(reg);
1289         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1290              "PCH VGA enabled on transcoder %c, should be disabled\n",
1291              pipe_name(pipe));
1292
1293         reg = PCH_LVDS;
1294         val = I915_READ(reg);
1295         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1296              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1297              pipe_name(pipe));
1298
1299         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1300         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1301         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1302 }
1303
1304 /**
1305  * intel_enable_pll - enable a PLL
1306  * @dev_priv: i915 private structure
1307  * @pipe: pipe PLL to enable
1308  *
1309  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1310  * make sure the PLL reg is writable first though, since the panel write
1311  * protect mechanism may be enabled.
1312  *
1313  * Note!  This is for pre-ILK only.
1314  *
1315  * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1316  */
1317 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1318 {
1319         int reg;
1320         u32 val;
1321
1322         assert_pipe_disabled(dev_priv, pipe);
1323
1324         /* No really, not for ILK+ */
1325         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1326
1327         /* PLL is protected by panel, make sure we can write it */
1328         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1329                 assert_panel_unlocked(dev_priv, pipe);
1330
1331         reg = DPLL(pipe);
1332         val = I915_READ(reg);
1333         val |= DPLL_VCO_ENABLE;
1334
1335         /* We do this three times for luck */
1336         I915_WRITE(reg, val);
1337         POSTING_READ(reg);
1338         udelay(150); /* wait for warmup */
1339         I915_WRITE(reg, val);
1340         POSTING_READ(reg);
1341         udelay(150); /* wait for warmup */
1342         I915_WRITE(reg, val);
1343         POSTING_READ(reg);
1344         udelay(150); /* wait for warmup */
1345 }
1346
1347 /**
1348  * intel_disable_pll - disable a PLL
1349  * @dev_priv: i915 private structure
1350  * @pipe: pipe PLL to disable
1351  *
1352  * Disable the PLL for @pipe, making sure the pipe is off first.
1353  *
1354  * Note!  This is for pre-ILK only.
1355  */
1356 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1357 {
1358         int reg;
1359         u32 val;
1360
1361         /* Don't disable pipe A or pipe A PLLs if needed */
1362         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1363                 return;
1364
1365         /* Make sure the pipe isn't still relying on us */
1366         assert_pipe_disabled(dev_priv, pipe);
1367
1368         reg = DPLL(pipe);
1369         val = I915_READ(reg);
1370         val &= ~DPLL_VCO_ENABLE;
1371         I915_WRITE(reg, val);
1372         POSTING_READ(reg);
1373 }
1374
1375 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1376 {
1377         u32 port_mask;
1378
1379         if (!port)
1380                 port_mask = DPLL_PORTB_READY_MASK;
1381         else
1382                 port_mask = DPLL_PORTC_READY_MASK;
1383
1384         if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1385                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1386                      'B' + port, I915_READ(DPLL(0)));
1387 }
1388
1389 /**
1390  * ironlake_enable_shared_dpll - enable PCH PLL
1391  * @dev_priv: i915 private structure
1392  * @pipe: pipe PLL to enable
1393  *
1394  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1395  * drives the transcoder clock.
1396  */
1397 static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
1398 {
1399         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1400         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1401
1402         /* PCH PLLs only available on ILK, SNB and IVB */
1403         BUG_ON(dev_priv->info->gen < 5);
1404         if (WARN_ON(pll == NULL))
1405                 return;
1406
1407         if (WARN_ON(pll->refcount == 0))
1408                 return;
1409
1410         DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1411                       pll->name, pll->active, pll->on,
1412                       crtc->base.base.id);
1413
1414         if (pll->active++) {
1415                 WARN_ON(!pll->on);
1416                 assert_shared_dpll_enabled(dev_priv, pll);
1417                 return;
1418         }
1419         WARN_ON(pll->on);
1420
1421         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1422         pll->enable(dev_priv, pll);
1423         pll->on = true;
1424 }
1425
1426 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1427 {
1428         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1429         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1430
1431         /* PCH only available on ILK+ */
1432         BUG_ON(dev_priv->info->gen < 5);
1433         if (WARN_ON(pll == NULL))
1434                return;
1435
1436         if (WARN_ON(pll->refcount == 0))
1437                 return;
1438
1439         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1440                       pll->name, pll->active, pll->on,
1441                       crtc->base.base.id);
1442
1443         if (WARN_ON(pll->active == 0)) {
1444                 assert_shared_dpll_disabled(dev_priv, pll);
1445                 return;
1446         }
1447
1448         assert_shared_dpll_enabled(dev_priv, pll);
1449         WARN_ON(!pll->on);
1450         if (--pll->active)
1451                 return;
1452
1453         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1454         pll->disable(dev_priv, pll);
1455         pll->on = false;
1456 }
1457
1458 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1459                                            enum pipe pipe)
1460 {
1461         struct drm_device *dev = dev_priv->dev;
1462         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1463         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1464         uint32_t reg, val, pipeconf_val;
1465
1466         /* PCH only available on ILK+ */
1467         BUG_ON(dev_priv->info->gen < 5);
1468
1469         /* Make sure PCH DPLL is enabled */
1470         assert_shared_dpll_enabled(dev_priv,
1471                                    intel_crtc_to_shared_dpll(intel_crtc));
1472
1473         /* FDI must be feeding us bits for PCH ports */
1474         assert_fdi_tx_enabled(dev_priv, pipe);
1475         assert_fdi_rx_enabled(dev_priv, pipe);
1476
1477         if (HAS_PCH_CPT(dev)) {
1478                 /* Workaround: Set the timing override bit before enabling the
1479                  * pch transcoder. */
1480                 reg = TRANS_CHICKEN2(pipe);
1481                 val = I915_READ(reg);
1482                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1483                 I915_WRITE(reg, val);
1484         }
1485
1486         reg = PCH_TRANSCONF(pipe);
1487         val = I915_READ(reg);
1488         pipeconf_val = I915_READ(PIPECONF(pipe));
1489
1490         if (HAS_PCH_IBX(dev_priv->dev)) {
1491                 /*
1492                  * make the BPC in transcoder be consistent with
1493                  * that in pipeconf reg.
1494                  */
1495                 val &= ~PIPECONF_BPC_MASK;
1496                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1497         }
1498
1499         val &= ~TRANS_INTERLACE_MASK;
1500         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1501                 if (HAS_PCH_IBX(dev_priv->dev) &&
1502                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1503                         val |= TRANS_LEGACY_INTERLACED_ILK;
1504                 else
1505                         val |= TRANS_INTERLACED;
1506         else
1507                 val |= TRANS_PROGRESSIVE;
1508
1509         I915_WRITE(reg, val | TRANS_ENABLE);
1510         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1511                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1512 }
1513
1514 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1515                                       enum transcoder cpu_transcoder)
1516 {
1517         u32 val, pipeconf_val;
1518
1519         /* PCH only available on ILK+ */
1520         BUG_ON(dev_priv->info->gen < 5);
1521
1522         /* FDI must be feeding us bits for PCH ports */
1523         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1524         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1525
1526         /* Workaround: set timing override bit. */
1527         val = I915_READ(_TRANSA_CHICKEN2);
1528         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1529         I915_WRITE(_TRANSA_CHICKEN2, val);
1530
1531         val = TRANS_ENABLE;
1532         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1533
1534         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1535             PIPECONF_INTERLACED_ILK)
1536                 val |= TRANS_INTERLACED;
1537         else
1538                 val |= TRANS_PROGRESSIVE;
1539
1540         I915_WRITE(LPT_TRANSCONF, val);
1541         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1542                 DRM_ERROR("Failed to enable PCH transcoder\n");
1543 }
1544
1545 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1546                                             enum pipe pipe)
1547 {
1548         struct drm_device *dev = dev_priv->dev;
1549         uint32_t reg, val;
1550
1551         /* FDI relies on the transcoder */
1552         assert_fdi_tx_disabled(dev_priv, pipe);
1553         assert_fdi_rx_disabled(dev_priv, pipe);
1554
1555         /* Ports must be off as well */
1556         assert_pch_ports_disabled(dev_priv, pipe);
1557
1558         reg = PCH_TRANSCONF(pipe);
1559         val = I915_READ(reg);
1560         val &= ~TRANS_ENABLE;
1561         I915_WRITE(reg, val);
1562         /* wait for PCH transcoder off, transcoder state */
1563         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1564                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1565
1566         if (!HAS_PCH_IBX(dev)) {
1567                 /* Workaround: Clear the timing override chicken bit again. */
1568                 reg = TRANS_CHICKEN2(pipe);
1569                 val = I915_READ(reg);
1570                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1571                 I915_WRITE(reg, val);
1572         }
1573 }
1574
1575 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1576 {
1577         u32 val;
1578
1579         val = I915_READ(LPT_TRANSCONF);
1580         val &= ~TRANS_ENABLE;
1581         I915_WRITE(LPT_TRANSCONF, val);
1582         /* wait for PCH transcoder off, transcoder state */
1583         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1584                 DRM_ERROR("Failed to disable PCH transcoder\n");
1585
1586         /* Workaround: clear timing override bit. */
1587         val = I915_READ(_TRANSA_CHICKEN2);
1588         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1589         I915_WRITE(_TRANSA_CHICKEN2, val);
1590 }
1591
1592 /**
1593  * intel_enable_pipe - enable a pipe, asserting requirements
1594  * @dev_priv: i915 private structure
1595  * @pipe: pipe to enable
1596  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1597  *
1598  * Enable @pipe, making sure that various hardware specific requirements
1599  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1600  *
1601  * @pipe should be %PIPE_A or %PIPE_B.
1602  *
1603  * Will wait until the pipe is actually running (i.e. first vblank) before
1604  * returning.
1605  */
1606 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1607                               bool pch_port)
1608 {
1609         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1610                                                                       pipe);
1611         enum pipe pch_transcoder;
1612         int reg;
1613         u32 val;
1614
1615         assert_planes_disabled(dev_priv, pipe);
1616         assert_sprites_disabled(dev_priv, pipe);
1617
1618         if (HAS_PCH_LPT(dev_priv->dev))
1619                 pch_transcoder = TRANSCODER_A;
1620         else
1621                 pch_transcoder = pipe;
1622
1623         /*
1624          * A pipe without a PLL won't actually be able to drive bits from
1625          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1626          * need the check.
1627          */
1628         if (!HAS_PCH_SPLIT(dev_priv->dev))
1629                 assert_pll_enabled(dev_priv, pipe);
1630         else {
1631                 if (pch_port) {
1632                         /* if driving the PCH, we need FDI enabled */
1633                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1634                         assert_fdi_tx_pll_enabled(dev_priv,
1635                                                   (enum pipe) cpu_transcoder);
1636                 }
1637                 /* FIXME: assert CPU port conditions for SNB+ */
1638         }
1639
1640         reg = PIPECONF(cpu_transcoder);
1641         val = I915_READ(reg);
1642         if (val & PIPECONF_ENABLE)
1643                 return;
1644
1645         I915_WRITE(reg, val | PIPECONF_ENABLE);
1646         intel_wait_for_vblank(dev_priv->dev, pipe);
1647 }
1648
1649 /**
1650  * intel_disable_pipe - disable a pipe, asserting requirements
1651  * @dev_priv: i915 private structure
1652  * @pipe: pipe to disable
1653  *
1654  * Disable @pipe, making sure that various hardware specific requirements
1655  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1656  *
1657  * @pipe should be %PIPE_A or %PIPE_B.
1658  *
1659  * Will wait until the pipe has shut down before returning.
1660  */
1661 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1662                                enum pipe pipe)
1663 {
1664         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1665                                                                       pipe);
1666         int reg;
1667         u32 val;
1668
1669         /*
1670          * Make sure planes won't keep trying to pump pixels to us,
1671          * or we might hang the display.
1672          */
1673         assert_planes_disabled(dev_priv, pipe);
1674         assert_sprites_disabled(dev_priv, pipe);
1675
1676         /* Don't disable pipe A or pipe A PLLs if needed */
1677         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1678                 return;
1679
1680         reg = PIPECONF(cpu_transcoder);
1681         val = I915_READ(reg);
1682         if ((val & PIPECONF_ENABLE) == 0)
1683                 return;
1684
1685         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1686         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1687 }
1688
1689 /*
1690  * Plane regs are double buffered, going from enabled->disabled needs a
1691  * trigger in order to latch.  The display address reg provides this.
1692  */
1693 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1694                                       enum plane plane)
1695 {
1696         if (dev_priv->info->gen >= 4)
1697                 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1698         else
1699                 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1700 }
1701
1702 /**
1703  * intel_enable_plane - enable a display plane on a given pipe
1704  * @dev_priv: i915 private structure
1705  * @plane: plane to enable
1706  * @pipe: pipe being fed
1707  *
1708  * Enable @plane on @pipe, making sure that @pipe is running first.
1709  */
1710 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1711                                enum plane plane, enum pipe pipe)
1712 {
1713         int reg;
1714         u32 val;
1715
1716         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1717         assert_pipe_enabled(dev_priv, pipe);
1718
1719         reg = DSPCNTR(plane);
1720         val = I915_READ(reg);
1721         if (val & DISPLAY_PLANE_ENABLE)
1722                 return;
1723
1724         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1725         intel_flush_display_plane(dev_priv, plane);
1726         intel_wait_for_vblank(dev_priv->dev, pipe);
1727 }
1728
1729 /**
1730  * intel_disable_plane - disable a display plane
1731  * @dev_priv: i915 private structure
1732  * @plane: plane to disable
1733  * @pipe: pipe consuming the data
1734  *
1735  * Disable @plane; should be an independent operation.
1736  */
1737 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1738                                 enum plane plane, enum pipe pipe)
1739 {
1740         int reg;
1741         u32 val;
1742
1743         reg = DSPCNTR(plane);
1744         val = I915_READ(reg);
1745         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1746                 return;
1747
1748         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1749         intel_flush_display_plane(dev_priv, plane);
1750         intel_wait_for_vblank(dev_priv->dev, pipe);
1751 }
1752
1753 static bool need_vtd_wa(struct drm_device *dev)
1754 {
1755 #ifdef CONFIG_INTEL_IOMMU
1756         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1757                 return true;
1758 #endif
1759         return false;
1760 }
1761
1762 int
1763 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1764                            struct drm_i915_gem_object *obj,
1765                            struct intel_ring_buffer *pipelined)
1766 {
1767         struct drm_i915_private *dev_priv = dev->dev_private;
1768         u32 alignment;
1769         int ret;
1770
1771         switch (obj->tiling_mode) {
1772         case I915_TILING_NONE:
1773                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1774                         alignment = 128 * 1024;
1775                 else if (INTEL_INFO(dev)->gen >= 4)
1776                         alignment = 4 * 1024;
1777                 else
1778                         alignment = 64 * 1024;
1779                 break;
1780         case I915_TILING_X:
1781                 /* pin() will align the object as required by fence */
1782                 alignment = 0;
1783                 break;
1784         case I915_TILING_Y:
1785                 /* Despite that we check this in framebuffer_init userspace can
1786                  * screw us over and change the tiling after the fact. Only
1787                  * pinned buffers can't change their tiling. */
1788                 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
1789                 return -EINVAL;
1790         default:
1791                 BUG();
1792         }
1793
1794         /* Note that the w/a also requires 64 PTE of padding following the
1795          * bo. We currently fill all unused PTE with the shadow page and so
1796          * we should always have valid PTE following the scanout preventing
1797          * the VT-d warning.
1798          */
1799         if (need_vtd_wa(dev) && alignment < 256 * 1024)
1800                 alignment = 256 * 1024;
1801
1802         dev_priv->mm.interruptible = false;
1803         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1804         if (ret)
1805                 goto err_interruptible;
1806
1807         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1808          * fence, whereas 965+ only requires a fence if using
1809          * framebuffer compression.  For simplicity, we always install
1810          * a fence as the cost is not that onerous.
1811          */
1812         ret = i915_gem_object_get_fence(obj);
1813         if (ret)
1814                 goto err_unpin;
1815
1816         i915_gem_object_pin_fence(obj);
1817
1818         dev_priv->mm.interruptible = true;
1819         return 0;
1820
1821 err_unpin:
1822         i915_gem_object_unpin(obj);
1823 err_interruptible:
1824         dev_priv->mm.interruptible = true;
1825         return ret;
1826 }
1827
1828 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1829 {
1830         i915_gem_object_unpin_fence(obj);
1831         i915_gem_object_unpin(obj);
1832 }
1833
1834 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1835  * is assumed to be a power-of-two. */
1836 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1837                                              unsigned int tiling_mode,
1838                                              unsigned int cpp,
1839                                              unsigned int pitch)
1840 {
1841         if (tiling_mode != I915_TILING_NONE) {
1842                 unsigned int tile_rows, tiles;
1843
1844                 tile_rows = *y / 8;
1845                 *y %= 8;
1846
1847                 tiles = *x / (512/cpp);
1848                 *x %= 512/cpp;
1849
1850                 return tile_rows * pitch * 8 + tiles * 4096;
1851         } else {
1852                 unsigned int offset;
1853
1854                 offset = *y * pitch + *x * cpp;
1855                 *y = 0;
1856                 *x = (offset & 4095) / cpp;
1857                 return offset & -4096;
1858         }
1859 }
1860
1861 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1862                              int x, int y)
1863 {
1864         struct drm_device *dev = crtc->dev;
1865         struct drm_i915_private *dev_priv = dev->dev_private;
1866         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1867         struct intel_framebuffer *intel_fb;
1868         struct drm_i915_gem_object *obj;
1869         int plane = intel_crtc->plane;
1870         unsigned long linear_offset;
1871         u32 dspcntr;
1872         u32 reg;
1873
1874         switch (plane) {
1875         case 0:
1876         case 1:
1877                 break;
1878         default:
1879                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
1880                 return -EINVAL;
1881         }
1882
1883         intel_fb = to_intel_framebuffer(fb);
1884         obj = intel_fb->obj;
1885
1886         reg = DSPCNTR(plane);
1887         dspcntr = I915_READ(reg);
1888         /* Mask out pixel format bits in case we change it */
1889         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1890         switch (fb->pixel_format) {
1891         case DRM_FORMAT_C8:
1892                 dspcntr |= DISPPLANE_8BPP;
1893                 break;
1894         case DRM_FORMAT_XRGB1555:
1895         case DRM_FORMAT_ARGB1555:
1896                 dspcntr |= DISPPLANE_BGRX555;
1897                 break;
1898         case DRM_FORMAT_RGB565:
1899                 dspcntr |= DISPPLANE_BGRX565;
1900                 break;
1901         case DRM_FORMAT_XRGB8888:
1902         case DRM_FORMAT_ARGB8888:
1903                 dspcntr |= DISPPLANE_BGRX888;
1904                 break;
1905         case DRM_FORMAT_XBGR8888:
1906         case DRM_FORMAT_ABGR8888:
1907                 dspcntr |= DISPPLANE_RGBX888;
1908                 break;
1909         case DRM_FORMAT_XRGB2101010:
1910         case DRM_FORMAT_ARGB2101010:
1911                 dspcntr |= DISPPLANE_BGRX101010;
1912                 break;
1913         case DRM_FORMAT_XBGR2101010:
1914         case DRM_FORMAT_ABGR2101010:
1915                 dspcntr |= DISPPLANE_RGBX101010;
1916                 break;
1917         default:
1918                 BUG();
1919         }
1920
1921         if (INTEL_INFO(dev)->gen >= 4) {
1922                 if (obj->tiling_mode != I915_TILING_NONE)
1923                         dspcntr |= DISPPLANE_TILED;
1924                 else
1925                         dspcntr &= ~DISPPLANE_TILED;
1926         }
1927
1928         if (IS_G4X(dev))
1929                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1930
1931         I915_WRITE(reg, dspcntr);
1932
1933         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
1934
1935         if (INTEL_INFO(dev)->gen >= 4) {
1936                 intel_crtc->dspaddr_offset =
1937                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
1938                                                        fb->bits_per_pixel / 8,
1939                                                        fb->pitches[0]);
1940                 linear_offset -= intel_crtc->dspaddr_offset;
1941         } else {
1942                 intel_crtc->dspaddr_offset = linear_offset;
1943         }
1944
1945         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
1946                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
1947         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
1948         if (INTEL_INFO(dev)->gen >= 4) {
1949                 I915_MODIFY_DISPBASE(DSPSURF(plane),
1950                                      obj->gtt_offset + intel_crtc->dspaddr_offset);
1951                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1952                 I915_WRITE(DSPLINOFF(plane), linear_offset);
1953         } else
1954                 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
1955         POSTING_READ(reg);
1956
1957         return 0;
1958 }
1959
1960 static int ironlake_update_plane(struct drm_crtc *crtc,
1961                                  struct drm_framebuffer *fb, int x, int y)
1962 {
1963         struct drm_device *dev = crtc->dev;
1964         struct drm_i915_private *dev_priv = dev->dev_private;
1965         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1966         struct intel_framebuffer *intel_fb;
1967         struct drm_i915_gem_object *obj;
1968         int plane = intel_crtc->plane;
1969         unsigned long linear_offset;
1970         u32 dspcntr;
1971         u32 reg;
1972
1973         switch (plane) {
1974         case 0:
1975         case 1:
1976         case 2:
1977                 break;
1978         default:
1979                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
1980                 return -EINVAL;
1981         }
1982
1983         intel_fb = to_intel_framebuffer(fb);
1984         obj = intel_fb->obj;
1985
1986         reg = DSPCNTR(plane);
1987         dspcntr = I915_READ(reg);
1988         /* Mask out pixel format bits in case we change it */
1989         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1990         switch (fb->pixel_format) {
1991         case DRM_FORMAT_C8:
1992                 dspcntr |= DISPPLANE_8BPP;
1993                 break;
1994         case DRM_FORMAT_RGB565:
1995                 dspcntr |= DISPPLANE_BGRX565;
1996                 break;
1997         case DRM_FORMAT_XRGB8888:
1998         case DRM_FORMAT_ARGB8888:
1999                 dspcntr |= DISPPLANE_BGRX888;
2000                 break;
2001         case DRM_FORMAT_XBGR8888:
2002         case DRM_FORMAT_ABGR8888:
2003                 dspcntr |= DISPPLANE_RGBX888;
2004                 break;
2005         case DRM_FORMAT_XRGB2101010:
2006         case DRM_FORMAT_ARGB2101010:
2007                 dspcntr |= DISPPLANE_BGRX101010;
2008                 break;
2009         case DRM_FORMAT_XBGR2101010:
2010         case DRM_FORMAT_ABGR2101010:
2011                 dspcntr |= DISPPLANE_RGBX101010;
2012                 break;
2013         default:
2014                 BUG();
2015         }
2016
2017         if (obj->tiling_mode != I915_TILING_NONE)
2018                 dspcntr |= DISPPLANE_TILED;
2019         else
2020                 dspcntr &= ~DISPPLANE_TILED;
2021
2022         /* must disable */
2023         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2024
2025         I915_WRITE(reg, dspcntr);
2026
2027         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2028         intel_crtc->dspaddr_offset =
2029                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2030                                                fb->bits_per_pixel / 8,
2031                                                fb->pitches[0]);
2032         linear_offset -= intel_crtc->dspaddr_offset;
2033
2034         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2035                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2036         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2037         I915_MODIFY_DISPBASE(DSPSURF(plane),
2038                              obj->gtt_offset + intel_crtc->dspaddr_offset);
2039         if (IS_HASWELL(dev)) {
2040                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2041         } else {
2042                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2043                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2044         }
2045         POSTING_READ(reg);
2046
2047         return 0;
2048 }
2049
2050 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2051 static int
2052 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2053                            int x, int y, enum mode_set_atomic state)
2054 {
2055         struct drm_device *dev = crtc->dev;
2056         struct drm_i915_private *dev_priv = dev->dev_private;
2057
2058         if (dev_priv->display.disable_fbc)
2059                 dev_priv->display.disable_fbc(dev);
2060         intel_increase_pllclock(crtc);
2061
2062         return dev_priv->display.update_plane(crtc, fb, x, y);
2063 }
2064
2065 void intel_display_handle_reset(struct drm_device *dev)
2066 {
2067         struct drm_i915_private *dev_priv = dev->dev_private;
2068         struct drm_crtc *crtc;
2069
2070         /*
2071          * Flips in the rings have been nuked by the reset,
2072          * so complete all pending flips so that user space
2073          * will get its events and not get stuck.
2074          *
2075          * Also update the base address of all primary
2076          * planes to the the last fb to make sure we're
2077          * showing the correct fb after a reset.
2078          *
2079          * Need to make two loops over the crtcs so that we
2080          * don't try to grab a crtc mutex before the
2081          * pending_flip_queue really got woken up.
2082          */
2083
2084         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2085                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2086                 enum plane plane = intel_crtc->plane;
2087
2088                 intel_prepare_page_flip(dev, plane);
2089                 intel_finish_page_flip_plane(dev, plane);
2090         }
2091
2092         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2093                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2094
2095                 mutex_lock(&crtc->mutex);
2096                 if (intel_crtc->active)
2097                         dev_priv->display.update_plane(crtc, crtc->fb,
2098                                                        crtc->x, crtc->y);
2099                 mutex_unlock(&crtc->mutex);
2100         }
2101 }
2102
2103 static int
2104 intel_finish_fb(struct drm_framebuffer *old_fb)
2105 {
2106         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2107         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2108         bool was_interruptible = dev_priv->mm.interruptible;
2109         int ret;
2110
2111         /* Big Hammer, we also need to ensure that any pending
2112          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2113          * current scanout is retired before unpinning the old
2114          * framebuffer.
2115          *
2116          * This should only fail upon a hung GPU, in which case we
2117          * can safely continue.
2118          */
2119         dev_priv->mm.interruptible = false;
2120         ret = i915_gem_object_finish_gpu(obj);
2121         dev_priv->mm.interruptible = was_interruptible;
2122
2123         return ret;
2124 }
2125
2126 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2127 {
2128         struct drm_device *dev = crtc->dev;
2129         struct drm_i915_master_private *master_priv;
2130         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2131
2132         if (!dev->primary->master)
2133                 return;
2134
2135         master_priv = dev->primary->master->driver_priv;
2136         if (!master_priv->sarea_priv)
2137                 return;
2138
2139         switch (intel_crtc->pipe) {
2140         case 0:
2141                 master_priv->sarea_priv->pipeA_x = x;
2142                 master_priv->sarea_priv->pipeA_y = y;
2143                 break;
2144         case 1:
2145                 master_priv->sarea_priv->pipeB_x = x;
2146                 master_priv->sarea_priv->pipeB_y = y;
2147                 break;
2148         default:
2149                 break;
2150         }
2151 }
2152
2153 static int
2154 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2155                     struct drm_framebuffer *fb)
2156 {
2157         struct drm_device *dev = crtc->dev;
2158         struct drm_i915_private *dev_priv = dev->dev_private;
2159         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2160         struct drm_framebuffer *old_fb;
2161         int ret;
2162
2163         /* no fb bound */
2164         if (!fb) {
2165                 DRM_ERROR("No FB bound\n");
2166                 return 0;
2167         }
2168
2169         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2170                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2171                           plane_name(intel_crtc->plane),
2172                           INTEL_INFO(dev)->num_pipes);
2173                 return -EINVAL;
2174         }
2175
2176         mutex_lock(&dev->struct_mutex);
2177         ret = intel_pin_and_fence_fb_obj(dev,
2178                                          to_intel_framebuffer(fb)->obj,
2179                                          NULL);
2180         if (ret != 0) {
2181                 mutex_unlock(&dev->struct_mutex);
2182                 DRM_ERROR("pin & fence failed\n");
2183                 return ret;
2184         }
2185
2186         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2187         if (ret) {
2188                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2189                 mutex_unlock(&dev->struct_mutex);
2190                 DRM_ERROR("failed to update base address\n");
2191                 return ret;
2192         }
2193
2194         old_fb = crtc->fb;
2195         crtc->fb = fb;
2196         crtc->x = x;
2197         crtc->y = y;
2198
2199         if (old_fb) {
2200                 if (intel_crtc->active && old_fb != fb)
2201                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2202                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2203         }
2204
2205         intel_update_fbc(dev);
2206         mutex_unlock(&dev->struct_mutex);
2207
2208         intel_crtc_update_sarea_pos(crtc, x, y);
2209
2210         return 0;
2211 }
2212
2213 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2214 {
2215         struct drm_device *dev = crtc->dev;
2216         struct drm_i915_private *dev_priv = dev->dev_private;
2217         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2218         int pipe = intel_crtc->pipe;
2219         u32 reg, temp;
2220
2221         /* enable normal train */
2222         reg = FDI_TX_CTL(pipe);
2223         temp = I915_READ(reg);
2224         if (IS_IVYBRIDGE(dev)) {
2225                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2226                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2227         } else {
2228                 temp &= ~FDI_LINK_TRAIN_NONE;
2229                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2230         }
2231         I915_WRITE(reg, temp);
2232
2233         reg = FDI_RX_CTL(pipe);
2234         temp = I915_READ(reg);
2235         if (HAS_PCH_CPT(dev)) {
2236                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2237                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2238         } else {
2239                 temp &= ~FDI_LINK_TRAIN_NONE;
2240                 temp |= FDI_LINK_TRAIN_NONE;
2241         }
2242         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2243
2244         /* wait one idle pattern time */
2245         POSTING_READ(reg);
2246         udelay(1000);
2247
2248         /* IVB wants error correction enabled */
2249         if (IS_IVYBRIDGE(dev))
2250                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2251                            FDI_FE_ERRC_ENABLE);
2252 }
2253
2254 static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2255 {
2256         return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2257 }
2258
2259 static void ivb_modeset_global_resources(struct drm_device *dev)
2260 {
2261         struct drm_i915_private *dev_priv = dev->dev_private;
2262         struct intel_crtc *pipe_B_crtc =
2263                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2264         struct intel_crtc *pipe_C_crtc =
2265                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2266         uint32_t temp;
2267
2268         /*
2269          * When everything is off disable fdi C so that we could enable fdi B
2270          * with all lanes. Note that we don't care about enabled pipes without
2271          * an enabled pch encoder.
2272          */
2273         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2274             !pipe_has_enabled_pch(pipe_C_crtc)) {
2275                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2276                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2277
2278                 temp = I915_READ(SOUTH_CHICKEN1);
2279                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2280                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2281                 I915_WRITE(SOUTH_CHICKEN1, temp);
2282         }
2283 }
2284
2285 /* The FDI link training functions for ILK/Ibexpeak. */
2286 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2287 {
2288         struct drm_device *dev = crtc->dev;
2289         struct drm_i915_private *dev_priv = dev->dev_private;
2290         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2291         int pipe = intel_crtc->pipe;
2292         int plane = intel_crtc->plane;
2293         u32 reg, temp, tries;
2294
2295         /* FDI needs bits from pipe & plane first */
2296         assert_pipe_enabled(dev_priv, pipe);
2297         assert_plane_enabled(dev_priv, plane);
2298
2299         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2300            for train result */
2301         reg = FDI_RX_IMR(pipe);
2302         temp = I915_READ(reg);
2303         temp &= ~FDI_RX_SYMBOL_LOCK;
2304         temp &= ~FDI_RX_BIT_LOCK;
2305         I915_WRITE(reg, temp);
2306         I915_READ(reg);
2307         udelay(150);
2308
2309         /* enable CPU FDI TX and PCH FDI RX */
2310         reg = FDI_TX_CTL(pipe);
2311         temp = I915_READ(reg);
2312         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2313         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2314         temp &= ~FDI_LINK_TRAIN_NONE;
2315         temp |= FDI_LINK_TRAIN_PATTERN_1;
2316         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2317
2318         reg = FDI_RX_CTL(pipe);
2319         temp = I915_READ(reg);
2320         temp &= ~FDI_LINK_TRAIN_NONE;
2321         temp |= FDI_LINK_TRAIN_PATTERN_1;
2322         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2323
2324         POSTING_READ(reg);
2325         udelay(150);
2326
2327         /* Ironlake workaround, enable clock pointer after FDI enable*/
2328         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2329         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2330                    FDI_RX_PHASE_SYNC_POINTER_EN);
2331
2332         reg = FDI_RX_IIR(pipe);
2333         for (tries = 0; tries < 5; tries++) {
2334                 temp = I915_READ(reg);
2335                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2336
2337                 if ((temp & FDI_RX_BIT_LOCK)) {
2338                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2339                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2340                         break;
2341                 }
2342         }
2343         if (tries == 5)
2344                 DRM_ERROR("FDI train 1 fail!\n");
2345
2346         /* Train 2 */
2347         reg = FDI_TX_CTL(pipe);
2348         temp = I915_READ(reg);
2349         temp &= ~FDI_LINK_TRAIN_NONE;
2350         temp |= FDI_LINK_TRAIN_PATTERN_2;
2351         I915_WRITE(reg, temp);
2352
2353         reg = FDI_RX_CTL(pipe);
2354         temp = I915_READ(reg);
2355         temp &= ~FDI_LINK_TRAIN_NONE;
2356         temp |= FDI_LINK_TRAIN_PATTERN_2;
2357         I915_WRITE(reg, temp);
2358
2359         POSTING_READ(reg);
2360         udelay(150);
2361
2362         reg = FDI_RX_IIR(pipe);
2363         for (tries = 0; tries < 5; tries++) {
2364                 temp = I915_READ(reg);
2365                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2366
2367                 if (temp & FDI_RX_SYMBOL_LOCK) {
2368                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2369                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2370                         break;
2371                 }
2372         }
2373         if (tries == 5)
2374                 DRM_ERROR("FDI train 2 fail!\n");
2375
2376         DRM_DEBUG_KMS("FDI train done\n");
2377
2378 }
2379
2380 static const int snb_b_fdi_train_param[] = {
2381         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2382         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2383         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2384         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2385 };
2386
2387 /* The FDI link training functions for SNB/Cougarpoint. */
2388 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2389 {
2390         struct drm_device *dev = crtc->dev;
2391         struct drm_i915_private *dev_priv = dev->dev_private;
2392         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2393         int pipe = intel_crtc->pipe;
2394         u32 reg, temp, i, retry;
2395
2396         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2397            for train result */
2398         reg = FDI_RX_IMR(pipe);
2399         temp = I915_READ(reg);
2400         temp &= ~FDI_RX_SYMBOL_LOCK;
2401         temp &= ~FDI_RX_BIT_LOCK;
2402         I915_WRITE(reg, temp);
2403
2404         POSTING_READ(reg);
2405         udelay(150);
2406
2407         /* enable CPU FDI TX and PCH FDI RX */
2408         reg = FDI_TX_CTL(pipe);
2409         temp = I915_READ(reg);
2410         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2411         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2412         temp &= ~FDI_LINK_TRAIN_NONE;
2413         temp |= FDI_LINK_TRAIN_PATTERN_1;
2414         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2415         /* SNB-B */
2416         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2417         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2418
2419         I915_WRITE(FDI_RX_MISC(pipe),
2420                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2421
2422         reg = FDI_RX_CTL(pipe);
2423         temp = I915_READ(reg);
2424         if (HAS_PCH_CPT(dev)) {
2425                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2426                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2427         } else {
2428                 temp &= ~FDI_LINK_TRAIN_NONE;
2429                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2430         }
2431         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2432
2433         POSTING_READ(reg);
2434         udelay(150);
2435
2436         for (i = 0; i < 4; i++) {
2437                 reg = FDI_TX_CTL(pipe);
2438                 temp = I915_READ(reg);
2439                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2440                 temp |= snb_b_fdi_train_param[i];
2441                 I915_WRITE(reg, temp);
2442
2443                 POSTING_READ(reg);
2444                 udelay(500);
2445
2446                 for (retry = 0; retry < 5; retry++) {
2447                         reg = FDI_RX_IIR(pipe);
2448                         temp = I915_READ(reg);
2449                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2450                         if (temp & FDI_RX_BIT_LOCK) {
2451                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2452                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2453                                 break;
2454                         }
2455                         udelay(50);
2456                 }
2457                 if (retry < 5)
2458                         break;
2459         }
2460         if (i == 4)
2461                 DRM_ERROR("FDI train 1 fail!\n");
2462
2463         /* Train 2 */
2464         reg = FDI_TX_CTL(pipe);
2465         temp = I915_READ(reg);
2466         temp &= ~FDI_LINK_TRAIN_NONE;
2467         temp |= FDI_LINK_TRAIN_PATTERN_2;
2468         if (IS_GEN6(dev)) {
2469                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2470                 /* SNB-B */
2471                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2472         }
2473         I915_WRITE(reg, temp);
2474
2475         reg = FDI_RX_CTL(pipe);
2476         temp = I915_READ(reg);
2477         if (HAS_PCH_CPT(dev)) {
2478                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2479                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2480         } else {
2481                 temp &= ~FDI_LINK_TRAIN_NONE;
2482                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2483         }
2484         I915_WRITE(reg, temp);
2485
2486         POSTING_READ(reg);
2487         udelay(150);
2488
2489         for (i = 0; i < 4; i++) {
2490                 reg = FDI_TX_CTL(pipe);
2491                 temp = I915_READ(reg);
2492                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2493                 temp |= snb_b_fdi_train_param[i];
2494                 I915_WRITE(reg, temp);
2495
2496                 POSTING_READ(reg);
2497                 udelay(500);
2498
2499                 for (retry = 0; retry < 5; retry++) {
2500                         reg = FDI_RX_IIR(pipe);
2501                         temp = I915_READ(reg);
2502                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2503                         if (temp & FDI_RX_SYMBOL_LOCK) {
2504                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2505                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2506                                 break;
2507                         }
2508                         udelay(50);
2509                 }
2510                 if (retry < 5)
2511                         break;
2512         }
2513         if (i == 4)
2514                 DRM_ERROR("FDI train 2 fail!\n");
2515
2516         DRM_DEBUG_KMS("FDI train done.\n");
2517 }
2518
2519 /* Manual link training for Ivy Bridge A0 parts */
2520 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2521 {
2522         struct drm_device *dev = crtc->dev;
2523         struct drm_i915_private *dev_priv = dev->dev_private;
2524         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2525         int pipe = intel_crtc->pipe;
2526         u32 reg, temp, i;
2527
2528         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2529            for train result */
2530         reg = FDI_RX_IMR(pipe);
2531         temp = I915_READ(reg);
2532         temp &= ~FDI_RX_SYMBOL_LOCK;
2533         temp &= ~FDI_RX_BIT_LOCK;
2534         I915_WRITE(reg, temp);
2535
2536         POSTING_READ(reg);
2537         udelay(150);
2538
2539         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2540                       I915_READ(FDI_RX_IIR(pipe)));
2541
2542         /* enable CPU FDI TX and PCH FDI RX */
2543         reg = FDI_TX_CTL(pipe);
2544         temp = I915_READ(reg);
2545         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2546         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2547         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2548         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2549         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2550         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2551         temp |= FDI_COMPOSITE_SYNC;
2552         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2553
2554         I915_WRITE(FDI_RX_MISC(pipe),
2555                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2556
2557         reg = FDI_RX_CTL(pipe);
2558         temp = I915_READ(reg);
2559         temp &= ~FDI_LINK_TRAIN_AUTO;
2560         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2561         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2562         temp |= FDI_COMPOSITE_SYNC;
2563         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2564
2565         POSTING_READ(reg);
2566         udelay(150);
2567
2568         for (i = 0; i < 4; i++) {
2569                 reg = FDI_TX_CTL(pipe);
2570                 temp = I915_READ(reg);
2571                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2572                 temp |= snb_b_fdi_train_param[i];
2573                 I915_WRITE(reg, temp);
2574
2575                 POSTING_READ(reg);
2576                 udelay(500);
2577
2578                 reg = FDI_RX_IIR(pipe);
2579                 temp = I915_READ(reg);
2580                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2581
2582                 if (temp & FDI_RX_BIT_LOCK ||
2583                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2584                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2585                         DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
2586                         break;
2587                 }
2588         }
2589         if (i == 4)
2590                 DRM_ERROR("FDI train 1 fail!\n");
2591
2592         /* Train 2 */
2593         reg = FDI_TX_CTL(pipe);
2594         temp = I915_READ(reg);
2595         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2596         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2597         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2598         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2599         I915_WRITE(reg, temp);
2600
2601         reg = FDI_RX_CTL(pipe);
2602         temp = I915_READ(reg);
2603         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2604         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2605         I915_WRITE(reg, temp);
2606
2607         POSTING_READ(reg);
2608         udelay(150);
2609
2610         for (i = 0; i < 4; i++) {
2611                 reg = FDI_TX_CTL(pipe);
2612                 temp = I915_READ(reg);
2613                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2614                 temp |= snb_b_fdi_train_param[i];
2615                 I915_WRITE(reg, temp);
2616
2617                 POSTING_READ(reg);
2618                 udelay(500);
2619
2620                 reg = FDI_RX_IIR(pipe);
2621                 temp = I915_READ(reg);
2622                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2623
2624                 if (temp & FDI_RX_SYMBOL_LOCK) {
2625                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2626                         DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
2627                         break;
2628                 }
2629         }
2630         if (i == 4)
2631                 DRM_ERROR("FDI train 2 fail!\n");
2632
2633         DRM_DEBUG_KMS("FDI train done.\n");
2634 }
2635
2636 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2637 {
2638         struct drm_device *dev = intel_crtc->base.dev;
2639         struct drm_i915_private *dev_priv = dev->dev_private;
2640         int pipe = intel_crtc->pipe;
2641         u32 reg, temp;
2642
2643
2644         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2645         reg = FDI_RX_CTL(pipe);
2646         temp = I915_READ(reg);
2647         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2648         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2649         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2650         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2651
2652         POSTING_READ(reg);
2653         udelay(200);
2654
2655         /* Switch from Rawclk to PCDclk */
2656         temp = I915_READ(reg);
2657         I915_WRITE(reg, temp | FDI_PCDCLK);
2658
2659         POSTING_READ(reg);
2660         udelay(200);
2661
2662         /* Enable CPU FDI TX PLL, always on for Ironlake */
2663         reg = FDI_TX_CTL(pipe);
2664         temp = I915_READ(reg);
2665         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2666                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2667
2668                 POSTING_READ(reg);
2669                 udelay(100);
2670         }
2671 }
2672
2673 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2674 {
2675         struct drm_device *dev = intel_crtc->base.dev;
2676         struct drm_i915_private *dev_priv = dev->dev_private;
2677         int pipe = intel_crtc->pipe;
2678         u32 reg, temp;
2679
2680         /* Switch from PCDclk to Rawclk */
2681         reg = FDI_RX_CTL(pipe);
2682         temp = I915_READ(reg);
2683         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2684
2685         /* Disable CPU FDI TX PLL */
2686         reg = FDI_TX_CTL(pipe);
2687         temp = I915_READ(reg);
2688         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2689
2690         POSTING_READ(reg);
2691         udelay(100);
2692
2693         reg = FDI_RX_CTL(pipe);
2694         temp = I915_READ(reg);
2695         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2696
2697         /* Wait for the clocks to turn off. */
2698         POSTING_READ(reg);
2699         udelay(100);
2700 }
2701
2702 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2703 {
2704         struct drm_device *dev = crtc->dev;
2705         struct drm_i915_private *dev_priv = dev->dev_private;
2706         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2707         int pipe = intel_crtc->pipe;
2708         u32 reg, temp;
2709
2710         /* disable CPU FDI tx and PCH FDI rx */
2711         reg = FDI_TX_CTL(pipe);
2712         temp = I915_READ(reg);
2713         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2714         POSTING_READ(reg);
2715
2716         reg = FDI_RX_CTL(pipe);
2717         temp = I915_READ(reg);
2718         temp &= ~(0x7 << 16);
2719         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2720         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2721
2722         POSTING_READ(reg);
2723         udelay(100);
2724
2725         /* Ironlake workaround, disable clock pointer after downing FDI */
2726         if (HAS_PCH_IBX(dev)) {
2727                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2728         }
2729
2730         /* still set train pattern 1 */
2731         reg = FDI_TX_CTL(pipe);
2732         temp = I915_READ(reg);
2733         temp &= ~FDI_LINK_TRAIN_NONE;
2734         temp |= FDI_LINK_TRAIN_PATTERN_1;
2735         I915_WRITE(reg, temp);
2736
2737         reg = FDI_RX_CTL(pipe);
2738         temp = I915_READ(reg);
2739         if (HAS_PCH_CPT(dev)) {
2740                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2741                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2742         } else {
2743                 temp &= ~FDI_LINK_TRAIN_NONE;
2744                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2745         }
2746         /* BPC in FDI rx is consistent with that in PIPECONF */
2747         temp &= ~(0x07 << 16);
2748         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2749         I915_WRITE(reg, temp);
2750
2751         POSTING_READ(reg);
2752         udelay(100);
2753 }
2754
2755 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2756 {
2757         struct drm_device *dev = crtc->dev;
2758         struct drm_i915_private *dev_priv = dev->dev_private;
2759         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2760         unsigned long flags;
2761         bool pending;
2762
2763         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2764             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2765                 return false;
2766
2767         spin_lock_irqsave(&dev->event_lock, flags);
2768         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2769         spin_unlock_irqrestore(&dev->event_lock, flags);
2770
2771         return pending;
2772 }
2773
2774 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2775 {
2776         struct drm_device *dev = crtc->dev;
2777         struct drm_i915_private *dev_priv = dev->dev_private;
2778
2779         if (crtc->fb == NULL)
2780                 return;
2781
2782         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2783
2784         wait_event(dev_priv->pending_flip_queue,
2785                    !intel_crtc_has_pending_flip(crtc));
2786
2787         mutex_lock(&dev->struct_mutex);
2788         intel_finish_fb(crtc->fb);
2789         mutex_unlock(&dev->struct_mutex);
2790 }
2791
2792 /* Program iCLKIP clock to the desired frequency */
2793 static void lpt_program_iclkip(struct drm_crtc *crtc)
2794 {
2795         struct drm_device *dev = crtc->dev;
2796         struct drm_i915_private *dev_priv = dev->dev_private;
2797         u32 divsel, phaseinc, auxdiv, phasedir = 0;
2798         u32 temp;
2799
2800         mutex_lock(&dev_priv->dpio_lock);
2801
2802         /* It is necessary to ungate the pixclk gate prior to programming
2803          * the divisors, and gate it back when it is done.
2804          */
2805         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2806
2807         /* Disable SSCCTL */
2808         intel_sbi_write(dev_priv, SBI_SSCCTL6,
2809                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2810                                 SBI_SSCCTL_DISABLE,
2811                         SBI_ICLK);
2812
2813         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2814         if (crtc->mode.clock == 20000) {
2815                 auxdiv = 1;
2816                 divsel = 0x41;
2817                 phaseinc = 0x20;
2818         } else {
2819                 /* The iCLK virtual clock root frequency is in MHz,
2820                  * but the crtc->mode.clock in in KHz. To get the divisors,
2821                  * it is necessary to divide one by another, so we
2822                  * convert the virtual clock precision to KHz here for higher
2823                  * precision.
2824                  */
2825                 u32 iclk_virtual_root_freq = 172800 * 1000;
2826                 u32 iclk_pi_range = 64;
2827                 u32 desired_divisor, msb_divisor_value, pi_value;
2828
2829                 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2830                 msb_divisor_value = desired_divisor / iclk_pi_range;
2831                 pi_value = desired_divisor % iclk_pi_range;
2832
2833                 auxdiv = 0;
2834                 divsel = msb_divisor_value - 2;
2835                 phaseinc = pi_value;
2836         }
2837
2838         /* This should not happen with any sane values */
2839         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2840                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2841         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2842                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2843
2844         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2845                         crtc->mode.clock,
2846                         auxdiv,
2847                         divsel,
2848                         phasedir,
2849                         phaseinc);
2850
2851         /* Program SSCDIVINTPHASE6 */
2852         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
2853         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2854         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2855         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2856         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2857         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2858         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2859         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
2860
2861         /* Program SSCAUXDIV */
2862         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
2863         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2864         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2865         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
2866
2867         /* Enable modulator and associated divider */
2868         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
2869         temp &= ~SBI_SSCCTL_DISABLE;
2870         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
2871
2872         /* Wait for initialization time */
2873         udelay(24);
2874
2875         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2876
2877         mutex_unlock(&dev_priv->dpio_lock);
2878 }
2879
2880 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
2881                                                 enum pipe pch_transcoder)
2882 {
2883         struct drm_device *dev = crtc->base.dev;
2884         struct drm_i915_private *dev_priv = dev->dev_private;
2885         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2886
2887         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
2888                    I915_READ(HTOTAL(cpu_transcoder)));
2889         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
2890                    I915_READ(HBLANK(cpu_transcoder)));
2891         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
2892                    I915_READ(HSYNC(cpu_transcoder)));
2893
2894         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
2895                    I915_READ(VTOTAL(cpu_transcoder)));
2896         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
2897                    I915_READ(VBLANK(cpu_transcoder)));
2898         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
2899                    I915_READ(VSYNC(cpu_transcoder)));
2900         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
2901                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
2902 }
2903
2904 /*
2905  * Enable PCH resources required for PCH ports:
2906  *   - PCH PLLs
2907  *   - FDI training & RX/TX
2908  *   - update transcoder timings
2909  *   - DP transcoding bits
2910  *   - transcoder
2911  */
2912 static void ironlake_pch_enable(struct drm_crtc *crtc)
2913 {
2914         struct drm_device *dev = crtc->dev;
2915         struct drm_i915_private *dev_priv = dev->dev_private;
2916         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2917         int pipe = intel_crtc->pipe;
2918         u32 reg, temp;
2919
2920         assert_pch_transcoder_disabled(dev_priv, pipe);
2921
2922         /* Write the TU size bits before fdi link training, so that error
2923          * detection works. */
2924         I915_WRITE(FDI_RX_TUSIZE1(pipe),
2925                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2926
2927         /* For PCH output, training FDI link */
2928         dev_priv->display.fdi_link_train(crtc);
2929
2930         /* XXX: pch pll's can be enabled any time before we enable the PCH
2931          * transcoder, and we actually should do this to not upset any PCH
2932          * transcoder that already use the clock when we share it.
2933          *
2934          * Note that enable_shared_dpll tries to do the right thing, but
2935          * get_shared_dpll unconditionally resets the pll - we need that to have
2936          * the right LVDS enable sequence. */
2937         ironlake_enable_shared_dpll(intel_crtc);
2938
2939         if (HAS_PCH_CPT(dev)) {
2940                 u32 sel;
2941
2942                 temp = I915_READ(PCH_DPLL_SEL);
2943                 temp |= TRANS_DPLL_ENABLE(pipe);
2944                 sel = TRANS_DPLLB_SEL(pipe);
2945                 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
2946                         temp |= sel;
2947                 else
2948                         temp &= ~sel;
2949                 I915_WRITE(PCH_DPLL_SEL, temp);
2950         }
2951
2952         /* set transcoder timing, panel must allow it */
2953         assert_panel_unlocked(dev_priv, pipe);
2954         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
2955
2956         intel_fdi_normal_train(crtc);
2957
2958         /* For PCH DP, enable TRANS_DP_CTL */
2959         if (HAS_PCH_CPT(dev) &&
2960             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
2961              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2962                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
2963                 reg = TRANS_DP_CTL(pipe);
2964                 temp = I915_READ(reg);
2965                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2966                           TRANS_DP_SYNC_MASK |
2967                           TRANS_DP_BPC_MASK);
2968                 temp |= (TRANS_DP_OUTPUT_ENABLE |
2969                          TRANS_DP_ENH_FRAMING);
2970                 temp |= bpc << 9; /* same format but at 11:9 */
2971
2972                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2973                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2974                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2975                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2976
2977                 switch (intel_trans_dp_port_sel(crtc)) {
2978                 case PCH_DP_B:
2979                         temp |= TRANS_DP_PORT_SEL_B;
2980                         break;
2981                 case PCH_DP_C:
2982                         temp |= TRANS_DP_PORT_SEL_C;
2983                         break;
2984                 case PCH_DP_D:
2985                         temp |= TRANS_DP_PORT_SEL_D;
2986                         break;
2987                 default:
2988                         BUG();
2989                 }
2990
2991                 I915_WRITE(reg, temp);
2992         }
2993
2994         ironlake_enable_pch_transcoder(dev_priv, pipe);
2995 }
2996
2997 static void lpt_pch_enable(struct drm_crtc *crtc)
2998 {
2999         struct drm_device *dev = crtc->dev;
3000         struct drm_i915_private *dev_priv = dev->dev_private;
3001         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3002         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3003
3004         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3005
3006         lpt_program_iclkip(crtc);
3007
3008         /* Set transcoder timing. */
3009         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3010
3011         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3012 }
3013
3014 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3015 {
3016         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3017
3018         if (pll == NULL)
3019                 return;
3020
3021         if (pll->refcount == 0) {
3022                 WARN(1, "bad %s refcount\n", pll->name);
3023                 return;
3024         }
3025
3026         if (--pll->refcount == 0) {
3027                 WARN_ON(pll->on);
3028                 WARN_ON(pll->active);
3029         }
3030
3031         crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3032 }
3033
3034 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, u32 dpll, u32 fp)
3035 {
3036         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3037         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3038         enum intel_dpll_id i;
3039
3040         if (pll) {
3041                 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3042                               crtc->base.base.id, pll->name);
3043                 intel_put_shared_dpll(crtc);
3044         }
3045
3046         if (HAS_PCH_IBX(dev_priv->dev)) {
3047                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3048                 i = crtc->pipe;
3049                 pll = &dev_priv->shared_dplls[i];
3050
3051                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3052                               crtc->base.base.id, pll->name);
3053
3054                 goto found;
3055         }
3056
3057         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3058                 pll = &dev_priv->shared_dplls[i];
3059
3060                 /* Only want to check enabled timings first */
3061                 if (pll->refcount == 0)
3062                         continue;
3063
3064                 if (dpll == (I915_READ(PCH_DPLL(pll->id)) & 0x7fffffff) &&
3065                     fp == I915_READ(PCH_FP0(pll->id))) {
3066                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3067                                       crtc->base.base.id,
3068                                       pll->name, pll->refcount, pll->active);
3069
3070                         goto found;
3071                 }
3072         }
3073
3074         /* Ok no matching timings, maybe there's a free one? */
3075         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3076                 pll = &dev_priv->shared_dplls[i];
3077                 if (pll->refcount == 0) {
3078                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3079                                       crtc->base.base.id, pll->name);
3080                         goto found;
3081                 }
3082         }
3083
3084         return NULL;
3085
3086 found:
3087         crtc->config.shared_dpll = i;
3088         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3089                          pipe_name(crtc->pipe));
3090
3091         if (pll->active == 0) {
3092                 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3093                        sizeof(pll->hw_state));
3094
3095                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
3096                 WARN_ON(pll->on);
3097                 assert_shared_dpll_disabled(dev_priv, pll);
3098
3099                 /* Wait for the clocks to stabilize before rewriting the regs */
3100                 I915_WRITE(PCH_DPLL(pll->id), dpll & ~DPLL_VCO_ENABLE);
3101                 POSTING_READ(PCH_DPLL(pll->id));
3102                 udelay(150);
3103
3104                 I915_WRITE(PCH_FP0(pll->id), fp);
3105                 I915_WRITE(PCH_DPLL(pll->id), dpll & ~DPLL_VCO_ENABLE);
3106         }
3107         pll->refcount++;
3108
3109         return pll;
3110 }
3111
3112 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3113 {
3114         struct drm_i915_private *dev_priv = dev->dev_private;
3115         int dslreg = PIPEDSL(pipe);
3116         u32 temp;
3117
3118         temp = I915_READ(dslreg);
3119         udelay(500);
3120         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3121                 if (wait_for(I915_READ(dslreg) != temp, 5))
3122                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3123         }
3124 }
3125
3126 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3127 {
3128         struct drm_device *dev = crtc->base.dev;
3129         struct drm_i915_private *dev_priv = dev->dev_private;
3130         int pipe = crtc->pipe;
3131
3132         if (crtc->config.pch_pfit.size) {
3133                 /* Force use of hard-coded filter coefficients
3134                  * as some pre-programmed values are broken,
3135                  * e.g. x201.
3136                  */
3137                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3138                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3139                                                  PF_PIPE_SEL_IVB(pipe));
3140                 else
3141                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3142                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3143                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3144         }
3145 }
3146
3147 static void intel_enable_planes(struct drm_crtc *crtc)
3148 {
3149         struct drm_device *dev = crtc->dev;
3150         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3151         struct intel_plane *intel_plane;
3152
3153         list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3154                 if (intel_plane->pipe == pipe)
3155                         intel_plane_restore(&intel_plane->base);
3156 }
3157
3158 static void intel_disable_planes(struct drm_crtc *crtc)
3159 {
3160         struct drm_device *dev = crtc->dev;
3161         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3162         struct intel_plane *intel_plane;
3163
3164         list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3165                 if (intel_plane->pipe == pipe)
3166                         intel_plane_disable(&intel_plane->base);
3167 }
3168
3169 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3170 {
3171         struct drm_device *dev = crtc->dev;
3172         struct drm_i915_private *dev_priv = dev->dev_private;
3173         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3174         struct intel_encoder *encoder;
3175         int pipe = intel_crtc->pipe;
3176         int plane = intel_crtc->plane;
3177         u32 temp;
3178
3179         WARN_ON(!crtc->enabled);
3180
3181         if (intel_crtc->active)
3182                 return;
3183
3184         intel_crtc->active = true;
3185
3186         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3187         intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3188
3189         intel_update_watermarks(dev);
3190
3191         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3192                 temp = I915_READ(PCH_LVDS);
3193                 if ((temp & LVDS_PORT_EN) == 0)
3194                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3195         }
3196
3197
3198         if (intel_crtc->config.has_pch_encoder) {
3199                 /* Note: FDI PLL enabling _must_ be done before we enable the
3200                  * cpu pipes, hence this is separate from all the other fdi/pch
3201                  * enabling. */
3202                 ironlake_fdi_pll_enable(intel_crtc);
3203         } else {
3204                 assert_fdi_tx_disabled(dev_priv, pipe);
3205                 assert_fdi_rx_disabled(dev_priv, pipe);
3206         }
3207
3208         for_each_encoder_on_crtc(dev, crtc, encoder)
3209                 if (encoder->pre_enable)
3210                         encoder->pre_enable(encoder);
3211
3212         /* Enable panel fitting for LVDS */
3213         ironlake_pfit_enable(intel_crtc);
3214
3215         /*
3216          * On ILK+ LUT must be loaded before the pipe is running but with
3217          * clocks enabled
3218          */
3219         intel_crtc_load_lut(crtc);
3220
3221         intel_enable_pipe(dev_priv, pipe,
3222                           intel_crtc->config.has_pch_encoder);
3223         intel_enable_plane(dev_priv, plane, pipe);
3224         intel_enable_planes(crtc);
3225         intel_crtc_update_cursor(crtc, true);
3226
3227         if (intel_crtc->config.has_pch_encoder)
3228                 ironlake_pch_enable(crtc);
3229
3230         mutex_lock(&dev->struct_mutex);
3231         intel_update_fbc(dev);
3232         mutex_unlock(&dev->struct_mutex);
3233
3234         for_each_encoder_on_crtc(dev, crtc, encoder)
3235                 encoder->enable(encoder);
3236
3237         if (HAS_PCH_CPT(dev))
3238                 cpt_verify_modeset(dev, intel_crtc->pipe);
3239
3240         /*
3241          * There seems to be a race in PCH platform hw (at least on some
3242          * outputs) where an enabled pipe still completes any pageflip right
3243          * away (as if the pipe is off) instead of waiting for vblank. As soon
3244          * as the first vblank happend, everything works as expected. Hence just
3245          * wait for one vblank before returning to avoid strange things
3246          * happening.
3247          */
3248         intel_wait_for_vblank(dev, intel_crtc->pipe);
3249 }
3250
3251 /* IPS only exists on ULT machines and is tied to pipe A. */
3252 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3253 {
3254         return IS_ULT(crtc->base.dev) && crtc->pipe == PIPE_A;
3255 }
3256
3257 static void hsw_enable_ips(struct intel_crtc *crtc)
3258 {
3259         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3260
3261         if (!crtc->config.ips_enabled)
3262                 return;
3263
3264         /* We can only enable IPS after we enable a plane and wait for a vblank.
3265          * We guarantee that the plane is enabled by calling intel_enable_ips
3266          * only after intel_enable_plane. And intel_enable_plane already waits
3267          * for a vblank, so all we need to do here is to enable the IPS bit. */
3268         assert_plane_enabled(dev_priv, crtc->plane);
3269         I915_WRITE(IPS_CTL, IPS_ENABLE);
3270 }
3271
3272 static void hsw_disable_ips(struct intel_crtc *crtc)
3273 {
3274         struct drm_device *dev = crtc->base.dev;
3275         struct drm_i915_private *dev_priv = dev->dev_private;
3276
3277         if (!crtc->config.ips_enabled)
3278                 return;
3279
3280         assert_plane_enabled(dev_priv, crtc->plane);
3281         I915_WRITE(IPS_CTL, 0);
3282
3283         /* We need to wait for a vblank before we can disable the plane. */
3284         intel_wait_for_vblank(dev, crtc->pipe);
3285 }
3286
3287 static void haswell_crtc_enable(struct drm_crtc *crtc)
3288 {
3289         struct drm_device *dev = crtc->dev;
3290         struct drm_i915_private *dev_priv = dev->dev_private;
3291         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3292         struct intel_encoder *encoder;
3293         int pipe = intel_crtc->pipe;
3294         int plane = intel_crtc->plane;
3295
3296         WARN_ON(!crtc->enabled);
3297
3298         if (intel_crtc->active)
3299                 return;
3300
3301         intel_crtc->active = true;
3302
3303         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3304         if (intel_crtc->config.has_pch_encoder)
3305                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3306
3307         intel_update_watermarks(dev);
3308
3309         if (intel_crtc->config.has_pch_encoder)
3310                 dev_priv->display.fdi_link_train(crtc);
3311
3312         for_each_encoder_on_crtc(dev, crtc, encoder)
3313                 if (encoder->pre_enable)
3314                         encoder->pre_enable(encoder);
3315
3316         intel_ddi_enable_pipe_clock(intel_crtc);
3317
3318         /* Enable panel fitting for eDP */
3319         ironlake_pfit_enable(intel_crtc);
3320
3321         /*
3322          * On ILK+ LUT must be loaded before the pipe is running but with
3323          * clocks enabled
3324          */
3325         intel_crtc_load_lut(crtc);
3326
3327         intel_ddi_set_pipe_settings(crtc);
3328         intel_ddi_enable_transcoder_func(crtc);
3329
3330         intel_enable_pipe(dev_priv, pipe,
3331                           intel_crtc->config.has_pch_encoder);
3332         intel_enable_plane(dev_priv, plane, pipe);
3333         intel_enable_planes(crtc);
3334         intel_crtc_update_cursor(crtc, true);
3335
3336         hsw_enable_ips(intel_crtc);
3337
3338         if (intel_crtc->config.has_pch_encoder)
3339                 lpt_pch_enable(crtc);
3340
3341         mutex_lock(&dev->struct_mutex);
3342         intel_update_fbc(dev);
3343         mutex_unlock(&dev->struct_mutex);
3344
3345         for_each_encoder_on_crtc(dev, crtc, encoder)
3346                 encoder->enable(encoder);
3347
3348         /*
3349          * There seems to be a race in PCH platform hw (at least on some
3350          * outputs) where an enabled pipe still completes any pageflip right
3351          * away (as if the pipe is off) instead of waiting for vblank. As soon
3352          * as the first vblank happend, everything works as expected. Hence just
3353          * wait for one vblank before returning to avoid strange things
3354          * happening.
3355          */
3356         intel_wait_for_vblank(dev, intel_crtc->pipe);
3357 }
3358
3359 static void ironlake_pfit_disable(struct intel_crtc *crtc)
3360 {
3361         struct drm_device *dev = crtc->base.dev;
3362         struct drm_i915_private *dev_priv = dev->dev_private;
3363         int pipe = crtc->pipe;
3364
3365         /* To avoid upsetting the power well on haswell only disable the pfit if
3366          * it's in use. The hw state code will make sure we get this right. */
3367         if (crtc->config.pch_pfit.size) {
3368                 I915_WRITE(PF_CTL(pipe), 0);
3369                 I915_WRITE(PF_WIN_POS(pipe), 0);
3370                 I915_WRITE(PF_WIN_SZ(pipe), 0);
3371         }
3372 }
3373
3374 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3375 {
3376         struct drm_device *dev = crtc->dev;
3377         struct drm_i915_private *dev_priv = dev->dev_private;
3378         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3379         struct intel_encoder *encoder;
3380         int pipe = intel_crtc->pipe;
3381         int plane = intel_crtc->plane;
3382         u32 reg, temp;
3383
3384
3385         if (!intel_crtc->active)
3386                 return;
3387
3388         for_each_encoder_on_crtc(dev, crtc, encoder)
3389                 encoder->disable(encoder);
3390
3391         intel_crtc_wait_for_pending_flips(crtc);
3392         drm_vblank_off(dev, pipe);
3393
3394         if (dev_priv->cfb_plane == plane)
3395                 intel_disable_fbc(dev);
3396
3397         intel_crtc_update_cursor(crtc, false);
3398         intel_disable_planes(crtc);
3399         intel_disable_plane(dev_priv, plane, pipe);
3400
3401         if (intel_crtc->config.has_pch_encoder)
3402                 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3403
3404         intel_disable_pipe(dev_priv, pipe);
3405
3406         ironlake_pfit_disable(intel_crtc);
3407
3408         for_each_encoder_on_crtc(dev, crtc, encoder)
3409                 if (encoder->post_disable)
3410                         encoder->post_disable(encoder);
3411
3412         if (intel_crtc->config.has_pch_encoder) {
3413                 ironlake_fdi_disable(crtc);
3414
3415                 ironlake_disable_pch_transcoder(dev_priv, pipe);
3416                 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3417
3418                 if (HAS_PCH_CPT(dev)) {
3419                         /* disable TRANS_DP_CTL */
3420                         reg = TRANS_DP_CTL(pipe);
3421                         temp = I915_READ(reg);
3422                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3423                                   TRANS_DP_PORT_SEL_MASK);
3424                         temp |= TRANS_DP_PORT_SEL_NONE;
3425                         I915_WRITE(reg, temp);
3426
3427                         /* disable DPLL_SEL */
3428                         temp = I915_READ(PCH_DPLL_SEL);
3429                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
3430                         I915_WRITE(PCH_DPLL_SEL, temp);
3431                 }
3432
3433                 /* disable PCH DPLL */
3434                 intel_disable_shared_dpll(intel_crtc);
3435
3436                 ironlake_fdi_pll_disable(intel_crtc);
3437         }
3438
3439         intel_crtc->active = false;
3440         intel_update_watermarks(dev);
3441
3442         mutex_lock(&dev->struct_mutex);
3443         intel_update_fbc(dev);
3444         mutex_unlock(&dev->struct_mutex);
3445 }
3446
3447 static void haswell_crtc_disable(struct drm_crtc *crtc)
3448 {
3449         struct drm_device *dev = crtc->dev;
3450         struct drm_i915_private *dev_priv = dev->dev_private;
3451         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3452         struct intel_encoder *encoder;
3453         int pipe = intel_crtc->pipe;
3454         int plane = intel_crtc->plane;
3455         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3456
3457         if (!intel_crtc->active)
3458                 return;
3459
3460         for_each_encoder_on_crtc(dev, crtc, encoder)
3461                 encoder->disable(encoder);
3462
3463         intel_crtc_wait_for_pending_flips(crtc);
3464         drm_vblank_off(dev, pipe);
3465
3466         /* FBC must be disabled before disabling the plane on HSW. */
3467         if (dev_priv->cfb_plane == plane)
3468                 intel_disable_fbc(dev);
3469
3470         hsw_disable_ips(intel_crtc);
3471
3472         intel_crtc_update_cursor(crtc, false);
3473         intel_disable_planes(crtc);
3474         intel_disable_plane(dev_priv, plane, pipe);
3475
3476         if (intel_crtc->config.has_pch_encoder)
3477                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3478         intel_disable_pipe(dev_priv, pipe);
3479
3480         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3481
3482         ironlake_pfit_disable(intel_crtc);
3483
3484         intel_ddi_disable_pipe_clock(intel_crtc);
3485
3486         for_each_encoder_on_crtc(dev, crtc, encoder)
3487                 if (encoder->post_disable)
3488                         encoder->post_disable(encoder);
3489
3490         if (intel_crtc->config.has_pch_encoder) {
3491                 lpt_disable_pch_transcoder(dev_priv);
3492                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3493                 intel_ddi_fdi_disable(crtc);
3494         }
3495
3496         intel_crtc->active = false;
3497         intel_update_watermarks(dev);
3498
3499         mutex_lock(&dev->struct_mutex);
3500         intel_update_fbc(dev);
3501         mutex_unlock(&dev->struct_mutex);
3502 }
3503
3504 static void ironlake_crtc_off(struct drm_crtc *crtc)
3505 {
3506         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3507         intel_put_shared_dpll(intel_crtc);
3508 }
3509
3510 static void haswell_crtc_off(struct drm_crtc *crtc)
3511 {
3512         intel_ddi_put_crtc_pll(crtc);
3513 }
3514
3515 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3516 {
3517         if (!enable && intel_crtc->overlay) {
3518                 struct drm_device *dev = intel_crtc->base.dev;
3519                 struct drm_i915_private *dev_priv = dev->dev_private;
3520
3521                 mutex_lock(&dev->struct_mutex);
3522                 dev_priv->mm.interruptible = false;
3523                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3524                 dev_priv->mm.interruptible = true;
3525                 mutex_unlock(&dev->struct_mutex);
3526         }
3527
3528         /* Let userspace switch the overlay on again. In most cases userspace
3529          * has to recompute where to put it anyway.
3530          */
3531 }
3532
3533 /**
3534  * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3535  * cursor plane briefly if not already running after enabling the display
3536  * plane.
3537  * This workaround avoids occasional blank screens when self refresh is
3538  * enabled.
3539  */
3540 static void
3541 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3542 {
3543         u32 cntl = I915_READ(CURCNTR(pipe));
3544
3545         if ((cntl & CURSOR_MODE) == 0) {
3546                 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3547
3548                 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3549                 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3550                 intel_wait_for_vblank(dev_priv->dev, pipe);
3551                 I915_WRITE(CURCNTR(pipe), cntl);
3552                 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3553                 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3554         }
3555 }
3556
3557 static void i9xx_pfit_enable(struct intel_crtc *crtc)
3558 {
3559         struct drm_device *dev = crtc->base.dev;
3560         struct drm_i915_private *dev_priv = dev->dev_private;
3561         struct intel_crtc_config *pipe_config = &crtc->config;
3562
3563         if (!crtc->config.gmch_pfit.control)
3564                 return;
3565
3566         /*
3567          * The panel fitter should only be adjusted whilst the pipe is disabled,
3568          * according to register description and PRM.
3569          */
3570         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3571         assert_pipe_disabled(dev_priv, crtc->pipe);
3572
3573         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3574         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
3575
3576         /* Border color in case we don't scale up to the full screen. Black by
3577          * default, change to something else for debugging. */
3578         I915_WRITE(BCLRPAT(crtc->pipe), 0);
3579 }
3580
3581 static void valleyview_crtc_enable(struct drm_crtc *crtc)
3582 {
3583         struct drm_device *dev = crtc->dev;
3584         struct drm_i915_private *dev_priv = dev->dev_private;
3585         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3586         struct intel_encoder *encoder;
3587         int pipe = intel_crtc->pipe;
3588         int plane = intel_crtc->plane;
3589
3590         WARN_ON(!crtc->enabled);
3591
3592         if (intel_crtc->active)
3593                 return;
3594
3595         intel_crtc->active = true;
3596         intel_update_watermarks(dev);
3597
3598         mutex_lock(&dev_priv->dpio_lock);
3599
3600         for_each_encoder_on_crtc(dev, crtc, encoder)
3601                 if (encoder->pre_pll_enable)
3602                         encoder->pre_pll_enable(encoder);
3603
3604         intel_enable_pll(dev_priv, pipe);
3605
3606         for_each_encoder_on_crtc(dev, crtc, encoder)
3607                 if (encoder->pre_enable)
3608                         encoder->pre_enable(encoder);
3609
3610         /* VLV wants encoder enabling _before_ the pipe is up. */
3611         for_each_encoder_on_crtc(dev, crtc, encoder)
3612                 encoder->enable(encoder);
3613
3614         /* Enable panel fitting for eDP */
3615         i9xx_pfit_enable(intel_crtc);
3616
3617         intel_crtc_load_lut(crtc);
3618
3619         intel_enable_pipe(dev_priv, pipe, false);
3620         intel_enable_plane(dev_priv, plane, pipe);
3621         intel_enable_planes(crtc);
3622         intel_crtc_update_cursor(crtc, true);
3623
3624         intel_update_fbc(dev);
3625
3626         mutex_unlock(&dev_priv->dpio_lock);
3627 }
3628
3629 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3630 {
3631         struct drm_device *dev = crtc->dev;
3632         struct drm_i915_private *dev_priv = dev->dev_private;
3633         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3634         struct intel_encoder *encoder;
3635         int pipe = intel_crtc->pipe;
3636         int plane = intel_crtc->plane;
3637
3638         WARN_ON(!crtc->enabled);
3639
3640         if (intel_crtc->active)
3641                 return;
3642
3643         intel_crtc->active = true;
3644         intel_update_watermarks(dev);
3645
3646         intel_enable_pll(dev_priv, pipe);
3647
3648         for_each_encoder_on_crtc(dev, crtc, encoder)
3649                 if (encoder->pre_enable)
3650                         encoder->pre_enable(encoder);
3651
3652         /* Enable panel fitting for LVDS */
3653         i9xx_pfit_enable(intel_crtc);
3654
3655         intel_crtc_load_lut(crtc);
3656
3657         intel_enable_pipe(dev_priv, pipe, false);
3658         intel_enable_plane(dev_priv, plane, pipe);
3659         intel_enable_planes(crtc);
3660         /* The fixup needs to happen before cursor is enabled */
3661         if (IS_G4X(dev))
3662                 g4x_fixup_plane(dev_priv, pipe);
3663         intel_crtc_update_cursor(crtc, true);
3664
3665         /* Give the overlay scaler a chance to enable if it's on this pipe */
3666         intel_crtc_dpms_overlay(intel_crtc, true);
3667
3668         intel_update_fbc(dev);
3669
3670         for_each_encoder_on_crtc(dev, crtc, encoder)
3671                 encoder->enable(encoder);
3672 }
3673
3674 static void i9xx_pfit_disable(struct intel_crtc *crtc)
3675 {
3676         struct drm_device *dev = crtc->base.dev;
3677         struct drm_i915_private *dev_priv = dev->dev_private;
3678
3679         if (!crtc->config.gmch_pfit.control)
3680                 return;
3681
3682         assert_pipe_disabled(dev_priv, crtc->pipe);
3683
3684         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3685                          I915_READ(PFIT_CONTROL));
3686         I915_WRITE(PFIT_CONTROL, 0);
3687 }
3688
3689 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3690 {
3691         struct drm_device *dev = crtc->dev;
3692         struct drm_i915_private *dev_priv = dev->dev_private;
3693         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3694         struct intel_encoder *encoder;
3695         int pipe = intel_crtc->pipe;
3696         int plane = intel_crtc->plane;
3697
3698         if (!intel_crtc->active)
3699                 return;
3700
3701         for_each_encoder_on_crtc(dev, crtc, encoder)
3702                 encoder->disable(encoder);
3703
3704         /* Give the overlay scaler a chance to disable if it's on this pipe */
3705         intel_crtc_wait_for_pending_flips(crtc);
3706         drm_vblank_off(dev, pipe);
3707
3708         if (dev_priv->cfb_plane == plane)
3709                 intel_disable_fbc(dev);
3710
3711         intel_crtc_dpms_overlay(intel_crtc, false);
3712         intel_crtc_update_cursor(crtc, false);
3713         intel_disable_planes(crtc);
3714         intel_disable_plane(dev_priv, plane, pipe);
3715
3716         intel_disable_pipe(dev_priv, pipe);
3717
3718         i9xx_pfit_disable(intel_crtc);
3719
3720         for_each_encoder_on_crtc(dev, crtc, encoder)
3721                 if (encoder->post_disable)
3722                         encoder->post_disable(encoder);
3723
3724         intel_disable_pll(dev_priv, pipe);
3725
3726         intel_crtc->active = false;
3727         intel_update_fbc(dev);
3728         intel_update_watermarks(dev);
3729 }
3730
3731 static void i9xx_crtc_off(struct drm_crtc *crtc)
3732 {
3733 }
3734
3735 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3736                                     bool enabled)
3737 {
3738         struct drm_device *dev = crtc->dev;
3739         struct drm_i915_master_private *master_priv;
3740         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3741         int pipe = intel_crtc->pipe;
3742
3743         if (!dev->primary->master)
3744                 return;
3745
3746         master_priv = dev->primary->master->driver_priv;
3747         if (!master_priv->sarea_priv)
3748                 return;
3749
3750         switch (pipe) {
3751         case 0:
3752                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3753                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3754                 break;
3755         case 1:
3756                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3757                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3758                 break;
3759         default:
3760                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3761                 break;
3762         }
3763 }
3764
3765 /**
3766  * Sets the power management mode of the pipe and plane.
3767  */
3768 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3769 {
3770         struct drm_device *dev = crtc->dev;
3771         struct drm_i915_private *dev_priv = dev->dev_private;
3772         struct intel_encoder *intel_encoder;
3773         bool enable = false;
3774
3775         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3776                 enable |= intel_encoder->connectors_active;
3777
3778         if (enable)
3779                 dev_priv->display.crtc_enable(crtc);
3780         else
3781                 dev_priv->display.crtc_disable(crtc);
3782
3783         intel_crtc_update_sarea(crtc, enable);
3784 }
3785
3786 static void intel_crtc_disable(struct drm_crtc *crtc)
3787 {
3788         struct drm_device *dev = crtc->dev;
3789         struct drm_connector *connector;
3790         struct drm_i915_private *dev_priv = dev->dev_private;
3791         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3792
3793         /* crtc should still be enabled when we disable it. */
3794         WARN_ON(!crtc->enabled);
3795
3796         dev_priv->display.crtc_disable(crtc);
3797         intel_crtc->eld_vld = false;
3798         intel_crtc_update_sarea(crtc, false);
3799         dev_priv->display.off(crtc);
3800
3801         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3802         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3803
3804         if (crtc->fb) {
3805                 mutex_lock(&dev->struct_mutex);
3806                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3807                 mutex_unlock(&dev->struct_mutex);
3808                 crtc->fb = NULL;
3809         }
3810
3811         /* Update computed state. */
3812         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3813                 if (!connector->encoder || !connector->encoder->crtc)
3814                         continue;
3815
3816                 if (connector->encoder->crtc != crtc)
3817                         continue;
3818
3819                 connector->dpms = DRM_MODE_DPMS_OFF;
3820                 to_intel_encoder(connector->encoder)->connectors_active = false;
3821         }
3822 }
3823
3824 void intel_modeset_disable(struct drm_device *dev)
3825 {
3826         struct drm_crtc *crtc;
3827
3828         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3829                 if (crtc->enabled)
3830                         intel_crtc_disable(crtc);
3831         }
3832 }
3833
3834 void intel_encoder_destroy(struct drm_encoder *encoder)
3835 {
3836         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3837
3838         drm_encoder_cleanup(encoder);
3839         kfree(intel_encoder);
3840 }
3841
3842 /* Simple dpms helper for encodres with just one connector, no cloning and only
3843  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3844  * state of the entire output pipe. */
3845 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3846 {
3847         if (mode == DRM_MODE_DPMS_ON) {
3848                 encoder->connectors_active = true;
3849
3850                 intel_crtc_update_dpms(encoder->base.crtc);
3851         } else {
3852                 encoder->connectors_active = false;
3853
3854                 intel_crtc_update_dpms(encoder->base.crtc);
3855         }
3856 }
3857
3858 /* Cross check the actual hw state with our own modeset state tracking (and it's
3859  * internal consistency). */
3860 static void intel_connector_check_state(struct intel_connector *connector)
3861 {
3862         if (connector->get_hw_state(connector)) {
3863                 struct intel_encoder *encoder = connector->encoder;
3864                 struct drm_crtc *crtc;
3865                 bool encoder_enabled;
3866                 enum pipe pipe;
3867
3868                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3869                               connector->base.base.id,
3870                               drm_get_connector_name(&connector->base));
3871
3872                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3873                      "wrong connector dpms state\n");
3874                 WARN(connector->base.encoder != &encoder->base,
3875                      "active connector not linked to encoder\n");
3876                 WARN(!encoder->connectors_active,
3877                      "encoder->connectors_active not set\n");
3878
3879                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3880                 WARN(!encoder_enabled, "encoder not enabled\n");
3881                 if (WARN_ON(!encoder->base.crtc))
3882                         return;
3883
3884                 crtc = encoder->base.crtc;
3885
3886                 WARN(!crtc->enabled, "crtc not enabled\n");
3887                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3888                 WARN(pipe != to_intel_crtc(crtc)->pipe,
3889                      "encoder active on the wrong pipe\n");
3890         }
3891 }
3892
3893 /* Even simpler default implementation, if there's really no special case to
3894  * consider. */
3895 void intel_connector_dpms(struct drm_connector *connector, int mode)
3896 {
3897         struct intel_encoder *encoder = intel_attached_encoder(connector);
3898
3899         /* All the simple cases only support two dpms states. */
3900         if (mode != DRM_MODE_DPMS_ON)
3901                 mode = DRM_MODE_DPMS_OFF;
3902
3903         if (mode == connector->dpms)
3904                 return;
3905
3906         connector->dpms = mode;
3907
3908         /* Only need to change hw state when actually enabled */
3909         if (encoder->base.crtc)
3910                 intel_encoder_dpms(encoder, mode);
3911         else
3912                 WARN_ON(encoder->connectors_active != false);
3913
3914         intel_modeset_check_state(connector->dev);
3915 }
3916
3917 /* Simple connector->get_hw_state implementation for encoders that support only
3918  * one connector and no cloning and hence the encoder state determines the state
3919  * of the connector. */
3920 bool intel_connector_get_hw_state(struct intel_connector *connector)
3921 {
3922         enum pipe pipe = 0;
3923         struct intel_encoder *encoder = connector->encoder;
3924
3925         return encoder->get_hw_state(encoder, &pipe);
3926 }
3927
3928 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
3929                                      struct intel_crtc_config *pipe_config)
3930 {
3931         struct drm_i915_private *dev_priv = dev->dev_private;
3932         struct intel_crtc *pipe_B_crtc =
3933                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3934
3935         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
3936                       pipe_name(pipe), pipe_config->fdi_lanes);
3937         if (pipe_config->fdi_lanes > 4) {
3938                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
3939                               pipe_name(pipe), pipe_config->fdi_lanes);
3940                 return false;
3941         }
3942
3943         if (IS_HASWELL(dev)) {
3944                 if (pipe_config->fdi_lanes > 2) {
3945                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
3946                                       pipe_config->fdi_lanes);
3947                         return false;
3948                 } else {
3949                         return true;
3950                 }
3951         }
3952
3953         if (INTEL_INFO(dev)->num_pipes == 2)
3954                 return true;
3955
3956         /* Ivybridge 3 pipe is really complicated */
3957         switch (pipe) {
3958         case PIPE_A:
3959                 return true;
3960         case PIPE_B:
3961                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
3962                     pipe_config->fdi_lanes > 2) {
3963                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
3964                                       pipe_name(pipe), pipe_config->fdi_lanes);
3965                         return false;
3966                 }
3967                 return true;
3968         case PIPE_C:
3969                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
3970                     pipe_B_crtc->config.fdi_lanes <= 2) {
3971                         if (pipe_config->fdi_lanes > 2) {
3972                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
3973                                               pipe_name(pipe), pipe_config->fdi_lanes);
3974                                 return false;
3975                         }
3976                 } else {
3977                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
3978                         return false;
3979                 }
3980                 return true;
3981         default:
3982                 BUG();
3983         }
3984 }
3985
3986 #define RETRY 1
3987 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
3988                                        struct intel_crtc_config *pipe_config)
3989 {
3990         struct drm_device *dev = intel_crtc->base.dev;
3991         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
3992         int lane, link_bw, fdi_dotclock;
3993         bool setup_ok, needs_recompute = false;
3994
3995 retry:
3996         /* FDI is a binary signal running at ~2.7GHz, encoding
3997          * each output octet as 10 bits. The actual frequency
3998          * is stored as a divider into a 100MHz clock, and the
3999          * mode pixel clock is stored in units of 1KHz.
4000          * Hence the bw of each lane in terms of the mode signal
4001          * is:
4002          */
4003         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4004
4005         fdi_dotclock = adjusted_mode->clock;
4006         fdi_dotclock /= pipe_config->pixel_multiplier;
4007
4008         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
4009                                            pipe_config->pipe_bpp);
4010
4011         pipe_config->fdi_lanes = lane;
4012
4013         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4014                                link_bw, &pipe_config->fdi_m_n);
4015
4016         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4017                                             intel_crtc->pipe, pipe_config);
4018         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4019                 pipe_config->pipe_bpp -= 2*3;
4020                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4021                               pipe_config->pipe_bpp);
4022                 needs_recompute = true;
4023                 pipe_config->bw_constrained = true;
4024
4025                 goto retry;
4026         }
4027
4028         if (needs_recompute)
4029                 return RETRY;
4030
4031         return setup_ok ? 0 : -EINVAL;
4032 }
4033
4034 static void hsw_compute_ips_config(struct intel_crtc *crtc,
4035                                    struct intel_crtc_config *pipe_config)
4036 {
4037         pipe_config->ips_enabled = i915_enable_ips &&
4038                                    hsw_crtc_supports_ips(crtc) &&
4039                                    pipe_config->pipe_bpp == 24;
4040 }
4041
4042 static int intel_crtc_compute_config(struct intel_crtc *crtc,
4043                                      struct intel_crtc_config *pipe_config)
4044 {
4045         struct drm_device *dev = crtc->base.dev;
4046         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4047
4048         if (HAS_PCH_SPLIT(dev)) {
4049                 /* FDI link clock is fixed at 2.7G */
4050                 if (pipe_config->requested_mode.clock * 3
4051                     > IRONLAKE_FDI_FREQ * 4)
4052                         return -EINVAL;
4053         }
4054
4055         /* All interlaced capable intel hw wants timings in frames. Note though
4056          * that intel_lvds_mode_fixup does some funny tricks with the crtc
4057          * timings, so we need to be careful not to clobber these.*/
4058         if (!pipe_config->timings_set)
4059                 drm_mode_set_crtcinfo(adjusted_mode, 0);
4060
4061         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4062          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4063          */
4064         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4065                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4066                 return -EINVAL;
4067
4068         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4069                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4070         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4071                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4072                  * for lvds. */
4073                 pipe_config->pipe_bpp = 8*3;
4074         }
4075
4076         if (IS_HASWELL(dev))
4077                 hsw_compute_ips_config(crtc, pipe_config);
4078
4079         /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4080          * clock survives for now. */
4081         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4082                 pipe_config->shared_dpll = crtc->config.shared_dpll;
4083
4084         if (pipe_config->has_pch_encoder)
4085                 return ironlake_fdi_compute_config(crtc, pipe_config);
4086
4087         return 0;
4088 }
4089
4090 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4091 {
4092         return 400000; /* FIXME */
4093 }
4094
4095 static int i945_get_display_clock_speed(struct drm_device *dev)
4096 {
4097         return 400000;
4098 }
4099
4100 static int i915_get_display_clock_speed(struct drm_device *dev)
4101 {
4102         return 333000;
4103 }
4104
4105 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4106 {
4107         return 200000;
4108 }
4109
4110 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4111 {
4112         u16 gcfgc = 0;
4113
4114         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4115
4116         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4117                 return 133000;
4118         else {
4119                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4120                 case GC_DISPLAY_CLOCK_333_MHZ:
4121                         return 333000;
4122                 default:
4123                 case GC_DISPLAY_CLOCK_190_200_MHZ:
4124                         return 190000;
4125                 }
4126         }
4127 }
4128
4129 static int i865_get_display_clock_speed(struct drm_device *dev)
4130 {
4131         return 266000;
4132 }
4133
4134 static int i855_get_display_clock_speed(struct drm_device *dev)
4135 {
4136         u16 hpllcc = 0;
4137         /* Assume that the hardware is in the high speed state.  This
4138          * should be the default.
4139          */
4140         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4141         case GC_CLOCK_133_200:
4142         case GC_CLOCK_100_200:
4143                 return 200000;
4144         case GC_CLOCK_166_250:
4145                 return 250000;
4146         case GC_CLOCK_100_133:
4147                 return 133000;
4148         }
4149
4150         /* Shouldn't happen */
4151         return 0;
4152 }
4153
4154 static int i830_get_display_clock_speed(struct drm_device *dev)
4155 {
4156         return 133000;
4157 }
4158
4159 static void
4160 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
4161 {
4162         while (*num > DATA_LINK_M_N_MASK ||
4163                *den > DATA_LINK_M_N_MASK) {
4164                 *num >>= 1;
4165                 *den >>= 1;
4166         }
4167 }
4168
4169 static void compute_m_n(unsigned int m, unsigned int n,
4170                         uint32_t *ret_m, uint32_t *ret_n)
4171 {
4172         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4173         *ret_m = div_u64((uint64_t) m * *ret_n, n);
4174         intel_reduce_m_n_ratio(ret_m, ret_n);
4175 }
4176
4177 void
4178 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4179                        int pixel_clock, int link_clock,
4180                        struct intel_link_m_n *m_n)
4181 {
4182         m_n->tu = 64;
4183
4184         compute_m_n(bits_per_pixel * pixel_clock,
4185                     link_clock * nlanes * 8,
4186                     &m_n->gmch_m, &m_n->gmch_n);
4187
4188         compute_m_n(pixel_clock, link_clock,
4189                     &m_n->link_m, &m_n->link_n);
4190 }
4191
4192 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4193 {
4194         if (i915_panel_use_ssc >= 0)
4195                 return i915_panel_use_ssc != 0;
4196         return dev_priv->vbt.lvds_use_ssc
4197                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4198 }
4199
4200 static int vlv_get_refclk(struct drm_crtc *crtc)
4201 {
4202         struct drm_device *dev = crtc->dev;
4203         struct drm_i915_private *dev_priv = dev->dev_private;
4204         int refclk = 27000; /* for DP & HDMI */
4205
4206         return 100000; /* only one validated so far */
4207
4208         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4209                 refclk = 96000;
4210         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4211                 if (intel_panel_use_ssc(dev_priv))
4212                         refclk = 100000;
4213                 else
4214                         refclk = 96000;
4215         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4216                 refclk = 100000;
4217         }
4218
4219         return refclk;
4220 }
4221
4222 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4223 {
4224         struct drm_device *dev = crtc->dev;
4225         struct drm_i915_private *dev_priv = dev->dev_private;
4226         int refclk;
4227
4228         if (IS_VALLEYVIEW(dev)) {
4229                 refclk = vlv_get_refclk(crtc);
4230         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4231             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4232                 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
4233                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4234                               refclk / 1000);
4235         } else if (!IS_GEN2(dev)) {
4236                 refclk = 96000;
4237         } else {
4238                 refclk = 48000;
4239         }
4240
4241         return refclk;
4242 }
4243
4244 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4245 {
4246         return (1 << dpll->n) << 16 | dpll->m2;
4247 }
4248
4249 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4250 {
4251         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4252 }
4253
4254 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4255                                      intel_clock_t *reduced_clock)
4256 {
4257         struct drm_device *dev = crtc->base.dev;
4258         struct drm_i915_private *dev_priv = dev->dev_private;
4259         int pipe = crtc->pipe;
4260         u32 fp, fp2 = 0;
4261
4262         if (IS_PINEVIEW(dev)) {
4263                 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
4264                 if (reduced_clock)
4265                         fp2 = pnv_dpll_compute_fp(reduced_clock);
4266         } else {
4267                 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
4268                 if (reduced_clock)
4269                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
4270         }
4271
4272         I915_WRITE(FP0(pipe), fp);
4273
4274         crtc->lowfreq_avail = false;
4275         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4276             reduced_clock && i915_powersave) {
4277                 I915_WRITE(FP1(pipe), fp2);
4278                 crtc->lowfreq_avail = true;
4279         } else {
4280                 I915_WRITE(FP1(pipe), fp);
4281         }
4282 }
4283
4284 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4285 {
4286         u32 reg_val;
4287
4288         /*
4289          * PLLB opamp always calibrates to max value of 0x3f, force enable it
4290          * and set it to a reasonable value instead.
4291          */
4292         reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
4293         reg_val &= 0xffffff00;
4294         reg_val |= 0x00000030;
4295         vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4296
4297         reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
4298         reg_val &= 0x8cffffff;
4299         reg_val = 0x8c000000;
4300         vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4301
4302         reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
4303         reg_val &= 0xffffff00;
4304         vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4305
4306         reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
4307         reg_val &= 0x00ffffff;
4308         reg_val |= 0xb0000000;
4309         vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4310 }
4311
4312 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4313                                          struct intel_link_m_n *m_n)
4314 {
4315         struct drm_device *dev = crtc->base.dev;
4316         struct drm_i915_private *dev_priv = dev->dev_private;
4317         int pipe = crtc->pipe;
4318
4319         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4320         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4321         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4322         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
4323 }
4324
4325 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4326                                          struct intel_link_m_n *m_n)
4327 {
4328         struct drm_device *dev = crtc->base.dev;
4329         struct drm_i915_private *dev_priv = dev->dev_private;
4330         int pipe = crtc->pipe;
4331         enum transcoder transcoder = crtc->config.cpu_transcoder;
4332
4333         if (INTEL_INFO(dev)->gen >= 5) {
4334                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4335                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4336                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4337                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4338         } else {
4339                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4340                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4341                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4342                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
4343         }
4344 }
4345
4346 static void intel_dp_set_m_n(struct intel_crtc *crtc)
4347 {
4348         if (crtc->config.has_pch_encoder)
4349                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4350         else
4351                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4352 }
4353
4354 static void vlv_update_pll(struct intel_crtc *crtc)
4355 {
4356         struct drm_device *dev = crtc->base.dev;
4357         struct drm_i915_private *dev_priv = dev->dev_private;
4358         struct intel_encoder *encoder;
4359         int pipe = crtc->pipe;
4360         u32 dpll, mdiv;
4361         u32 bestn, bestm1, bestm2, bestp1, bestp2;
4362         bool is_hdmi;
4363         u32 coreclk, reg_val, dpll_md;
4364
4365         mutex_lock(&dev_priv->dpio_lock);
4366
4367         is_hdmi = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4368
4369         bestn = crtc->config.dpll.n;
4370         bestm1 = crtc->config.dpll.m1;
4371         bestm2 = crtc->config.dpll.m2;
4372         bestp1 = crtc->config.dpll.p1;
4373         bestp2 = crtc->config.dpll.p2;
4374
4375         /* See eDP HDMI DPIO driver vbios notes doc */
4376
4377         /* PLL B needs special handling */
4378         if (pipe)
4379                 vlv_pllb_recal_opamp(dev_priv);
4380
4381         /* Set up Tx target for periodic Rcomp update */
4382         vlv_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
4383
4384         /* Disable target IRef on PLL */
4385         reg_val = vlv_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
4386         reg_val &= 0x00ffffff;
4387         vlv_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
4388
4389         /* Disable fast lock */
4390         vlv_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
4391
4392         /* Set idtafcrecal before PLL is enabled */
4393         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4394         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4395         mdiv |= ((bestn << DPIO_N_SHIFT));
4396         mdiv |= (1 << DPIO_K_SHIFT);
4397
4398         /*
4399          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4400          * but we don't support that).
4401          * Note: don't use the DAC post divider as it seems unstable.
4402          */
4403         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
4404         vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4405
4406         mdiv |= DPIO_ENABLE_CALIBRATION;
4407         vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4408
4409         /* Set HBR and RBR LPF coefficients */
4410         if (crtc->config.port_clock == 162000 ||
4411             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4412                 vlv_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
4413                                  0x005f0021);
4414         else
4415                 vlv_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
4416                                  0x00d0000f);
4417
4418         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4419             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4420                 /* Use SSC source */
4421                 if (!pipe)
4422                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4423                                          0x0df40000);
4424                 else
4425                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4426                                          0x0df70000);
4427         } else { /* HDMI or VGA */
4428                 /* Use bend source */
4429                 if (!pipe)
4430                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4431                                          0x0df70000);
4432                 else
4433                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4434                                          0x0df40000);
4435         }
4436
4437         coreclk = vlv_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
4438         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4439         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4440             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4441                 coreclk |= 0x01000000;
4442         vlv_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
4443
4444         vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
4445
4446         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4447                 if (encoder->pre_pll_enable)
4448                         encoder->pre_pll_enable(encoder);
4449
4450         /* Enable DPIO clock input */
4451         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4452                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4453         if (pipe)
4454                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
4455
4456         dpll |= DPLL_VCO_ENABLE;
4457         I915_WRITE(DPLL(pipe), dpll);
4458         POSTING_READ(DPLL(pipe));
4459         udelay(150);
4460
4461         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4462                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4463
4464         dpll_md = (crtc->config.pixel_multiplier - 1)
4465                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4466         I915_WRITE(DPLL_MD(pipe), dpll_md);
4467         POSTING_READ(DPLL_MD(pipe));
4468
4469         if (crtc->config.has_dp_encoder)
4470                 intel_dp_set_m_n(crtc);
4471
4472         mutex_unlock(&dev_priv->dpio_lock);
4473 }
4474
4475 static void i9xx_update_pll(struct intel_crtc *crtc,
4476                             intel_clock_t *reduced_clock,
4477                             int num_connectors)
4478 {
4479         struct drm_device *dev = crtc->base.dev;
4480         struct drm_i915_private *dev_priv = dev->dev_private;
4481         struct intel_encoder *encoder;
4482         int pipe = crtc->pipe;
4483         u32 dpll;
4484         bool is_sdvo;
4485         struct dpll *clock = &crtc->config.dpll;
4486
4487         i9xx_update_pll_dividers(crtc, reduced_clock);
4488
4489         is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4490                 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4491
4492         dpll = DPLL_VGA_MODE_DIS;
4493
4494         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
4495                 dpll |= DPLLB_MODE_LVDS;
4496         else
4497                 dpll |= DPLLB_MODE_DAC_SERIAL;
4498
4499         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
4500                 dpll |= (crtc->config.pixel_multiplier - 1)
4501                         << SDVO_MULTIPLIER_SHIFT_HIRES;
4502         }
4503
4504         if (is_sdvo)
4505                 dpll |= DPLL_DVO_HIGH_SPEED;
4506
4507         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4508                 dpll |= DPLL_DVO_HIGH_SPEED;
4509
4510         /* compute bitmask from p1 value */
4511         if (IS_PINEVIEW(dev))
4512                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4513         else {
4514                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4515                 if (IS_G4X(dev) && reduced_clock)
4516                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4517         }
4518         switch (clock->p2) {
4519         case 5:
4520                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4521                 break;
4522         case 7:
4523                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4524                 break;
4525         case 10:
4526                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4527                 break;
4528         case 14:
4529                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4530                 break;
4531         }
4532         if (INTEL_INFO(dev)->gen >= 4)
4533                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4534
4535         if (crtc->config.sdvo_tv_clock)
4536                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4537         else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4538                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4539                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4540         else
4541                 dpll |= PLL_REF_INPUT_DREFCLK;
4542
4543         dpll |= DPLL_VCO_ENABLE;
4544         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4545         POSTING_READ(DPLL(pipe));
4546         udelay(150);
4547
4548         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4549                 if (encoder->pre_pll_enable)
4550                         encoder->pre_pll_enable(encoder);
4551
4552         if (crtc->config.has_dp_encoder)
4553                 intel_dp_set_m_n(crtc);
4554
4555         I915_WRITE(DPLL(pipe), dpll);
4556
4557         /* Wait for the clocks to stabilize. */
4558         POSTING_READ(DPLL(pipe));
4559         udelay(150);
4560
4561         if (INTEL_INFO(dev)->gen >= 4) {
4562                 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4563                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4564                 I915_WRITE(DPLL_MD(pipe), dpll_md);
4565         } else {
4566                 /* The pixel multiplier can only be updated once the
4567                  * DPLL is enabled and the clocks are stable.
4568                  *
4569                  * So write it again.
4570                  */
4571                 I915_WRITE(DPLL(pipe), dpll);
4572         }
4573 }
4574
4575 static void i8xx_update_pll(struct intel_crtc *crtc,
4576                             intel_clock_t *reduced_clock,
4577                             int num_connectors)
4578 {
4579         struct drm_device *dev = crtc->base.dev;
4580         struct drm_i915_private *dev_priv = dev->dev_private;
4581         struct intel_encoder *encoder;
4582         int pipe = crtc->pipe;
4583         u32 dpll;
4584         struct dpll *clock = &crtc->config.dpll;
4585
4586         i9xx_update_pll_dividers(crtc, reduced_clock);
4587
4588         dpll = DPLL_VGA_MODE_DIS;
4589
4590         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
4591                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4592         } else {
4593                 if (clock->p1 == 2)
4594                         dpll |= PLL_P1_DIVIDE_BY_TWO;
4595                 else
4596                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4597                 if (clock->p2 == 4)
4598                         dpll |= PLL_P2_DIVIDE_BY_4;
4599         }
4600
4601         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4602                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4603                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4604         else
4605                 dpll |= PLL_REF_INPUT_DREFCLK;
4606
4607         dpll |= DPLL_VCO_ENABLE;
4608         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4609         POSTING_READ(DPLL(pipe));
4610         udelay(150);
4611
4612         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4613                 if (encoder->pre_pll_enable)
4614                         encoder->pre_pll_enable(encoder);
4615
4616         I915_WRITE(DPLL(pipe), dpll);
4617
4618         /* Wait for the clocks to stabilize. */
4619         POSTING_READ(DPLL(pipe));
4620         udelay(150);
4621
4622         /* The pixel multiplier can only be updated once the
4623          * DPLL is enabled and the clocks are stable.
4624          *
4625          * So write it again.
4626          */
4627         I915_WRITE(DPLL(pipe), dpll);
4628 }
4629
4630 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
4631 {
4632         struct drm_device *dev = intel_crtc->base.dev;
4633         struct drm_i915_private *dev_priv = dev->dev_private;
4634         enum pipe pipe = intel_crtc->pipe;
4635         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4636         struct drm_display_mode *adjusted_mode =
4637                 &intel_crtc->config.adjusted_mode;
4638         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4639         uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4640
4641         /* We need to be careful not to changed the adjusted mode, for otherwise
4642          * the hw state checker will get angry at the mismatch. */
4643         crtc_vtotal = adjusted_mode->crtc_vtotal;
4644         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
4645
4646         if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4647                 /* the chip adds 2 halflines automatically */
4648                 crtc_vtotal -= 1;
4649                 crtc_vblank_end -= 1;
4650                 vsyncshift = adjusted_mode->crtc_hsync_start
4651                              - adjusted_mode->crtc_htotal / 2;
4652         } else {
4653                 vsyncshift = 0;
4654         }
4655
4656         if (INTEL_INFO(dev)->gen > 3)
4657                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4658
4659         I915_WRITE(HTOTAL(cpu_transcoder),
4660                    (adjusted_mode->crtc_hdisplay - 1) |
4661                    ((adjusted_mode->crtc_htotal - 1) << 16));
4662         I915_WRITE(HBLANK(cpu_transcoder),
4663                    (adjusted_mode->crtc_hblank_start - 1) |
4664                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4665         I915_WRITE(HSYNC(cpu_transcoder),
4666                    (adjusted_mode->crtc_hsync_start - 1) |
4667                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4668
4669         I915_WRITE(VTOTAL(cpu_transcoder),
4670                    (adjusted_mode->crtc_vdisplay - 1) |
4671                    ((crtc_vtotal - 1) << 16));
4672         I915_WRITE(VBLANK(cpu_transcoder),
4673                    (adjusted_mode->crtc_vblank_start - 1) |
4674                    ((crtc_vblank_end - 1) << 16));
4675         I915_WRITE(VSYNC(cpu_transcoder),
4676                    (adjusted_mode->crtc_vsync_start - 1) |
4677                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4678
4679         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4680          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4681          * documented on the DDI_FUNC_CTL register description, EDP Input Select
4682          * bits. */
4683         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4684             (pipe == PIPE_B || pipe == PIPE_C))
4685                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4686
4687         /* pipesrc controls the size that is scaled from, which should
4688          * always be the user's requested size.
4689          */
4690         I915_WRITE(PIPESRC(pipe),
4691                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4692 }
4693
4694 static void intel_get_pipe_timings(struct intel_crtc *crtc,
4695                                    struct intel_crtc_config *pipe_config)
4696 {
4697         struct drm_device *dev = crtc->base.dev;
4698         struct drm_i915_private *dev_priv = dev->dev_private;
4699         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4700         uint32_t tmp;
4701
4702         tmp = I915_READ(HTOTAL(cpu_transcoder));
4703         pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4704         pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4705         tmp = I915_READ(HBLANK(cpu_transcoder));
4706         pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4707         pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4708         tmp = I915_READ(HSYNC(cpu_transcoder));
4709         pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4710         pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4711
4712         tmp = I915_READ(VTOTAL(cpu_transcoder));
4713         pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4714         pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4715         tmp = I915_READ(VBLANK(cpu_transcoder));
4716         pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4717         pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4718         tmp = I915_READ(VSYNC(cpu_transcoder));
4719         pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4720         pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4721
4722         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4723                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4724                 pipe_config->adjusted_mode.crtc_vtotal += 1;
4725                 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4726         }
4727
4728         tmp = I915_READ(PIPESRC(crtc->pipe));
4729         pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4730         pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4731 }
4732
4733 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4734 {
4735         struct drm_device *dev = intel_crtc->base.dev;
4736         struct drm_i915_private *dev_priv = dev->dev_private;
4737         uint32_t pipeconf;
4738
4739         pipeconf = 0;
4740
4741         if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4742                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4743                  * core speed.
4744                  *
4745                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4746                  * pipe == 0 check?
4747                  */
4748                 if (intel_crtc->config.requested_mode.clock >
4749                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4750                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4751         }
4752
4753         /* only g4x and later have fancy bpc/dither controls */
4754         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
4755                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4756                 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4757                         pipeconf |= PIPECONF_DITHER_EN |
4758                                     PIPECONF_DITHER_TYPE_SP;
4759
4760                 switch (intel_crtc->config.pipe_bpp) {
4761                 case 18:
4762                         pipeconf |= PIPECONF_6BPC;
4763                         break;
4764                 case 24:
4765                         pipeconf |= PIPECONF_8BPC;
4766                         break;
4767                 case 30:
4768                         pipeconf |= PIPECONF_10BPC;
4769                         break;
4770                 default:
4771                         /* Case prevented by intel_choose_pipe_bpp_dither. */
4772                         BUG();
4773                 }
4774         }
4775
4776         if (HAS_PIPE_CXSR(dev)) {
4777                 if (intel_crtc->lowfreq_avail) {
4778                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4779                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4780                 } else {
4781                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4782                 }
4783         }
4784
4785         if (!IS_GEN2(dev) &&
4786             intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4787                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4788         else
4789                 pipeconf |= PIPECONF_PROGRESSIVE;
4790
4791         if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
4792                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4793
4794         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4795         POSTING_READ(PIPECONF(intel_crtc->pipe));
4796 }
4797
4798 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4799                               int x, int y,
4800                               struct drm_framebuffer *fb)
4801 {
4802         struct drm_device *dev = crtc->dev;
4803         struct drm_i915_private *dev_priv = dev->dev_private;
4804         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4805         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4806         int pipe = intel_crtc->pipe;
4807         int plane = intel_crtc->plane;
4808         int refclk, num_connectors = 0;
4809         intel_clock_t clock, reduced_clock;
4810         u32 dspcntr;
4811         bool ok, has_reduced_clock = false;
4812         bool is_lvds = false;
4813         struct intel_encoder *encoder;
4814         const intel_limit_t *limit;
4815         int ret;
4816
4817         for_each_encoder_on_crtc(dev, crtc, encoder) {
4818                 switch (encoder->type) {
4819                 case INTEL_OUTPUT_LVDS:
4820                         is_lvds = true;
4821                         break;
4822                 }
4823
4824                 num_connectors++;
4825         }
4826
4827         refclk = i9xx_get_refclk(crtc, num_connectors);
4828
4829         /*
4830          * Returns a set of divisors for the desired target clock with the given
4831          * refclk, or FALSE.  The returned values represent the clock equation:
4832          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4833          */
4834         limit = intel_limit(crtc, refclk);
4835         ok = dev_priv->display.find_dpll(limit, crtc,
4836                                          intel_crtc->config.port_clock,
4837                                          refclk, NULL, &clock);
4838         if (!ok && !intel_crtc->config.clock_set) {
4839                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4840                 return -EINVAL;
4841         }
4842
4843         /* Ensure that the cursor is valid for the new mode before changing... */
4844         intel_crtc_update_cursor(crtc, true);
4845
4846         if (is_lvds && dev_priv->lvds_downclock_avail) {
4847                 /*
4848                  * Ensure we match the reduced clock's P to the target clock.
4849                  * If the clocks don't match, we can't switch the display clock
4850                  * by using the FP0/FP1. In such case we will disable the LVDS
4851                  * downclock feature.
4852                 */
4853                 has_reduced_clock =
4854                         dev_priv->display.find_dpll(limit, crtc,
4855                                                     dev_priv->lvds_downclock,
4856                                                     refclk, &clock,
4857                                                     &reduced_clock);
4858         }
4859         /* Compat-code for transition, will disappear. */
4860         if (!intel_crtc->config.clock_set) {
4861                 intel_crtc->config.dpll.n = clock.n;
4862                 intel_crtc->config.dpll.m1 = clock.m1;
4863                 intel_crtc->config.dpll.m2 = clock.m2;
4864                 intel_crtc->config.dpll.p1 = clock.p1;
4865                 intel_crtc->config.dpll.p2 = clock.p2;
4866         }
4867
4868         if (IS_GEN2(dev))
4869                 i8xx_update_pll(intel_crtc,
4870                                 has_reduced_clock ? &reduced_clock : NULL,
4871                                 num_connectors);
4872         else if (IS_VALLEYVIEW(dev))
4873                 vlv_update_pll(intel_crtc);
4874         else
4875                 i9xx_update_pll(intel_crtc,
4876                                 has_reduced_clock ? &reduced_clock : NULL,
4877                                 num_connectors);
4878
4879         /* Set up the display plane register */
4880         dspcntr = DISPPLANE_GAMMA_ENABLE;
4881
4882         if (!IS_VALLEYVIEW(dev)) {
4883                 if (pipe == 0)
4884                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4885                 else
4886                         dspcntr |= DISPPLANE_SEL_PIPE_B;
4887         }
4888
4889         intel_set_pipe_timings(intel_crtc);
4890
4891         /* pipesrc and dspsize control the size that is scaled from,
4892          * which should always be the user's requested size.
4893          */
4894         I915_WRITE(DSPSIZE(plane),
4895                    ((mode->vdisplay - 1) << 16) |
4896                    (mode->hdisplay - 1));
4897         I915_WRITE(DSPPOS(plane), 0);
4898
4899         i9xx_set_pipeconf(intel_crtc);
4900
4901         I915_WRITE(DSPCNTR(plane), dspcntr);
4902         POSTING_READ(DSPCNTR(plane));
4903
4904         ret = intel_pipe_set_base(crtc, x, y, fb);
4905
4906         intel_update_watermarks(dev);
4907
4908         return ret;
4909 }
4910
4911 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
4912                                  struct intel_crtc_config *pipe_config)
4913 {
4914         struct drm_device *dev = crtc->base.dev;
4915         struct drm_i915_private *dev_priv = dev->dev_private;
4916         uint32_t tmp;
4917
4918         tmp = I915_READ(PFIT_CONTROL);
4919
4920         if (INTEL_INFO(dev)->gen < 4) {
4921                 if (crtc->pipe != PIPE_B)
4922                         return;
4923
4924                 /* gen2/3 store dither state in pfit control, needs to match */
4925                 pipe_config->gmch_pfit.control = tmp & PANEL_8TO6_DITHER_ENABLE;
4926         } else {
4927                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
4928                         return;
4929         }
4930
4931         if (!(tmp & PFIT_ENABLE))
4932                 return;
4933
4934         pipe_config->gmch_pfit.control = I915_READ(PFIT_CONTROL);
4935         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
4936         if (INTEL_INFO(dev)->gen < 5)
4937                 pipe_config->gmch_pfit.lvds_border_bits =
4938                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
4939 }
4940
4941 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4942                                  struct intel_crtc_config *pipe_config)
4943 {
4944         struct drm_device *dev = crtc->base.dev;
4945         struct drm_i915_private *dev_priv = dev->dev_private;
4946         uint32_t tmp;
4947
4948         pipe_config->cpu_transcoder = crtc->pipe;
4949         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
4950
4951         tmp = I915_READ(PIPECONF(crtc->pipe));
4952         if (!(tmp & PIPECONF_ENABLE))
4953                 return false;
4954
4955         intel_get_pipe_timings(crtc, pipe_config);
4956
4957         i9xx_get_pfit_config(crtc, pipe_config);
4958
4959         if (INTEL_INFO(dev)->gen >= 4) {
4960                 tmp = I915_READ(DPLL_MD(crtc->pipe));
4961                 pipe_config->pixel_multiplier =
4962                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
4963                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
4964         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
4965                 tmp = I915_READ(DPLL(crtc->pipe));
4966                 pipe_config->pixel_multiplier =
4967                         ((tmp & SDVO_MULTIPLIER_MASK)
4968                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
4969         } else {
4970                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
4971                  * port and will be fixed up in the encoder->get_config
4972                  * function. */
4973                 pipe_config->pixel_multiplier = 1;
4974         }
4975
4976         return true;
4977 }
4978
4979 static void ironlake_init_pch_refclk(struct drm_device *dev)
4980 {
4981         struct drm_i915_private *dev_priv = dev->dev_private;
4982         struct drm_mode_config *mode_config = &dev->mode_config;
4983         struct intel_encoder *encoder;
4984         u32 val, final;
4985         bool has_lvds = false;
4986         bool has_cpu_edp = false;
4987         bool has_panel = false;
4988         bool has_ck505 = false;
4989         bool can_ssc = false;
4990
4991         /* We need to take the global config into account */
4992         list_for_each_entry(encoder, &mode_config->encoder_list,
4993                             base.head) {
4994                 switch (encoder->type) {
4995                 case INTEL_OUTPUT_LVDS:
4996                         has_panel = true;
4997                         has_lvds = true;
4998                         break;
4999                 case INTEL_OUTPUT_EDP:
5000                         has_panel = true;
5001                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5002                                 has_cpu_edp = true;
5003                         break;
5004                 }
5005         }
5006
5007         if (HAS_PCH_IBX(dev)) {
5008                 has_ck505 = dev_priv->vbt.display_clock_mode;
5009                 can_ssc = has_ck505;
5010         } else {
5011                 has_ck505 = false;
5012                 can_ssc = true;
5013         }
5014
5015         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5016                       has_panel, has_lvds, has_ck505);
5017
5018         /* Ironlake: try to setup display ref clock before DPLL
5019          * enabling. This is only under driver's control after
5020          * PCH B stepping, previous chipset stepping should be
5021          * ignoring this setting.
5022          */
5023         val = I915_READ(PCH_DREF_CONTROL);
5024
5025         /* As we must carefully and slowly disable/enable each source in turn,
5026          * compute the final state we want first and check if we need to
5027          * make any changes at all.
5028          */
5029         final = val;
5030         final &= ~DREF_NONSPREAD_SOURCE_MASK;
5031         if (has_ck505)
5032                 final |= DREF_NONSPREAD_CK505_ENABLE;
5033         else
5034                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5035
5036         final &= ~DREF_SSC_SOURCE_MASK;
5037         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5038         final &= ~DREF_SSC1_ENABLE;
5039
5040         if (has_panel) {
5041                 final |= DREF_SSC_SOURCE_ENABLE;
5042
5043                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5044                         final |= DREF_SSC1_ENABLE;
5045
5046                 if (has_cpu_edp) {
5047                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
5048                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5049                         else
5050                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5051                 } else
5052                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5053         } else {
5054                 final |= DREF_SSC_SOURCE_DISABLE;
5055                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5056         }
5057
5058         if (final == val)
5059                 return;
5060
5061         /* Always enable nonspread source */
5062         val &= ~DREF_NONSPREAD_SOURCE_MASK;
5063
5064         if (has_ck505)
5065                 val |= DREF_NONSPREAD_CK505_ENABLE;
5066         else
5067                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5068
5069         if (has_panel) {
5070                 val &= ~DREF_SSC_SOURCE_MASK;
5071                 val |= DREF_SSC_SOURCE_ENABLE;
5072
5073                 /* SSC must be turned on before enabling the CPU output  */
5074                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5075                         DRM_DEBUG_KMS("Using SSC on panel\n");
5076                         val |= DREF_SSC1_ENABLE;
5077                 } else
5078                         val &= ~DREF_SSC1_ENABLE;
5079
5080                 /* Get SSC going before enabling the outputs */
5081                 I915_WRITE(PCH_DREF_CONTROL, val);
5082                 POSTING_READ(PCH_DREF_CONTROL);
5083                 udelay(200);
5084
5085                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5086
5087                 /* Enable CPU source on CPU attached eDP */
5088                 if (has_cpu_edp) {
5089                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5090                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
5091                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5092                         }
5093                         else
5094                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5095                 } else
5096                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5097
5098                 I915_WRITE(PCH_DREF_CONTROL, val);
5099                 POSTING_READ(PCH_DREF_CONTROL);
5100                 udelay(200);
5101         } else {
5102                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5103
5104                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5105
5106                 /* Turn off CPU output */
5107                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5108
5109                 I915_WRITE(PCH_DREF_CONTROL, val);
5110                 POSTING_READ(PCH_DREF_CONTROL);
5111                 udelay(200);
5112
5113                 /* Turn off the SSC source */
5114                 val &= ~DREF_SSC_SOURCE_MASK;
5115                 val |= DREF_SSC_SOURCE_DISABLE;
5116
5117                 /* Turn off SSC1 */
5118                 val &= ~DREF_SSC1_ENABLE;
5119
5120                 I915_WRITE(PCH_DREF_CONTROL, val);
5121                 POSTING_READ(PCH_DREF_CONTROL);
5122                 udelay(200);
5123         }
5124
5125         BUG_ON(val != final);
5126 }
5127
5128 /* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
5129 static void lpt_init_pch_refclk(struct drm_device *dev)
5130 {
5131         struct drm_i915_private *dev_priv = dev->dev_private;
5132         struct drm_mode_config *mode_config = &dev->mode_config;
5133         struct intel_encoder *encoder;
5134         bool has_vga = false;
5135         bool is_sdv = false;
5136         u32 tmp;
5137
5138         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5139                 switch (encoder->type) {
5140                 case INTEL_OUTPUT_ANALOG:
5141                         has_vga = true;
5142                         break;
5143                 }
5144         }
5145
5146         if (!has_vga)
5147                 return;
5148
5149         mutex_lock(&dev_priv->dpio_lock);
5150
5151         /* XXX: Rip out SDV support once Haswell ships for real. */
5152         if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
5153                 is_sdv = true;
5154
5155         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5156         tmp &= ~SBI_SSCCTL_DISABLE;
5157         tmp |= SBI_SSCCTL_PATHALT;
5158         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5159
5160         udelay(24);
5161
5162         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5163         tmp &= ~SBI_SSCCTL_PATHALT;
5164         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5165
5166         if (!is_sdv) {
5167                 tmp = I915_READ(SOUTH_CHICKEN2);
5168                 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5169                 I915_WRITE(SOUTH_CHICKEN2, tmp);
5170
5171                 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5172                                        FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5173                         DRM_ERROR("FDI mPHY reset assert timeout\n");
5174
5175                 tmp = I915_READ(SOUTH_CHICKEN2);
5176                 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5177                 I915_WRITE(SOUTH_CHICKEN2, tmp);
5178
5179                 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5180                                         FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
5181                                        100))
5182                         DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5183         }
5184
5185         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5186         tmp &= ~(0xFF << 24);
5187         tmp |= (0x12 << 24);
5188         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5189
5190         if (is_sdv) {
5191                 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
5192                 tmp |= 0x7FFF;
5193                 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
5194         }
5195
5196         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5197         tmp |= (1 << 11);
5198         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5199
5200         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5201         tmp |= (1 << 11);
5202         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5203
5204         if (is_sdv) {
5205                 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
5206                 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5207                 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
5208
5209                 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5210                 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5211                 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5212
5213                 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5214                 tmp |= (0x3F << 8);
5215                 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5216
5217                 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5218                 tmp |= (0x3F << 8);
5219                 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5220         }
5221
5222         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5223         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5224         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5225
5226         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5227         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5228         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5229
5230         if (!is_sdv) {
5231                 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5232                 tmp &= ~(7 << 13);
5233                 tmp |= (5 << 13);
5234                 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5235
5236                 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5237                 tmp &= ~(7 << 13);
5238                 tmp |= (5 << 13);
5239                 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5240         }
5241
5242         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5243         tmp &= ~0xFF;
5244         tmp |= 0x1C;
5245         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5246
5247         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5248         tmp &= ~0xFF;
5249         tmp |= 0x1C;
5250         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5251
5252         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5253         tmp &= ~(0xFF << 16);
5254         tmp |= (0x1C << 16);
5255         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5256
5257         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5258         tmp &= ~(0xFF << 16);
5259         tmp |= (0x1C << 16);
5260         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5261
5262         if (!is_sdv) {
5263                 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5264                 tmp |= (1 << 27);
5265                 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5266
5267                 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5268                 tmp |= (1 << 27);
5269                 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5270
5271                 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5272                 tmp &= ~(0xF << 28);
5273                 tmp |= (4 << 28);
5274                 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5275
5276                 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5277                 tmp &= ~(0xF << 28);
5278                 tmp |= (4 << 28);
5279                 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5280         }
5281
5282         /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5283         tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5284         tmp |= SBI_DBUFF0_ENABLE;
5285         intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
5286
5287         mutex_unlock(&dev_priv->dpio_lock);
5288 }
5289
5290 /*
5291  * Initialize reference clocks when the driver loads
5292  */
5293 void intel_init_pch_refclk(struct drm_device *dev)
5294 {
5295         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5296                 ironlake_init_pch_refclk(dev);
5297         else if (HAS_PCH_LPT(dev))
5298                 lpt_init_pch_refclk(dev);
5299 }
5300
5301 static int ironlake_get_refclk(struct drm_crtc *crtc)
5302 {
5303         struct drm_device *dev = crtc->dev;
5304         struct drm_i915_private *dev_priv = dev->dev_private;
5305         struct intel_encoder *encoder;
5306         int num_connectors = 0;
5307         bool is_lvds = false;
5308
5309         for_each_encoder_on_crtc(dev, crtc, encoder) {
5310                 switch (encoder->type) {
5311                 case INTEL_OUTPUT_LVDS:
5312                         is_lvds = true;
5313                         break;
5314                 }
5315                 num_connectors++;
5316         }
5317
5318         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5319                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5320                               dev_priv->vbt.lvds_ssc_freq);
5321                 return dev_priv->vbt.lvds_ssc_freq * 1000;
5322         }
5323
5324         return 120000;
5325 }
5326
5327 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
5328 {
5329         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5330         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5331         int pipe = intel_crtc->pipe;
5332         uint32_t val;
5333
5334         val = 0;
5335
5336         switch (intel_crtc->config.pipe_bpp) {
5337         case 18:
5338                 val |= PIPECONF_6BPC;
5339                 break;
5340         case 24:
5341                 val |= PIPECONF_8BPC;
5342                 break;
5343         case 30:
5344                 val |= PIPECONF_10BPC;
5345                 break;
5346         case 36:
5347                 val |= PIPECONF_12BPC;
5348                 break;
5349         default:
5350                 /* Case prevented by intel_choose_pipe_bpp_dither. */
5351                 BUG();
5352         }
5353
5354         if (intel_crtc->config.dither)
5355                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5356
5357         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5358                 val |= PIPECONF_INTERLACED_ILK;
5359         else
5360                 val |= PIPECONF_PROGRESSIVE;
5361
5362         if (intel_crtc->config.limited_color_range)
5363                 val |= PIPECONF_COLOR_RANGE_SELECT;
5364
5365         I915_WRITE(PIPECONF(pipe), val);
5366         POSTING_READ(PIPECONF(pipe));
5367 }
5368
5369 /*
5370  * Set up the pipe CSC unit.
5371  *
5372  * Currently only full range RGB to limited range RGB conversion
5373  * is supported, but eventually this should handle various
5374  * RGB<->YCbCr scenarios as well.
5375  */
5376 static void intel_set_pipe_csc(struct drm_crtc *crtc)
5377 {
5378         struct drm_device *dev = crtc->dev;
5379         struct drm_i915_private *dev_priv = dev->dev_private;
5380         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5381         int pipe = intel_crtc->pipe;
5382         uint16_t coeff = 0x7800; /* 1.0 */
5383
5384         /*
5385          * TODO: Check what kind of values actually come out of the pipe
5386          * with these coeff/postoff values and adjust to get the best
5387          * accuracy. Perhaps we even need to take the bpc value into
5388          * consideration.
5389          */
5390
5391         if (intel_crtc->config.limited_color_range)
5392                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5393
5394         /*
5395          * GY/GU and RY/RU should be the other way around according
5396          * to BSpec, but reality doesn't agree. Just set them up in
5397          * a way that results in the correct picture.
5398          */
5399         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5400         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5401
5402         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5403         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5404
5405         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5406         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5407
5408         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5409         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5410         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5411
5412         if (INTEL_INFO(dev)->gen > 6) {
5413                 uint16_t postoff = 0;
5414
5415                 if (intel_crtc->config.limited_color_range)
5416                         postoff = (16 * (1 << 13) / 255) & 0x1fff;
5417
5418                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5419                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5420                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5421
5422                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5423         } else {
5424                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5425
5426                 if (intel_crtc->config.limited_color_range)
5427                         mode |= CSC_BLACK_SCREEN_OFFSET;
5428
5429                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5430         }
5431 }
5432
5433 static void haswell_set_pipeconf(struct drm_crtc *crtc)
5434 {
5435         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5436         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5437         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5438         uint32_t val;
5439
5440         val = 0;
5441
5442         if (intel_crtc->config.dither)
5443                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5444
5445         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5446                 val |= PIPECONF_INTERLACED_ILK;
5447         else
5448                 val |= PIPECONF_PROGRESSIVE;
5449
5450         I915_WRITE(PIPECONF(cpu_transcoder), val);
5451         POSTING_READ(PIPECONF(cpu_transcoder));
5452
5453         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
5454         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
5455 }
5456
5457 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5458                                     intel_clock_t *clock,
5459                                     bool *has_reduced_clock,
5460                                     intel_clock_t *reduced_clock)
5461 {
5462         struct drm_device *dev = crtc->dev;
5463         struct drm_i915_private *dev_priv = dev->dev_private;
5464         struct intel_encoder *intel_encoder;
5465         int refclk;
5466         const intel_limit_t *limit;
5467         bool ret, is_lvds = false;
5468
5469         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5470                 switch (intel_encoder->type) {
5471                 case INTEL_OUTPUT_LVDS:
5472                         is_lvds = true;
5473                         break;
5474                 }
5475         }
5476
5477         refclk = ironlake_get_refclk(crtc);
5478
5479         /*
5480          * Returns a set of divisors for the desired target clock with the given
5481          * refclk, or FALSE.  The returned values represent the clock equation:
5482          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5483          */
5484         limit = intel_limit(crtc, refclk);
5485         ret = dev_priv->display.find_dpll(limit, crtc,
5486                                           to_intel_crtc(crtc)->config.port_clock,
5487                                           refclk, NULL, clock);
5488         if (!ret)
5489                 return false;
5490
5491         if (is_lvds && dev_priv->lvds_downclock_avail) {
5492                 /*
5493                  * Ensure we match the reduced clock's P to the target clock.
5494                  * If the clocks don't match, we can't switch the display clock
5495                  * by using the FP0/FP1. In such case we will disable the LVDS
5496                  * downclock feature.
5497                 */
5498                 *has_reduced_clock =
5499                         dev_priv->display.find_dpll(limit, crtc,
5500                                                     dev_priv->lvds_downclock,
5501                                                     refclk, clock,
5502                                                     reduced_clock);
5503         }
5504
5505         return true;
5506 }
5507
5508 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5509 {
5510         struct drm_i915_private *dev_priv = dev->dev_private;
5511         uint32_t temp;
5512
5513         temp = I915_READ(SOUTH_CHICKEN1);
5514         if (temp & FDI_BC_BIFURCATION_SELECT)
5515                 return;
5516
5517         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5518         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5519
5520         temp |= FDI_BC_BIFURCATION_SELECT;
5521         DRM_DEBUG_KMS("enabling fdi C rx\n");
5522         I915_WRITE(SOUTH_CHICKEN1, temp);
5523         POSTING_READ(SOUTH_CHICKEN1);
5524 }
5525
5526 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
5527 {
5528         struct drm_device *dev = intel_crtc->base.dev;
5529         struct drm_i915_private *dev_priv = dev->dev_private;
5530
5531         switch (intel_crtc->pipe) {
5532         case PIPE_A:
5533                 break;
5534         case PIPE_B:
5535                 if (intel_crtc->config.fdi_lanes > 2)
5536                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5537                 else
5538                         cpt_enable_fdi_bc_bifurcation(dev);
5539
5540                 break;
5541         case PIPE_C:
5542                 cpt_enable_fdi_bc_bifurcation(dev);
5543
5544                 break;
5545         default:
5546                 BUG();
5547         }
5548 }
5549
5550 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5551 {
5552         /*
5553          * Account for spread spectrum to avoid
5554          * oversubscribing the link. Max center spread
5555          * is 2.5%; use 5% for safety's sake.
5556          */
5557         u32 bps = target_clock * bpp * 21 / 20;
5558         return bps / (link_bw * 8) + 1;
5559 }
5560
5561 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5562 {
5563         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5564 }
5565
5566 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5567                                       u32 *fp,
5568                                       intel_clock_t *reduced_clock, u32 *fp2)
5569 {
5570         struct drm_crtc *crtc = &intel_crtc->base;
5571         struct drm_device *dev = crtc->dev;
5572         struct drm_i915_private *dev_priv = dev->dev_private;
5573         struct intel_encoder *intel_encoder;
5574         uint32_t dpll;
5575         int factor, num_connectors = 0;
5576         bool is_lvds = false, is_sdvo = false;
5577
5578         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5579                 switch (intel_encoder->type) {
5580                 case INTEL_OUTPUT_LVDS:
5581                         is_lvds = true;
5582                         break;
5583                 case INTEL_OUTPUT_SDVO:
5584                 case INTEL_OUTPUT_HDMI:
5585                         is_sdvo = true;
5586                         break;
5587                 }
5588
5589                 num_connectors++;
5590         }
5591
5592         /* Enable autotuning of the PLL clock (if permissible) */
5593         factor = 21;
5594         if (is_lvds) {
5595                 if ((intel_panel_use_ssc(dev_priv) &&
5596                      dev_priv->vbt.lvds_ssc_freq == 100) ||
5597                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
5598                         factor = 25;
5599         } else if (intel_crtc->config.sdvo_tv_clock)
5600                 factor = 20;
5601
5602         if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
5603                 *fp |= FP_CB_TUNE;
5604
5605         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5606                 *fp2 |= FP_CB_TUNE;
5607
5608         dpll = 0;
5609
5610         if (is_lvds)
5611                 dpll |= DPLLB_MODE_LVDS;
5612         else
5613                 dpll |= DPLLB_MODE_DAC_SERIAL;
5614
5615         dpll |= (intel_crtc->config.pixel_multiplier - 1)
5616                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5617
5618         if (is_sdvo)
5619                 dpll |= DPLL_DVO_HIGH_SPEED;
5620         if (intel_crtc->config.has_dp_encoder)
5621                 dpll |= DPLL_DVO_HIGH_SPEED;
5622
5623         /* compute bitmask from p1 value */
5624         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5625         /* also FPA1 */
5626         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5627
5628         switch (intel_crtc->config.dpll.p2) {
5629         case 5:
5630                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5631                 break;
5632         case 7:
5633                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5634                 break;
5635         case 10:
5636                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5637                 break;
5638         case 14:
5639                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5640                 break;
5641         }
5642
5643         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5644                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5645         else
5646                 dpll |= PLL_REF_INPUT_DREFCLK;
5647
5648         return dpll | DPLL_VCO_ENABLE;
5649 }
5650
5651 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5652                                   int x, int y,
5653                                   struct drm_framebuffer *fb)
5654 {
5655         struct drm_device *dev = crtc->dev;
5656         struct drm_i915_private *dev_priv = dev->dev_private;
5657         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5658         int pipe = intel_crtc->pipe;
5659         int plane = intel_crtc->plane;
5660         int num_connectors = 0;
5661         intel_clock_t clock, reduced_clock;
5662         u32 dpll = 0, fp = 0, fp2 = 0;
5663         bool ok, has_reduced_clock = false;
5664         bool is_lvds = false;
5665         struct intel_encoder *encoder;
5666         struct intel_shared_dpll *pll;
5667         int ret;
5668
5669         for_each_encoder_on_crtc(dev, crtc, encoder) {
5670                 switch (encoder->type) {
5671                 case INTEL_OUTPUT_LVDS:
5672                         is_lvds = true;
5673                         break;
5674                 }
5675
5676                 num_connectors++;
5677         }
5678
5679         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5680              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5681
5682         ok = ironlake_compute_clocks(crtc, &clock,
5683                                      &has_reduced_clock, &reduced_clock);
5684         if (!ok && !intel_crtc->config.clock_set) {
5685                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5686                 return -EINVAL;
5687         }
5688         /* Compat-code for transition, will disappear. */
5689         if (!intel_crtc->config.clock_set) {
5690                 intel_crtc->config.dpll.n = clock.n;
5691                 intel_crtc->config.dpll.m1 = clock.m1;
5692                 intel_crtc->config.dpll.m2 = clock.m2;
5693                 intel_crtc->config.dpll.p1 = clock.p1;
5694                 intel_crtc->config.dpll.p2 = clock.p2;
5695         }
5696
5697         /* Ensure that the cursor is valid for the new mode before changing... */
5698         intel_crtc_update_cursor(crtc, true);
5699
5700         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5701         if (intel_crtc->config.has_pch_encoder) {
5702                 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
5703                 if (has_reduced_clock)
5704                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
5705
5706                 dpll = ironlake_compute_dpll(intel_crtc,
5707                                              &fp, &reduced_clock,
5708                                              has_reduced_clock ? &fp2 : NULL);
5709
5710                 intel_crtc->config.dpll_hw_state.dpll = dpll;
5711                 intel_crtc->config.dpll_hw_state.fp0 = fp;
5712                 if (has_reduced_clock)
5713                         intel_crtc->config.dpll_hw_state.fp1 = fp2;
5714                 else
5715                         intel_crtc->config.dpll_hw_state.fp1 = fp;
5716
5717                 pll = intel_get_shared_dpll(intel_crtc, dpll, fp);
5718                 if (pll == NULL) {
5719                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5720                                          pipe_name(pipe));
5721                         return -EINVAL;
5722                 }
5723         } else
5724                 intel_put_shared_dpll(intel_crtc);
5725
5726         if (intel_crtc->config.has_dp_encoder)
5727                 intel_dp_set_m_n(intel_crtc);
5728
5729         for_each_encoder_on_crtc(dev, crtc, encoder)
5730                 if (encoder->pre_pll_enable)
5731                         encoder->pre_pll_enable(encoder);
5732
5733         if (is_lvds && has_reduced_clock && i915_powersave)
5734                 intel_crtc->lowfreq_avail = true;
5735         else
5736                 intel_crtc->lowfreq_avail = false;
5737
5738         if (intel_crtc->config.has_pch_encoder) {
5739                 pll = intel_crtc_to_shared_dpll(intel_crtc);
5740
5741                 I915_WRITE(PCH_DPLL(pll->id), dpll);
5742
5743                 /* Wait for the clocks to stabilize. */
5744                 POSTING_READ(PCH_DPLL(pll->id));
5745                 udelay(150);
5746
5747                 /* The pixel multiplier can only be updated once the
5748                  * DPLL is enabled and the clocks are stable.
5749                  *
5750                  * So write it again.
5751                  */
5752                 I915_WRITE(PCH_DPLL(pll->id), dpll);
5753
5754                 if (has_reduced_clock)
5755                         I915_WRITE(PCH_FP1(pll->id), fp2);
5756                 else
5757                         I915_WRITE(PCH_FP1(pll->id), fp);
5758         }
5759
5760         intel_set_pipe_timings(intel_crtc);
5761
5762         if (intel_crtc->config.has_pch_encoder) {
5763                 intel_cpu_transcoder_set_m_n(intel_crtc,
5764                                              &intel_crtc->config.fdi_m_n);
5765         }
5766
5767         if (IS_IVYBRIDGE(dev))
5768                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
5769
5770         ironlake_set_pipeconf(crtc);
5771
5772         /* Set up the display plane register */
5773         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5774         POSTING_READ(DSPCNTR(plane));
5775
5776         ret = intel_pipe_set_base(crtc, x, y, fb);
5777
5778         intel_update_watermarks(dev);
5779
5780         return ret;
5781 }
5782
5783 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5784                                         struct intel_crtc_config *pipe_config)
5785 {
5786         struct drm_device *dev = crtc->base.dev;
5787         struct drm_i915_private *dev_priv = dev->dev_private;
5788         enum transcoder transcoder = pipe_config->cpu_transcoder;
5789
5790         pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
5791         pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
5792         pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5793                                         & ~TU_SIZE_MASK;
5794         pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5795         pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5796                                    & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5797 }
5798
5799 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5800                                      struct intel_crtc_config *pipe_config)
5801 {
5802         struct drm_device *dev = crtc->base.dev;
5803         struct drm_i915_private *dev_priv = dev->dev_private;
5804         uint32_t tmp;
5805
5806         tmp = I915_READ(PF_CTL(crtc->pipe));
5807
5808         if (tmp & PF_ENABLE) {
5809                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5810                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
5811
5812                 /* We currently do not free assignements of panel fitters on
5813                  * ivb/hsw (since we don't use the higher upscaling modes which
5814                  * differentiates them) so just WARN about this case for now. */
5815                 if (IS_GEN7(dev)) {
5816                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
5817                                 PF_PIPE_SEL_IVB(crtc->pipe));
5818                 }
5819         }
5820 }
5821
5822 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5823                                      struct intel_crtc_config *pipe_config)
5824 {
5825         struct drm_device *dev = crtc->base.dev;
5826         struct drm_i915_private *dev_priv = dev->dev_private;
5827         uint32_t tmp;
5828
5829         pipe_config->cpu_transcoder = crtc->pipe;
5830         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5831
5832         tmp = I915_READ(PIPECONF(crtc->pipe));
5833         if (!(tmp & PIPECONF_ENABLE))
5834                 return false;
5835
5836         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
5837                 struct intel_shared_dpll *pll;
5838
5839                 pipe_config->has_pch_encoder = true;
5840
5841                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5842                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5843                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
5844
5845                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
5846
5847                 /* XXX: Can't properly read out the pch dpll pixel multiplier
5848                  * since we don't have state tracking for pch clocks yet. */
5849                 pipe_config->pixel_multiplier = 1;
5850
5851                 if (HAS_PCH_IBX(dev_priv->dev)) {
5852                         pipe_config->shared_dpll = crtc->pipe;
5853                 } else {
5854                         tmp = I915_READ(PCH_DPLL_SEL);
5855                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
5856                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
5857                         else
5858                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
5859                 }
5860
5861                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
5862
5863                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
5864                                            &pipe_config->dpll_hw_state));
5865         } else {
5866                 pipe_config->pixel_multiplier = 1;
5867         }
5868
5869         intel_get_pipe_timings(crtc, pipe_config);
5870
5871         ironlake_get_pfit_config(crtc, pipe_config);
5872
5873         return true;
5874 }
5875
5876 static void haswell_modeset_global_resources(struct drm_device *dev)
5877 {
5878         bool enable = false;
5879         struct intel_crtc *crtc;
5880
5881         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
5882                 if (!crtc->base.enabled)
5883                         continue;
5884
5885                 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.size ||
5886                     crtc->config.cpu_transcoder != TRANSCODER_EDP)
5887                         enable = true;
5888         }
5889
5890         intel_set_power_well(dev, enable);
5891 }
5892
5893 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5894                                  int x, int y,
5895                                  struct drm_framebuffer *fb)
5896 {
5897         struct drm_device *dev = crtc->dev;
5898         struct drm_i915_private *dev_priv = dev->dev_private;
5899         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5900         int plane = intel_crtc->plane;
5901         int ret;
5902
5903         if (!intel_ddi_pll_mode_set(crtc))
5904                 return -EINVAL;
5905
5906         /* Ensure that the cursor is valid for the new mode before changing... */
5907         intel_crtc_update_cursor(crtc, true);
5908
5909         if (intel_crtc->config.has_dp_encoder)
5910                 intel_dp_set_m_n(intel_crtc);
5911
5912         intel_crtc->lowfreq_avail = false;
5913
5914         intel_set_pipe_timings(intel_crtc);
5915
5916         if (intel_crtc->config.has_pch_encoder) {
5917                 intel_cpu_transcoder_set_m_n(intel_crtc,
5918                                              &intel_crtc->config.fdi_m_n);
5919         }
5920
5921         haswell_set_pipeconf(crtc);
5922
5923         intel_set_pipe_csc(crtc);
5924
5925         /* Set up the display plane register */
5926         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
5927         POSTING_READ(DSPCNTR(plane));
5928
5929         ret = intel_pipe_set_base(crtc, x, y, fb);
5930
5931         intel_update_watermarks(dev);
5932
5933         return ret;
5934 }
5935
5936 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5937                                     struct intel_crtc_config *pipe_config)
5938 {
5939         struct drm_device *dev = crtc->base.dev;
5940         struct drm_i915_private *dev_priv = dev->dev_private;
5941         enum intel_display_power_domain pfit_domain;
5942         uint32_t tmp;
5943
5944         pipe_config->cpu_transcoder = crtc->pipe;
5945         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5946
5947         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
5948         if (tmp & TRANS_DDI_FUNC_ENABLE) {
5949                 enum pipe trans_edp_pipe;
5950                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
5951                 default:
5952                         WARN(1, "unknown pipe linked to edp transcoder\n");
5953                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
5954                 case TRANS_DDI_EDP_INPUT_A_ON:
5955                         trans_edp_pipe = PIPE_A;
5956                         break;
5957                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
5958                         trans_edp_pipe = PIPE_B;
5959                         break;
5960                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
5961                         trans_edp_pipe = PIPE_C;
5962                         break;
5963                 }
5964
5965                 if (trans_edp_pipe == crtc->pipe)
5966                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
5967         }
5968
5969         if (!intel_display_power_enabled(dev,
5970                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
5971                 return false;
5972
5973         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
5974         if (!(tmp & PIPECONF_ENABLE))
5975                 return false;
5976
5977         /*
5978          * Haswell has only FDI/PCH transcoder A. It is which is connected to
5979          * DDI E. So just check whether this pipe is wired to DDI E and whether
5980          * the PCH transcoder is on.
5981          */
5982         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
5983         if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
5984             I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
5985                 pipe_config->has_pch_encoder = true;
5986
5987                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
5988                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5989                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
5990
5991                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
5992         }
5993
5994         intel_get_pipe_timings(crtc, pipe_config);
5995
5996         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
5997         if (intel_display_power_enabled(dev, pfit_domain))
5998                 ironlake_get_pfit_config(crtc, pipe_config);
5999
6000         pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6001                                    (I915_READ(IPS_CTL) & IPS_ENABLE);
6002
6003         pipe_config->pixel_multiplier = 1;
6004
6005         return true;
6006 }
6007
6008 static int intel_crtc_mode_set(struct drm_crtc *crtc,
6009                                int x, int y,
6010                                struct drm_framebuffer *fb)
6011 {
6012         struct drm_device *dev = crtc->dev;
6013         struct drm_i915_private *dev_priv = dev->dev_private;
6014         struct drm_encoder_helper_funcs *encoder_funcs;
6015         struct intel_encoder *encoder;
6016         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6017         struct drm_display_mode *adjusted_mode =
6018                 &intel_crtc->config.adjusted_mode;
6019         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
6020         int pipe = intel_crtc->pipe;
6021         int ret;
6022
6023         drm_vblank_pre_modeset(dev, pipe);
6024
6025         ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6026
6027         drm_vblank_post_modeset(dev, pipe);
6028
6029         if (ret != 0)
6030                 return ret;
6031
6032         for_each_encoder_on_crtc(dev, crtc, encoder) {
6033                 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6034                         encoder->base.base.id,
6035                         drm_get_encoder_name(&encoder->base),
6036                         mode->base.id, mode->name);
6037                 if (encoder->mode_set) {
6038                         encoder->mode_set(encoder);
6039                 } else {
6040                         encoder_funcs = encoder->base.helper_private;
6041                         encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
6042                 }
6043         }
6044
6045         return 0;
6046 }
6047
6048 static bool intel_eld_uptodate(struct drm_connector *connector,
6049                                int reg_eldv, uint32_t bits_eldv,
6050                                int reg_elda, uint32_t bits_elda,
6051                                int reg_edid)
6052 {
6053         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6054         uint8_t *eld = connector->eld;
6055         uint32_t i;
6056
6057         i = I915_READ(reg_eldv);
6058         i &= bits_eldv;
6059
6060         if (!eld[0])
6061                 return !i;
6062
6063         if (!i)
6064                 return false;
6065
6066         i = I915_READ(reg_elda);
6067         i &= ~bits_elda;
6068         I915_WRITE(reg_elda, i);
6069
6070         for (i = 0; i < eld[2]; i++)
6071                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6072                         return false;
6073
6074         return true;
6075 }
6076
6077 static void g4x_write_eld(struct drm_connector *connector,
6078                           struct drm_crtc *crtc)
6079 {
6080         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6081         uint8_t *eld = connector->eld;
6082         uint32_t eldv;
6083         uint32_t len;
6084         uint32_t i;
6085
6086         i = I915_READ(G4X_AUD_VID_DID);
6087
6088         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6089                 eldv = G4X_ELDV_DEVCL_DEVBLC;
6090         else
6091                 eldv = G4X_ELDV_DEVCTG;
6092
6093         if (intel_eld_uptodate(connector,
6094                                G4X_AUD_CNTL_ST, eldv,
6095                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6096                                G4X_HDMIW_HDMIEDID))
6097                 return;
6098
6099         i = I915_READ(G4X_AUD_CNTL_ST);
6100         i &= ~(eldv | G4X_ELD_ADDR);
6101         len = (i >> 9) & 0x1f;          /* ELD buffer size */
6102         I915_WRITE(G4X_AUD_CNTL_ST, i);
6103
6104         if (!eld[0])
6105                 return;
6106
6107         len = min_t(uint8_t, eld[2], len);
6108         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6109         for (i = 0; i < len; i++)
6110                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6111
6112         i = I915_READ(G4X_AUD_CNTL_ST);
6113         i |= eldv;
6114         I915_WRITE(G4X_AUD_CNTL_ST, i);
6115 }
6116
6117 static void haswell_write_eld(struct drm_connector *connector,
6118                                      struct drm_crtc *crtc)
6119 {
6120         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6121         uint8_t *eld = connector->eld;
6122         struct drm_device *dev = crtc->dev;
6123         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6124         uint32_t eldv;
6125         uint32_t i;
6126         int len;
6127         int pipe = to_intel_crtc(crtc)->pipe;
6128         int tmp;
6129
6130         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6131         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6132         int aud_config = HSW_AUD_CFG(pipe);
6133         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6134
6135
6136         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6137
6138         /* Audio output enable */
6139         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6140         tmp = I915_READ(aud_cntrl_st2);
6141         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6142         I915_WRITE(aud_cntrl_st2, tmp);
6143
6144         /* Wait for 1 vertical blank */
6145         intel_wait_for_vblank(dev, pipe);
6146
6147         /* Set ELD valid state */
6148         tmp = I915_READ(aud_cntrl_st2);
6149         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6150         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6151         I915_WRITE(aud_cntrl_st2, tmp);
6152         tmp = I915_READ(aud_cntrl_st2);
6153         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6154
6155         /* Enable HDMI mode */
6156         tmp = I915_READ(aud_config);
6157         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6158         /* clear N_programing_enable and N_value_index */
6159         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6160         I915_WRITE(aud_config, tmp);
6161
6162         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6163
6164         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
6165         intel_crtc->eld_vld = true;
6166
6167         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6168                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6169                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6170                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6171         } else
6172                 I915_WRITE(aud_config, 0);
6173
6174         if (intel_eld_uptodate(connector,
6175                                aud_cntrl_st2, eldv,
6176                                aud_cntl_st, IBX_ELD_ADDRESS,
6177                                hdmiw_hdmiedid))
6178                 return;
6179
6180         i = I915_READ(aud_cntrl_st2);
6181         i &= ~eldv;
6182         I915_WRITE(aud_cntrl_st2, i);
6183
6184         if (!eld[0])
6185                 return;
6186
6187         i = I915_READ(aud_cntl_st);
6188         i &= ~IBX_ELD_ADDRESS;
6189         I915_WRITE(aud_cntl_st, i);
6190         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6191         DRM_DEBUG_DRIVER("port num:%d\n", i);
6192
6193         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6194         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6195         for (i = 0; i < len; i++)
6196                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6197
6198         i = I915_READ(aud_cntrl_st2);
6199         i |= eldv;
6200         I915_WRITE(aud_cntrl_st2, i);
6201
6202 }
6203
6204 static void ironlake_write_eld(struct drm_connector *connector,
6205                                      struct drm_crtc *crtc)
6206 {
6207         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6208         uint8_t *eld = connector->eld;
6209         uint32_t eldv;
6210         uint32_t i;
6211         int len;
6212         int hdmiw_hdmiedid;
6213         int aud_config;
6214         int aud_cntl_st;
6215         int aud_cntrl_st2;
6216         int pipe = to_intel_crtc(crtc)->pipe;
6217
6218         if (HAS_PCH_IBX(connector->dev)) {
6219                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6220                 aud_config = IBX_AUD_CFG(pipe);
6221                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6222                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6223         } else {
6224                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6225                 aud_config = CPT_AUD_CFG(pipe);
6226                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6227                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6228         }
6229
6230         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6231
6232         i = I915_READ(aud_cntl_st);
6233         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6234         if (!i) {
6235                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6236                 /* operate blindly on all ports */
6237                 eldv = IBX_ELD_VALIDB;
6238                 eldv |= IBX_ELD_VALIDB << 4;
6239                 eldv |= IBX_ELD_VALIDB << 8;
6240         } else {
6241                 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
6242                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6243         }
6244
6245         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6246                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6247                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6248                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6249         } else
6250                 I915_WRITE(aud_config, 0);
6251
6252         if (intel_eld_uptodate(connector,
6253                                aud_cntrl_st2, eldv,
6254                                aud_cntl_st, IBX_ELD_ADDRESS,
6255                                hdmiw_hdmiedid))
6256                 return;
6257
6258         i = I915_READ(aud_cntrl_st2);
6259         i &= ~eldv;
6260         I915_WRITE(aud_cntrl_st2, i);
6261
6262         if (!eld[0])
6263                 return;
6264
6265         i = I915_READ(aud_cntl_st);
6266         i &= ~IBX_ELD_ADDRESS;
6267         I915_WRITE(aud_cntl_st, i);
6268
6269         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6270         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6271         for (i = 0; i < len; i++)
6272                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6273
6274         i = I915_READ(aud_cntrl_st2);
6275         i |= eldv;
6276         I915_WRITE(aud_cntrl_st2, i);
6277 }
6278
6279 void intel_write_eld(struct drm_encoder *encoder,
6280                      struct drm_display_mode *mode)
6281 {
6282         struct drm_crtc *crtc = encoder->crtc;
6283         struct drm_connector *connector;
6284         struct drm_device *dev = encoder->dev;
6285         struct drm_i915_private *dev_priv = dev->dev_private;
6286
6287         connector = drm_select_eld(encoder, mode);
6288         if (!connector)
6289                 return;
6290
6291         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6292                          connector->base.id,
6293                          drm_get_connector_name(connector),
6294                          connector->encoder->base.id,
6295                          drm_get_encoder_name(connector->encoder));
6296
6297         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6298
6299         if (dev_priv->display.write_eld)
6300                 dev_priv->display.write_eld(connector, crtc);
6301 }
6302
6303 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6304 void intel_crtc_load_lut(struct drm_crtc *crtc)
6305 {
6306         struct drm_device *dev = crtc->dev;
6307         struct drm_i915_private *dev_priv = dev->dev_private;
6308         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6309         enum pipe pipe = intel_crtc->pipe;
6310         int palreg = PALETTE(pipe);
6311         int i;
6312         bool reenable_ips = false;
6313
6314         /* The clocks have to be on to load the palette. */
6315         if (!crtc->enabled || !intel_crtc->active)
6316                 return;
6317
6318         if (!HAS_PCH_SPLIT(dev_priv->dev))
6319                 assert_pll_enabled(dev_priv, pipe);
6320
6321         /* use legacy palette for Ironlake */
6322         if (HAS_PCH_SPLIT(dev))
6323                 palreg = LGC_PALETTE(pipe);
6324
6325         /* Workaround : Do not read or write the pipe palette/gamma data while
6326          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6327          */
6328         if (intel_crtc->config.ips_enabled &&
6329             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
6330              GAMMA_MODE_MODE_SPLIT)) {
6331                 hsw_disable_ips(intel_crtc);
6332                 reenable_ips = true;
6333         }
6334
6335         for (i = 0; i < 256; i++) {
6336                 I915_WRITE(palreg + 4 * i,
6337                            (intel_crtc->lut_r[i] << 16) |
6338                            (intel_crtc->lut_g[i] << 8) |
6339                            intel_crtc->lut_b[i]);
6340         }
6341
6342         if (reenable_ips)
6343                 hsw_enable_ips(intel_crtc);
6344 }
6345
6346 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6347 {
6348         struct drm_device *dev = crtc->dev;
6349         struct drm_i915_private *dev_priv = dev->dev_private;
6350         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6351         bool visible = base != 0;
6352         u32 cntl;
6353
6354         if (intel_crtc->cursor_visible == visible)
6355                 return;
6356
6357         cntl = I915_READ(_CURACNTR);
6358         if (visible) {
6359                 /* On these chipsets we can only modify the base whilst
6360                  * the cursor is disabled.
6361                  */
6362                 I915_WRITE(_CURABASE, base);
6363
6364                 cntl &= ~(CURSOR_FORMAT_MASK);
6365                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6366                 cntl |= CURSOR_ENABLE |
6367                         CURSOR_GAMMA_ENABLE |
6368                         CURSOR_FORMAT_ARGB;
6369         } else
6370                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6371         I915_WRITE(_CURACNTR, cntl);
6372
6373         intel_crtc->cursor_visible = visible;
6374 }
6375
6376 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6377 {
6378         struct drm_device *dev = crtc->dev;
6379         struct drm_i915_private *dev_priv = dev->dev_private;
6380         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6381         int pipe = intel_crtc->pipe;
6382         bool visible = base != 0;
6383
6384         if (intel_crtc->cursor_visible != visible) {
6385                 uint32_t cntl = I915_READ(CURCNTR(pipe));
6386                 if (base) {
6387                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6388                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6389                         cntl |= pipe << 28; /* Connect to correct pipe */
6390                 } else {
6391                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6392                         cntl |= CURSOR_MODE_DISABLE;
6393                 }
6394                 I915_WRITE(CURCNTR(pipe), cntl);
6395
6396                 intel_crtc->cursor_visible = visible;
6397         }
6398         /* and commit changes on next vblank */
6399         I915_WRITE(CURBASE(pipe), base);
6400 }
6401
6402 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6403 {
6404         struct drm_device *dev = crtc->dev;
6405         struct drm_i915_private *dev_priv = dev->dev_private;
6406         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6407         int pipe = intel_crtc->pipe;
6408         bool visible = base != 0;
6409
6410         if (intel_crtc->cursor_visible != visible) {
6411                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6412                 if (base) {
6413                         cntl &= ~CURSOR_MODE;
6414                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6415                 } else {
6416                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6417                         cntl |= CURSOR_MODE_DISABLE;
6418                 }
6419                 if (IS_HASWELL(dev))
6420                         cntl |= CURSOR_PIPE_CSC_ENABLE;
6421                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6422
6423                 intel_crtc->cursor_visible = visible;
6424         }
6425         /* and commit changes on next vblank */
6426         I915_WRITE(CURBASE_IVB(pipe), base);
6427 }
6428
6429 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6430 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6431                                      bool on)
6432 {
6433         struct drm_device *dev = crtc->dev;
6434         struct drm_i915_private *dev_priv = dev->dev_private;
6435         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6436         int pipe = intel_crtc->pipe;
6437         int x = intel_crtc->cursor_x;
6438         int y = intel_crtc->cursor_y;
6439         u32 base, pos;
6440         bool visible;
6441
6442         pos = 0;
6443
6444         if (on && crtc->enabled && crtc->fb) {
6445                 base = intel_crtc->cursor_addr;
6446                 if (x > (int) crtc->fb->width)
6447                         base = 0;
6448
6449                 if (y > (int) crtc->fb->height)
6450                         base = 0;
6451         } else
6452                 base = 0;
6453
6454         if (x < 0) {
6455                 if (x + intel_crtc->cursor_width < 0)
6456                         base = 0;
6457
6458                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6459                 x = -x;
6460         }
6461         pos |= x << CURSOR_X_SHIFT;
6462
6463         if (y < 0) {
6464                 if (y + intel_crtc->cursor_height < 0)
6465                         base = 0;
6466
6467                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6468                 y = -y;
6469         }
6470         pos |= y << CURSOR_Y_SHIFT;
6471
6472         visible = base != 0;
6473         if (!visible && !intel_crtc->cursor_visible)
6474                 return;
6475
6476         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6477                 I915_WRITE(CURPOS_IVB(pipe), pos);
6478                 ivb_update_cursor(crtc, base);
6479         } else {
6480                 I915_WRITE(CURPOS(pipe), pos);
6481                 if (IS_845G(dev) || IS_I865G(dev))
6482                         i845_update_cursor(crtc, base);
6483                 else
6484                         i9xx_update_cursor(crtc, base);
6485         }
6486 }
6487
6488 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6489                                  struct drm_file *file,
6490                                  uint32_t handle,
6491                                  uint32_t width, uint32_t height)
6492 {
6493         struct drm_device *dev = crtc->dev;
6494         struct drm_i915_private *dev_priv = dev->dev_private;
6495         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6496         struct drm_i915_gem_object *obj;
6497         uint32_t addr;
6498         int ret;
6499
6500         /* if we want to turn off the cursor ignore width and height */
6501         if (!handle) {
6502                 DRM_DEBUG_KMS("cursor off\n");
6503                 addr = 0;
6504                 obj = NULL;
6505                 mutex_lock(&dev->struct_mutex);
6506                 goto finish;
6507         }
6508
6509         /* Currently we only support 64x64 cursors */
6510         if (width != 64 || height != 64) {
6511                 DRM_ERROR("we currently only support 64x64 cursors\n");
6512                 return -EINVAL;
6513         }
6514
6515         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6516         if (&obj->base == NULL)
6517                 return -ENOENT;
6518
6519         if (obj->base.size < width * height * 4) {
6520                 DRM_ERROR("buffer is to small\n");
6521                 ret = -ENOMEM;
6522                 goto fail;
6523         }
6524
6525         /* we only need to pin inside GTT if cursor is non-phy */
6526         mutex_lock(&dev->struct_mutex);
6527         if (!dev_priv->info->cursor_needs_physical) {
6528                 unsigned alignment;
6529
6530                 if (obj->tiling_mode) {
6531                         DRM_ERROR("cursor cannot be tiled\n");
6532                         ret = -EINVAL;
6533                         goto fail_locked;
6534                 }
6535
6536                 /* Note that the w/a also requires 2 PTE of padding following
6537                  * the bo. We currently fill all unused PTE with the shadow
6538                  * page and so we should always have valid PTE following the
6539                  * cursor preventing the VT-d warning.
6540                  */
6541                 alignment = 0;
6542                 if (need_vtd_wa(dev))
6543                         alignment = 64*1024;
6544
6545                 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
6546                 if (ret) {
6547                         DRM_ERROR("failed to move cursor bo into the GTT\n");
6548                         goto fail_locked;
6549                 }
6550
6551                 ret = i915_gem_object_put_fence(obj);
6552                 if (ret) {
6553                         DRM_ERROR("failed to release fence for cursor");
6554                         goto fail_unpin;
6555                 }
6556
6557                 addr = obj->gtt_offset;
6558         } else {
6559                 int align = IS_I830(dev) ? 16 * 1024 : 256;
6560                 ret = i915_gem_attach_phys_object(dev, obj,
6561                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6562                                                   align);
6563                 if (ret) {
6564                         DRM_ERROR("failed to attach phys object\n");
6565                         goto fail_locked;
6566                 }
6567                 addr = obj->phys_obj->handle->busaddr;
6568         }
6569
6570         if (IS_GEN2(dev))
6571                 I915_WRITE(CURSIZE, (height << 12) | width);
6572
6573  finish:
6574         if (intel_crtc->cursor_bo) {
6575                 if (dev_priv->info->cursor_needs_physical) {
6576                         if (intel_crtc->cursor_bo != obj)
6577                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6578                 } else
6579                         i915_gem_object_unpin(intel_crtc->cursor_bo);
6580                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6581         }
6582
6583         mutex_unlock(&dev->struct_mutex);
6584
6585         intel_crtc->cursor_addr = addr;
6586         intel_crtc->cursor_bo = obj;
6587         intel_crtc->cursor_width = width;
6588         intel_crtc->cursor_height = height;
6589
6590         intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
6591
6592         return 0;
6593 fail_unpin:
6594         i915_gem_object_unpin(obj);
6595 fail_locked:
6596         mutex_unlock(&dev->struct_mutex);
6597 fail:
6598         drm_gem_object_unreference_unlocked(&obj->base);
6599         return ret;
6600 }
6601
6602 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6603 {
6604         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6605
6606         intel_crtc->cursor_x = x;
6607         intel_crtc->cursor_y = y;
6608
6609         intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
6610
6611         return 0;
6612 }
6613
6614 /** Sets the color ramps on behalf of RandR */
6615 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6616                                  u16 blue, int regno)
6617 {
6618         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6619
6620         intel_crtc->lut_r[regno] = red >> 8;
6621         intel_crtc->lut_g[regno] = green >> 8;
6622         intel_crtc->lut_b[regno] = blue >> 8;
6623 }
6624
6625 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6626                              u16 *blue, int regno)
6627 {
6628         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6629
6630         *red = intel_crtc->lut_r[regno] << 8;
6631         *green = intel_crtc->lut_g[regno] << 8;
6632         *blue = intel_crtc->lut_b[regno] << 8;
6633 }
6634
6635 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6636                                  u16 *blue, uint32_t start, uint32_t size)
6637 {
6638         int end = (start + size > 256) ? 256 : start + size, i;
6639         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6640
6641         for (i = start; i < end; i++) {
6642                 intel_crtc->lut_r[i] = red[i] >> 8;
6643                 intel_crtc->lut_g[i] = green[i] >> 8;
6644                 intel_crtc->lut_b[i] = blue[i] >> 8;
6645         }
6646
6647         intel_crtc_load_lut(crtc);
6648 }
6649
6650 /* VESA 640x480x72Hz mode to set on the pipe */
6651 static struct drm_display_mode load_detect_mode = {
6652         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6653                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6654 };
6655
6656 static struct drm_framebuffer *
6657 intel_framebuffer_create(struct drm_device *dev,
6658                          struct drm_mode_fb_cmd2 *mode_cmd,
6659                          struct drm_i915_gem_object *obj)
6660 {
6661         struct intel_framebuffer *intel_fb;
6662         int ret;
6663
6664         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6665         if (!intel_fb) {
6666                 drm_gem_object_unreference_unlocked(&obj->base);
6667                 return ERR_PTR(-ENOMEM);
6668         }
6669
6670         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6671         if (ret) {
6672                 drm_gem_object_unreference_unlocked(&obj->base);
6673                 kfree(intel_fb);
6674                 return ERR_PTR(ret);
6675         }
6676
6677         return &intel_fb->base;
6678 }
6679
6680 static u32
6681 intel_framebuffer_pitch_for_width(int width, int bpp)
6682 {
6683         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6684         return ALIGN(pitch, 64);
6685 }
6686
6687 static u32
6688 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6689 {
6690         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6691         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6692 }
6693
6694 static struct drm_framebuffer *
6695 intel_framebuffer_create_for_mode(struct drm_device *dev,
6696                                   struct drm_display_mode *mode,
6697                                   int depth, int bpp)
6698 {
6699         struct drm_i915_gem_object *obj;
6700         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
6701
6702         obj = i915_gem_alloc_object(dev,
6703                                     intel_framebuffer_size_for_mode(mode, bpp));
6704         if (obj == NULL)
6705                 return ERR_PTR(-ENOMEM);
6706
6707         mode_cmd.width = mode->hdisplay;
6708         mode_cmd.height = mode->vdisplay;
6709         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6710                                                                 bpp);
6711         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6712
6713         return intel_framebuffer_create(dev, &mode_cmd, obj);
6714 }
6715
6716 static struct drm_framebuffer *
6717 mode_fits_in_fbdev(struct drm_device *dev,
6718                    struct drm_display_mode *mode)
6719 {
6720         struct drm_i915_private *dev_priv = dev->dev_private;
6721         struct drm_i915_gem_object *obj;
6722         struct drm_framebuffer *fb;
6723
6724         if (dev_priv->fbdev == NULL)
6725                 return NULL;
6726
6727         obj = dev_priv->fbdev->ifb.obj;
6728         if (obj == NULL)
6729                 return NULL;
6730
6731         fb = &dev_priv->fbdev->ifb.base;
6732         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6733                                                                fb->bits_per_pixel))
6734                 return NULL;
6735
6736         if (obj->base.size < mode->vdisplay * fb->pitches[0])
6737                 return NULL;
6738
6739         return fb;
6740 }
6741
6742 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6743                                 struct drm_display_mode *mode,
6744                                 struct intel_load_detect_pipe *old)
6745 {
6746         struct intel_crtc *intel_crtc;
6747         struct intel_encoder *intel_encoder =
6748                 intel_attached_encoder(connector);
6749         struct drm_crtc *possible_crtc;
6750         struct drm_encoder *encoder = &intel_encoder->base;
6751         struct drm_crtc *crtc = NULL;
6752         struct drm_device *dev = encoder->dev;
6753         struct drm_framebuffer *fb;
6754         int i = -1;
6755
6756         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6757                       connector->base.id, drm_get_connector_name(connector),
6758                       encoder->base.id, drm_get_encoder_name(encoder));
6759
6760         /*
6761          * Algorithm gets a little messy:
6762          *
6763          *   - if the connector already has an assigned crtc, use it (but make
6764          *     sure it's on first)
6765          *
6766          *   - try to find the first unused crtc that can drive this connector,
6767          *     and use that if we find one
6768          */
6769
6770         /* See if we already have a CRTC for this connector */
6771         if (encoder->crtc) {
6772                 crtc = encoder->crtc;
6773
6774                 mutex_lock(&crtc->mutex);
6775
6776                 old->dpms_mode = connector->dpms;
6777                 old->load_detect_temp = false;
6778
6779                 /* Make sure the crtc and connector are running */
6780                 if (connector->dpms != DRM_MODE_DPMS_ON)
6781                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6782
6783                 return true;
6784         }
6785
6786         /* Find an unused one (if possible) */
6787         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6788                 i++;
6789                 if (!(encoder->possible_crtcs & (1 << i)))
6790                         continue;
6791                 if (!possible_crtc->enabled) {
6792                         crtc = possible_crtc;
6793                         break;
6794                 }
6795         }
6796
6797         /*
6798          * If we didn't find an unused CRTC, don't use any.
6799          */
6800         if (!crtc) {
6801                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6802                 return false;
6803         }
6804
6805         mutex_lock(&crtc->mutex);
6806         intel_encoder->new_crtc = to_intel_crtc(crtc);
6807         to_intel_connector(connector)->new_encoder = intel_encoder;
6808
6809         intel_crtc = to_intel_crtc(crtc);
6810         old->dpms_mode = connector->dpms;
6811         old->load_detect_temp = true;
6812         old->release_fb = NULL;
6813
6814         if (!mode)
6815                 mode = &load_detect_mode;
6816
6817         /* We need a framebuffer large enough to accommodate all accesses
6818          * that the plane may generate whilst we perform load detection.
6819          * We can not rely on the fbcon either being present (we get called
6820          * during its initialisation to detect all boot displays, or it may
6821          * not even exist) or that it is large enough to satisfy the
6822          * requested mode.
6823          */
6824         fb = mode_fits_in_fbdev(dev, mode);
6825         if (fb == NULL) {
6826                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6827                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6828                 old->release_fb = fb;
6829         } else
6830                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6831         if (IS_ERR(fb)) {
6832                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6833                 mutex_unlock(&crtc->mutex);
6834                 return false;
6835         }
6836
6837         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6838                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6839                 if (old->release_fb)
6840                         old->release_fb->funcs->destroy(old->release_fb);
6841                 mutex_unlock(&crtc->mutex);
6842                 return false;
6843         }
6844
6845         /* let the connector get through one full cycle before testing */
6846         intel_wait_for_vblank(dev, intel_crtc->pipe);
6847         return true;
6848 }
6849
6850 void intel_release_load_detect_pipe(struct drm_connector *connector,
6851                                     struct intel_load_detect_pipe *old)
6852 {
6853         struct intel_encoder *intel_encoder =
6854                 intel_attached_encoder(connector);
6855         struct drm_encoder *encoder = &intel_encoder->base;
6856         struct drm_crtc *crtc = encoder->crtc;
6857
6858         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6859                       connector->base.id, drm_get_connector_name(connector),
6860                       encoder->base.id, drm_get_encoder_name(encoder));
6861
6862         if (old->load_detect_temp) {
6863                 to_intel_connector(connector)->new_encoder = NULL;
6864                 intel_encoder->new_crtc = NULL;
6865                 intel_set_mode(crtc, NULL, 0, 0, NULL);
6866
6867                 if (old->release_fb) {
6868                         drm_framebuffer_unregister_private(old->release_fb);
6869                         drm_framebuffer_unreference(old->release_fb);
6870                 }
6871
6872                 mutex_unlock(&crtc->mutex);
6873                 return;
6874         }
6875
6876         /* Switch crtc and encoder back off if necessary */
6877         if (old->dpms_mode != DRM_MODE_DPMS_ON)
6878                 connector->funcs->dpms(connector, old->dpms_mode);
6879
6880         mutex_unlock(&crtc->mutex);
6881 }
6882
6883 /* Returns the clock of the currently programmed mode of the given pipe. */
6884 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6885 {
6886         struct drm_i915_private *dev_priv = dev->dev_private;
6887         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6888         int pipe = intel_crtc->pipe;
6889         u32 dpll = I915_READ(DPLL(pipe));
6890         u32 fp;
6891         intel_clock_t clock;
6892
6893         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6894                 fp = I915_READ(FP0(pipe));
6895         else
6896                 fp = I915_READ(FP1(pipe));
6897
6898         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6899         if (IS_PINEVIEW(dev)) {
6900                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6901                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6902         } else {
6903                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6904                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6905         }
6906
6907         if (!IS_GEN2(dev)) {
6908                 if (IS_PINEVIEW(dev))
6909                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6910                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6911                 else
6912                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6913                                DPLL_FPA01_P1_POST_DIV_SHIFT);
6914
6915                 switch (dpll & DPLL_MODE_MASK) {
6916                 case DPLLB_MODE_DAC_SERIAL:
6917                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6918                                 5 : 10;
6919                         break;
6920                 case DPLLB_MODE_LVDS:
6921                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6922                                 7 : 14;
6923                         break;
6924                 default:
6925                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6926                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
6927                         return 0;
6928                 }
6929
6930                 if (IS_PINEVIEW(dev))
6931                         pineview_clock(96000, &clock);
6932                 else
6933                         i9xx_clock(96000, &clock);
6934         } else {
6935                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6936
6937                 if (is_lvds) {
6938                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6939                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
6940                         clock.p2 = 14;
6941
6942                         if ((dpll & PLL_REF_INPUT_MASK) ==
6943                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6944                                 /* XXX: might not be 66MHz */
6945                                 i9xx_clock(66000, &clock);
6946                         } else
6947                                 i9xx_clock(48000, &clock);
6948                 } else {
6949                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
6950                                 clock.p1 = 2;
6951                         else {
6952                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6953                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6954                         }
6955                         if (dpll & PLL_P2_DIVIDE_BY_4)
6956                                 clock.p2 = 4;
6957                         else
6958                                 clock.p2 = 2;
6959
6960                         i9xx_clock(48000, &clock);
6961                 }
6962         }
6963
6964         /* XXX: It would be nice to validate the clocks, but we can't reuse
6965          * i830PllIsValid() because it relies on the xf86_config connector
6966          * configuration being accurate, which it isn't necessarily.
6967          */
6968
6969         return clock.dot;
6970 }
6971
6972 /** Returns the currently programmed mode of the given pipe. */
6973 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6974                                              struct drm_crtc *crtc)
6975 {
6976         struct drm_i915_private *dev_priv = dev->dev_private;
6977         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6978         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6979         struct drm_display_mode *mode;
6980         int htot = I915_READ(HTOTAL(cpu_transcoder));
6981         int hsync = I915_READ(HSYNC(cpu_transcoder));
6982         int vtot = I915_READ(VTOTAL(cpu_transcoder));
6983         int vsync = I915_READ(VSYNC(cpu_transcoder));
6984
6985         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6986         if (!mode)
6987                 return NULL;
6988
6989         mode->clock = intel_crtc_clock_get(dev, crtc);
6990         mode->hdisplay = (htot & 0xffff) + 1;
6991         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6992         mode->hsync_start = (hsync & 0xffff) + 1;
6993         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6994         mode->vdisplay = (vtot & 0xffff) + 1;
6995         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6996         mode->vsync_start = (vsync & 0xffff) + 1;
6997         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6998
6999         drm_mode_set_name(mode);
7000
7001         return mode;
7002 }
7003
7004 static void intel_increase_pllclock(struct drm_crtc *crtc)
7005 {
7006         struct drm_device *dev = crtc->dev;
7007         drm_i915_private_t *dev_priv = dev->dev_private;
7008         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7009         int pipe = intel_crtc->pipe;
7010         int dpll_reg = DPLL(pipe);
7011         int dpll;
7012
7013         if (HAS_PCH_SPLIT(dev))
7014                 return;
7015
7016         if (!dev_priv->lvds_downclock_avail)
7017                 return;
7018
7019         dpll = I915_READ(dpll_reg);
7020         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
7021                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
7022
7023                 assert_panel_unlocked(dev_priv, pipe);
7024
7025                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7026                 I915_WRITE(dpll_reg, dpll);
7027                 intel_wait_for_vblank(dev, pipe);
7028
7029                 dpll = I915_READ(dpll_reg);
7030                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
7031                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7032         }
7033 }
7034
7035 static void intel_decrease_pllclock(struct drm_crtc *crtc)
7036 {
7037         struct drm_device *dev = crtc->dev;
7038         drm_i915_private_t *dev_priv = dev->dev_private;
7039         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7040
7041         if (HAS_PCH_SPLIT(dev))
7042                 return;
7043
7044         if (!dev_priv->lvds_downclock_avail)
7045                 return;
7046
7047         /*
7048          * Since this is called by a timer, we should never get here in
7049          * the manual case.
7050          */
7051         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
7052                 int pipe = intel_crtc->pipe;
7053                 int dpll_reg = DPLL(pipe);
7054                 int dpll;
7055
7056                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7057
7058                 assert_panel_unlocked(dev_priv, pipe);
7059
7060                 dpll = I915_READ(dpll_reg);
7061                 dpll |= DISPLAY_RATE_SELECT_FPA1;
7062                 I915_WRITE(dpll_reg, dpll);
7063                 intel_wait_for_vblank(dev, pipe);
7064                 dpll = I915_READ(dpll_reg);
7065                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
7066                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7067         }
7068
7069 }
7070
7071 void intel_mark_busy(struct drm_device *dev)
7072 {
7073         i915_update_gfx_val(dev->dev_private);
7074 }
7075
7076 void intel_mark_idle(struct drm_device *dev)
7077 {
7078         struct drm_crtc *crtc;
7079
7080         if (!i915_powersave)
7081                 return;
7082
7083         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7084                 if (!crtc->fb)
7085                         continue;
7086
7087                 intel_decrease_pllclock(crtc);
7088         }
7089 }
7090
7091 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7092                         struct intel_ring_buffer *ring)
7093 {
7094         struct drm_device *dev = obj->base.dev;
7095         struct drm_crtc *crtc;
7096
7097         if (!i915_powersave)
7098                 return;
7099
7100         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7101                 if (!crtc->fb)
7102                         continue;
7103
7104                 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7105                         continue;
7106
7107                 intel_increase_pllclock(crtc);
7108                 if (ring && intel_fbc_enabled(dev))
7109                         ring->fbc_dirty = true;
7110         }
7111 }
7112
7113 static void intel_crtc_destroy(struct drm_crtc *crtc)
7114 {
7115         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7116         struct drm_device *dev = crtc->dev;
7117         struct intel_unpin_work *work;
7118         unsigned long flags;
7119
7120         spin_lock_irqsave(&dev->event_lock, flags);
7121         work = intel_crtc->unpin_work;
7122         intel_crtc->unpin_work = NULL;
7123         spin_unlock_irqrestore(&dev->event_lock, flags);
7124
7125         if (work) {
7126                 cancel_work_sync(&work->work);
7127                 kfree(work);
7128         }
7129
7130         intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7131
7132         drm_crtc_cleanup(crtc);
7133
7134         kfree(intel_crtc);
7135 }
7136
7137 static void intel_unpin_work_fn(struct work_struct *__work)
7138 {
7139         struct intel_unpin_work *work =
7140                 container_of(__work, struct intel_unpin_work, work);
7141         struct drm_device *dev = work->crtc->dev;
7142
7143         mutex_lock(&dev->struct_mutex);
7144         intel_unpin_fb_obj(work->old_fb_obj);
7145         drm_gem_object_unreference(&work->pending_flip_obj->base);
7146         drm_gem_object_unreference(&work->old_fb_obj->base);
7147
7148         intel_update_fbc(dev);
7149         mutex_unlock(&dev->struct_mutex);
7150
7151         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7152         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7153
7154         kfree(work);
7155 }
7156
7157 static void do_intel_finish_page_flip(struct drm_device *dev,
7158                                       struct drm_crtc *crtc)
7159 {
7160         drm_i915_private_t *dev_priv = dev->dev_private;
7161         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7162         struct intel_unpin_work *work;
7163         unsigned long flags;
7164
7165         /* Ignore early vblank irqs */
7166         if (intel_crtc == NULL)
7167                 return;
7168
7169         spin_lock_irqsave(&dev->event_lock, flags);
7170         work = intel_crtc->unpin_work;
7171
7172         /* Ensure we don't miss a work->pending update ... */
7173         smp_rmb();
7174
7175         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
7176                 spin_unlock_irqrestore(&dev->event_lock, flags);
7177                 return;
7178         }
7179
7180         /* and that the unpin work is consistent wrt ->pending. */
7181         smp_rmb();
7182
7183         intel_crtc->unpin_work = NULL;
7184
7185         if (work->event)
7186                 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
7187
7188         drm_vblank_put(dev, intel_crtc->pipe);
7189
7190         spin_unlock_irqrestore(&dev->event_lock, flags);
7191
7192         wake_up_all(&dev_priv->pending_flip_queue);
7193
7194         queue_work(dev_priv->wq, &work->work);
7195
7196         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7197 }
7198
7199 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7200 {
7201         drm_i915_private_t *dev_priv = dev->dev_private;
7202         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7203
7204         do_intel_finish_page_flip(dev, crtc);
7205 }
7206
7207 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7208 {
7209         drm_i915_private_t *dev_priv = dev->dev_private;
7210         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7211
7212         do_intel_finish_page_flip(dev, crtc);
7213 }
7214
7215 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7216 {
7217         drm_i915_private_t *dev_priv = dev->dev_private;
7218         struct intel_crtc *intel_crtc =
7219                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7220         unsigned long flags;
7221
7222         /* NB: An MMIO update of the plane base pointer will also
7223          * generate a page-flip completion irq, i.e. every modeset
7224          * is also accompanied by a spurious intel_prepare_page_flip().
7225          */
7226         spin_lock_irqsave(&dev->event_lock, flags);
7227         if (intel_crtc->unpin_work)
7228                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
7229         spin_unlock_irqrestore(&dev->event_lock, flags);
7230 }
7231
7232 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7233 {
7234         /* Ensure that the work item is consistent when activating it ... */
7235         smp_wmb();
7236         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7237         /* and that it is marked active as soon as the irq could fire. */
7238         smp_wmb();
7239 }
7240
7241 static int intel_gen2_queue_flip(struct drm_device *dev,
7242                                  struct drm_crtc *crtc,
7243                                  struct drm_framebuffer *fb,
7244                                  struct drm_i915_gem_object *obj)
7245 {
7246         struct drm_i915_private *dev_priv = dev->dev_private;
7247         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7248         u32 flip_mask;
7249         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7250         int ret;
7251
7252         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7253         if (ret)
7254                 goto err;
7255
7256         ret = intel_ring_begin(ring, 6);
7257         if (ret)
7258                 goto err_unpin;
7259
7260         /* Can't queue multiple flips, so wait for the previous
7261          * one to finish before executing the next.
7262          */
7263         if (intel_crtc->plane)
7264                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7265         else
7266                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7267         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7268         intel_ring_emit(ring, MI_NOOP);
7269         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7270                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7271         intel_ring_emit(ring, fb->pitches[0]);
7272         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7273         intel_ring_emit(ring, 0); /* aux display base address, unused */
7274
7275         intel_mark_page_flip_active(intel_crtc);
7276         intel_ring_advance(ring);
7277         return 0;
7278
7279 err_unpin:
7280         intel_unpin_fb_obj(obj);
7281 err:
7282         return ret;
7283 }
7284
7285 static int intel_gen3_queue_flip(struct drm_device *dev,
7286                                  struct drm_crtc *crtc,
7287                                  struct drm_framebuffer *fb,
7288                                  struct drm_i915_gem_object *obj)
7289 {
7290         struct drm_i915_private *dev_priv = dev->dev_private;
7291         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7292         u32 flip_mask;
7293         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7294         int ret;
7295
7296         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7297         if (ret)
7298                 goto err;
7299
7300         ret = intel_ring_begin(ring, 6);
7301         if (ret)
7302                 goto err_unpin;
7303
7304         if (intel_crtc->plane)
7305                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7306         else
7307                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7308         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7309         intel_ring_emit(ring, MI_NOOP);
7310         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7311                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7312         intel_ring_emit(ring, fb->pitches[0]);
7313         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7314         intel_ring_emit(ring, MI_NOOP);
7315
7316         intel_mark_page_flip_active(intel_crtc);
7317         intel_ring_advance(ring);
7318         return 0;
7319
7320 err_unpin:
7321         intel_unpin_fb_obj(obj);
7322 err:
7323         return ret;
7324 }
7325
7326 static int intel_gen4_queue_flip(struct drm_device *dev,
7327                                  struct drm_crtc *crtc,
7328                                  struct drm_framebuffer *fb,
7329                                  struct drm_i915_gem_object *obj)
7330 {
7331         struct drm_i915_private *dev_priv = dev->dev_private;
7332         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7333         uint32_t pf, pipesrc;
7334         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7335         int ret;
7336
7337         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7338         if (ret)
7339                 goto err;
7340
7341         ret = intel_ring_begin(ring, 4);
7342         if (ret)
7343                 goto err_unpin;
7344
7345         /* i965+ uses the linear or tiled offsets from the
7346          * Display Registers (which do not change across a page-flip)
7347          * so we need only reprogram the base address.
7348          */
7349         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7350                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7351         intel_ring_emit(ring, fb->pitches[0]);
7352         intel_ring_emit(ring,
7353                         (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7354                         obj->tiling_mode);
7355
7356         /* XXX Enabling the panel-fitter across page-flip is so far
7357          * untested on non-native modes, so ignore it for now.
7358          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7359          */
7360         pf = 0;
7361         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7362         intel_ring_emit(ring, pf | pipesrc);
7363
7364         intel_mark_page_flip_active(intel_crtc);
7365         intel_ring_advance(ring);
7366         return 0;
7367
7368 err_unpin:
7369         intel_unpin_fb_obj(obj);
7370 err:
7371         return ret;
7372 }
7373
7374 static int intel_gen6_queue_flip(struct drm_device *dev,
7375                                  struct drm_crtc *crtc,
7376                                  struct drm_framebuffer *fb,
7377                                  struct drm_i915_gem_object *obj)
7378 {
7379         struct drm_i915_private *dev_priv = dev->dev_private;
7380         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7381         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7382         uint32_t pf, pipesrc;
7383         int ret;
7384
7385         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7386         if (ret)
7387                 goto err;
7388
7389         ret = intel_ring_begin(ring, 4);
7390         if (ret)
7391                 goto err_unpin;
7392
7393         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7394                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7395         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7396         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7397
7398         /* Contrary to the suggestions in the documentation,
7399          * "Enable Panel Fitter" does not seem to be required when page
7400          * flipping with a non-native mode, and worse causes a normal
7401          * modeset to fail.
7402          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7403          */
7404         pf = 0;
7405         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7406         intel_ring_emit(ring, pf | pipesrc);
7407
7408         intel_mark_page_flip_active(intel_crtc);
7409         intel_ring_advance(ring);
7410         return 0;
7411
7412 err_unpin:
7413         intel_unpin_fb_obj(obj);
7414 err:
7415         return ret;
7416 }
7417
7418 /*
7419  * On gen7 we currently use the blit ring because (in early silicon at least)
7420  * the render ring doesn't give us interrpts for page flip completion, which
7421  * means clients will hang after the first flip is queued.  Fortunately the
7422  * blit ring generates interrupts properly, so use it instead.
7423  */
7424 static int intel_gen7_queue_flip(struct drm_device *dev,
7425                                  struct drm_crtc *crtc,
7426                                  struct drm_framebuffer *fb,
7427                                  struct drm_i915_gem_object *obj)
7428 {
7429         struct drm_i915_private *dev_priv = dev->dev_private;
7430         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7431         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7432         uint32_t plane_bit = 0;
7433         int ret;
7434
7435         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7436         if (ret)
7437                 goto err;
7438
7439         switch(intel_crtc->plane) {
7440         case PLANE_A:
7441                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7442                 break;
7443         case PLANE_B:
7444                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7445                 break;
7446         case PLANE_C:
7447                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7448                 break;
7449         default:
7450                 WARN_ONCE(1, "unknown plane in flip command\n");
7451                 ret = -ENODEV;
7452                 goto err_unpin;
7453         }
7454
7455         ret = intel_ring_begin(ring, 4);
7456         if (ret)
7457                 goto err_unpin;
7458
7459         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7460         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7461         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7462         intel_ring_emit(ring, (MI_NOOP));
7463
7464         intel_mark_page_flip_active(intel_crtc);
7465         intel_ring_advance(ring);
7466         return 0;
7467
7468 err_unpin:
7469         intel_unpin_fb_obj(obj);
7470 err:
7471         return ret;
7472 }
7473
7474 static int intel_default_queue_flip(struct drm_device *dev,
7475                                     struct drm_crtc *crtc,
7476                                     struct drm_framebuffer *fb,
7477                                     struct drm_i915_gem_object *obj)
7478 {
7479         return -ENODEV;
7480 }
7481
7482 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7483                                 struct drm_framebuffer *fb,
7484                                 struct drm_pending_vblank_event *event)
7485 {
7486         struct drm_device *dev = crtc->dev;
7487         struct drm_i915_private *dev_priv = dev->dev_private;
7488         struct drm_framebuffer *old_fb = crtc->fb;
7489         struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
7490         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7491         struct intel_unpin_work *work;
7492         unsigned long flags;
7493         int ret;
7494
7495         /* Can't change pixel format via MI display flips. */
7496         if (fb->pixel_format != crtc->fb->pixel_format)
7497                 return -EINVAL;
7498
7499         /*
7500          * TILEOFF/LINOFF registers can't be changed via MI display flips.
7501          * Note that pitch changes could also affect these register.
7502          */
7503         if (INTEL_INFO(dev)->gen > 3 &&
7504             (fb->offsets[0] != crtc->fb->offsets[0] ||
7505              fb->pitches[0] != crtc->fb->pitches[0]))
7506                 return -EINVAL;
7507
7508         work = kzalloc(sizeof *work, GFP_KERNEL);
7509         if (work == NULL)
7510                 return -ENOMEM;
7511
7512         work->event = event;
7513         work->crtc = crtc;
7514         work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
7515         INIT_WORK(&work->work, intel_unpin_work_fn);
7516
7517         ret = drm_vblank_get(dev, intel_crtc->pipe);
7518         if (ret)
7519                 goto free_work;
7520
7521         /* We borrow the event spin lock for protecting unpin_work */
7522         spin_lock_irqsave(&dev->event_lock, flags);
7523         if (intel_crtc->unpin_work) {
7524                 spin_unlock_irqrestore(&dev->event_lock, flags);
7525                 kfree(work);
7526                 drm_vblank_put(dev, intel_crtc->pipe);
7527
7528                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7529                 return -EBUSY;
7530         }
7531         intel_crtc->unpin_work = work;
7532         spin_unlock_irqrestore(&dev->event_lock, flags);
7533
7534         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7535                 flush_workqueue(dev_priv->wq);
7536
7537         ret = i915_mutex_lock_interruptible(dev);
7538         if (ret)
7539                 goto cleanup;
7540
7541         /* Reference the objects for the scheduled work. */
7542         drm_gem_object_reference(&work->old_fb_obj->base);
7543         drm_gem_object_reference(&obj->base);
7544
7545         crtc->fb = fb;
7546
7547         work->pending_flip_obj = obj;
7548
7549         work->enable_stall_check = true;
7550
7551         atomic_inc(&intel_crtc->unpin_work_count);
7552         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
7553
7554         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7555         if (ret)
7556                 goto cleanup_pending;
7557
7558         intel_disable_fbc(dev);
7559         intel_mark_fb_busy(obj, NULL);
7560         mutex_unlock(&dev->struct_mutex);
7561
7562         trace_i915_flip_request(intel_crtc->plane, obj);
7563
7564         return 0;
7565
7566 cleanup_pending:
7567         atomic_dec(&intel_crtc->unpin_work_count);
7568         crtc->fb = old_fb;
7569         drm_gem_object_unreference(&work->old_fb_obj->base);
7570         drm_gem_object_unreference(&obj->base);
7571         mutex_unlock(&dev->struct_mutex);
7572
7573 cleanup:
7574         spin_lock_irqsave(&dev->event_lock, flags);
7575         intel_crtc->unpin_work = NULL;
7576         spin_unlock_irqrestore(&dev->event_lock, flags);
7577
7578         drm_vblank_put(dev, intel_crtc->pipe);
7579 free_work:
7580         kfree(work);
7581
7582         return ret;
7583 }
7584
7585 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7586         .mode_set_base_atomic = intel_pipe_set_base_atomic,
7587         .load_lut = intel_crtc_load_lut,
7588 };
7589
7590 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7591                                   struct drm_crtc *crtc)
7592 {
7593         struct drm_device *dev;
7594         struct drm_crtc *tmp;
7595         int crtc_mask = 1;
7596
7597         WARN(!crtc, "checking null crtc?\n");
7598
7599         dev = crtc->dev;
7600
7601         list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7602                 if (tmp == crtc)
7603                         break;
7604                 crtc_mask <<= 1;
7605         }
7606
7607         if (encoder->possible_crtcs & crtc_mask)
7608                 return true;
7609         return false;
7610 }
7611
7612 /**
7613  * intel_modeset_update_staged_output_state
7614  *
7615  * Updates the staged output configuration state, e.g. after we've read out the
7616  * current hw state.
7617  */
7618 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7619 {
7620         struct intel_encoder *encoder;
7621         struct intel_connector *connector;
7622
7623         list_for_each_entry(connector, &dev->mode_config.connector_list,
7624                             base.head) {
7625                 connector->new_encoder =
7626                         to_intel_encoder(connector->base.encoder);
7627         }
7628
7629         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7630                             base.head) {
7631                 encoder->new_crtc =
7632                         to_intel_crtc(encoder->base.crtc);
7633         }
7634 }
7635
7636 /**
7637  * intel_modeset_commit_output_state
7638  *
7639  * This function copies the stage display pipe configuration to the real one.
7640  */
7641 static void intel_modeset_commit_output_state(struct drm_device *dev)
7642 {
7643         struct intel_encoder *encoder;
7644         struct intel_connector *connector;
7645
7646         list_for_each_entry(connector, &dev->mode_config.connector_list,
7647                             base.head) {
7648                 connector->base.encoder = &connector->new_encoder->base;
7649         }
7650
7651         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7652                             base.head) {
7653                 encoder->base.crtc = &encoder->new_crtc->base;
7654         }
7655 }
7656
7657 static void
7658 connected_sink_compute_bpp(struct intel_connector * connector,
7659                            struct intel_crtc_config *pipe_config)
7660 {
7661         int bpp = pipe_config->pipe_bpp;
7662
7663         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
7664                 connector->base.base.id,
7665                 drm_get_connector_name(&connector->base));
7666
7667         /* Don't use an invalid EDID bpc value */
7668         if (connector->base.display_info.bpc &&
7669             connector->base.display_info.bpc * 3 < bpp) {
7670                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7671                               bpp, connector->base.display_info.bpc*3);
7672                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
7673         }
7674
7675         /* Clamp bpp to 8 on screens without EDID 1.4 */
7676         if (connector->base.display_info.bpc == 0 && bpp > 24) {
7677                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
7678                               bpp);
7679                 pipe_config->pipe_bpp = 24;
7680         }
7681 }
7682
7683 static int
7684 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
7685                           struct drm_framebuffer *fb,
7686                           struct intel_crtc_config *pipe_config)
7687 {
7688         struct drm_device *dev = crtc->base.dev;
7689         struct intel_connector *connector;
7690         int bpp;
7691
7692         switch (fb->pixel_format) {
7693         case DRM_FORMAT_C8:
7694                 bpp = 8*3; /* since we go through a colormap */
7695                 break;
7696         case DRM_FORMAT_XRGB1555:
7697         case DRM_FORMAT_ARGB1555:
7698                 /* checked in intel_framebuffer_init already */
7699                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7700                         return -EINVAL;
7701         case DRM_FORMAT_RGB565:
7702                 bpp = 6*3; /* min is 18bpp */
7703                 break;
7704         case DRM_FORMAT_XBGR8888:
7705         case DRM_FORMAT_ABGR8888:
7706                 /* checked in intel_framebuffer_init already */
7707                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7708                         return -EINVAL;
7709         case DRM_FORMAT_XRGB8888:
7710         case DRM_FORMAT_ARGB8888:
7711                 bpp = 8*3;
7712                 break;
7713         case DRM_FORMAT_XRGB2101010:
7714         case DRM_FORMAT_ARGB2101010:
7715         case DRM_FORMAT_XBGR2101010:
7716         case DRM_FORMAT_ABGR2101010:
7717                 /* checked in intel_framebuffer_init already */
7718                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7719                         return -EINVAL;
7720                 bpp = 10*3;
7721                 break;
7722         /* TODO: gen4+ supports 16 bpc floating point, too. */
7723         default:
7724                 DRM_DEBUG_KMS("unsupported depth\n");
7725                 return -EINVAL;
7726         }
7727
7728         pipe_config->pipe_bpp = bpp;
7729
7730         /* Clamp display bpp to EDID value */
7731         list_for_each_entry(connector, &dev->mode_config.connector_list,
7732                             base.head) {
7733                 if (!connector->new_encoder ||
7734                     connector->new_encoder->new_crtc != crtc)
7735                         continue;
7736
7737                 connected_sink_compute_bpp(connector, pipe_config);
7738         }
7739
7740         return bpp;
7741 }
7742
7743 static void intel_dump_pipe_config(struct intel_crtc *crtc,
7744                                    struct intel_crtc_config *pipe_config,
7745                                    const char *context)
7746 {
7747         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
7748                       context, pipe_name(crtc->pipe));
7749
7750         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
7751         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
7752                       pipe_config->pipe_bpp, pipe_config->dither);
7753         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
7754                       pipe_config->has_pch_encoder,
7755                       pipe_config->fdi_lanes,
7756                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
7757                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
7758                       pipe_config->fdi_m_n.tu);
7759         DRM_DEBUG_KMS("requested mode:\n");
7760         drm_mode_debug_printmodeline(&pipe_config->requested_mode);
7761         DRM_DEBUG_KMS("adjusted mode:\n");
7762         drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
7763         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
7764                       pipe_config->gmch_pfit.control,
7765                       pipe_config->gmch_pfit.pgm_ratios,
7766                       pipe_config->gmch_pfit.lvds_border_bits);
7767         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
7768                       pipe_config->pch_pfit.pos,
7769                       pipe_config->pch_pfit.size);
7770         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
7771 }
7772
7773 static bool check_encoder_cloning(struct drm_crtc *crtc)
7774 {
7775         int num_encoders = 0;
7776         bool uncloneable_encoders = false;
7777         struct intel_encoder *encoder;
7778
7779         list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
7780                             base.head) {
7781                 if (&encoder->new_crtc->base != crtc)
7782                         continue;
7783
7784                 num_encoders++;
7785                 if (!encoder->cloneable)
7786                         uncloneable_encoders = true;
7787         }
7788
7789         return !(num_encoders > 1 && uncloneable_encoders);
7790 }
7791
7792 static struct intel_crtc_config *
7793 intel_modeset_pipe_config(struct drm_crtc *crtc,
7794                           struct drm_framebuffer *fb,
7795                           struct drm_display_mode *mode)
7796 {
7797         struct drm_device *dev = crtc->dev;
7798         struct drm_encoder_helper_funcs *encoder_funcs;
7799         struct intel_encoder *encoder;
7800         struct intel_crtc_config *pipe_config;
7801         int plane_bpp, ret = -EINVAL;
7802         bool retry = true;
7803
7804         if (!check_encoder_cloning(crtc)) {
7805                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
7806                 return ERR_PTR(-EINVAL);
7807         }
7808
7809         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7810         if (!pipe_config)
7811                 return ERR_PTR(-ENOMEM);
7812
7813         drm_mode_copy(&pipe_config->adjusted_mode, mode);
7814         drm_mode_copy(&pipe_config->requested_mode, mode);
7815         pipe_config->cpu_transcoder = to_intel_crtc(crtc)->pipe;
7816         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7817
7818         /* Compute a starting value for pipe_config->pipe_bpp taking the source
7819          * plane pixel format and any sink constraints into account. Returns the
7820          * source plane bpp so that dithering can be selected on mismatches
7821          * after encoders and crtc also have had their say. */
7822         plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
7823                                               fb, pipe_config);
7824         if (plane_bpp < 0)
7825                 goto fail;
7826
7827 encoder_retry:
7828         /* Ensure the port clock defaults are reset when retrying. */
7829         pipe_config->port_clock = 0;
7830         pipe_config->pixel_multiplier = 1;
7831
7832         /* Pass our mode to the connectors and the CRTC to give them a chance to
7833          * adjust it according to limitations or connector properties, and also
7834          * a chance to reject the mode entirely.
7835          */
7836         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7837                             base.head) {
7838
7839                 if (&encoder->new_crtc->base != crtc)
7840                         continue;
7841
7842                 if (encoder->compute_config) {
7843                         if (!(encoder->compute_config(encoder, pipe_config))) {
7844                                 DRM_DEBUG_KMS("Encoder config failure\n");
7845                                 goto fail;
7846                         }
7847
7848                         continue;
7849                 }
7850
7851                 encoder_funcs = encoder->base.helper_private;
7852                 if (!(encoder_funcs->mode_fixup(&encoder->base,
7853                                                 &pipe_config->requested_mode,
7854                                                 &pipe_config->adjusted_mode))) {
7855                         DRM_DEBUG_KMS("Encoder fixup failed\n");
7856                         goto fail;
7857                 }
7858         }
7859
7860         /* Set default port clock if not overwritten by the encoder. Needs to be
7861          * done afterwards in case the encoder adjusts the mode. */
7862         if (!pipe_config->port_clock)
7863                 pipe_config->port_clock = pipe_config->adjusted_mode.clock;
7864
7865         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
7866         if (ret < 0) {
7867                 DRM_DEBUG_KMS("CRTC fixup failed\n");
7868                 goto fail;
7869         }
7870
7871         if (ret == RETRY) {
7872                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
7873                         ret = -EINVAL;
7874                         goto fail;
7875                 }
7876
7877                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
7878                 retry = false;
7879                 goto encoder_retry;
7880         }
7881
7882         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7883         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7884                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7885
7886         return pipe_config;
7887 fail:
7888         kfree(pipe_config);
7889         return ERR_PTR(ret);
7890 }
7891
7892 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7893  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7894 static void
7895 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7896                              unsigned *prepare_pipes, unsigned *disable_pipes)
7897 {
7898         struct intel_crtc *intel_crtc;
7899         struct drm_device *dev = crtc->dev;
7900         struct intel_encoder *encoder;
7901         struct intel_connector *connector;
7902         struct drm_crtc *tmp_crtc;
7903
7904         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7905
7906         /* Check which crtcs have changed outputs connected to them, these need
7907          * to be part of the prepare_pipes mask. We don't (yet) support global
7908          * modeset across multiple crtcs, so modeset_pipes will only have one
7909          * bit set at most. */
7910         list_for_each_entry(connector, &dev->mode_config.connector_list,
7911                             base.head) {
7912                 if (connector->base.encoder == &connector->new_encoder->base)
7913                         continue;
7914
7915                 if (connector->base.encoder) {
7916                         tmp_crtc = connector->base.encoder->crtc;
7917
7918                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7919                 }
7920
7921                 if (connector->new_encoder)
7922                         *prepare_pipes |=
7923                                 1 << connector->new_encoder->new_crtc->pipe;
7924         }
7925
7926         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7927                             base.head) {
7928                 if (encoder->base.crtc == &encoder->new_crtc->base)
7929                         continue;
7930
7931                 if (encoder->base.crtc) {
7932                         tmp_crtc = encoder->base.crtc;
7933
7934                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7935                 }
7936
7937                 if (encoder->new_crtc)
7938                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7939         }
7940
7941         /* Check for any pipes that will be fully disabled ... */
7942         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7943                             base.head) {
7944                 bool used = false;
7945
7946                 /* Don't try to disable disabled crtcs. */
7947                 if (!intel_crtc->base.enabled)
7948                         continue;
7949
7950                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7951                                     base.head) {
7952                         if (encoder->new_crtc == intel_crtc)
7953                                 used = true;
7954                 }
7955
7956                 if (!used)
7957                         *disable_pipes |= 1 << intel_crtc->pipe;
7958         }
7959
7960
7961         /* set_mode is also used to update properties on life display pipes. */
7962         intel_crtc = to_intel_crtc(crtc);
7963         if (crtc->enabled)
7964                 *prepare_pipes |= 1 << intel_crtc->pipe;
7965
7966         /*
7967          * For simplicity do a full modeset on any pipe where the output routing
7968          * changed. We could be more clever, but that would require us to be
7969          * more careful with calling the relevant encoder->mode_set functions.
7970          */
7971         if (*prepare_pipes)
7972                 *modeset_pipes = *prepare_pipes;
7973
7974         /* ... and mask these out. */
7975         *modeset_pipes &= ~(*disable_pipes);
7976         *prepare_pipes &= ~(*disable_pipes);
7977
7978         /*
7979          * HACK: We don't (yet) fully support global modesets. intel_set_config
7980          * obies this rule, but the modeset restore mode of
7981          * intel_modeset_setup_hw_state does not.
7982          */
7983         *modeset_pipes &= 1 << intel_crtc->pipe;
7984         *prepare_pipes &= 1 << intel_crtc->pipe;
7985
7986         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7987                       *modeset_pipes, *prepare_pipes, *disable_pipes);
7988 }
7989
7990 static bool intel_crtc_in_use(struct drm_crtc *crtc)
7991 {
7992         struct drm_encoder *encoder;
7993         struct drm_device *dev = crtc->dev;
7994
7995         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7996                 if (encoder->crtc == crtc)
7997                         return true;
7998
7999         return false;
8000 }
8001
8002 static void
8003 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8004 {
8005         struct intel_encoder *intel_encoder;
8006         struct intel_crtc *intel_crtc;
8007         struct drm_connector *connector;
8008
8009         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8010                             base.head) {
8011                 if (!intel_encoder->base.crtc)
8012                         continue;
8013
8014                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8015
8016                 if (prepare_pipes & (1 << intel_crtc->pipe))
8017                         intel_encoder->connectors_active = false;
8018         }
8019
8020         intel_modeset_commit_output_state(dev);
8021
8022         /* Update computed state. */
8023         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8024                             base.head) {
8025                 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8026         }
8027
8028         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8029                 if (!connector->encoder || !connector->encoder->crtc)
8030                         continue;
8031
8032                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8033
8034                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
8035                         struct drm_property *dpms_property =
8036                                 dev->mode_config.dpms_property;
8037
8038                         connector->dpms = DRM_MODE_DPMS_ON;
8039                         drm_object_property_set_value(&connector->base,
8040                                                          dpms_property,
8041                                                          DRM_MODE_DPMS_ON);
8042
8043                         intel_encoder = to_intel_encoder(connector->encoder);
8044                         intel_encoder->connectors_active = true;
8045                 }
8046         }
8047
8048 }
8049
8050 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8051         list_for_each_entry((intel_crtc), \
8052                             &(dev)->mode_config.crtc_list, \
8053                             base.head) \
8054                 if (mask & (1 <<(intel_crtc)->pipe))
8055
8056 static bool
8057 intel_pipe_config_compare(struct drm_device *dev,
8058                           struct intel_crtc_config *current_config,
8059                           struct intel_crtc_config *pipe_config)
8060 {
8061 #define PIPE_CONF_CHECK_X(name) \
8062         if (current_config->name != pipe_config->name) { \
8063                 DRM_ERROR("mismatch in " #name " " \
8064                           "(expected 0x%08x, found 0x%08x)\n", \
8065                           current_config->name, \
8066                           pipe_config->name); \
8067                 return false; \
8068         }
8069
8070 #define PIPE_CONF_CHECK_I(name) \
8071         if (current_config->name != pipe_config->name) { \
8072                 DRM_ERROR("mismatch in " #name " " \
8073                           "(expected %i, found %i)\n", \
8074                           current_config->name, \
8075                           pipe_config->name); \
8076                 return false; \
8077         }
8078
8079 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
8080         if ((current_config->name ^ pipe_config->name) & (mask)) { \
8081                 DRM_ERROR("mismatch in " #name " " \
8082                           "(expected %i, found %i)\n", \
8083                           current_config->name & (mask), \
8084                           pipe_config->name & (mask)); \
8085                 return false; \
8086         }
8087
8088 #define PIPE_CONF_QUIRK(quirk)  \
8089         ((current_config->quirks | pipe_config->quirks) & (quirk))
8090
8091         PIPE_CONF_CHECK_I(cpu_transcoder);
8092
8093         PIPE_CONF_CHECK_I(has_pch_encoder);
8094         PIPE_CONF_CHECK_I(fdi_lanes);
8095         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8096         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8097         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8098         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8099         PIPE_CONF_CHECK_I(fdi_m_n.tu);
8100
8101         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8102         PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8103         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8104         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8105         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8106         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8107
8108         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8109         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8110         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8111         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8112         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8113         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8114
8115         if (!HAS_PCH_SPLIT(dev))
8116                 PIPE_CONF_CHECK_I(pixel_multiplier);
8117
8118         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8119                               DRM_MODE_FLAG_INTERLACE);
8120
8121         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8122                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8123                                       DRM_MODE_FLAG_PHSYNC);
8124                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8125                                       DRM_MODE_FLAG_NHSYNC);
8126                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8127                                       DRM_MODE_FLAG_PVSYNC);
8128                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8129                                       DRM_MODE_FLAG_NVSYNC);
8130         }
8131
8132         PIPE_CONF_CHECK_I(requested_mode.hdisplay);
8133         PIPE_CONF_CHECK_I(requested_mode.vdisplay);
8134
8135         PIPE_CONF_CHECK_I(gmch_pfit.control);
8136         /* pfit ratios are autocomputed by the hw on gen4+ */
8137         if (INTEL_INFO(dev)->gen < 4)
8138                 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8139         PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8140         PIPE_CONF_CHECK_I(pch_pfit.pos);
8141         PIPE_CONF_CHECK_I(pch_pfit.size);
8142
8143         PIPE_CONF_CHECK_I(ips_enabled);
8144
8145         PIPE_CONF_CHECK_I(shared_dpll);
8146         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8147         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
8148         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
8149
8150 #undef PIPE_CONF_CHECK_X
8151 #undef PIPE_CONF_CHECK_I
8152 #undef PIPE_CONF_CHECK_FLAGS
8153 #undef PIPE_CONF_QUIRK
8154
8155         return true;
8156 }
8157
8158 static void
8159 check_connector_state(struct drm_device *dev)
8160 {
8161         struct intel_connector *connector;
8162
8163         list_for_each_entry(connector, &dev->mode_config.connector_list,
8164                             base.head) {
8165                 /* This also checks the encoder/connector hw state with the
8166                  * ->get_hw_state callbacks. */
8167                 intel_connector_check_state(connector);
8168
8169                 WARN(&connector->new_encoder->base != connector->base.encoder,
8170                      "connector's staged encoder doesn't match current encoder\n");
8171         }
8172 }
8173
8174 static void
8175 check_encoder_state(struct drm_device *dev)
8176 {
8177         struct intel_encoder *encoder;
8178         struct intel_connector *connector;
8179
8180         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8181                             base.head) {
8182                 bool enabled = false;
8183                 bool active = false;
8184                 enum pipe pipe, tracked_pipe;
8185
8186                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8187                               encoder->base.base.id,
8188                               drm_get_encoder_name(&encoder->base));
8189
8190                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8191                      "encoder's stage crtc doesn't match current crtc\n");
8192                 WARN(encoder->connectors_active && !encoder->base.crtc,
8193                      "encoder's active_connectors set, but no crtc\n");
8194
8195                 list_for_each_entry(connector, &dev->mode_config.connector_list,
8196                                     base.head) {
8197                         if (connector->base.encoder != &encoder->base)
8198                                 continue;
8199                         enabled = true;
8200                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8201                                 active = true;
8202                 }
8203                 WARN(!!encoder->base.crtc != enabled,
8204                      "encoder's enabled state mismatch "
8205                      "(expected %i, found %i)\n",
8206                      !!encoder->base.crtc, enabled);
8207                 WARN(active && !encoder->base.crtc,
8208                      "active encoder with no crtc\n");
8209
8210                 WARN(encoder->connectors_active != active,
8211                      "encoder's computed active state doesn't match tracked active state "
8212                      "(expected %i, found %i)\n", active, encoder->connectors_active);
8213
8214                 active = encoder->get_hw_state(encoder, &pipe);
8215                 WARN(active != encoder->connectors_active,
8216                      "encoder's hw state doesn't match sw tracking "
8217                      "(expected %i, found %i)\n",
8218                      encoder->connectors_active, active);
8219
8220                 if (!encoder->base.crtc)
8221                         continue;
8222
8223                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8224                 WARN(active && pipe != tracked_pipe,
8225                      "active encoder's pipe doesn't match"
8226                      "(expected %i, found %i)\n",
8227                      tracked_pipe, pipe);
8228
8229         }
8230 }
8231
8232 static void
8233 check_crtc_state(struct drm_device *dev)
8234 {
8235         drm_i915_private_t *dev_priv = dev->dev_private;
8236         struct intel_crtc *crtc;
8237         struct intel_encoder *encoder;
8238         struct intel_crtc_config pipe_config;
8239
8240         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8241                             base.head) {
8242                 bool enabled = false;
8243                 bool active = false;
8244
8245                 memset(&pipe_config, 0, sizeof(pipe_config));
8246
8247                 DRM_DEBUG_KMS("[CRTC:%d]\n",
8248                               crtc->base.base.id);
8249
8250                 WARN(crtc->active && !crtc->base.enabled,
8251                      "active crtc, but not enabled in sw tracking\n");
8252
8253                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8254                                     base.head) {
8255                         if (encoder->base.crtc != &crtc->base)
8256                                 continue;
8257                         enabled = true;
8258                         if (encoder->connectors_active)
8259                                 active = true;
8260                 }
8261
8262                 WARN(active != crtc->active,
8263                      "crtc's computed active state doesn't match tracked active state "
8264                      "(expected %i, found %i)\n", active, crtc->active);
8265                 WARN(enabled != crtc->base.enabled,
8266                      "crtc's computed enabled state doesn't match tracked enabled state "
8267                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8268
8269                 active = dev_priv->display.get_pipe_config(crtc,
8270                                                            &pipe_config);
8271                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8272                                     base.head) {
8273                         if (encoder->base.crtc != &crtc->base)
8274                                 continue;
8275                         if (encoder->get_config)
8276                                 encoder->get_config(encoder, &pipe_config);
8277                 }
8278
8279                 WARN(crtc->active != active,
8280                      "crtc active state doesn't match with hw state "
8281                      "(expected %i, found %i)\n", crtc->active, active);
8282
8283                 if (active &&
8284                     !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
8285                         WARN(1, "pipe state doesn't match!\n");
8286                         intel_dump_pipe_config(crtc, &pipe_config,
8287                                                "[hw state]");
8288                         intel_dump_pipe_config(crtc, &crtc->config,
8289                                                "[sw state]");
8290                 }
8291         }
8292 }
8293
8294 static void
8295 check_shared_dpll_state(struct drm_device *dev)
8296 {
8297         drm_i915_private_t *dev_priv = dev->dev_private;
8298         struct intel_crtc *crtc;
8299         struct intel_dpll_hw_state dpll_hw_state;
8300         int i;
8301
8302         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8303                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
8304                 int enabled_crtcs = 0, active_crtcs = 0;
8305                 bool active;
8306
8307                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
8308
8309                 DRM_DEBUG_KMS("%s\n", pll->name);
8310
8311                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
8312
8313                 WARN(pll->active > pll->refcount,
8314                      "more active pll users than references: %i vs %i\n",
8315                      pll->active, pll->refcount);
8316                 WARN(pll->active && !pll->on,
8317                      "pll in active use but not on in sw tracking\n");
8318                 WARN(pll->on != active,
8319                      "pll on state mismatch (expected %i, found %i)\n",
8320                      pll->on, active);
8321
8322                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8323                                     base.head) {
8324                         if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
8325                                 enabled_crtcs++;
8326                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
8327                                 active_crtcs++;
8328                 }
8329                 WARN(pll->active != active_crtcs,
8330                      "pll active crtcs mismatch (expected %i, found %i)\n",
8331                      pll->active, active_crtcs);
8332                 WARN(pll->refcount != enabled_crtcs,
8333                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
8334                      pll->refcount, enabled_crtcs);
8335
8336                 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
8337                                        sizeof(dpll_hw_state)),
8338                      "pll hw state mismatch\n");
8339         }
8340 }
8341
8342 void
8343 intel_modeset_check_state(struct drm_device *dev)
8344 {
8345         check_connector_state(dev);
8346         check_encoder_state(dev);
8347         check_crtc_state(dev);
8348         check_shared_dpll_state(dev);
8349 }
8350
8351 static int __intel_set_mode(struct drm_crtc *crtc,
8352                             struct drm_display_mode *mode,
8353                             int x, int y, struct drm_framebuffer *fb)
8354 {
8355         struct drm_device *dev = crtc->dev;
8356         drm_i915_private_t *dev_priv = dev->dev_private;
8357         struct drm_display_mode *saved_mode, *saved_hwmode;
8358         struct intel_crtc_config *pipe_config = NULL;
8359         struct intel_crtc *intel_crtc;
8360         unsigned disable_pipes, prepare_pipes, modeset_pipes;
8361         int ret = 0;
8362
8363         saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
8364         if (!saved_mode)
8365                 return -ENOMEM;
8366         saved_hwmode = saved_mode + 1;
8367
8368         intel_modeset_affected_pipes(crtc, &modeset_pipes,
8369                                      &prepare_pipes, &disable_pipes);
8370
8371         *saved_hwmode = crtc->hwmode;
8372         *saved_mode = crtc->mode;
8373
8374         /* Hack: Because we don't (yet) support global modeset on multiple
8375          * crtcs, we don't keep track of the new mode for more than one crtc.
8376          * Hence simply check whether any bit is set in modeset_pipes in all the
8377          * pieces of code that are not yet converted to deal with mutliple crtcs
8378          * changing their mode at the same time. */
8379         if (modeset_pipes) {
8380                 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
8381                 if (IS_ERR(pipe_config)) {
8382                         ret = PTR_ERR(pipe_config);
8383                         pipe_config = NULL;
8384
8385                         goto out;
8386                 }
8387                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
8388                                        "[modeset]");
8389         }
8390
8391         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8392                 intel_crtc_disable(&intel_crtc->base);
8393
8394         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8395                 if (intel_crtc->base.enabled)
8396                         dev_priv->display.crtc_disable(&intel_crtc->base);
8397         }
8398
8399         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8400          * to set it here already despite that we pass it down the callchain.
8401          */
8402         if (modeset_pipes) {
8403                 crtc->mode = *mode;
8404                 /* mode_set/enable/disable functions rely on a correct pipe
8405                  * config. */
8406                 to_intel_crtc(crtc)->config = *pipe_config;
8407         }
8408
8409         /* Only after disabling all output pipelines that will be changed can we
8410          * update the the output configuration. */
8411         intel_modeset_update_state(dev, prepare_pipes);
8412
8413         if (dev_priv->display.modeset_global_resources)
8414                 dev_priv->display.modeset_global_resources(dev);
8415
8416         /* Set up the DPLL and any encoders state that needs to adjust or depend
8417          * on the DPLL.
8418          */
8419         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
8420                 ret = intel_crtc_mode_set(&intel_crtc->base,
8421                                           x, y, fb);
8422                 if (ret)
8423                         goto done;
8424         }
8425
8426         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
8427         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8428                 dev_priv->display.crtc_enable(&intel_crtc->base);
8429
8430         if (modeset_pipes) {
8431                 /* Store real post-adjustment hardware mode. */
8432                 crtc->hwmode = pipe_config->adjusted_mode;
8433
8434                 /* Calculate and store various constants which
8435                  * are later needed by vblank and swap-completion
8436                  * timestamping. They are derived from true hwmode.
8437                  */
8438                 drm_calc_timestamping_constants(crtc);
8439         }
8440
8441         /* FIXME: add subpixel order */
8442 done:
8443         if (ret && crtc->enabled) {
8444                 crtc->hwmode = *saved_hwmode;
8445                 crtc->mode = *saved_mode;
8446         }
8447
8448 out:
8449         kfree(pipe_config);
8450         kfree(saved_mode);
8451         return ret;
8452 }
8453
8454 int intel_set_mode(struct drm_crtc *crtc,
8455                      struct drm_display_mode *mode,
8456                      int x, int y, struct drm_framebuffer *fb)
8457 {
8458         int ret;
8459
8460         ret = __intel_set_mode(crtc, mode, x, y, fb);
8461
8462         if (ret == 0)
8463                 intel_modeset_check_state(crtc->dev);
8464
8465         return ret;
8466 }
8467
8468 void intel_crtc_restore_mode(struct drm_crtc *crtc)
8469 {
8470         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8471 }
8472
8473 #undef for_each_intel_crtc_masked
8474
8475 static void intel_set_config_free(struct intel_set_config *config)
8476 {
8477         if (!config)
8478                 return;
8479
8480         kfree(config->save_connector_encoders);
8481         kfree(config->save_encoder_crtcs);
8482         kfree(config);
8483 }
8484
8485 static int intel_set_config_save_state(struct drm_device *dev,
8486                                        struct intel_set_config *config)
8487 {
8488         struct drm_encoder *encoder;
8489         struct drm_connector *connector;
8490         int count;
8491
8492         config->save_encoder_crtcs =
8493                 kcalloc(dev->mode_config.num_encoder,
8494                         sizeof(struct drm_crtc *), GFP_KERNEL);
8495         if (!config->save_encoder_crtcs)
8496                 return -ENOMEM;
8497
8498         config->save_connector_encoders =
8499                 kcalloc(dev->mode_config.num_connector,
8500                         sizeof(struct drm_encoder *), GFP_KERNEL);
8501         if (!config->save_connector_encoders)
8502                 return -ENOMEM;
8503
8504         /* Copy data. Note that driver private data is not affected.
8505          * Should anything bad happen only the expected state is
8506          * restored, not the drivers personal bookkeeping.
8507          */
8508         count = 0;
8509         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
8510                 config->save_encoder_crtcs[count++] = encoder->crtc;
8511         }
8512
8513         count = 0;
8514         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8515                 config->save_connector_encoders[count++] = connector->encoder;
8516         }
8517
8518         return 0;
8519 }
8520
8521 static void intel_set_config_restore_state(struct drm_device *dev,
8522                                            struct intel_set_config *config)
8523 {
8524         struct intel_encoder *encoder;
8525         struct intel_connector *connector;
8526         int count;
8527
8528         count = 0;
8529         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8530                 encoder->new_crtc =
8531                         to_intel_crtc(config->save_encoder_crtcs[count++]);
8532         }
8533
8534         count = 0;
8535         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8536                 connector->new_encoder =
8537                         to_intel_encoder(config->save_connector_encoders[count++]);
8538         }
8539 }
8540
8541 static void
8542 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8543                                       struct intel_set_config *config)
8544 {
8545
8546         /* We should be able to check here if the fb has the same properties
8547          * and then just flip_or_move it */
8548         if (set->crtc->fb != set->fb) {
8549                 /* If we have no fb then treat it as a full mode set */
8550                 if (set->crtc->fb == NULL) {
8551                         DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8552                         config->mode_changed = true;
8553                 } else if (set->fb == NULL) {
8554                         config->mode_changed = true;
8555                 } else if (set->fb->pixel_format !=
8556                            set->crtc->fb->pixel_format) {
8557                         config->mode_changed = true;
8558                 } else
8559                         config->fb_changed = true;
8560         }
8561
8562         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
8563                 config->fb_changed = true;
8564
8565         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8566                 DRM_DEBUG_KMS("modes are different, full mode set\n");
8567                 drm_mode_debug_printmodeline(&set->crtc->mode);
8568                 drm_mode_debug_printmodeline(set->mode);
8569                 config->mode_changed = true;
8570         }
8571 }
8572
8573 static int
8574 intel_modeset_stage_output_state(struct drm_device *dev,
8575                                  struct drm_mode_set *set,
8576                                  struct intel_set_config *config)
8577 {
8578         struct drm_crtc *new_crtc;
8579         struct intel_connector *connector;
8580         struct intel_encoder *encoder;
8581         int count, ro;
8582
8583         /* The upper layers ensure that we either disable a crtc or have a list
8584          * of connectors. For paranoia, double-check this. */
8585         WARN_ON(!set->fb && (set->num_connectors != 0));
8586         WARN_ON(set->fb && (set->num_connectors == 0));
8587
8588         count = 0;
8589         list_for_each_entry(connector, &dev->mode_config.connector_list,
8590                             base.head) {
8591                 /* Otherwise traverse passed in connector list and get encoders
8592                  * for them. */
8593                 for (ro = 0; ro < set->num_connectors; ro++) {
8594                         if (set->connectors[ro] == &connector->base) {
8595                                 connector->new_encoder = connector->encoder;
8596                                 break;
8597                         }
8598                 }
8599
8600                 /* If we disable the crtc, disable all its connectors. Also, if
8601                  * the connector is on the changing crtc but not on the new
8602                  * connector list, disable it. */
8603                 if ((!set->fb || ro == set->num_connectors) &&
8604                     connector->base.encoder &&
8605                     connector->base.encoder->crtc == set->crtc) {
8606                         connector->new_encoder = NULL;
8607
8608                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8609                                 connector->base.base.id,
8610                                 drm_get_connector_name(&connector->base));
8611                 }
8612
8613
8614                 if (&connector->new_encoder->base != connector->base.encoder) {
8615                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
8616                         config->mode_changed = true;
8617                 }
8618         }
8619         /* connector->new_encoder is now updated for all connectors. */
8620
8621         /* Update crtc of enabled connectors. */
8622         count = 0;
8623         list_for_each_entry(connector, &dev->mode_config.connector_list,
8624                             base.head) {
8625                 if (!connector->new_encoder)
8626                         continue;
8627
8628                 new_crtc = connector->new_encoder->base.crtc;
8629
8630                 for (ro = 0; ro < set->num_connectors; ro++) {
8631                         if (set->connectors[ro] == &connector->base)
8632                                 new_crtc = set->crtc;
8633                 }
8634
8635                 /* Make sure the new CRTC will work with the encoder */
8636                 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8637                                            new_crtc)) {
8638                         return -EINVAL;
8639                 }
8640                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8641
8642                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8643                         connector->base.base.id,
8644                         drm_get_connector_name(&connector->base),
8645                         new_crtc->base.id);
8646         }
8647
8648         /* Check for any encoders that needs to be disabled. */
8649         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8650                             base.head) {
8651                 list_for_each_entry(connector,
8652                                     &dev->mode_config.connector_list,
8653                                     base.head) {
8654                         if (connector->new_encoder == encoder) {
8655                                 WARN_ON(!connector->new_encoder->new_crtc);
8656
8657                                 goto next_encoder;
8658                         }
8659                 }
8660                 encoder->new_crtc = NULL;
8661 next_encoder:
8662                 /* Only now check for crtc changes so we don't miss encoders
8663                  * that will be disabled. */
8664                 if (&encoder->new_crtc->base != encoder->base.crtc) {
8665                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8666                         config->mode_changed = true;
8667                 }
8668         }
8669         /* Now we've also updated encoder->new_crtc for all encoders. */
8670
8671         return 0;
8672 }
8673
8674 static int intel_crtc_set_config(struct drm_mode_set *set)
8675 {
8676         struct drm_device *dev;
8677         struct drm_mode_set save_set;
8678         struct intel_set_config *config;
8679         int ret;
8680
8681         BUG_ON(!set);
8682         BUG_ON(!set->crtc);
8683         BUG_ON(!set->crtc->helper_private);
8684
8685         /* Enforce sane interface api - has been abused by the fb helper. */
8686         BUG_ON(!set->mode && set->fb);
8687         BUG_ON(set->fb && set->num_connectors == 0);
8688
8689         if (set->fb) {
8690                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8691                                 set->crtc->base.id, set->fb->base.id,
8692                                 (int)set->num_connectors, set->x, set->y);
8693         } else {
8694                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
8695         }
8696
8697         dev = set->crtc->dev;
8698
8699         ret = -ENOMEM;
8700         config = kzalloc(sizeof(*config), GFP_KERNEL);
8701         if (!config)
8702                 goto out_config;
8703
8704         ret = intel_set_config_save_state(dev, config);
8705         if (ret)
8706                 goto out_config;
8707
8708         save_set.crtc = set->crtc;
8709         save_set.mode = &set->crtc->mode;
8710         save_set.x = set->crtc->x;
8711         save_set.y = set->crtc->y;
8712         save_set.fb = set->crtc->fb;
8713
8714         /* Compute whether we need a full modeset, only an fb base update or no
8715          * change at all. In the future we might also check whether only the
8716          * mode changed, e.g. for LVDS where we only change the panel fitter in
8717          * such cases. */
8718         intel_set_config_compute_mode_changes(set, config);
8719
8720         ret = intel_modeset_stage_output_state(dev, set, config);
8721         if (ret)
8722                 goto fail;
8723
8724         if (config->mode_changed) {
8725                 ret = intel_set_mode(set->crtc, set->mode,
8726                                      set->x, set->y, set->fb);
8727                 if (ret) {
8728                         DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8729                                   set->crtc->base.id, ret);
8730                         goto fail;
8731                 }
8732         } else if (config->fb_changed) {
8733                 intel_crtc_wait_for_pending_flips(set->crtc);
8734
8735                 ret = intel_pipe_set_base(set->crtc,
8736                                           set->x, set->y, set->fb);
8737         }
8738
8739         intel_set_config_free(config);
8740
8741         return 0;
8742
8743 fail:
8744         intel_set_config_restore_state(dev, config);
8745
8746         /* Try to restore the config */
8747         if (config->mode_changed &&
8748             intel_set_mode(save_set.crtc, save_set.mode,
8749                            save_set.x, save_set.y, save_set.fb))
8750                 DRM_ERROR("failed to restore config after modeset failure\n");
8751
8752 out_config:
8753         intel_set_config_free(config);
8754         return ret;
8755 }
8756
8757 static const struct drm_crtc_funcs intel_crtc_funcs = {
8758         .cursor_set = intel_crtc_cursor_set,
8759         .cursor_move = intel_crtc_cursor_move,
8760         .gamma_set = intel_crtc_gamma_set,
8761         .set_config = intel_crtc_set_config,
8762         .destroy = intel_crtc_destroy,
8763         .page_flip = intel_crtc_page_flip,
8764 };
8765
8766 static void intel_cpu_pll_init(struct drm_device *dev)
8767 {
8768         if (HAS_DDI(dev))
8769                 intel_ddi_pll_init(dev);
8770 }
8771
8772 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
8773                                       struct intel_shared_dpll *pll,
8774                                       struct intel_dpll_hw_state *hw_state)
8775 {
8776         uint32_t val;
8777
8778         val = I915_READ(PCH_DPLL(pll->id));
8779         hw_state->dpll = val;
8780         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
8781         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
8782
8783         return val & DPLL_VCO_ENABLE;
8784 }
8785
8786 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
8787                                 struct intel_shared_dpll *pll)
8788 {
8789         uint32_t reg, val;
8790
8791         /* PCH refclock must be enabled first */
8792         assert_pch_refclk_enabled(dev_priv);
8793
8794         reg = PCH_DPLL(pll->id);
8795         val = I915_READ(reg);
8796         val |= DPLL_VCO_ENABLE;
8797         I915_WRITE(reg, val);
8798         POSTING_READ(reg);
8799         udelay(200);
8800 }
8801
8802 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
8803                                  struct intel_shared_dpll *pll)
8804 {
8805         struct drm_device *dev = dev_priv->dev;
8806         struct intel_crtc *crtc;
8807         uint32_t reg, val;
8808
8809         /* Make sure no transcoder isn't still depending on us. */
8810         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
8811                 if (intel_crtc_to_shared_dpll(crtc) == pll)
8812                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
8813         }
8814
8815         reg = PCH_DPLL(pll->id);
8816         val = I915_READ(reg);
8817         val &= ~DPLL_VCO_ENABLE;
8818         I915_WRITE(reg, val);
8819         POSTING_READ(reg);
8820         udelay(200);
8821 }
8822
8823 static char *ibx_pch_dpll_names[] = {
8824         "PCH DPLL A",
8825         "PCH DPLL B",
8826 };
8827
8828 static void ibx_pch_dpll_init(struct drm_device *dev)
8829 {
8830         struct drm_i915_private *dev_priv = dev->dev_private;
8831         int i;
8832
8833         dev_priv->num_shared_dpll = 2;
8834
8835         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8836                 dev_priv->shared_dplls[i].id = i;
8837                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
8838                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
8839                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
8840                 dev_priv->shared_dplls[i].get_hw_state =
8841                         ibx_pch_dpll_get_hw_state;
8842         }
8843 }
8844
8845 static void intel_shared_dpll_init(struct drm_device *dev)
8846 {
8847         struct drm_i915_private *dev_priv = dev->dev_private;
8848
8849         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8850                 ibx_pch_dpll_init(dev);
8851         else
8852                 dev_priv->num_shared_dpll = 0;
8853
8854         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
8855         DRM_DEBUG_KMS("%i shared PLLs initialized\n",
8856                       dev_priv->num_shared_dpll);
8857 }
8858
8859 static void intel_crtc_init(struct drm_device *dev, int pipe)
8860 {
8861         drm_i915_private_t *dev_priv = dev->dev_private;
8862         struct intel_crtc *intel_crtc;
8863         int i;
8864
8865         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8866         if (intel_crtc == NULL)
8867                 return;
8868
8869         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8870
8871         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
8872         for (i = 0; i < 256; i++) {
8873                 intel_crtc->lut_r[i] = i;
8874                 intel_crtc->lut_g[i] = i;
8875                 intel_crtc->lut_b[i] = i;
8876         }
8877
8878         /* Swap pipes & planes for FBC on pre-965 */
8879         intel_crtc->pipe = pipe;
8880         intel_crtc->plane = pipe;
8881         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
8882                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8883                 intel_crtc->plane = !pipe;
8884         }
8885
8886         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8887                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8888         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8889         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8890
8891         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
8892 }
8893
8894 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
8895                                 struct drm_file *file)
8896 {
8897         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
8898         struct drm_mode_object *drmmode_obj;
8899         struct intel_crtc *crtc;
8900
8901         if (!drm_core_check_feature(dev, DRIVER_MODESET))
8902                 return -ENODEV;
8903
8904         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8905                         DRM_MODE_OBJECT_CRTC);
8906
8907         if (!drmmode_obj) {
8908                 DRM_ERROR("no such CRTC id\n");
8909                 return -EINVAL;
8910         }
8911
8912         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8913         pipe_from_crtc_id->pipe = crtc->pipe;
8914
8915         return 0;
8916 }
8917
8918 static int intel_encoder_clones(struct intel_encoder *encoder)
8919 {
8920         struct drm_device *dev = encoder->base.dev;
8921         struct intel_encoder *source_encoder;
8922         int index_mask = 0;
8923         int entry = 0;
8924
8925         list_for_each_entry(source_encoder,
8926                             &dev->mode_config.encoder_list, base.head) {
8927
8928                 if (encoder == source_encoder)
8929                         index_mask |= (1 << entry);
8930
8931                 /* Intel hw has only one MUX where enocoders could be cloned. */
8932                 if (encoder->cloneable && source_encoder->cloneable)
8933                         index_mask |= (1 << entry);
8934
8935                 entry++;
8936         }
8937
8938         return index_mask;
8939 }
8940
8941 static bool has_edp_a(struct drm_device *dev)
8942 {
8943         struct drm_i915_private *dev_priv = dev->dev_private;
8944
8945         if (!IS_MOBILE(dev))
8946                 return false;
8947
8948         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8949                 return false;
8950
8951         if (IS_GEN5(dev) &&
8952             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8953                 return false;
8954
8955         return true;
8956 }
8957
8958 static void intel_setup_outputs(struct drm_device *dev)
8959 {
8960         struct drm_i915_private *dev_priv = dev->dev_private;
8961         struct intel_encoder *encoder;
8962         bool dpd_is_edp = false;
8963
8964         intel_lvds_init(dev);
8965
8966         if (!IS_ULT(dev))
8967                 intel_crt_init(dev);
8968
8969         if (HAS_DDI(dev)) {
8970                 int found;
8971
8972                 /* Haswell uses DDI functions to detect digital outputs */
8973                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8974                 /* DDI A only supports eDP */
8975                 if (found)
8976                         intel_ddi_init(dev, PORT_A);
8977
8978                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8979                  * register */
8980                 found = I915_READ(SFUSE_STRAP);
8981
8982                 if (found & SFUSE_STRAP_DDIB_DETECTED)
8983                         intel_ddi_init(dev, PORT_B);
8984                 if (found & SFUSE_STRAP_DDIC_DETECTED)
8985                         intel_ddi_init(dev, PORT_C);
8986                 if (found & SFUSE_STRAP_DDID_DETECTED)
8987                         intel_ddi_init(dev, PORT_D);
8988         } else if (HAS_PCH_SPLIT(dev)) {
8989                 int found;
8990                 dpd_is_edp = intel_dpd_is_edp(dev);
8991
8992                 if (has_edp_a(dev))
8993                         intel_dp_init(dev, DP_A, PORT_A);
8994
8995                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
8996                         /* PCH SDVOB multiplex with HDMIB */
8997                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
8998                         if (!found)
8999                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
9000                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
9001                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
9002                 }
9003
9004                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
9005                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
9006
9007                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
9008                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
9009
9010                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
9011                         intel_dp_init(dev, PCH_DP_C, PORT_C);
9012
9013                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
9014                         intel_dp_init(dev, PCH_DP_D, PORT_D);
9015         } else if (IS_VALLEYVIEW(dev)) {
9016                 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
9017                 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
9018                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
9019
9020                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
9021                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
9022                                         PORT_B);
9023                         if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
9024                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
9025                 }
9026         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
9027                 bool found = false;
9028
9029                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
9030                         DRM_DEBUG_KMS("probing SDVOB\n");
9031                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
9032                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
9033                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
9034                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
9035                         }
9036
9037                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
9038                                 intel_dp_init(dev, DP_B, PORT_B);
9039                 }
9040
9041                 /* Before G4X SDVOC doesn't have its own detect register */
9042
9043                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
9044                         DRM_DEBUG_KMS("probing SDVOC\n");
9045                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
9046                 }
9047
9048                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
9049
9050                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
9051                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
9052                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
9053                         }
9054                         if (SUPPORTS_INTEGRATED_DP(dev))
9055                                 intel_dp_init(dev, DP_C, PORT_C);
9056                 }
9057
9058                 if (SUPPORTS_INTEGRATED_DP(dev) &&
9059                     (I915_READ(DP_D) & DP_DETECTED))
9060                         intel_dp_init(dev, DP_D, PORT_D);
9061         } else if (IS_GEN2(dev))
9062                 intel_dvo_init(dev);
9063
9064         if (SUPPORTS_TV(dev))
9065                 intel_tv_init(dev);
9066
9067         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9068                 encoder->base.possible_crtcs = encoder->crtc_mask;
9069                 encoder->base.possible_clones =
9070                         intel_encoder_clones(encoder);
9071         }
9072
9073         intel_init_pch_refclk(dev);
9074
9075         drm_helper_move_panel_connectors_to_head(dev);
9076 }
9077
9078 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
9079 {
9080         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9081
9082         drm_framebuffer_cleanup(fb);
9083         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
9084
9085         kfree(intel_fb);
9086 }
9087
9088 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
9089                                                 struct drm_file *file,
9090                                                 unsigned int *handle)
9091 {
9092         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9093         struct drm_i915_gem_object *obj = intel_fb->obj;
9094
9095         return drm_gem_handle_create(file, &obj->base, handle);
9096 }
9097
9098 static const struct drm_framebuffer_funcs intel_fb_funcs = {
9099         .destroy = intel_user_framebuffer_destroy,
9100         .create_handle = intel_user_framebuffer_create_handle,
9101 };
9102
9103 int intel_framebuffer_init(struct drm_device *dev,
9104                            struct intel_framebuffer *intel_fb,
9105                            struct drm_mode_fb_cmd2 *mode_cmd,
9106                            struct drm_i915_gem_object *obj)
9107 {
9108         int ret;
9109
9110         if (obj->tiling_mode == I915_TILING_Y) {
9111                 DRM_DEBUG("hardware does not support tiling Y\n");
9112                 return -EINVAL;
9113         }
9114
9115         if (mode_cmd->pitches[0] & 63) {
9116                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9117                           mode_cmd->pitches[0]);
9118                 return -EINVAL;
9119         }
9120
9121         /* FIXME <= Gen4 stride limits are bit unclear */
9122         if (mode_cmd->pitches[0] > 32768) {
9123                 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
9124                           mode_cmd->pitches[0]);
9125                 return -EINVAL;
9126         }
9127
9128         if (obj->tiling_mode != I915_TILING_NONE &&
9129             mode_cmd->pitches[0] != obj->stride) {
9130                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
9131                           mode_cmd->pitches[0], obj->stride);
9132                 return -EINVAL;
9133         }
9134
9135         /* Reject formats not supported by any plane early. */
9136         switch (mode_cmd->pixel_format) {
9137         case DRM_FORMAT_C8:
9138         case DRM_FORMAT_RGB565:
9139         case DRM_FORMAT_XRGB8888:
9140         case DRM_FORMAT_ARGB8888:
9141                 break;
9142         case DRM_FORMAT_XRGB1555:
9143         case DRM_FORMAT_ARGB1555:
9144                 if (INTEL_INFO(dev)->gen > 3) {
9145                         DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
9146                         return -EINVAL;
9147                 }
9148                 break;
9149         case DRM_FORMAT_XBGR8888:
9150         case DRM_FORMAT_ABGR8888:
9151         case DRM_FORMAT_XRGB2101010:
9152         case DRM_FORMAT_ARGB2101010:
9153         case DRM_FORMAT_XBGR2101010:
9154         case DRM_FORMAT_ABGR2101010:
9155                 if (INTEL_INFO(dev)->gen < 4) {
9156                         DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
9157                         return -EINVAL;
9158                 }
9159                 break;
9160         case DRM_FORMAT_YUYV:
9161         case DRM_FORMAT_UYVY:
9162         case DRM_FORMAT_YVYU:
9163         case DRM_FORMAT_VYUY:
9164                 if (INTEL_INFO(dev)->gen < 5) {
9165                         DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
9166                         return -EINVAL;
9167                 }
9168                 break;
9169         default:
9170                 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
9171                 return -EINVAL;
9172         }
9173
9174         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
9175         if (mode_cmd->offsets[0] != 0)
9176                 return -EINVAL;
9177
9178         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
9179         intel_fb->obj = obj;
9180
9181         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
9182         if (ret) {
9183                 DRM_ERROR("framebuffer init failed %d\n", ret);
9184                 return ret;
9185         }
9186
9187         return 0;
9188 }
9189
9190 static struct drm_framebuffer *
9191 intel_user_framebuffer_create(struct drm_device *dev,
9192                               struct drm_file *filp,
9193                               struct drm_mode_fb_cmd2 *mode_cmd)
9194 {
9195         struct drm_i915_gem_object *obj;
9196
9197         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
9198                                                 mode_cmd->handles[0]));
9199         if (&obj->base == NULL)
9200                 return ERR_PTR(-ENOENT);
9201
9202         return intel_framebuffer_create(dev, mode_cmd, obj);
9203 }
9204
9205 static const struct drm_mode_config_funcs intel_mode_funcs = {
9206         .fb_create = intel_user_framebuffer_create,
9207         .output_poll_changed = intel_fb_output_poll_changed,
9208 };
9209
9210 /* Set up chip specific display functions */
9211 static void intel_init_display(struct drm_device *dev)
9212 {
9213         struct drm_i915_private *dev_priv = dev->dev_private;
9214
9215         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
9216                 dev_priv->display.find_dpll = g4x_find_best_dpll;
9217         else if (IS_VALLEYVIEW(dev))
9218                 dev_priv->display.find_dpll = vlv_find_best_dpll;
9219         else if (IS_PINEVIEW(dev))
9220                 dev_priv->display.find_dpll = pnv_find_best_dpll;
9221         else
9222                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
9223
9224         if (HAS_DDI(dev)) {
9225                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
9226                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
9227                 dev_priv->display.crtc_enable = haswell_crtc_enable;
9228                 dev_priv->display.crtc_disable = haswell_crtc_disable;
9229                 dev_priv->display.off = haswell_crtc_off;
9230                 dev_priv->display.update_plane = ironlake_update_plane;
9231         } else if (HAS_PCH_SPLIT(dev)) {
9232                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
9233                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
9234                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9235                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
9236                 dev_priv->display.off = ironlake_crtc_off;
9237                 dev_priv->display.update_plane = ironlake_update_plane;
9238         } else if (IS_VALLEYVIEW(dev)) {
9239                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9240                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9241                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9242                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9243                 dev_priv->display.off = i9xx_crtc_off;
9244                 dev_priv->display.update_plane = i9xx_update_plane;
9245         } else {
9246                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9247                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9248                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
9249                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9250                 dev_priv->display.off = i9xx_crtc_off;
9251                 dev_priv->display.update_plane = i9xx_update_plane;
9252         }
9253
9254         /* Returns the core display clock speed */
9255         if (IS_VALLEYVIEW(dev))
9256                 dev_priv->display.get_display_clock_speed =
9257                         valleyview_get_display_clock_speed;
9258         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
9259                 dev_priv->display.get_display_clock_speed =
9260                         i945_get_display_clock_speed;
9261         else if (IS_I915G(dev))
9262                 dev_priv->display.get_display_clock_speed =
9263                         i915_get_display_clock_speed;
9264         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
9265                 dev_priv->display.get_display_clock_speed =
9266                         i9xx_misc_get_display_clock_speed;
9267         else if (IS_I915GM(dev))
9268                 dev_priv->display.get_display_clock_speed =
9269                         i915gm_get_display_clock_speed;
9270         else if (IS_I865G(dev))
9271                 dev_priv->display.get_display_clock_speed =
9272                         i865_get_display_clock_speed;
9273         else if (IS_I85X(dev))
9274                 dev_priv->display.get_display_clock_speed =
9275                         i855_get_display_clock_speed;
9276         else /* 852, 830 */
9277                 dev_priv->display.get_display_clock_speed =
9278                         i830_get_display_clock_speed;
9279
9280         if (HAS_PCH_SPLIT(dev)) {
9281                 if (IS_GEN5(dev)) {
9282                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
9283                         dev_priv->display.write_eld = ironlake_write_eld;
9284                 } else if (IS_GEN6(dev)) {
9285                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
9286                         dev_priv->display.write_eld = ironlake_write_eld;
9287                 } else if (IS_IVYBRIDGE(dev)) {
9288                         /* FIXME: detect B0+ stepping and use auto training */
9289                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
9290                         dev_priv->display.write_eld = ironlake_write_eld;
9291                         dev_priv->display.modeset_global_resources =
9292                                 ivb_modeset_global_resources;
9293                 } else if (IS_HASWELL(dev)) {
9294                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
9295                         dev_priv->display.write_eld = haswell_write_eld;
9296                         dev_priv->display.modeset_global_resources =
9297                                 haswell_modeset_global_resources;
9298                 }
9299         } else if (IS_G4X(dev)) {
9300                 dev_priv->display.write_eld = g4x_write_eld;
9301         }
9302
9303         /* Default just returns -ENODEV to indicate unsupported */
9304         dev_priv->display.queue_flip = intel_default_queue_flip;
9305
9306         switch (INTEL_INFO(dev)->gen) {
9307         case 2:
9308                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9309                 break;
9310
9311         case 3:
9312                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9313                 break;
9314
9315         case 4:
9316         case 5:
9317                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9318                 break;
9319
9320         case 6:
9321                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9322                 break;
9323         case 7:
9324                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9325                 break;
9326         }
9327 }
9328
9329 /*
9330  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9331  * resume, or other times.  This quirk makes sure that's the case for
9332  * affected systems.
9333  */
9334 static void quirk_pipea_force(struct drm_device *dev)
9335 {
9336         struct drm_i915_private *dev_priv = dev->dev_private;
9337
9338         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
9339         DRM_INFO("applying pipe a force quirk\n");
9340 }
9341
9342 /*
9343  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9344  */
9345 static void quirk_ssc_force_disable(struct drm_device *dev)
9346 {
9347         struct drm_i915_private *dev_priv = dev->dev_private;
9348         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
9349         DRM_INFO("applying lvds SSC disable quirk\n");
9350 }
9351
9352 /*
9353  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9354  * brightness value
9355  */
9356 static void quirk_invert_brightness(struct drm_device *dev)
9357 {
9358         struct drm_i915_private *dev_priv = dev->dev_private;
9359         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
9360         DRM_INFO("applying inverted panel brightness quirk\n");
9361 }
9362
9363 struct intel_quirk {
9364         int device;
9365         int subsystem_vendor;
9366         int subsystem_device;
9367         void (*hook)(struct drm_device *dev);
9368 };
9369
9370 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9371 struct intel_dmi_quirk {
9372         void (*hook)(struct drm_device *dev);
9373         const struct dmi_system_id (*dmi_id_list)[];
9374 };
9375
9376 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
9377 {
9378         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
9379         return 1;
9380 }
9381
9382 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
9383         {
9384                 .dmi_id_list = &(const struct dmi_system_id[]) {
9385                         {
9386                                 .callback = intel_dmi_reverse_brightness,
9387                                 .ident = "NCR Corporation",
9388                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
9389                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
9390                                 },
9391                         },
9392                         { }  /* terminating entry */
9393                 },
9394                 .hook = quirk_invert_brightness,
9395         },
9396 };
9397
9398 static struct intel_quirk intel_quirks[] = {
9399         /* HP Mini needs pipe A force quirk (LP: #322104) */
9400         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
9401
9402         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9403         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9404
9405         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9406         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9407
9408         /* 830/845 need to leave pipe A & dpll A up */
9409         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9410         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9411
9412         /* Lenovo U160 cannot use SSC on LVDS */
9413         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
9414
9415         /* Sony Vaio Y cannot use SSC on LVDS */
9416         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
9417
9418         /* Acer Aspire 5734Z must invert backlight brightness */
9419         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
9420
9421         /* Acer/eMachines G725 */
9422         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
9423
9424         /* Acer/eMachines e725 */
9425         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
9426
9427         /* Acer/Packard Bell NCL20 */
9428         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
9429
9430         /* Acer Aspire 4736Z */
9431         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
9432 };
9433
9434 static void intel_init_quirks(struct drm_device *dev)
9435 {
9436         struct pci_dev *d = dev->pdev;
9437         int i;
9438
9439         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9440                 struct intel_quirk *q = &intel_quirks[i];
9441
9442                 if (d->device == q->device &&
9443                     (d->subsystem_vendor == q->subsystem_vendor ||
9444                      q->subsystem_vendor == PCI_ANY_ID) &&
9445                     (d->subsystem_device == q->subsystem_device ||
9446                      q->subsystem_device == PCI_ANY_ID))
9447                         q->hook(dev);
9448         }
9449         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
9450                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
9451                         intel_dmi_quirks[i].hook(dev);
9452         }
9453 }
9454
9455 /* Disable the VGA plane that we never use */
9456 static void i915_disable_vga(struct drm_device *dev)
9457 {
9458         struct drm_i915_private *dev_priv = dev->dev_private;
9459         u8 sr1;
9460         u32 vga_reg = i915_vgacntrl_reg(dev);
9461
9462         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
9463         outb(SR01, VGA_SR_INDEX);
9464         sr1 = inb(VGA_SR_DATA);
9465         outb(sr1 | 1<<5, VGA_SR_DATA);
9466         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9467         udelay(300);
9468
9469         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9470         POSTING_READ(vga_reg);
9471 }
9472
9473 void intel_modeset_init_hw(struct drm_device *dev)
9474 {
9475         intel_init_power_well(dev);
9476
9477         intel_prepare_ddi(dev);
9478
9479         intel_init_clock_gating(dev);
9480
9481         mutex_lock(&dev->struct_mutex);
9482         intel_enable_gt_powersave(dev);
9483         mutex_unlock(&dev->struct_mutex);
9484 }
9485
9486 void intel_modeset_suspend_hw(struct drm_device *dev)
9487 {
9488         intel_suspend_hw(dev);
9489 }
9490
9491 void intel_modeset_init(struct drm_device *dev)
9492 {
9493         struct drm_i915_private *dev_priv = dev->dev_private;
9494         int i, j, ret;
9495
9496         drm_mode_config_init(dev);
9497
9498         dev->mode_config.min_width = 0;
9499         dev->mode_config.min_height = 0;
9500
9501         dev->mode_config.preferred_depth = 24;
9502         dev->mode_config.prefer_shadow = 1;
9503
9504         dev->mode_config.funcs = &intel_mode_funcs;
9505
9506         intel_init_quirks(dev);
9507
9508         intel_init_pm(dev);
9509
9510         if (INTEL_INFO(dev)->num_pipes == 0)
9511                 return;
9512
9513         intel_init_display(dev);
9514
9515         if (IS_GEN2(dev)) {
9516                 dev->mode_config.max_width = 2048;
9517                 dev->mode_config.max_height = 2048;
9518         } else if (IS_GEN3(dev)) {
9519                 dev->mode_config.max_width = 4096;
9520                 dev->mode_config.max_height = 4096;
9521         } else {
9522                 dev->mode_config.max_width = 8192;
9523                 dev->mode_config.max_height = 8192;
9524         }
9525         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
9526
9527         DRM_DEBUG_KMS("%d display pipe%s available.\n",
9528                       INTEL_INFO(dev)->num_pipes,
9529                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
9530
9531         for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
9532                 intel_crtc_init(dev, i);
9533                 for (j = 0; j < dev_priv->num_plane; j++) {
9534                         ret = intel_plane_init(dev, i, j);
9535                         if (ret)
9536                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9537                                               pipe_name(i), sprite_name(i, j), ret);
9538                 }
9539         }
9540
9541         intel_cpu_pll_init(dev);
9542         intel_shared_dpll_init(dev);
9543
9544         /* Just disable it once at startup */
9545         i915_disable_vga(dev);
9546         intel_setup_outputs(dev);
9547
9548         /* Just in case the BIOS is doing something questionable. */
9549         intel_disable_fbc(dev);
9550 }
9551
9552 static void
9553 intel_connector_break_all_links(struct intel_connector *connector)
9554 {
9555         connector->base.dpms = DRM_MODE_DPMS_OFF;
9556         connector->base.encoder = NULL;
9557         connector->encoder->connectors_active = false;
9558         connector->encoder->base.crtc = NULL;
9559 }
9560
9561 static void intel_enable_pipe_a(struct drm_device *dev)
9562 {
9563         struct intel_connector *connector;
9564         struct drm_connector *crt = NULL;
9565         struct intel_load_detect_pipe load_detect_temp;
9566
9567         /* We can't just switch on the pipe A, we need to set things up with a
9568          * proper mode and output configuration. As a gross hack, enable pipe A
9569          * by enabling the load detect pipe once. */
9570         list_for_each_entry(connector,
9571                             &dev->mode_config.connector_list,
9572                             base.head) {
9573                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9574                         crt = &connector->base;
9575                         break;
9576                 }
9577         }
9578
9579         if (!crt)
9580                 return;
9581
9582         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9583                 intel_release_load_detect_pipe(crt, &load_detect_temp);
9584
9585
9586 }
9587
9588 static bool
9589 intel_check_plane_mapping(struct intel_crtc *crtc)
9590 {
9591         struct drm_device *dev = crtc->base.dev;
9592         struct drm_i915_private *dev_priv = dev->dev_private;
9593         u32 reg, val;
9594
9595         if (INTEL_INFO(dev)->num_pipes == 1)
9596                 return true;
9597
9598         reg = DSPCNTR(!crtc->plane);
9599         val = I915_READ(reg);
9600
9601         if ((val & DISPLAY_PLANE_ENABLE) &&
9602             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9603                 return false;
9604
9605         return true;
9606 }
9607
9608 static void intel_sanitize_crtc(struct intel_crtc *crtc)
9609 {
9610         struct drm_device *dev = crtc->base.dev;
9611         struct drm_i915_private *dev_priv = dev->dev_private;
9612         u32 reg;
9613
9614         /* Clear any frame start delays used for debugging left by the BIOS */
9615         reg = PIPECONF(crtc->config.cpu_transcoder);
9616         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9617
9618         /* We need to sanitize the plane -> pipe mapping first because this will
9619          * disable the crtc (and hence change the state) if it is wrong. Note
9620          * that gen4+ has a fixed plane -> pipe mapping.  */
9621         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
9622                 struct intel_connector *connector;
9623                 bool plane;
9624
9625                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9626                               crtc->base.base.id);
9627
9628                 /* Pipe has the wrong plane attached and the plane is active.
9629                  * Temporarily change the plane mapping and disable everything
9630                  * ...  */
9631                 plane = crtc->plane;
9632                 crtc->plane = !plane;
9633                 dev_priv->display.crtc_disable(&crtc->base);
9634                 crtc->plane = plane;
9635
9636                 /* ... and break all links. */
9637                 list_for_each_entry(connector, &dev->mode_config.connector_list,
9638                                     base.head) {
9639                         if (connector->encoder->base.crtc != &crtc->base)
9640                                 continue;
9641
9642                         intel_connector_break_all_links(connector);
9643                 }
9644
9645                 WARN_ON(crtc->active);
9646                 crtc->base.enabled = false;
9647         }
9648
9649         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9650             crtc->pipe == PIPE_A && !crtc->active) {
9651                 /* BIOS forgot to enable pipe A, this mostly happens after
9652                  * resume. Force-enable the pipe to fix this, the update_dpms
9653                  * call below we restore the pipe to the right state, but leave
9654                  * the required bits on. */
9655                 intel_enable_pipe_a(dev);
9656         }
9657
9658         /* Adjust the state of the output pipe according to whether we
9659          * have active connectors/encoders. */
9660         intel_crtc_update_dpms(&crtc->base);
9661
9662         if (crtc->active != crtc->base.enabled) {
9663                 struct intel_encoder *encoder;
9664
9665                 /* This can happen either due to bugs in the get_hw_state
9666                  * functions or because the pipe is force-enabled due to the
9667                  * pipe A quirk. */
9668                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9669                               crtc->base.base.id,
9670                               crtc->base.enabled ? "enabled" : "disabled",
9671                               crtc->active ? "enabled" : "disabled");
9672
9673                 crtc->base.enabled = crtc->active;
9674
9675                 /* Because we only establish the connector -> encoder ->
9676                  * crtc links if something is active, this means the
9677                  * crtc is now deactivated. Break the links. connector
9678                  * -> encoder links are only establish when things are
9679                  *  actually up, hence no need to break them. */
9680                 WARN_ON(crtc->active);
9681
9682                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9683                         WARN_ON(encoder->connectors_active);
9684                         encoder->base.crtc = NULL;
9685                 }
9686         }
9687 }
9688
9689 static void intel_sanitize_encoder(struct intel_encoder *encoder)
9690 {
9691         struct intel_connector *connector;
9692         struct drm_device *dev = encoder->base.dev;
9693
9694         /* We need to check both for a crtc link (meaning that the
9695          * encoder is active and trying to read from a pipe) and the
9696          * pipe itself being active. */
9697         bool has_active_crtc = encoder->base.crtc &&
9698                 to_intel_crtc(encoder->base.crtc)->active;
9699
9700         if (encoder->connectors_active && !has_active_crtc) {
9701                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9702                               encoder->base.base.id,
9703                               drm_get_encoder_name(&encoder->base));
9704
9705                 /* Connector is active, but has no active pipe. This is
9706                  * fallout from our resume register restoring. Disable
9707                  * the encoder manually again. */
9708                 if (encoder->base.crtc) {
9709                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9710                                       encoder->base.base.id,
9711                                       drm_get_encoder_name(&encoder->base));
9712                         encoder->disable(encoder);
9713                 }
9714
9715                 /* Inconsistent output/port/pipe state happens presumably due to
9716                  * a bug in one of the get_hw_state functions. Or someplace else
9717                  * in our code, like the register restore mess on resume. Clamp
9718                  * things to off as a safer default. */
9719                 list_for_each_entry(connector,
9720                                     &dev->mode_config.connector_list,
9721                                     base.head) {
9722                         if (connector->encoder != encoder)
9723                                 continue;
9724
9725                         intel_connector_break_all_links(connector);
9726                 }
9727         }
9728         /* Enabled encoders without active connectors will be fixed in
9729          * the crtc fixup. */
9730 }
9731
9732 void i915_redisable_vga(struct drm_device *dev)
9733 {
9734         struct drm_i915_private *dev_priv = dev->dev_private;
9735         u32 vga_reg = i915_vgacntrl_reg(dev);
9736
9737         if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9738                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
9739                 i915_disable_vga(dev);
9740         }
9741 }
9742
9743 static void intel_modeset_readout_hw_state(struct drm_device *dev)
9744 {
9745         struct drm_i915_private *dev_priv = dev->dev_private;
9746         enum pipe pipe;
9747         struct intel_crtc *crtc;
9748         struct intel_encoder *encoder;
9749         struct intel_connector *connector;
9750         int i;
9751
9752         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9753                             base.head) {
9754                 memset(&crtc->config, 0, sizeof(crtc->config));
9755
9756                 crtc->active = dev_priv->display.get_pipe_config(crtc,
9757                                                                  &crtc->config);
9758
9759                 crtc->base.enabled = crtc->active;
9760
9761                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9762                               crtc->base.base.id,
9763                               crtc->active ? "enabled" : "disabled");
9764         }
9765
9766         /* FIXME: Smash this into the new shared dpll infrastructure. */
9767         if (HAS_DDI(dev))
9768                 intel_ddi_setup_hw_pll_state(dev);
9769
9770         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9771                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
9772
9773                 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
9774                 pll->active = 0;
9775                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9776                                     base.head) {
9777                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
9778                                 pll->active++;
9779                 }
9780                 pll->refcount = pll->active;
9781
9782                 DRM_DEBUG_KMS("%s hw state readout: refcount %i\n",
9783                               pll->name, pll->refcount);
9784         }
9785
9786         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9787                             base.head) {
9788                 pipe = 0;
9789
9790                 if (encoder->get_hw_state(encoder, &pipe)) {
9791                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9792                         encoder->base.crtc = &crtc->base;
9793                         if (encoder->get_config)
9794                                 encoder->get_config(encoder, &crtc->config);
9795                 } else {
9796                         encoder->base.crtc = NULL;
9797                 }
9798
9799                 encoder->connectors_active = false;
9800                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9801                               encoder->base.base.id,
9802                               drm_get_encoder_name(&encoder->base),
9803                               encoder->base.crtc ? "enabled" : "disabled",
9804                               pipe);
9805         }
9806
9807         list_for_each_entry(connector, &dev->mode_config.connector_list,
9808                             base.head) {
9809                 if (connector->get_hw_state(connector)) {
9810                         connector->base.dpms = DRM_MODE_DPMS_ON;
9811                         connector->encoder->connectors_active = true;
9812                         connector->base.encoder = &connector->encoder->base;
9813                 } else {
9814                         connector->base.dpms = DRM_MODE_DPMS_OFF;
9815                         connector->base.encoder = NULL;
9816                 }
9817                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9818                               connector->base.base.id,
9819                               drm_get_connector_name(&connector->base),
9820                               connector->base.encoder ? "enabled" : "disabled");
9821         }
9822 }
9823
9824 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9825  * and i915 state tracking structures. */
9826 void intel_modeset_setup_hw_state(struct drm_device *dev,
9827                                   bool force_restore)
9828 {
9829         struct drm_i915_private *dev_priv = dev->dev_private;
9830         enum pipe pipe;
9831         struct drm_plane *plane;
9832         struct intel_crtc *crtc;
9833         struct intel_encoder *encoder;
9834
9835         intel_modeset_readout_hw_state(dev);
9836
9837         /* HW state is read out, now we need to sanitize this mess. */
9838         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9839                             base.head) {
9840                 intel_sanitize_encoder(encoder);
9841         }
9842
9843         for_each_pipe(pipe) {
9844                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9845                 intel_sanitize_crtc(crtc);
9846                 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
9847         }
9848
9849         if (force_restore) {
9850                 /*
9851                  * We need to use raw interfaces for restoring state to avoid
9852                  * checking (bogus) intermediate states.
9853                  */
9854                 for_each_pipe(pipe) {
9855                         struct drm_crtc *crtc =
9856                                 dev_priv->pipe_to_crtc_mapping[pipe];
9857
9858                         __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
9859                                          crtc->fb);
9860                 }
9861                 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
9862                         intel_plane_restore(plane);
9863
9864                 i915_redisable_vga(dev);
9865         } else {
9866                 intel_modeset_update_staged_output_state(dev);
9867         }
9868
9869         intel_modeset_check_state(dev);
9870
9871         drm_mode_config_reset(dev);
9872 }
9873
9874 void intel_modeset_gem_init(struct drm_device *dev)
9875 {
9876         intel_modeset_init_hw(dev);
9877
9878         intel_setup_overlay(dev);
9879
9880         intel_modeset_setup_hw_state(dev, false);
9881 }
9882
9883 void intel_modeset_cleanup(struct drm_device *dev)
9884 {
9885         struct drm_i915_private *dev_priv = dev->dev_private;
9886         struct drm_crtc *crtc;
9887         struct intel_crtc *intel_crtc;
9888
9889         /*
9890          * Interrupts and polling as the first thing to avoid creating havoc.
9891          * Too much stuff here (turning of rps, connectors, ...) would
9892          * experience fancy races otherwise.
9893          */
9894         drm_irq_uninstall(dev);
9895         cancel_work_sync(&dev_priv->hotplug_work);
9896         /*
9897          * Due to the hpd irq storm handling the hotplug work can re-arm the
9898          * poll handlers. Hence disable polling after hpd handling is shut down.
9899          */
9900         drm_kms_helper_poll_fini(dev);
9901
9902         mutex_lock(&dev->struct_mutex);
9903
9904         intel_unregister_dsm_handler();
9905
9906         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9907                 /* Skip inactive CRTCs */
9908                 if (!crtc->fb)
9909                         continue;
9910
9911                 intel_crtc = to_intel_crtc(crtc);
9912                 intel_increase_pllclock(crtc);
9913         }
9914
9915         intel_disable_fbc(dev);
9916
9917         intel_disable_gt_powersave(dev);
9918
9919         ironlake_teardown_rc6(dev);
9920
9921         mutex_unlock(&dev->struct_mutex);
9922
9923         /* flush any delayed tasks or pending work */
9924         flush_scheduled_work();
9925
9926         /* destroy backlight, if any, before the connectors */
9927         intel_panel_destroy_backlight(dev);
9928
9929         drm_mode_config_cleanup(dev);
9930
9931         intel_cleanup_overlay(dev);
9932 }
9933
9934 /*
9935  * Return which encoder is currently attached for connector.
9936  */
9937 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9938 {
9939         return &intel_attached_encoder(connector)->base;
9940 }
9941
9942 void intel_connector_attach_encoder(struct intel_connector *connector,
9943                                     struct intel_encoder *encoder)
9944 {
9945         connector->encoder = encoder;
9946         drm_mode_connector_attach_encoder(&connector->base,
9947                                           &encoder->base);
9948 }
9949
9950 /*
9951  * set vga decode state - true == enable VGA decode
9952  */
9953 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9954 {
9955         struct drm_i915_private *dev_priv = dev->dev_private;
9956         u16 gmch_ctrl;
9957
9958         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9959         if (state)
9960                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9961         else
9962                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9963         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9964         return 0;
9965 }
9966
9967 #ifdef CONFIG_DEBUG_FS
9968 #include <linux/seq_file.h>
9969
9970 struct intel_display_error_state {
9971
9972         u32 power_well_driver;
9973
9974         struct intel_cursor_error_state {
9975                 u32 control;
9976                 u32 position;
9977                 u32 base;
9978                 u32 size;
9979         } cursor[I915_MAX_PIPES];
9980
9981         struct intel_pipe_error_state {
9982                 enum transcoder cpu_transcoder;
9983                 u32 conf;
9984                 u32 source;
9985
9986                 u32 htotal;
9987                 u32 hblank;
9988                 u32 hsync;
9989                 u32 vtotal;
9990                 u32 vblank;
9991                 u32 vsync;
9992         } pipe[I915_MAX_PIPES];
9993
9994         struct intel_plane_error_state {
9995                 u32 control;
9996                 u32 stride;
9997                 u32 size;
9998                 u32 pos;
9999                 u32 addr;
10000                 u32 surface;
10001                 u32 tile_offset;
10002         } plane[I915_MAX_PIPES];
10003 };
10004
10005 struct intel_display_error_state *
10006 intel_display_capture_error_state(struct drm_device *dev)
10007 {
10008         drm_i915_private_t *dev_priv = dev->dev_private;
10009         struct intel_display_error_state *error;
10010         enum transcoder cpu_transcoder;
10011         int i;
10012
10013         error = kmalloc(sizeof(*error), GFP_ATOMIC);
10014         if (error == NULL)
10015                 return NULL;
10016
10017         if (HAS_POWER_WELL(dev))
10018                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
10019
10020         for_each_pipe(i) {
10021                 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
10022                 error->pipe[i].cpu_transcoder = cpu_transcoder;
10023
10024                 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
10025                         error->cursor[i].control = I915_READ(CURCNTR(i));
10026                         error->cursor[i].position = I915_READ(CURPOS(i));
10027                         error->cursor[i].base = I915_READ(CURBASE(i));
10028                 } else {
10029                         error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
10030                         error->cursor[i].position = I915_READ(CURPOS_IVB(i));
10031                         error->cursor[i].base = I915_READ(CURBASE_IVB(i));
10032                 }
10033
10034                 error->plane[i].control = I915_READ(DSPCNTR(i));
10035                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
10036                 if (INTEL_INFO(dev)->gen <= 3) {
10037                         error->plane[i].size = I915_READ(DSPSIZE(i));
10038                         error->plane[i].pos = I915_READ(DSPPOS(i));
10039                 }
10040                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10041                         error->plane[i].addr = I915_READ(DSPADDR(i));
10042                 if (INTEL_INFO(dev)->gen >= 4) {
10043                         error->plane[i].surface = I915_READ(DSPSURF(i));
10044                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
10045                 }
10046
10047                 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
10048                 error->pipe[i].source = I915_READ(PIPESRC(i));
10049                 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
10050                 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
10051                 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
10052                 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
10053                 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
10054                 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
10055         }
10056
10057         /* In the code above we read the registers without checking if the power
10058          * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
10059          * prevent the next I915_WRITE from detecting it and printing an error
10060          * message. */
10061         if (HAS_POWER_WELL(dev))
10062                 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
10063
10064         return error;
10065 }
10066
10067 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
10068
10069 void
10070 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
10071                                 struct drm_device *dev,
10072                                 struct intel_display_error_state *error)
10073 {
10074         int i;
10075
10076         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
10077         if (HAS_POWER_WELL(dev))
10078                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
10079                            error->power_well_driver);
10080         for_each_pipe(i) {
10081                 err_printf(m, "Pipe [%d]:\n", i);
10082                 err_printf(m, "  CPU transcoder: %c\n",
10083                            transcoder_name(error->pipe[i].cpu_transcoder));
10084                 err_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
10085                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
10086                 err_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
10087                 err_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
10088                 err_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
10089                 err_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
10090                 err_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
10091                 err_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
10092
10093                 err_printf(m, "Plane [%d]:\n", i);
10094                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
10095                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
10096                 if (INTEL_INFO(dev)->gen <= 3) {
10097                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
10098                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
10099                 }
10100                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10101                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
10102                 if (INTEL_INFO(dev)->gen >= 4) {
10103                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
10104                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
10105                 }
10106
10107                 err_printf(m, "Cursor [%d]:\n", i);
10108                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
10109                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
10110                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
10111         }
10112 }
10113 #endif