drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  45 static void intel_increase_pllclock(struct drm_crtc *crtc);
  46 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  47
  48 typedef struct {
  49         int     min, max;
  50 } intel_range_t;
  51
  52 typedef struct {
  53         int     dot_limit;
  54         int     p2_slow, p2_fast;
  55 } intel_p2_t;
  56
  57 #define INTEL_P2_NUM                  2
  58 typedef struct intel_limit intel_limit_t;
  59 struct intel_limit {
  60         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  61         intel_p2_t          p2;
  62 };
  63
  64 /* FDI */
  65 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  66
  67 int
  68 intel_pch_rawclk(struct drm_device *dev)
  69 {
  70         struct drm_i915_private *dev_priv = dev->dev_private;
  71
  72         WARN_ON(!HAS_PCH_SPLIT(dev));
  73
  74         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  75 }
  76
  77 static inline u32 /* units of 100MHz */
  78 intel_fdi_link_freq(struct drm_device *dev)
  79 {
  80         if (IS_GEN5(dev)) {
  81                 struct drm_i915_private *dev_priv = dev->dev_private;
  82                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
  83         } else
  84                 return 27;
  85 }
  86
  87 static const intel_limit_t intel_limits_i8xx_dvo = {
  88         .dot = { .min = 25000, .max = 350000 },
  89         .vco = { .min = 930000, .max = 1400000 },
  90         .n = { .min = 3, .max = 16 },
  91         .m = { .min = 96, .max = 140 },
  92         .m1 = { .min = 18, .max = 26 },
  93         .m2 = { .min = 6, .max = 16 },
  94         .p = { .min = 4, .max = 128 },
  95         .p1 = { .min = 2, .max = 33 },
  96         .p2 = { .dot_limit = 165000,
  97                 .p2_slow = 4, .p2_fast = 2 },
  98 };
  99
 100 static const intel_limit_t intel_limits_i8xx_lvds = {
 101         .dot = { .min = 25000, .max = 350000 },
 102         .vco = { .min = 930000, .max = 1400000 },
 103         .n = { .min = 3, .max = 16 },
 104         .m = { .min = 96, .max = 140 },
 105         .m1 = { .min = 18, .max = 26 },
 106         .m2 = { .min = 6, .max = 16 },
 107         .p = { .min = 4, .max = 128 },
 108         .p1 = { .min = 1, .max = 6 },
 109         .p2 = { .dot_limit = 165000,
 110                 .p2_slow = 14, .p2_fast = 7 },
 111 };
 112
 113 static const intel_limit_t intel_limits_i9xx_sdvo = {
 114         .dot = { .min = 20000, .max = 400000 },
 115         .vco = { .min = 1400000, .max = 2800000 },
 116         .n = { .min = 1, .max = 6 },
 117         .m = { .min = 70, .max = 120 },
 118         .m1 = { .min = 8, .max = 18 },
 119         .m2 = { .min = 3, .max = 7 },
 120         .p = { .min = 5, .max = 80 },
 121         .p1 = { .min = 1, .max = 8 },
 122         .p2 = { .dot_limit = 200000,
 123                 .p2_slow = 10, .p2_fast = 5 },
 124 };
 125
 126 static const intel_limit_t intel_limits_i9xx_lvds = {
 127         .dot = { .min = 20000, .max = 400000 },
 128         .vco = { .min = 1400000, .max = 2800000 },
 129         .n = { .min = 1, .max = 6 },
 130         .m = { .min = 70, .max = 120 },
 131         .m1 = { .min = 8, .max = 18 },
 132         .m2 = { .min = 3, .max = 7 },
 133         .p = { .min = 7, .max = 98 },
 134         .p1 = { .min = 1, .max = 8 },
 135         .p2 = { .dot_limit = 112000,
 136                 .p2_slow = 14, .p2_fast = 7 },
 137 };
 138
 139
 140 static const intel_limit_t intel_limits_g4x_sdvo = {
 141         .dot = { .min = 25000, .max = 270000 },
 142         .vco = { .min = 1750000, .max = 3500000},
 143         .n = { .min = 1, .max = 4 },
 144         .m = { .min = 104, .max = 138 },
 145         .m1 = { .min = 17, .max = 23 },
 146         .m2 = { .min = 5, .max = 11 },
 147         .p = { .min = 10, .max = 30 },
 148         .p1 = { .min = 1, .max = 3},
 149         .p2 = { .dot_limit = 270000,
 150                 .p2_slow = 10,
 151                 .p2_fast = 10
 152         },
 153 };
 154
 155 static const intel_limit_t intel_limits_g4x_hdmi = {
 156         .dot = { .min = 22000, .max = 400000 },
 157         .vco = { .min = 1750000, .max = 3500000},
 158         .n = { .min = 1, .max = 4 },
 159         .m = { .min = 104, .max = 138 },
 160         .m1 = { .min = 16, .max = 23 },
 161         .m2 = { .min = 5, .max = 11 },
 162         .p = { .min = 5, .max = 80 },
 163         .p1 = { .min = 1, .max = 8},
 164         .p2 = { .dot_limit = 165000,
 165                 .p2_slow = 10, .p2_fast = 5 },
 166 };
 167
 168 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 169         .dot = { .min = 20000, .max = 115000 },
 170         .vco = { .min = 1750000, .max = 3500000 },
 171         .n = { .min = 1, .max = 3 },
 172         .m = { .min = 104, .max = 138 },
 173         .m1 = { .min = 17, .max = 23 },
 174         .m2 = { .min = 5, .max = 11 },
 175         .p = { .min = 28, .max = 112 },
 176         .p1 = { .min = 2, .max = 8 },
 177         .p2 = { .dot_limit = 0,
 178                 .p2_slow = 14, .p2_fast = 14
 179         },
 180 };
 181
 182 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 183         .dot = { .min = 80000, .max = 224000 },
 184         .vco = { .min = 1750000, .max = 3500000 },
 185         .n = { .min = 1, .max = 3 },
 186         .m = { .min = 104, .max = 138 },
 187         .m1 = { .min = 17, .max = 23 },
 188         .m2 = { .min = 5, .max = 11 },
 189         .p = { .min = 14, .max = 42 },
 190         .p1 = { .min = 2, .max = 6 },
 191         .p2 = { .dot_limit = 0,
 192                 .p2_slow = 7, .p2_fast = 7
 193         },
 194 };
 195
 196 static const intel_limit_t intel_limits_pineview_sdvo = {
 197         .dot = { .min = 20000, .max = 400000},
 198         .vco = { .min = 1700000, .max = 3500000 },
 199         /* Pineview's Ncounter is a ring counter */
 200         .n = { .min = 3, .max = 6 },
 201         .m = { .min = 2, .max = 256 },
 202         /* Pineview only has one combined m divider, which we treat as m2. */
 203         .m1 = { .min = 0, .max = 0 },
 204         .m2 = { .min = 0, .max = 254 },
 205         .p = { .min = 5, .max = 80 },
 206         .p1 = { .min = 1, .max = 8 },
 207         .p2 = { .dot_limit = 200000,
 208                 .p2_slow = 10, .p2_fast = 5 },
 209 };
 210
 211 static const intel_limit_t intel_limits_pineview_lvds = {
 212         .dot = { .min = 20000, .max = 400000 },
 213         .vco = { .min = 1700000, .max = 3500000 },
 214         .n = { .min = 3, .max = 6 },
 215         .m = { .min = 2, .max = 256 },
 216         .m1 = { .min = 0, .max = 0 },
 217         .m2 = { .min = 0, .max = 254 },
 218         .p = { .min = 7, .max = 112 },
 219         .p1 = { .min = 1, .max = 8 },
 220         .p2 = { .dot_limit = 112000,
 221                 .p2_slow = 14, .p2_fast = 14 },
 222 };
 223
 224 /* Ironlake / Sandybridge
 225  *
 226  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 227  * the range value for them is (actual_value - 2).
 228  */
 229 static const intel_limit_t intel_limits_ironlake_dac = {
 230         .dot = { .min = 25000, .max = 350000 },
 231         .vco = { .min = 1760000, .max = 3510000 },
 232         .n = { .min = 1, .max = 5 },
 233         .m = { .min = 79, .max = 127 },
 234         .m1 = { .min = 12, .max = 22 },
 235         .m2 = { .min = 5, .max = 9 },
 236         .p = { .min = 5, .max = 80 },
 237         .p1 = { .min = 1, .max = 8 },
 238         .p2 = { .dot_limit = 225000,
 239                 .p2_slow = 10, .p2_fast = 5 },
 240 };
 241
 242 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 243         .dot = { .min = 25000, .max = 350000 },
 244         .vco = { .min = 1760000, .max = 3510000 },
 245         .n = { .min = 1, .max = 3 },
 246         .m = { .min = 79, .max = 118 },
 247         .m1 = { .min = 12, .max = 22 },
 248         .m2 = { .min = 5, .max = 9 },
 249         .p = { .min = 28, .max = 112 },
 250         .p1 = { .min = 2, .max = 8 },
 251         .p2 = { .dot_limit = 225000,
 252                 .p2_slow = 14, .p2_fast = 14 },
 253 };
 254
 255 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 256         .dot = { .min = 25000, .max = 350000 },
 257         .vco = { .min = 1760000, .max = 3510000 },
 258         .n = { .min = 1, .max = 3 },
 259         .m = { .min = 79, .max = 127 },
 260         .m1 = { .min = 12, .max = 22 },
 261         .m2 = { .min = 5, .max = 9 },
 262         .p = { .min = 14, .max = 56 },
 263         .p1 = { .min = 2, .max = 8 },
 264         .p2 = { .dot_limit = 225000,
 265                 .p2_slow = 7, .p2_fast = 7 },
 266 };
 267
 268 /* LVDS 100mhz refclk limits. */
 269 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 270         .dot = { .min = 25000, .max = 350000 },
 271         .vco = { .min = 1760000, .max = 3510000 },
 272         .n = { .min = 1, .max = 2 },
 273         .m = { .min = 79, .max = 126 },
 274         .m1 = { .min = 12, .max = 22 },
 275         .m2 = { .min = 5, .max = 9 },
 276         .p = { .min = 28, .max = 112 },
 277         .p1 = { .min = 2, .max = 8 },
 278         .p2 = { .dot_limit = 225000,
 279                 .p2_slow = 14, .p2_fast = 14 },
 280 };
 281
 282 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 283         .dot = { .min = 25000, .max = 350000 },
 284         .vco = { .min = 1760000, .max = 3510000 },
 285         .n = { .min = 1, .max = 3 },
 286         .m = { .min = 79, .max = 126 },
 287         .m1 = { .min = 12, .max = 22 },
 288         .m2 = { .min = 5, .max = 9 },
 289         .p = { .min = 14, .max = 42 },
 290         .p1 = { .min = 2, .max = 6 },
 291         .p2 = { .dot_limit = 225000,
 292                 .p2_slow = 7, .p2_fast = 7 },
 293 };
 294
 295 static const intel_limit_t intel_limits_vlv_dac = {
 296         .dot = { .min = 25000, .max = 270000 },
 297         .vco = { .min = 4000000, .max = 6000000 },
 298         .n = { .min = 1, .max = 7 },
 299         .m = { .min = 22, .max = 450 }, /* guess */
 300         .m1 = { .min = 2, .max = 3 },
 301         .m2 = { .min = 11, .max = 156 },
 302         .p = { .min = 10, .max = 30 },
 303         .p1 = { .min = 1, .max = 3 },
 304         .p2 = { .dot_limit = 270000,
 305                 .p2_slow = 2, .p2_fast = 20 },
 306 };
 307
 308 static const intel_limit_t intel_limits_vlv_hdmi = {
 309         .dot = { .min = 25000, .max = 270000 },
 310         .vco = { .min = 4000000, .max = 6000000 },
 311         .n = { .min = 1, .max = 7 },
 312         .m = { .min = 60, .max = 300 }, /* guess */
 313         .m1 = { .min = 2, .max = 3 },
 314         .m2 = { .min = 11, .max = 156 },
 315         .p = { .min = 10, .max = 30 },
 316         .p1 = { .min = 2, .max = 3 },
 317         .p2 = { .dot_limit = 270000,
 318                 .p2_slow = 2, .p2_fast = 20 },
 319 };
 320
 321 static const intel_limit_t intel_limits_vlv_dp = {
 322         .dot = { .min = 25000, .max = 270000 },
 323         .vco = { .min = 4000000, .max = 6000000 },
 324         .n = { .min = 1, .max = 7 },
 325         .m = { .min = 22, .max = 450 },
 326         .m1 = { .min = 2, .max = 3 },
 327         .m2 = { .min = 11, .max = 156 },
 328         .p = { .min = 10, .max = 30 },
 329         .p1 = { .min = 1, .max = 3 },
 330         .p2 = { .dot_limit = 270000,
 331                 .p2_slow = 2, .p2_fast = 20 },
 332 };
 333
 334 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 335                                                 int refclk)
 336 {
 337         struct drm_device *dev = crtc->dev;
 338         const intel_limit_t *limit;
 339
 340         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 341                 if (intel_is_dual_link_lvds(dev)) {
 342                         if (refclk == 100000)
 343                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 344                         else
 345                                 limit = &intel_limits_ironlake_dual_lvds;
 346                 } else {
 347                         if (refclk == 100000)
 348                                 limit = &intel_limits_ironlake_single_lvds_100m;
 349                         else
 350                                 limit = &intel_limits_ironlake_single_lvds;
 351                 }
 352         } else
 353                 limit = &intel_limits_ironlake_dac;
 354
 355         return limit;
 356 }
 357
 358 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 359 {
 360         struct drm_device *dev = crtc->dev;
 361         const intel_limit_t *limit;
 362
 363         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 364                 if (intel_is_dual_link_lvds(dev))
 365                         limit = &intel_limits_g4x_dual_channel_lvds;
 366                 else
 367                         limit = &intel_limits_g4x_single_channel_lvds;
 368         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 369                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 370                 limit = &intel_limits_g4x_hdmi;
 371         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 372                 limit = &intel_limits_g4x_sdvo;
 373         } else /* The option is for other outputs */
 374                 limit = &intel_limits_i9xx_sdvo;
 375
 376         return limit;
 377 }
 378
 379 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 380 {
 381         struct drm_device *dev = crtc->dev;
 382         const intel_limit_t *limit;
 383
 384         if (HAS_PCH_SPLIT(dev))
 385                 limit = intel_ironlake_limit(crtc, refclk);
 386         else if (IS_G4X(dev)) {
 387                 limit = intel_g4x_limit(crtc);
 388         } else if (IS_PINEVIEW(dev)) {
 389                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 390                         limit = &intel_limits_pineview_lvds;
 391                 else
 392                         limit = &intel_limits_pineview_sdvo;
 393         } else if (IS_VALLEYVIEW(dev)) {
 394                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
 395                         limit = &intel_limits_vlv_dac;
 396                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
 397                         limit = &intel_limits_vlv_hdmi;
 398                 else
 399                         limit = &intel_limits_vlv_dp;
 400         } else if (!IS_GEN2(dev)) {
 401                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 402                         limit = &intel_limits_i9xx_lvds;
 403                 else
 404                         limit = &intel_limits_i9xx_sdvo;
 405         } else {
 406                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 407                         limit = &intel_limits_i8xx_lvds;
 408                 else
 409                         limit = &intel_limits_i8xx_dvo;
 410         }
 411         return limit;
 412 }
 413
 414 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 415 static void pineview_clock(int refclk, intel_clock_t *clock)
 416 {
 417         clock->m = clock->m2 + 2;
 418         clock->p = clock->p1 * clock->p2;
 419         clock->vco = refclk * clock->m / clock->n;
 420         clock->dot = clock->vco / clock->p;
 421 }
 422
 423 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 424 {
 425         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 426 }
 427
 428 static void i9xx_clock(int refclk, intel_clock_t *clock)
 429 {
 430         clock->m = i9xx_dpll_compute_m(clock);
 431         clock->p = clock->p1 * clock->p2;
 432         clock->vco = refclk * clock->m / (clock->n + 2);
 433         clock->dot = clock->vco / clock->p;
 434 }
 435
 436 /**
 437  * Returns whether any output on the specified pipe is of the specified type
 438  */
 439 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 440 {
 441         struct drm_device *dev = crtc->dev;
 442         struct intel_encoder *encoder;
 443
 444         for_each_encoder_on_crtc(dev, crtc, encoder)
 445                 if (encoder->type == type)
 446                         return true;
 447
 448         return false;
 449 }
 450
 451 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 452 /**
 453  * Returns whether the given set of divisors are valid for a given refclk with
 454  * the given connectors.
 455  */
 456
 457 static bool intel_PLL_is_valid(struct drm_device *dev,
 458                                const intel_limit_t *limit,
 459                                const intel_clock_t *clock)
 460 {
 461         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 462                 INTELPllInvalid("p1 out of range\n");
 463         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 464                 INTELPllInvalid("p out of range\n");
 465         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 466                 INTELPllInvalid("m2 out of range\n");
 467         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 468                 INTELPllInvalid("m1 out of range\n");
 469         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 470                 INTELPllInvalid("m1 <= m2\n");
 471         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 472                 INTELPllInvalid("m out of range\n");
 473         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 474                 INTELPllInvalid("n out of range\n");
 475         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 476                 INTELPllInvalid("vco out of range\n");
 477         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 478          * connector, etc., rather than just a single range.
 479          */
 480         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 481                 INTELPllInvalid("dot out of range\n");
 482
 483         return true;
 484 }
 485
 486 static bool
 487 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 488                     int target, int refclk, intel_clock_t *match_clock,
 489                     intel_clock_t *best_clock)
 490 {
 491         struct drm_device *dev = crtc->dev;
 492         intel_clock_t clock;
 493         int err = target;
 494
 495         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 496                 /*
 497                  * For LVDS just rely on its current settings for dual-channel.
 498                  * We haven't figured out how to reliably set up different
 499                  * single/dual channel state, if we even can.
 500                  */
 501                 if (intel_is_dual_link_lvds(dev))
 502                         clock.p2 = limit->p2.p2_fast;
 503                 else
 504                         clock.p2 = limit->p2.p2_slow;
 505         } else {
 506                 if (target < limit->p2.dot_limit)
 507                         clock.p2 = limit->p2.p2_slow;
 508                 else
 509                         clock.p2 = limit->p2.p2_fast;
 510         }
 511
 512         memset(best_clock, 0, sizeof(*best_clock));
 513
 514         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 515              clock.m1++) {
 516                 for (clock.m2 = limit->m2.min;
 517                      clock.m2 <= limit->m2.max; clock.m2++) {
 518                         if (clock.m2 >= clock.m1)
 519                                 break;
 520                         for (clock.n = limit->n.min;
 521                              clock.n <= limit->n.max; clock.n++) {
 522                                 for (clock.p1 = limit->p1.min;
 523                                         clock.p1 <= limit->p1.max; clock.p1++) {
 524                                         int this_err;
 525
 526                                         i9xx_clock(refclk, &clock);
 527                                         if (!intel_PLL_is_valid(dev, limit,
 528                                                                 &clock))
 529                                                 continue;
 530                                         if (match_clock &&
 531                                             clock.p != match_clock->p)
 532                                                 continue;
 533
 534                                         this_err = abs(clock.dot - target);
 535                                         if (this_err < err) {
 536                                                 *best_clock = clock;
 537                                                 err = this_err;
 538                                         }
 539                                 }
 540                         }
 541                 }
 542         }
 543
 544         return (err != target);
 545 }
 546
 547 static bool
 548 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 549                    int target, int refclk, intel_clock_t *match_clock,
 550                    intel_clock_t *best_clock)
 551 {
 552         struct drm_device *dev = crtc->dev;
 553         intel_clock_t clock;
 554         int err = target;
 555
 556         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 557                 /*
 558                  * For LVDS just rely on its current settings for dual-channel.
 559                  * We haven't figured out how to reliably set up different
 560                  * single/dual channel state, if we even can.
 561                  */
 562                 if (intel_is_dual_link_lvds(dev))
 563                         clock.p2 = limit->p2.p2_fast;
 564                 else
 565                         clock.p2 = limit->p2.p2_slow;
 566         } else {
 567                 if (target < limit->p2.dot_limit)
 568                         clock.p2 = limit->p2.p2_slow;
 569                 else
 570                         clock.p2 = limit->p2.p2_fast;
 571         }
 572
 573         memset(best_clock, 0, sizeof(*best_clock));
 574
 575         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 576              clock.m1++) {
 577                 for (clock.m2 = limit->m2.min;
 578                      clock.m2 <= limit->m2.max; clock.m2++) {
 579                         for (clock.n = limit->n.min;
 580                              clock.n <= limit->n.max; clock.n++) {
 581                                 for (clock.p1 = limit->p1.min;
 582                                         clock.p1 <= limit->p1.max; clock.p1++) {
 583                                         int this_err;
 584
 585                                         pineview_clock(refclk, &clock);
 586                                         if (!intel_PLL_is_valid(dev, limit,
 587                                                                 &clock))
 588                                                 continue;
 589                                         if (match_clock &&
 590                                             clock.p != match_clock->p)
 591                                                 continue;
 592
 593                                         this_err = abs(clock.dot - target);
 594                                         if (this_err < err) {
 595                                                 *best_clock = clock;
 596                                                 err = this_err;
 597                                         }
 598                                 }
 599                         }
 600                 }
 601         }
 602
 603         return (err != target);
 604 }
 605
 606 static bool
 607 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 608                    int target, int refclk, intel_clock_t *match_clock,
 609                    intel_clock_t *best_clock)
 610 {
 611         struct drm_device *dev = crtc->dev;
 612         intel_clock_t clock;
 613         int max_n;
 614         bool found;
 615         /* approximately equals target * 0.00585 */
 616         int err_most = (target >> 8) + (target >> 9);
 617         found = false;
 618
 619         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 620                 if (intel_is_dual_link_lvds(dev))
 621                         clock.p2 = limit->p2.p2_fast;
 622                 else
 623                         clock.p2 = limit->p2.p2_slow;
 624         } else {
 625                 if (target < limit->p2.dot_limit)
 626                         clock.p2 = limit->p2.p2_slow;
 627                 else
 628                         clock.p2 = limit->p2.p2_fast;
 629         }
 630
 631         memset(best_clock, 0, sizeof(*best_clock));
 632         max_n = limit->n.max;
 633         /* based on hardware requirement, prefer smaller n to precision */
 634         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 635                 /* based on hardware requirement, prefere larger m1,m2 */
 636                 for (clock.m1 = limit->m1.max;
 637                      clock.m1 >= limit->m1.min; clock.m1--) {
 638                         for (clock.m2 = limit->m2.max;
 639                              clock.m2 >= limit->m2.min; clock.m2--) {
 640                                 for (clock.p1 = limit->p1.max;
 641                                      clock.p1 >= limit->p1.min; clock.p1--) {
 642                                         int this_err;
 643
 644                                         i9xx_clock(refclk, &clock);
 645                                         if (!intel_PLL_is_valid(dev, limit,
 646                                                                 &clock))
 647                                                 continue;
 648
 649                                         this_err = abs(clock.dot - target);
 650                                         if (this_err < err_most) {
 651                                                 *best_clock = clock;
 652                                                 err_most = this_err;
 653                                                 max_n = clock.n;
 654                                                 found = true;
 655                                         }
 656                                 }
 657                         }
 658                 }
 659         }
 660         return found;
 661 }
 662
 663 static bool
 664 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 665                    int target, int refclk, intel_clock_t *match_clock,
 666                    intel_clock_t *best_clock)
 667 {
 668         u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
 669         u32 m, n, fastclk;
 670         u32 updrate, minupdate, fracbits, p;
 671         unsigned long bestppm, ppm, absppm;
 672         int dotclk, flag;
 673
 674         flag = 0;
 675         dotclk = target * 1000;
 676         bestppm = 1000000;
 677         ppm = absppm = 0;
 678         fastclk = dotclk / (2*100);
 679         updrate = 0;
 680         minupdate = 19200;
 681         fracbits = 1;
 682         n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
 683         bestm1 = bestm2 = bestp1 = bestp2 = 0;
 684
 685         /* based on hardware requirement, prefer smaller n to precision */
 686         for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
 687                 updrate = refclk / n;
 688                 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
 689                         for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
 690                                 if (p2 > 10)
 691                                         p2 = p2 - 1;
 692                                 p = p1 * p2;
 693                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 694                                 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
 695                                         m2 = (((2*(fastclk * p * n / m1 )) +
 696                                                refclk) / (2*refclk));
 697                                         m = m1 * m2;
 698                                         vco = updrate * m;
 699                                         if (vco >= limit->vco.min && vco < limit->vco.max) {
 700                                                 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
 701                                                 absppm = (ppm > 0) ? ppm : (-ppm);
 702                                                 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
 703                                                         bestppm = 0;
 704                                                         flag = 1;
 705                                                 }
 706                                                 if (absppm < bestppm - 10) {
 707                                                         bestppm = absppm;
 708                                                         flag = 1;
 709                                                 }
 710                                                 if (flag) {
 711                                                         bestn = n;
 712                                                         bestm1 = m1;
 713                                                         bestm2 = m2;
 714                                                         bestp1 = p1;
 715                                                         bestp2 = p2;
 716                                                         flag = 0;
 717                                                 }
 718                                         }
 719                                 }
 720                         }
 721                 }
 722         }
 723         best_clock->n = bestn;
 724         best_clock->m1 = bestm1;
 725         best_clock->m2 = bestm2;
 726         best_clock->p1 = bestp1;
 727         best_clock->p2 = bestp2;
 728
 729         return true;
 730 }
 731
 732 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 733                                              enum pipe pipe)
 734 {
 735         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 736         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 737
 738         return intel_crtc->config.cpu_transcoder;
 739 }
 740
 741 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 742 {
 743         struct drm_i915_private *dev_priv = dev->dev_private;
 744         u32 frame, frame_reg = PIPEFRAME(pipe);
 745
 746         frame = I915_READ(frame_reg);
 747
 748         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 749                 DRM_DEBUG_KMS("vblank wait timed out\n");
 750 }
 751
 752 /**
 753  * intel_wait_for_vblank - wait for vblank on a given pipe
 754  * @dev: drm device
 755  * @pipe: pipe to wait for
 756  *
 757  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 758  * mode setting code.
 759  */
 760 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 761 {
 762         struct drm_i915_private *dev_priv = dev->dev_private;
 763         int pipestat_reg = PIPESTAT(pipe);
 764
 765         if (INTEL_INFO(dev)->gen >= 5) {
 766                 ironlake_wait_for_vblank(dev, pipe);
 767                 return;
 768         }
 769
 770         /* Clear existing vblank status. Note this will clear any other
 771          * sticky status fields as well.
 772          *
 773          * This races with i915_driver_irq_handler() with the result
 774          * that either function could miss a vblank event.  Here it is not
 775          * fatal, as we will either wait upon the next vblank interrupt or
 776          * timeout.  Generally speaking intel_wait_for_vblank() is only
 777          * called during modeset at which time the GPU should be idle and
 778          * should *not* be performing page flips and thus not waiting on
 779          * vblanks...
 780          * Currently, the result of us stealing a vblank from the irq
 781          * handler is that a single frame will be skipped during swapbuffers.
 782          */
 783         I915_WRITE(pipestat_reg,
 784                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 785
 786         /* Wait for vblank interrupt bit to set */
 787         if (wait_for(I915_READ(pipestat_reg) &
 788                      PIPE_VBLANK_INTERRUPT_STATUS,
 789                      50))
 790                 DRM_DEBUG_KMS("vblank wait timed out\n");
 791 }
 792
 793 /*
 794  * intel_wait_for_pipe_off - wait for pipe to turn off
 795  * @dev: drm device
 796  * @pipe: pipe to wait for
 797  *
 798  * After disabling a pipe, we can't wait for vblank in the usual way,
 799  * spinning on the vblank interrupt status bit, since we won't actually
 800  * see an interrupt when the pipe is disabled.
 801  *
 802  * On Gen4 and above:
 803  *   wait for the pipe register state bit to turn off
 804  *
 805  * Otherwise:
 806  *   wait for the display line value to settle (it usually
 807  *   ends up stopping at the start of the next frame).
 808  *
 809  */
 810 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 811 {
 812         struct drm_i915_private *dev_priv = dev->dev_private;
 813         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 814                                                                       pipe);
 815
 816         if (INTEL_INFO(dev)->gen >= 4) {
 817                 int reg = PIPECONF(cpu_transcoder);
 818
 819                 /* Wait for the Pipe State to go off */
 820                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 821                              100))
 822                         WARN(1, "pipe_off wait timed out\n");
 823         } else {
 824                 u32 last_line, line_mask;
 825                 int reg = PIPEDSL(pipe);
 826                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
 827
 828                 if (IS_GEN2(dev))
 829                         line_mask = DSL_LINEMASK_GEN2;
 830                 else
 831                         line_mask = DSL_LINEMASK_GEN3;
 832
 833                 /* Wait for the display line to settle */
 834                 do {
 835                         last_line = I915_READ(reg) & line_mask;
 836                         mdelay(5);
 837                 } while (((I915_READ(reg) & line_mask) != last_line) &&
 838                          time_after(timeout, jiffies));
 839                 if (time_after(jiffies, timeout))
 840                         WARN(1, "pipe_off wait timed out\n");
 841         }
 842 }
 843
 844 /*
 845  * ibx_digital_port_connected - is the specified port connected?
 846  * @dev_priv: i915 private structure
 847  * @port: the port to test
 848  *
 849  * Returns true if @port is connected, false otherwise.
 850  */
 851 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 852                                 struct intel_digital_port *port)
 853 {
 854         u32 bit;
 855
 856         if (HAS_PCH_IBX(dev_priv->dev)) {
 857                 switch(port->port) {
 858                 case PORT_B:
 859                         bit = SDE_PORTB_HOTPLUG;
 860                         break;
 861                 case PORT_C:
 862                         bit = SDE_PORTC_HOTPLUG;
 863                         break;
 864                 case PORT_D:
 865                         bit = SDE_PORTD_HOTPLUG;
 866                         break;
 867                 default:
 868                         return true;
 869                 }
 870         } else {
 871                 switch(port->port) {
 872                 case PORT_B:
 873                         bit = SDE_PORTB_HOTPLUG_CPT;
 874                         break;
 875                 case PORT_C:
 876                         bit = SDE_PORTC_HOTPLUG_CPT;
 877                         break;
 878                 case PORT_D:
 879                         bit = SDE_PORTD_HOTPLUG_CPT;
 880                         break;
 881                 default:
 882                         return true;
 883                 }
 884         }
 885
 886         return I915_READ(SDEISR) & bit;
 887 }
 888
 889 static const char *state_string(bool enabled)
 890 {
 891         return enabled ? "on" : "off";
 892 }
 893
 894 /* Only for pre-ILK configs */
 895 static void assert_pll(struct drm_i915_private *dev_priv,
 896                        enum pipe pipe, bool state)
 897 {
 898         int reg;
 899         u32 val;
 900         bool cur_state;
 901
 902         reg = DPLL(pipe);
 903         val = I915_READ(reg);
 904         cur_state = !!(val & DPLL_VCO_ENABLE);
 905         WARN(cur_state != state,
 906              "PLL state assertion failure (expected %s, current %s)\n",
 907              state_string(state), state_string(cur_state));
 908 }
 909 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
 910 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
 911
 912 static struct intel_shared_dpll *
 913 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
 914 {
 915         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 916
 917         if (crtc->config.shared_dpll < 0)
 918                 return NULL;
 919
 920         return &dev_priv->shared_dplls[crtc->config.shared_dpll];
 921 }
 922
 923 /* For ILK+ */
 924 static void assert_shared_dpll(struct drm_i915_private *dev_priv,
 925                                struct intel_shared_dpll *pll,
 926                                bool state)
 927 {
 928         bool cur_state;
 929         struct intel_dpll_hw_state hw_state;
 930
 931         if (HAS_PCH_LPT(dev_priv->dev)) {
 932                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
 933                 return;
 934         }
 935
 936         if (WARN (!pll,
 937                   "asserting DPLL %s with no DPLL\n", state_string(state)))
 938                 return;
 939
 940         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
 941         WARN(cur_state != state,
 942              "%s assertion failure (expected %s, current %s)\n",
 943              pll->name, state_string(state), state_string(cur_state));
 944 }
 945 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
 946 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
 947
 948 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 949                           enum pipe pipe, bool state)
 950 {
 951         int reg;
 952         u32 val;
 953         bool cur_state;
 954         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 955                                                                       pipe);
 956
 957         if (HAS_DDI(dev_priv->dev)) {
 958                 /* DDI does not have a specific FDI_TX register */
 959                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
 960                 val = I915_READ(reg);
 961                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
 962         } else {
 963                 reg = FDI_TX_CTL(pipe);
 964                 val = I915_READ(reg);
 965                 cur_state = !!(val & FDI_TX_ENABLE);
 966         }
 967         WARN(cur_state != state,
 968              "FDI TX state assertion failure (expected %s, current %s)\n",
 969              state_string(state), state_string(cur_state));
 970 }
 971 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
 972 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
 973
 974 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
 975                           enum pipe pipe, bool state)
 976 {
 977         int reg;
 978         u32 val;
 979         bool cur_state;
 980
 981         reg = FDI_RX_CTL(pipe);
 982         val = I915_READ(reg);
 983         cur_state = !!(val & FDI_RX_ENABLE);
 984         WARN(cur_state != state,
 985              "FDI RX state assertion failure (expected %s, current %s)\n",
 986              state_string(state), state_string(cur_state));
 987 }
 988 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
 989 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
 990
 991 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
 992                                       enum pipe pipe)
 993 {
 994         int reg;
 995         u32 val;
 996
 997         /* ILK FDI PLL is always enabled */
 998         if (dev_priv->info->gen == 5)
 999                 return;
1000
1001         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1002         if (HAS_DDI(dev_priv->dev))
1003                 return;
1004
1005         reg = FDI_TX_CTL(pipe);
1006         val = I915_READ(reg);
1007         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1008 }
1009
1010 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1011                                       enum pipe pipe)
1012 {
1013         int reg;
1014         u32 val;
1015
1016         reg = FDI_RX_CTL(pipe);
1017         val = I915_READ(reg);
1018         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1019 }
1020
1021 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1022                                   enum pipe pipe)
1023 {
1024         int pp_reg, lvds_reg;
1025         u32 val;
1026         enum pipe panel_pipe = PIPE_A;
1027         bool locked = true;
1028
1029         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1030                 pp_reg = PCH_PP_CONTROL;
1031                 lvds_reg = PCH_LVDS;
1032         } else {
1033                 pp_reg = PP_CONTROL;
1034                 lvds_reg = LVDS;
1035         }
1036
1037         val = I915_READ(pp_reg);
1038         if (!(val & PANEL_POWER_ON) ||
1039             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1040                 locked = false;
1041
1042         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1043                 panel_pipe = PIPE_B;
1044
1045         WARN(panel_pipe == pipe && locked,
1046              "panel assertion failure, pipe %c regs locked\n",
1047              pipe_name(pipe));
1048 }
1049
1050 void assert_pipe(struct drm_i915_private *dev_priv,
1051                  enum pipe pipe, bool state)
1052 {
1053         int reg;
1054         u32 val;
1055         bool cur_state;
1056         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1057                                                                       pipe);
1058
1059         /* if we need the pipe A quirk it must be always on */
1060         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1061                 state = true;
1062
1063         if (!intel_display_power_enabled(dev_priv->dev,
1064                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1065                 cur_state = false;
1066         } else {
1067                 reg = PIPECONF(cpu_transcoder);
1068                 val = I915_READ(reg);
1069                 cur_state = !!(val & PIPECONF_ENABLE);
1070         }
1071
1072         WARN(cur_state != state,
1073              "pipe %c assertion failure (expected %s, current %s)\n",
1074              pipe_name(pipe), state_string(state), state_string(cur_state));
1075 }
1076
1077 static void assert_plane(struct drm_i915_private *dev_priv,
1078                          enum plane plane, bool state)
1079 {
1080         int reg;
1081         u32 val;
1082         bool cur_state;
1083
1084         reg = DSPCNTR(plane);
1085         val = I915_READ(reg);
1086         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1087         WARN(cur_state != state,
1088              "plane %c assertion failure (expected %s, current %s)\n",
1089              plane_name(plane), state_string(state), state_string(cur_state));
1090 }
1091
1092 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1093 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1094
1095 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1096                                    enum pipe pipe)
1097 {
1098         struct drm_device *dev = dev_priv->dev;
1099         int reg, i;
1100         u32 val;
1101         int cur_pipe;
1102
1103         /* Primary planes are fixed to pipes on gen4+ */
1104         if (INTEL_INFO(dev)->gen >= 4) {
1105                 reg = DSPCNTR(pipe);
1106                 val = I915_READ(reg);
1107                 WARN((val & DISPLAY_PLANE_ENABLE),
1108                      "plane %c assertion failure, should be disabled but not\n",
1109                      plane_name(pipe));
1110                 return;
1111         }
1112
1113         /* Need to check both planes against the pipe */
1114         for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
1115                 reg = DSPCNTR(i);
1116                 val = I915_READ(reg);
1117                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1118                         DISPPLANE_SEL_PIPE_SHIFT;
1119                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1120                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1121                      plane_name(i), pipe_name(pipe));
1122         }
1123 }
1124
1125 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1126                                     enum pipe pipe)
1127 {
1128         struct drm_device *dev = dev_priv->dev;
1129         int reg, i;
1130         u32 val;
1131
1132         if (IS_VALLEYVIEW(dev)) {
1133                 for (i = 0; i < dev_priv->num_plane; i++) {
1134                         reg = SPCNTR(pipe, i);
1135                         val = I915_READ(reg);
1136                         WARN((val & SP_ENABLE),
1137                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1138                              sprite_name(pipe, i), pipe_name(pipe));
1139                 }
1140         } else if (INTEL_INFO(dev)->gen >= 7) {
1141                 reg = SPRCTL(pipe);
1142                 val = I915_READ(reg);
1143                 WARN((val & SPRITE_ENABLE),
1144                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1145                      plane_name(pipe), pipe_name(pipe));
1146         } else if (INTEL_INFO(dev)->gen >= 5) {
1147                 reg = DVSCNTR(pipe);
1148                 val = I915_READ(reg);
1149                 WARN((val & DVS_ENABLE),
1150                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1151                      plane_name(pipe), pipe_name(pipe));
1152         }
1153 }
1154
1155 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1156 {
1157         u32 val;
1158         bool enabled;
1159
1160         if (HAS_PCH_LPT(dev_priv->dev)) {
1161                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1162                 return;
1163         }
1164
1165         val = I915_READ(PCH_DREF_CONTROL);
1166         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1167                             DREF_SUPERSPREAD_SOURCE_MASK));
1168         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1169 }
1170
1171 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1172                                            enum pipe pipe)
1173 {
1174         int reg;
1175         u32 val;
1176         bool enabled;
1177
1178         reg = PCH_TRANSCONF(pipe);
1179         val = I915_READ(reg);
1180         enabled = !!(val & TRANS_ENABLE);
1181         WARN(enabled,
1182              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1183              pipe_name(pipe));
1184 }
1185
1186 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1187                             enum pipe pipe, u32 port_sel, u32 val)
1188 {
1189         if ((val & DP_PORT_EN) == 0)
1190                 return false;
1191
1192         if (HAS_PCH_CPT(dev_priv->dev)) {
1193                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1194                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1195                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1196                         return false;
1197         } else {
1198                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1199                         return false;
1200         }
1201         return true;
1202 }
1203
1204 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1205                               enum pipe pipe, u32 val)
1206 {
1207         if ((val & SDVO_ENABLE) == 0)
1208                 return false;
1209
1210         if (HAS_PCH_CPT(dev_priv->dev)) {
1211                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1212                         return false;
1213         } else {
1214                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1215                         return false;
1216         }
1217         return true;
1218 }
1219
1220 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1221                               enum pipe pipe, u32 val)
1222 {
1223         if ((val & LVDS_PORT_EN) == 0)
1224                 return false;
1225
1226         if (HAS_PCH_CPT(dev_priv->dev)) {
1227                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1228                         return false;
1229         } else {
1230                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1231                         return false;
1232         }
1233         return true;
1234 }
1235
1236 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1237                               enum pipe pipe, u32 val)
1238 {
1239         if ((val & ADPA_DAC_ENABLE) == 0)
1240                 return false;
1241         if (HAS_PCH_CPT(dev_priv->dev)) {
1242                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1243                         return false;
1244         } else {
1245                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1246                         return false;
1247         }
1248         return true;
1249 }
1250
1251 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1252                                    enum pipe pipe, int reg, u32 port_sel)
1253 {
1254         u32 val = I915_READ(reg);
1255         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1256              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1257              reg, pipe_name(pipe));
1258
1259         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1260              && (val & DP_PIPEB_SELECT),
1261              "IBX PCH dp port still using transcoder B\n");
1262 }
1263
1264 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1265                                      enum pipe pipe, int reg)
1266 {
1267         u32 val = I915_READ(reg);
1268         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1269              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1270              reg, pipe_name(pipe));
1271
1272         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1273              && (val & SDVO_PIPE_B_SELECT),
1274              "IBX PCH hdmi port still using transcoder B\n");
1275 }
1276
1277 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1278                                       enum pipe pipe)
1279 {
1280         int reg;
1281         u32 val;
1282
1283         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1284         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1285         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1286
1287         reg = PCH_ADPA;
1288         val = I915_READ(reg);
1289         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1290              "PCH VGA enabled on transcoder %c, should be disabled\n",
1291              pipe_name(pipe));
1292
1293         reg = PCH_LVDS;
1294         val = I915_READ(reg);
1295         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1296              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1297              pipe_name(pipe));
1298
1299         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1300         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1301         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1302 }
1303
1304 /**
1305  * intel_enable_pll - enable a PLL
1306  * @dev_priv: i915 private structure
1307  * @pipe: pipe PLL to enable
1308  *
1309  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1310  * make sure the PLL reg is writable first though, since the panel write
1311  * protect mechanism may be enabled.
1312  *
1313  * Note!  This is for pre-ILK only.
1314  *
1315  * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1316  */
1317 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1318 {
1319         int reg;
1320         u32 val;
1321
1322         assert_pipe_disabled(dev_priv, pipe);
1323
1324         /* No really, not for ILK+ */
1325         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1326
1327         /* PLL is protected by panel, make sure we can write it */
1328         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1329                 assert_panel_unlocked(dev_priv, pipe);
1330
1331         reg = DPLL(pipe);
1332         val = I915_READ(reg);
1333         val |= DPLL_VCO_ENABLE;
1334
1335         /* We do this three times for luck */
1336         I915_WRITE(reg, val);
1337         POSTING_READ(reg);
1338         udelay(150); /* wait for warmup */
1339         I915_WRITE(reg, val);
1340         POSTING_READ(reg);
1341         udelay(150); /* wait for warmup */
1342         I915_WRITE(reg, val);
1343         POSTING_READ(reg);
1344         udelay(150); /* wait for warmup */
1345 }
1346
1347 /**
1348  * intel_disable_pll - disable a PLL
1349  * @dev_priv: i915 private structure
1350  * @pipe: pipe PLL to disable
1351  *
1352  * Disable the PLL for @pipe, making sure the pipe is off first.
1353  *
1354  * Note!  This is for pre-ILK only.
1355  */
1356 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1357 {
1358         int reg;
1359         u32 val;
1360
1361         /* Don't disable pipe A or pipe A PLLs if needed */
1362         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1363                 return;
1364
1365         /* Make sure the pipe isn't still relying on us */
1366         assert_pipe_disabled(dev_priv, pipe);
1367
1368         reg = DPLL(pipe);
1369         val = I915_READ(reg);
1370         val &= ~DPLL_VCO_ENABLE;
1371         I915_WRITE(reg, val);
1372         POSTING_READ(reg);
1373 }
1374
1375 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1376 {
1377         u32 port_mask;
1378
1379         if (!port)
1380                 port_mask = DPLL_PORTB_READY_MASK;
1381         else
1382                 port_mask = DPLL_PORTC_READY_MASK;
1383
1384         if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1385                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1386                      'B' + port, I915_READ(DPLL(0)));
1387 }
1388
1389 /**
1390  * ironlake_enable_shared_dpll - enable PCH PLL
1391  * @dev_priv: i915 private structure
1392  * @pipe: pipe PLL to enable
1393  *
1394  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1395  * drives the transcoder clock.
1396  */
1397 static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
1398 {
1399         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1400         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1401
1402         /* PCH PLLs only available on ILK, SNB and IVB */
1403         BUG_ON(dev_priv->info->gen < 5);
1404         if (WARN_ON(pll == NULL))
1405                 return;
1406
1407         if (WARN_ON(pll->refcount == 0))
1408                 return;
1409
1410         DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1411                       pll->name, pll->active, pll->on,
1412                       crtc->base.base.id);
1413
1414         if (pll->active++) {
1415                 WARN_ON(!pll->on);
1416                 assert_shared_dpll_enabled(dev_priv, pll);
1417                 return;
1418         }
1419         WARN_ON(pll->on);
1420
1421         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1422         pll->enable(dev_priv, pll);
1423         pll->on = true;
1424 }
1425
1426 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1427 {
1428         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1429         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1430
1431         /* PCH only available on ILK+ */
1432         BUG_ON(dev_priv->info->gen < 5);
1433         if (WARN_ON(pll == NULL))
1434                return;
1435
1436         if (WARN_ON(pll->refcount == 0))
1437                 return;
1438
1439         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1440                       pll->name, pll->active, pll->on,
1441                       crtc->base.base.id);
1442
1443         if (WARN_ON(pll->active == 0)) {
1444                 assert_shared_dpll_disabled(dev_priv, pll);
1445                 return;
1446         }
1447
1448         assert_shared_dpll_enabled(dev_priv, pll);
1449         WARN_ON(!pll->on);
1450         if (--pll->active)
1451                 return;
1452
1453         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1454         pll->disable(dev_priv, pll);
1455         pll->on = false;
1456 }
1457
1458 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1459                                            enum pipe pipe)
1460 {
1461         struct drm_device *dev = dev_priv->dev;
1462         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1463         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1464         uint32_t reg, val, pipeconf_val;
1465
1466         /* PCH only available on ILK+ */
1467         BUG_ON(dev_priv->info->gen < 5);
1468
1469         /* Make sure PCH DPLL is enabled */
1470         assert_shared_dpll_enabled(dev_priv,
1471                                    intel_crtc_to_shared_dpll(intel_crtc));
1472
1473         /* FDI must be feeding us bits for PCH ports */
1474         assert_fdi_tx_enabled(dev_priv, pipe);
1475         assert_fdi_rx_enabled(dev_priv, pipe);
1476
1477         if (HAS_PCH_CPT(dev)) {
1478                 /* Workaround: Set the timing override bit before enabling the
1479                  * pch transcoder. */
1480                 reg = TRANS_CHICKEN2(pipe);
1481                 val = I915_READ(reg);
1482                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1483                 I915_WRITE(reg, val);
1484         }
1485
1486         reg = PCH_TRANSCONF(pipe);
1487         val = I915_READ(reg);
1488         pipeconf_val = I915_READ(PIPECONF(pipe));
1489
1490         if (HAS_PCH_IBX(dev_priv->dev)) {
1491                 /*
1492                  * make the BPC in transcoder be consistent with
1493                  * that in pipeconf reg.
1494                  */
1495                 val &= ~PIPECONF_BPC_MASK;
1496                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1497         }
1498
1499         val &= ~TRANS_INTERLACE_MASK;
1500         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1501                 if (HAS_PCH_IBX(dev_priv->dev) &&
1502                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1503                         val |= TRANS_LEGACY_INTERLACED_ILK;
1504                 else
1505                         val |= TRANS_INTERLACED;
1506         else
1507                 val |= TRANS_PROGRESSIVE;
1508
1509         I915_WRITE(reg, val | TRANS_ENABLE);
1510         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1511                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1512 }
1513
1514 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1515                                       enum transcoder cpu_transcoder)
1516 {
1517         u32 val, pipeconf_val;
1518
1519         /* PCH only available on ILK+ */
1520         BUG_ON(dev_priv->info->gen < 5);
1521
1522         /* FDI must be feeding us bits for PCH ports */
1523         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1524         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1525
1526         /* Workaround: set timing override bit. */
1527         val = I915_READ(_TRANSA_CHICKEN2);
1528         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1529         I915_WRITE(_TRANSA_CHICKEN2, val);
1530
1531         val = TRANS_ENABLE;
1532         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1533
1534         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1535             PIPECONF_INTERLACED_ILK)
1536                 val |= TRANS_INTERLACED;
1537         else
1538                 val |= TRANS_PROGRESSIVE;
1539
1540         I915_WRITE(LPT_TRANSCONF, val);
1541         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1542                 DRM_ERROR("Failed to enable PCH transcoder\n");
1543 }
1544
1545 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1546                                             enum pipe pipe)
1547 {
1548         struct drm_device *dev = dev_priv->dev;
1549         uint32_t reg, val;
1550
1551         /* FDI relies on the transcoder */
1552         assert_fdi_tx_disabled(dev_priv, pipe);
1553         assert_fdi_rx_disabled(dev_priv, pipe);
1554
1555         /* Ports must be off as well */
1556         assert_pch_ports_disabled(dev_priv, pipe);
1557
1558         reg = PCH_TRANSCONF(pipe);
1559         val = I915_READ(reg);
1560         val &= ~TRANS_ENABLE;
1561         I915_WRITE(reg, val);
1562         /* wait for PCH transcoder off, transcoder state */
1563         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1564                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1565
1566         if (!HAS_PCH_IBX(dev)) {
1567                 /* Workaround: Clear the timing override chicken bit again. */
1568                 reg = TRANS_CHICKEN2(pipe);
1569                 val = I915_READ(reg);
1570                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1571                 I915_WRITE(reg, val);
1572         }
1573 }
1574
1575 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1576 {
1577         u32 val;
1578
1579         val = I915_READ(LPT_TRANSCONF);
1580         val &= ~TRANS_ENABLE;
1581         I915_WRITE(LPT_TRANSCONF, val);
1582         /* wait for PCH transcoder off, transcoder state */
1583         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1584                 DRM_ERROR("Failed to disable PCH transcoder\n");
1585
1586         /* Workaround: clear timing override bit. */
1587         val = I915_READ(_TRANSA_CHICKEN2);
1588         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1589         I915_WRITE(_TRANSA_CHICKEN2, val);
1590 }
1591
1592 /**
1593  * intel_enable_pipe - enable a pipe, asserting requirements
1594  * @dev_priv: i915 private structure
1595  * @pipe: pipe to enable
1596  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1597  *
1598  * Enable @pipe, making sure that various hardware specific requirements
1599  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1600  *
1601  * @pipe should be %PIPE_A or %PIPE_B.
1602  *
1603  * Will wait until the pipe is actually running (i.e. first vblank) before
1604  * returning.
1605  */
1606 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1607                               bool pch_port)
1608 {
1609         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1610                                                                       pipe);
1611         enum pipe pch_transcoder;
1612         int reg;
1613         u32 val;
1614
1615         assert_planes_disabled(dev_priv, pipe);
1616         assert_sprites_disabled(dev_priv, pipe);
1617
1618         if (HAS_PCH_LPT(dev_priv->dev))
1619                 pch_transcoder = TRANSCODER_A;
1620         else
1621                 pch_transcoder = pipe;
1622
1623         /*
1624          * A pipe without a PLL won't actually be able to drive bits from
1625          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1626          * need the check.
1627          */
1628         if (!HAS_PCH_SPLIT(dev_priv->dev))
1629                 assert_pll_enabled(dev_priv, pipe);
1630         else {
1631                 if (pch_port) {
1632                         /* if driving the PCH, we need FDI enabled */
1633                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1634                         assert_fdi_tx_pll_enabled(dev_priv,
1635                                                   (enum pipe) cpu_transcoder);
1636                 }
1637                 /* FIXME: assert CPU port conditions for SNB+ */
1638         }
1639
1640         reg = PIPECONF(cpu_transcoder);
1641         val = I915_READ(reg);
1642         if (val & PIPECONF_ENABLE)
1643                 return;
1644
1645         I915_WRITE(reg, val | PIPECONF_ENABLE);
1646         intel_wait_for_vblank(dev_priv->dev, pipe);
1647 }
1648
1649 /**
1650  * intel_disable_pipe - disable a pipe, asserting requirements
1651  * @dev_priv: i915 private structure
1652  * @pipe: pipe to disable
1653  *
1654  * Disable @pipe, making sure that various hardware specific requirements
1655  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1656  *
1657  * @pipe should be %PIPE_A or %PIPE_B.
1658  *
1659  * Will wait until the pipe has shut down before returning.
1660  */
1661 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1662                                enum pipe pipe)
1663 {
1664         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1665                                                                       pipe);
1666         int reg;
1667         u32 val;
1668
1669         /*
1670          * Make sure planes won't keep trying to pump pixels to us,
1671          * or we might hang the display.
1672          */
1673         assert_planes_disabled(dev_priv, pipe);
1674         assert_sprites_disabled(dev_priv, pipe);
1675
1676         /* Don't disable pipe A or pipe A PLLs if needed */
1677         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1678                 return;
1679
1680         reg = PIPECONF(cpu_transcoder);
1681         val = I915_READ(reg);
1682         if ((val & PIPECONF_ENABLE) == 0)
1683                 return;
1684
1685         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1686         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1687 }
1688
1689 /*
1690  * Plane regs are double buffered, going from enabled->disabled needs a
1691  * trigger in order to latch.  The display address reg provides this.
1692  */
1693 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1694                                       enum plane plane)
1695 {
1696         if (dev_priv->info->gen >= 4)
1697                 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1698         else
1699                 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1700 }
1701
1702 /**
1703  * intel_enable_plane - enable a display plane on a given pipe
1704  * @dev_priv: i915 private structure
1705  * @plane: plane to enable
1706  * @pipe: pipe being fed
1707  *
1708  * Enable @plane on @pipe, making sure that @pipe is running first.
1709  */
1710 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1711                                enum plane plane, enum pipe pipe)
1712 {
1713         int reg;
1714         u32 val;
1715
1716         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1717         assert_pipe_enabled(dev_priv, pipe);
1718
1719         reg = DSPCNTR(plane);
1720         val = I915_READ(reg);
1721         if (val & DISPLAY_PLANE_ENABLE)
1722                 return;
1723
1724         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1725         intel_flush_display_plane(dev_priv, plane);
1726         intel_wait_for_vblank(dev_priv->dev, pipe);
1727 }
1728
1729 /**
1730  * intel_disable_plane - disable a display plane
1731  * @dev_priv: i915 private structure
1732  * @plane: plane to disable
1733  * @pipe: pipe consuming the data
1734  *
1735  * Disable @plane; should be an independent operation.
1736  */
1737 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1738                                 enum plane plane, enum pipe pipe)
1739 {
1740         int reg;
1741         u32 val;
1742
1743         reg = DSPCNTR(plane);
1744         val = I915_READ(reg);
1745         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1746                 return;
1747
1748         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1749         intel_flush_display_plane(dev_priv, plane);
1750         intel_wait_for_vblank(dev_priv->dev, pipe);
1751 }
1752
1753 static bool need_vtd_wa(struct drm_device *dev)
1754 {
1755 #ifdef CONFIG_INTEL_IOMMU
1756         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1757                 return true;
1758 #endif
1759         return false;
1760 }
1761
1762 int
1763 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1764                            struct drm_i915_gem_object *obj,
1765                            struct intel_ring_buffer *pipelined)
1766 {
1767         struct drm_i915_private *dev_priv = dev->dev_private;
1768         u32 alignment;
1769         int ret;
1770
1771         switch (obj->tiling_mode) {
1772         case I915_TILING_NONE:
1773                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1774                         alignment = 128 * 1024;
1775                 else if (INTEL_INFO(dev)->gen >= 4)
1776                         alignment = 4 * 1024;
1777                 else
1778                         alignment = 64 * 1024;
1779                 break;
1780         case I915_TILING_X:
1781                 /* pin() will align the object as required by fence */
1782                 alignment = 0;
1783                 break;
1784         case I915_TILING_Y:
1785                 /* Despite that we check this in framebuffer_init userspace can
1786                  * screw us over and change the tiling after the fact. Only
1787                  * pinned buffers can't change their tiling. */
1788                 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
1789                 return -EINVAL;
1790         default:
1791                 BUG();
1792         }
1793
1794         /* Note that the w/a also requires 64 PTE of padding following the
1795          * bo. We currently fill all unused PTE with the shadow page and so
1796          * we should always have valid PTE following the scanout preventing
1797          * the VT-d warning.
1798          */
1799         if (need_vtd_wa(dev) && alignment < 256 * 1024)
1800                 alignment = 256 * 1024;
1801
1802         dev_priv->mm.interruptible = false;
1803         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1804         if (ret)
1805                 goto err_interruptible;
1806
1807         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1808          * fence, whereas 965+ only requires a fence if using
1809          * framebuffer compression.  For simplicity, we always install
1810          * a fence as the cost is not that onerous.
1811          */
1812         ret = i915_gem_object_get_fence(obj);
1813         if (ret)
1814                 goto err_unpin;
1815
1816         i915_gem_object_pin_fence(obj);
1817
1818         dev_priv->mm.interruptible = true;
1819         return 0;
1820
1821 err_unpin:
1822         i915_gem_object_unpin(obj);
1823 err_interruptible:
1824         dev_priv->mm.interruptible = true;
1825         return ret;
1826 }
1827
1828 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1829 {
1830         i915_gem_object_unpin_fence(obj);
1831         i915_gem_object_unpin(obj);
1832 }
1833
1834 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1835  * is assumed to be a power-of-two. */
1836 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1837                                              unsigned int tiling_mode,
1838                                              unsigned int cpp,
1839                                              unsigned int pitch)
1840 {
1841         if (tiling_mode != I915_TILING_NONE) {
1842                 unsigned int tile_rows, tiles;
1843
1844                 tile_rows = *y / 8;
1845                 *y %= 8;
1846
1847                 tiles = *x / (512/cpp);
1848                 *x %= 512/cpp;
1849
1850                 return tile_rows * pitch * 8 + tiles * 4096;
1851         } else {
1852                 unsigned int offset;
1853
1854                 offset = *y * pitch + *x * cpp;
1855                 *y = 0;
1856                 *x = (offset & 4095) / cpp;
1857                 return offset & -4096;
1858         }
1859 }
1860
1861 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1862                              int x, int y)
1863 {
1864         struct drm_device *dev = crtc->dev;
1865         struct drm_i915_private *dev_priv = dev->dev_private;
1866         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1867         struct intel_framebuffer *intel_fb;
1868         struct drm_i915_gem_object *obj;
1869         int plane = intel_crtc->plane;
1870         unsigned long linear_offset;
1871         u32 dspcntr;
1872         u32 reg;
1873
1874         switch (plane) {
1875         case 0:
1876         case 1:
1877                 break;
1878         default:
1879                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
1880                 return -EINVAL;
1881         }
1882
1883         intel_fb = to_intel_framebuffer(fb);
1884         obj = intel_fb->obj;
1885
1886         reg = DSPCNTR(plane);
1887         dspcntr = I915_READ(reg);
1888         /* Mask out pixel format bits in case we change it */
1889         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1890         switch (fb->pixel_format) {
1891         case DRM_FORMAT_C8:
1892                 dspcntr |= DISPPLANE_8BPP;
1893                 break;
1894         case DRM_FORMAT_XRGB1555:
1895         case DRM_FORMAT_ARGB1555:
1896                 dspcntr |= DISPPLANE_BGRX555;
1897                 break;
1898         case DRM_FORMAT_RGB565:
1899                 dspcntr |= DISPPLANE_BGRX565;
1900                 break;
1901         case DRM_FORMAT_XRGB8888:
1902         case DRM_FORMAT_ARGB8888:
1903                 dspcntr |= DISPPLANE_BGRX888;
1904                 break;
1905         case DRM_FORMAT_XBGR8888:
1906         case DRM_FORMAT_ABGR8888:
1907                 dspcntr |= DISPPLANE_RGBX888;
1908                 break;
1909         case DRM_FORMAT_XRGB2101010:
1910         case DRM_FORMAT_ARGB2101010:
1911                 dspcntr |= DISPPLANE_BGRX101010;
1912                 break;
1913         case DRM_FORMAT_XBGR2101010:
1914         case DRM_FORMAT_ABGR2101010:
1915                 dspcntr |= DISPPLANE_RGBX101010;
1916                 break;
1917         default:
1918                 BUG();
1919         }
1920
1921         if (INTEL_INFO(dev)->gen >= 4) {
1922                 if (obj->tiling_mode != I915_TILING_NONE)
1923                         dspcntr |= DISPPLANE_TILED;
1924                 else
1925                         dspcntr &= ~DISPPLANE_TILED;
1926         }
1927
1928         if (IS_G4X(dev))
1929                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1930
1931         I915_WRITE(reg, dspcntr);
1932
1933         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
1934
1935         if (INTEL_INFO(dev)->gen >= 4) {
1936                 intel_crtc->dspaddr_offset =
1937                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
1938                                                        fb->bits_per_pixel / 8,
1939                                                        fb->pitches[0]);
1940                 linear_offset -= intel_crtc->dspaddr_offset;
1941         } else {
1942                 intel_crtc->dspaddr_offset = linear_offset;
1943         }
1944
1945         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
1946                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
1947         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
1948         if (INTEL_INFO(dev)->gen >= 4) {
1949                 I915_MODIFY_DISPBASE(DSPSURF(plane),
1950                                      obj->gtt_offset + intel_crtc->dspaddr_offset);
1951                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1952                 I915_WRITE(DSPLINOFF(plane), linear_offset);
1953         } else
1954                 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
1955         POSTING_READ(reg);
1956
1957         return 0;
1958 }
1959
1960 static int ironlake_update_plane(struct drm_crtc *crtc,
1961                                  struct drm_framebuffer *fb, int x, int y)
1962 {
1963         struct drm_device *dev = crtc->dev;
1964         struct drm_i915_private *dev_priv = dev->dev_private;
1965         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1966         struct intel_framebuffer *intel_fb;
1967         struct drm_i915_gem_object *obj;
1968         int plane = intel_crtc->plane;
1969         unsigned long linear_offset;
1970         u32 dspcntr;
1971         u32 reg;
1972
1973         switch (plane) {
1974         case 0:
1975         case 1:
1976         case 2:
1977                 break;
1978         default:
1979                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
1980                 return -EINVAL;
1981         }
1982
1983         intel_fb = to_intel_framebuffer(fb);
1984         obj = intel_fb->obj;
1985
1986         reg = DSPCNTR(plane);
1987         dspcntr = I915_READ(reg);
1988         /* Mask out pixel format bits in case we change it */
1989         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1990         switch (fb->pixel_format) {
1991         case DRM_FORMAT_C8:
1992                 dspcntr |= DISPPLANE_8BPP;
1993                 break;
1994         case DRM_FORMAT_RGB565:
1995                 dspcntr |= DISPPLANE_BGRX565;
1996                 break;
1997         case DRM_FORMAT_XRGB8888:
1998         case DRM_FORMAT_ARGB8888:
1999                 dspcntr |= DISPPLANE_BGRX888;
2000                 break;
2001         case DRM_FORMAT_XBGR8888:
2002         case DRM_FORMAT_ABGR8888:
2003                 dspcntr |= DISPPLANE_RGBX888;
2004                 break;
2005         case DRM_FORMAT_XRGB2101010:
2006         case DRM_FORMAT_ARGB2101010:
2007                 dspcntr |= DISPPLANE_BGRX101010;
2008                 break;
2009         case DRM_FORMAT_XBGR2101010:
2010         case DRM_FORMAT_ABGR2101010:
2011                 dspcntr |= DISPPLANE_RGBX101010;
2012                 break;
2013         default:
2014                 BUG();
2015         }
2016
2017         if (obj->tiling_mode != I915_TILING_NONE)
2018                 dspcntr |= DISPPLANE_TILED;
2019         else
2020                 dspcntr &= ~DISPPLANE_TILED;
2021
2022         /* must disable */
2023         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2024
2025         I915_WRITE(reg, dspcntr);
2026
2027         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2028         intel_crtc->dspaddr_offset =
2029                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2030                                                fb->bits_per_pixel / 8,
2031                                                fb->pitches[0]);
2032         linear_offset -= intel_crtc->dspaddr_offset;
2033
2034         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2035                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2036         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2037         I915_MODIFY_DISPBASE(DSPSURF(plane),
2038                              obj->gtt_offset + intel_crtc->dspaddr_offset);
2039         if (IS_HASWELL(dev)) {
2040                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2041         } else {
2042                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2043                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2044         }
2045         POSTING_READ(reg);
2046
2047         return 0;
2048 }
2049
2050 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2051 static int
2052 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2053                            int x, int y, enum mode_set_atomic state)
2054 {
2055         struct drm_device *dev = crtc->dev;
2056         struct drm_i915_private *dev_priv = dev->dev_private;
2057
2058         if (dev_priv->display.disable_fbc)
2059                 dev_priv->display.disable_fbc(dev);
2060         intel_increase_pllclock(crtc);
2061
2062         return dev_priv->display.update_plane(crtc, fb, x, y);
2063 }
2064
2065 void intel_display_handle_reset(struct drm_device *dev)
2066 {
2067         struct drm_i915_private *dev_priv = dev->dev_private;
2068         struct drm_crtc *crtc;
2069
2070         /*
2071          * Flips in the rings have been nuked by the reset,
2072          * so complete all pending flips so that user space
2073          * will get its events and not get stuck.
2074          *
2075          * Also update the base address of all primary
2076          * planes to the the last fb to make sure we're
2077          * showing the correct fb after a reset.
2078          *
2079          * Need to make two loops over the crtcs so that we
2080          * don't try to grab a crtc mutex before the
2081          * pending_flip_queue really got woken up.
2082          */
2083
2084         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2085                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2086                 enum plane plane = intel_crtc->plane;
2087
2088                 intel_prepare_page_flip(dev, plane);
2089                 intel_finish_page_flip_plane(dev, plane);
2090         }
2091
2092         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2093                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2094
2095                 mutex_lock(&crtc->mutex);
2096                 if (intel_crtc->active)
2097                         dev_priv->display.update_plane(crtc, crtc->fb,
2098                                                        crtc->x, crtc->y);
2099                 mutex_unlock(&crtc->mutex);
2100         }
2101 }
2102
2103 static int
2104 intel_finish_fb(struct drm_framebuffer *old_fb)
2105 {
2106         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2107         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2108         bool was_interruptible = dev_priv->mm.interruptible;
2109         int ret;
2110
2111         /* Big Hammer, we also need to ensure that any pending
2112          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2113          * current scanout is retired before unpinning the old
2114          * framebuffer.
2115          *
2116          * This should only fail upon a hung GPU, in which case we
2117          * can safely continue.
2118          */
2119         dev_priv->mm.interruptible = false;
2120         ret = i915_gem_object_finish_gpu(obj);
2121         dev_priv->mm.interruptible = was_interruptible;
2122
2123         return ret;
2124 }
2125
2126 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2127 {
2128         struct drm_device *dev = crtc->dev;
2129         struct drm_i915_master_private *master_priv;
2130         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2131
2132         if (!dev->primary->master)
2133                 return;
2134
2135         master_priv = dev->primary->master->driver_priv;
2136         if (!master_priv->sarea_priv)
2137                 return;
2138
2139         switch (intel_crtc->pipe) {
2140         case 0:
2141                 master_priv->sarea_priv->pipeA_x = x;
2142                 master_priv->sarea_priv->pipeA_y = y;
2143                 break;
2144         case 1:
2145                 master_priv->sarea_priv->pipeB_x = x;
2146                 master_priv->sarea_priv->pipeB_y = y;
2147                 break;
2148         default:
2149                 break;
2150         }
2151 }
2152
2153 static int
2154 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2155                     struct drm_framebuffer *fb)
2156 {
2157         struct drm_device *dev = crtc->dev;
2158         struct drm_i915_private *dev_priv = dev->dev_private;
2159         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2160         struct drm_framebuffer *old_fb;
2161         int ret;
2162
2163         /* no fb bound */
2164         if (!fb) {
2165                 DRM_ERROR("No FB bound\n");
2166                 return 0;
2167         }
2168
2169         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2170                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2171                           plane_name(intel_crtc->plane),
2172                           INTEL_INFO(dev)->num_pipes);
2173                 return -EINVAL;
2174         }
2175
2176         mutex_lock(&dev->struct_mutex);
2177         ret = intel_pin_and_fence_fb_obj(dev,
2178                                          to_intel_framebuffer(fb)->obj,
2179                                          NULL);
2180         if (ret != 0) {
2181                 mutex_unlock(&dev->struct_mutex);
2182                 DRM_ERROR("pin & fence failed\n");
2183                 return ret;
2184         }
2185
2186         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2187         if (ret) {
2188                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2189                 mutex_unlock(&dev->struct_mutex);
2190                 DRM_ERROR("failed to update base address\n");
2191                 return ret;
2192         }
2193
2194         old_fb = crtc->fb;
2195         crtc->fb = fb;
2196         crtc->x = x;
2197         crtc->y = y;
2198
2199         if (old_fb) {
2200                 if (intel_crtc->active && old_fb != fb)
2201                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2202                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2203         }
2204
2205         intel_update_fbc(dev);
2206         mutex_unlock(&dev->struct_mutex);
2207
2208         intel_crtc_update_sarea_pos(crtc, x, y);
2209
2210         return 0;
2211 }
2212
2213 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2214 {
2215         struct drm_device *dev = crtc->dev;
2216         struct drm_i915_private *dev_priv = dev->dev_private;
2217         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2218         int pipe = intel_crtc->pipe;
2219         u32 reg, temp;
2220
2221         /* enable normal train */
2222         reg = FDI_TX_CTL(pipe);
2223         temp = I915_READ(reg);
2224         if (IS_IVYBRIDGE(dev)) {
2225                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2226                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2227         } else {
2228                 temp &= ~FDI_LINK_TRAIN_NONE;
2229                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2230         }
2231         I915_WRITE(reg, temp);
2232
2233         reg = FDI_RX_CTL(pipe);
2234         temp = I915_READ(reg);
2235         if (HAS_PCH_CPT(dev)) {
2236                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2237                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2238         } else {
2239                 temp &= ~FDI_LINK_TRAIN_NONE;
2240                 temp |= FDI_LINK_TRAIN_NONE;
2241         }
2242         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2243
2244         /* wait one idle pattern time */
2245         POSTING_READ(reg);
2246         udelay(1000);
2247
2248         /* IVB wants error correction enabled */
2249         if (IS_IVYBRIDGE(dev))
2250                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2251                            FDI_FE_ERRC_ENABLE);
2252 }
2253
2254 static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2255 {
2256         return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2257 }
2258
2259 static void ivb_modeset_global_resources(struct drm_device *dev)
2260 {
2261         struct drm_i915_private *dev_priv = dev->dev_private;
2262         struct intel_crtc *pipe_B_crtc =
2263                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2264         struct intel_crtc *pipe_C_crtc =
2265                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2266         uint32_t temp;
2267
2268         /*
2269          * When everything is off disable fdi C so that we could enable fdi B
2270          * with all lanes. Note that we don't care about enabled pipes without
2271          * an enabled pch encoder.
2272          */
2273         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2274             !pipe_has_enabled_pch(pipe_C_crtc)) {
2275                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2276                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2277
2278                 temp = I915_READ(SOUTH_CHICKEN1);
2279                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2280                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2281                 I915_WRITE(SOUTH_CHICKEN1, temp);
2282         }
2283 }
2284
2285 /* The FDI link training functions for ILK/Ibexpeak. */
2286 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2287 {
2288         struct drm_device *dev = crtc->dev;
2289         struct drm_i915_private *dev_priv = dev->dev_private;
2290         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2291         int pipe = intel_crtc->pipe;
2292         int plane = intel_crtc->plane;
2293         u32 reg, temp, tries;
2294
2295         /* FDI needs bits from pipe & plane first */
2296         assert_pipe_enabled(dev_priv, pipe);
2297         assert_plane_enabled(dev_priv, plane);
2298
2299         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2300            for train result */
2301         reg = FDI_RX_IMR(pipe);
2302         temp = I915_READ(reg);
2303         temp &= ~FDI_RX_SYMBOL_LOCK;
2304         temp &= ~FDI_RX_BIT_LOCK;
2305         I915_WRITE(reg, temp);
2306         I915_READ(reg);
2307         udelay(150);
2308
2309         /* enable CPU FDI TX and PCH FDI RX */
2310         reg = FDI_TX_CTL(pipe);
2311         temp = I915_READ(reg);
2312         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2313         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2314         temp &= ~FDI_LINK_TRAIN_NONE;
2315         temp |= FDI_LINK_TRAIN_PATTERN_1;
2316         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2317
2318         reg = FDI_RX_CTL(pipe);
2319         temp = I915_READ(reg);
2320         temp &= ~FDI_LINK_TRAIN_NONE;
2321         temp |= FDI_LINK_TRAIN_PATTERN_1;
2322         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2323
2324         POSTING_READ(reg);
2325         udelay(150);
2326
2327         /* Ironlake workaround, enable clock pointer after FDI enable*/
2328         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2329         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2330                    FDI_RX_PHASE_SYNC_POINTER_EN);
2331
2332         reg = FDI_RX_IIR(pipe);
2333         for (tries = 0; tries < 5; tries++) {
2334                 temp = I915_READ(reg);
2335                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2336
2337                 if ((temp & FDI_RX_BIT_LOCK)) {
2338                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2339                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2340                         break;
2341                 }
2342         }
2343         if (tries == 5)
2344                 DRM_ERROR("FDI train 1 fail!\n");
2345
2346         /* Train 2 */
2347         reg = FDI_TX_CTL(pipe);
2348         temp = I915_READ(reg);
2349         temp &= ~FDI_LINK_TRAIN_NONE;
2350         temp |= FDI_LINK_TRAIN_PATTERN_2;
2351         I915_WRITE(reg, temp);
2352
2353         reg = FDI_RX_CTL(pipe);
2354         temp = I915_READ(reg);
2355         temp &= ~FDI_LINK_TRAIN_NONE;
2356         temp |= FDI_LINK_TRAIN_PATTERN_2;
2357         I915_WRITE(reg, temp);
2358
2359         POSTING_READ(reg);
2360         udelay(150);
2361
2362         reg = FDI_RX_IIR(pipe);
2363         for (tries = 0; tries < 5; tries++) {
2364                 temp = I915_READ(reg);
2365                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2366
2367                 if (temp & FDI_RX_SYMBOL_LOCK) {
2368                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2369                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2370                         break;
2371                 }
2372         }
2373         if (tries == 5)
2374                 DRM_ERROR("FDI train 2 fail!\n");
2375
2376         DRM_DEBUG_KMS("FDI train done\n");
2377
2378 }
2379
2380 static const int snb_b_fdi_train_param[] = {
2381         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2382         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2383         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2384         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2385 };
2386
2387 /* The FDI link training functions for SNB/Cougarpoint. */
2388 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2389 {
2390         struct drm_device *dev = crtc->dev;
2391         struct drm_i915_private *dev_priv = dev->dev_private;
2392         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2393         int pipe = intel_crtc->pipe;
2394         u32 reg, temp, i, retry;
2395
2396         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2397            for train result */
2398         reg = FDI_RX_IMR(pipe);
2399         temp = I915_READ(reg);
2400         temp &= ~FDI_RX_SYMBOL_LOCK;
2401         temp &= ~FDI_RX_BIT_LOCK;
2402         I915_WRITE(reg, temp);
2403
2404         POSTING_READ(reg);
2405         udelay(150);
2406
2407         /* enable CPU FDI TX and PCH FDI RX */
2408         reg = FDI_TX_CTL(pipe);
2409         temp = I915_READ(reg);
2410         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2411         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2412         temp &= ~FDI_LINK_TRAIN_NONE;
2413         temp |= FDI_LINK_TRAIN_PATTERN_1;
2414         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2415         /* SNB-B */
2416         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2417         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2418
2419         I915_WRITE(FDI_RX_MISC(pipe),
2420                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2421
2422         reg = FDI_RX_CTL(pipe);
2423         temp = I915_READ(reg);
2424         if (HAS_PCH_CPT(dev)) {
2425                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2426                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2427         } else {
2428                 temp &= ~FDI_LINK_TRAIN_NONE;
2429                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2430         }
2431         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2432
2433         POSTING_READ(reg);
2434         udelay(150);
2435
2436         for (i = 0; i < 4; i++) {
2437                 reg = FDI_TX_CTL(pipe);
2438                 temp = I915_READ(reg);
2439                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2440                 temp |= snb_b_fdi_train_param[i];
2441                 I915_WRITE(reg, temp);
2442
2443                 POSTING_READ(reg);
2444                 udelay(500);
2445
2446                 for (retry = 0; retry < 5; retry++) {
2447                         reg = FDI_RX_IIR(pipe);
2448                         temp = I915_READ(reg);
2449                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2450                         if (temp & FDI_RX_BIT_LOCK) {
2451                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2452                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2453                                 break;
2454                         }
2455                         udelay(50);
2456                 }
2457                 if (retry < 5)
2458                         break;
2459         }
2460         if (i == 4)
2461                 DRM_ERROR("FDI train 1 fail!\n");
2462
2463         /* Train 2 */
2464         reg = FDI_TX_CTL(pipe);
2465         temp = I915_READ(reg);
2466         temp &= ~FDI_LINK_TRAIN_NONE;
2467         temp |= FDI_LINK_TRAIN_PATTERN_2;
2468         if (IS_GEN6(dev)) {
2469                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2470                 /* SNB-B */
2471                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2472         }
2473         I915_WRITE(reg, temp);
2474
2475         reg = FDI_RX_CTL(pipe);
2476         temp = I915_READ(reg);
2477         if (HAS_PCH_CPT(dev)) {
2478                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2479                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2480         } else {
2481                 temp &= ~FDI_LINK_TRAIN_NONE;
2482                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2483         }
2484         I915_WRITE(reg, temp);
2485
2486         POSTING_READ(reg);
2487         udelay(150);
2488
2489         for (i = 0; i < 4; i++) {
2490                 reg = FDI_TX_CTL(pipe);
2491                 temp = I915_READ(reg);
2492                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2493                 temp |= snb_b_fdi_train_param[i];
2494                 I915_WRITE(reg, temp);
2495
2496                 POSTING_READ(reg);
2497                 udelay(500);
2498
2499                 for (retry = 0; retry < 5; retry++) {
2500                         reg = FDI_RX_IIR(pipe);
2501                         temp = I915_READ(reg);
2502                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2503                         if (temp & FDI_RX_SYMBOL_LOCK) {
2504                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2505                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2506                                 break;
2507                         }
2508                         udelay(50);
2509                 }
2510                 if (retry < 5)
2511                         break;
2512         }
2513         if (i == 4)
2514                 DRM_ERROR("FDI train 2 fail!\n");
2515
2516         DRM_DEBUG_KMS("FDI train done.\n");
2517 }
2518
2519 /* Manual link training for Ivy Bridge A0 parts */
2520 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2521 {
2522         struct drm_device *dev = crtc->dev;
2523         struct drm_i915_private *dev_priv = dev->dev_private;
2524         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2525         int pipe = intel_crtc->pipe;
2526         u32 reg, temp, i;
2527
2528         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2529            for train result */
2530         reg = FDI_RX_IMR(pipe);
2531         temp = I915_READ(reg);
2532         temp &= ~FDI_RX_SYMBOL_LOCK;
2533         temp &= ~FDI_RX_BIT_LOCK;
2534         I915_WRITE(reg, temp);
2535
2536         POSTING_READ(reg);
2537         udelay(150);
2538
2539         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2540                       I915_READ(FDI_RX_IIR(pipe)));
2541
2542         /* enable CPU FDI TX and PCH FDI RX */
2543         reg = FDI_TX_CTL(pipe);
2544         temp = I915_READ(reg);
2545         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2546         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2547         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2548         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2549         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2550         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2551         temp |= FDI_COMPOSITE_SYNC;
2552         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2553
2554         I915_WRITE(FDI_RX_MISC(pipe),
2555                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2556
2557         reg = FDI_RX_CTL(pipe);
2558         temp = I915_READ(reg);
2559         temp &= ~FDI_LINK_TRAIN_AUTO;
2560         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2561         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2562         temp |= FDI_COMPOSITE_SYNC;
2563         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2564
2565         POSTING_READ(reg);
2566         udelay(150);
2567
2568         for (i = 0; i < 4; i++) {
2569                 reg = FDI_TX_CTL(pipe);
2570                 temp = I915_READ(reg);
2571                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2572                 temp |= snb_b_fdi_train_param[i];
2573                 I915_WRITE(reg, temp);
2574
2575                 POSTING_READ(reg);
2576                 udelay(500);
2577
2578                 reg = FDI_RX_IIR(pipe);
2579                 temp = I915_READ(reg);
2580                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2581
2582                 if (temp & FDI_RX_BIT_LOCK ||
2583                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2584                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2585                         DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
2586                         break;
2587                 }
2588         }
2589         if (i == 4)
2590                 DRM_ERROR("FDI train 1 fail!\n");
2591
2592         /* Train 2 */
2593         reg = FDI_TX_CTL(pipe);
2594         temp = I915_READ(reg);
2595         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2596         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2597         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2598         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2599         I915_WRITE(reg, temp);
2600
2601         reg = FDI_RX_CTL(pipe);
2602         temp = I915_READ(reg);
2603         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2604         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2605         I915_WRITE(reg, temp);
2606
2607         POSTING_READ(reg);
2608         udelay(150);
2609
2610         for (i = 0; i < 4; i++) {
2611                 reg = FDI_TX_CTL(pipe);
2612                 temp = I915_READ(reg);
2613                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2614                 temp |= snb_b_fdi_train_param[i];
2615                 I915_WRITE(reg, temp);
2616
2617                 POSTING_READ(reg);
2618                 udelay(500);
2619
2620                 reg = FDI_RX_IIR(pipe);
2621                 temp = I915_READ(reg);
2622                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2623
2624                 if (temp & FDI_RX_SYMBOL_LOCK) {
2625                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2626                         DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
2627                         break;
2628                 }
2629         }
2630         if (i == 4)
2631                 DRM_ERROR("FDI train 2 fail!\n");
2632
2633         DRM_DEBUG_KMS("FDI train done.\n");
2634 }
2635
2636 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2637 {
2638         struct drm_device *dev = intel_crtc->base.dev;
2639         struct drm_i915_private *dev_priv = dev->dev_private;
2640         int pipe = intel_crtc->pipe;
2641         u32 reg, temp;
2642
2643
2644         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2645         reg = FDI_RX_CTL(pipe);
2646         temp = I915_READ(reg);
2647         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2648         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2649         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2650         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2651
2652         POSTING_READ(reg);
2653         udelay(200);
2654
2655         /* Switch from Rawclk to PCDclk */
2656         temp = I915_READ(reg);
2657         I915_WRITE(reg, temp | FDI_PCDCLK);
2658
2659         POSTING_READ(reg);
2660         udelay(200);
2661
2662         /* Enable CPU FDI TX PLL, always on for Ironlake */
2663         reg = FDI_TX_CTL(pipe);
2664         temp = I915_READ(reg);
2665         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2666                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2667
2668                 POSTING_READ(reg);
2669                 udelay(100);
2670         }
2671 }
2672
2673 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2674 {
2675         struct drm_device *dev = intel_crtc->base.dev;
2676         struct drm_i915_private *dev_priv = dev->dev_private;
2677         int pipe = intel_crtc->pipe;
2678         u32 reg, temp;
2679
2680         /* Switch from PCDclk to Rawclk */
2681         reg = FDI_RX_CTL(pipe);
2682         temp = I915_READ(reg);
2683         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2684
2685         /* Disable CPU FDI TX PLL */
2686         reg = FDI_TX_CTL(pipe);
2687         temp = I915_READ(reg);
2688         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2689
2690         POSTING_READ(reg);
2691         udelay(100);
2692
2693         reg = FDI_RX_CTL(pipe);
2694         temp = I915_READ(reg);
2695         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2696
2697         /* Wait for the clocks to turn off. */
2698         POSTING_READ(reg);
2699         udelay(100);
2700 }
2701
2702 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2703 {
2704         struct drm_device *dev = crtc->dev;
2705         struct drm_i915_private *dev_priv = dev->dev_private;
2706         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2707         int pipe = intel_crtc->pipe;
2708         u32 reg, temp;
2709
2710         /* disable CPU FDI tx and PCH FDI rx */
2711         reg = FDI_TX_CTL(pipe);
2712         temp = I915_READ(reg);
2713         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2714         POSTING_READ(reg);
2715
2716         reg = FDI_RX_CTL(pipe);
2717         temp = I915_READ(reg);
2718         temp &= ~(0x7 << 16);
2719         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2720         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2721
2722         POSTING_READ(reg);
2723         udelay(100);
2724
2725         /* Ironlake workaround, disable clock pointer after downing FDI */
2726         if (HAS_PCH_IBX(dev)) {
2727                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2728         }
2729
2730         /* still set train pattern 1 */
2731         reg = FDI_TX_CTL(pipe);
2732         temp = I915_READ(reg);
2733         temp &= ~FDI_LINK_TRAIN_NONE;
2734         temp |= FDI_LINK_TRAIN_PATTERN_1;
2735         I915_WRITE(reg, temp);
2736
2737         reg = FDI_RX_CTL(pipe);
2738         temp = I915_READ(reg);
2739         if (HAS_PCH_CPT(dev)) {
2740                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2741                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2742         } else {
2743                 temp &= ~FDI_LINK_TRAIN_NONE;
2744                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2745         }
2746         /* BPC in FDI rx is consistent with that in PIPECONF */
2747         temp &= ~(0x07 << 16);
2748         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2749         I915_WRITE(reg, temp);
2750
2751         POSTING_READ(reg);
2752         udelay(100);
2753 }
2754
2755 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2756 {
2757         struct drm_device *dev = crtc->dev;
2758         struct drm_i915_private *dev_priv = dev->dev_private;
2759         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2760         unsigned long flags;
2761         bool pending;
2762
2763         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2764             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2765                 return false;
2766
2767         spin_lock_irqsave(&dev->event_lock, flags);
2768         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2769         spin_unlock_irqrestore(&dev->event_lock, flags);
2770
2771         return pending;
2772 }
2773
2774 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2775 {
2776         struct drm_device *dev = crtc->dev;
2777         struct drm_i915_private *dev_priv = dev->dev_private;
2778
2779         if (crtc->fb == NULL)
2780                 return;
2781
2782         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2783
2784         wait_event(dev_priv->pending_flip_queue,
2785                    !intel_crtc_has_pending_flip(crtc));
2786
2787         mutex_lock(&dev->struct_mutex);
2788         intel_finish_fb(crtc->fb);
2789         mutex_unlock(&dev->struct_mutex);
2790 }
2791
2792 /* Program iCLKIP clock to the desired frequency */
2793 static void lpt_program_iclkip(struct drm_crtc *crtc)
2794 {
2795         struct drm_device *dev = crtc->dev;
2796         struct drm_i915_private *dev_priv = dev->dev_private;
2797         u32 divsel, phaseinc, auxdiv, phasedir = 0;
2798         u32 temp;
2799
2800         mutex_lock(&dev_priv->dpio_lock);
2801
2802         /* It is necessary to ungate the pixclk gate prior to programming
2803          * the divisors, and gate it back when it is done.
2804          */
2805         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2806
2807         /* Disable SSCCTL */
2808         intel_sbi_write(dev_priv, SBI_SSCCTL6,
2809                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2810                                 SBI_SSCCTL_DISABLE,
2811                         SBI_ICLK);
2812
2813         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2814         if (crtc->mode.clock == 20000) {
2815                 auxdiv = 1;
2816                 divsel = 0x41;
2817                 phaseinc = 0x20;
2818         } else {
2819                 /* The iCLK virtual clock root frequency is in MHz,
2820                  * but the crtc->mode.clock in in KHz. To get the divisors,
2821                  * it is necessary to divide one by another, so we
2822                  * convert the virtual clock precision to KHz here for higher
2823                  * precision.
2824                  */
2825                 u32 iclk_virtual_root_freq = 172800 * 1000;
2826                 u32 iclk_pi_range = 64;
2827                 u32 desired_divisor, msb_divisor_value, pi_value;
2828
2829                 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2830                 msb_divisor_value = desired_divisor / iclk_pi_range;
2831                 pi_value = desired_divisor % iclk_pi_range;
2832
2833                 auxdiv = 0;
2834                 divsel = msb_divisor_value - 2;
2835                 phaseinc = pi_value;
2836         }
2837
2838         /* This should not happen with any sane values */
2839         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2840                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2841         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2842                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2843
2844         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2845                         crtc->mode.clock,
2846                         auxdiv,
2847                         divsel,
2848                         phasedir,
2849                         phaseinc);
2850
2851         /* Program SSCDIVINTPHASE6 */
2852         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
2853         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2854         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2855         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2856         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2857         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2858         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2859         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
2860
2861         /* Program SSCAUXDIV */
2862         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
2863         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2864         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2865         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
2866
2867         /* Enable modulator and associated divider */
2868         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
2869         temp &= ~SBI_SSCCTL_DISABLE;
2870         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
2871
2872         /* Wait for initialization time */
2873         udelay(24);
2874
2875         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2876
2877         mutex_unlock(&dev_priv->dpio_lock);
2878 }
2879
2880 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
2881                                                 enum pipe pch_transcoder)
2882 {
2883         struct drm_device *dev = crtc->base.dev;
2884         struct drm_i915_private *dev_priv = dev->dev_private;
2885         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2886
2887         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
2888                    I915_READ(HTOTAL(cpu_transcoder)));
2889         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
2890                    I915_READ(HBLANK(cpu_transcoder)));
2891         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
2892                    I915_READ(HSYNC(cpu_transcoder)));
2893
2894         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
2895                    I915_READ(VTOTAL(cpu_transcoder)));
2896         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
2897                    I915_READ(VBLANK(cpu_transcoder)));
2898         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
2899                    I915_READ(VSYNC(cpu_transcoder)));
2900         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
2901                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
2902 }
2903
2904 /*
2905  * Enable PCH resources required for PCH ports:
2906  *   - PCH PLLs
2907  *   - FDI training & RX/TX
2908  *   - update transcoder timings
2909  *   - DP transcoding bits
2910  *   - transcoder
2911  */
2912 static void ironlake_pch_enable(struct drm_crtc *crtc)
2913 {
2914         struct drm_device *dev = crtc->dev;
2915         struct drm_i915_private *dev_priv = dev->dev_private;
2916         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2917         int pipe = intel_crtc->pipe;
2918         u32 reg, temp;
2919
2920         assert_pch_transcoder_disabled(dev_priv, pipe);
2921
2922         /* Write the TU size bits before fdi link training, so that error
2923          * detection works. */
2924         I915_WRITE(FDI_RX_TUSIZE1(pipe),
2925                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2926
2927         /* For PCH output, training FDI link */
2928         dev_priv->display.fdi_link_train(crtc);
2929
2930         /* XXX: pch pll's can be enabled any time before we enable the PCH
2931          * transcoder, and we actually should do this to not upset any PCH
2932          * transcoder that already use the clock when we share it.
2933          *
2934          * Note that enable_shared_dpll tries to do the right thing, but
2935          * get_shared_dpll unconditionally resets the pll - we need that to have
2936          * the right LVDS enable sequence. */
2937         ironlake_enable_shared_dpll(intel_crtc);
2938
2939         if (HAS_PCH_CPT(dev)) {
2940                 u32 sel;
2941
2942                 temp = I915_READ(PCH_DPLL_SEL);
2943                 temp |= TRANS_DPLL_ENABLE(pipe);
2944                 sel = TRANS_DPLLB_SEL(pipe);
2945                 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
2946                         temp |= sel;
2947                 else
2948                         temp &= ~sel;
2949                 I915_WRITE(PCH_DPLL_SEL, temp);
2950         }
2951
2952         /* set transcoder timing, panel must allow it */
2953         assert_panel_unlocked(dev_priv, pipe);
2954         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
2955
2956         intel_fdi_normal_train(crtc);
2957
2958         /* For PCH DP, enable TRANS_DP_CTL */
2959         if (HAS_PCH_CPT(dev) &&
2960             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
2961              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2962                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
2963                 reg = TRANS_DP_CTL(pipe);
2964                 temp = I915_READ(reg);
2965                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2966                           TRANS_DP_SYNC_MASK |
2967                           TRANS_DP_BPC_MASK);
2968                 temp |= (TRANS_DP_OUTPUT_ENABLE |
2969                          TRANS_DP_ENH_FRAMING);
2970                 temp |= bpc << 9; /* same format but at 11:9 */
2971
2972                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2973                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2974                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2975                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2976
2977                 switch (intel_trans_dp_port_sel(crtc)) {
2978                 case PCH_DP_B:
2979                         temp |= TRANS_DP_PORT_SEL_B;
2980                         break;
2981                 case PCH_DP_C:
2982                         temp |= TRANS_DP_PORT_SEL_C;
2983                         break;
2984                 case PCH_DP_D:
2985                         temp |= TRANS_DP_PORT_SEL_D;
2986                         break;
2987                 default:
2988                         BUG();
2989                 }
2990
2991                 I915_WRITE(reg, temp);
2992         }
2993
2994         ironlake_enable_pch_transcoder(dev_priv, pipe);
2995 }
2996
2997 static void lpt_pch_enable(struct drm_crtc *crtc)
2998 {
2999         struct drm_device *dev = crtc->dev;
3000         struct drm_i915_private *dev_priv = dev->dev_private;
3001         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3002         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3003
3004         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3005
3006         lpt_program_iclkip(crtc);
3007
3008         /* Set transcoder timing. */
3009         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3010
3011         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3012 }
3013
3014 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3015 {
3016         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3017
3018         if (pll == NULL)
3019                 return;
3020
3021         if (pll->refcount == 0) {
3022                 WARN(1, "bad %s refcount\n", pll->name);
3023                 return;
3024         }
3025
3026         if (--pll->refcount == 0) {
3027                 WARN_ON(pll->on);
3028                 WARN_ON(pll->active);
3029         }
3030
3031         crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3032 }
3033
3034 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, u32 dpll, u32 fp)
3035 {
3036         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3037         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3038         enum intel_dpll_id i;
3039
3040         if (pll) {
3041                 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3042                               crtc->base.base.id, pll->name);
3043                 intel_put_shared_dpll(crtc);
3044         }
3045
3046         if (HAS_PCH_IBX(dev_priv->dev)) {
3047                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3048                 i = crtc->pipe;
3049                 pll = &dev_priv->shared_dplls[i];
3050
3051                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3052                               crtc->base.base.id, pll->name);
3053
3054                 goto found;
3055         }
3056
3057         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3058                 pll = &dev_priv->shared_dplls[i];
3059
3060                 /* Only want to check enabled timings first */
3061                 if (pll->refcount == 0)
3062                         continue;
3063
3064                 if (dpll == (I915_READ(PCH_DPLL(pll->id)) & 0x7fffffff) &&
3065                     fp == I915_READ(PCH_FP0(pll->id))) {
3066                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3067                                       crtc->base.base.id,
3068                                       pll->name, pll->refcount, pll->active);
3069
3070                         goto found;
3071                 }
3072         }
3073
3074         /* Ok no matching timings, maybe there's a free one? */
3075         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3076                 pll = &dev_priv->shared_dplls[i];
3077                 if (pll->refcount == 0) {
3078                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3079                                       crtc->base.base.id, pll->name);
3080                         goto found;
3081                 }
3082         }
3083
3084         return NULL;
3085
3086 found:
3087         crtc->config.shared_dpll = i;
3088         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3089                          pipe_name(crtc->pipe));
3090
3091         if (pll->active == 0) {
3092                 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3093                        sizeof(pll->hw_state));
3094
3095                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
3096                 WARN_ON(pll->on);
3097                 assert_shared_dpll_disabled(dev_priv, pll);
3098
3099                 /* Wait for the clocks to stabilize before rewriting the regs */
3100                 I915_WRITE(PCH_DPLL(pll->id), dpll & ~DPLL_VCO_ENABLE);
3101                 POSTING_READ(PCH_DPLL(pll->id));
3102                 udelay(150);
3103
3104                 I915_WRITE(PCH_FP0(pll->id), fp);
3105                 I915_WRITE(PCH_DPLL(pll->id), dpll & ~DPLL_VCO_ENABLE);
3106         }
3107         pll->refcount++;
3108
3109         return pll;
3110 }
3111
3112 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3113 {
3114         struct drm_i915_private *dev_priv = dev->dev_private;
3115         int dslreg = PIPEDSL(pipe);
3116         u32 temp;
3117
3118         temp = I915_READ(dslreg);
3119         udelay(500);
3120         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3121                 if (wait_for(I915_READ(dslreg) != temp, 5))
3122                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3123         }
3124 }
3125
3126 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3127 {
3128         struct drm_device *dev = crtc->base.dev;
3129         struct drm_i915_private *dev_priv = dev->dev_private;
3130         int pipe = crtc->pipe;
3131
3132         if (crtc->config.pch_pfit.size) {
3133                 /* Force use of hard-coded filter coefficients
3134                  * as some pre-programmed values are broken,
3135                  * e.g. x201.
3136                  */
3137                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3138                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3139                                                  PF_PIPE_SEL_IVB(pipe));
3140                 else
3141                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3142                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3143                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3144         }
3145 }
3146
3147 static void intel_enable_planes(struct drm_crtc *crtc)
3148 {
3149         struct drm_device *dev = crtc->dev;
3150         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3151         struct intel_plane *intel_plane;
3152
3153         list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3154                 if (intel_plane->pipe == pipe)
3155                         intel_plane_restore(&intel_plane->base);
3156 }
3157
3158 static void intel_disable_planes(struct drm_crtc *crtc)
3159 {
3160         struct drm_device *dev = crtc->dev;
3161         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3162         struct intel_plane *intel_plane;
3163
3164         list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3165                 if (intel_plane->pipe == pipe)
3166                         intel_plane_disable(&intel_plane->base);
3167 }
3168
3169 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3170 {
3171         struct drm_device *dev = crtc->dev;
3172         struct drm_i915_private *dev_priv = dev->dev_private;
3173         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3174         struct intel_encoder *encoder;
3175         int pipe = intel_crtc->pipe;
3176         int plane = intel_crtc->plane;
3177         u32 temp;
3178
3179         WARN_ON(!crtc->enabled);
3180
3181         if (intel_crtc->active)
3182                 return;
3183
3184         intel_crtc->active = true;
3185
3186         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3187         intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3188
3189         intel_update_watermarks(dev);
3190
3191         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3192                 temp = I915_READ(PCH_LVDS);
3193                 if ((temp & LVDS_PORT_EN) == 0)
3194                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3195         }
3196
3197
3198         if (intel_crtc->config.has_pch_encoder) {
3199                 /* Note: FDI PLL enabling _must_ be done before we enable the
3200                  * cpu pipes, hence this is separate from all the other fdi/pch
3201                  * enabling. */
3202                 ironlake_fdi_pll_enable(intel_crtc);
3203         } else {
3204                 assert_fdi_tx_disabled(dev_priv, pipe);
3205                 assert_fdi_rx_disabled(dev_priv, pipe);
3206         }
3207
3208         for_each_encoder_on_crtc(dev, crtc, encoder)
3209                 if (encoder->pre_enable)
3210                         encoder->pre_enable(encoder);
3211
3212         /* Enable panel fitting for LVDS */
3213         ironlake_pfit_enable(intel_crtc);
3214
3215         /*
3216          * On ILK+ LUT must be loaded before the pipe is running but with
3217          * clocks enabled
3218          */
3219         intel_crtc_load_lut(crtc);
3220
3221         intel_enable_pipe(dev_priv, pipe,
3222                           intel_crtc->config.has_pch_encoder);
3223         intel_enable_plane(dev_priv, plane, pipe);
3224         intel_enable_planes(crtc);
3225         intel_crtc_update_cursor(crtc, true);
3226
3227         if (intel_crtc->config.has_pch_encoder)
3228                 ironlake_pch_enable(crtc);
3229
3230         mutex_lock(&dev->struct_mutex);
3231         intel_update_fbc(dev);
3232         mutex_unlock(&dev->struct_mutex);
3233
3234         for_each_encoder_on_crtc(dev, crtc, encoder)
3235                 encoder->enable(encoder);
3236
3237         if (HAS_PCH_CPT(dev))
3238                 cpt_verify_modeset(dev, intel_crtc->pipe);
3239
3240         /*
3241          * There seems to be a race in PCH platform hw (at least on some
3242          * outputs) where an enabled pipe still completes any pageflip right
3243          * away (as if the pipe is off) instead of waiting for vblank. As soon
3244          * as the first vblank happend, everything works as expected. Hence just
3245          * wait for one vblank before returning to avoid strange things
3246          * happening.
3247          */
3248         intel_wait_for_vblank(dev, intel_crtc->pipe);
3249 }
3250
3251 /* IPS only exists on ULT machines and is tied to pipe A. */
3252 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3253 {
3254         return IS_ULT(crtc->base.dev) && crtc->pipe == PIPE_A;
3255 }
3256
3257 static void hsw_enable_ips(struct intel_crtc *crtc)
3258 {
3259         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3260
3261         if (!crtc->config.ips_enabled)
3262                 return;
3263
3264         /* We can only enable IPS after we enable a plane and wait for a vblank.
3265          * We guarantee that the plane is enabled by calling intel_enable_ips
3266          * only after intel_enable_plane. And intel_enable_plane already waits
3267          * for a vblank, so all we need to do here is to enable the IPS bit. */
3268         assert_plane_enabled(dev_priv, crtc->plane);
3269         I915_WRITE(IPS_CTL, IPS_ENABLE);
3270 }
3271
3272 static void hsw_disable_ips(struct intel_crtc *crtc)
3273 {
3274         struct drm_device *dev = crtc->base.dev;
3275         struct drm_i915_private *dev_priv = dev->dev_private;
3276
3277         if (!crtc->config.ips_enabled)
3278                 return;
3279
3280         assert_plane_enabled(dev_priv, crtc->plane);
3281         I915_WRITE(IPS_CTL, 0);
3282
3283         /* We need to wait for a vblank before we can disable the plane. */
3284         intel_wait_for_vblank(dev, crtc->pipe);
3285 }
3286
3287 static void haswell_crtc_enable(struct drm_crtc *crtc)
3288 {
3289         struct drm_device *dev = crtc->dev;
3290         struct drm_i915_private *dev_priv = dev->dev_private;
3291         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3292         struct intel_encoder *encoder;
3293         int pipe = intel_crtc->pipe;
3294         int plane = intel_crtc->plane;
3295
3296         WARN_ON(!crtc->enabled);
3297
3298         if (intel_crtc->active)
3299                 return;
3300
3301         intel_crtc->active = true;
3302
3303         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3304         if (intel_crtc->config.has_pch_encoder)
3305                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3306
3307         intel_update_watermarks(dev);
3308
3309         if (intel_crtc->config.has_pch_encoder)
3310                 dev_priv->display.fdi_link_train(crtc);
3311
3312         for_each_encoder_on_crtc(dev, crtc, encoder)
3313                 if (encoder->pre_enable)
3314                         encoder->pre_enable(encoder);
3315
3316         intel_ddi_enable_pipe_clock(intel_crtc);
3317
3318         /* Enable panel fitting for eDP */
3319         ironlake_pfit_enable(intel_crtc);
3320
3321         /*
3322          * On ILK+ LUT must be loaded before the pipe is running but with
3323          * clocks enabled
3324          */
3325         intel_crtc_load_lut(crtc);
3326
3327         intel_ddi_set_pipe_settings(crtc);
3328         intel_ddi_enable_transcoder_func(crtc);
3329
3330         intel_enable_pipe(dev_priv, pipe,
3331                           intel_crtc->config.has_pch_encoder);
3332         intel_enable_plane(dev_priv, plane, pipe);
3333         intel_enable_planes(crtc);
3334         intel_crtc_update_cursor(crtc, true);
3335
3336         hsw_enable_ips(intel_crtc);
3337
3338         if (intel_crtc->config.has_pch_encoder)
3339                 lpt_pch_enable(crtc);
3340
3341         mutex_lock(&dev->struct_mutex);
3342         intel_update_fbc(dev);
3343         mutex_unlock(&dev->struct_mutex);
3344
3345         for_each_encoder_on_crtc(dev, crtc, encoder)
3346                 encoder->enable(encoder);
3347
3348         /*
3349          * There seems to be a race in PCH platform hw (at least on some
3350          * outputs) where an enabled pipe still completes any pageflip right
3351          * away (as if the pipe is off) instead of waiting for vblank. As soon
3352          * as the first vblank happend, everything works as expected. Hence just
3353          * wait for one vblank before returning to avoid strange things
3354          * happening.
3355          */
3356         intel_wait_for_vblank(dev, intel_crtc->pipe);
3357 }
3358
3359 static void ironlake_pfit_disable(struct intel_crtc *crtc)
3360 {
3361         struct drm_device *dev = crtc->base.dev;
3362         struct drm_i915_private *dev_priv = dev->dev_private;
3363         int pipe = crtc->pipe;
3364
3365         /* To avoid upsetting the power well on haswell only disable the pfit if
3366          * it's in use. The hw state code will make sure we get this right. */
3367         if (crtc->config.pch_pfit.size) {
3368                 I915_WRITE(PF_CTL(pipe), 0);
3369                 I915_WRITE(PF_WIN_POS(pipe), 0);
3370                 I915_WRITE(PF_WIN_SZ(pipe), 0);
3371         }
3372 }
3373
3374 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3375 {
3376         struct drm_device *dev = crtc->dev;
3377         struct drm_i915_private *dev_priv = dev->dev_private;
3378         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3379         struct intel_encoder *encoder;
3380         int pipe = intel_crtc->pipe;
3381         int plane = intel_crtc->plane;
3382         u32 reg, temp;
3383
3384
3385         if (!intel_crtc->active)
3386                 return;
3387
3388         for_each_encoder_on_crtc(dev, crtc, encoder)
3389                 encoder->disable(encoder);
3390
3391         intel_crtc_wait_for_pending_flips(crtc);
3392         drm_vblank_off(dev, pipe);
3393
3394         if (dev_priv->cfb_plane == plane)
3395                 intel_disable_fbc(dev);
3396
3397         intel_crtc_update_cursor(crtc, false);
3398         intel_disable_planes(crtc);
3399         intel_disable_plane(dev_priv, plane, pipe);
3400
3401         if (intel_crtc->config.has_pch_encoder)
3402                 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3403
3404         intel_disable_pipe(dev_priv, pipe);
3405
3406         ironlake_pfit_disable(intel_crtc);
3407
3408         for_each_encoder_on_crtc(dev, crtc, encoder)
3409                 if (encoder->post_disable)
3410                         encoder->post_disable(encoder);
3411
3412         if (intel_crtc->config.has_pch_encoder) {
3413                 ironlake_fdi_disable(crtc);
3414
3415                 ironlake_disable_pch_transcoder(dev_priv, pipe);
3416                 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3417
3418                 if (HAS_PCH_CPT(dev)) {
3419                         /* disable TRANS_DP_CTL */
3420                         reg = TRANS_DP_CTL(pipe);
3421                         temp = I915_READ(reg);
3422                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3423                                   TRANS_DP_PORT_SEL_MASK);
3424                         temp |= TRANS_DP_PORT_SEL_NONE;
3425                         I915_WRITE(reg, temp);
3426
3427                         /* disable DPLL_SEL */
3428                         temp = I915_READ(PCH_DPLL_SEL);
3429                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
3430                         I915_WRITE(PCH_DPLL_SEL, temp);
3431                 }
3432
3433                 /* disable PCH DPLL */
3434                 intel_disable_shared_dpll(intel_crtc);
3435
3436                 ironlake_fdi_pll_disable(intel_crtc);
3437         }
3438
3439         intel_crtc->active = false;
3440         intel_update_watermarks(dev);
3441
3442         mutex_lock(&dev->struct_mutex);
3443         intel_update_fbc(dev);
3444         mutex_unlock(&dev->struct_mutex);
3445 }
3446
3447 static void haswell_crtc_disable(struct drm_crtc *crtc)
3448 {
3449         struct drm_device *dev = crtc->dev;
3450         struct drm_i915_private *dev_priv = dev->dev_private;
3451         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3452         struct intel_encoder *encoder;
3453         int pipe = intel_crtc->pipe;
3454         int plane = intel_crtc->plane;
3455         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3456
3457         if (!intel_crtc->active)
3458                 return;
3459
3460         for_each_encoder_on_crtc(dev, crtc, encoder)
3461                 encoder->disable(encoder);
3462
3463         intel_crtc_wait_for_pending_flips(crtc);
3464         drm_vblank_off(dev, pipe);
3465
3466         /* FBC must be disabled before disabling the plane on HSW. */
3467         if (dev_priv->cfb_plane == plane)
3468                 intel_disable_fbc(dev);
3469
3470         hsw_disable_ips(intel_crtc);
3471
3472         intel_crtc_update_cursor(crtc, false);
3473         intel_disable_planes(crtc);
3474         intel_disable_plane(dev_priv, plane, pipe);
3475
3476         if (intel_crtc->config.has_pch_encoder)
3477                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3478         intel_disable_pipe(dev_priv, pipe);
3479
3480         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3481
3482         ironlake_pfit_disable(intel_crtc);
3483
3484         intel_ddi_disable_pipe_clock(intel_crtc);
3485
3486         for_each_encoder_on_crtc(dev, crtc, encoder)
3487                 if (encoder->post_disable)
3488                         encoder->post_disable(encoder);
3489
3490         if (intel_crtc->config.has_pch_encoder) {
3491                 lpt_disable_pch_transcoder(dev_priv);
3492                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3493                 intel_ddi_fdi_disable(crtc);
3494         }
3495
3496         intel_crtc->active = false;
3497         intel_update_watermarks(dev);
3498
3499         mutex_lock(&dev->struct_mutex);
3500         intel_update_fbc(dev);
3501         mutex_unlock(&dev->struct_mutex);
3502 }
3503
3504 static void ironlake_crtc_off(struct drm_crtc *crtc)
3505 {
3506         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3507         intel_put_shared_dpll(intel_crtc);
3508 }
3509
3510 static void haswell_crtc_off(struct drm_crtc *crtc)
3511 {
3512         intel_ddi_put_crtc_pll(crtc);
3513 }
3514
3515 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3516 {
3517         if (!enable && intel_crtc->overlay) {
3518                 struct drm_device *dev = intel_crtc->base.dev;
3519                 struct drm_i915_private *dev_priv = dev->dev_private;
3520
3521                 mutex_lock(&dev->struct_mutex);
3522                 dev_priv->mm.interruptible = false;
3523                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3524                 dev_priv->mm.interruptible = true;
3525                 mutex_unlock(&dev->struct_mutex);
3526         }
3527
3528         /* Let userspace switch the overlay on again. In most cases userspace
3529          * has to recompute where to put it anyway.
3530          */
3531 }
3532
3533 /**
3534  * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3535  * cursor plane briefly if not already running after enabling the display
3536  * plane.
3537  * This workaround avoids occasional blank screens when self refresh is
3538  * enabled.
3539  */
3540 static void
3541 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3542 {
3543         u32 cntl = I915_READ(CURCNTR(pipe));
3544
3545         if ((cntl & CURSOR_MODE) == 0) {
3546                 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3547
3548                 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3549                 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3550                 intel_wait_for_vblank(dev_priv->dev, pipe);
3551                 I915_WRITE(CURCNTR(pipe), cntl);
3552                 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3553                 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3554         }
3555 }
3556
3557 static void i9xx_pfit_enable(struct intel_crtc *crtc)
3558 {
3559         struct drm_device *dev = crtc->base.dev;
3560         struct drm_i915_private *dev_priv = dev->dev_private;
3561         struct intel_crtc_config *pipe_config = &crtc->config;
3562
3563         if (!crtc->config.gmch_pfit.control)
3564                 return;
3565
3566         /*
3567          * The panel fitter should only be adjusted whilst the pipe is disabled,
3568          * according to register description and PRM.
3569          */
3570         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3571         assert_pipe_disabled(dev_priv, crtc->pipe);
3572
3573         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3574         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
3575
3576         /* Border color in case we don't scale up to the full screen. Black by
3577          * default, change to something else for debugging. */
3578         I915_WRITE(BCLRPAT(crtc->pipe), 0);
3579 }
3580
3581 static void valleyview_crtc_enable(struct drm_crtc *crtc)
3582 {
3583         struct drm_device *dev = crtc->dev;
3584         struct drm_i915_private *dev_priv = dev->dev_private;
3585         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3586         struct intel_encoder *encoder;
3587         int pipe = intel_crtc->pipe;
3588         int plane = intel_crtc->plane;
3589
3590         WARN_ON(!crtc->enabled);
3591
3592         if (intel_crtc->active)
3593                 return;
3594
3595         intel_crtc->active = true;
3596         intel_update_watermarks(dev);
3597
3598         mutex_lock(&dev_priv->dpio_lock);
3599
3600         for_each_encoder_on_crtc(dev, crtc, encoder)
3601                 if (encoder->pre_pll_enable)
3602                         encoder->pre_pll_enable(encoder);
3603
3604         intel_enable_pll(dev_priv, pipe);
3605
3606         for_each_encoder_on_crtc(dev, crtc, encoder)
3607                 if (encoder->pre_enable)
3608                         encoder->pre_enable(encoder);
3609
3610         /* VLV wants encoder enabling _before_ the pipe is up. */
3611         for_each_encoder_on_crtc(dev, crtc, encoder)
3612                 encoder->enable(encoder);
3613
3614         /* Enable panel fitting for eDP */
3615         i9xx_pfit_enable(intel_crtc);
3616
3617         intel_crtc_load_lut(crtc);
3618
3619         intel_enable_pipe(dev_priv, pipe, false);
3620         intel_enable_plane(dev_priv, plane, pipe);
3621         intel_enable_planes(crtc);
3622         intel_crtc_update_cursor(crtc, true);
3623
3624         intel_update_fbc(dev);
3625
3626         mutex_unlock(&dev_priv->dpio_lock);
3627 }
3628
3629 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3630 {
3631         struct drm_device *dev = crtc->dev;
3632         struct drm_i915_private *dev_priv = dev->dev_private;
3633         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3634         struct intel_encoder *encoder;
3635         int pipe = intel_crtc->pipe;
3636         int plane = intel_crtc->plane;
3637
3638         WARN_ON(!crtc->enabled);
3639
3640         if (intel_crtc->active)
3641                 return;
3642
3643         intel_crtc->active = true;
3644         intel_update_watermarks(dev);
3645
3646         intel_enable_pll(dev_priv, pipe);
3647
3648         for_each_encoder_on_crtc(dev, crtc, encoder)
3649                 if (encoder->pre_enable)
3650                         encoder->pre_enable(encoder);
3651
3652         /* Enable panel fitting for LVDS */
3653         i9xx_pfit_enable(intel_crtc);
3654
3655         intel_crtc_load_lut(crtc);
3656
3657         intel_enable_pipe(dev_priv, pipe, false);
3658         intel_enable_plane(dev_priv, plane, pipe);
3659         intel_enable_planes(crtc);
3660         /* The fixup needs to happen before cursor is enabled */
3661         if (IS_G4X(dev))
3662                 g4x_fixup_plane(dev_priv, pipe);
3663         intel_crtc_update_cursor(crtc, true);
3664
3665         /* Give the overlay scaler a chance to enable if it's on this pipe */
3666         intel_crtc_dpms_overlay(intel_crtc, true);
3667
3668         intel_update_fbc(dev);
3669
3670         for_each_encoder_on_crtc(dev, crtc, encoder)
3671                 encoder->enable(encoder);
3672 }
3673
3674 static void i9xx_pfit_disable(struct intel_crtc *crtc)
3675 {
3676         struct drm_device *dev = crtc->base.dev;
3677         struct drm_i915_private *dev_priv = dev->dev_private;
3678
3679         if (!crtc->config.gmch_pfit.control)
3680                 return;
3681
3682         assert_pipe_disabled(dev_priv, crtc->pipe);
3683
3684         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3685                          I915_READ(PFIT_CONTROL));
3686         I915_WRITE(PFIT_CONTROL, 0);
3687 }
3688
3689 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3690 {
3691         struct drm_device *dev = crtc->dev;
3692         struct drm_i915_private *dev_priv = dev->dev_private;
3693         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3694         struct intel_encoder *encoder;
3695         int pipe = intel_crtc->pipe;
3696         int plane = intel_crtc->plane;
3697
3698         if (!intel_crtc->active)
3699                 return;
3700
3701         for_each_encoder_on_crtc(dev, crtc, encoder)
3702                 encoder->disable(encoder);
3703
3704         /* Give the overlay scaler a chance to disable if it's on this pipe */
3705         intel_crtc_wait_for_pending_flips(crtc);
3706         drm_vblank_off(dev, pipe);
3707
3708         if (dev_priv->cfb_plane == plane)
3709                 intel_disable_fbc(dev);
3710
3711         intel_crtc_dpms_overlay(intel_crtc, false);
3712         intel_crtc_update_cursor(crtc, false);
3713         intel_disable_planes(crtc);
3714         intel_disable_plane(dev_priv, plane, pipe);
3715
3716         intel_disable_pipe(dev_priv, pipe);
3717
3718         i9xx_pfit_disable(intel_crtc);
3719
3720         for_each_encoder_on_crtc(dev, crtc, encoder)
3721                 if (encoder->post_disable)
3722                         encoder->post_disable(encoder);
3723
3724         intel_disable_pll(dev_priv, pipe);
3725
3726         intel_crtc->active = false;
3727         intel_update_fbc(dev);
3728         intel_update_watermarks(dev);
3729 }
3730
3731 static void i9xx_crtc_off(struct drm_crtc *crtc)
3732 {
3733 }
3734
3735 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3736                                     bool enabled)
3737 {
3738         struct drm_device *dev = crtc->dev;
3739         struct drm_i915_master_private *master_priv;
3740         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3741         int pipe = intel_crtc->pipe;
3742
3743         if (!dev->primary->master)
3744                 return;
3745
3746         master_priv = dev->primary->master->driver_priv;
3747         if (!master_priv->sarea_priv)
3748                 return;
3749
3750         switch (pipe) {
3751         case 0:
3752                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3753                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3754                 break;
3755         case 1:
3756                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3757                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3758                 break;
3759         default:
3760                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3761                 break;
3762         }
3763 }
3764
3765 /**
3766  * Sets the power management mode of the pipe and plane.
3767  */
3768 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3769 {
3770         struct drm_device *dev = crtc->dev;
3771         struct drm_i915_private *dev_priv = dev->dev_private;
3772         struct intel_encoder *intel_encoder;
3773         bool enable = false;
3774
3775         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3776                 enable |= intel_encoder->connectors_active;
3777
3778         if (enable)
3779                 dev_priv->display.crtc_enable(crtc);
3780         else
3781                 dev_priv->display.crtc_disable(crtc);
3782
3783         intel_crtc_update_sarea(crtc, enable);
3784 }
3785
3786 static void intel_crtc_disable(struct drm_crtc *crtc)
3787 {
3788         struct drm_device *dev = crtc->dev;
3789         struct drm_connector *connector;
3790         struct drm_i915_private *dev_priv = dev->dev_private;
3791         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3792
3793         /* crtc should still be enabled when we disable it. */
3794         WARN_ON(!crtc->enabled);
3795
3796         dev_priv->display.crtc_disable(crtc);
3797         intel_crtc->eld_vld = false;
3798         intel_crtc_update_sarea(crtc, false);
3799         dev_priv->display.off(crtc);
3800
3801         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3802         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3803
3804         if (crtc->fb) {
3805                 mutex_lock(&dev->struct_mutex);
3806                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3807                 mutex_unlock(&dev->struct_mutex);
3808                 crtc->fb = NULL;
3809         }
3810
3811         /* Update computed state. */
3812         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3813                 if (!connector->encoder || !connector->encoder->crtc)
3814                         continue;
3815
3816                 if (connector->encoder->crtc != crtc)
3817                         continue;
3818
3819                 connector->dpms = DRM_MODE_DPMS_OFF;
3820                 to_intel_encoder(connector->encoder)->connectors_active = false;
3821         }
3822 }
3823
3824 void intel_modeset_disable(struct drm_device *dev)
3825 {
3826         struct drm_crtc *crtc;
3827
3828         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3829                 if (crtc->enabled)
3830                         intel_crtc_disable(crtc);
3831         }
3832 }
3833
3834 void intel_encoder_destroy(struct drm_encoder *encoder)
3835 {
3836         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3837
3838         drm_encoder_cleanup(encoder);
3839         kfree(intel_encoder);
3840 }
3841
3842 /* Simple dpms helper for encodres with just one connector, no cloning and only
3843  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3844  * state of the entire output pipe. */
3845 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3846 {
3847         if (mode == DRM_MODE_DPMS_ON) {
3848                 encoder->connectors_active = true;
3849
3850                 intel_crtc_update_dpms(encoder->base.crtc);
3851         } else {
3852                 encoder->connectors_active = false;
3853
3854                 intel_crtc_update_dpms(encoder->base.crtc);
3855         }
3856 }
3857
3858 /* Cross check the actual hw state with our own modeset state tracking (and it's
3859  * internal consistency). */
3860 static void intel_connector_check_state(struct intel_connector *connector)
3861 {
3862         if (connector->get_hw_state(connector)) {
3863                 struct intel_encoder *encoder = connector->encoder;
3864                 struct drm_crtc *crtc;
3865                 bool encoder_enabled;
3866                 enum pipe pipe;
3867
3868                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3869                               connector->base.base.id,
3870                               drm_get_connector_name(&connector->base));
3871
3872                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3873                      "wrong connector dpms state\n");
3874                 WARN(connector->base.encoder != &encoder->base,
3875                      "active connector not linked to encoder\n");
3876                 WARN(!encoder->connectors_active,
3877                      "encoder->connectors_active not set\n");
3878
3879                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3880                 WARN(!encoder_enabled, "encoder not enabled\n");
3881                 if (WARN_ON(!encoder->base.crtc))
3882                         return;
3883
3884                 crtc = encoder->base.crtc;
3885
3886                 WARN(!crtc->enabled, "crtc not enabled\n");
3887                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3888                 WARN(pipe != to_intel_crtc(crtc)->pipe,
3889                      "encoder active on the wrong pipe\n");
3890         }
3891 }
3892
3893 /* Even simpler default implementation, if there's really no special case to
3894  * consider. */
3895 void intel_connector_dpms(struct drm_connector *connector, int mode)
3896 {
3897         struct intel_encoder *encoder = intel_attached_encoder(connector);
3898
3899         /* All the simple cases only support two dpms states. */
3900         if (mode != DRM_MODE_DPMS_ON)
3901                 mode = DRM_MODE_DPMS_OFF;
3902
3903         if (mode == connector->dpms)
3904                 return;
3905
3906         connector->dpms = mode;
3907
3908         /* Only need to change hw state when actually enabled */
3909         if (encoder->base.crtc)
3910                 intel_encoder_dpms(encoder, mode);
3911         else
3912                 WARN_ON(encoder->connectors_active != false);
3913
3914         intel_modeset_check_state(connector->dev);
3915 }
3916
3917 /* Simple connector->get_hw_state implementation for encoders that support only
3918  * one connector and no cloning and hence the encoder state determines the state
3919  * of the connector. */
3920 bool intel_connector_get_hw_state(struct intel_connector *connector)
3921 {
3922         enum pipe pipe = 0;
3923         struct intel_encoder *encoder = connector->encoder;
3924
3925         return encoder->get_hw_state(encoder, &pipe);
3926 }
3927
3928 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
3929                                      struct intel_crtc_config *pipe_config)
3930 {
3931         struct drm_i915_private *dev_priv = dev->dev_private;
3932         struct intel_crtc *pipe_B_crtc =
3933                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3934
3935         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
3936                       pipe_name(pipe), pipe_config->fdi_lanes);
3937         if (pipe_config->fdi_lanes > 4) {
3938                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
3939                               pipe_name(pipe), pipe_config->fdi_lanes);
3940                 return false;
3941         }
3942
3943         if (IS_HASWELL(dev)) {
3944                 if (pipe_config->fdi_lanes > 2) {
3945                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
3946                                       pipe_config->fdi_lanes);
3947                         return false;
3948                 } else {
3949                         return true;
3950                 }
3951         }
3952
3953         if (INTEL_INFO(dev)->num_pipes == 2)
3954                 return true;
3955
3956         /* Ivybridge 3 pipe is really complicated */
3957         switch (pipe) {
3958         case PIPE_A:
3959                 return true;
3960         case PIPE_B:
3961                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
3962                     pipe_config->fdi_lanes > 2) {
3963                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
3964                                       pipe_name(pipe), pipe_config->fdi_lanes);
3965                         return false;
3966                 }
3967                 return true;
3968         case PIPE_C:
3969                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
3970                     pipe_B_crtc->config.fdi_lanes <= 2) {
3971                         if (pipe_config->fdi_lanes > 2) {
3972                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
3973                                               pipe_name(pipe), pipe_config->fdi_lanes);
3974                                 return false;
3975                         }
3976                 } else {
3977                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
3978                         return false;
3979                 }
3980                 return true;
3981         default:
3982                 BUG();
3983         }
3984 }
3985
3986 #define RETRY 1
3987 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
3988                                        struct intel_crtc_config *pipe_config)
3989 {
3990         struct drm_device *dev = intel_crtc->base.dev;
3991         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
3992         int lane, link_bw, fdi_dotclock;
3993         bool setup_ok, needs_recompute = false;
3994
3995 retry:
3996         /* FDI is a binary signal running at ~2.7GHz, encoding
3997          * each output octet as 10 bits. The actual frequency
3998          * is stored as a divider into a 100MHz clock, and the
3999          * mode pixel clock is stored in units of 1KHz.
4000          * Hence the bw of each lane in terms of the mode signal
4001          * is:
4002          */
4003         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4004
4005         fdi_dotclock = adjusted_mode->clock;
4006         fdi_dotclock /= pipe_config->pixel_multiplier;
4007
4008         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
4009                                            pipe_config->pipe_bpp);
4010
4011         pipe_config->fdi_lanes = lane;
4012
4013         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4014                                link_bw, &pipe_config->fdi_m_n);
4015
4016         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4017                                             intel_crtc->pipe, pipe_config);
4018         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4019                 pipe_config->pipe_bpp -= 2*3;
4020                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4021                               pipe_config->pipe_bpp);
4022                 needs_recompute = true;
4023                 pipe_config->bw_constrained = true;
4024
4025                 goto retry;
4026         }
4027
4028         if (needs_recompute)
4029                 return RETRY;
4030
4031         return setup_ok ? 0 : -EINVAL;
4032 }
4033
4034 static void hsw_compute_ips_config(struct intel_crtc *crtc,
4035                                    struct intel_crtc_config *pipe_config)
4036 {
4037         pipe_config->ips_enabled = i915_enable_ips &&
4038                                    hsw_crtc_supports_ips(crtc) &&
4039                                    pipe_config->pipe_bpp == 24;
4040 }
4041
4042 static int intel_crtc_compute_config(struct intel_crtc *crtc,
4043                                      struct intel_crtc_config *pipe_config)
4044 {
4045         struct drm_device *dev = crtc->base.dev;
4046         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4047
4048         if (HAS_PCH_SPLIT(dev)) {
4049                 /* FDI link clock is fixed at 2.7G */
4050                 if (pipe_config->requested_mode.clock * 3
4051                     > IRONLAKE_FDI_FREQ * 4)
4052                         return -EINVAL;
4053         }
4054
4055         /* All interlaced capable intel hw wants timings in frames. Note though
4056          * that intel_lvds_mode_fixup does some funny tricks with the crtc
4057          * timings, so we need to be careful not to clobber these.*/
4058         if (!pipe_config->timings_set)
4059                 drm_mode_set_crtcinfo(adjusted_mode, 0);
4060
4061         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4062          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4063          */
4064         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4065                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4066                 return -EINVAL;
4067
4068         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4069                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4070         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4071                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4072                  * for lvds. */
4073                 pipe_config->pipe_bpp = 8*3;
4074         }
4075
4076         if (IS_HASWELL(dev))
4077                 hsw_compute_ips_config(crtc, pipe_config);
4078
4079         /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4080          * clock survives for now. */
4081         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4082                 pipe_config->shared_dpll = crtc->config.shared_dpll;
4083
4084         if (pipe_config->has_pch_encoder)
4085                 return ironlake_fdi_compute_config(crtc, pipe_config);
4086
4087         return 0;
4088 }
4089
4090 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4091 {
4092         return 400000; /* FIXME */
4093 }
4094
4095 static int i945_get_display_clock_speed(struct drm_device *dev)
4096 {
4097         return 400000;
4098 }
4099
4100 static int i915_get_display_clock_speed(struct drm_device *dev)
4101 {
4102         return 333000;
4103 }
4104
4105 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4106 {
4107         return 200000;
4108 }
4109
4110 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4111 {
4112         u16 gcfgc = 0;
4113
4114         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4115
4116         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4117                 return 133000;
4118         else {
4119                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4120                 case GC_DISPLAY_CLOCK_333_MHZ:
4121                         return 333000;
4122                 default:
4123                 case GC_DISPLAY_CLOCK_190_200_MHZ:
4124                         return 190000;
4125                 }
4126         }
4127 }
4128
4129 static int i865_get_display_clock_speed(struct drm_device *dev)
4130 {
4131         return 266000;
4132 }
4133
4134 static int i855_get_display_clock_speed(struct drm_device *dev)
4135 {
4136         u16 hpllcc = 0;
4137         /* Assume that the hardware is in the high speed state.  This
4138          * should be the default.
4139          */
4140         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4141         case GC_CLOCK_133_200:
4142         case GC_CLOCK_100_200:
4143                 return 200000;
4144         case GC_CLOCK_166_250:
4145                 return 250000;
4146         case GC_CLOCK_100_133:
4147                 return 133000;
4148         }
4149
4150         /* Shouldn't happen */
4151         return 0;
4152 }
4153
4154 static int i830_get_display_clock_speed(struct drm_device *dev)
4155 {
4156         return 133000;
4157 }
4158
4159 static void
4160 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
4161 {
4162         while (*num > DATA_LINK_M_N_MASK ||
4163                *den > DATA_LINK_M_N_MASK) {
4164                 *num >>= 1;
4165                 *den >>= 1;
4166         }
4167 }
4168
4169 static void compute_m_n(unsigned int m, unsigned int n,
4170                         uint32_t *ret_m, uint32_t *ret_n)
4171 {
4172         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4173         *ret_m = div_u64((uint64_t) m * *ret_n, n);
4174         intel_reduce_m_n_ratio(ret_m, ret_n);
4175 }
4176
4177 void
4178 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4179                        int pixel_clock, int link_clock,
4180                        struct intel_link_m_n *m_n)
4181 {
4182         m_n->tu = 64;
4183
4184         compute_m_n(bits_per_pixel * pixel_clock,
4185                     link_clock * nlanes * 8,
4186                     &m_n->gmch_m, &m_n->gmch_n);
4187
4188         compute_m_n(pixel_clock, link_clock,
4189                     &m_n->link_m, &m_n->link_n);
4190 }
4191
4192 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4193 {
4194         if (i915_panel_use_ssc >= 0)
4195                 return i915_panel_use_ssc != 0;
4196         return dev_priv->vbt.lvds_use_ssc
4197                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4198 }
4199
4200 static int vlv_get_refclk(struct drm_crtc *crtc)
4201 {
4202         struct drm_device *dev = crtc->dev;
4203         struct drm_i915_private *dev_priv = dev->dev_private;
4204         int refclk = 27000; /* for DP & HDMI */
4205
4206         return 100000; /* only one validated so far */
4207
4208         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4209                 refclk = 96000;
4210         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4211                 if (intel_panel_use_ssc(dev_priv))
4212                         refclk = 100000;
4213                 else
4214                         refclk = 96000;
4215         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4216                 refclk = 100000;
4217         }
4218
4219         return refclk;
4220 }
4221
4222 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4223 {
4224         struct drm_device *dev = crtc->dev;
4225         struct drm_i915_private *dev_priv = dev->dev_private;
4226         int refclk;
4227
4228         if (IS_VALLEYVIEW(dev)) {
4229                 refclk = vlv_get_refclk(crtc);
4230         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4231             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4232                 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
4233                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4234                               refclk / 1000);
4235         } else if (!IS_GEN2(dev)) {
4236                 refclk = 96000;
4237         } else {
4238                 refclk = 48000;
4239         }
4240
4241         return refclk;
4242 }
4243
4244 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4245 {
4246         return (1 << dpll->n) << 16 | dpll->m2;
4247 }
4248
4249 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4250 {
4251         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4252 }
4253
4254 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4255                                      intel_clock_t *reduced_clock)
4256 {
4257         struct drm_device *dev = crtc->base.dev;
4258         struct drm_i915_private *dev_priv = dev->dev_private;
4259         int pipe = crtc->pipe;
4260         u32 fp, fp2 = 0;
4261
4262         if (IS_PINEVIEW(dev)) {
4263                 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
4264                 if (reduced_clock)
4265                         fp2 = pnv_dpll_compute_fp(reduced_clock);
4266         } else {
4267                 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
4268                 if (reduced_clock)
4269                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
4270         }
4271
4272         I915_WRITE(FP0(pipe), fp);
4273
4274         crtc->lowfreq_avail = false;
4275         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4276             reduced_clock && i915_powersave) {
4277                 I915_WRITE(FP1(pipe), fp2);
4278                 crtc->lowfreq_avail = true;
4279         } else {
4280                 I915_WRITE(FP1(pipe), fp);
4281         }
4282 }
4283
4284 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4285 {
4286         u32 reg_val;
4287
4288         /*
4289          * PLLB opamp always calibrates to max value of 0x3f, force enable it
4290          * and set it to a reasonable value instead.
4291          */
4292         reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
4293         reg_val &= 0xffffff00;
4294         reg_val |= 0x00000030;
4295         vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4296
4297         reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
4298         reg_val &= 0x8cffffff;
4299         reg_val = 0x8c000000;
4300         vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4301
4302         reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
4303         reg_val &= 0xffffff00;
4304         vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4305
4306         reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
4307         reg_val &= 0x00ffffff;
4308         reg_val |= 0xb0000000;
4309         vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4310 }
4311
4312 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4313                                          struct intel_link_m_n *m_n)
4314 {
4315         struct drm_device *dev = crtc->base.dev;
4316         struct drm_i915_private *dev_priv = dev->dev_private;
4317         int pipe = crtc->pipe;
4318
4319         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4320         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4321         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4322         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
4323 }
4324
4325 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4326                                          struct intel_link_m_n *m_n)
4327 {
4328         struct drm_device *dev = crtc->base.dev;
4329         struct drm_i915_private *dev_priv = dev->dev_private;
4330         int pipe = crtc->pipe;
4331         enum transcoder transcoder = crtc->config.cpu_transcoder;
4332
4333         if (INTEL_INFO(dev)->gen >= 5) {
4334                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4335                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4336                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4337                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4338         } else {
4339                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4340                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4341                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4342                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
4343         }
4344 }
4345
4346 static void intel_dp_set_m_n(struct intel_crtc *crtc)
4347 {
4348         if (crtc->config.has_pch_encoder)
4349                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4350         else
4351                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4352 }
4353
4354 static void vlv_update_pll(struct intel_crtc *crtc)
4355 {
4356         struct drm_device *dev = crtc->base.dev;
4357         struct drm_i915_private *dev_priv = dev->dev_private;
4358         struct intel_encoder *encoder;
4359         int pipe = crtc->pipe;
4360         u32 dpll, mdiv;
4361         u32 bestn, bestm1, bestm2, bestp1, bestp2;
4362         bool is_hdmi;
4363         u32 coreclk, reg_val, dpll_md;
4364
4365         mutex_lock(&dev_priv->dpio_lock);
4366
4367         is_hdmi = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4368
4369         bestn = crtc->config.dpll.n;
4370         bestm1 = crtc->config.dpll.m1;
4371         bestm2 = crtc->config.dpll.m2;
4372         bestp1 = crtc->config.dpll.p1;
4373         bestp2 = crtc->config.dpll.p2;
4374
4375         /* See eDP HDMI DPIO driver vbios notes doc */
4376
4377         /* PLL B needs special handling */
4378         if (pipe)
4379                 vlv_pllb_recal_opamp(dev_priv);
4380
4381         /* Set up Tx target for periodic Rcomp update */
4382         vlv_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
4383
4384         /* Disable target IRef on PLL */
4385         reg_val = vlv_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
4386         reg_val &= 0x00ffffff;
4387         vlv_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
4388
4389         /* Disable fast lock */
4390         vlv_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
4391
4392         /* Set idtafcrecal before PLL is enabled */
4393         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4394         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4395         mdiv |= ((bestn << DPIO_N_SHIFT));
4396         mdiv |= (1 << DPIO_K_SHIFT);
4397
4398         /*
4399          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4400          * but we don't support that).
4401          * Note: don't use the DAC post divider as it seems unstable.
4402          */
4403         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
4404         vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4405
4406         mdiv |= DPIO_ENABLE_CALIBRATION;
4407         vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4408
4409         /* Set HBR and RBR LPF coefficients */
4410         if (crtc->config.port_clock == 162000 ||
4411             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4412                 vlv_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
4413                                  0x005f0021);
4414         else
4415                 vlv_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
4416                                  0x00d0000f);
4417
4418         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4419             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4420                 /* Use SSC source */
4421                 if (!pipe)
4422                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4423                                          0x0df40000);
4424                 else
4425                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4426                                          0x0df70000);
4427         } else { /* HDMI or VGA */
4428                 /* Use bend source */
4429                 if (!pipe)
4430                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4431                                          0x0df70000);
4432                 else
4433                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4434                                          0x0df40000);
4435         }
4436
4437         coreclk = vlv_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
4438         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4439         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4440             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4441                 coreclk |= 0x01000000;
4442         vlv_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
4443
4444         vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
4445
4446         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4447                 if (encoder->pre_pll_enable)
4448                         encoder->pre_pll_enable(encoder);
4449
4450         /* Enable DPIO clock input */
4451         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4452                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4453         if (pipe)
4454                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
4455
4456         dpll |= DPLL_VCO_ENABLE;
4457         I915_WRITE(DPLL(pipe), dpll);
4458         POSTING_READ(DPLL(pipe));
4459         udelay(150);
4460
4461         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4462                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4463
4464         dpll_md = (crtc->config.pixel_multiplier - 1)
4465                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4466         I915_WRITE(DPLL_MD(pipe), dpll_md);
4467         POSTING_READ(DPLL_MD(pipe));
4468
4469         if (crtc->config.has_dp_encoder)
4470                 intel_dp_set_m_n(crtc);
4471
4472         mutex_unlock(&dev_priv->dpio_lock);
4473 }
4474
4475 static void i9xx_update_pll(struct intel_crtc *crtc,
4476                             intel_clock_t *reduced_clock,
4477                             int num_connectors)
4478 {
4479         struct drm_device *dev = crtc->base.dev;
4480         struct drm_i915_private *dev_priv = dev->dev_private;
4481         struct intel_encoder *encoder;
4482         int pipe = crtc->pipe;
4483         u32 dpll;
4484         bool is_sdvo;
4485         struct dpll *clock = &crtc->config.dpll;
4486
4487         i9xx_update_pll_dividers(crtc, reduced_clock);
4488
4489         is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4490                 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4491
4492         dpll = DPLL_VGA_MODE_DIS;
4493
4494         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
4495                 dpll |= DPLLB_MODE_LVDS;
4496         else
4497                 dpll |= DPLLB_MODE_DAC_SERIAL;
4498
4499         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
4500                 dpll |= (crtc->config.pixel_multiplier - 1)
4501                         << SDVO_MULTIPLIER_SHIFT_HIRES;
4502         }
4503
4504         if (is_sdvo)
4505                 dpll |= DPLL_DVO_HIGH_SPEED;
4506
4507         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4508                 dpll |= DPLL_DVO_HIGH_SPEED;
4509
4510         /* compute bitmask from p1 value */
4511         if (IS_PINEVIEW(dev))
4512                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4513         else {
4514                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4515                 if (IS_G4X(dev) && reduced_clock)
4516                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4517         }
4518         switch (clock->p2) {
4519         case 5:
4520                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4521                 break;
4522         case 7:
4523                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4524                 break;
4525         case 10:
4526                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4527                 break;
4528         case 14:
4529                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4530                 break;
4531         }
4532         if (INTEL_INFO(dev)->gen >= 4)
4533                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4534
4535         if (crtc->config.sdvo_tv_clock)
4536                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4537         else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4538                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4539                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4540         else
4541                 dpll |= PLL_REF_INPUT_DREFCLK;
4542
4543         dpll |= DPLL_VCO_ENABLE;
4544         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4545         POSTING_READ(DPLL(pipe));
4546         udelay(150);
4547
4548         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4549                 if (encoder->pre_pll_enable)
4550                         encoder->pre_pll_enable(encoder);
4551
4552         if (crtc->config.has_dp_encoder)
4553                 intel_dp_set_m_n(crtc);
4554
4555         I915_WRITE(DPLL(pipe), dpll);
4556
4557         /* Wait for the clocks to stabilize. */
4558         POSTING_READ(DPLL(pipe));
4559         udelay(150);
4560
4561         if (INTEL_INFO(dev)->gen >= 4) {
4562                 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4563                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4564                 I915_WRITE(DPLL_MD(pipe), dpll_md);
4565         } else {
4566                 /* The pixel multiplier can only be updated once the
4567                  * DPLL is enabled and the clocks are stable.
4568                  *
4569                  * So write it again.
4570                  */
4571                 I915_WRITE(DPLL(pipe), dpll);
4572         }
4573 }
4574
4575 static void i8xx_update_pll(struct intel_crtc *crtc,
4576                             intel_clock_t *reduced_clock,
4577                             int num_connectors)
4578 {
4579         struct drm_device *dev = crtc->base.dev;
4580         struct drm_i915_private *dev_priv = dev->dev_private;
4581         struct intel_encoder *encoder;
4582         int pipe = crtc->pipe;
4583         u32 dpll;
4584         struct dpll *clock = &crtc->config.dpll;
4585
4586         i9xx_update_pll_dividers(crtc, reduced_clock);
4587
4588         dpll = DPLL_VGA_MODE_DIS;
4589
4590         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
4591                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4592         } else {
4593                 if (clock->p1 == 2)
4594                         dpll |= PLL_P1_DIVIDE_BY_TWO;
4595                 else
4596                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4597                 if (clock->p2 == 4)
4598                         dpll |= PLL_P2_DIVIDE_BY_4;
4599         }
4600
4601         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4602                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4603                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4604         else
4605                 dpll |= PLL_REF_INPUT_DREFCLK;
4606
4607         dpll |= DPLL_VCO_ENABLE;
4608         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4609         POSTING_READ(DPLL(pipe));
4610         udelay(150);
4611
4612         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4613                 if (encoder->pre_pll_enable)
4614                         encoder->pre_pll_enable(encoder);
4615
4616         I915_WRITE(DPLL(pipe), dpll);
4617
4618         /* Wait for the clocks to stabilize. */
4619         POSTING_READ(DPLL(pipe));
4620         udelay(150);
4621
4622         /* The pixel multiplier can only be updated once the
4623          * DPLL is enabled and the clocks are stable.
4624          *
4625          * So write it again.
4626          */
4627         I915_WRITE(DPLL(pipe), dpll);
4628 }
4629
4630 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
4631 {
4632         struct drm_device *dev = intel_crtc->base.dev;
4633         struct drm_i915_private *dev_priv = dev->dev_private;
4634         enum pipe pipe = intel_crtc->pipe;
4635         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4636         struct drm_display_mode *adjusted_mode =
4637                 &intel_crtc->config.adjusted_mode;
4638         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4639         uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4640
4641         /* We need to be careful not to changed the adjusted mode, for otherwise
4642          * the hw state checker will get angry at the mismatch. */
4643         crtc_vtotal = adjusted_mode->crtc_vtotal;
4644         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
4645
4646         if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4647                 /* the chip adds 2 halflines automatically */
4648                 crtc_vtotal -= 1;
4649                 crtc_vblank_end -= 1;
4650                 vsyncshift = adjusted_mode->crtc_hsync_start
4651                              - adjusted_mode->crtc_htotal / 2;
4652         } else {
4653                 vsyncshift = 0;
4654         }
4655
4656         if (INTEL_INFO(dev)->gen > 3)
4657                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4658
4659         I915_WRITE(HTOTAL(cpu_transcoder),
4660                    (adjusted_mode->crtc_hdisplay - 1) |
4661                    ((adjusted_mode->crtc_htotal - 1) << 16));
4662         I915_WRITE(HBLANK(cpu_transcoder),
4663                    (adjusted_mode->crtc_hblank_start - 1) |
4664                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4665         I915_WRITE(HSYNC(cpu_transcoder),
4666                    (adjusted_mode->crtc_hsync_start - 1) |
4667                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4668
4669         I915_WRITE(VTOTAL(cpu_transcoder),
4670                    (adjusted_mode->crtc_vdisplay - 1) |
4671                    ((crtc_vtotal - 1) << 16));
4672         I915_WRITE(VBLANK(cpu_transcoder),
4673                    (adjusted_mode->crtc_vblank_start - 1) |
4674                    ((crtc_vblank_end - 1) << 16));
4675         I915_WRITE(VSYNC(cpu_transcoder),
4676                    (adjusted_mode->crtc_vsync_start - 1) |
4677                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4678
4679         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4680          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4681          * documented on the DDI_FUNC_CTL register description, EDP Input Select
4682          * bits. */
4683         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4684             (pipe == PIPE_B || pipe == PIPE_C))
4685                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4686
4687         /* pipesrc controls the size that is scaled from, which should
4688          * always be the user's requested size.
4689          */
4690         I915_WRITE(PIPESRC(pipe),
4691                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4692 }
4693
4694 static void intel_get_pipe_timings(struct intel_crtc *crtc,
4695                                    struct intel_crtc_config *pipe_config)
4696 {
4697         struct drm_device *dev = crtc->base.dev;
4698         struct drm_i915_private *dev_priv = dev->dev_private;
4699         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4700         uint32_t tmp;
4701
4702         tmp = I915_READ(HTOTAL(cpu_transcoder));
4703         pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4704         pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4705         tmp = I915_READ(HBLANK(cpu_transcoder));
4706         pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4707         pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4708         tmp = I915_READ(HSYNC(cpu_transcoder));
4709         pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4710         pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4711
4712         tmp = I915_READ(VTOTAL(cpu_transcoder));
4713         pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4714         pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4715         tmp = I915_READ(VBLANK(cpu_transcoder));
4716         pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4717         pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4718         tmp = I915_READ(VSYNC(cpu_transcoder));
4719         pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4720         pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4721
4722         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4723                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4724                 pipe_config->adjusted_mode.crtc_vtotal += 1;
4725                 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4726         }
4727
4728         tmp = I915_READ(PIPESRC(crtc->pipe));
4729         pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4730         pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4731 }
4732
4733 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4734 {
4735         struct drm_device *dev = intel_crtc->base.dev;
4736         struct drm_i915_private *dev_priv = dev->dev_private;
4737         uint32_t pipeconf;
4738
4739         pipeconf = 0;
4740
4741         if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4742                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4743                  * core speed.
4744                  *
4745                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4746                  * pipe == 0 check?
4747                  */
4748                 if (intel_crtc->config.requested_mode.clock >
4749                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4750                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4751         }
4752
4753         /* only g4x and later have fancy bpc/dither controls */
4754         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
4755                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4756                 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4757                         pipeconf |= PIPECONF_DITHER_EN |
4758                                     PIPECONF_DITHER_TYPE_SP;
4759
4760                 switch (intel_crtc->config.pipe_bpp) {
4761                 case 18:
4762                         pipeconf |= PIPECONF_6BPC;
4763                         break;
4764                 case 24:
4765                         pipeconf |= PIPECONF_8BPC;
4766                         break;
4767                 case 30:
4768                         pipeconf |= PIPECONF_10BPC;
4769                         break;
4770                 default:
4771                         /* Case prevented by intel_choose_pipe_bpp_dither. */
4772                         BUG();
4773                 }
4774         }
4775
4776         if (HAS_PIPE_CXSR(dev)) {
4777                 if (intel_crtc->lowfreq_avail) {
4778                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4779                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4780                 } else {
4781                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4782                 }
4783         }
4784
4785         if (!IS_GEN2(dev) &&
4786             intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4787                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4788         else
4789                 pipeconf |= PIPECONF_PROGRESSIVE;
4790
4791         if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
4792                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4793
4794         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4795         POSTING_READ(PIPECONF(intel_crtc->pipe));
4796 }
4797
4798 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4799                               int x, int y,
4800                               struct drm_framebuffer *fb)
4801 {
4802         struct drm_device *dev = crtc->dev;
4803         struct drm_i915_private *dev_priv = dev->dev_private;
4804         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4805         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4806         int pipe = intel_crtc->pipe;
4807         int plane = intel_crtc->plane;
4808         int refclk, num_connectors = 0;
4809         intel_clock_t clock, reduced_clock;
4810         u32 dspcntr;
4811         bool ok, has_reduced_clock = false;
4812         bool is_lvds = false;
4813         struct intel_encoder *encoder;
4814         const intel_limit_t *limit;
4815         int ret;
4816
4817         for_each_encoder_on_crtc(dev, crtc, encoder) {
4818                 switch (encoder->type) {
4819                 case INTEL_OUTPUT_LVDS:
4820                         is_lvds = true;
4821                         break;
4822                 }
4823
4824                 num_connectors++;
4825         }
4826
4827         refclk = i9xx_get_refclk(crtc, num_connectors);
4828
4829         /*
4830          * Returns a set of divisors for the desired target clock with the given
4831          * refclk, or FALSE.  The returned values represent the clock equation:
4832          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4833          */
4834         limit = intel_limit(crtc, refclk);
4835         ok = dev_priv->display.find_dpll(limit, crtc,
4836                                          intel_crtc->config.port_clock,
4837                                          refclk, NULL, &clock);
4838         if (!ok && !intel_crtc->config.clock_set) {
4839                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4840                 return -EINVAL;
4841         }
4842
4843         /* Ensure that the cursor is valid for the new mode before changing... */
4844         intel_crtc_update_cursor(crtc, true);
4845
4846         if (is_lvds && dev_priv->lvds_downclock_avail) {
4847                 /*
4848                  * Ensure we match the reduced clock's P to the target clock.
4849                  * If the clocks don't match, we can't switch the display clock
4850                  * by using the FP0/FP1. In such case we will disable the LVDS
4851                  * downclock feature.
4852                 */
4853                 has_reduced_clock =
4854                         dev_priv->display.find_dpll(limit, crtc,
4855                                                     dev_priv->lvds_downclock,
4856                                                     refclk, &clock,
4857                                                     &reduced_clock);
4858         }
4859         /* Compat-code for transition, will disappear. */
4860         if (!intel_crtc->config.clock_set) {
4861                 intel_crtc->config.dpll.n = clock.n;
4862                 intel_crtc->config.dpll.m1 = clock.m1;
4863                 intel_crtc->config.dpll.m2 = clock.m2;
4864                 intel_crtc->config.dpll.p1 = clock.p1;
4865                 intel_crtc->config.dpll.p2 = clock.p2;
4866         }
4867
4868         if (IS_GEN2(dev))
4869                 i8xx_update_pll(intel_crtc,
4870                                 has_reduced_clock ? &reduced_clock : NULL,
4871                                 num_connectors);
4872         else if (IS_VALLEYVIEW(dev))
4873                 vlv_update_pll(intel_crtc);
4874         else
4875                 i9xx_update_pll(intel_crtc,
4876                                 has_reduced_clock ? &reduced_clock : NULL,
4877                                 num_connectors);
4878
4879         /* Set up the display plane register */
4880         dspcntr = DISPPLANE_GAMMA_ENABLE;
4881
4882         if (!IS_VALLEYVIEW(dev)) {
4883                 if (pipe == 0)
4884                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4885                 else
4886                         dspcntr |= DISPPLANE_SEL_PIPE_B;
4887         }
4888
4889         intel_set_pipe_timings(intel_crtc);
4890
4891         /* pipesrc and dspsize control the size that is scaled from,
4892          * which should always be the user's requested size.
4893          */
4894         I915_WRITE(DSPSIZE(plane),
4895                    ((mode->vdisplay - 1) << 16) |
4896                    (mode->hdisplay - 1));
4897         I915_WRITE(DSPPOS(plane), 0);
4898
4899         i9xx_set_pipeconf(intel_crtc);
4900
4901         I915_WRITE(DSPCNTR(plane), dspcntr);
4902         POSTING_READ(DSPCNTR(plane));
4903
4904         ret = intel_pipe_set_base(crtc, x, y, fb);
4905
4906         intel_update_watermarks(dev);
4907
4908         return ret;
4909 }
4910
4911 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
4912                                  struct intel_crtc_config *pipe_config)
4913 {
4914         struct drm_device *dev = crtc->base.dev;
4915         struct drm_i915_private *dev_priv = dev->dev_private;
4916         uint32_t tmp;
4917
4918         tmp = I915_READ(PFIT_CONTROL);
4919
4920         if (INTEL_INFO(dev)->gen < 4) {
4921                 if (crtc->pipe != PIPE_B)
4922                         return;
4923
4924                 /* gen2/3 store dither state in pfit control, needs to match */
4925                 pipe_config->gmch_pfit.control = tmp & PANEL_8TO6_DITHER_ENABLE;
4926         } else {
4927                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
4928                         return;
4929         }
4930
4931         if (!(tmp & PFIT_ENABLE))
4932                 return;
4933
4934         pipe_config->gmch_pfit.control = I915_READ(PFIT_CONTROL);
4935         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
4936         if (INTEL_INFO(dev)->gen < 5)
4937                 pipe_config->gmch_pfit.lvds_border_bits =
4938                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
4939 }
4940
4941 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4942                                  struct intel_crtc_config *pipe_config)
4943 {
4944         struct drm_device *dev = crtc->base.dev;
4945         struct drm_i915_private *dev_priv = dev->dev_private;
4946         uint32_t tmp;
4947
4948         pipe_config->cpu_transcoder = crtc->pipe;
4949         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
4950
4951         tmp = I915_READ(PIPECONF(crtc->pipe));
4952         if (!(tmp & PIPECONF_ENABLE))
4953                 return false;
4954
4955         intel_get_pipe_timings(crtc, pipe_config);
4956
4957         i9xx_get_pfit_config(crtc, pipe_config);
4958
4959         if (INTEL_INFO(dev)->gen >= 4) {
4960                 tmp = I915_READ(DPLL_MD(crtc->pipe));
4961                 pipe_config->pixel_multiplier =
4962                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
4963                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
4964         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
4965                 tmp = I915_READ(DPLL(crtc->pipe));
4966                 pipe_config->pixel_multiplier =
4967                         ((tmp & SDVO_MULTIPLIER_MASK)
4968                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
4969         } else {
4970                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
4971                  * port and will be fixed up in the encoder->get_config
4972                  * function. */
4973                 pipe_config->pixel_multiplier = 1;
4974         }
4975
4976         return true;
4977 }
4978
4979 static void ironlake_init_pch_refclk(struct drm_device *dev)
4980 {
4981         struct drm_i915_private *dev_priv = dev->dev_private;
4982         struct drm_mode_config *mode_config = &dev->mode_config;
4983         struct intel_encoder *encoder;
4984         u32 val, final;
4985         bool has_lvds = false;
4986         bool has_cpu_edp = false;
4987         bool has_panel = false;
4988         bool has_ck505 = false;
4989         bool can_ssc = false;
4990
4991         /* We need to take the global config into account */
4992         list_for_each_entry(encoder, &mode_config->encoder_list,
4993                             base.head) {
4994                 switch (encoder->type) {
4995                 case INTEL_OUTPUT_LVDS:
4996                         has_panel = true;
4997                         has_lvds = true;
4998                         break;
4999                 case INTEL_OUTPUT_EDP:
5000                         has_panel = true;
5001                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5002                                 has_cpu_edp = true;
5003                         break;
5004                 }
5005         }
5006
5007         if (HAS_PCH_IBX(dev)) {
5008                 has_ck505 = dev_priv->vbt.display_clock_mode;
5009                 can_ssc = has_ck505;
5010         } else {
5011                 has_ck505 = false;
5012                 can_ssc = true;
5013         }
5014
5015         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5016                       has_panel, has_lvds, has_ck505);
5017
5018         /* Ironlake: try to setup display ref clock before DPLL
5019          * enabling. This is only under driver's control after
5020          * PCH B stepping, previous chipset stepping should be
5021          * ignoring this setting.
5022          */
5023         val = I915_READ(PCH_DREF_CONTROL);
5024
5025         /* As we must carefully and slowly disable/enable each source in turn,
5026          * compute the final state we want first and check if we need to
5027          * make any changes at all.
5028          */
5029         final = val;
5030         final &= ~DREF_NONSPREAD_SOURCE_MASK;
5031         if (has_ck505)
5032                 final |= DREF_NONSPREAD_CK505_ENABLE;
5033         else
5034                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5035
5036         final &= ~DREF_SSC_SOURCE_MASK;
5037         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5038         final &= ~DREF_SSC1_ENABLE;
5039
5040         if (has_panel) {
5041                 final |= DREF_SSC_SOURCE_ENABLE;
5042
5043                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5044                         final |= DREF_SSC1_ENABLE;
5045
5046                 if (has_cpu_edp) {
5047                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
5048                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5049                         else
5050                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5051                 } else
5052                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5053         } else {
5054                 final |= DREF_SSC_SOURCE_DISABLE;
5055                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5056         }
5057
5058         if (final == val)
5059                 return;
5060
5061         /* Always enable nonspread source */
5062         val &= ~DREF_NONSPREAD_SOURCE_MASK;
5063
5064         if (has_ck505)
5065                 val |= DREF_NONSPREAD_CK505_ENABLE;
5066         else
5067                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5068
5069         if (has_panel) {
5070                 val &= ~DREF_SSC_SOURCE_MASK;
5071                 val |= DREF_SSC_SOURCE_ENABLE;
5072
5073                 /* SSC must be turned on before enabling the CPU output  */
5074                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5075                         DRM_DEBUG_KMS("Using SSC on panel\n");
5076                         val |= DREF_SSC1_ENABLE;
5077                 } else
5078                         val &= ~DREF_SSC1_ENABLE;
5079
5080                 /* Get SSC going before enabling the outputs */
5081                 I915_WRITE(PCH_DREF_CONTROL, val);
5082                 POSTING_READ(PCH_DREF_CONTROL);
5083                 udelay(200);
5084
5085                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5086
5087                 /* Enable CPU source on CPU attached eDP */
5088                 if (has_cpu_edp) {
5089                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5090                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
5091                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5092                         }
5093                         else
5094                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5095                 } else
5096                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5097
5098                 I915_WRITE(PCH_DREF_CONTROL, val);
5099                 POSTING_READ(PCH_DREF_CONTROL);
5100                 udelay(200);
5101         } else {
5102                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5103
5104                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5105
5106                 /* Turn off CPU output */
5107                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5108
5109                 I915_WRITE(PCH_DREF_CONTROL, val);
5110                 POSTING_READ(PCH_DREF_CONTROL);
5111                 udelay(200);
5112
5113                 /* Turn off the SSC source */
5114                 val &= ~DREF_SSC_SOURCE_MASK;
5115                 val |= DREF_SSC_SOURCE_DISABLE;
5116
5117                 /* Turn off SSC1 */
5118                 val &= ~DREF_SSC1_ENABLE;
5119
5120                 I915_WRITE(PCH_DREF_CONTROL, val);
5121                 POSTING_READ(PCH_DREF_CONTROL);
5122                 udelay(200);
5123         }
5124
5125         BUG_ON(val != final);
5126 }
5127
5128 /* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
5129 static void lpt_init_pch_refclk(struct drm_device *dev)
5130 {
5131         struct drm_i915_private *dev_priv = dev->dev_private;
5132         struct drm_mode_config *mode_config = &dev->mode_config;
5133         struct intel_encoder *encoder;
5134         bool has_vga = false;
5135         bool is_sdv = false;
5136         u32 tmp;
5137
5138         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5139                 switch (encoder->type) {
5140                 case INTEL_OUTPUT_ANALOG:
5141                         has_vga = true;
5142                         break;
5143                 }
5144         }
5145
5146         if (!has_vga)
5147                 return;
5148
5149         mutex_lock(&dev_priv->dpio_lock);
5150
5151         /* XXX: Rip out SDV support once Haswell ships for real. */
5152         if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
5153                 is_sdv = true;
5154
5155         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5156         tmp &= ~SBI_SSCCTL_DISABLE;
5157         tmp |= SBI_SSCCTL_PATHALT;
5158         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5159
5160         udelay(24);
5161
5162         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5163         tmp &= ~SBI_SSCCTL_PATHALT;
5164         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5165
5166         if (!is_sdv) {
5167                 tmp = I915_READ(SOUTH_CHICKEN2);
5168                 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5169                 I915_WRITE(SOUTH_CHICKEN2, tmp);
5170
5171                 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5172                                        FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5173                         DRM_ERROR("FDI mPHY reset assert timeout\n");
5174
5175                 tmp = I915_READ(SOUTH_CHICKEN2);
5176                 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5177                 I915_WRITE(SOUTH_CHICKEN2, tmp);
5178
5179                 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5180                                         FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
5181                                        100))
5182                         DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5183         }
5184
5185         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5186         tmp &= ~(0xFF << 24);
5187         tmp |= (0x12 << 24);
5188         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5189
5190         if (is_sdv) {
5191                 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
5192                 tmp |= 0x7FFF;
5193                 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
5194         }
5195
5196         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5197         tmp |= (1 << 11);
5198         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5199
5200         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5201         tmp |= (1 << 11);
5202         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5203
5204         if (is_sdv) {
5205                 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
5206                 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5207                 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
5208
5209                 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5210                 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5211                 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5212
5213                 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5214                 tmp |= (0x3F << 8);
5215                 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5216
5217                 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5218                 tmp |= (0x3F << 8);
5219                 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5220         }
5221
5222         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5223         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5224         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5225
5226         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5227         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5228         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5229
5230         if (!is_sdv) {
5231                 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5232                 tmp &= ~(7 << 13);
5233                 tmp |= (5 << 13);
5234                 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5235
5236                 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5237                 tmp &= ~(7 << 13);
5238                 tmp |= (5 << 13);
5239                 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5240         }
5241
5242         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5243         tmp &= ~0xFF;
5244         tmp |= 0x1C;
5245         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5246
5247         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5248         tmp &= ~0xFF;
5249         tmp |= 0x1C;
5250         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5251
5252         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5253         tmp &= ~(0xFF << 16);
5254         tmp |= (0x1C << 16);
5255         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5256
5257         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5258         tmp &= ~(0xFF << 16);
5259         tmp |= (0x1C << 16);
5260         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5261
5262         if (!is_sdv) {
5263                 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5264                 tmp |= (1 << 27);
5265                 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5266
5267                 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5268                 tmp |= (1 << 27);
5269                 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5270
5271                 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5272                 tmp &= ~(0xF << 28);
5273                 tmp |= (4 << 28);
5274                 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5275
5276                 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5277                 tmp &= ~(0xF << 28);
5278                 tmp |= (4 << 28);
5279                 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5280         }
5281
5282         /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5283         tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5284         tmp |= SBI_DBUFF0_ENABLE;
5285         intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
5286
5287         mutex_unlock(&dev_priv->dpio_lock);
5288 }
5289
5290 /*
5291  * Initialize reference clocks when the driver loads
5292  */
5293 void intel_init_pch_refclk(struct drm_device *dev)
5294 {
5295         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5296                 ironlake_init_pch_refclk(dev);
5297         else if (HAS_PCH_LPT(dev))
5298                 lpt_init_pch_refclk(dev);
5299 }
5300
5301 static int ironlake_get_refclk(struct drm_crtc *crtc)
5302 {
5303         struct drm_device *dev = crtc->dev;
5304         struct drm_i915_private *dev_priv = dev->dev_private;
5305         struct intel_encoder *encoder;
5306         int num_connectors = 0;
5307         bool is_lvds = false;
5308
5309         for_each_encoder_on_crtc(dev, crtc, encoder) {
5310                 switch (encoder->type) {
5311                 case INTEL_OUTPUT_LVDS:
5312                         is_lvds = true;
5313                         break;
5314                 }
5315                 num_connectors++;
5316         }
5317
5318         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5319                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5320                               dev_priv->vbt.lvds_ssc_freq);
5321                 return dev_priv->vbt.lvds_ssc_freq * 1000;
5322         }
5323
5324         return 120000;
5325 }
5326
5327 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
5328 {
5329         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5330         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5331         int pipe = intel_crtc->pipe;
5332         uint32_t val;
5333
5334         val = 0;
5335
5336         switch (intel_crtc->config.pipe_bpp) {
5337         case 18:
5338                 val |= PIPECONF_6BPC;
5339                 break;
5340         case 24:
5341                 val |= PIPECONF_8BPC;
5342                 break;
5343         case 30:
5344                 val |= PIPECONF_10BPC;
5345                 break;
5346         case 36:
5347                 val |= PIPECONF_12BPC;
5348                 break;
5349         default:
5350                 /* Case prevented by intel_choose_pipe_bpp_dither. */
5351                 BUG();
5352         }
5353
5354         if (intel_crtc->config.dither)
5355                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5356
5357         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5358                 val |= PIPECONF_INTERLACED_ILK;
5359         else
5360                 val |= PIPECONF_PROGRESSIVE;
5361
5362         if (intel_crtc->config.limited_color_range)
5363                 val |= PIPECONF_COLOR_RANGE_SELECT;
5364
5365         I915_WRITE(PIPECONF(pipe), val);
5366         POSTING_READ(PIPECONF(pipe));
5367 }
5368
5369 /*
5370  * Set up the pipe CSC unit.
5371  *
5372  * Currently only full range RGB to limited range RGB conversion
5373  * is supported, but eventually this should handle various
5374  * RGB<->YCbCr scenarios as well.
5375  */
5376 static void intel_set_pipe_csc(struct drm_crtc *crtc)
5377 {
5378         struct drm_device *dev = crtc->dev;
5379         struct drm_i915_private *dev_priv = dev->dev_private;
5380         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5381         int pipe = intel_crtc->pipe;
5382         uint16_t coeff = 0x7800; /* 1.0 */
5383
5384         /*
5385          * TODO: Check what kind of values actually come out of the pipe
5386          * with these coeff/postoff values and adjust to get the best
5387          * accuracy. Perhaps we even need to take the bpc value into
5388          * consideration.
5389          */
5390
5391         if (intel_crtc->config.limited_color_range)
5392                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5393
5394         /*
5395          * GY/GU and RY/RU should be the other way around according
5396          * to BSpec, but reality doesn't agree. Just set them up in
5397          * a way that results in the correct picture.
5398          */
5399         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5400         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5401
5402         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5403         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5404
5405         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5406         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5407
5408         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5409         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5410         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5411
5412         if (INTEL_INFO(dev)->gen > 6) {
5413                 uint16_t postoff = 0;
5414
5415                 if (intel_crtc->config.limited_color_range)
5416                         postoff = (16 * (1 << 13) / 255) & 0x1fff;
5417
5418                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5419                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5420                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5421
5422                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5423         } else {
5424                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5425
5426                 if (intel_crtc->config.limited_color_range)
5427                         mode |= CSC_BLACK_SCREEN_OFFSET;
5428
5429                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5430         }
5431 }
5432
5433 static void haswell_set_pipeconf(struct drm_crtc *crtc)
5434 {
5435         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5436         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5437         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5438         uint32_t val;
5439
5440         val = 0;
5441
5442         if (intel_crtc->config.dither)
5443                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5444
5445         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5446                 val |= PIPECONF_INTERLACED_ILK;
5447         else
5448                 val |= PIPECONF_PROGRESSIVE;
5449
5450         I915_WRITE(PIPECONF(cpu_transcoder), val);
5451         POSTING_READ(PIPECONF(cpu_transcoder));
5452
5453         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
5454         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
5455 }
5456
5457 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5458                                     intel_clock_t *clock,
5459                                     bool *has_reduced_clock,
5460                                     intel_clock_t *reduced_clock)
5461 {
5462         struct drm_device *dev = crtc->dev;
5463         struct drm_i915_private *dev_priv = dev->dev_private;
5464         struct intel_encoder *intel_encoder;
5465         int refclk;
5466         const intel_limit_t *limit;
5467         bool ret, is_lvds = false;
5468
5469         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5470                 switch (intel_encoder->type) {
5471                 case INTEL_OUTPUT_LVDS:
5472                         is_lvds = true;
5473                         break;
5474                 }
5475         }
5476
5477         refclk = ironlake_get_refclk(crtc);
5478
5479         /*
5480          * Returns a set of divisors for the desired target clock with the given
5481          * refclk, or FALSE.  The returned values represent the clock equation:
5482          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5483          */
5484         limit = intel_limit(crtc, refclk);
5485         ret = dev_priv->display.find_dpll(limit, crtc,
5486                                           to_intel_crtc(crtc)->config.port_clock,
5487                                           refclk, NULL, clock);
5488         if (!ret)
5489                 return false;
5490
5491         if (is_lvds && dev_priv->lvds_downclock_avail) {
5492                 /*
5493                  * Ensure we match the reduced clock's P to the target clock.
5494                  * If the clocks don't match, we can't switch the display clock
5495                  * by using the FP0/FP1. In such case we will disable the LVDS
5496                  * downclock feature.
5497                 */
5498                 *has_reduced_clock =
5499                         dev_priv->display.find_dpll(limit, crtc,
5500                                                     dev_priv->lvds_downclock,
5501                                                     refclk, clock,
5502                                                     reduced_clock);
5503         }
5504
5505         return true;
5506 }
5507
5508 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5509 {
5510         struct drm_i915_private *dev_priv = dev->dev_private;
5511         uint32_t temp;
5512
5513         temp = I915_READ(SOUTH_CHICKEN1);
5514         if (temp & FDI_BC_BIFURCATION_SELECT)
5515                 return;
5516
5517         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5518         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5519
5520         temp |= FDI_BC_BIFURCATION_SELECT;
5521         DRM_DEBUG_KMS("enabling fdi C rx\n");
5522         I915_WRITE(SOUTH_CHICKEN1, temp);
5523         POSTING_READ(SOUTH_CHICKEN1);
5524 }
5525
5526 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
5527 {
5528         struct drm_device *dev = intel_crtc->base.dev;
5529         struct drm_i915_private *dev_priv = dev->dev_private;
5530
5531         switch (intel_crtc->pipe) {
5532         case PIPE_A:
5533                 break;
5534         case PIPE_B:
5535                 if (intel_crtc->config.fdi_lanes > 2)
5536                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5537                 else
5538                         cpt_enable_fdi_bc_bifurcation(dev);
5539
5540                 break;
5541         case PIPE_C:
5542                 cpt_enable_fdi_bc_bifurcation(dev);
5543
5544                 break;
5545         default:
5546                 BUG();
5547         }
5548 }
5549
5550 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5551 {
5552         /*
5553          * Account for spread spectrum to avoid
5554          * oversubscribing the link. Max center spread
5555          * is 2.5%; use 5% for safety's sake.
5556          */
5557         u32 bps = target_clock * bpp * 21 / 20;
5558         return bps / (link_bw * 8) + 1;
5559 }
5560
5561 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5562 {
5563         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5564 }
5565
5566 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5567                                       u32 *fp,
5568                                       intel_clock_t *reduced_clock, u32 *fp2)
5569 {
5570         struct drm_crtc *crtc = &intel_crtc->base;
5571         struct drm_device *dev = crtc->dev;
5572         struct drm_i915_private *dev_priv = dev->dev_private;
5573         struct intel_encoder *intel_encoder;
5574         uint32_t dpll;
5575         int factor, num_connectors = 0;
5576         bool is_lvds = false, is_sdvo = false;
5577
5578         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5579                 switch (intel_encoder->type) {
5580                 case INTEL_OUTPUT_LVDS:
5581                         is_lvds = true;
5582                         break;
5583                 case INTEL_OUTPUT_SDVO:
5584                 case INTEL_OUTPUT_HDMI:
5585                         is_sdvo = true;
5586                         break;
5587                 }
5588
5589                 num_connectors++;
5590         }
5591
5592         /* Enable autotuning of the PLL clock (if permissible) */
5593         factor = 21;
5594         if (is_lvds) {
5595                 if ((intel_panel_use_ssc(dev_priv) &&
5596                      dev_priv->vbt.lvds_ssc_freq == 100) ||
5597                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
5598                         factor = 25;
5599         } else if (intel_crtc->config.sdvo_tv_clock)
5600                 factor = 20;
5601
5602         if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
5603                 *fp |= FP_CB_TUNE;
5604
5605         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5606                 *fp2 |= FP_CB_TUNE;
5607
5608         dpll = 0;
5609
5610         if (is_lvds)
5611                 dpll |= DPLLB_MODE_LVDS;
5612         else
5613                 dpll |= DPLLB_MODE_DAC_SERIAL;
5614
5615         dpll |= (intel_crtc->config.pixel_multiplier - 1)
5616                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5617
5618         if (is_sdvo)
5619                 dpll |= DPLL_DVO_HIGH_SPEED;
5620         if (intel_crtc->config.has_dp_encoder)
5621                 dpll |= DPLL_DVO_HIGH_SPEED;
5622
5623         /* compute bitmask from p1 value */
5624         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5625         /* also FPA1 */
5626         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5627
5628         switch (intel_crtc->config.dpll.p2) {
5629         case 5:
5630                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5631                 break;
5632         case 7:
5633                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5634                 break;
5635         case 10:
5636                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5637                 break;
5638         case 14:
5639                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5640                 break;
5641         }
5642
5643         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5644                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5645         else
5646                 dpll |= PLL_REF_INPUT_DREFCLK;
5647
5648         return dpll | DPLL_VCO_ENABLE;
5649 }
5650
5651 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5652                                   int x, int y,
5653                                   struct drm_framebuffer *fb)
5654 {
5655         struct drm_device *dev = crtc->dev;
5656         struct drm_i915_private *dev_priv = dev->dev_private;
5657         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5658         int pipe = intel_crtc->pipe;
5659         int plane = intel_crtc->plane;
5660         int num_connectors = 0;
5661         intel_clock_t clock, reduced_clock;
5662         u32 dpll = 0, fp = 0, fp2 = 0;
5663         bool ok, has_reduced_clock = false;
5664         bool is_lvds = false;
5665         struct intel_encoder *encoder;
5666         struct intel_shared_dpll *pll;
5667         int ret;
5668
5669         for_each_encoder_on_crtc(dev, crtc, encoder) {
5670                 switch (encoder->type) {
5671                 case INTEL_OUTPUT_LVDS:
5672                         is_lvds = true;
5673                         break;
5674                 }
5675
5676                 num_connectors++;
5677         }
5678
5679         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5680              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5681
5682         ok = ironlake_compute_clocks(crtc, &clock,
5683                                      &has_reduced_clock, &reduced_clock);
5684         if (!ok && !intel_crtc->config.clock_set) {
5685                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5686                 return -EINVAL;
5687         }
5688         /* Compat-code for transition, will disappear. */
5689         if (!intel_crtc->config.clock_set) {
5690                 intel_crtc->config.dpll.n = clock.n;
5691                 intel_crtc->config.dpll.m1 = clock.m1;
5692                 intel_crtc->config.dpll.m2 = clock.m2;
5693                 intel_crtc->config.dpll.p1 = clock.p1;
5694                 intel_crtc->config.dpll.p2 = clock.p2;
5695         }
5696
5697         /* Ensure that the cursor is valid for the new mode before changing... */
5698         intel_crtc_update_cursor(crtc, true);
5699
5700         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5701         if (intel_crtc->config.has_pch_encoder) {
5702                 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
5703                 if (has_reduced_clock)
5704                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
5705
5706                 dpll = ironlake_compute_dpll(intel_crtc,
5707                                              &fp, &reduced_clock,
5708                                              has_reduced_clock ? &fp2 : NULL);
5709
5710                 intel_crtc->config.dpll_hw_state.dpll = dpll;
5711                 intel_crtc->config.dpll_hw_state.fp0 = fp;
5712                 if (has_reduced_clock)
5713                         intel_crtc->config.dpll_hw_state.fp1 = fp2;
5714                 else
5715                         intel_crtc->config.dpll_hw_state.fp1 = fp;
5716
5717                 pll = intel_get_shared_dpll(intel_crtc, dpll, fp);
5718                 if (pll == NULL) {
5719                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5720                                          pipe_name(pipe));
5721                         return -EINVAL;
5722                 }
5723         } else
5724                 intel_put_shared_dpll(intel_crtc);
5725
5726         if (intel_crtc->config.has_dp_encoder)
5727                 intel_dp_set_m_n(intel_crtc);
5728
5729         for_each_encoder_on_crtc(dev, crtc, encoder)
5730                 if (encoder->pre_pll_enable)
5731                         encoder->pre_pll_enable(encoder);
5732
5733         intel_crtc->lowfreq_avail = false;
5734
5735         if (intel_crtc->config.has_pch_encoder) {
5736                 pll = intel_crtc_to_shared_dpll(intel_crtc);
5737
5738                 I915_WRITE(PCH_DPLL(pll->id), dpll);
5739
5740                 /* Wait for the clocks to stabilize. */
5741                 POSTING_READ(PCH_DPLL(pll->id));
5742                 udelay(150);
5743
5744                 /* The pixel multiplier can only be updated once the
5745                  * DPLL is enabled and the clocks are stable.
5746                  *
5747                  * So write it again.
5748                  */
5749                 I915_WRITE(PCH_DPLL(pll->id), dpll);
5750
5751                 if (is_lvds && has_reduced_clock && i915_powersave) {
5752                         I915_WRITE(PCH_FP1(pll->id), fp2);
5753                         intel_crtc->lowfreq_avail = true;
5754                 } else {
5755                         I915_WRITE(PCH_FP1(pll->id), fp);
5756                 }
5757         }
5758
5759         intel_set_pipe_timings(intel_crtc);
5760
5761         if (intel_crtc->config.has_pch_encoder) {
5762                 intel_cpu_transcoder_set_m_n(intel_crtc,
5763                                              &intel_crtc->config.fdi_m_n);
5764         }
5765
5766         if (IS_IVYBRIDGE(dev))
5767                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
5768
5769         ironlake_set_pipeconf(crtc);
5770
5771         /* Set up the display plane register */
5772         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5773         POSTING_READ(DSPCNTR(plane));
5774
5775         ret = intel_pipe_set_base(crtc, x, y, fb);
5776
5777         intel_update_watermarks(dev);
5778
5779         return ret;
5780 }
5781
5782 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5783                                         struct intel_crtc_config *pipe_config)
5784 {
5785         struct drm_device *dev = crtc->base.dev;
5786         struct drm_i915_private *dev_priv = dev->dev_private;
5787         enum transcoder transcoder = pipe_config->cpu_transcoder;
5788
5789         pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
5790         pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
5791         pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5792                                         & ~TU_SIZE_MASK;
5793         pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5794         pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5795                                    & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5796 }
5797
5798 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5799                                      struct intel_crtc_config *pipe_config)
5800 {
5801         struct drm_device *dev = crtc->base.dev;
5802         struct drm_i915_private *dev_priv = dev->dev_private;
5803         uint32_t tmp;
5804
5805         tmp = I915_READ(PF_CTL(crtc->pipe));
5806
5807         if (tmp & PF_ENABLE) {
5808                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5809                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
5810
5811                 /* We currently do not free assignements of panel fitters on
5812                  * ivb/hsw (since we don't use the higher upscaling modes which
5813                  * differentiates them) so just WARN about this case for now. */
5814                 if (IS_GEN7(dev)) {
5815                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
5816                                 PF_PIPE_SEL_IVB(crtc->pipe));
5817                 }
5818         }
5819 }
5820
5821 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5822                                      struct intel_crtc_config *pipe_config)
5823 {
5824         struct drm_device *dev = crtc->base.dev;
5825         struct drm_i915_private *dev_priv = dev->dev_private;
5826         uint32_t tmp;
5827
5828         pipe_config->cpu_transcoder = crtc->pipe;
5829         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5830
5831         tmp = I915_READ(PIPECONF(crtc->pipe));
5832         if (!(tmp & PIPECONF_ENABLE))
5833                 return false;
5834
5835         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
5836                 struct intel_shared_dpll *pll;
5837
5838                 pipe_config->has_pch_encoder = true;
5839
5840                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5841                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5842                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
5843
5844                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
5845
5846                 /* XXX: Can't properly read out the pch dpll pixel multiplier
5847                  * since we don't have state tracking for pch clocks yet. */
5848                 pipe_config->pixel_multiplier = 1;
5849
5850                 if (HAS_PCH_IBX(dev_priv->dev)) {
5851                         pipe_config->shared_dpll = crtc->pipe;
5852                 } else {
5853                         tmp = I915_READ(PCH_DPLL_SEL);
5854                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
5855                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
5856                         else
5857                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
5858                 }
5859
5860                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
5861
5862                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
5863                                            &pipe_config->dpll_hw_state));
5864         } else {
5865                 pipe_config->pixel_multiplier = 1;
5866         }
5867
5868         intel_get_pipe_timings(crtc, pipe_config);
5869
5870         ironlake_get_pfit_config(crtc, pipe_config);
5871
5872         return true;
5873 }
5874
5875 static void haswell_modeset_global_resources(struct drm_device *dev)
5876 {
5877         bool enable = false;
5878         struct intel_crtc *crtc;
5879
5880         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
5881                 if (!crtc->base.enabled)
5882                         continue;
5883
5884                 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.size ||
5885                     crtc->config.cpu_transcoder != TRANSCODER_EDP)
5886                         enable = true;
5887         }
5888
5889         intel_set_power_well(dev, enable);
5890 }
5891
5892 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5893                                  int x, int y,
5894                                  struct drm_framebuffer *fb)
5895 {
5896         struct drm_device *dev = crtc->dev;
5897         struct drm_i915_private *dev_priv = dev->dev_private;
5898         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5899         int plane = intel_crtc->plane;
5900         int ret;
5901
5902         if (!intel_ddi_pll_mode_set(crtc))
5903                 return -EINVAL;
5904
5905         /* Ensure that the cursor is valid for the new mode before changing... */
5906         intel_crtc_update_cursor(crtc, true);
5907
5908         if (intel_crtc->config.has_dp_encoder)
5909                 intel_dp_set_m_n(intel_crtc);
5910
5911         intel_crtc->lowfreq_avail = false;
5912
5913         intel_set_pipe_timings(intel_crtc);
5914
5915         if (intel_crtc->config.has_pch_encoder) {
5916                 intel_cpu_transcoder_set_m_n(intel_crtc,
5917                                              &intel_crtc->config.fdi_m_n);
5918         }
5919
5920         haswell_set_pipeconf(crtc);
5921
5922         intel_set_pipe_csc(crtc);
5923
5924         /* Set up the display plane register */
5925         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
5926         POSTING_READ(DSPCNTR(plane));
5927
5928         ret = intel_pipe_set_base(crtc, x, y, fb);
5929
5930         intel_update_watermarks(dev);
5931
5932         return ret;
5933 }
5934
5935 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5936                                     struct intel_crtc_config *pipe_config)
5937 {
5938         struct drm_device *dev = crtc->base.dev;
5939         struct drm_i915_private *dev_priv = dev->dev_private;
5940         enum intel_display_power_domain pfit_domain;
5941         uint32_t tmp;
5942
5943         pipe_config->cpu_transcoder = crtc->pipe;
5944         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5945
5946         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
5947         if (tmp & TRANS_DDI_FUNC_ENABLE) {
5948                 enum pipe trans_edp_pipe;
5949                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
5950                 default:
5951                         WARN(1, "unknown pipe linked to edp transcoder\n");
5952                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
5953                 case TRANS_DDI_EDP_INPUT_A_ON:
5954                         trans_edp_pipe = PIPE_A;
5955                         break;
5956                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
5957                         trans_edp_pipe = PIPE_B;
5958                         break;
5959                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
5960                         trans_edp_pipe = PIPE_C;
5961                         break;
5962                 }
5963
5964                 if (trans_edp_pipe == crtc->pipe)
5965                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
5966         }
5967
5968         if (!intel_display_power_enabled(dev,
5969                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
5970                 return false;
5971
5972         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
5973         if (!(tmp & PIPECONF_ENABLE))
5974                 return false;
5975
5976         /*
5977          * Haswell has only FDI/PCH transcoder A. It is which is connected to
5978          * DDI E. So just check whether this pipe is wired to DDI E and whether
5979          * the PCH transcoder is on.
5980          */
5981         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
5982         if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
5983             I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
5984                 pipe_config->has_pch_encoder = true;
5985
5986                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
5987                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5988                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
5989
5990                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
5991         }
5992
5993         intel_get_pipe_timings(crtc, pipe_config);
5994
5995         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
5996         if (intel_display_power_enabled(dev, pfit_domain))
5997                 ironlake_get_pfit_config(crtc, pipe_config);
5998
5999         pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6000                                    (I915_READ(IPS_CTL) & IPS_ENABLE);
6001
6002         pipe_config->pixel_multiplier = 1;
6003
6004         return true;
6005 }
6006
6007 static int intel_crtc_mode_set(struct drm_crtc *crtc,
6008                                int x, int y,
6009                                struct drm_framebuffer *fb)
6010 {
6011         struct drm_device *dev = crtc->dev;
6012         struct drm_i915_private *dev_priv = dev->dev_private;
6013         struct drm_encoder_helper_funcs *encoder_funcs;
6014         struct intel_encoder *encoder;
6015         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6016         struct drm_display_mode *adjusted_mode =
6017                 &intel_crtc->config.adjusted_mode;
6018         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
6019         int pipe = intel_crtc->pipe;
6020         int ret;
6021
6022         drm_vblank_pre_modeset(dev, pipe);
6023
6024         ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6025
6026         drm_vblank_post_modeset(dev, pipe);
6027
6028         if (ret != 0)
6029                 return ret;
6030
6031         for_each_encoder_on_crtc(dev, crtc, encoder) {
6032                 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6033                         encoder->base.base.id,
6034                         drm_get_encoder_name(&encoder->base),
6035                         mode->base.id, mode->name);
6036                 if (encoder->mode_set) {
6037                         encoder->mode_set(encoder);
6038                 } else {
6039                         encoder_funcs = encoder->base.helper_private;
6040                         encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
6041                 }
6042         }
6043
6044         return 0;
6045 }
6046
6047 static bool intel_eld_uptodate(struct drm_connector *connector,
6048                                int reg_eldv, uint32_t bits_eldv,
6049                                int reg_elda, uint32_t bits_elda,
6050                                int reg_edid)
6051 {
6052         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6053         uint8_t *eld = connector->eld;
6054         uint32_t i;
6055
6056         i = I915_READ(reg_eldv);
6057         i &= bits_eldv;
6058
6059         if (!eld[0])
6060                 return !i;
6061
6062         if (!i)
6063                 return false;
6064
6065         i = I915_READ(reg_elda);
6066         i &= ~bits_elda;
6067         I915_WRITE(reg_elda, i);
6068
6069         for (i = 0; i < eld[2]; i++)
6070                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6071                         return false;
6072
6073         return true;
6074 }
6075
6076 static void g4x_write_eld(struct drm_connector *connector,
6077                           struct drm_crtc *crtc)
6078 {
6079         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6080         uint8_t *eld = connector->eld;
6081         uint32_t eldv;
6082         uint32_t len;
6083         uint32_t i;
6084
6085         i = I915_READ(G4X_AUD_VID_DID);
6086
6087         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6088                 eldv = G4X_ELDV_DEVCL_DEVBLC;
6089         else
6090                 eldv = G4X_ELDV_DEVCTG;
6091
6092         if (intel_eld_uptodate(connector,
6093                                G4X_AUD_CNTL_ST, eldv,
6094                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6095                                G4X_HDMIW_HDMIEDID))
6096                 return;
6097
6098         i = I915_READ(G4X_AUD_CNTL_ST);
6099         i &= ~(eldv | G4X_ELD_ADDR);
6100         len = (i >> 9) & 0x1f;          /* ELD buffer size */
6101         I915_WRITE(G4X_AUD_CNTL_ST, i);
6102
6103         if (!eld[0])
6104                 return;
6105
6106         len = min_t(uint8_t, eld[2], len);
6107         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6108         for (i = 0; i < len; i++)
6109                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6110
6111         i = I915_READ(G4X_AUD_CNTL_ST);
6112         i |= eldv;
6113         I915_WRITE(G4X_AUD_CNTL_ST, i);
6114 }
6115
6116 static void haswell_write_eld(struct drm_connector *connector,
6117                                      struct drm_crtc *crtc)
6118 {
6119         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6120         uint8_t *eld = connector->eld;
6121         struct drm_device *dev = crtc->dev;
6122         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6123         uint32_t eldv;
6124         uint32_t i;
6125         int len;
6126         int pipe = to_intel_crtc(crtc)->pipe;
6127         int tmp;
6128
6129         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6130         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6131         int aud_config = HSW_AUD_CFG(pipe);
6132         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6133
6134
6135         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6136
6137         /* Audio output enable */
6138         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6139         tmp = I915_READ(aud_cntrl_st2);
6140         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6141         I915_WRITE(aud_cntrl_st2, tmp);
6142
6143         /* Wait for 1 vertical blank */
6144         intel_wait_for_vblank(dev, pipe);
6145
6146         /* Set ELD valid state */
6147         tmp = I915_READ(aud_cntrl_st2);
6148         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6149         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6150         I915_WRITE(aud_cntrl_st2, tmp);
6151         tmp = I915_READ(aud_cntrl_st2);
6152         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6153
6154         /* Enable HDMI mode */
6155         tmp = I915_READ(aud_config);
6156         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6157         /* clear N_programing_enable and N_value_index */
6158         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6159         I915_WRITE(aud_config, tmp);
6160
6161         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6162
6163         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
6164         intel_crtc->eld_vld = true;
6165
6166         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6167                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6168                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6169                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6170         } else
6171                 I915_WRITE(aud_config, 0);
6172
6173         if (intel_eld_uptodate(connector,
6174                                aud_cntrl_st2, eldv,
6175                                aud_cntl_st, IBX_ELD_ADDRESS,
6176                                hdmiw_hdmiedid))
6177                 return;
6178
6179         i = I915_READ(aud_cntrl_st2);
6180         i &= ~eldv;
6181         I915_WRITE(aud_cntrl_st2, i);
6182
6183         if (!eld[0])
6184                 return;
6185
6186         i = I915_READ(aud_cntl_st);
6187         i &= ~IBX_ELD_ADDRESS;
6188         I915_WRITE(aud_cntl_st, i);
6189         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6190         DRM_DEBUG_DRIVER("port num:%d\n", i);
6191
6192         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6193         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6194         for (i = 0; i < len; i++)
6195                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6196
6197         i = I915_READ(aud_cntrl_st2);
6198         i |= eldv;
6199         I915_WRITE(aud_cntrl_st2, i);
6200
6201 }
6202
6203 static void ironlake_write_eld(struct drm_connector *connector,
6204                                      struct drm_crtc *crtc)
6205 {
6206         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6207         uint8_t *eld = connector->eld;
6208         uint32_t eldv;
6209         uint32_t i;
6210         int len;
6211         int hdmiw_hdmiedid;
6212         int aud_config;
6213         int aud_cntl_st;
6214         int aud_cntrl_st2;
6215         int pipe = to_intel_crtc(crtc)->pipe;
6216
6217         if (HAS_PCH_IBX(connector->dev)) {
6218                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6219                 aud_config = IBX_AUD_CFG(pipe);
6220                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6221                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6222         } else {
6223                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6224                 aud_config = CPT_AUD_CFG(pipe);
6225                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6226                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6227         }
6228
6229         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6230
6231         i = I915_READ(aud_cntl_st);
6232         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6233         if (!i) {
6234                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6235                 /* operate blindly on all ports */
6236                 eldv = IBX_ELD_VALIDB;
6237                 eldv |= IBX_ELD_VALIDB << 4;
6238                 eldv |= IBX_ELD_VALIDB << 8;
6239         } else {
6240                 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
6241                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6242         }
6243
6244         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6245                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6246                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6247                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6248         } else
6249                 I915_WRITE(aud_config, 0);
6250
6251         if (intel_eld_uptodate(connector,
6252                                aud_cntrl_st2, eldv,
6253                                aud_cntl_st, IBX_ELD_ADDRESS,
6254                                hdmiw_hdmiedid))
6255                 return;
6256
6257         i = I915_READ(aud_cntrl_st2);
6258         i &= ~eldv;
6259         I915_WRITE(aud_cntrl_st2, i);
6260
6261         if (!eld[0])
6262                 return;
6263
6264         i = I915_READ(aud_cntl_st);
6265         i &= ~IBX_ELD_ADDRESS;
6266         I915_WRITE(aud_cntl_st, i);
6267
6268         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6269         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6270         for (i = 0; i < len; i++)
6271                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6272
6273         i = I915_READ(aud_cntrl_st2);
6274         i |= eldv;
6275         I915_WRITE(aud_cntrl_st2, i);
6276 }
6277
6278 void intel_write_eld(struct drm_encoder *encoder,
6279                      struct drm_display_mode *mode)
6280 {
6281         struct drm_crtc *crtc = encoder->crtc;
6282         struct drm_connector *connector;
6283         struct drm_device *dev = encoder->dev;
6284         struct drm_i915_private *dev_priv = dev->dev_private;
6285
6286         connector = drm_select_eld(encoder, mode);
6287         if (!connector)
6288                 return;
6289
6290         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6291                          connector->base.id,
6292                          drm_get_connector_name(connector),
6293                          connector->encoder->base.id,
6294                          drm_get_encoder_name(connector->encoder));
6295
6296         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6297
6298         if (dev_priv->display.write_eld)
6299                 dev_priv->display.write_eld(connector, crtc);
6300 }
6301
6302 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6303 void intel_crtc_load_lut(struct drm_crtc *crtc)
6304 {
6305         struct drm_device *dev = crtc->dev;
6306         struct drm_i915_private *dev_priv = dev->dev_private;
6307         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6308         enum pipe pipe = intel_crtc->pipe;
6309         int palreg = PALETTE(pipe);
6310         int i;
6311         bool reenable_ips = false;
6312
6313         /* The clocks have to be on to load the palette. */
6314         if (!crtc->enabled || !intel_crtc->active)
6315                 return;
6316
6317         if (!HAS_PCH_SPLIT(dev_priv->dev))
6318                 assert_pll_enabled(dev_priv, pipe);
6319
6320         /* use legacy palette for Ironlake */
6321         if (HAS_PCH_SPLIT(dev))
6322                 palreg = LGC_PALETTE(pipe);
6323
6324         /* Workaround : Do not read or write the pipe palette/gamma data while
6325          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6326          */
6327         if (intel_crtc->config.ips_enabled &&
6328             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
6329              GAMMA_MODE_MODE_SPLIT)) {
6330                 hsw_disable_ips(intel_crtc);
6331                 reenable_ips = true;
6332         }
6333
6334         for (i = 0; i < 256; i++) {
6335                 I915_WRITE(palreg + 4 * i,
6336                            (intel_crtc->lut_r[i] << 16) |
6337                            (intel_crtc->lut_g[i] << 8) |
6338                            intel_crtc->lut_b[i]);
6339         }
6340
6341         if (reenable_ips)
6342                 hsw_enable_ips(intel_crtc);
6343 }
6344
6345 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6346 {
6347         struct drm_device *dev = crtc->dev;
6348         struct drm_i915_private *dev_priv = dev->dev_private;
6349         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6350         bool visible = base != 0;
6351         u32 cntl;
6352
6353         if (intel_crtc->cursor_visible == visible)
6354                 return;
6355
6356         cntl = I915_READ(_CURACNTR);
6357         if (visible) {
6358                 /* On these chipsets we can only modify the base whilst
6359                  * the cursor is disabled.
6360                  */
6361                 I915_WRITE(_CURABASE, base);
6362
6363                 cntl &= ~(CURSOR_FORMAT_MASK);
6364                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6365                 cntl |= CURSOR_ENABLE |
6366                         CURSOR_GAMMA_ENABLE |
6367                         CURSOR_FORMAT_ARGB;
6368         } else
6369                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6370         I915_WRITE(_CURACNTR, cntl);
6371
6372         intel_crtc->cursor_visible = visible;
6373 }
6374
6375 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6376 {
6377         struct drm_device *dev = crtc->dev;
6378         struct drm_i915_private *dev_priv = dev->dev_private;
6379         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6380         int pipe = intel_crtc->pipe;
6381         bool visible = base != 0;
6382
6383         if (intel_crtc->cursor_visible != visible) {
6384                 uint32_t cntl = I915_READ(CURCNTR(pipe));
6385                 if (base) {
6386                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6387                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6388                         cntl |= pipe << 28; /* Connect to correct pipe */
6389                 } else {
6390                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6391                         cntl |= CURSOR_MODE_DISABLE;
6392                 }
6393                 I915_WRITE(CURCNTR(pipe), cntl);
6394
6395                 intel_crtc->cursor_visible = visible;
6396         }
6397         /* and commit changes on next vblank */
6398         I915_WRITE(CURBASE(pipe), base);
6399 }
6400
6401 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6402 {
6403         struct drm_device *dev = crtc->dev;
6404         struct drm_i915_private *dev_priv = dev->dev_private;
6405         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6406         int pipe = intel_crtc->pipe;
6407         bool visible = base != 0;
6408
6409         if (intel_crtc->cursor_visible != visible) {
6410                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6411                 if (base) {
6412                         cntl &= ~CURSOR_MODE;
6413                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6414                 } else {
6415                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6416                         cntl |= CURSOR_MODE_DISABLE;
6417                 }
6418                 if (IS_HASWELL(dev))
6419                         cntl |= CURSOR_PIPE_CSC_ENABLE;
6420                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6421
6422                 intel_crtc->cursor_visible = visible;
6423         }
6424         /* and commit changes on next vblank */
6425         I915_WRITE(CURBASE_IVB(pipe), base);
6426 }
6427
6428 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6429 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6430                                      bool on)
6431 {
6432         struct drm_device *dev = crtc->dev;
6433         struct drm_i915_private *dev_priv = dev->dev_private;
6434         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6435         int pipe = intel_crtc->pipe;
6436         int x = intel_crtc->cursor_x;
6437         int y = intel_crtc->cursor_y;
6438         u32 base, pos;
6439         bool visible;
6440
6441         pos = 0;
6442
6443         if (on && crtc->enabled && crtc->fb) {
6444                 base = intel_crtc->cursor_addr;
6445                 if (x > (int) crtc->fb->width)
6446                         base = 0;
6447
6448                 if (y > (int) crtc->fb->height)
6449                         base = 0;
6450         } else
6451                 base = 0;
6452
6453         if (x < 0) {
6454                 if (x + intel_crtc->cursor_width < 0)
6455                         base = 0;
6456
6457                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6458                 x = -x;
6459         }
6460         pos |= x << CURSOR_X_SHIFT;
6461
6462         if (y < 0) {
6463                 if (y + intel_crtc->cursor_height < 0)
6464                         base = 0;
6465
6466                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6467                 y = -y;
6468         }
6469         pos |= y << CURSOR_Y_SHIFT;
6470
6471         visible = base != 0;
6472         if (!visible && !intel_crtc->cursor_visible)
6473                 return;
6474
6475         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6476                 I915_WRITE(CURPOS_IVB(pipe), pos);
6477                 ivb_update_cursor(crtc, base);
6478         } else {
6479                 I915_WRITE(CURPOS(pipe), pos);
6480                 if (IS_845G(dev) || IS_I865G(dev))
6481                         i845_update_cursor(crtc, base);
6482                 else
6483                         i9xx_update_cursor(crtc, base);
6484         }
6485 }
6486
6487 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6488                                  struct drm_file *file,
6489                                  uint32_t handle,
6490                                  uint32_t width, uint32_t height)
6491 {
6492         struct drm_device *dev = crtc->dev;
6493         struct drm_i915_private *dev_priv = dev->dev_private;
6494         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6495         struct drm_i915_gem_object *obj;
6496         uint32_t addr;
6497         int ret;
6498
6499         /* if we want to turn off the cursor ignore width and height */
6500         if (!handle) {
6501                 DRM_DEBUG_KMS("cursor off\n");
6502                 addr = 0;
6503                 obj = NULL;
6504                 mutex_lock(&dev->struct_mutex);
6505                 goto finish;
6506         }
6507
6508         /* Currently we only support 64x64 cursors */
6509         if (width != 64 || height != 64) {
6510                 DRM_ERROR("we currently only support 64x64 cursors\n");
6511                 return -EINVAL;
6512         }
6513
6514         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6515         if (&obj->base == NULL)
6516                 return -ENOENT;
6517
6518         if (obj->base.size < width * height * 4) {
6519                 DRM_ERROR("buffer is to small\n");
6520                 ret = -ENOMEM;
6521                 goto fail;
6522         }
6523
6524         /* we only need to pin inside GTT if cursor is non-phy */
6525         mutex_lock(&dev->struct_mutex);
6526         if (!dev_priv->info->cursor_needs_physical) {
6527                 unsigned alignment;
6528
6529                 if (obj->tiling_mode) {
6530                         DRM_ERROR("cursor cannot be tiled\n");
6531                         ret = -EINVAL;
6532                         goto fail_locked;
6533                 }
6534
6535                 /* Note that the w/a also requires 2 PTE of padding following
6536                  * the bo. We currently fill all unused PTE with the shadow
6537                  * page and so we should always have valid PTE following the
6538                  * cursor preventing the VT-d warning.
6539                  */
6540                 alignment = 0;
6541                 if (need_vtd_wa(dev))
6542                         alignment = 64*1024;
6543
6544                 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
6545                 if (ret) {
6546                         DRM_ERROR("failed to move cursor bo into the GTT\n");
6547                         goto fail_locked;
6548                 }
6549
6550                 ret = i915_gem_object_put_fence(obj);
6551                 if (ret) {
6552                         DRM_ERROR("failed to release fence for cursor");
6553                         goto fail_unpin;
6554                 }
6555
6556                 addr = obj->gtt_offset;
6557         } else {
6558                 int align = IS_I830(dev) ? 16 * 1024 : 256;
6559                 ret = i915_gem_attach_phys_object(dev, obj,
6560                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6561                                                   align);
6562                 if (ret) {
6563                         DRM_ERROR("failed to attach phys object\n");
6564                         goto fail_locked;
6565                 }
6566                 addr = obj->phys_obj->handle->busaddr;
6567         }
6568
6569         if (IS_GEN2(dev))
6570                 I915_WRITE(CURSIZE, (height << 12) | width);
6571
6572  finish:
6573         if (intel_crtc->cursor_bo) {
6574                 if (dev_priv->info->cursor_needs_physical) {
6575                         if (intel_crtc->cursor_bo != obj)
6576                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6577                 } else
6578                         i915_gem_object_unpin(intel_crtc->cursor_bo);
6579                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6580         }
6581
6582         mutex_unlock(&dev->struct_mutex);
6583
6584         intel_crtc->cursor_addr = addr;
6585         intel_crtc->cursor_bo = obj;
6586         intel_crtc->cursor_width = width;
6587         intel_crtc->cursor_height = height;
6588
6589         intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
6590
6591         return 0;
6592 fail_unpin:
6593         i915_gem_object_unpin(obj);
6594 fail_locked:
6595         mutex_unlock(&dev->struct_mutex);
6596 fail:
6597         drm_gem_object_unreference_unlocked(&obj->base);
6598         return ret;
6599 }
6600
6601 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6602 {
6603         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6604
6605         intel_crtc->cursor_x = x;
6606         intel_crtc->cursor_y = y;
6607
6608         intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
6609
6610         return 0;
6611 }
6612
6613 /** Sets the color ramps on behalf of RandR */
6614 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6615                                  u16 blue, int regno)
6616 {
6617         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6618
6619         intel_crtc->lut_r[regno] = red >> 8;
6620         intel_crtc->lut_g[regno] = green >> 8;
6621         intel_crtc->lut_b[regno] = blue >> 8;
6622 }
6623
6624 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6625                              u16 *blue, int regno)
6626 {
6627         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6628
6629         *red = intel_crtc->lut_r[regno] << 8;
6630         *green = intel_crtc->lut_g[regno] << 8;
6631         *blue = intel_crtc->lut_b[regno] << 8;
6632 }
6633
6634 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6635                                  u16 *blue, uint32_t start, uint32_t size)
6636 {
6637         int end = (start + size > 256) ? 256 : start + size, i;
6638         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6639
6640         for (i = start; i < end; i++) {
6641                 intel_crtc->lut_r[i] = red[i] >> 8;
6642                 intel_crtc->lut_g[i] = green[i] >> 8;
6643                 intel_crtc->lut_b[i] = blue[i] >> 8;
6644         }
6645
6646         intel_crtc_load_lut(crtc);
6647 }
6648
6649 /* VESA 640x480x72Hz mode to set on the pipe */
6650 static struct drm_display_mode load_detect_mode = {
6651         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6652                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6653 };
6654
6655 static struct drm_framebuffer *
6656 intel_framebuffer_create(struct drm_device *dev,
6657                          struct drm_mode_fb_cmd2 *mode_cmd,
6658                          struct drm_i915_gem_object *obj)
6659 {
6660         struct intel_framebuffer *intel_fb;
6661         int ret;
6662
6663         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6664         if (!intel_fb) {
6665                 drm_gem_object_unreference_unlocked(&obj->base);
6666                 return ERR_PTR(-ENOMEM);
6667         }
6668
6669         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6670         if (ret) {
6671                 drm_gem_object_unreference_unlocked(&obj->base);
6672                 kfree(intel_fb);
6673                 return ERR_PTR(ret);
6674         }
6675
6676         return &intel_fb->base;
6677 }
6678
6679 static u32
6680 intel_framebuffer_pitch_for_width(int width, int bpp)
6681 {
6682         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6683         return ALIGN(pitch, 64);
6684 }
6685
6686 static u32
6687 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6688 {
6689         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6690         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6691 }
6692
6693 static struct drm_framebuffer *
6694 intel_framebuffer_create_for_mode(struct drm_device *dev,
6695                                   struct drm_display_mode *mode,
6696                                   int depth, int bpp)
6697 {
6698         struct drm_i915_gem_object *obj;
6699         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
6700
6701         obj = i915_gem_alloc_object(dev,
6702                                     intel_framebuffer_size_for_mode(mode, bpp));
6703         if (obj == NULL)
6704                 return ERR_PTR(-ENOMEM);
6705
6706         mode_cmd.width = mode->hdisplay;
6707         mode_cmd.height = mode->vdisplay;
6708         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6709                                                                 bpp);
6710         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6711
6712         return intel_framebuffer_create(dev, &mode_cmd, obj);
6713 }
6714
6715 static struct drm_framebuffer *
6716 mode_fits_in_fbdev(struct drm_device *dev,
6717                    struct drm_display_mode *mode)
6718 {
6719         struct drm_i915_private *dev_priv = dev->dev_private;
6720         struct drm_i915_gem_object *obj;
6721         struct drm_framebuffer *fb;
6722
6723         if (dev_priv->fbdev == NULL)
6724                 return NULL;
6725
6726         obj = dev_priv->fbdev->ifb.obj;
6727         if (obj == NULL)
6728                 return NULL;
6729
6730         fb = &dev_priv->fbdev->ifb.base;
6731         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6732                                                                fb->bits_per_pixel))
6733                 return NULL;
6734
6735         if (obj->base.size < mode->vdisplay * fb->pitches[0])
6736                 return NULL;
6737
6738         return fb;
6739 }
6740
6741 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6742                                 struct drm_display_mode *mode,
6743                                 struct intel_load_detect_pipe *old)
6744 {
6745         struct intel_crtc *intel_crtc;
6746         struct intel_encoder *intel_encoder =
6747                 intel_attached_encoder(connector);
6748         struct drm_crtc *possible_crtc;
6749         struct drm_encoder *encoder = &intel_encoder->base;
6750         struct drm_crtc *crtc = NULL;
6751         struct drm_device *dev = encoder->dev;
6752         struct drm_framebuffer *fb;
6753         int i = -1;
6754
6755         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6756                       connector->base.id, drm_get_connector_name(connector),
6757                       encoder->base.id, drm_get_encoder_name(encoder));
6758
6759         /*
6760          * Algorithm gets a little messy:
6761          *
6762          *   - if the connector already has an assigned crtc, use it (but make
6763          *     sure it's on first)
6764          *
6765          *   - try to find the first unused crtc that can drive this connector,
6766          *     and use that if we find one
6767          */
6768
6769         /* See if we already have a CRTC for this connector */
6770         if (encoder->crtc) {
6771                 crtc = encoder->crtc;
6772
6773                 mutex_lock(&crtc->mutex);
6774
6775                 old->dpms_mode = connector->dpms;
6776                 old->load_detect_temp = false;
6777
6778                 /* Make sure the crtc and connector are running */
6779                 if (connector->dpms != DRM_MODE_DPMS_ON)
6780                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6781
6782                 return true;
6783         }
6784
6785         /* Find an unused one (if possible) */
6786         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6787                 i++;
6788                 if (!(encoder->possible_crtcs & (1 << i)))
6789                         continue;
6790                 if (!possible_crtc->enabled) {
6791                         crtc = possible_crtc;
6792                         break;
6793                 }
6794         }
6795
6796         /*
6797          * If we didn't find an unused CRTC, don't use any.
6798          */
6799         if (!crtc) {
6800                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6801                 return false;
6802         }
6803
6804         mutex_lock(&crtc->mutex);
6805         intel_encoder->new_crtc = to_intel_crtc(crtc);
6806         to_intel_connector(connector)->new_encoder = intel_encoder;
6807
6808         intel_crtc = to_intel_crtc(crtc);
6809         old->dpms_mode = connector->dpms;
6810         old->load_detect_temp = true;
6811         old->release_fb = NULL;
6812
6813         if (!mode)
6814                 mode = &load_detect_mode;
6815
6816         /* We need a framebuffer large enough to accommodate all accesses
6817          * that the plane may generate whilst we perform load detection.
6818          * We can not rely on the fbcon either being present (we get called
6819          * during its initialisation to detect all boot displays, or it may
6820          * not even exist) or that it is large enough to satisfy the
6821          * requested mode.
6822          */
6823         fb = mode_fits_in_fbdev(dev, mode);
6824         if (fb == NULL) {
6825                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6826                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6827                 old->release_fb = fb;
6828         } else
6829                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6830         if (IS_ERR(fb)) {
6831                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6832                 mutex_unlock(&crtc->mutex);
6833                 return false;
6834         }
6835
6836         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6837                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6838                 if (old->release_fb)
6839                         old->release_fb->funcs->destroy(old->release_fb);
6840                 mutex_unlock(&crtc->mutex);
6841                 return false;
6842         }
6843
6844         /* let the connector get through one full cycle before testing */
6845         intel_wait_for_vblank(dev, intel_crtc->pipe);
6846         return true;
6847 }
6848
6849 void intel_release_load_detect_pipe(struct drm_connector *connector,
6850                                     struct intel_load_detect_pipe *old)
6851 {
6852         struct intel_encoder *intel_encoder =
6853                 intel_attached_encoder(connector);
6854         struct drm_encoder *encoder = &intel_encoder->base;
6855         struct drm_crtc *crtc = encoder->crtc;
6856
6857         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6858                       connector->base.id, drm_get_connector_name(connector),
6859                       encoder->base.id, drm_get_encoder_name(encoder));
6860
6861         if (old->load_detect_temp) {
6862                 to_intel_connector(connector)->new_encoder = NULL;
6863                 intel_encoder->new_crtc = NULL;
6864                 intel_set_mode(crtc, NULL, 0, 0, NULL);
6865
6866                 if (old->release_fb) {
6867                         drm_framebuffer_unregister_private(old->release_fb);
6868                         drm_framebuffer_unreference(old->release_fb);
6869                 }
6870
6871                 mutex_unlock(&crtc->mutex);
6872                 return;
6873         }
6874
6875         /* Switch crtc and encoder back off if necessary */
6876         if (old->dpms_mode != DRM_MODE_DPMS_ON)
6877                 connector->funcs->dpms(connector, old->dpms_mode);
6878
6879         mutex_unlock(&crtc->mutex);
6880 }
6881
6882 /* Returns the clock of the currently programmed mode of the given pipe. */
6883 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6884 {
6885         struct drm_i915_private *dev_priv = dev->dev_private;
6886         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6887         int pipe = intel_crtc->pipe;
6888         u32 dpll = I915_READ(DPLL(pipe));
6889         u32 fp;
6890         intel_clock_t clock;
6891
6892         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6893                 fp = I915_READ(FP0(pipe));
6894         else
6895                 fp = I915_READ(FP1(pipe));
6896
6897         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6898         if (IS_PINEVIEW(dev)) {
6899                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6900                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6901         } else {
6902                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6903                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6904         }
6905
6906         if (!IS_GEN2(dev)) {
6907                 if (IS_PINEVIEW(dev))
6908                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6909                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6910                 else
6911                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6912                                DPLL_FPA01_P1_POST_DIV_SHIFT);
6913
6914                 switch (dpll & DPLL_MODE_MASK) {
6915                 case DPLLB_MODE_DAC_SERIAL:
6916                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6917                                 5 : 10;
6918                         break;
6919                 case DPLLB_MODE_LVDS:
6920                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6921                                 7 : 14;
6922                         break;
6923                 default:
6924                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6925                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
6926                         return 0;
6927                 }
6928
6929                 if (IS_PINEVIEW(dev))
6930                         pineview_clock(96000, &clock);
6931                 else
6932                         i9xx_clock(96000, &clock);
6933         } else {
6934                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6935
6936                 if (is_lvds) {
6937                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6938                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
6939                         clock.p2 = 14;
6940
6941                         if ((dpll & PLL_REF_INPUT_MASK) ==
6942                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6943                                 /* XXX: might not be 66MHz */
6944                                 i9xx_clock(66000, &clock);
6945                         } else
6946                                 i9xx_clock(48000, &clock);
6947                 } else {
6948                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
6949                                 clock.p1 = 2;
6950                         else {
6951                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6952                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6953                         }
6954                         if (dpll & PLL_P2_DIVIDE_BY_4)
6955                                 clock.p2 = 4;
6956                         else
6957                                 clock.p2 = 2;
6958
6959                         i9xx_clock(48000, &clock);
6960                 }
6961         }
6962
6963         /* XXX: It would be nice to validate the clocks, but we can't reuse
6964          * i830PllIsValid() because it relies on the xf86_config connector
6965          * configuration being accurate, which it isn't necessarily.
6966          */
6967
6968         return clock.dot;
6969 }
6970
6971 /** Returns the currently programmed mode of the given pipe. */
6972 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6973                                              struct drm_crtc *crtc)
6974 {
6975         struct drm_i915_private *dev_priv = dev->dev_private;
6976         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6977         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6978         struct drm_display_mode *mode;
6979         int htot = I915_READ(HTOTAL(cpu_transcoder));
6980         int hsync = I915_READ(HSYNC(cpu_transcoder));
6981         int vtot = I915_READ(VTOTAL(cpu_transcoder));
6982         int vsync = I915_READ(VSYNC(cpu_transcoder));
6983
6984         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6985         if (!mode)
6986                 return NULL;
6987
6988         mode->clock = intel_crtc_clock_get(dev, crtc);
6989         mode->hdisplay = (htot & 0xffff) + 1;
6990         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6991         mode->hsync_start = (hsync & 0xffff) + 1;
6992         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6993         mode->vdisplay = (vtot & 0xffff) + 1;
6994         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6995         mode->vsync_start = (vsync & 0xffff) + 1;
6996         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6997
6998         drm_mode_set_name(mode);
6999
7000         return mode;
7001 }
7002
7003 static void intel_increase_pllclock(struct drm_crtc *crtc)
7004 {
7005         struct drm_device *dev = crtc->dev;
7006         drm_i915_private_t *dev_priv = dev->dev_private;
7007         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7008         int pipe = intel_crtc->pipe;
7009         int dpll_reg = DPLL(pipe);
7010         int dpll;
7011
7012         if (HAS_PCH_SPLIT(dev))
7013                 return;
7014
7015         if (!dev_priv->lvds_downclock_avail)
7016                 return;
7017
7018         dpll = I915_READ(dpll_reg);
7019         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
7020                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
7021
7022                 assert_panel_unlocked(dev_priv, pipe);
7023
7024                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7025                 I915_WRITE(dpll_reg, dpll);
7026                 intel_wait_for_vblank(dev, pipe);
7027
7028                 dpll = I915_READ(dpll_reg);
7029                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
7030                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7031         }
7032 }
7033
7034 static void intel_decrease_pllclock(struct drm_crtc *crtc)
7035 {
7036         struct drm_device *dev = crtc->dev;
7037         drm_i915_private_t *dev_priv = dev->dev_private;
7038         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7039
7040         if (HAS_PCH_SPLIT(dev))
7041                 return;
7042
7043         if (!dev_priv->lvds_downclock_avail)
7044                 return;
7045
7046         /*
7047          * Since this is called by a timer, we should never get here in
7048          * the manual case.
7049          */
7050         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
7051                 int pipe = intel_crtc->pipe;
7052                 int dpll_reg = DPLL(pipe);
7053                 int dpll;
7054
7055                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7056
7057                 assert_panel_unlocked(dev_priv, pipe);
7058
7059                 dpll = I915_READ(dpll_reg);
7060                 dpll |= DISPLAY_RATE_SELECT_FPA1;
7061                 I915_WRITE(dpll_reg, dpll);
7062                 intel_wait_for_vblank(dev, pipe);
7063                 dpll = I915_READ(dpll_reg);
7064                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
7065                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7066         }
7067
7068 }
7069
7070 void intel_mark_busy(struct drm_device *dev)
7071 {
7072         i915_update_gfx_val(dev->dev_private);
7073 }
7074
7075 void intel_mark_idle(struct drm_device *dev)
7076 {
7077         struct drm_crtc *crtc;
7078
7079         if (!i915_powersave)
7080                 return;
7081
7082         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7083                 if (!crtc->fb)
7084                         continue;
7085
7086                 intel_decrease_pllclock(crtc);
7087         }
7088 }
7089
7090 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7091                         struct intel_ring_buffer *ring)
7092 {
7093         struct drm_device *dev = obj->base.dev;
7094         struct drm_crtc *crtc;
7095
7096         if (!i915_powersave)
7097                 return;
7098
7099         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7100                 if (!crtc->fb)
7101                         continue;
7102
7103                 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7104                         continue;
7105
7106                 intel_increase_pllclock(crtc);
7107                 if (ring && intel_fbc_enabled(dev))
7108                         ring->fbc_dirty = true;
7109         }
7110 }
7111
7112 static void intel_crtc_destroy(struct drm_crtc *crtc)
7113 {
7114         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7115         struct drm_device *dev = crtc->dev;
7116         struct intel_unpin_work *work;
7117         unsigned long flags;
7118
7119         spin_lock_irqsave(&dev->event_lock, flags);
7120         work = intel_crtc->unpin_work;
7121         intel_crtc->unpin_work = NULL;
7122         spin_unlock_irqrestore(&dev->event_lock, flags);
7123
7124         if (work) {
7125                 cancel_work_sync(&work->work);
7126                 kfree(work);
7127         }
7128
7129         intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7130
7131         drm_crtc_cleanup(crtc);
7132
7133         kfree(intel_crtc);
7134 }
7135
7136 static void intel_unpin_work_fn(struct work_struct *__work)
7137 {
7138         struct intel_unpin_work *work =
7139                 container_of(__work, struct intel_unpin_work, work);
7140         struct drm_device *dev = work->crtc->dev;
7141
7142         mutex_lock(&dev->struct_mutex);
7143         intel_unpin_fb_obj(work->old_fb_obj);
7144         drm_gem_object_unreference(&work->pending_flip_obj->base);
7145         drm_gem_object_unreference(&work->old_fb_obj->base);
7146
7147         intel_update_fbc(dev);
7148         mutex_unlock(&dev->struct_mutex);
7149
7150         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7151         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7152
7153         kfree(work);
7154 }
7155
7156 static void do_intel_finish_page_flip(struct drm_device *dev,
7157                                       struct drm_crtc *crtc)
7158 {
7159         drm_i915_private_t *dev_priv = dev->dev_private;
7160         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7161         struct intel_unpin_work *work;
7162         unsigned long flags;
7163
7164         /* Ignore early vblank irqs */
7165         if (intel_crtc == NULL)
7166                 return;
7167
7168         spin_lock_irqsave(&dev->event_lock, flags);
7169         work = intel_crtc->unpin_work;
7170
7171         /* Ensure we don't miss a work->pending update ... */
7172         smp_rmb();
7173
7174         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
7175                 spin_unlock_irqrestore(&dev->event_lock, flags);
7176                 return;
7177         }
7178
7179         /* and that the unpin work is consistent wrt ->pending. */
7180         smp_rmb();
7181
7182         intel_crtc->unpin_work = NULL;
7183
7184         if (work->event)
7185                 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
7186
7187         drm_vblank_put(dev, intel_crtc->pipe);
7188
7189         spin_unlock_irqrestore(&dev->event_lock, flags);
7190
7191         wake_up_all(&dev_priv->pending_flip_queue);
7192
7193         queue_work(dev_priv->wq, &work->work);
7194
7195         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7196 }
7197
7198 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7199 {
7200         drm_i915_private_t *dev_priv = dev->dev_private;
7201         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7202
7203         do_intel_finish_page_flip(dev, crtc);
7204 }
7205
7206 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7207 {
7208         drm_i915_private_t *dev_priv = dev->dev_private;
7209         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7210
7211         do_intel_finish_page_flip(dev, crtc);
7212 }
7213
7214 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7215 {
7216         drm_i915_private_t *dev_priv = dev->dev_private;
7217         struct intel_crtc *intel_crtc =
7218                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7219         unsigned long flags;
7220
7221         /* NB: An MMIO update of the plane base pointer will also
7222          * generate a page-flip completion irq, i.e. every modeset
7223          * is also accompanied by a spurious intel_prepare_page_flip().
7224          */
7225         spin_lock_irqsave(&dev->event_lock, flags);
7226         if (intel_crtc->unpin_work)
7227                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
7228         spin_unlock_irqrestore(&dev->event_lock, flags);
7229 }
7230
7231 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7232 {
7233         /* Ensure that the work item is consistent when activating it ... */
7234         smp_wmb();
7235         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7236         /* and that it is marked active as soon as the irq could fire. */
7237         smp_wmb();
7238 }
7239
7240 static int intel_gen2_queue_flip(struct drm_device *dev,
7241                                  struct drm_crtc *crtc,
7242                                  struct drm_framebuffer *fb,
7243                                  struct drm_i915_gem_object *obj)
7244 {
7245         struct drm_i915_private *dev_priv = dev->dev_private;
7246         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7247         u32 flip_mask;
7248         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7249         int ret;
7250
7251         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7252         if (ret)
7253                 goto err;
7254
7255         ret = intel_ring_begin(ring, 6);
7256         if (ret)
7257                 goto err_unpin;
7258
7259         /* Can't queue multiple flips, so wait for the previous
7260          * one to finish before executing the next.
7261          */
7262         if (intel_crtc->plane)
7263                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7264         else
7265                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7266         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7267         intel_ring_emit(ring, MI_NOOP);
7268         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7269                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7270         intel_ring_emit(ring, fb->pitches[0]);
7271         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7272         intel_ring_emit(ring, 0); /* aux display base address, unused */
7273
7274         intel_mark_page_flip_active(intel_crtc);
7275         intel_ring_advance(ring);
7276         return 0;
7277
7278 err_unpin:
7279         intel_unpin_fb_obj(obj);
7280 err:
7281         return ret;
7282 }
7283
7284 static int intel_gen3_queue_flip(struct drm_device *dev,
7285                                  struct drm_crtc *crtc,
7286                                  struct drm_framebuffer *fb,
7287                                  struct drm_i915_gem_object *obj)
7288 {
7289         struct drm_i915_private *dev_priv = dev->dev_private;
7290         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7291         u32 flip_mask;
7292         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7293         int ret;
7294
7295         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7296         if (ret)
7297                 goto err;
7298
7299         ret = intel_ring_begin(ring, 6);
7300         if (ret)
7301                 goto err_unpin;
7302
7303         if (intel_crtc->plane)
7304                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7305         else
7306                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7307         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7308         intel_ring_emit(ring, MI_NOOP);
7309         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7310                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7311         intel_ring_emit(ring, fb->pitches[0]);
7312         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7313         intel_ring_emit(ring, MI_NOOP);
7314
7315         intel_mark_page_flip_active(intel_crtc);
7316         intel_ring_advance(ring);
7317         return 0;
7318
7319 err_unpin:
7320         intel_unpin_fb_obj(obj);
7321 err:
7322         return ret;
7323 }
7324
7325 static int intel_gen4_queue_flip(struct drm_device *dev,
7326                                  struct drm_crtc *crtc,
7327                                  struct drm_framebuffer *fb,
7328                                  struct drm_i915_gem_object *obj)
7329 {
7330         struct drm_i915_private *dev_priv = dev->dev_private;
7331         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7332         uint32_t pf, pipesrc;
7333         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7334         int ret;
7335
7336         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7337         if (ret)
7338                 goto err;
7339
7340         ret = intel_ring_begin(ring, 4);
7341         if (ret)
7342                 goto err_unpin;
7343
7344         /* i965+ uses the linear or tiled offsets from the
7345          * Display Registers (which do not change across a page-flip)
7346          * so we need only reprogram the base address.
7347          */
7348         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7349                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7350         intel_ring_emit(ring, fb->pitches[0]);
7351         intel_ring_emit(ring,
7352                         (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7353                         obj->tiling_mode);
7354
7355         /* XXX Enabling the panel-fitter across page-flip is so far
7356          * untested on non-native modes, so ignore it for now.
7357          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7358          */
7359         pf = 0;
7360         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7361         intel_ring_emit(ring, pf | pipesrc);
7362
7363         intel_mark_page_flip_active(intel_crtc);
7364         intel_ring_advance(ring);
7365         return 0;
7366
7367 err_unpin:
7368         intel_unpin_fb_obj(obj);
7369 err:
7370         return ret;
7371 }
7372
7373 static int intel_gen6_queue_flip(struct drm_device *dev,
7374                                  struct drm_crtc *crtc,
7375                                  struct drm_framebuffer *fb,
7376                                  struct drm_i915_gem_object *obj)
7377 {
7378         struct drm_i915_private *dev_priv = dev->dev_private;
7379         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7380         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7381         uint32_t pf, pipesrc;
7382         int ret;
7383
7384         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7385         if (ret)
7386                 goto err;
7387
7388         ret = intel_ring_begin(ring, 4);
7389         if (ret)
7390                 goto err_unpin;
7391
7392         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7393                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7394         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7395         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7396
7397         /* Contrary to the suggestions in the documentation,
7398          * "Enable Panel Fitter" does not seem to be required when page
7399          * flipping with a non-native mode, and worse causes a normal
7400          * modeset to fail.
7401          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7402          */
7403         pf = 0;
7404         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7405         intel_ring_emit(ring, pf | pipesrc);
7406
7407         intel_mark_page_flip_active(intel_crtc);
7408         intel_ring_advance(ring);
7409         return 0;
7410
7411 err_unpin:
7412         intel_unpin_fb_obj(obj);
7413 err:
7414         return ret;
7415 }
7416
7417 /*
7418  * On gen7 we currently use the blit ring because (in early silicon at least)
7419  * the render ring doesn't give us interrpts for page flip completion, which
7420  * means clients will hang after the first flip is queued.  Fortunately the
7421  * blit ring generates interrupts properly, so use it instead.
7422  */
7423 static int intel_gen7_queue_flip(struct drm_device *dev,
7424                                  struct drm_crtc *crtc,
7425                                  struct drm_framebuffer *fb,
7426                                  struct drm_i915_gem_object *obj)
7427 {
7428         struct drm_i915_private *dev_priv = dev->dev_private;
7429         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7430         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7431         uint32_t plane_bit = 0;
7432         int ret;
7433
7434         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7435         if (ret)
7436                 goto err;
7437
7438         switch(intel_crtc->plane) {
7439         case PLANE_A:
7440                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7441                 break;
7442         case PLANE_B:
7443                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7444                 break;
7445         case PLANE_C:
7446                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7447                 break;
7448         default:
7449                 WARN_ONCE(1, "unknown plane in flip command\n");
7450                 ret = -ENODEV;
7451                 goto err_unpin;
7452         }
7453
7454         ret = intel_ring_begin(ring, 4);
7455         if (ret)
7456                 goto err_unpin;
7457
7458         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7459         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7460         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7461         intel_ring_emit(ring, (MI_NOOP));
7462
7463         intel_mark_page_flip_active(intel_crtc);
7464         intel_ring_advance(ring);
7465         return 0;
7466
7467 err_unpin:
7468         intel_unpin_fb_obj(obj);
7469 err:
7470         return ret;
7471 }
7472
7473 static int intel_default_queue_flip(struct drm_device *dev,
7474                                     struct drm_crtc *crtc,
7475                                     struct drm_framebuffer *fb,
7476                                     struct drm_i915_gem_object *obj)
7477 {
7478         return -ENODEV;
7479 }
7480
7481 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7482                                 struct drm_framebuffer *fb,
7483                                 struct drm_pending_vblank_event *event)
7484 {
7485         struct drm_device *dev = crtc->dev;
7486         struct drm_i915_private *dev_priv = dev->dev_private;
7487         struct drm_framebuffer *old_fb = crtc->fb;
7488         struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
7489         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7490         struct intel_unpin_work *work;
7491         unsigned long flags;
7492         int ret;
7493
7494         /* Can't change pixel format via MI display flips. */
7495         if (fb->pixel_format != crtc->fb->pixel_format)
7496                 return -EINVAL;
7497
7498         /*
7499          * TILEOFF/LINOFF registers can't be changed via MI display flips.
7500          * Note that pitch changes could also affect these register.
7501          */
7502         if (INTEL_INFO(dev)->gen > 3 &&
7503             (fb->offsets[0] != crtc->fb->offsets[0] ||
7504              fb->pitches[0] != crtc->fb->pitches[0]))
7505                 return -EINVAL;
7506
7507         work = kzalloc(sizeof *work, GFP_KERNEL);
7508         if (work == NULL)
7509                 return -ENOMEM;
7510
7511         work->event = event;
7512         work->crtc = crtc;
7513         work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
7514         INIT_WORK(&work->work, intel_unpin_work_fn);
7515
7516         ret = drm_vblank_get(dev, intel_crtc->pipe);
7517         if (ret)
7518                 goto free_work;
7519
7520         /* We borrow the event spin lock for protecting unpin_work */
7521         spin_lock_irqsave(&dev->event_lock, flags);
7522         if (intel_crtc->unpin_work) {
7523                 spin_unlock_irqrestore(&dev->event_lock, flags);
7524                 kfree(work);
7525                 drm_vblank_put(dev, intel_crtc->pipe);
7526
7527                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7528                 return -EBUSY;
7529         }
7530         intel_crtc->unpin_work = work;
7531         spin_unlock_irqrestore(&dev->event_lock, flags);
7532
7533         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7534                 flush_workqueue(dev_priv->wq);
7535
7536         ret = i915_mutex_lock_interruptible(dev);
7537         if (ret)
7538                 goto cleanup;
7539
7540         /* Reference the objects for the scheduled work. */
7541         drm_gem_object_reference(&work->old_fb_obj->base);
7542         drm_gem_object_reference(&obj->base);
7543
7544         crtc->fb = fb;
7545
7546         work->pending_flip_obj = obj;
7547
7548         work->enable_stall_check = true;
7549
7550         atomic_inc(&intel_crtc->unpin_work_count);
7551         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
7552
7553         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7554         if (ret)
7555                 goto cleanup_pending;
7556
7557         intel_disable_fbc(dev);
7558         intel_mark_fb_busy(obj, NULL);
7559         mutex_unlock(&dev->struct_mutex);
7560
7561         trace_i915_flip_request(intel_crtc->plane, obj);
7562
7563         return 0;
7564
7565 cleanup_pending:
7566         atomic_dec(&intel_crtc->unpin_work_count);
7567         crtc->fb = old_fb;
7568         drm_gem_object_unreference(&work->old_fb_obj->base);
7569         drm_gem_object_unreference(&obj->base);
7570         mutex_unlock(&dev->struct_mutex);
7571
7572 cleanup:
7573         spin_lock_irqsave(&dev->event_lock, flags);
7574         intel_crtc->unpin_work = NULL;
7575         spin_unlock_irqrestore(&dev->event_lock, flags);
7576
7577         drm_vblank_put(dev, intel_crtc->pipe);
7578 free_work:
7579         kfree(work);
7580
7581         return ret;
7582 }
7583
7584 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7585         .mode_set_base_atomic = intel_pipe_set_base_atomic,
7586         .load_lut = intel_crtc_load_lut,
7587 };
7588
7589 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7590                                   struct drm_crtc *crtc)
7591 {
7592         struct drm_device *dev;
7593         struct drm_crtc *tmp;
7594         int crtc_mask = 1;
7595
7596         WARN(!crtc, "checking null crtc?\n");
7597
7598         dev = crtc->dev;
7599
7600         list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7601                 if (tmp == crtc)
7602                         break;
7603                 crtc_mask <<= 1;
7604         }
7605
7606         if (encoder->possible_crtcs & crtc_mask)
7607                 return true;
7608         return false;
7609 }
7610
7611 /**
7612  * intel_modeset_update_staged_output_state
7613  *
7614  * Updates the staged output configuration state, e.g. after we've read out the
7615  * current hw state.
7616  */
7617 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7618 {
7619         struct intel_encoder *encoder;
7620         struct intel_connector *connector;
7621
7622         list_for_each_entry(connector, &dev->mode_config.connector_list,
7623                             base.head) {
7624                 connector->new_encoder =
7625                         to_intel_encoder(connector->base.encoder);
7626         }
7627
7628         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7629                             base.head) {
7630                 encoder->new_crtc =
7631                         to_intel_crtc(encoder->base.crtc);
7632         }
7633 }
7634
7635 /**
7636  * intel_modeset_commit_output_state
7637  *
7638  * This function copies the stage display pipe configuration to the real one.
7639  */
7640 static void intel_modeset_commit_output_state(struct drm_device *dev)
7641 {
7642         struct intel_encoder *encoder;
7643         struct intel_connector *connector;
7644
7645         list_for_each_entry(connector, &dev->mode_config.connector_list,
7646                             base.head) {
7647                 connector->base.encoder = &connector->new_encoder->base;
7648         }
7649
7650         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7651                             base.head) {
7652                 encoder->base.crtc = &encoder->new_crtc->base;
7653         }
7654 }
7655
7656 static void
7657 connected_sink_compute_bpp(struct intel_connector * connector,
7658                            struct intel_crtc_config *pipe_config)
7659 {
7660         int bpp = pipe_config->pipe_bpp;
7661
7662         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
7663                 connector->base.base.id,
7664                 drm_get_connector_name(&connector->base));
7665
7666         /* Don't use an invalid EDID bpc value */
7667         if (connector->base.display_info.bpc &&
7668             connector->base.display_info.bpc * 3 < bpp) {
7669                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7670                               bpp, connector->base.display_info.bpc*3);
7671                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
7672         }
7673
7674         /* Clamp bpp to 8 on screens without EDID 1.4 */
7675         if (connector->base.display_info.bpc == 0 && bpp > 24) {
7676                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
7677                               bpp);
7678                 pipe_config->pipe_bpp = 24;
7679         }
7680 }
7681
7682 static int
7683 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
7684                           struct drm_framebuffer *fb,
7685                           struct intel_crtc_config *pipe_config)
7686 {
7687         struct drm_device *dev = crtc->base.dev;
7688         struct intel_connector *connector;
7689         int bpp;
7690
7691         switch (fb->pixel_format) {
7692         case DRM_FORMAT_C8:
7693                 bpp = 8*3; /* since we go through a colormap */
7694                 break;
7695         case DRM_FORMAT_XRGB1555:
7696         case DRM_FORMAT_ARGB1555:
7697                 /* checked in intel_framebuffer_init already */
7698                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7699                         return -EINVAL;
7700         case DRM_FORMAT_RGB565:
7701                 bpp = 6*3; /* min is 18bpp */
7702                 break;
7703         case DRM_FORMAT_XBGR8888:
7704         case DRM_FORMAT_ABGR8888:
7705                 /* checked in intel_framebuffer_init already */
7706                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7707                         return -EINVAL;
7708         case DRM_FORMAT_XRGB8888:
7709         case DRM_FORMAT_ARGB8888:
7710                 bpp = 8*3;
7711                 break;
7712         case DRM_FORMAT_XRGB2101010:
7713         case DRM_FORMAT_ARGB2101010:
7714         case DRM_FORMAT_XBGR2101010:
7715         case DRM_FORMAT_ABGR2101010:
7716                 /* checked in intel_framebuffer_init already */
7717                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7718                         return -EINVAL;
7719                 bpp = 10*3;
7720                 break;
7721         /* TODO: gen4+ supports 16 bpc floating point, too. */
7722         default:
7723                 DRM_DEBUG_KMS("unsupported depth\n");
7724                 return -EINVAL;
7725         }
7726
7727         pipe_config->pipe_bpp = bpp;
7728
7729         /* Clamp display bpp to EDID value */
7730         list_for_each_entry(connector, &dev->mode_config.connector_list,
7731                             base.head) {
7732                 if (!connector->new_encoder ||
7733                     connector->new_encoder->new_crtc != crtc)
7734                         continue;
7735
7736                 connected_sink_compute_bpp(connector, pipe_config);
7737         }
7738
7739         return bpp;
7740 }
7741
7742 static void intel_dump_pipe_config(struct intel_crtc *crtc,
7743                                    struct intel_crtc_config *pipe_config,
7744                                    const char *context)
7745 {
7746         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
7747                       context, pipe_name(crtc->pipe));
7748
7749         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
7750         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
7751                       pipe_config->pipe_bpp, pipe_config->dither);
7752         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
7753                       pipe_config->has_pch_encoder,
7754                       pipe_config->fdi_lanes,
7755                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
7756                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
7757                       pipe_config->fdi_m_n.tu);
7758         DRM_DEBUG_KMS("requested mode:\n");
7759         drm_mode_debug_printmodeline(&pipe_config->requested_mode);
7760         DRM_DEBUG_KMS("adjusted mode:\n");
7761         drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
7762         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
7763                       pipe_config->gmch_pfit.control,
7764                       pipe_config->gmch_pfit.pgm_ratios,
7765                       pipe_config->gmch_pfit.lvds_border_bits);
7766         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
7767                       pipe_config->pch_pfit.pos,
7768                       pipe_config->pch_pfit.size);
7769         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
7770 }
7771
7772 static bool check_encoder_cloning(struct drm_crtc *crtc)
7773 {
7774         int num_encoders = 0;
7775         bool uncloneable_encoders = false;
7776         struct intel_encoder *encoder;
7777
7778         list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
7779                             base.head) {
7780                 if (&encoder->new_crtc->base != crtc)
7781                         continue;
7782
7783                 num_encoders++;
7784                 if (!encoder->cloneable)
7785                         uncloneable_encoders = true;
7786         }
7787
7788         return !(num_encoders > 1 && uncloneable_encoders);
7789 }
7790
7791 static struct intel_crtc_config *
7792 intel_modeset_pipe_config(struct drm_crtc *crtc,
7793                           struct drm_framebuffer *fb,
7794                           struct drm_display_mode *mode)
7795 {
7796         struct drm_device *dev = crtc->dev;
7797         struct drm_encoder_helper_funcs *encoder_funcs;
7798         struct intel_encoder *encoder;
7799         struct intel_crtc_config *pipe_config;
7800         int plane_bpp, ret = -EINVAL;
7801         bool retry = true;
7802
7803         if (!check_encoder_cloning(crtc)) {
7804                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
7805                 return ERR_PTR(-EINVAL);
7806         }
7807
7808         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7809         if (!pipe_config)
7810                 return ERR_PTR(-ENOMEM);
7811
7812         drm_mode_copy(&pipe_config->adjusted_mode, mode);
7813         drm_mode_copy(&pipe_config->requested_mode, mode);
7814         pipe_config->cpu_transcoder = to_intel_crtc(crtc)->pipe;
7815         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7816
7817         /* Compute a starting value for pipe_config->pipe_bpp taking the source
7818          * plane pixel format and any sink constraints into account. Returns the
7819          * source plane bpp so that dithering can be selected on mismatches
7820          * after encoders and crtc also have had their say. */
7821         plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
7822                                               fb, pipe_config);
7823         if (plane_bpp < 0)
7824                 goto fail;
7825
7826 encoder_retry:
7827         /* Ensure the port clock defaults are reset when retrying. */
7828         pipe_config->port_clock = 0;
7829         pipe_config->pixel_multiplier = 1;
7830
7831         /* Pass our mode to the connectors and the CRTC to give them a chance to
7832          * adjust it according to limitations or connector properties, and also
7833          * a chance to reject the mode entirely.
7834          */
7835         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7836                             base.head) {
7837
7838                 if (&encoder->new_crtc->base != crtc)
7839                         continue;
7840
7841                 if (encoder->compute_config) {
7842                         if (!(encoder->compute_config(encoder, pipe_config))) {
7843                                 DRM_DEBUG_KMS("Encoder config failure\n");
7844                                 goto fail;
7845                         }
7846
7847                         continue;
7848                 }
7849
7850                 encoder_funcs = encoder->base.helper_private;
7851                 if (!(encoder_funcs->mode_fixup(&encoder->base,
7852                                                 &pipe_config->requested_mode,
7853                                                 &pipe_config->adjusted_mode))) {
7854                         DRM_DEBUG_KMS("Encoder fixup failed\n");
7855                         goto fail;
7856                 }
7857         }
7858
7859         /* Set default port clock if not overwritten by the encoder. Needs to be
7860          * done afterwards in case the encoder adjusts the mode. */
7861         if (!pipe_config->port_clock)
7862                 pipe_config->port_clock = pipe_config->adjusted_mode.clock;
7863
7864         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
7865         if (ret < 0) {
7866                 DRM_DEBUG_KMS("CRTC fixup failed\n");
7867                 goto fail;
7868         }
7869
7870         if (ret == RETRY) {
7871                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
7872                         ret = -EINVAL;
7873                         goto fail;
7874                 }
7875
7876                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
7877                 retry = false;
7878                 goto encoder_retry;
7879         }
7880
7881         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7882         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7883                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7884
7885         return pipe_config;
7886 fail:
7887         kfree(pipe_config);
7888         return ERR_PTR(ret);
7889 }
7890
7891 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7892  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7893 static void
7894 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7895                              unsigned *prepare_pipes, unsigned *disable_pipes)
7896 {
7897         struct intel_crtc *intel_crtc;
7898         struct drm_device *dev = crtc->dev;
7899         struct intel_encoder *encoder;
7900         struct intel_connector *connector;
7901         struct drm_crtc *tmp_crtc;
7902
7903         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7904
7905         /* Check which crtcs have changed outputs connected to them, these need
7906          * to be part of the prepare_pipes mask. We don't (yet) support global
7907          * modeset across multiple crtcs, so modeset_pipes will only have one
7908          * bit set at most. */
7909         list_for_each_entry(connector, &dev->mode_config.connector_list,
7910                             base.head) {
7911                 if (connector->base.encoder == &connector->new_encoder->base)
7912                         continue;
7913
7914                 if (connector->base.encoder) {
7915                         tmp_crtc = connector->base.encoder->crtc;
7916
7917                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7918                 }
7919
7920                 if (connector->new_encoder)
7921                         *prepare_pipes |=
7922                                 1 << connector->new_encoder->new_crtc->pipe;
7923         }
7924
7925         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7926                             base.head) {
7927                 if (encoder->base.crtc == &encoder->new_crtc->base)
7928                         continue;
7929
7930                 if (encoder->base.crtc) {
7931                         tmp_crtc = encoder->base.crtc;
7932
7933                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7934                 }
7935
7936                 if (encoder->new_crtc)
7937                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7938         }
7939
7940         /* Check for any pipes that will be fully disabled ... */
7941         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7942                             base.head) {
7943                 bool used = false;
7944
7945                 /* Don't try to disable disabled crtcs. */
7946                 if (!intel_crtc->base.enabled)
7947                         continue;
7948
7949                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7950                                     base.head) {
7951                         if (encoder->new_crtc == intel_crtc)
7952                                 used = true;
7953                 }
7954
7955                 if (!used)
7956                         *disable_pipes |= 1 << intel_crtc->pipe;
7957         }
7958
7959
7960         /* set_mode is also used to update properties on life display pipes. */
7961         intel_crtc = to_intel_crtc(crtc);
7962         if (crtc->enabled)
7963                 *prepare_pipes |= 1 << intel_crtc->pipe;
7964
7965         /*
7966          * For simplicity do a full modeset on any pipe where the output routing
7967          * changed. We could be more clever, but that would require us to be
7968          * more careful with calling the relevant encoder->mode_set functions.
7969          */
7970         if (*prepare_pipes)
7971                 *modeset_pipes = *prepare_pipes;
7972
7973         /* ... and mask these out. */
7974         *modeset_pipes &= ~(*disable_pipes);
7975         *prepare_pipes &= ~(*disable_pipes);
7976
7977         /*
7978          * HACK: We don't (yet) fully support global modesets. intel_set_config
7979          * obies this rule, but the modeset restore mode of
7980          * intel_modeset_setup_hw_state does not.
7981          */
7982         *modeset_pipes &= 1 << intel_crtc->pipe;
7983         *prepare_pipes &= 1 << intel_crtc->pipe;
7984
7985         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7986                       *modeset_pipes, *prepare_pipes, *disable_pipes);
7987 }
7988
7989 static bool intel_crtc_in_use(struct drm_crtc *crtc)
7990 {
7991         struct drm_encoder *encoder;
7992         struct drm_device *dev = crtc->dev;
7993
7994         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7995                 if (encoder->crtc == crtc)
7996                         return true;
7997
7998         return false;
7999 }
8000
8001 static void
8002 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8003 {
8004         struct intel_encoder *intel_encoder;
8005         struct intel_crtc *intel_crtc;
8006         struct drm_connector *connector;
8007
8008         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8009                             base.head) {
8010                 if (!intel_encoder->base.crtc)
8011                         continue;
8012
8013                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8014
8015                 if (prepare_pipes & (1 << intel_crtc->pipe))
8016                         intel_encoder->connectors_active = false;
8017         }
8018
8019         intel_modeset_commit_output_state(dev);
8020
8021         /* Update computed state. */
8022         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8023                             base.head) {
8024                 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8025         }
8026
8027         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8028                 if (!connector->encoder || !connector->encoder->crtc)
8029                         continue;
8030
8031                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8032
8033                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
8034                         struct drm_property *dpms_property =
8035                                 dev->mode_config.dpms_property;
8036
8037                         connector->dpms = DRM_MODE_DPMS_ON;
8038                         drm_object_property_set_value(&connector->base,
8039                                                          dpms_property,
8040                                                          DRM_MODE_DPMS_ON);
8041
8042                         intel_encoder = to_intel_encoder(connector->encoder);
8043                         intel_encoder->connectors_active = true;
8044                 }
8045         }
8046
8047 }
8048
8049 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8050         list_for_each_entry((intel_crtc), \
8051                             &(dev)->mode_config.crtc_list, \
8052                             base.head) \
8053                 if (mask & (1 <<(intel_crtc)->pipe))
8054
8055 static bool
8056 intel_pipe_config_compare(struct drm_device *dev,
8057                           struct intel_crtc_config *current_config,
8058                           struct intel_crtc_config *pipe_config)
8059 {
8060 #define PIPE_CONF_CHECK_X(name) \
8061         if (current_config->name != pipe_config->name) { \
8062                 DRM_ERROR("mismatch in " #name " " \
8063                           "(expected 0x%08x, found 0x%08x)\n", \
8064                           current_config->name, \
8065                           pipe_config->name); \
8066                 return false; \
8067         }
8068
8069 #define PIPE_CONF_CHECK_I(name) \
8070         if (current_config->name != pipe_config->name) { \
8071                 DRM_ERROR("mismatch in " #name " " \
8072                           "(expected %i, found %i)\n", \
8073                           current_config->name, \
8074                           pipe_config->name); \
8075                 return false; \
8076         }
8077
8078 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
8079         if ((current_config->name ^ pipe_config->name) & (mask)) { \
8080                 DRM_ERROR("mismatch in " #name " " \
8081                           "(expected %i, found %i)\n", \
8082                           current_config->name & (mask), \
8083                           pipe_config->name & (mask)); \
8084                 return false; \
8085         }
8086
8087 #define PIPE_CONF_QUIRK(quirk)  \
8088         ((current_config->quirks | pipe_config->quirks) & (quirk))
8089
8090         PIPE_CONF_CHECK_I(cpu_transcoder);
8091
8092         PIPE_CONF_CHECK_I(has_pch_encoder);
8093         PIPE_CONF_CHECK_I(fdi_lanes);
8094         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8095         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8096         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8097         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8098         PIPE_CONF_CHECK_I(fdi_m_n.tu);
8099
8100         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8101         PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8102         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8103         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8104         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8105         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8106
8107         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8108         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8109         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8110         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8111         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8112         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8113
8114         if (!HAS_PCH_SPLIT(dev))
8115                 PIPE_CONF_CHECK_I(pixel_multiplier);
8116
8117         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8118                               DRM_MODE_FLAG_INTERLACE);
8119
8120         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8121                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8122                                       DRM_MODE_FLAG_PHSYNC);
8123                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8124                                       DRM_MODE_FLAG_NHSYNC);
8125                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8126                                       DRM_MODE_FLAG_PVSYNC);
8127                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8128                                       DRM_MODE_FLAG_NVSYNC);
8129         }
8130
8131         PIPE_CONF_CHECK_I(requested_mode.hdisplay);
8132         PIPE_CONF_CHECK_I(requested_mode.vdisplay);
8133
8134         PIPE_CONF_CHECK_I(gmch_pfit.control);
8135         /* pfit ratios are autocomputed by the hw on gen4+ */
8136         if (INTEL_INFO(dev)->gen < 4)
8137                 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8138         PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8139         PIPE_CONF_CHECK_I(pch_pfit.pos);
8140         PIPE_CONF_CHECK_I(pch_pfit.size);
8141
8142         PIPE_CONF_CHECK_I(ips_enabled);
8143
8144         PIPE_CONF_CHECK_I(shared_dpll);
8145         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8146         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
8147         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
8148
8149 #undef PIPE_CONF_CHECK_X
8150 #undef PIPE_CONF_CHECK_I
8151 #undef PIPE_CONF_CHECK_FLAGS
8152 #undef PIPE_CONF_QUIRK
8153
8154         return true;
8155 }
8156
8157 static void
8158 check_connector_state(struct drm_device *dev)
8159 {
8160         struct intel_connector *connector;
8161
8162         list_for_each_entry(connector, &dev->mode_config.connector_list,
8163                             base.head) {
8164                 /* This also checks the encoder/connector hw state with the
8165                  * ->get_hw_state callbacks. */
8166                 intel_connector_check_state(connector);
8167
8168                 WARN(&connector->new_encoder->base != connector->base.encoder,
8169                      "connector's staged encoder doesn't match current encoder\n");
8170         }
8171 }
8172
8173 static void
8174 check_encoder_state(struct drm_device *dev)
8175 {
8176         struct intel_encoder *encoder;
8177         struct intel_connector *connector;
8178
8179         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8180                             base.head) {
8181                 bool enabled = false;
8182                 bool active = false;
8183                 enum pipe pipe, tracked_pipe;
8184
8185                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8186                               encoder->base.base.id,
8187                               drm_get_encoder_name(&encoder->base));
8188
8189                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8190                      "encoder's stage crtc doesn't match current crtc\n");
8191                 WARN(encoder->connectors_active && !encoder->base.crtc,
8192                      "encoder's active_connectors set, but no crtc\n");
8193
8194                 list_for_each_entry(connector, &dev->mode_config.connector_list,
8195                                     base.head) {
8196                         if (connector->base.encoder != &encoder->base)
8197                                 continue;
8198                         enabled = true;
8199                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8200                                 active = true;
8201                 }
8202                 WARN(!!encoder->base.crtc != enabled,
8203                      "encoder's enabled state mismatch "
8204                      "(expected %i, found %i)\n",
8205                      !!encoder->base.crtc, enabled);
8206                 WARN(active && !encoder->base.crtc,
8207                      "active encoder with no crtc\n");
8208
8209                 WARN(encoder->connectors_active != active,
8210                      "encoder's computed active state doesn't match tracked active state "
8211                      "(expected %i, found %i)\n", active, encoder->connectors_active);
8212
8213                 active = encoder->get_hw_state(encoder, &pipe);
8214                 WARN(active != encoder->connectors_active,
8215                      "encoder's hw state doesn't match sw tracking "
8216                      "(expected %i, found %i)\n",
8217                      encoder->connectors_active, active);
8218
8219                 if (!encoder->base.crtc)
8220                         continue;
8221
8222                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8223                 WARN(active && pipe != tracked_pipe,
8224                      "active encoder's pipe doesn't match"
8225                      "(expected %i, found %i)\n",
8226                      tracked_pipe, pipe);
8227
8228         }
8229 }
8230
8231 static void
8232 check_crtc_state(struct drm_device *dev)
8233 {
8234         drm_i915_private_t *dev_priv = dev->dev_private;
8235         struct intel_crtc *crtc;
8236         struct intel_encoder *encoder;
8237         struct intel_crtc_config pipe_config;
8238
8239         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8240                             base.head) {
8241                 bool enabled = false;
8242                 bool active = false;
8243
8244                 memset(&pipe_config, 0, sizeof(pipe_config));
8245
8246                 DRM_DEBUG_KMS("[CRTC:%d]\n",
8247                               crtc->base.base.id);
8248
8249                 WARN(crtc->active && !crtc->base.enabled,
8250                      "active crtc, but not enabled in sw tracking\n");
8251
8252                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8253                                     base.head) {
8254                         if (encoder->base.crtc != &crtc->base)
8255                                 continue;
8256                         enabled = true;
8257                         if (encoder->connectors_active)
8258                                 active = true;
8259                 }
8260
8261                 WARN(active != crtc->active,
8262                      "crtc's computed active state doesn't match tracked active state "
8263                      "(expected %i, found %i)\n", active, crtc->active);
8264                 WARN(enabled != crtc->base.enabled,
8265                      "crtc's computed enabled state doesn't match tracked enabled state "
8266                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8267
8268                 active = dev_priv->display.get_pipe_config(crtc,
8269                                                            &pipe_config);
8270                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8271                                     base.head) {
8272                         if (encoder->base.crtc != &crtc->base)
8273                                 continue;
8274                         if (encoder->get_config)
8275                                 encoder->get_config(encoder, &pipe_config);
8276                 }
8277
8278                 WARN(crtc->active != active,
8279                      "crtc active state doesn't match with hw state "
8280                      "(expected %i, found %i)\n", crtc->active, active);
8281
8282                 if (active &&
8283                     !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
8284                         WARN(1, "pipe state doesn't match!\n");
8285                         intel_dump_pipe_config(crtc, &pipe_config,
8286                                                "[hw state]");
8287                         intel_dump_pipe_config(crtc, &crtc->config,
8288                                                "[sw state]");
8289                 }
8290         }
8291 }
8292
8293 static void
8294 check_shared_dpll_state(struct drm_device *dev)
8295 {
8296         drm_i915_private_t *dev_priv = dev->dev_private;
8297         struct intel_crtc *crtc;
8298         struct intel_dpll_hw_state dpll_hw_state;
8299         int i;
8300
8301         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8302                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
8303                 int enabled_crtcs = 0, active_crtcs = 0;
8304                 bool active;
8305
8306                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
8307
8308                 DRM_DEBUG_KMS("%s\n", pll->name);
8309
8310                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
8311
8312                 WARN(pll->active > pll->refcount,
8313                      "more active pll users than references: %i vs %i\n",
8314                      pll->active, pll->refcount);
8315                 WARN(pll->active && !pll->on,
8316                      "pll in active use but not on in sw tracking\n");
8317                 WARN(pll->on != active,
8318                      "pll on state mismatch (expected %i, found %i)\n",
8319                      pll->on, active);
8320
8321                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8322                                     base.head) {
8323                         if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
8324                                 enabled_crtcs++;
8325                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
8326                                 active_crtcs++;
8327                 }
8328                 WARN(pll->active != active_crtcs,
8329                      "pll active crtcs mismatch (expected %i, found %i)\n",
8330                      pll->active, active_crtcs);
8331                 WARN(pll->refcount != enabled_crtcs,
8332                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
8333                      pll->refcount, enabled_crtcs);
8334
8335                 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
8336                                        sizeof(dpll_hw_state)),
8337                      "pll hw state mismatch\n");
8338         }
8339 }
8340
8341 void
8342 intel_modeset_check_state(struct drm_device *dev)
8343 {
8344         check_connector_state(dev);
8345         check_encoder_state(dev);
8346         check_crtc_state(dev);
8347         check_shared_dpll_state(dev);
8348 }
8349
8350 static int __intel_set_mode(struct drm_crtc *crtc,
8351                             struct drm_display_mode *mode,
8352                             int x, int y, struct drm_framebuffer *fb)
8353 {
8354         struct drm_device *dev = crtc->dev;
8355         drm_i915_private_t *dev_priv = dev->dev_private;
8356         struct drm_display_mode *saved_mode, *saved_hwmode;
8357         struct intel_crtc_config *pipe_config = NULL;
8358         struct intel_crtc *intel_crtc;
8359         unsigned disable_pipes, prepare_pipes, modeset_pipes;
8360         int ret = 0;
8361
8362         saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
8363         if (!saved_mode)
8364                 return -ENOMEM;
8365         saved_hwmode = saved_mode + 1;
8366
8367         intel_modeset_affected_pipes(crtc, &modeset_pipes,
8368                                      &prepare_pipes, &disable_pipes);
8369
8370         *saved_hwmode = crtc->hwmode;
8371         *saved_mode = crtc->mode;
8372
8373         /* Hack: Because we don't (yet) support global modeset on multiple
8374          * crtcs, we don't keep track of the new mode for more than one crtc.
8375          * Hence simply check whether any bit is set in modeset_pipes in all the
8376          * pieces of code that are not yet converted to deal with mutliple crtcs
8377          * changing their mode at the same time. */
8378         if (modeset_pipes) {
8379                 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
8380                 if (IS_ERR(pipe_config)) {
8381                         ret = PTR_ERR(pipe_config);
8382                         pipe_config = NULL;
8383
8384                         goto out;
8385                 }
8386                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
8387                                        "[modeset]");
8388         }
8389
8390         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8391                 intel_crtc_disable(&intel_crtc->base);
8392
8393         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8394                 if (intel_crtc->base.enabled)
8395                         dev_priv->display.crtc_disable(&intel_crtc->base);
8396         }
8397
8398         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8399          * to set it here already despite that we pass it down the callchain.
8400          */
8401         if (modeset_pipes) {
8402                 crtc->mode = *mode;
8403                 /* mode_set/enable/disable functions rely on a correct pipe
8404                  * config. */
8405                 to_intel_crtc(crtc)->config = *pipe_config;
8406         }
8407
8408         /* Only after disabling all output pipelines that will be changed can we
8409          * update the the output configuration. */
8410         intel_modeset_update_state(dev, prepare_pipes);
8411
8412         if (dev_priv->display.modeset_global_resources)
8413                 dev_priv->display.modeset_global_resources(dev);
8414
8415         /* Set up the DPLL and any encoders state that needs to adjust or depend
8416          * on the DPLL.
8417          */
8418         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
8419                 ret = intel_crtc_mode_set(&intel_crtc->base,
8420                                           x, y, fb);
8421                 if (ret)
8422                         goto done;
8423         }
8424
8425         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
8426         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8427                 dev_priv->display.crtc_enable(&intel_crtc->base);
8428
8429         if (modeset_pipes) {
8430                 /* Store real post-adjustment hardware mode. */
8431                 crtc->hwmode = pipe_config->adjusted_mode;
8432
8433                 /* Calculate and store various constants which
8434                  * are later needed by vblank and swap-completion
8435                  * timestamping. They are derived from true hwmode.
8436                  */
8437                 drm_calc_timestamping_constants(crtc);
8438         }
8439
8440         /* FIXME: add subpixel order */
8441 done:
8442         if (ret && crtc->enabled) {
8443                 crtc->hwmode = *saved_hwmode;
8444                 crtc->mode = *saved_mode;
8445         }
8446
8447 out:
8448         kfree(pipe_config);
8449         kfree(saved_mode);
8450         return ret;
8451 }
8452
8453 int intel_set_mode(struct drm_crtc *crtc,
8454                      struct drm_display_mode *mode,
8455                      int x, int y, struct drm_framebuffer *fb)
8456 {
8457         int ret;
8458
8459         ret = __intel_set_mode(crtc, mode, x, y, fb);
8460
8461         if (ret == 0)
8462                 intel_modeset_check_state(crtc->dev);
8463
8464         return ret;
8465 }
8466
8467 void intel_crtc_restore_mode(struct drm_crtc *crtc)
8468 {
8469         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8470 }
8471
8472 #undef for_each_intel_crtc_masked
8473
8474 static void intel_set_config_free(struct intel_set_config *config)
8475 {
8476         if (!config)
8477                 return;
8478
8479         kfree(config->save_connector_encoders);
8480         kfree(config->save_encoder_crtcs);
8481         kfree(config);
8482 }
8483
8484 static int intel_set_config_save_state(struct drm_device *dev,
8485                                        struct intel_set_config *config)
8486 {
8487         struct drm_encoder *encoder;
8488         struct drm_connector *connector;
8489         int count;
8490
8491         config->save_encoder_crtcs =
8492                 kcalloc(dev->mode_config.num_encoder,
8493                         sizeof(struct drm_crtc *), GFP_KERNEL);
8494         if (!config->save_encoder_crtcs)
8495                 return -ENOMEM;
8496
8497         config->save_connector_encoders =
8498                 kcalloc(dev->mode_config.num_connector,
8499                         sizeof(struct drm_encoder *), GFP_KERNEL);
8500         if (!config->save_connector_encoders)
8501                 return -ENOMEM;
8502
8503         /* Copy data. Note that driver private data is not affected.
8504          * Should anything bad happen only the expected state is
8505          * restored, not the drivers personal bookkeeping.
8506          */
8507         count = 0;
8508         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
8509                 config->save_encoder_crtcs[count++] = encoder->crtc;
8510         }
8511
8512         count = 0;
8513         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8514                 config->save_connector_encoders[count++] = connector->encoder;
8515         }
8516
8517         return 0;
8518 }
8519
8520 static void intel_set_config_restore_state(struct drm_device *dev,
8521                                            struct intel_set_config *config)
8522 {
8523         struct intel_encoder *encoder;
8524         struct intel_connector *connector;
8525         int count;
8526
8527         count = 0;
8528         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8529                 encoder->new_crtc =
8530                         to_intel_crtc(config->save_encoder_crtcs[count++]);
8531         }
8532
8533         count = 0;
8534         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8535                 connector->new_encoder =
8536                         to_intel_encoder(config->save_connector_encoders[count++]);
8537         }
8538 }
8539
8540 static void
8541 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8542                                       struct intel_set_config *config)
8543 {
8544
8545         /* We should be able to check here if the fb has the same properties
8546          * and then just flip_or_move it */
8547         if (set->crtc->fb != set->fb) {
8548                 /* If we have no fb then treat it as a full mode set */
8549                 if (set->crtc->fb == NULL) {
8550                         DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8551                         config->mode_changed = true;
8552                 } else if (set->fb == NULL) {
8553                         config->mode_changed = true;
8554                 } else if (set->fb->pixel_format !=
8555                            set->crtc->fb->pixel_format) {
8556                         config->mode_changed = true;
8557                 } else
8558                         config->fb_changed = true;
8559         }
8560
8561         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
8562                 config->fb_changed = true;
8563
8564         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8565                 DRM_DEBUG_KMS("modes are different, full mode set\n");
8566                 drm_mode_debug_printmodeline(&set->crtc->mode);
8567                 drm_mode_debug_printmodeline(set->mode);
8568                 config->mode_changed = true;
8569         }
8570 }
8571
8572 static int
8573 intel_modeset_stage_output_state(struct drm_device *dev,
8574                                  struct drm_mode_set *set,
8575                                  struct intel_set_config *config)
8576 {
8577         struct drm_crtc *new_crtc;
8578         struct intel_connector *connector;
8579         struct intel_encoder *encoder;
8580         int count, ro;
8581
8582         /* The upper layers ensure that we either disable a crtc or have a list
8583          * of connectors. For paranoia, double-check this. */
8584         WARN_ON(!set->fb && (set->num_connectors != 0));
8585         WARN_ON(set->fb && (set->num_connectors == 0));
8586
8587         count = 0;
8588         list_for_each_entry(connector, &dev->mode_config.connector_list,
8589                             base.head) {
8590                 /* Otherwise traverse passed in connector list and get encoders
8591                  * for them. */
8592                 for (ro = 0; ro < set->num_connectors; ro++) {
8593                         if (set->connectors[ro] == &connector->base) {
8594                                 connector->new_encoder = connector->encoder;
8595                                 break;
8596                         }
8597                 }
8598
8599                 /* If we disable the crtc, disable all its connectors. Also, if
8600                  * the connector is on the changing crtc but not on the new
8601                  * connector list, disable it. */
8602                 if ((!set->fb || ro == set->num_connectors) &&
8603                     connector->base.encoder &&
8604                     connector->base.encoder->crtc == set->crtc) {
8605                         connector->new_encoder = NULL;
8606
8607                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8608                                 connector->base.base.id,
8609                                 drm_get_connector_name(&connector->base));
8610                 }
8611
8612
8613                 if (&connector->new_encoder->base != connector->base.encoder) {
8614                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
8615                         config->mode_changed = true;
8616                 }
8617         }
8618         /* connector->new_encoder is now updated for all connectors. */
8619
8620         /* Update crtc of enabled connectors. */
8621         count = 0;
8622         list_for_each_entry(connector, &dev->mode_config.connector_list,
8623                             base.head) {
8624                 if (!connector->new_encoder)
8625                         continue;
8626
8627                 new_crtc = connector->new_encoder->base.crtc;
8628
8629                 for (ro = 0; ro < set->num_connectors; ro++) {
8630                         if (set->connectors[ro] == &connector->base)
8631                                 new_crtc = set->crtc;
8632                 }
8633
8634                 /* Make sure the new CRTC will work with the encoder */
8635                 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8636                                            new_crtc)) {
8637                         return -EINVAL;
8638                 }
8639                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8640
8641                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8642                         connector->base.base.id,
8643                         drm_get_connector_name(&connector->base),
8644                         new_crtc->base.id);
8645         }
8646
8647         /* Check for any encoders that needs to be disabled. */
8648         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8649                             base.head) {
8650                 list_for_each_entry(connector,
8651                                     &dev->mode_config.connector_list,
8652                                     base.head) {
8653                         if (connector->new_encoder == encoder) {
8654                                 WARN_ON(!connector->new_encoder->new_crtc);
8655
8656                                 goto next_encoder;
8657                         }
8658                 }
8659                 encoder->new_crtc = NULL;
8660 next_encoder:
8661                 /* Only now check for crtc changes so we don't miss encoders
8662                  * that will be disabled. */
8663                 if (&encoder->new_crtc->base != encoder->base.crtc) {
8664                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8665                         config->mode_changed = true;
8666                 }
8667         }
8668         /* Now we've also updated encoder->new_crtc for all encoders. */
8669
8670         return 0;
8671 }
8672
8673 static int intel_crtc_set_config(struct drm_mode_set *set)
8674 {
8675         struct drm_device *dev;
8676         struct drm_mode_set save_set;
8677         struct intel_set_config *config;
8678         int ret;
8679
8680         BUG_ON(!set);
8681         BUG_ON(!set->crtc);
8682         BUG_ON(!set->crtc->helper_private);
8683
8684         /* Enforce sane interface api - has been abused by the fb helper. */
8685         BUG_ON(!set->mode && set->fb);
8686         BUG_ON(set->fb && set->num_connectors == 0);
8687
8688         if (set->fb) {
8689                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8690                                 set->crtc->base.id, set->fb->base.id,
8691                                 (int)set->num_connectors, set->x, set->y);
8692         } else {
8693                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
8694         }
8695
8696         dev = set->crtc->dev;
8697
8698         ret = -ENOMEM;
8699         config = kzalloc(sizeof(*config), GFP_KERNEL);
8700         if (!config)
8701                 goto out_config;
8702
8703         ret = intel_set_config_save_state(dev, config);
8704         if (ret)
8705                 goto out_config;
8706
8707         save_set.crtc = set->crtc;
8708         save_set.mode = &set->crtc->mode;
8709         save_set.x = set->crtc->x;
8710         save_set.y = set->crtc->y;
8711         save_set.fb = set->crtc->fb;
8712
8713         /* Compute whether we need a full modeset, only an fb base update or no
8714          * change at all. In the future we might also check whether only the
8715          * mode changed, e.g. for LVDS where we only change the panel fitter in
8716          * such cases. */
8717         intel_set_config_compute_mode_changes(set, config);
8718
8719         ret = intel_modeset_stage_output_state(dev, set, config);
8720         if (ret)
8721                 goto fail;
8722
8723         if (config->mode_changed) {
8724                 ret = intel_set_mode(set->crtc, set->mode,
8725                                      set->x, set->y, set->fb);
8726                 if (ret) {
8727                         DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8728                                   set->crtc->base.id, ret);
8729                         goto fail;
8730                 }
8731         } else if (config->fb_changed) {
8732                 intel_crtc_wait_for_pending_flips(set->crtc);
8733
8734                 ret = intel_pipe_set_base(set->crtc,
8735                                           set->x, set->y, set->fb);
8736         }
8737
8738         intel_set_config_free(config);
8739
8740         return 0;
8741
8742 fail:
8743         intel_set_config_restore_state(dev, config);
8744
8745         /* Try to restore the config */
8746         if (config->mode_changed &&
8747             intel_set_mode(save_set.crtc, save_set.mode,
8748                            save_set.x, save_set.y, save_set.fb))
8749                 DRM_ERROR("failed to restore config after modeset failure\n");
8750
8751 out_config:
8752         intel_set_config_free(config);
8753         return ret;
8754 }
8755
8756 static const struct drm_crtc_funcs intel_crtc_funcs = {
8757         .cursor_set = intel_crtc_cursor_set,
8758         .cursor_move = intel_crtc_cursor_move,
8759         .gamma_set = intel_crtc_gamma_set,
8760         .set_config = intel_crtc_set_config,
8761         .destroy = intel_crtc_destroy,
8762         .page_flip = intel_crtc_page_flip,
8763 };
8764
8765 static void intel_cpu_pll_init(struct drm_device *dev)
8766 {
8767         if (HAS_DDI(dev))
8768                 intel_ddi_pll_init(dev);
8769 }
8770
8771 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
8772                                       struct intel_shared_dpll *pll,
8773                                       struct intel_dpll_hw_state *hw_state)
8774 {
8775         uint32_t val;
8776
8777         val = I915_READ(PCH_DPLL(pll->id));
8778         hw_state->dpll = val;
8779         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
8780         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
8781
8782         return val & DPLL_VCO_ENABLE;
8783 }
8784
8785 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
8786                                 struct intel_shared_dpll *pll)
8787 {
8788         uint32_t reg, val;
8789
8790         /* PCH refclock must be enabled first */
8791         assert_pch_refclk_enabled(dev_priv);
8792
8793         reg = PCH_DPLL(pll->id);
8794         val = I915_READ(reg);
8795         val |= DPLL_VCO_ENABLE;
8796         I915_WRITE(reg, val);
8797         POSTING_READ(reg);
8798         udelay(200);
8799 }
8800
8801 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
8802                                  struct intel_shared_dpll *pll)
8803 {
8804         struct drm_device *dev = dev_priv->dev;
8805         struct intel_crtc *crtc;
8806         uint32_t reg, val;
8807
8808         /* Make sure no transcoder isn't still depending on us. */
8809         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
8810                 if (intel_crtc_to_shared_dpll(crtc) == pll)
8811                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
8812         }
8813
8814         reg = PCH_DPLL(pll->id);
8815         val = I915_READ(reg);
8816         val &= ~DPLL_VCO_ENABLE;
8817         I915_WRITE(reg, val);
8818         POSTING_READ(reg);
8819         udelay(200);
8820 }
8821
8822 static char *ibx_pch_dpll_names[] = {
8823         "PCH DPLL A",
8824         "PCH DPLL B",
8825 };
8826
8827 static void ibx_pch_dpll_init(struct drm_device *dev)
8828 {
8829         struct drm_i915_private *dev_priv = dev->dev_private;
8830         int i;
8831
8832         dev_priv->num_shared_dpll = 2;
8833
8834         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8835                 dev_priv->shared_dplls[i].id = i;
8836                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
8837                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
8838                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
8839                 dev_priv->shared_dplls[i].get_hw_state =
8840                         ibx_pch_dpll_get_hw_state;
8841         }
8842 }
8843
8844 static void intel_shared_dpll_init(struct drm_device *dev)
8845 {
8846         struct drm_i915_private *dev_priv = dev->dev_private;
8847
8848         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8849                 ibx_pch_dpll_init(dev);
8850         else
8851                 dev_priv->num_shared_dpll = 0;
8852
8853         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
8854         DRM_DEBUG_KMS("%i shared PLLs initialized\n",
8855                       dev_priv->num_shared_dpll);
8856 }
8857
8858 static void intel_crtc_init(struct drm_device *dev, int pipe)
8859 {
8860         drm_i915_private_t *dev_priv = dev->dev_private;
8861         struct intel_crtc *intel_crtc;
8862         int i;
8863
8864         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8865         if (intel_crtc == NULL)
8866                 return;
8867
8868         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8869
8870         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
8871         for (i = 0; i < 256; i++) {
8872                 intel_crtc->lut_r[i] = i;
8873                 intel_crtc->lut_g[i] = i;
8874                 intel_crtc->lut_b[i] = i;
8875         }
8876
8877         /* Swap pipes & planes for FBC on pre-965 */
8878         intel_crtc->pipe = pipe;
8879         intel_crtc->plane = pipe;
8880         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
8881                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8882                 intel_crtc->plane = !pipe;
8883         }
8884
8885         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8886                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8887         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8888         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8889
8890         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
8891 }
8892
8893 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
8894                                 struct drm_file *file)
8895 {
8896         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
8897         struct drm_mode_object *drmmode_obj;
8898         struct intel_crtc *crtc;
8899
8900         if (!drm_core_check_feature(dev, DRIVER_MODESET))
8901                 return -ENODEV;
8902
8903         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8904                         DRM_MODE_OBJECT_CRTC);
8905
8906         if (!drmmode_obj) {
8907                 DRM_ERROR("no such CRTC id\n");
8908                 return -EINVAL;
8909         }
8910
8911         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8912         pipe_from_crtc_id->pipe = crtc->pipe;
8913
8914         return 0;
8915 }
8916
8917 static int intel_encoder_clones(struct intel_encoder *encoder)
8918 {
8919         struct drm_device *dev = encoder->base.dev;
8920         struct intel_encoder *source_encoder;
8921         int index_mask = 0;
8922         int entry = 0;
8923
8924         list_for_each_entry(source_encoder,
8925                             &dev->mode_config.encoder_list, base.head) {
8926
8927                 if (encoder == source_encoder)
8928                         index_mask |= (1 << entry);
8929
8930                 /* Intel hw has only one MUX where enocoders could be cloned. */
8931                 if (encoder->cloneable && source_encoder->cloneable)
8932                         index_mask |= (1 << entry);
8933
8934                 entry++;
8935         }
8936
8937         return index_mask;
8938 }
8939
8940 static bool has_edp_a(struct drm_device *dev)
8941 {
8942         struct drm_i915_private *dev_priv = dev->dev_private;
8943
8944         if (!IS_MOBILE(dev))
8945                 return false;
8946
8947         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8948                 return false;
8949
8950         if (IS_GEN5(dev) &&
8951             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8952                 return false;
8953
8954         return true;
8955 }
8956
8957 static void intel_setup_outputs(struct drm_device *dev)
8958 {
8959         struct drm_i915_private *dev_priv = dev->dev_private;
8960         struct intel_encoder *encoder;
8961         bool dpd_is_edp = false;
8962
8963         intel_lvds_init(dev);
8964
8965         if (!IS_ULT(dev))
8966                 intel_crt_init(dev);
8967
8968         if (HAS_DDI(dev)) {
8969                 int found;
8970
8971                 /* Haswell uses DDI functions to detect digital outputs */
8972                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8973                 /* DDI A only supports eDP */
8974                 if (found)
8975                         intel_ddi_init(dev, PORT_A);
8976
8977                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8978                  * register */
8979                 found = I915_READ(SFUSE_STRAP);
8980
8981                 if (found & SFUSE_STRAP_DDIB_DETECTED)
8982                         intel_ddi_init(dev, PORT_B);
8983                 if (found & SFUSE_STRAP_DDIC_DETECTED)
8984                         intel_ddi_init(dev, PORT_C);
8985                 if (found & SFUSE_STRAP_DDID_DETECTED)
8986                         intel_ddi_init(dev, PORT_D);
8987         } else if (HAS_PCH_SPLIT(dev)) {
8988                 int found;
8989                 dpd_is_edp = intel_dpd_is_edp(dev);
8990
8991                 if (has_edp_a(dev))
8992                         intel_dp_init(dev, DP_A, PORT_A);
8993
8994                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
8995                         /* PCH SDVOB multiplex with HDMIB */
8996                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
8997                         if (!found)
8998                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
8999                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
9000                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
9001                 }
9002
9003                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
9004                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
9005
9006                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
9007                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
9008
9009                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
9010                         intel_dp_init(dev, PCH_DP_C, PORT_C);
9011
9012                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
9013                         intel_dp_init(dev, PCH_DP_D, PORT_D);
9014         } else if (IS_VALLEYVIEW(dev)) {
9015                 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
9016                 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
9017                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
9018
9019                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
9020                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
9021                                         PORT_B);
9022                         if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
9023                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
9024                 }
9025         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
9026                 bool found = false;
9027
9028                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
9029                         DRM_DEBUG_KMS("probing SDVOB\n");
9030                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
9031                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
9032                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
9033                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
9034                         }
9035
9036                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
9037                                 intel_dp_init(dev, DP_B, PORT_B);
9038                 }
9039
9040                 /* Before G4X SDVOC doesn't have its own detect register */
9041
9042                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
9043                         DRM_DEBUG_KMS("probing SDVOC\n");
9044                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
9045                 }
9046
9047                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
9048
9049                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
9050                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
9051                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
9052                         }
9053                         if (SUPPORTS_INTEGRATED_DP(dev))
9054                                 intel_dp_init(dev, DP_C, PORT_C);
9055                 }
9056
9057                 if (SUPPORTS_INTEGRATED_DP(dev) &&
9058                     (I915_READ(DP_D) & DP_DETECTED))
9059                         intel_dp_init(dev, DP_D, PORT_D);
9060         } else if (IS_GEN2(dev))
9061                 intel_dvo_init(dev);
9062
9063         if (SUPPORTS_TV(dev))
9064                 intel_tv_init(dev);
9065
9066         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9067                 encoder->base.possible_crtcs = encoder->crtc_mask;
9068                 encoder->base.possible_clones =
9069                         intel_encoder_clones(encoder);
9070         }
9071
9072         intel_init_pch_refclk(dev);
9073
9074         drm_helper_move_panel_connectors_to_head(dev);
9075 }
9076
9077 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
9078 {
9079         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9080
9081         drm_framebuffer_cleanup(fb);
9082         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
9083
9084         kfree(intel_fb);
9085 }
9086
9087 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
9088                                                 struct drm_file *file,
9089                                                 unsigned int *handle)
9090 {
9091         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9092         struct drm_i915_gem_object *obj = intel_fb->obj;
9093
9094         return drm_gem_handle_create(file, &obj->base, handle);
9095 }
9096
9097 static const struct drm_framebuffer_funcs intel_fb_funcs = {
9098         .destroy = intel_user_framebuffer_destroy,
9099         .create_handle = intel_user_framebuffer_create_handle,
9100 };
9101
9102 int intel_framebuffer_init(struct drm_device *dev,
9103                            struct intel_framebuffer *intel_fb,
9104                            struct drm_mode_fb_cmd2 *mode_cmd,
9105                            struct drm_i915_gem_object *obj)
9106 {
9107         int ret;
9108
9109         if (obj->tiling_mode == I915_TILING_Y) {
9110                 DRM_DEBUG("hardware does not support tiling Y\n");
9111                 return -EINVAL;
9112         }
9113
9114         if (mode_cmd->pitches[0] & 63) {
9115                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9116                           mode_cmd->pitches[0]);
9117                 return -EINVAL;
9118         }
9119
9120         /* FIXME <= Gen4 stride limits are bit unclear */
9121         if (mode_cmd->pitches[0] > 32768) {
9122                 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
9123                           mode_cmd->pitches[0]);
9124                 return -EINVAL;
9125         }
9126
9127         if (obj->tiling_mode != I915_TILING_NONE &&
9128             mode_cmd->pitches[0] != obj->stride) {
9129                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
9130                           mode_cmd->pitches[0], obj->stride);
9131                 return -EINVAL;
9132         }
9133
9134         /* Reject formats not supported by any plane early. */
9135         switch (mode_cmd->pixel_format) {
9136         case DRM_FORMAT_C8:
9137         case DRM_FORMAT_RGB565:
9138         case DRM_FORMAT_XRGB8888:
9139         case DRM_FORMAT_ARGB8888:
9140                 break;
9141         case DRM_FORMAT_XRGB1555:
9142         case DRM_FORMAT_ARGB1555:
9143                 if (INTEL_INFO(dev)->gen > 3) {
9144                         DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
9145                         return -EINVAL;
9146                 }
9147                 break;
9148         case DRM_FORMAT_XBGR8888:
9149         case DRM_FORMAT_ABGR8888:
9150         case DRM_FORMAT_XRGB2101010:
9151         case DRM_FORMAT_ARGB2101010:
9152         case DRM_FORMAT_XBGR2101010:
9153         case DRM_FORMAT_ABGR2101010:
9154                 if (INTEL_INFO(dev)->gen < 4) {
9155                         DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
9156                         return -EINVAL;
9157                 }
9158                 break;
9159         case DRM_FORMAT_YUYV:
9160         case DRM_FORMAT_UYVY:
9161         case DRM_FORMAT_YVYU:
9162         case DRM_FORMAT_VYUY:
9163                 if (INTEL_INFO(dev)->gen < 5) {
9164                         DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
9165                         return -EINVAL;
9166                 }
9167                 break;
9168         default:
9169                 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
9170                 return -EINVAL;
9171         }
9172
9173         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
9174         if (mode_cmd->offsets[0] != 0)
9175                 return -EINVAL;
9176
9177         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
9178         intel_fb->obj = obj;
9179
9180         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
9181         if (ret) {
9182                 DRM_ERROR("framebuffer init failed %d\n", ret);
9183                 return ret;
9184         }
9185
9186         return 0;
9187 }
9188
9189 static struct drm_framebuffer *
9190 intel_user_framebuffer_create(struct drm_device *dev,
9191                               struct drm_file *filp,
9192                               struct drm_mode_fb_cmd2 *mode_cmd)
9193 {
9194         struct drm_i915_gem_object *obj;
9195
9196         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
9197                                                 mode_cmd->handles[0]));
9198         if (&obj->base == NULL)
9199                 return ERR_PTR(-ENOENT);
9200
9201         return intel_framebuffer_create(dev, mode_cmd, obj);
9202 }
9203
9204 static const struct drm_mode_config_funcs intel_mode_funcs = {
9205         .fb_create = intel_user_framebuffer_create,
9206         .output_poll_changed = intel_fb_output_poll_changed,
9207 };
9208
9209 /* Set up chip specific display functions */
9210 static void intel_init_display(struct drm_device *dev)
9211 {
9212         struct drm_i915_private *dev_priv = dev->dev_private;
9213
9214         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
9215                 dev_priv->display.find_dpll = g4x_find_best_dpll;
9216         else if (IS_VALLEYVIEW(dev))
9217                 dev_priv->display.find_dpll = vlv_find_best_dpll;
9218         else if (IS_PINEVIEW(dev))
9219                 dev_priv->display.find_dpll = pnv_find_best_dpll;
9220         else
9221                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
9222
9223         if (HAS_DDI(dev)) {
9224                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
9225                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
9226                 dev_priv->display.crtc_enable = haswell_crtc_enable;
9227                 dev_priv->display.crtc_disable = haswell_crtc_disable;
9228                 dev_priv->display.off = haswell_crtc_off;
9229                 dev_priv->display.update_plane = ironlake_update_plane;
9230         } else if (HAS_PCH_SPLIT(dev)) {
9231                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
9232                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
9233                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9234                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
9235                 dev_priv->display.off = ironlake_crtc_off;
9236                 dev_priv->display.update_plane = ironlake_update_plane;
9237         } else if (IS_VALLEYVIEW(dev)) {
9238                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9239                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9240                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9241                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9242                 dev_priv->display.off = i9xx_crtc_off;
9243                 dev_priv->display.update_plane = i9xx_update_plane;
9244         } else {
9245                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9246                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9247                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
9248                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9249                 dev_priv->display.off = i9xx_crtc_off;
9250                 dev_priv->display.update_plane = i9xx_update_plane;
9251         }
9252
9253         /* Returns the core display clock speed */
9254         if (IS_VALLEYVIEW(dev))
9255                 dev_priv->display.get_display_clock_speed =
9256                         valleyview_get_display_clock_speed;
9257         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
9258                 dev_priv->display.get_display_clock_speed =
9259                         i945_get_display_clock_speed;
9260         else if (IS_I915G(dev))
9261                 dev_priv->display.get_display_clock_speed =
9262                         i915_get_display_clock_speed;
9263         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
9264                 dev_priv->display.get_display_clock_speed =
9265                         i9xx_misc_get_display_clock_speed;
9266         else if (IS_I915GM(dev))
9267                 dev_priv->display.get_display_clock_speed =
9268                         i915gm_get_display_clock_speed;
9269         else if (IS_I865G(dev))
9270                 dev_priv->display.get_display_clock_speed =
9271                         i865_get_display_clock_speed;
9272         else if (IS_I85X(dev))
9273                 dev_priv->display.get_display_clock_speed =
9274                         i855_get_display_clock_speed;
9275         else /* 852, 830 */
9276                 dev_priv->display.get_display_clock_speed =
9277                         i830_get_display_clock_speed;
9278
9279         if (HAS_PCH_SPLIT(dev)) {
9280                 if (IS_GEN5(dev)) {
9281                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
9282                         dev_priv->display.write_eld = ironlake_write_eld;
9283                 } else if (IS_GEN6(dev)) {
9284                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
9285                         dev_priv->display.write_eld = ironlake_write_eld;
9286                 } else if (IS_IVYBRIDGE(dev)) {
9287                         /* FIXME: detect B0+ stepping and use auto training */
9288                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
9289                         dev_priv->display.write_eld = ironlake_write_eld;
9290                         dev_priv->display.modeset_global_resources =
9291                                 ivb_modeset_global_resources;
9292                 } else if (IS_HASWELL(dev)) {
9293                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
9294                         dev_priv->display.write_eld = haswell_write_eld;
9295                         dev_priv->display.modeset_global_resources =
9296                                 haswell_modeset_global_resources;
9297                 }
9298         } else if (IS_G4X(dev)) {
9299                 dev_priv->display.write_eld = g4x_write_eld;
9300         }
9301
9302         /* Default just returns -ENODEV to indicate unsupported */
9303         dev_priv->display.queue_flip = intel_default_queue_flip;
9304
9305         switch (INTEL_INFO(dev)->gen) {
9306         case 2:
9307                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9308                 break;
9309
9310         case 3:
9311                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9312                 break;
9313
9314         case 4:
9315         case 5:
9316                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9317                 break;
9318
9319         case 6:
9320                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9321                 break;
9322         case 7:
9323                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9324                 break;
9325         }
9326 }
9327
9328 /*
9329  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9330  * resume, or other times.  This quirk makes sure that's the case for
9331  * affected systems.
9332  */
9333 static void quirk_pipea_force(struct drm_device *dev)
9334 {
9335         struct drm_i915_private *dev_priv = dev->dev_private;
9336
9337         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
9338         DRM_INFO("applying pipe a force quirk\n");
9339 }
9340
9341 /*
9342  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9343  */
9344 static void quirk_ssc_force_disable(struct drm_device *dev)
9345 {
9346         struct drm_i915_private *dev_priv = dev->dev_private;
9347         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
9348         DRM_INFO("applying lvds SSC disable quirk\n");
9349 }
9350
9351 /*
9352  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9353  * brightness value
9354  */
9355 static void quirk_invert_brightness(struct drm_device *dev)
9356 {
9357         struct drm_i915_private *dev_priv = dev->dev_private;
9358         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
9359         DRM_INFO("applying inverted panel brightness quirk\n");
9360 }
9361
9362 struct intel_quirk {
9363         int device;
9364         int subsystem_vendor;
9365         int subsystem_device;
9366         void (*hook)(struct drm_device *dev);
9367 };
9368
9369 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9370 struct intel_dmi_quirk {
9371         void (*hook)(struct drm_device *dev);
9372         const struct dmi_system_id (*dmi_id_list)[];
9373 };
9374
9375 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
9376 {
9377         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
9378         return 1;
9379 }
9380
9381 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
9382         {
9383                 .dmi_id_list = &(const struct dmi_system_id[]) {
9384                         {
9385                                 .callback = intel_dmi_reverse_brightness,
9386                                 .ident = "NCR Corporation",
9387                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
9388                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
9389                                 },
9390                         },
9391                         { }  /* terminating entry */
9392                 },
9393                 .hook = quirk_invert_brightness,
9394         },
9395 };
9396
9397 static struct intel_quirk intel_quirks[] = {
9398         /* HP Mini needs pipe A force quirk (LP: #322104) */
9399         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
9400
9401         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9402         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9403
9404         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9405         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9406
9407         /* 830/845 need to leave pipe A & dpll A up */
9408         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9409         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9410
9411         /* Lenovo U160 cannot use SSC on LVDS */
9412         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
9413
9414         /* Sony Vaio Y cannot use SSC on LVDS */
9415         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
9416
9417         /* Acer Aspire 5734Z must invert backlight brightness */
9418         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
9419
9420         /* Acer/eMachines G725 */
9421         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
9422
9423         /* Acer/eMachines e725 */
9424         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
9425
9426         /* Acer/Packard Bell NCL20 */
9427         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
9428
9429         /* Acer Aspire 4736Z */
9430         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
9431 };
9432
9433 static void intel_init_quirks(struct drm_device *dev)
9434 {
9435         struct pci_dev *d = dev->pdev;
9436         int i;
9437
9438         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9439                 struct intel_quirk *q = &intel_quirks[i];
9440
9441                 if (d->device == q->device &&
9442                     (d->subsystem_vendor == q->subsystem_vendor ||
9443                      q->subsystem_vendor == PCI_ANY_ID) &&
9444                     (d->subsystem_device == q->subsystem_device ||
9445                      q->subsystem_device == PCI_ANY_ID))
9446                         q->hook(dev);
9447         }
9448         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
9449                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
9450                         intel_dmi_quirks[i].hook(dev);
9451         }
9452 }
9453
9454 /* Disable the VGA plane that we never use */
9455 static void i915_disable_vga(struct drm_device *dev)
9456 {
9457         struct drm_i915_private *dev_priv = dev->dev_private;
9458         u8 sr1;
9459         u32 vga_reg = i915_vgacntrl_reg(dev);
9460
9461         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
9462         outb(SR01, VGA_SR_INDEX);
9463         sr1 = inb(VGA_SR_DATA);
9464         outb(sr1 | 1<<5, VGA_SR_DATA);
9465         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9466         udelay(300);
9467
9468         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9469         POSTING_READ(vga_reg);
9470 }
9471
9472 void intel_modeset_init_hw(struct drm_device *dev)
9473 {
9474         intel_init_power_well(dev);
9475
9476         intel_prepare_ddi(dev);
9477
9478         intel_init_clock_gating(dev);
9479
9480         mutex_lock(&dev->struct_mutex);
9481         intel_enable_gt_powersave(dev);
9482         mutex_unlock(&dev->struct_mutex);
9483 }
9484
9485 void intel_modeset_suspend_hw(struct drm_device *dev)
9486 {
9487         intel_suspend_hw(dev);
9488 }
9489
9490 void intel_modeset_init(struct drm_device *dev)
9491 {
9492         struct drm_i915_private *dev_priv = dev->dev_private;
9493         int i, j, ret;
9494
9495         drm_mode_config_init(dev);
9496
9497         dev->mode_config.min_width = 0;
9498         dev->mode_config.min_height = 0;
9499
9500         dev->mode_config.preferred_depth = 24;
9501         dev->mode_config.prefer_shadow = 1;
9502
9503         dev->mode_config.funcs = &intel_mode_funcs;
9504
9505         intel_init_quirks(dev);
9506
9507         intel_init_pm(dev);
9508
9509         if (INTEL_INFO(dev)->num_pipes == 0)
9510                 return;
9511
9512         intel_init_display(dev);
9513
9514         if (IS_GEN2(dev)) {
9515                 dev->mode_config.max_width = 2048;
9516                 dev->mode_config.max_height = 2048;
9517         } else if (IS_GEN3(dev)) {
9518                 dev->mode_config.max_width = 4096;
9519                 dev->mode_config.max_height = 4096;
9520         } else {
9521                 dev->mode_config.max_width = 8192;
9522                 dev->mode_config.max_height = 8192;
9523         }
9524         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
9525
9526         DRM_DEBUG_KMS("%d display pipe%s available.\n",
9527                       INTEL_INFO(dev)->num_pipes,
9528                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
9529
9530         for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
9531                 intel_crtc_init(dev, i);
9532                 for (j = 0; j < dev_priv->num_plane; j++) {
9533                         ret = intel_plane_init(dev, i, j);
9534                         if (ret)
9535                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9536                                               pipe_name(i), sprite_name(i, j), ret);
9537                 }
9538         }
9539
9540         intel_cpu_pll_init(dev);
9541         intel_shared_dpll_init(dev);
9542
9543         /* Just disable it once at startup */
9544         i915_disable_vga(dev);
9545         intel_setup_outputs(dev);
9546
9547         /* Just in case the BIOS is doing something questionable. */
9548         intel_disable_fbc(dev);
9549 }
9550
9551 static void
9552 intel_connector_break_all_links(struct intel_connector *connector)
9553 {
9554         connector->base.dpms = DRM_MODE_DPMS_OFF;
9555         connector->base.encoder = NULL;
9556         connector->encoder->connectors_active = false;
9557         connector->encoder->base.crtc = NULL;
9558 }
9559
9560 static void intel_enable_pipe_a(struct drm_device *dev)
9561 {
9562         struct intel_connector *connector;
9563         struct drm_connector *crt = NULL;
9564         struct intel_load_detect_pipe load_detect_temp;
9565
9566         /* We can't just switch on the pipe A, we need to set things up with a
9567          * proper mode and output configuration. As a gross hack, enable pipe A
9568          * by enabling the load detect pipe once. */
9569         list_for_each_entry(connector,
9570                             &dev->mode_config.connector_list,
9571                             base.head) {
9572                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9573                         crt = &connector->base;
9574                         break;
9575                 }
9576         }
9577
9578         if (!crt)
9579                 return;
9580
9581         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9582                 intel_release_load_detect_pipe(crt, &load_detect_temp);
9583
9584
9585 }
9586
9587 static bool
9588 intel_check_plane_mapping(struct intel_crtc *crtc)
9589 {
9590         struct drm_device *dev = crtc->base.dev;
9591         struct drm_i915_private *dev_priv = dev->dev_private;
9592         u32 reg, val;
9593
9594         if (INTEL_INFO(dev)->num_pipes == 1)
9595                 return true;
9596
9597         reg = DSPCNTR(!crtc->plane);
9598         val = I915_READ(reg);
9599
9600         if ((val & DISPLAY_PLANE_ENABLE) &&
9601             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9602                 return false;
9603
9604         return true;
9605 }
9606
9607 static void intel_sanitize_crtc(struct intel_crtc *crtc)
9608 {
9609         struct drm_device *dev = crtc->base.dev;
9610         struct drm_i915_private *dev_priv = dev->dev_private;
9611         u32 reg;
9612
9613         /* Clear any frame start delays used for debugging left by the BIOS */
9614         reg = PIPECONF(crtc->config.cpu_transcoder);
9615         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9616
9617         /* We need to sanitize the plane -> pipe mapping first because this will
9618          * disable the crtc (and hence change the state) if it is wrong. Note
9619          * that gen4+ has a fixed plane -> pipe mapping.  */
9620         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
9621                 struct intel_connector *connector;
9622                 bool plane;
9623
9624                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9625                               crtc->base.base.id);
9626
9627                 /* Pipe has the wrong plane attached and the plane is active.
9628                  * Temporarily change the plane mapping and disable everything
9629                  * ...  */
9630                 plane = crtc->plane;
9631                 crtc->plane = !plane;
9632                 dev_priv->display.crtc_disable(&crtc->base);
9633                 crtc->plane = plane;
9634
9635                 /* ... and break all links. */
9636                 list_for_each_entry(connector, &dev->mode_config.connector_list,
9637                                     base.head) {
9638                         if (connector->encoder->base.crtc != &crtc->base)
9639                                 continue;
9640
9641                         intel_connector_break_all_links(connector);
9642                 }
9643
9644                 WARN_ON(crtc->active);
9645                 crtc->base.enabled = false;
9646         }
9647
9648         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9649             crtc->pipe == PIPE_A && !crtc->active) {
9650                 /* BIOS forgot to enable pipe A, this mostly happens after
9651                  * resume. Force-enable the pipe to fix this, the update_dpms
9652                  * call below we restore the pipe to the right state, but leave
9653                  * the required bits on. */
9654                 intel_enable_pipe_a(dev);
9655         }
9656
9657         /* Adjust the state of the output pipe according to whether we
9658          * have active connectors/encoders. */
9659         intel_crtc_update_dpms(&crtc->base);
9660
9661         if (crtc->active != crtc->base.enabled) {
9662                 struct intel_encoder *encoder;
9663
9664                 /* This can happen either due to bugs in the get_hw_state
9665                  * functions or because the pipe is force-enabled due to the
9666                  * pipe A quirk. */
9667                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9668                               crtc->base.base.id,
9669                               crtc->base.enabled ? "enabled" : "disabled",
9670                               crtc->active ? "enabled" : "disabled");
9671
9672                 crtc->base.enabled = crtc->active;
9673
9674                 /* Because we only establish the connector -> encoder ->
9675                  * crtc links if something is active, this means the
9676                  * crtc is now deactivated. Break the links. connector
9677                  * -> encoder links are only establish when things are
9678                  *  actually up, hence no need to break them. */
9679                 WARN_ON(crtc->active);
9680
9681                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9682                         WARN_ON(encoder->connectors_active);
9683                         encoder->base.crtc = NULL;
9684                 }
9685         }
9686 }
9687
9688 static void intel_sanitize_encoder(struct intel_encoder *encoder)
9689 {
9690         struct intel_connector *connector;
9691         struct drm_device *dev = encoder->base.dev;
9692
9693         /* We need to check both for a crtc link (meaning that the
9694          * encoder is active and trying to read from a pipe) and the
9695          * pipe itself being active. */
9696         bool has_active_crtc = encoder->base.crtc &&
9697                 to_intel_crtc(encoder->base.crtc)->active;
9698
9699         if (encoder->connectors_active && !has_active_crtc) {
9700                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9701                               encoder->base.base.id,
9702                               drm_get_encoder_name(&encoder->base));
9703
9704                 /* Connector is active, but has no active pipe. This is
9705                  * fallout from our resume register restoring. Disable
9706                  * the encoder manually again. */
9707                 if (encoder->base.crtc) {
9708                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9709                                       encoder->base.base.id,
9710                                       drm_get_encoder_name(&encoder->base));
9711                         encoder->disable(encoder);
9712                 }
9713
9714                 /* Inconsistent output/port/pipe state happens presumably due to
9715                  * a bug in one of the get_hw_state functions. Or someplace else
9716                  * in our code, like the register restore mess on resume. Clamp
9717                  * things to off as a safer default. */
9718                 list_for_each_entry(connector,
9719                                     &dev->mode_config.connector_list,
9720                                     base.head) {
9721                         if (connector->encoder != encoder)
9722                                 continue;
9723
9724                         intel_connector_break_all_links(connector);
9725                 }
9726         }
9727         /* Enabled encoders without active connectors will be fixed in
9728          * the crtc fixup. */
9729 }
9730
9731 void i915_redisable_vga(struct drm_device *dev)
9732 {
9733         struct drm_i915_private *dev_priv = dev->dev_private;
9734         u32 vga_reg = i915_vgacntrl_reg(dev);
9735
9736         if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9737                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
9738                 i915_disable_vga(dev);
9739         }
9740 }
9741
9742 static void intel_modeset_readout_hw_state(struct drm_device *dev)
9743 {
9744         struct drm_i915_private *dev_priv = dev->dev_private;
9745         enum pipe pipe;
9746         struct intel_crtc *crtc;
9747         struct intel_encoder *encoder;
9748         struct intel_connector *connector;
9749         int i;
9750
9751         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9752                             base.head) {
9753                 memset(&crtc->config, 0, sizeof(crtc->config));
9754
9755                 crtc->active = dev_priv->display.get_pipe_config(crtc,
9756                                                                  &crtc->config);
9757
9758                 crtc->base.enabled = crtc->active;
9759
9760                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9761                               crtc->base.base.id,
9762                               crtc->active ? "enabled" : "disabled");
9763         }
9764
9765         /* FIXME: Smash this into the new shared dpll infrastructure. */
9766         if (HAS_DDI(dev))
9767                 intel_ddi_setup_hw_pll_state(dev);
9768
9769         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9770                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
9771
9772                 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
9773                 pll->active = 0;
9774                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9775                                     base.head) {
9776                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
9777                                 pll->active++;
9778                 }
9779                 pll->refcount = pll->active;
9780
9781                 DRM_DEBUG_KMS("%s hw state readout: refcount %i\n",
9782                               pll->name, pll->refcount);
9783         }
9784
9785         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9786                             base.head) {
9787                 pipe = 0;
9788
9789                 if (encoder->get_hw_state(encoder, &pipe)) {
9790                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9791                         encoder->base.crtc = &crtc->base;
9792                         if (encoder->get_config)
9793                                 encoder->get_config(encoder, &crtc->config);
9794                 } else {
9795                         encoder->base.crtc = NULL;
9796                 }
9797
9798                 encoder->connectors_active = false;
9799                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9800                               encoder->base.base.id,
9801                               drm_get_encoder_name(&encoder->base),
9802                               encoder->base.crtc ? "enabled" : "disabled",
9803                               pipe);
9804         }
9805
9806         list_for_each_entry(connector, &dev->mode_config.connector_list,
9807                             base.head) {
9808                 if (connector->get_hw_state(connector)) {
9809                         connector->base.dpms = DRM_MODE_DPMS_ON;
9810                         connector->encoder->connectors_active = true;
9811                         connector->base.encoder = &connector->encoder->base;
9812                 } else {
9813                         connector->base.dpms = DRM_MODE_DPMS_OFF;
9814                         connector->base.encoder = NULL;
9815                 }
9816                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9817                               connector->base.base.id,
9818                               drm_get_connector_name(&connector->base),
9819                               connector->base.encoder ? "enabled" : "disabled");
9820         }
9821 }
9822
9823 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9824  * and i915 state tracking structures. */
9825 void intel_modeset_setup_hw_state(struct drm_device *dev,
9826                                   bool force_restore)
9827 {
9828         struct drm_i915_private *dev_priv = dev->dev_private;
9829         enum pipe pipe;
9830         struct drm_plane *plane;
9831         struct intel_crtc *crtc;
9832         struct intel_encoder *encoder;
9833
9834         intel_modeset_readout_hw_state(dev);
9835
9836         /* HW state is read out, now we need to sanitize this mess. */
9837         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9838                             base.head) {
9839                 intel_sanitize_encoder(encoder);
9840         }
9841
9842         for_each_pipe(pipe) {
9843                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9844                 intel_sanitize_crtc(crtc);
9845                 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
9846         }
9847
9848         if (force_restore) {
9849                 /*
9850                  * We need to use raw interfaces for restoring state to avoid
9851                  * checking (bogus) intermediate states.
9852                  */
9853                 for_each_pipe(pipe) {
9854                         struct drm_crtc *crtc =
9855                                 dev_priv->pipe_to_crtc_mapping[pipe];
9856
9857                         __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
9858                                          crtc->fb);
9859                 }
9860                 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
9861                         intel_plane_restore(plane);
9862
9863                 i915_redisable_vga(dev);
9864         } else {
9865                 intel_modeset_update_staged_output_state(dev);
9866         }
9867
9868         intel_modeset_check_state(dev);
9869
9870         drm_mode_config_reset(dev);
9871 }
9872
9873 void intel_modeset_gem_init(struct drm_device *dev)
9874 {
9875         intel_modeset_init_hw(dev);
9876
9877         intel_setup_overlay(dev);
9878
9879         intel_modeset_setup_hw_state(dev, false);
9880 }
9881
9882 void intel_modeset_cleanup(struct drm_device *dev)
9883 {
9884         struct drm_i915_private *dev_priv = dev->dev_private;
9885         struct drm_crtc *crtc;
9886         struct intel_crtc *intel_crtc;
9887
9888         /*
9889          * Interrupts and polling as the first thing to avoid creating havoc.
9890          * Too much stuff here (turning of rps, connectors, ...) would
9891          * experience fancy races otherwise.
9892          */
9893         drm_irq_uninstall(dev);
9894         cancel_work_sync(&dev_priv->hotplug_work);
9895         /*
9896          * Due to the hpd irq storm handling the hotplug work can re-arm the
9897          * poll handlers. Hence disable polling after hpd handling is shut down.
9898          */
9899         drm_kms_helper_poll_fini(dev);
9900
9901         mutex_lock(&dev->struct_mutex);
9902
9903         intel_unregister_dsm_handler();
9904
9905         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9906                 /* Skip inactive CRTCs */
9907                 if (!crtc->fb)
9908                         continue;
9909
9910                 intel_crtc = to_intel_crtc(crtc);
9911                 intel_increase_pllclock(crtc);
9912         }
9913
9914         intel_disable_fbc(dev);
9915
9916         intel_disable_gt_powersave(dev);
9917
9918         ironlake_teardown_rc6(dev);
9919
9920         mutex_unlock(&dev->struct_mutex);
9921
9922         /* flush any delayed tasks or pending work */
9923         flush_scheduled_work();
9924
9925         /* destroy backlight, if any, before the connectors */
9926         intel_panel_destroy_backlight(dev);
9927
9928         drm_mode_config_cleanup(dev);
9929
9930         intel_cleanup_overlay(dev);
9931 }
9932
9933 /*
9934  * Return which encoder is currently attached for connector.
9935  */
9936 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9937 {
9938         return &intel_attached_encoder(connector)->base;
9939 }
9940
9941 void intel_connector_attach_encoder(struct intel_connector *connector,
9942                                     struct intel_encoder *encoder)
9943 {
9944         connector->encoder = encoder;
9945         drm_mode_connector_attach_encoder(&connector->base,
9946                                           &encoder->base);
9947 }
9948
9949 /*
9950  * set vga decode state - true == enable VGA decode
9951  */
9952 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9953 {
9954         struct drm_i915_private *dev_priv = dev->dev_private;
9955         u16 gmch_ctrl;
9956
9957         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9958         if (state)
9959                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9960         else
9961                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9962         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9963         return 0;
9964 }
9965
9966 #ifdef CONFIG_DEBUG_FS
9967 #include <linux/seq_file.h>
9968
9969 struct intel_display_error_state {
9970
9971         u32 power_well_driver;
9972
9973         struct intel_cursor_error_state {
9974                 u32 control;
9975                 u32 position;
9976                 u32 base;
9977                 u32 size;
9978         } cursor[I915_MAX_PIPES];
9979
9980         struct intel_pipe_error_state {
9981                 enum transcoder cpu_transcoder;
9982                 u32 conf;
9983                 u32 source;
9984
9985                 u32 htotal;
9986                 u32 hblank;
9987                 u32 hsync;
9988                 u32 vtotal;
9989                 u32 vblank;
9990                 u32 vsync;
9991         } pipe[I915_MAX_PIPES];
9992
9993         struct intel_plane_error_state {
9994                 u32 control;
9995                 u32 stride;
9996                 u32 size;
9997                 u32 pos;
9998                 u32 addr;
9999                 u32 surface;
10000                 u32 tile_offset;
10001         } plane[I915_MAX_PIPES];
10002 };
10003
10004 struct intel_display_error_state *
10005 intel_display_capture_error_state(struct drm_device *dev)
10006 {
10007         drm_i915_private_t *dev_priv = dev->dev_private;
10008         struct intel_display_error_state *error;
10009         enum transcoder cpu_transcoder;
10010         int i;
10011
10012         error = kmalloc(sizeof(*error), GFP_ATOMIC);
10013         if (error == NULL)
10014                 return NULL;
10015
10016         if (HAS_POWER_WELL(dev))
10017                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
10018
10019         for_each_pipe(i) {
10020                 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
10021                 error->pipe[i].cpu_transcoder = cpu_transcoder;
10022
10023                 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
10024                         error->cursor[i].control = I915_READ(CURCNTR(i));
10025                         error->cursor[i].position = I915_READ(CURPOS(i));
10026                         error->cursor[i].base = I915_READ(CURBASE(i));
10027                 } else {
10028                         error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
10029                         error->cursor[i].position = I915_READ(CURPOS_IVB(i));
10030                         error->cursor[i].base = I915_READ(CURBASE_IVB(i));
10031                 }
10032
10033                 error->plane[i].control = I915_READ(DSPCNTR(i));
10034                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
10035                 if (INTEL_INFO(dev)->gen <= 3) {
10036                         error->plane[i].size = I915_READ(DSPSIZE(i));
10037                         error->plane[i].pos = I915_READ(DSPPOS(i));
10038                 }
10039                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10040                         error->plane[i].addr = I915_READ(DSPADDR(i));
10041                 if (INTEL_INFO(dev)->gen >= 4) {
10042                         error->plane[i].surface = I915_READ(DSPSURF(i));
10043                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
10044                 }
10045
10046                 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
10047                 error->pipe[i].source = I915_READ(PIPESRC(i));
10048                 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
10049                 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
10050                 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
10051                 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
10052                 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
10053                 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
10054         }
10055
10056         /* In the code above we read the registers without checking if the power
10057          * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
10058          * prevent the next I915_WRITE from detecting it and printing an error
10059          * message. */
10060         if (HAS_POWER_WELL(dev))
10061                 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
10062
10063         return error;
10064 }
10065
10066 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
10067
10068 void
10069 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
10070                                 struct drm_device *dev,
10071                                 struct intel_display_error_state *error)
10072 {
10073         int i;
10074
10075         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
10076         if (HAS_POWER_WELL(dev))
10077                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
10078                            error->power_well_driver);
10079         for_each_pipe(i) {
10080                 err_printf(m, "Pipe [%d]:\n", i);
10081                 err_printf(m, "  CPU transcoder: %c\n",
10082                            transcoder_name(error->pipe[i].cpu_transcoder));
10083                 err_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
10084                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
10085                 err_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
10086                 err_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
10087                 err_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
10088                 err_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
10089                 err_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
10090                 err_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
10091
10092                 err_printf(m, "Plane [%d]:\n", i);
10093                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
10094                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
10095                 if (INTEL_INFO(dev)->gen <= 3) {
10096                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
10097                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
10098                 }
10099                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10100                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
10101                 if (INTEL_INFO(dev)->gen >= 4) {
10102                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
10103                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
10104                 }
10105
10106                 err_printf(m, "Cursor [%d]:\n", i);
10107                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
10108                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
10109                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
10110         }
10111 }
10112 #endif