drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_atomic.h>
  41 #include <drm/drm_atomic_helper.h>
  42 #include <drm/drm_dp_helper.h>
  43 #include <drm/drm_crtc_helper.h>
  44 #include <drm/drm_plane_helper.h>
  45 #include <drm/drm_rect.h>
  46 #include <linux/dma_remapping.h>
  47 #include <linux/reservation.h>
  48 #include <linux/dma-buf.h>
  49
  50 /* Primary plane formats for gen <= 3 */
  51 static const uint32_t i8xx_primary_formats[] = {
  52         DRM_FORMAT_C8,
  53         DRM_FORMAT_RGB565,
  54         DRM_FORMAT_XRGB1555,
  55         DRM_FORMAT_XRGB8888,
  56 };
  57
  58 /* Primary plane formats for gen >= 4 */
  59 static const uint32_t i965_primary_formats[] = {
  60         DRM_FORMAT_C8,
  61         DRM_FORMAT_RGB565,
  62         DRM_FORMAT_XRGB8888,
  63         DRM_FORMAT_XBGR8888,
  64         DRM_FORMAT_XRGB2101010,
  65         DRM_FORMAT_XBGR2101010,
  66 };
  67
  68 static const uint32_t skl_primary_formats[] = {
  69         DRM_FORMAT_C8,
  70         DRM_FORMAT_RGB565,
  71         DRM_FORMAT_XRGB8888,
  72         DRM_FORMAT_XBGR8888,
  73         DRM_FORMAT_ARGB8888,
  74         DRM_FORMAT_ABGR8888,
  75         DRM_FORMAT_XRGB2101010,
  76         DRM_FORMAT_XBGR2101010,
  77         DRM_FORMAT_YUYV,
  78         DRM_FORMAT_YVYU,
  79         DRM_FORMAT_UYVY,
  80         DRM_FORMAT_VYUY,
  81 };
  82
  83 /* Cursor formats */
  84 static const uint32_t intel_cursor_formats[] = {
  85         DRM_FORMAT_ARGB8888,
  86 };
  87
  88 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  89                                 struct intel_crtc_state *pipe_config);
  90 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  91                                    struct intel_crtc_state *pipe_config);
  92
  93 static int intel_framebuffer_init(struct drm_device *dev,
  94                                   struct intel_framebuffer *ifb,
  95                                   struct drm_mode_fb_cmd2 *mode_cmd,
  96                                   struct drm_i915_gem_object *obj);
  97 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
  98 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
  99 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
 100                                          struct intel_link_m_n *m_n,
 101                                          struct intel_link_m_n *m2_n2);
 102 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
 103 static void haswell_set_pipeconf(struct drm_crtc *crtc);
 104 static void intel_set_pipe_csc(struct drm_crtc *crtc);
 105 static void vlv_prepare_pll(struct intel_crtc *crtc,
 106                             const struct intel_crtc_state *pipe_config);
 107 static void chv_prepare_pll(struct intel_crtc *crtc,
 108                             const struct intel_crtc_state *pipe_config);
 109 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 110 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 111 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
 112         struct intel_crtc_state *crtc_state);
 113 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
 114                            int num_connectors);
 115 static void skylake_pfit_enable(struct intel_crtc *crtc);
 116 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
 117 static void ironlake_pfit_enable(struct intel_crtc *crtc);
 118 static void intel_modeset_setup_hw_state(struct drm_device *dev);
 119 static void intel_pre_disable_primary(struct drm_crtc *crtc);
 120
 121 typedef struct {
 122         int     min, max;
 123 } intel_range_t;
 124
 125 typedef struct {
 126         int     dot_limit;
 127         int     p2_slow, p2_fast;
 128 } intel_p2_t;
 129
 130 typedef struct intel_limit intel_limit_t;
 131 struct intel_limit {
 132         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
 133         intel_p2_t          p2;
 134 };
 135
 136 /* returns HPLL frequency in kHz */
 137 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
 138 {
 139         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
 140
 141         /* Obtain SKU information */
 142         mutex_lock(&dev_priv->sb_lock);
 143         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
 144                 CCK_FUSE_HPLL_FREQ_MASK;
 145         mutex_unlock(&dev_priv->sb_lock);
 146
 147         return vco_freq[hpll_freq] * 1000;
 148 }
 149
 150 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
 151                                   const char *name, u32 reg)
 152 {
 153         u32 val;
 154         int divider;
 155
 156         if (dev_priv->hpll_freq == 0)
 157                 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
 158
 159         mutex_lock(&dev_priv->sb_lock);
 160         val = vlv_cck_read(dev_priv, reg);
 161         mutex_unlock(&dev_priv->sb_lock);
 162
 163         divider = val & CCK_FREQUENCY_VALUES;
 164
 165         WARN((val & CCK_FREQUENCY_STATUS) !=
 166              (divider << CCK_FREQUENCY_STATUS_SHIFT),
 167              "%s change in progress\n", name);
 168
 169         return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
 170 }
 171
 172 static int
 173 intel_pch_rawclk(struct drm_i915_private *dev_priv)
 174 {
 175         return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
 176 }
 177
 178 static int
 179 intel_vlv_hrawclk(struct drm_i915_private *dev_priv)
 180 {
 181         return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
 182                                       CCK_DISPLAY_REF_CLOCK_CONTROL);
 183 }
 184
 185 static int
 186 intel_g4x_hrawclk(struct drm_i915_private *dev_priv)
 187 {
 188         uint32_t clkcfg;
 189
 190         /* hrawclock is 1/4 the FSB frequency */
 191         clkcfg = I915_READ(CLKCFG);
 192         switch (clkcfg & CLKCFG_FSB_MASK) {
 193         case CLKCFG_FSB_400:
 194                 return 100000;
 195         case CLKCFG_FSB_533:
 196                 return 133333;
 197         case CLKCFG_FSB_667:
 198                 return 166667;
 199         case CLKCFG_FSB_800:
 200                 return 200000;
 201         case CLKCFG_FSB_1067:
 202                 return 266667;
 203         case CLKCFG_FSB_1333:
 204                 return 333333;
 205         /* these two are just a guess; one of them might be right */
 206         case CLKCFG_FSB_1600:
 207         case CLKCFG_FSB_1600_ALT:
 208                 return 400000;
 209         default:
 210                 return 133333;
 211         }
 212 }
 213
 214 static void intel_update_rawclk(struct drm_i915_private *dev_priv)
 215 {
 216         if (HAS_PCH_SPLIT(dev_priv))
 217                 dev_priv->rawclk_freq = intel_pch_rawclk(dev_priv);
 218         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 219                 dev_priv->rawclk_freq = intel_vlv_hrawclk(dev_priv);
 220         else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv))
 221                 dev_priv->rawclk_freq = intel_g4x_hrawclk(dev_priv);
 222         else
 223                 return; /* no rawclk on other platforms, or no need to know it */
 224
 225         DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq);
 226 }
 227
 228 static void intel_update_czclk(struct drm_i915_private *dev_priv)
 229 {
 230         if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
 231                 return;
 232
 233         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
 234                                                       CCK_CZ_CLOCK_CONTROL);
 235
 236         DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
 237 }
 238
 239 static inline u32 /* units of 100MHz */
 240 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
 241                     const struct intel_crtc_state *pipe_config)
 242 {
 243         if (HAS_DDI(dev_priv))
 244                 return pipe_config->port_clock; /* SPLL */
 245         else if (IS_GEN5(dev_priv))
 246                 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
 247         else
 248                 return 270000;
 249 }
 250
 251 static const intel_limit_t intel_limits_i8xx_dac = {
 252         .dot = { .min = 25000, .max = 350000 },
 253         .vco = { .min = 908000, .max = 1512000 },
 254         .n = { .min = 2, .max = 16 },
 255         .m = { .min = 96, .max = 140 },
 256         .m1 = { .min = 18, .max = 26 },
 257         .m2 = { .min = 6, .max = 16 },
 258         .p = { .min = 4, .max = 128 },
 259         .p1 = { .min = 2, .max = 33 },
 260         .p2 = { .dot_limit = 165000,
 261                 .p2_slow = 4, .p2_fast = 2 },
 262 };
 263
 264 static const intel_limit_t intel_limits_i8xx_dvo = {
 265         .dot = { .min = 25000, .max = 350000 },
 266         .vco = { .min = 908000, .max = 1512000 },
 267         .n = { .min = 2, .max = 16 },
 268         .m = { .min = 96, .max = 140 },
 269         .m1 = { .min = 18, .max = 26 },
 270         .m2 = { .min = 6, .max = 16 },
 271         .p = { .min = 4, .max = 128 },
 272         .p1 = { .min = 2, .max = 33 },
 273         .p2 = { .dot_limit = 165000,
 274                 .p2_slow = 4, .p2_fast = 4 },
 275 };
 276
 277 static const intel_limit_t intel_limits_i8xx_lvds = {
 278         .dot = { .min = 25000, .max = 350000 },
 279         .vco = { .min = 908000, .max = 1512000 },
 280         .n = { .min = 2, .max = 16 },
 281         .m = { .min = 96, .max = 140 },
 282         .m1 = { .min = 18, .max = 26 },
 283         .m2 = { .min = 6, .max = 16 },
 284         .p = { .min = 4, .max = 128 },
 285         .p1 = { .min = 1, .max = 6 },
 286         .p2 = { .dot_limit = 165000,
 287                 .p2_slow = 14, .p2_fast = 7 },
 288 };
 289
 290 static const intel_limit_t intel_limits_i9xx_sdvo = {
 291         .dot = { .min = 20000, .max = 400000 },
 292         .vco = { .min = 1400000, .max = 2800000 },
 293         .n = { .min = 1, .max = 6 },
 294         .m = { .min = 70, .max = 120 },
 295         .m1 = { .min = 8, .max = 18 },
 296         .m2 = { .min = 3, .max = 7 },
 297         .p = { .min = 5, .max = 80 },
 298         .p1 = { .min = 1, .max = 8 },
 299         .p2 = { .dot_limit = 200000,
 300                 .p2_slow = 10, .p2_fast = 5 },
 301 };
 302
 303 static const intel_limit_t intel_limits_i9xx_lvds = {
 304         .dot = { .min = 20000, .max = 400000 },
 305         .vco = { .min = 1400000, .max = 2800000 },
 306         .n = { .min = 1, .max = 6 },
 307         .m = { .min = 70, .max = 120 },
 308         .m1 = { .min = 8, .max = 18 },
 309         .m2 = { .min = 3, .max = 7 },
 310         .p = { .min = 7, .max = 98 },
 311         .p1 = { .min = 1, .max = 8 },
 312         .p2 = { .dot_limit = 112000,
 313                 .p2_slow = 14, .p2_fast = 7 },
 314 };
 315
 316
 317 static const intel_limit_t intel_limits_g4x_sdvo = {
 318         .dot = { .min = 25000, .max = 270000 },
 319         .vco = { .min = 1750000, .max = 3500000},
 320         .n = { .min = 1, .max = 4 },
 321         .m = { .min = 104, .max = 138 },
 322         .m1 = { .min = 17, .max = 23 },
 323         .m2 = { .min = 5, .max = 11 },
 324         .p = { .min = 10, .max = 30 },
 325         .p1 = { .min = 1, .max = 3},
 326         .p2 = { .dot_limit = 270000,
 327                 .p2_slow = 10,
 328                 .p2_fast = 10
 329         },
 330 };
 331
 332 static const intel_limit_t intel_limits_g4x_hdmi = {
 333         .dot = { .min = 22000, .max = 400000 },
 334         .vco = { .min = 1750000, .max = 3500000},
 335         .n = { .min = 1, .max = 4 },
 336         .m = { .min = 104, .max = 138 },
 337         .m1 = { .min = 16, .max = 23 },
 338         .m2 = { .min = 5, .max = 11 },
 339         .p = { .min = 5, .max = 80 },
 340         .p1 = { .min = 1, .max = 8},
 341         .p2 = { .dot_limit = 165000,
 342                 .p2_slow = 10, .p2_fast = 5 },
 343 };
 344
 345 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 346         .dot = { .min = 20000, .max = 115000 },
 347         .vco = { .min = 1750000, .max = 3500000 },
 348         .n = { .min = 1, .max = 3 },
 349         .m = { .min = 104, .max = 138 },
 350         .m1 = { .min = 17, .max = 23 },
 351         .m2 = { .min = 5, .max = 11 },
 352         .p = { .min = 28, .max = 112 },
 353         .p1 = { .min = 2, .max = 8 },
 354         .p2 = { .dot_limit = 0,
 355                 .p2_slow = 14, .p2_fast = 14
 356         },
 357 };
 358
 359 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 360         .dot = { .min = 80000, .max = 224000 },
 361         .vco = { .min = 1750000, .max = 3500000 },
 362         .n = { .min = 1, .max = 3 },
 363         .m = { .min = 104, .max = 138 },
 364         .m1 = { .min = 17, .max = 23 },
 365         .m2 = { .min = 5, .max = 11 },
 366         .p = { .min = 14, .max = 42 },
 367         .p1 = { .min = 2, .max = 6 },
 368         .p2 = { .dot_limit = 0,
 369                 .p2_slow = 7, .p2_fast = 7
 370         },
 371 };
 372
 373 static const intel_limit_t intel_limits_pineview_sdvo = {
 374         .dot = { .min = 20000, .max = 400000},
 375         .vco = { .min = 1700000, .max = 3500000 },
 376         /* Pineview's Ncounter is a ring counter */
 377         .n = { .min = 3, .max = 6 },
 378         .m = { .min = 2, .max = 256 },
 379         /* Pineview only has one combined m divider, which we treat as m2. */
 380         .m1 = { .min = 0, .max = 0 },
 381         .m2 = { .min = 0, .max = 254 },
 382         .p = { .min = 5, .max = 80 },
 383         .p1 = { .min = 1, .max = 8 },
 384         .p2 = { .dot_limit = 200000,
 385                 .p2_slow = 10, .p2_fast = 5 },
 386 };
 387
 388 static const intel_limit_t intel_limits_pineview_lvds = {
 389         .dot = { .min = 20000, .max = 400000 },
 390         .vco = { .min = 1700000, .max = 3500000 },
 391         .n = { .min = 3, .max = 6 },
 392         .m = { .min = 2, .max = 256 },
 393         .m1 = { .min = 0, .max = 0 },
 394         .m2 = { .min = 0, .max = 254 },
 395         .p = { .min = 7, .max = 112 },
 396         .p1 = { .min = 1, .max = 8 },
 397         .p2 = { .dot_limit = 112000,
 398                 .p2_slow = 14, .p2_fast = 14 },
 399 };
 400
 401 /* Ironlake / Sandybridge
 402  *
 403  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 404  * the range value for them is (actual_value - 2).
 405  */
 406 static const intel_limit_t intel_limits_ironlake_dac = {
 407         .dot = { .min = 25000, .max = 350000 },
 408         .vco = { .min = 1760000, .max = 3510000 },
 409         .n = { .min = 1, .max = 5 },
 410         .m = { .min = 79, .max = 127 },
 411         .m1 = { .min = 12, .max = 22 },
 412         .m2 = { .min = 5, .max = 9 },
 413         .p = { .min = 5, .max = 80 },
 414         .p1 = { .min = 1, .max = 8 },
 415         .p2 = { .dot_limit = 225000,
 416                 .p2_slow = 10, .p2_fast = 5 },
 417 };
 418
 419 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 420         .dot = { .min = 25000, .max = 350000 },
 421         .vco = { .min = 1760000, .max = 3510000 },
 422         .n = { .min = 1, .max = 3 },
 423         .m = { .min = 79, .max = 118 },
 424         .m1 = { .min = 12, .max = 22 },
 425         .m2 = { .min = 5, .max = 9 },
 426         .p = { .min = 28, .max = 112 },
 427         .p1 = { .min = 2, .max = 8 },
 428         .p2 = { .dot_limit = 225000,
 429                 .p2_slow = 14, .p2_fast = 14 },
 430 };
 431
 432 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 433         .dot = { .min = 25000, .max = 350000 },
 434         .vco = { .min = 1760000, .max = 3510000 },
 435         .n = { .min = 1, .max = 3 },
 436         .m = { .min = 79, .max = 127 },
 437         .m1 = { .min = 12, .max = 22 },
 438         .m2 = { .min = 5, .max = 9 },
 439         .p = { .min = 14, .max = 56 },
 440         .p1 = { .min = 2, .max = 8 },
 441         .p2 = { .dot_limit = 225000,
 442                 .p2_slow = 7, .p2_fast = 7 },
 443 };
 444
 445 /* LVDS 100mhz refclk limits. */
 446 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 447         .dot = { .min = 25000, .max = 350000 },
 448         .vco = { .min = 1760000, .max = 3510000 },
 449         .n = { .min = 1, .max = 2 },
 450         .m = { .min = 79, .max = 126 },
 451         .m1 = { .min = 12, .max = 22 },
 452         .m2 = { .min = 5, .max = 9 },
 453         .p = { .min = 28, .max = 112 },
 454         .p1 = { .min = 2, .max = 8 },
 455         .p2 = { .dot_limit = 225000,
 456                 .p2_slow = 14, .p2_fast = 14 },
 457 };
 458
 459 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 460         .dot = { .min = 25000, .max = 350000 },
 461         .vco = { .min = 1760000, .max = 3510000 },
 462         .n = { .min = 1, .max = 3 },
 463         .m = { .min = 79, .max = 126 },
 464         .m1 = { .min = 12, .max = 22 },
 465         .m2 = { .min = 5, .max = 9 },
 466         .p = { .min = 14, .max = 42 },
 467         .p1 = { .min = 2, .max = 6 },
 468         .p2 = { .dot_limit = 225000,
 469                 .p2_slow = 7, .p2_fast = 7 },
 470 };
 471
 472 static const intel_limit_t intel_limits_vlv = {
 473          /*
 474           * These are the data rate limits (measured in fast clocks)
 475           * since those are the strictest limits we have. The fast
 476           * clock and actual rate limits are more relaxed, so checking
 477           * them would make no difference.
 478           */
 479         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 480         .vco = { .min = 4000000, .max = 6000000 },
 481         .n = { .min = 1, .max = 7 },
 482         .m1 = { .min = 2, .max = 3 },
 483         .m2 = { .min = 11, .max = 156 },
 484         .p1 = { .min = 2, .max = 3 },
 485         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 486 };
 487
 488 static const intel_limit_t intel_limits_chv = {
 489         /*
 490          * These are the data rate limits (measured in fast clocks)
 491          * since those are the strictest limits we have.  The fast
 492          * clock and actual rate limits are more relaxed, so checking
 493          * them would make no difference.
 494          */
 495         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 496         .vco = { .min = 4800000, .max = 6480000 },
 497         .n = { .min = 1, .max = 1 },
 498         .m1 = { .min = 2, .max = 2 },
 499         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 500         .p1 = { .min = 2, .max = 4 },
 501         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 502 };
 503
 504 static const intel_limit_t intel_limits_bxt = {
 505         /* FIXME: find real dot limits */
 506         .dot = { .min = 0, .max = INT_MAX },
 507         .vco = { .min = 4800000, .max = 6700000 },
 508         .n = { .min = 1, .max = 1 },
 509         .m1 = { .min = 2, .max = 2 },
 510         /* FIXME: find real m2 limits */
 511         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 512         .p1 = { .min = 2, .max = 4 },
 513         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 514 };
 515
 516 static bool
 517 needs_modeset(struct drm_crtc_state *state)
 518 {
 519         return drm_atomic_crtc_needs_modeset(state);
 520 }
 521
 522 /**
 523  * Returns whether any output on the specified pipe is of the specified type
 524  */
 525 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
 526 {
 527         struct drm_device *dev = crtc->base.dev;
 528         struct intel_encoder *encoder;
 529
 530         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
 531                 if (encoder->type == type)
 532                         return true;
 533
 534         return false;
 535 }
 536
 537 /**
 538  * Returns whether any output on the specified pipe will have the specified
 539  * type after a staged modeset is complete, i.e., the same as
 540  * intel_pipe_has_type() but looking at encoder->new_crtc instead of
 541  * encoder->crtc.
 542  */
 543 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
 544                                       int type)
 545 {
 546         struct drm_atomic_state *state = crtc_state->base.state;
 547         struct drm_connector *connector;
 548         struct drm_connector_state *connector_state;
 549         struct intel_encoder *encoder;
 550         int i, num_connectors = 0;
 551
 552         for_each_connector_in_state(state, connector, connector_state, i) {
 553                 if (connector_state->crtc != crtc_state->base.crtc)
 554                         continue;
 555
 556                 num_connectors++;
 557
 558                 encoder = to_intel_encoder(connector_state->best_encoder);
 559                 if (encoder->type == type)
 560                         return true;
 561         }
 562
 563         WARN_ON(num_connectors == 0);
 564
 565         return false;
 566 }
 567
 568 static const intel_limit_t *
 569 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
 570 {
 571         struct drm_device *dev = crtc_state->base.crtc->dev;
 572         const intel_limit_t *limit;
 573
 574         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 575                 if (intel_is_dual_link_lvds(dev)) {
 576                         if (refclk == 100000)
 577                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 578                         else
 579                                 limit = &intel_limits_ironlake_dual_lvds;
 580                 } else {
 581                         if (refclk == 100000)
 582                                 limit = &intel_limits_ironlake_single_lvds_100m;
 583                         else
 584                                 limit = &intel_limits_ironlake_single_lvds;
 585                 }
 586         } else
 587                 limit = &intel_limits_ironlake_dac;
 588
 589         return limit;
 590 }
 591
 592 static const intel_limit_t *
 593 intel_g4x_limit(struct intel_crtc_state *crtc_state)
 594 {
 595         struct drm_device *dev = crtc_state->base.crtc->dev;
 596         const intel_limit_t *limit;
 597
 598         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 599                 if (intel_is_dual_link_lvds(dev))
 600                         limit = &intel_limits_g4x_dual_channel_lvds;
 601                 else
 602                         limit = &intel_limits_g4x_single_channel_lvds;
 603         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
 604                    intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
 605                 limit = &intel_limits_g4x_hdmi;
 606         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
 607                 limit = &intel_limits_g4x_sdvo;
 608         } else /* The option is for other outputs */
 609                 limit = &intel_limits_i9xx_sdvo;
 610
 611         return limit;
 612 }
 613
 614 static const intel_limit_t *
 615 intel_limit(struct intel_crtc_state *crtc_state, int refclk)
 616 {
 617         struct drm_device *dev = crtc_state->base.crtc->dev;
 618         const intel_limit_t *limit;
 619
 620         if (IS_BROXTON(dev))
 621                 limit = &intel_limits_bxt;
 622         else if (HAS_PCH_SPLIT(dev))
 623                 limit = intel_ironlake_limit(crtc_state, refclk);
 624         else if (IS_G4X(dev)) {
 625                 limit = intel_g4x_limit(crtc_state);
 626         } else if (IS_PINEVIEW(dev)) {
 627                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 628                         limit = &intel_limits_pineview_lvds;
 629                 else
 630                         limit = &intel_limits_pineview_sdvo;
 631         } else if (IS_CHERRYVIEW(dev)) {
 632                 limit = &intel_limits_chv;
 633         } else if (IS_VALLEYVIEW(dev)) {
 634                 limit = &intel_limits_vlv;
 635         } else if (!IS_GEN2(dev)) {
 636                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 637                         limit = &intel_limits_i9xx_lvds;
 638                 else
 639                         limit = &intel_limits_i9xx_sdvo;
 640         } else {
 641                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 642                         limit = &intel_limits_i8xx_lvds;
 643                 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
 644                         limit = &intel_limits_i8xx_dvo;
 645                 else
 646                         limit = &intel_limits_i8xx_dac;
 647         }
 648         return limit;
 649 }
 650
 651 /*
 652  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
 653  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
 654  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
 655  * The helpers' return value is the rate of the clock that is fed to the
 656  * display engine's pipe which can be the above fast dot clock rate or a
 657  * divided-down version of it.
 658  */
 659 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 660 static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
 661 {
 662         clock->m = clock->m2 + 2;
 663         clock->p = clock->p1 * clock->p2;
 664         if (WARN_ON(clock->n == 0 || clock->p == 0))
 665                 return 0;
 666         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 667         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 668
 669         return clock->dot;
 670 }
 671
 672 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 673 {
 674         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 675 }
 676
 677 static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
 678 {
 679         clock->m = i9xx_dpll_compute_m(clock);
 680         clock->p = clock->p1 * clock->p2;
 681         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 682                 return 0;
 683         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 684         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 685
 686         return clock->dot;
 687 }
 688
 689 static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
 690 {
 691         clock->m = clock->m1 * clock->m2;
 692         clock->p = clock->p1 * clock->p2;
 693         if (WARN_ON(clock->n == 0 || clock->p == 0))
 694                 return 0;
 695         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 696         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 697
 698         return clock->dot / 5;
 699 }
 700
 701 int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
 702 {
 703         clock->m = clock->m1 * clock->m2;
 704         clock->p = clock->p1 * clock->p2;
 705         if (WARN_ON(clock->n == 0 || clock->p == 0))
 706                 return 0;
 707         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 708                         clock->n << 22);
 709         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 710
 711         return clock->dot / 5;
 712 }
 713
 714 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 715 /**
 716  * Returns whether the given set of divisors are valid for a given refclk with
 717  * the given connectors.
 718  */
 719
 720 static bool intel_PLL_is_valid(struct drm_device *dev,
 721                                const intel_limit_t *limit,
 722                                const intel_clock_t *clock)
 723 {
 724         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 725                 INTELPllInvalid("n out of range\n");
 726         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 727                 INTELPllInvalid("p1 out of range\n");
 728         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 729                 INTELPllInvalid("m2 out of range\n");
 730         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 731                 INTELPllInvalid("m1 out of range\n");
 732
 733         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) &&
 734             !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev))
 735                 if (clock->m1 <= clock->m2)
 736                         INTELPllInvalid("m1 <= m2\n");
 737
 738         if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) {
 739                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 740                         INTELPllInvalid("p out of range\n");
 741                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 742                         INTELPllInvalid("m out of range\n");
 743         }
 744
 745         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 746                 INTELPllInvalid("vco out of range\n");
 747         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 748          * connector, etc., rather than just a single range.
 749          */
 750         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 751                 INTELPllInvalid("dot out of range\n");
 752
 753         return true;
 754 }
 755
 756 static int
 757 i9xx_select_p2_div(const intel_limit_t *limit,
 758                    const struct intel_crtc_state *crtc_state,
 759                    int target)
 760 {
 761         struct drm_device *dev = crtc_state->base.crtc->dev;
 762
 763         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 764                 /*
 765                  * For LVDS just rely on its current settings for dual-channel.
 766                  * We haven't figured out how to reliably set up different
 767                  * single/dual channel state, if we even can.
 768                  */
 769                 if (intel_is_dual_link_lvds(dev))
 770                         return limit->p2.p2_fast;
 771                 else
 772                         return limit->p2.p2_slow;
 773         } else {
 774                 if (target < limit->p2.dot_limit)
 775                         return limit->p2.p2_slow;
 776                 else
 777                         return limit->p2.p2_fast;
 778         }
 779 }
 780
 781 static bool
 782 i9xx_find_best_dpll(const intel_limit_t *limit,
 783                     struct intel_crtc_state *crtc_state,
 784                     int target, int refclk, intel_clock_t *match_clock,
 785                     intel_clock_t *best_clock)
 786 {
 787         struct drm_device *dev = crtc_state->base.crtc->dev;
 788         intel_clock_t clock;
 789         int err = target;
 790
 791         memset(best_clock, 0, sizeof(*best_clock));
 792
 793         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 794
 795         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 796              clock.m1++) {
 797                 for (clock.m2 = limit->m2.min;
 798                      clock.m2 <= limit->m2.max; clock.m2++) {
 799                         if (clock.m2 >= clock.m1)
 800                                 break;
 801                         for (clock.n = limit->n.min;
 802                              clock.n <= limit->n.max; clock.n++) {
 803                                 for (clock.p1 = limit->p1.min;
 804                                         clock.p1 <= limit->p1.max; clock.p1++) {
 805                                         int this_err;
 806
 807                                         i9xx_calc_dpll_params(refclk, &clock);
 808                                         if (!intel_PLL_is_valid(dev, limit,
 809                                                                 &clock))
 810                                                 continue;
 811                                         if (match_clock &&
 812                                             clock.p != match_clock->p)
 813                                                 continue;
 814
 815                                         this_err = abs(clock.dot - target);
 816                                         if (this_err < err) {
 817                                                 *best_clock = clock;
 818                                                 err = this_err;
 819                                         }
 820                                 }
 821                         }
 822                 }
 823         }
 824
 825         return (err != target);
 826 }
 827
 828 static bool
 829 pnv_find_best_dpll(const intel_limit_t *limit,
 830                    struct intel_crtc_state *crtc_state,
 831                    int target, int refclk, intel_clock_t *match_clock,
 832                    intel_clock_t *best_clock)
 833 {
 834         struct drm_device *dev = crtc_state->base.crtc->dev;
 835         intel_clock_t clock;
 836         int err = target;
 837
 838         memset(best_clock, 0, sizeof(*best_clock));
 839
 840         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 841
 842         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 843              clock.m1++) {
 844                 for (clock.m2 = limit->m2.min;
 845                      clock.m2 <= limit->m2.max; clock.m2++) {
 846                         for (clock.n = limit->n.min;
 847                              clock.n <= limit->n.max; clock.n++) {
 848                                 for (clock.p1 = limit->p1.min;
 849                                         clock.p1 <= limit->p1.max; clock.p1++) {
 850                                         int this_err;
 851
 852                                         pnv_calc_dpll_params(refclk, &clock);
 853                                         if (!intel_PLL_is_valid(dev, limit,
 854                                                                 &clock))
 855                                                 continue;
 856                                         if (match_clock &&
 857                                             clock.p != match_clock->p)
 858                                                 continue;
 859
 860                                         this_err = abs(clock.dot - target);
 861                                         if (this_err < err) {
 862                                                 *best_clock = clock;
 863                                                 err = this_err;
 864                                         }
 865                                 }
 866                         }
 867                 }
 868         }
 869
 870         return (err != target);
 871 }
 872
 873 static bool
 874 g4x_find_best_dpll(const intel_limit_t *limit,
 875                    struct intel_crtc_state *crtc_state,
 876                    int target, int refclk, intel_clock_t *match_clock,
 877                    intel_clock_t *best_clock)
 878 {
 879         struct drm_device *dev = crtc_state->base.crtc->dev;
 880         intel_clock_t clock;
 881         int max_n;
 882         bool found = false;
 883         /* approximately equals target * 0.00585 */
 884         int err_most = (target >> 8) + (target >> 9);
 885
 886         memset(best_clock, 0, sizeof(*best_clock));
 887
 888         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 889
 890         max_n = limit->n.max;
 891         /* based on hardware requirement, prefer smaller n to precision */
 892         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 893                 /* based on hardware requirement, prefere larger m1,m2 */
 894                 for (clock.m1 = limit->m1.max;
 895                      clock.m1 >= limit->m1.min; clock.m1--) {
 896                         for (clock.m2 = limit->m2.max;
 897                              clock.m2 >= limit->m2.min; clock.m2--) {
 898                                 for (clock.p1 = limit->p1.max;
 899                                      clock.p1 >= limit->p1.min; clock.p1--) {
 900                                         int this_err;
 901
 902                                         i9xx_calc_dpll_params(refclk, &clock);
 903                                         if (!intel_PLL_is_valid(dev, limit,
 904                                                                 &clock))
 905                                                 continue;
 906
 907                                         this_err = abs(clock.dot - target);
 908                                         if (this_err < err_most) {
 909                                                 *best_clock = clock;
 910                                                 err_most = this_err;
 911                                                 max_n = clock.n;
 912                                                 found = true;
 913                                         }
 914                                 }
 915                         }
 916                 }
 917         }
 918         return found;
 919 }
 920
 921 /*
 922  * Check if the calculated PLL configuration is more optimal compared to the
 923  * best configuration and error found so far. Return the calculated error.
 924  */
 925 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 926                                const intel_clock_t *calculated_clock,
 927                                const intel_clock_t *best_clock,
 928                                unsigned int best_error_ppm,
 929                                unsigned int *error_ppm)
 930 {
 931         /*
 932          * For CHV ignore the error and consider only the P value.
 933          * Prefer a bigger P value based on HW requirements.
 934          */
 935         if (IS_CHERRYVIEW(dev)) {
 936                 *error_ppm = 0;
 937
 938                 return calculated_clock->p > best_clock->p;
 939         }
 940
 941         if (WARN_ON_ONCE(!target_freq))
 942                 return false;
 943
 944         *error_ppm = div_u64(1000000ULL *
 945                                 abs(target_freq - calculated_clock->dot),
 946                              target_freq);
 947         /*
 948          * Prefer a better P value over a better (smaller) error if the error
 949          * is small. Ensure this preference for future configurations too by
 950          * setting the error to 0.
 951          */
 952         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 953                 *error_ppm = 0;
 954
 955                 return true;
 956         }
 957
 958         return *error_ppm + 10 < best_error_ppm;
 959 }
 960
 961 static bool
 962 vlv_find_best_dpll(const intel_limit_t *limit,
 963                    struct intel_crtc_state *crtc_state,
 964                    int target, int refclk, intel_clock_t *match_clock,
 965                    intel_clock_t *best_clock)
 966 {
 967         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 968         struct drm_device *dev = crtc->base.dev;
 969         intel_clock_t clock;
 970         unsigned int bestppm = 1000000;
 971         /* min update 19.2 MHz */
 972         int max_n = min(limit->n.max, refclk / 19200);
 973         bool found = false;
 974
 975         target *= 5; /* fast clock */
 976
 977         memset(best_clock, 0, sizeof(*best_clock));
 978
 979         /* based on hardware requirement, prefer smaller n to precision */
 980         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 981                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 982                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 983                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 984                                 clock.p = clock.p1 * clock.p2;
 985                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 986                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 987                                         unsigned int ppm;
 988
 989                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 990                                                                      refclk * clock.m1);
 991
 992                                         vlv_calc_dpll_params(refclk, &clock);
 993
 994                                         if (!intel_PLL_is_valid(dev, limit,
 995                                                                 &clock))
 996                                                 continue;
 997
 998                                         if (!vlv_PLL_is_optimal(dev, target,
 999                                                                 &clock,
1000                                                                 best_clock,
1001                                                                 bestppm, &ppm))
1002                                                 continue;
1003
1004                                         *best_clock = clock;
1005                                         bestppm = ppm;
1006                                         found = true;
1007                                 }
1008                         }
1009                 }
1010         }
1011
1012         return found;
1013 }
1014
1015 static bool
1016 chv_find_best_dpll(const intel_limit_t *limit,
1017                    struct intel_crtc_state *crtc_state,
1018                    int target, int refclk, intel_clock_t *match_clock,
1019                    intel_clock_t *best_clock)
1020 {
1021         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1022         struct drm_device *dev = crtc->base.dev;
1023         unsigned int best_error_ppm;
1024         intel_clock_t clock;
1025         uint64_t m2;
1026         int found = false;
1027
1028         memset(best_clock, 0, sizeof(*best_clock));
1029         best_error_ppm = 1000000;
1030
1031         /*
1032          * Based on hardware doc, the n always set to 1, and m1 always
1033          * set to 2.  If requires to support 200Mhz refclk, we need to
1034          * revisit this because n may not 1 anymore.
1035          */
1036         clock.n = 1, clock.m1 = 2;
1037         target *= 5;    /* fast clock */
1038
1039         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
1040                 for (clock.p2 = limit->p2.p2_fast;
1041                                 clock.p2 >= limit->p2.p2_slow;
1042                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
1043                         unsigned int error_ppm;
1044
1045                         clock.p = clock.p1 * clock.p2;
1046
1047                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
1048                                         clock.n) << 22, refclk * clock.m1);
1049
1050                         if (m2 > INT_MAX/clock.m1)
1051                                 continue;
1052
1053                         clock.m2 = m2;
1054
1055                         chv_calc_dpll_params(refclk, &clock);
1056
1057                         if (!intel_PLL_is_valid(dev, limit, &clock))
1058                                 continue;
1059
1060                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1061                                                 best_error_ppm, &error_ppm))
1062                                 continue;
1063
1064                         *best_clock = clock;
1065                         best_error_ppm = error_ppm;
1066                         found = true;
1067                 }
1068         }
1069
1070         return found;
1071 }
1072
1073 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1074                         intel_clock_t *best_clock)
1075 {
1076         int refclk = i9xx_get_refclk(crtc_state, 0);
1077
1078         return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
1079                                   target_clock, refclk, NULL, best_clock);
1080 }
1081
1082 bool intel_crtc_active(struct drm_crtc *crtc)
1083 {
1084         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1085
1086         /* Be paranoid as we can arrive here with only partial
1087          * state retrieved from the hardware during setup.
1088          *
1089          * We can ditch the adjusted_mode.crtc_clock check as soon
1090          * as Haswell has gained clock readout/fastboot support.
1091          *
1092          * We can ditch the crtc->primary->fb check as soon as we can
1093          * properly reconstruct framebuffers.
1094          *
1095          * FIXME: The intel_crtc->active here should be switched to
1096          * crtc->state->active once we have proper CRTC states wired up
1097          * for atomic.
1098          */
1099         return intel_crtc->active && crtc->primary->state->fb &&
1100                 intel_crtc->config->base.adjusted_mode.crtc_clock;
1101 }
1102
1103 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1104                                              enum pipe pipe)
1105 {
1106         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1107         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1108
1109         return intel_crtc->config->cpu_transcoder;
1110 }
1111
1112 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1113 {
1114         struct drm_i915_private *dev_priv = dev->dev_private;
1115         i915_reg_t reg = PIPEDSL(pipe);
1116         u32 line1, line2;
1117         u32 line_mask;
1118
1119         if (IS_GEN2(dev))
1120                 line_mask = DSL_LINEMASK_GEN2;
1121         else
1122                 line_mask = DSL_LINEMASK_GEN3;
1123
1124         line1 = I915_READ(reg) & line_mask;
1125         msleep(5);
1126         line2 = I915_READ(reg) & line_mask;
1127
1128         return line1 == line2;
1129 }
1130
1131 /*
1132  * intel_wait_for_pipe_off - wait for pipe to turn off
1133  * @crtc: crtc whose pipe to wait for
1134  *
1135  * After disabling a pipe, we can't wait for vblank in the usual way,
1136  * spinning on the vblank interrupt status bit, since we won't actually
1137  * see an interrupt when the pipe is disabled.
1138  *
1139  * On Gen4 and above:
1140  *   wait for the pipe register state bit to turn off
1141  *
1142  * Otherwise:
1143  *   wait for the display line value to settle (it usually
1144  *   ends up stopping at the start of the next frame).
1145  *
1146  */
1147 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1148 {
1149         struct drm_device *dev = crtc->base.dev;
1150         struct drm_i915_private *dev_priv = dev->dev_private;
1151         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1152         enum pipe pipe = crtc->pipe;
1153
1154         if (INTEL_INFO(dev)->gen >= 4) {
1155                 i915_reg_t reg = PIPECONF(cpu_transcoder);
1156
1157                 /* Wait for the Pipe State to go off */
1158                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1159                              100))
1160                         WARN(1, "pipe_off wait timed out\n");
1161         } else {
1162                 /* Wait for the display line to settle */
1163                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1164                         WARN(1, "pipe_off wait timed out\n");
1165         }
1166 }
1167
1168 /* Only for pre-ILK configs */
1169 void assert_pll(struct drm_i915_private *dev_priv,
1170                 enum pipe pipe, bool state)
1171 {
1172         u32 val;
1173         bool cur_state;
1174
1175         val = I915_READ(DPLL(pipe));
1176         cur_state = !!(val & DPLL_VCO_ENABLE);
1177         I915_STATE_WARN(cur_state != state,
1178              "PLL state assertion failure (expected %s, current %s)\n",
1179                         onoff(state), onoff(cur_state));
1180 }
1181
1182 /* XXX: the dsi pll is shared between MIPI DSI ports */
1183 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1184 {
1185         u32 val;
1186         bool cur_state;
1187
1188         mutex_lock(&dev_priv->sb_lock);
1189         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1190         mutex_unlock(&dev_priv->sb_lock);
1191
1192         cur_state = val & DSI_PLL_VCO_EN;
1193         I915_STATE_WARN(cur_state != state,
1194              "DSI PLL state assertion failure (expected %s, current %s)\n",
1195                         onoff(state), onoff(cur_state));
1196 }
1197 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1198 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1199
1200 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1201                           enum pipe pipe, bool state)
1202 {
1203         bool cur_state;
1204         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1205                                                                       pipe);
1206
1207         if (HAS_DDI(dev_priv->dev)) {
1208                 /* DDI does not have a specific FDI_TX register */
1209                 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1210                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1211         } else {
1212                 u32 val = I915_READ(FDI_TX_CTL(pipe));
1213                 cur_state = !!(val & FDI_TX_ENABLE);
1214         }
1215         I915_STATE_WARN(cur_state != state,
1216              "FDI TX state assertion failure (expected %s, current %s)\n",
1217                         onoff(state), onoff(cur_state));
1218 }
1219 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1220 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1221
1222 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1223                           enum pipe pipe, bool state)
1224 {
1225         u32 val;
1226         bool cur_state;
1227
1228         val = I915_READ(FDI_RX_CTL(pipe));
1229         cur_state = !!(val & FDI_RX_ENABLE);
1230         I915_STATE_WARN(cur_state != state,
1231              "FDI RX state assertion failure (expected %s, current %s)\n",
1232                         onoff(state), onoff(cur_state));
1233 }
1234 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1235 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1236
1237 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1238                                       enum pipe pipe)
1239 {
1240         u32 val;
1241
1242         /* ILK FDI PLL is always enabled */
1243         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1244                 return;
1245
1246         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1247         if (HAS_DDI(dev_priv->dev))
1248                 return;
1249
1250         val = I915_READ(FDI_TX_CTL(pipe));
1251         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1252 }
1253
1254 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1255                        enum pipe pipe, bool state)
1256 {
1257         u32 val;
1258         bool cur_state;
1259
1260         val = I915_READ(FDI_RX_CTL(pipe));
1261         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1262         I915_STATE_WARN(cur_state != state,
1263              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1264                         onoff(state), onoff(cur_state));
1265 }
1266
1267 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1268                            enum pipe pipe)
1269 {
1270         struct drm_device *dev = dev_priv->dev;
1271         i915_reg_t pp_reg;
1272         u32 val;
1273         enum pipe panel_pipe = PIPE_A;
1274         bool locked = true;
1275
1276         if (WARN_ON(HAS_DDI(dev)))
1277                 return;
1278
1279         if (HAS_PCH_SPLIT(dev)) {
1280                 u32 port_sel;
1281
1282                 pp_reg = PCH_PP_CONTROL;
1283                 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1284
1285                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1286                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1287                         panel_pipe = PIPE_B;
1288                 /* XXX: else fix for eDP */
1289         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1290                 /* presumably write lock depends on pipe, not port select */
1291                 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1292                 panel_pipe = pipe;
1293         } else {
1294                 pp_reg = PP_CONTROL;
1295                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1296                         panel_pipe = PIPE_B;
1297         }
1298
1299         val = I915_READ(pp_reg);
1300         if (!(val & PANEL_POWER_ON) ||
1301             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1302                 locked = false;
1303
1304         I915_STATE_WARN(panel_pipe == pipe && locked,
1305              "panel assertion failure, pipe %c regs locked\n",
1306              pipe_name(pipe));
1307 }
1308
1309 static void assert_cursor(struct drm_i915_private *dev_priv,
1310                           enum pipe pipe, bool state)
1311 {
1312         struct drm_device *dev = dev_priv->dev;
1313         bool cur_state;
1314
1315         if (IS_845G(dev) || IS_I865G(dev))
1316                 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1317         else
1318                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1319
1320         I915_STATE_WARN(cur_state != state,
1321              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1322                         pipe_name(pipe), onoff(state), onoff(cur_state));
1323 }
1324 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1325 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1326
1327 void assert_pipe(struct drm_i915_private *dev_priv,
1328                  enum pipe pipe, bool state)
1329 {
1330         bool cur_state;
1331         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1332                                                                       pipe);
1333         enum intel_display_power_domain power_domain;
1334
1335         /* if we need the pipe quirk it must be always on */
1336         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1337             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1338                 state = true;
1339
1340         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1341         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1342                 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1343                 cur_state = !!(val & PIPECONF_ENABLE);
1344
1345                 intel_display_power_put(dev_priv, power_domain);
1346         } else {
1347                 cur_state = false;
1348         }
1349
1350         I915_STATE_WARN(cur_state != state,
1351              "pipe %c assertion failure (expected %s, current %s)\n",
1352                         pipe_name(pipe), onoff(state), onoff(cur_state));
1353 }
1354
1355 static void assert_plane(struct drm_i915_private *dev_priv,
1356                          enum plane plane, bool state)
1357 {
1358         u32 val;
1359         bool cur_state;
1360
1361         val = I915_READ(DSPCNTR(plane));
1362         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1363         I915_STATE_WARN(cur_state != state,
1364              "plane %c assertion failure (expected %s, current %s)\n",
1365                         plane_name(plane), onoff(state), onoff(cur_state));
1366 }
1367
1368 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1369 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1370
1371 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1372                                    enum pipe pipe)
1373 {
1374         struct drm_device *dev = dev_priv->dev;
1375         int i;
1376
1377         /* Primary planes are fixed to pipes on gen4+ */
1378         if (INTEL_INFO(dev)->gen >= 4) {
1379                 u32 val = I915_READ(DSPCNTR(pipe));
1380                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1381                      "plane %c assertion failure, should be disabled but not\n",
1382                      plane_name(pipe));
1383                 return;
1384         }
1385
1386         /* Need to check both planes against the pipe */
1387         for_each_pipe(dev_priv, i) {
1388                 u32 val = I915_READ(DSPCNTR(i));
1389                 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1390                         DISPPLANE_SEL_PIPE_SHIFT;
1391                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1392                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1393                      plane_name(i), pipe_name(pipe));
1394         }
1395 }
1396
1397 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1398                                     enum pipe pipe)
1399 {
1400         struct drm_device *dev = dev_priv->dev;
1401         int sprite;
1402
1403         if (INTEL_INFO(dev)->gen >= 9) {
1404                 for_each_sprite(dev_priv, pipe, sprite) {
1405                         u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1406                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1407                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1408                              sprite, pipe_name(pipe));
1409                 }
1410         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1411                 for_each_sprite(dev_priv, pipe, sprite) {
1412                         u32 val = I915_READ(SPCNTR(pipe, sprite));
1413                         I915_STATE_WARN(val & SP_ENABLE,
1414                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1415                              sprite_name(pipe, sprite), pipe_name(pipe));
1416                 }
1417         } else if (INTEL_INFO(dev)->gen >= 7) {
1418                 u32 val = I915_READ(SPRCTL(pipe));
1419                 I915_STATE_WARN(val & SPRITE_ENABLE,
1420                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1421                      plane_name(pipe), pipe_name(pipe));
1422         } else if (INTEL_INFO(dev)->gen >= 5) {
1423                 u32 val = I915_READ(DVSCNTR(pipe));
1424                 I915_STATE_WARN(val & DVS_ENABLE,
1425                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1426                      plane_name(pipe), pipe_name(pipe));
1427         }
1428 }
1429
1430 static void assert_vblank_disabled(struct drm_crtc *crtc)
1431 {
1432         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1433                 drm_crtc_vblank_put(crtc);
1434 }
1435
1436 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1437                                     enum pipe pipe)
1438 {
1439         u32 val;
1440         bool enabled;
1441
1442         val = I915_READ(PCH_TRANSCONF(pipe));
1443         enabled = !!(val & TRANS_ENABLE);
1444         I915_STATE_WARN(enabled,
1445              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1446              pipe_name(pipe));
1447 }
1448
1449 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1450                             enum pipe pipe, u32 port_sel, u32 val)
1451 {
1452         if ((val & DP_PORT_EN) == 0)
1453                 return false;
1454
1455         if (HAS_PCH_CPT(dev_priv->dev)) {
1456                 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1457                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1458                         return false;
1459         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1460                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1461                         return false;
1462         } else {
1463                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1464                         return false;
1465         }
1466         return true;
1467 }
1468
1469 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1470                               enum pipe pipe, u32 val)
1471 {
1472         if ((val & SDVO_ENABLE) == 0)
1473                 return false;
1474
1475         if (HAS_PCH_CPT(dev_priv->dev)) {
1476                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1477                         return false;
1478         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1479                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1480                         return false;
1481         } else {
1482                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1483                         return false;
1484         }
1485         return true;
1486 }
1487
1488 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1489                               enum pipe pipe, u32 val)
1490 {
1491         if ((val & LVDS_PORT_EN) == 0)
1492                 return false;
1493
1494         if (HAS_PCH_CPT(dev_priv->dev)) {
1495                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1496                         return false;
1497         } else {
1498                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1499                         return false;
1500         }
1501         return true;
1502 }
1503
1504 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1505                               enum pipe pipe, u32 val)
1506 {
1507         if ((val & ADPA_DAC_ENABLE) == 0)
1508                 return false;
1509         if (HAS_PCH_CPT(dev_priv->dev)) {
1510                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1511                         return false;
1512         } else {
1513                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1514                         return false;
1515         }
1516         return true;
1517 }
1518
1519 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1520                                    enum pipe pipe, i915_reg_t reg,
1521                                    u32 port_sel)
1522 {
1523         u32 val = I915_READ(reg);
1524         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1525              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1526              i915_mmio_reg_offset(reg), pipe_name(pipe));
1527
1528         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1529              && (val & DP_PIPEB_SELECT),
1530              "IBX PCH dp port still using transcoder B\n");
1531 }
1532
1533 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1534                                      enum pipe pipe, i915_reg_t reg)
1535 {
1536         u32 val = I915_READ(reg);
1537         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1538              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1539              i915_mmio_reg_offset(reg), pipe_name(pipe));
1540
1541         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1542              && (val & SDVO_PIPE_B_SELECT),
1543              "IBX PCH hdmi port still using transcoder B\n");
1544 }
1545
1546 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1547                                       enum pipe pipe)
1548 {
1549         u32 val;
1550
1551         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1552         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1553         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1554
1555         val = I915_READ(PCH_ADPA);
1556         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1557              "PCH VGA enabled on transcoder %c, should be disabled\n",
1558              pipe_name(pipe));
1559
1560         val = I915_READ(PCH_LVDS);
1561         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1562              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1563              pipe_name(pipe));
1564
1565         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1566         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1567         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1568 }
1569
1570 static void vlv_enable_pll(struct intel_crtc *crtc,
1571                            const struct intel_crtc_state *pipe_config)
1572 {
1573         struct drm_device *dev = crtc->base.dev;
1574         struct drm_i915_private *dev_priv = dev->dev_private;
1575         i915_reg_t reg = DPLL(crtc->pipe);
1576         u32 dpll = pipe_config->dpll_hw_state.dpll;
1577
1578         assert_pipe_disabled(dev_priv, crtc->pipe);
1579
1580         /* PLL is protected by panel, make sure we can write it */
1581         if (IS_MOBILE(dev_priv->dev))
1582                 assert_panel_unlocked(dev_priv, crtc->pipe);
1583
1584         I915_WRITE(reg, dpll);
1585         POSTING_READ(reg);
1586         udelay(150);
1587
1588         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1589                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1590
1591         I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1592         POSTING_READ(DPLL_MD(crtc->pipe));
1593
1594         /* We do this three times for luck */
1595         I915_WRITE(reg, dpll);
1596         POSTING_READ(reg);
1597         udelay(150); /* wait for warmup */
1598         I915_WRITE(reg, dpll);
1599         POSTING_READ(reg);
1600         udelay(150); /* wait for warmup */
1601         I915_WRITE(reg, dpll);
1602         POSTING_READ(reg);
1603         udelay(150); /* wait for warmup */
1604 }
1605
1606 static void chv_enable_pll(struct intel_crtc *crtc,
1607                            const struct intel_crtc_state *pipe_config)
1608 {
1609         struct drm_device *dev = crtc->base.dev;
1610         struct drm_i915_private *dev_priv = dev->dev_private;
1611         int pipe = crtc->pipe;
1612         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1613         u32 tmp;
1614
1615         assert_pipe_disabled(dev_priv, crtc->pipe);
1616
1617         mutex_lock(&dev_priv->sb_lock);
1618
1619         /* Enable back the 10bit clock to display controller */
1620         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1621         tmp |= DPIO_DCLKP_EN;
1622         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1623
1624         mutex_unlock(&dev_priv->sb_lock);
1625
1626         /*
1627          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1628          */
1629         udelay(1);
1630
1631         /* Enable PLL */
1632         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1633
1634         /* Check PLL is locked */
1635         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1636                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1637
1638         /* not sure when this should be written */
1639         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1640         POSTING_READ(DPLL_MD(pipe));
1641 }
1642
1643 static int intel_num_dvo_pipes(struct drm_device *dev)
1644 {
1645         struct intel_crtc *crtc;
1646         int count = 0;
1647
1648         for_each_intel_crtc(dev, crtc)
1649                 count += crtc->base.state->active &&
1650                         intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1651
1652         return count;
1653 }
1654
1655 static void i9xx_enable_pll(struct intel_crtc *crtc)
1656 {
1657         struct drm_device *dev = crtc->base.dev;
1658         struct drm_i915_private *dev_priv = dev->dev_private;
1659         i915_reg_t reg = DPLL(crtc->pipe);
1660         u32 dpll = crtc->config->dpll_hw_state.dpll;
1661
1662         assert_pipe_disabled(dev_priv, crtc->pipe);
1663
1664         /* No really, not for ILK+ */
1665         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1666
1667         /* PLL is protected by panel, make sure we can write it */
1668         if (IS_MOBILE(dev) && !IS_I830(dev))
1669                 assert_panel_unlocked(dev_priv, crtc->pipe);
1670
1671         /* Enable DVO 2x clock on both PLLs if necessary */
1672         if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1673                 /*
1674                  * It appears to be important that we don't enable this
1675                  * for the current pipe before otherwise configuring the
1676                  * PLL. No idea how this should be handled if multiple
1677                  * DVO outputs are enabled simultaneosly.
1678                  */
1679                 dpll |= DPLL_DVO_2X_MODE;
1680                 I915_WRITE(DPLL(!crtc->pipe),
1681                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1682         }
1683
1684         /*
1685          * Apparently we need to have VGA mode enabled prior to changing
1686          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1687          * dividers, even though the register value does change.
1688          */
1689         I915_WRITE(reg, 0);
1690
1691         I915_WRITE(reg, dpll);
1692
1693         /* Wait for the clocks to stabilize. */
1694         POSTING_READ(reg);
1695         udelay(150);
1696
1697         if (INTEL_INFO(dev)->gen >= 4) {
1698                 I915_WRITE(DPLL_MD(crtc->pipe),
1699                            crtc->config->dpll_hw_state.dpll_md);
1700         } else {
1701                 /* The pixel multiplier can only be updated once the
1702                  * DPLL is enabled and the clocks are stable.
1703                  *
1704                  * So write it again.
1705                  */
1706                 I915_WRITE(reg, dpll);
1707         }
1708
1709         /* We do this three times for luck */
1710         I915_WRITE(reg, dpll);
1711         POSTING_READ(reg);
1712         udelay(150); /* wait for warmup */
1713         I915_WRITE(reg, dpll);
1714         POSTING_READ(reg);
1715         udelay(150); /* wait for warmup */
1716         I915_WRITE(reg, dpll);
1717         POSTING_READ(reg);
1718         udelay(150); /* wait for warmup */
1719 }
1720
1721 /**
1722  * i9xx_disable_pll - disable a PLL
1723  * @dev_priv: i915 private structure
1724  * @pipe: pipe PLL to disable
1725  *
1726  * Disable the PLL for @pipe, making sure the pipe is off first.
1727  *
1728  * Note!  This is for pre-ILK only.
1729  */
1730 static void i9xx_disable_pll(struct intel_crtc *crtc)
1731 {
1732         struct drm_device *dev = crtc->base.dev;
1733         struct drm_i915_private *dev_priv = dev->dev_private;
1734         enum pipe pipe = crtc->pipe;
1735
1736         /* Disable DVO 2x clock on both PLLs if necessary */
1737         if (IS_I830(dev) &&
1738             intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1739             !intel_num_dvo_pipes(dev)) {
1740                 I915_WRITE(DPLL(PIPE_B),
1741                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1742                 I915_WRITE(DPLL(PIPE_A),
1743                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1744         }
1745
1746         /* Don't disable pipe or pipe PLLs if needed */
1747         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1748             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1749                 return;
1750
1751         /* Make sure the pipe isn't still relying on us */
1752         assert_pipe_disabled(dev_priv, pipe);
1753
1754         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1755         POSTING_READ(DPLL(pipe));
1756 }
1757
1758 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1759 {
1760         u32 val;
1761
1762         /* Make sure the pipe isn't still relying on us */
1763         assert_pipe_disabled(dev_priv, pipe);
1764
1765         /*
1766          * Leave integrated clock source and reference clock enabled for pipe B.
1767          * The latter is needed for VGA hotplug / manual detection.
1768          */
1769         val = DPLL_VGA_MODE_DIS;
1770         if (pipe == PIPE_B)
1771                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV;
1772         I915_WRITE(DPLL(pipe), val);
1773         POSTING_READ(DPLL(pipe));
1774
1775 }
1776
1777 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1778 {
1779         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1780         u32 val;
1781
1782         /* Make sure the pipe isn't still relying on us */
1783         assert_pipe_disabled(dev_priv, pipe);
1784
1785         /* Set PLL en = 0 */
1786         val = DPLL_SSC_REF_CLK_CHV |
1787                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1788         if (pipe != PIPE_A)
1789                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1790         I915_WRITE(DPLL(pipe), val);
1791         POSTING_READ(DPLL(pipe));
1792
1793         mutex_lock(&dev_priv->sb_lock);
1794
1795         /* Disable 10bit clock to display controller */
1796         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1797         val &= ~DPIO_DCLKP_EN;
1798         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1799
1800         mutex_unlock(&dev_priv->sb_lock);
1801 }
1802
1803 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1804                          struct intel_digital_port *dport,
1805                          unsigned int expected_mask)
1806 {
1807         u32 port_mask;
1808         i915_reg_t dpll_reg;
1809
1810         switch (dport->port) {
1811         case PORT_B:
1812                 port_mask = DPLL_PORTB_READY_MASK;
1813                 dpll_reg = DPLL(0);
1814                 break;
1815         case PORT_C:
1816                 port_mask = DPLL_PORTC_READY_MASK;
1817                 dpll_reg = DPLL(0);
1818                 expected_mask <<= 4;
1819                 break;
1820         case PORT_D:
1821                 port_mask = DPLL_PORTD_READY_MASK;
1822                 dpll_reg = DPIO_PHY_STATUS;
1823                 break;
1824         default:
1825                 BUG();
1826         }
1827
1828         if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1829                 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1830                      port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1831 }
1832
1833 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1834                                            enum pipe pipe)
1835 {
1836         struct drm_device *dev = dev_priv->dev;
1837         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1838         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1839         i915_reg_t reg;
1840         uint32_t val, pipeconf_val;
1841
1842         /* PCH only available on ILK+ */
1843         BUG_ON(!HAS_PCH_SPLIT(dev));
1844
1845         /* Make sure PCH DPLL is enabled */
1846         assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1847
1848         /* FDI must be feeding us bits for PCH ports */
1849         assert_fdi_tx_enabled(dev_priv, pipe);
1850         assert_fdi_rx_enabled(dev_priv, pipe);
1851
1852         if (HAS_PCH_CPT(dev)) {
1853                 /* Workaround: Set the timing override bit before enabling the
1854                  * pch transcoder. */
1855                 reg = TRANS_CHICKEN2(pipe);
1856                 val = I915_READ(reg);
1857                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1858                 I915_WRITE(reg, val);
1859         }
1860
1861         reg = PCH_TRANSCONF(pipe);
1862         val = I915_READ(reg);
1863         pipeconf_val = I915_READ(PIPECONF(pipe));
1864
1865         if (HAS_PCH_IBX(dev_priv->dev)) {
1866                 /*
1867                  * Make the BPC in transcoder be consistent with
1868                  * that in pipeconf reg. For HDMI we must use 8bpc
1869                  * here for both 8bpc and 12bpc.
1870                  */
1871                 val &= ~PIPECONF_BPC_MASK;
1872                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
1873                         val |= PIPECONF_8BPC;
1874                 else
1875                         val |= pipeconf_val & PIPECONF_BPC_MASK;
1876         }
1877
1878         val &= ~TRANS_INTERLACE_MASK;
1879         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1880                 if (HAS_PCH_IBX(dev_priv->dev) &&
1881                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1882                         val |= TRANS_LEGACY_INTERLACED_ILK;
1883                 else
1884                         val |= TRANS_INTERLACED;
1885         else
1886                 val |= TRANS_PROGRESSIVE;
1887
1888         I915_WRITE(reg, val | TRANS_ENABLE);
1889         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1890                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1891 }
1892
1893 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1894                                       enum transcoder cpu_transcoder)
1895 {
1896         u32 val, pipeconf_val;
1897
1898         /* PCH only available on ILK+ */
1899         BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
1900
1901         /* FDI must be feeding us bits for PCH ports */
1902         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1903         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1904
1905         /* Workaround: set timing override bit. */
1906         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1907         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1908         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1909
1910         val = TRANS_ENABLE;
1911         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1912
1913         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1914             PIPECONF_INTERLACED_ILK)
1915                 val |= TRANS_INTERLACED;
1916         else
1917                 val |= TRANS_PROGRESSIVE;
1918
1919         I915_WRITE(LPT_TRANSCONF, val);
1920         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1921                 DRM_ERROR("Failed to enable PCH transcoder\n");
1922 }
1923
1924 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1925                                             enum pipe pipe)
1926 {
1927         struct drm_device *dev = dev_priv->dev;
1928         i915_reg_t reg;
1929         uint32_t val;
1930
1931         /* FDI relies on the transcoder */
1932         assert_fdi_tx_disabled(dev_priv, pipe);
1933         assert_fdi_rx_disabled(dev_priv, pipe);
1934
1935         /* Ports must be off as well */
1936         assert_pch_ports_disabled(dev_priv, pipe);
1937
1938         reg = PCH_TRANSCONF(pipe);
1939         val = I915_READ(reg);
1940         val &= ~TRANS_ENABLE;
1941         I915_WRITE(reg, val);
1942         /* wait for PCH transcoder off, transcoder state */
1943         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1944                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1945
1946         if (HAS_PCH_CPT(dev)) {
1947                 /* Workaround: Clear the timing override chicken bit again. */
1948                 reg = TRANS_CHICKEN2(pipe);
1949                 val = I915_READ(reg);
1950                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1951                 I915_WRITE(reg, val);
1952         }
1953 }
1954
1955 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1956 {
1957         u32 val;
1958
1959         val = I915_READ(LPT_TRANSCONF);
1960         val &= ~TRANS_ENABLE;
1961         I915_WRITE(LPT_TRANSCONF, val);
1962         /* wait for PCH transcoder off, transcoder state */
1963         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1964                 DRM_ERROR("Failed to disable PCH transcoder\n");
1965
1966         /* Workaround: clear timing override bit. */
1967         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1968         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1969         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1970 }
1971
1972 /**
1973  * intel_enable_pipe - enable a pipe, asserting requirements
1974  * @crtc: crtc responsible for the pipe
1975  *
1976  * Enable @crtc's pipe, making sure that various hardware specific requirements
1977  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1978  */
1979 static void intel_enable_pipe(struct intel_crtc *crtc)
1980 {
1981         struct drm_device *dev = crtc->base.dev;
1982         struct drm_i915_private *dev_priv = dev->dev_private;
1983         enum pipe pipe = crtc->pipe;
1984         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1985         enum pipe pch_transcoder;
1986         i915_reg_t reg;
1987         u32 val;
1988
1989         DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1990
1991         assert_planes_disabled(dev_priv, pipe);
1992         assert_cursor_disabled(dev_priv, pipe);
1993         assert_sprites_disabled(dev_priv, pipe);
1994
1995         if (HAS_PCH_LPT(dev_priv->dev))
1996                 pch_transcoder = TRANSCODER_A;
1997         else
1998                 pch_transcoder = pipe;
1999
2000         /*
2001          * A pipe without a PLL won't actually be able to drive bits from
2002          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
2003          * need the check.
2004          */
2005         if (HAS_GMCH_DISPLAY(dev_priv->dev))
2006                 if (crtc->config->has_dsi_encoder)
2007                         assert_dsi_pll_enabled(dev_priv);
2008                 else
2009                         assert_pll_enabled(dev_priv, pipe);
2010         else {
2011                 if (crtc->config->has_pch_encoder) {
2012                         /* if driving the PCH, we need FDI enabled */
2013                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2014                         assert_fdi_tx_pll_enabled(dev_priv,
2015                                                   (enum pipe) cpu_transcoder);
2016                 }
2017                 /* FIXME: assert CPU port conditions for SNB+ */
2018         }
2019
2020         reg = PIPECONF(cpu_transcoder);
2021         val = I915_READ(reg);
2022         if (val & PIPECONF_ENABLE) {
2023                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2024                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2025                 return;
2026         }
2027
2028         I915_WRITE(reg, val | PIPECONF_ENABLE);
2029         POSTING_READ(reg);
2030
2031         /*
2032          * Until the pipe starts DSL will read as 0, which would cause
2033          * an apparent vblank timestamp jump, which messes up also the
2034          * frame count when it's derived from the timestamps. So let's
2035          * wait for the pipe to start properly before we call
2036          * drm_crtc_vblank_on()
2037          */
2038         if (dev->max_vblank_count == 0 &&
2039             wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
2040                 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
2041 }
2042
2043 /**
2044  * intel_disable_pipe - disable a pipe, asserting requirements
2045  * @crtc: crtc whose pipes is to be disabled
2046  *
2047  * Disable the pipe of @crtc, making sure that various hardware
2048  * specific requirements are met, if applicable, e.g. plane
2049  * disabled, panel fitter off, etc.
2050  *
2051  * Will wait until the pipe has shut down before returning.
2052  */
2053 static void intel_disable_pipe(struct intel_crtc *crtc)
2054 {
2055         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2056         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2057         enum pipe pipe = crtc->pipe;
2058         i915_reg_t reg;
2059         u32 val;
2060
2061         DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2062
2063         /*
2064          * Make sure planes won't keep trying to pump pixels to us,
2065          * or we might hang the display.
2066          */
2067         assert_planes_disabled(dev_priv, pipe);
2068         assert_cursor_disabled(dev_priv, pipe);
2069         assert_sprites_disabled(dev_priv, pipe);
2070
2071         reg = PIPECONF(cpu_transcoder);
2072         val = I915_READ(reg);
2073         if ((val & PIPECONF_ENABLE) == 0)
2074                 return;
2075
2076         /*
2077          * Double wide has implications for planes
2078          * so best keep it disabled when not needed.
2079          */
2080         if (crtc->config->double_wide)
2081                 val &= ~PIPECONF_DOUBLE_WIDE;
2082
2083         /* Don't disable pipe or pipe PLLs if needed */
2084         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2085             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2086                 val &= ~PIPECONF_ENABLE;
2087
2088         I915_WRITE(reg, val);
2089         if ((val & PIPECONF_ENABLE) == 0)
2090                 intel_wait_for_pipe_off(crtc);
2091 }
2092
2093 static bool need_vtd_wa(struct drm_device *dev)
2094 {
2095 #ifdef CONFIG_INTEL_IOMMU
2096         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2097                 return true;
2098 #endif
2099         return false;
2100 }
2101
2102 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
2103 {
2104         return IS_GEN2(dev_priv) ? 2048 : 4096;
2105 }
2106
2107 static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv,
2108                                            uint64_t fb_modifier, unsigned int cpp)
2109 {
2110         switch (fb_modifier) {
2111         case DRM_FORMAT_MOD_NONE:
2112                 return cpp;
2113         case I915_FORMAT_MOD_X_TILED:
2114                 if (IS_GEN2(dev_priv))
2115                         return 128;
2116                 else
2117                         return 512;
2118         case I915_FORMAT_MOD_Y_TILED:
2119                 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2120                         return 128;
2121                 else
2122                         return 512;
2123         case I915_FORMAT_MOD_Yf_TILED:
2124                 switch (cpp) {
2125                 case 1:
2126                         return 64;
2127                 case 2:
2128                 case 4:
2129                         return 128;
2130                 case 8:
2131                 case 16:
2132                         return 256;
2133                 default:
2134                         MISSING_CASE(cpp);
2135                         return cpp;
2136                 }
2137                 break;
2138         default:
2139                 MISSING_CASE(fb_modifier);
2140                 return cpp;
2141         }
2142 }
2143
2144 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
2145                                uint64_t fb_modifier, unsigned int cpp)
2146 {
2147         if (fb_modifier == DRM_FORMAT_MOD_NONE)
2148                 return 1;
2149         else
2150                 return intel_tile_size(dev_priv) /
2151                         intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2152 }
2153
2154 /* Return the tile dimensions in pixel units */
2155 static void intel_tile_dims(const struct drm_i915_private *dev_priv,
2156                             unsigned int *tile_width,
2157                             unsigned int *tile_height,
2158                             uint64_t fb_modifier,
2159                             unsigned int cpp)
2160 {
2161         unsigned int tile_width_bytes =
2162                 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2163
2164         *tile_width = tile_width_bytes / cpp;
2165         *tile_height = intel_tile_size(dev_priv) / tile_width_bytes;
2166 }
2167
2168 unsigned int
2169 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2170                       uint32_t pixel_format, uint64_t fb_modifier)
2171 {
2172         unsigned int cpp = drm_format_plane_cpp(pixel_format, 0);
2173         unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp);
2174
2175         return ALIGN(height, tile_height);
2176 }
2177
2178 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2179 {
2180         unsigned int size = 0;
2181         int i;
2182
2183         for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2184                 size += rot_info->plane[i].width * rot_info->plane[i].height;
2185
2186         return size;
2187 }
2188
2189 static void
2190 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2191                         const struct drm_framebuffer *fb,
2192                         unsigned int rotation)
2193 {
2194         if (intel_rotation_90_or_270(rotation)) {
2195                 *view = i915_ggtt_view_rotated;
2196                 view->params.rotated = to_intel_framebuffer(fb)->rot_info;
2197         } else {
2198                 *view = i915_ggtt_view_normal;
2199         }
2200 }
2201
2202 static void
2203 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2204                    struct drm_framebuffer *fb)
2205 {
2206         struct intel_rotation_info *info = &to_intel_framebuffer(fb)->rot_info;
2207         unsigned int tile_size, tile_width, tile_height, cpp;
2208
2209         tile_size = intel_tile_size(dev_priv);
2210
2211         cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2212         intel_tile_dims(dev_priv, &tile_width, &tile_height,
2213                         fb->modifier[0], cpp);
2214
2215         info->plane[0].width = DIV_ROUND_UP(fb->pitches[0], tile_width * cpp);
2216         info->plane[0].height = DIV_ROUND_UP(fb->height, tile_height);
2217
2218         if (info->pixel_format == DRM_FORMAT_NV12) {
2219                 cpp = drm_format_plane_cpp(fb->pixel_format, 1);
2220                 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2221                                 fb->modifier[1], cpp);
2222
2223                 info->uv_offset = fb->offsets[1];
2224                 info->plane[1].width = DIV_ROUND_UP(fb->pitches[1], tile_width * cpp);
2225                 info->plane[1].height = DIV_ROUND_UP(fb->height / 2, tile_height);
2226         }
2227 }
2228
2229 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2230 {
2231         if (INTEL_INFO(dev_priv)->gen >= 9)
2232                 return 256 * 1024;
2233         else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2234                  IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2235                 return 128 * 1024;
2236         else if (INTEL_INFO(dev_priv)->gen >= 4)
2237                 return 4 * 1024;
2238         else
2239                 return 0;
2240 }
2241
2242 static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv,
2243                                          uint64_t fb_modifier)
2244 {
2245         switch (fb_modifier) {
2246         case DRM_FORMAT_MOD_NONE:
2247                 return intel_linear_alignment(dev_priv);
2248         case I915_FORMAT_MOD_X_TILED:
2249                 if (INTEL_INFO(dev_priv)->gen >= 9)
2250                         return 256 * 1024;
2251                 return 0;
2252         case I915_FORMAT_MOD_Y_TILED:
2253         case I915_FORMAT_MOD_Yf_TILED:
2254                 return 1 * 1024 * 1024;
2255         default:
2256                 MISSING_CASE(fb_modifier);
2257                 return 0;
2258         }
2259 }
2260
2261 int
2262 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
2263                            unsigned int rotation)
2264 {
2265         struct drm_device *dev = fb->dev;
2266         struct drm_i915_private *dev_priv = dev->dev_private;
2267         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2268         struct i915_ggtt_view view;
2269         u32 alignment;
2270         int ret;
2271
2272         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2273
2274         alignment = intel_surf_alignment(dev_priv, fb->modifier[0]);
2275
2276         intel_fill_fb_ggtt_view(&view, fb, rotation);
2277
2278         /* Note that the w/a also requires 64 PTE of padding following the
2279          * bo. We currently fill all unused PTE with the shadow page and so
2280          * we should always have valid PTE following the scanout preventing
2281          * the VT-d warning.
2282          */
2283         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2284                 alignment = 256 * 1024;
2285
2286         /*
2287          * Global gtt pte registers are special registers which actually forward
2288          * writes to a chunk of system memory. Which means that there is no risk
2289          * that the register values disappear as soon as we call
2290          * intel_runtime_pm_put(), so it is correct to wrap only the
2291          * pin/unpin/fence and not more.
2292          */
2293         intel_runtime_pm_get(dev_priv);
2294
2295         ret = i915_gem_object_pin_to_display_plane(obj, alignment,
2296                                                    &view);
2297         if (ret)
2298                 goto err_pm;
2299
2300         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2301          * fence, whereas 965+ only requires a fence if using
2302          * framebuffer compression.  For simplicity, we always install
2303          * a fence as the cost is not that onerous.
2304          */
2305         if (view.type == I915_GGTT_VIEW_NORMAL) {
2306                 ret = i915_gem_object_get_fence(obj);
2307                 if (ret == -EDEADLK) {
2308                         /*
2309                          * -EDEADLK means there are no free fences
2310                          * no pending flips.
2311                          *
2312                          * This is propagated to atomic, but it uses
2313                          * -EDEADLK to force a locking recovery, so
2314                          * change the returned error to -EBUSY.
2315                          */
2316                         ret = -EBUSY;
2317                         goto err_unpin;
2318                 } else if (ret)
2319                         goto err_unpin;
2320
2321                 i915_gem_object_pin_fence(obj);
2322         }
2323
2324         intel_runtime_pm_put(dev_priv);
2325         return 0;
2326
2327 err_unpin:
2328         i915_gem_object_unpin_from_display_plane(obj, &view);
2329 err_pm:
2330         intel_runtime_pm_put(dev_priv);
2331         return ret;
2332 }
2333
2334 static void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2335 {
2336         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2337         struct i915_ggtt_view view;
2338
2339         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2340
2341         intel_fill_fb_ggtt_view(&view, fb, rotation);
2342
2343         if (view.type == I915_GGTT_VIEW_NORMAL)
2344                 i915_gem_object_unpin_fence(obj);
2345
2346         i915_gem_object_unpin_from_display_plane(obj, &view);
2347 }
2348
2349 /*
2350  * Adjust the tile offset by moving the difference into
2351  * the x/y offsets.
2352  *
2353  * Input tile dimensions and pitch must already be
2354  * rotated to match x and y, and in pixel units.
2355  */
2356 static u32 intel_adjust_tile_offset(int *x, int *y,
2357                                     unsigned int tile_width,
2358                                     unsigned int tile_height,
2359                                     unsigned int tile_size,
2360                                     unsigned int pitch_tiles,
2361                                     u32 old_offset,
2362                                     u32 new_offset)
2363 {
2364         unsigned int tiles;
2365
2366         WARN_ON(old_offset & (tile_size - 1));
2367         WARN_ON(new_offset & (tile_size - 1));
2368         WARN_ON(new_offset > old_offset);
2369
2370         tiles = (old_offset - new_offset) / tile_size;
2371
2372         *y += tiles / pitch_tiles * tile_height;
2373         *x += tiles % pitch_tiles * tile_width;
2374
2375         return new_offset;
2376 }
2377
2378 /*
2379  * Computes the linear offset to the base tile and adjusts
2380  * x, y. bytes per pixel is assumed to be a power-of-two.
2381  *
2382  * In the 90/270 rotated case, x and y are assumed
2383  * to be already rotated to match the rotated GTT view, and
2384  * pitch is the tile_height aligned framebuffer height.
2385  */
2386 u32 intel_compute_tile_offset(int *x, int *y,
2387                               const struct drm_framebuffer *fb, int plane,
2388                               unsigned int pitch,
2389                               unsigned int rotation)
2390 {
2391         const struct drm_i915_private *dev_priv = to_i915(fb->dev);
2392         uint64_t fb_modifier = fb->modifier[plane];
2393         unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2394         u32 offset, offset_aligned, alignment;
2395
2396         alignment = intel_surf_alignment(dev_priv, fb_modifier);
2397         if (alignment)
2398                 alignment--;
2399
2400         if (fb_modifier != DRM_FORMAT_MOD_NONE) {
2401                 unsigned int tile_size, tile_width, tile_height;
2402                 unsigned int tile_rows, tiles, pitch_tiles;
2403
2404                 tile_size = intel_tile_size(dev_priv);
2405                 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2406                                 fb_modifier, cpp);
2407
2408                 if (intel_rotation_90_or_270(rotation)) {
2409                         pitch_tiles = pitch / tile_height;
2410                         swap(tile_width, tile_height);
2411                 } else {
2412                         pitch_tiles = pitch / (tile_width * cpp);
2413                 }
2414
2415                 tile_rows = *y / tile_height;
2416                 *y %= tile_height;
2417
2418                 tiles = *x / tile_width;
2419                 *x %= tile_width;
2420
2421                 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2422                 offset_aligned = offset & ~alignment;
2423
2424                 intel_adjust_tile_offset(x, y, tile_width, tile_height,
2425                                          tile_size, pitch_tiles,
2426                                          offset, offset_aligned);
2427         } else {
2428                 offset = *y * pitch + *x * cpp;
2429                 offset_aligned = offset & ~alignment;
2430
2431                 *y = (offset & alignment) / pitch;
2432                 *x = ((offset & alignment) - *y * pitch) / cpp;
2433         }
2434
2435         return offset_aligned;
2436 }
2437
2438 static int i9xx_format_to_fourcc(int format)
2439 {
2440         switch (format) {
2441         case DISPPLANE_8BPP:
2442                 return DRM_FORMAT_C8;
2443         case DISPPLANE_BGRX555:
2444                 return DRM_FORMAT_XRGB1555;
2445         case DISPPLANE_BGRX565:
2446                 return DRM_FORMAT_RGB565;
2447         default:
2448         case DISPPLANE_BGRX888:
2449                 return DRM_FORMAT_XRGB8888;
2450         case DISPPLANE_RGBX888:
2451                 return DRM_FORMAT_XBGR8888;
2452         case DISPPLANE_BGRX101010:
2453                 return DRM_FORMAT_XRGB2101010;
2454         case DISPPLANE_RGBX101010:
2455                 return DRM_FORMAT_XBGR2101010;
2456         }
2457 }
2458
2459 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2460 {
2461         switch (format) {
2462         case PLANE_CTL_FORMAT_RGB_565:
2463                 return DRM_FORMAT_RGB565;
2464         default:
2465         case PLANE_CTL_FORMAT_XRGB_8888:
2466                 if (rgb_order) {
2467                         if (alpha)
2468                                 return DRM_FORMAT_ABGR8888;
2469                         else
2470                                 return DRM_FORMAT_XBGR8888;
2471                 } else {
2472                         if (alpha)
2473                                 return DRM_FORMAT_ARGB8888;
2474                         else
2475                                 return DRM_FORMAT_XRGB8888;
2476                 }
2477         case PLANE_CTL_FORMAT_XRGB_2101010:
2478                 if (rgb_order)
2479                         return DRM_FORMAT_XBGR2101010;
2480                 else
2481                         return DRM_FORMAT_XRGB2101010;
2482         }
2483 }
2484
2485 static bool
2486 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2487                               struct intel_initial_plane_config *plane_config)
2488 {
2489         struct drm_device *dev = crtc->base.dev;
2490         struct drm_i915_private *dev_priv = to_i915(dev);
2491         struct drm_i915_gem_object *obj = NULL;
2492         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2493         struct drm_framebuffer *fb = &plane_config->fb->base;
2494         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2495         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2496                                     PAGE_SIZE);
2497
2498         size_aligned -= base_aligned;
2499
2500         if (plane_config->size == 0)
2501                 return false;
2502
2503         /* If the FB is too big, just don't use it since fbdev is not very
2504          * important and we should probably use that space with FBC or other
2505          * features. */
2506         if (size_aligned * 2 > dev_priv->gtt.stolen_usable_size)
2507                 return false;
2508
2509         mutex_lock(&dev->struct_mutex);
2510
2511         obj = i915_gem_object_create_stolen_for_preallocated(dev,
2512                                                              base_aligned,
2513                                                              base_aligned,
2514                                                              size_aligned);
2515         if (!obj) {
2516                 mutex_unlock(&dev->struct_mutex);
2517                 return false;
2518         }
2519
2520         obj->tiling_mode = plane_config->tiling;
2521         if (obj->tiling_mode == I915_TILING_X)
2522                 obj->stride = fb->pitches[0];
2523
2524         mode_cmd.pixel_format = fb->pixel_format;
2525         mode_cmd.width = fb->width;
2526         mode_cmd.height = fb->height;
2527         mode_cmd.pitches[0] = fb->pitches[0];
2528         mode_cmd.modifier[0] = fb->modifier[0];
2529         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2530
2531         if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2532                                    &mode_cmd, obj)) {
2533                 DRM_DEBUG_KMS("intel fb init failed\n");
2534                 goto out_unref_obj;
2535         }
2536
2537         mutex_unlock(&dev->struct_mutex);
2538
2539         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2540         return true;
2541
2542 out_unref_obj:
2543         drm_gem_object_unreference(&obj->base);
2544         mutex_unlock(&dev->struct_mutex);
2545         return false;
2546 }
2547
2548 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2549 static void
2550 update_state_fb(struct drm_plane *plane)
2551 {
2552         if (plane->fb == plane->state->fb)
2553                 return;
2554
2555         if (plane->state->fb)
2556                 drm_framebuffer_unreference(plane->state->fb);
2557         plane->state->fb = plane->fb;
2558         if (plane->state->fb)
2559                 drm_framebuffer_reference(plane->state->fb);
2560 }
2561
2562 static void
2563 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2564                              struct intel_initial_plane_config *plane_config)
2565 {
2566         struct drm_device *dev = intel_crtc->base.dev;
2567         struct drm_i915_private *dev_priv = dev->dev_private;
2568         struct drm_crtc *c;
2569         struct intel_crtc *i;
2570         struct drm_i915_gem_object *obj;
2571         struct drm_plane *primary = intel_crtc->base.primary;
2572         struct drm_plane_state *plane_state = primary->state;
2573         struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2574         struct intel_plane *intel_plane = to_intel_plane(primary);
2575         struct intel_plane_state *intel_state =
2576                 to_intel_plane_state(plane_state);
2577         struct drm_framebuffer *fb;
2578
2579         if (!plane_config->fb)
2580                 return;
2581
2582         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2583                 fb = &plane_config->fb->base;
2584                 goto valid_fb;
2585         }
2586
2587         kfree(plane_config->fb);
2588
2589         /*
2590          * Failed to alloc the obj, check to see if we should share
2591          * an fb with another CRTC instead
2592          */
2593         for_each_crtc(dev, c) {
2594                 i = to_intel_crtc(c);
2595
2596                 if (c == &intel_crtc->base)
2597                         continue;
2598
2599                 if (!i->active)
2600                         continue;
2601
2602                 fb = c->primary->fb;
2603                 if (!fb)
2604                         continue;
2605
2606                 obj = intel_fb_obj(fb);
2607                 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2608                         drm_framebuffer_reference(fb);
2609                         goto valid_fb;
2610                 }
2611         }
2612
2613         /*
2614          * We've failed to reconstruct the BIOS FB.  Current display state
2615          * indicates that the primary plane is visible, but has a NULL FB,
2616          * which will lead to problems later if we don't fix it up.  The
2617          * simplest solution is to just disable the primary plane now and
2618          * pretend the BIOS never had it enabled.
2619          */
2620         to_intel_plane_state(plane_state)->visible = false;
2621         crtc_state->plane_mask &= ~(1 << drm_plane_index(primary));
2622         intel_pre_disable_primary(&intel_crtc->base);
2623         intel_plane->disable_plane(primary, &intel_crtc->base);
2624
2625         return;
2626
2627 valid_fb:
2628         plane_state->src_x = 0;
2629         plane_state->src_y = 0;
2630         plane_state->src_w = fb->width << 16;
2631         plane_state->src_h = fb->height << 16;
2632
2633         plane_state->crtc_x = 0;
2634         plane_state->crtc_y = 0;
2635         plane_state->crtc_w = fb->width;
2636         plane_state->crtc_h = fb->height;
2637
2638         intel_state->src.x1 = plane_state->src_x;
2639         intel_state->src.y1 = plane_state->src_y;
2640         intel_state->src.x2 = plane_state->src_x + plane_state->src_w;
2641         intel_state->src.y2 = plane_state->src_y + plane_state->src_h;
2642         intel_state->dst.x1 = plane_state->crtc_x;
2643         intel_state->dst.y1 = plane_state->crtc_y;
2644         intel_state->dst.x2 = plane_state->crtc_x + plane_state->crtc_w;
2645         intel_state->dst.y2 = plane_state->crtc_y + plane_state->crtc_h;
2646
2647         obj = intel_fb_obj(fb);
2648         if (obj->tiling_mode != I915_TILING_NONE)
2649                 dev_priv->preserve_bios_swizzle = true;
2650
2651         drm_framebuffer_reference(fb);
2652         primary->fb = primary->state->fb = fb;
2653         primary->crtc = primary->state->crtc = &intel_crtc->base;
2654         intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2655         obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2656 }
2657
2658 static void i9xx_update_primary_plane(struct drm_plane *primary,
2659                                       const struct intel_crtc_state *crtc_state,
2660                                       const struct intel_plane_state *plane_state)
2661 {
2662         struct drm_device *dev = primary->dev;
2663         struct drm_i915_private *dev_priv = dev->dev_private;
2664         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2665         struct drm_framebuffer *fb = plane_state->base.fb;
2666         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2667         int plane = intel_crtc->plane;
2668         u32 linear_offset;
2669         u32 dspcntr;
2670         i915_reg_t reg = DSPCNTR(plane);
2671         unsigned int rotation = plane_state->base.rotation;
2672         int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2673         int x = plane_state->src.x1 >> 16;
2674         int y = plane_state->src.y1 >> 16;
2675
2676         dspcntr = DISPPLANE_GAMMA_ENABLE;
2677
2678         dspcntr |= DISPLAY_PLANE_ENABLE;
2679
2680         if (INTEL_INFO(dev)->gen < 4) {
2681                 if (intel_crtc->pipe == PIPE_B)
2682                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2683
2684                 /* pipesrc and dspsize control the size that is scaled from,
2685                  * which should always be the user's requested size.
2686                  */
2687                 I915_WRITE(DSPSIZE(plane),
2688                            ((crtc_state->pipe_src_h - 1) << 16) |
2689                            (crtc_state->pipe_src_w - 1));
2690                 I915_WRITE(DSPPOS(plane), 0);
2691         } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2692                 I915_WRITE(PRIMSIZE(plane),
2693                            ((crtc_state->pipe_src_h - 1) << 16) |
2694                            (crtc_state->pipe_src_w - 1));
2695                 I915_WRITE(PRIMPOS(plane), 0);
2696                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2697         }
2698
2699         switch (fb->pixel_format) {
2700         case DRM_FORMAT_C8:
2701                 dspcntr |= DISPPLANE_8BPP;
2702                 break;
2703         case DRM_FORMAT_XRGB1555:
2704                 dspcntr |= DISPPLANE_BGRX555;
2705                 break;
2706         case DRM_FORMAT_RGB565:
2707                 dspcntr |= DISPPLANE_BGRX565;
2708                 break;
2709         case DRM_FORMAT_XRGB8888:
2710                 dspcntr |= DISPPLANE_BGRX888;
2711                 break;
2712         case DRM_FORMAT_XBGR8888:
2713                 dspcntr |= DISPPLANE_RGBX888;
2714                 break;
2715         case DRM_FORMAT_XRGB2101010:
2716                 dspcntr |= DISPPLANE_BGRX101010;
2717                 break;
2718         case DRM_FORMAT_XBGR2101010:
2719                 dspcntr |= DISPPLANE_RGBX101010;
2720                 break;
2721         default:
2722                 BUG();
2723         }
2724
2725         if (INTEL_INFO(dev)->gen >= 4 &&
2726             obj->tiling_mode != I915_TILING_NONE)
2727                 dspcntr |= DISPPLANE_TILED;
2728
2729         if (IS_G4X(dev))
2730                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2731
2732         linear_offset = y * fb->pitches[0] + x * cpp;
2733
2734         if (INTEL_INFO(dev)->gen >= 4) {
2735                 intel_crtc->dspaddr_offset =
2736                         intel_compute_tile_offset(&x, &y, fb, 0,
2737                                                   fb->pitches[0], rotation);
2738                 linear_offset -= intel_crtc->dspaddr_offset;
2739         } else {
2740                 intel_crtc->dspaddr_offset = linear_offset;
2741         }
2742
2743         if (rotation == BIT(DRM_ROTATE_180)) {
2744                 dspcntr |= DISPPLANE_ROTATE_180;
2745
2746                 x += (crtc_state->pipe_src_w - 1);
2747                 y += (crtc_state->pipe_src_h - 1);
2748
2749                 /* Finding the last pixel of the last line of the display
2750                 data and adding to linear_offset*/
2751                 linear_offset +=
2752                         (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
2753                         (crtc_state->pipe_src_w - 1) * cpp;
2754         }
2755
2756         intel_crtc->adjusted_x = x;
2757         intel_crtc->adjusted_y = y;
2758
2759         I915_WRITE(reg, dspcntr);
2760
2761         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2762         if (INTEL_INFO(dev)->gen >= 4) {
2763                 I915_WRITE(DSPSURF(plane),
2764                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2765                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2766                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2767         } else
2768                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2769         POSTING_READ(reg);
2770 }
2771
2772 static void i9xx_disable_primary_plane(struct drm_plane *primary,
2773                                        struct drm_crtc *crtc)
2774 {
2775         struct drm_device *dev = crtc->dev;
2776         struct drm_i915_private *dev_priv = dev->dev_private;
2777         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2778         int plane = intel_crtc->plane;
2779
2780         I915_WRITE(DSPCNTR(plane), 0);
2781         if (INTEL_INFO(dev_priv)->gen >= 4)
2782                 I915_WRITE(DSPSURF(plane), 0);
2783         else
2784                 I915_WRITE(DSPADDR(plane), 0);
2785         POSTING_READ(DSPCNTR(plane));
2786 }
2787
2788 static void ironlake_update_primary_plane(struct drm_plane *primary,
2789                                           const struct intel_crtc_state *crtc_state,
2790                                           const struct intel_plane_state *plane_state)
2791 {
2792         struct drm_device *dev = primary->dev;
2793         struct drm_i915_private *dev_priv = dev->dev_private;
2794         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2795         struct drm_framebuffer *fb = plane_state->base.fb;
2796         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2797         int plane = intel_crtc->plane;
2798         u32 linear_offset;
2799         u32 dspcntr;
2800         i915_reg_t reg = DSPCNTR(plane);
2801         unsigned int rotation = plane_state->base.rotation;
2802         int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2803         int x = plane_state->src.x1 >> 16;
2804         int y = plane_state->src.y1 >> 16;
2805
2806         dspcntr = DISPPLANE_GAMMA_ENABLE;
2807         dspcntr |= DISPLAY_PLANE_ENABLE;
2808
2809         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2810                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2811
2812         switch (fb->pixel_format) {
2813         case DRM_FORMAT_C8:
2814                 dspcntr |= DISPPLANE_8BPP;
2815                 break;
2816         case DRM_FORMAT_RGB565:
2817                 dspcntr |= DISPPLANE_BGRX565;
2818                 break;
2819         case DRM_FORMAT_XRGB8888:
2820                 dspcntr |= DISPPLANE_BGRX888;
2821                 break;
2822         case DRM_FORMAT_XBGR8888:
2823                 dspcntr |= DISPPLANE_RGBX888;
2824                 break;
2825         case DRM_FORMAT_XRGB2101010:
2826                 dspcntr |= DISPPLANE_BGRX101010;
2827                 break;
2828         case DRM_FORMAT_XBGR2101010:
2829                 dspcntr |= DISPPLANE_RGBX101010;
2830                 break;
2831         default:
2832                 BUG();
2833         }
2834
2835         if (obj->tiling_mode != I915_TILING_NONE)
2836                 dspcntr |= DISPPLANE_TILED;
2837
2838         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2839                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2840
2841         linear_offset = y * fb->pitches[0] + x * cpp;
2842         intel_crtc->dspaddr_offset =
2843                 intel_compute_tile_offset(&x, &y, fb, 0,
2844                                           fb->pitches[0], rotation);
2845         linear_offset -= intel_crtc->dspaddr_offset;
2846         if (rotation == BIT(DRM_ROTATE_180)) {
2847                 dspcntr |= DISPPLANE_ROTATE_180;
2848
2849                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2850                         x += (crtc_state->pipe_src_w - 1);
2851                         y += (crtc_state->pipe_src_h - 1);
2852
2853                         /* Finding the last pixel of the last line of the display
2854                         data and adding to linear_offset*/
2855                         linear_offset +=
2856                                 (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
2857                                 (crtc_state->pipe_src_w - 1) * cpp;
2858                 }
2859         }
2860
2861         intel_crtc->adjusted_x = x;
2862         intel_crtc->adjusted_y = y;
2863
2864         I915_WRITE(reg, dspcntr);
2865
2866         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2867         I915_WRITE(DSPSURF(plane),
2868                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2869         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2870                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2871         } else {
2872                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2873                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2874         }
2875         POSTING_READ(reg);
2876 }
2877
2878 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
2879                               uint64_t fb_modifier, uint32_t pixel_format)
2880 {
2881         if (fb_modifier == DRM_FORMAT_MOD_NONE) {
2882                 return 64;
2883         } else {
2884                 int cpp = drm_format_plane_cpp(pixel_format, 0);
2885
2886                 return intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2887         }
2888 }
2889
2890 u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
2891                            struct drm_i915_gem_object *obj,
2892                            unsigned int plane)
2893 {
2894         struct i915_ggtt_view view;
2895         struct i915_vma *vma;
2896         u64 offset;
2897
2898         intel_fill_fb_ggtt_view(&view, intel_plane->base.state->fb,
2899                                 intel_plane->base.state->rotation);
2900
2901         vma = i915_gem_obj_to_ggtt_view(obj, &view);
2902         if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
2903                 view.type))
2904                 return -1;
2905
2906         offset = vma->node.start;
2907
2908         if (plane == 1) {
2909                 offset += vma->ggtt_view.params.rotated.uv_start_page *
2910                           PAGE_SIZE;
2911         }
2912
2913         WARN_ON(upper_32_bits(offset));
2914
2915         return lower_32_bits(offset);
2916 }
2917
2918 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2919 {
2920         struct drm_device *dev = intel_crtc->base.dev;
2921         struct drm_i915_private *dev_priv = dev->dev_private;
2922
2923         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2924         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2925         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
2926 }
2927
2928 /*
2929  * This function detaches (aka. unbinds) unused scalers in hardware
2930  */
2931 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2932 {
2933         struct intel_crtc_scaler_state *scaler_state;
2934         int i;
2935
2936         scaler_state = &intel_crtc->config->scaler_state;
2937
2938         /* loop through and disable scalers that aren't in use */
2939         for (i = 0; i < intel_crtc->num_scalers; i++) {
2940                 if (!scaler_state->scalers[i].in_use)
2941                         skl_detach_scaler(intel_crtc, i);
2942         }
2943 }
2944
2945 u32 skl_plane_ctl_format(uint32_t pixel_format)
2946 {
2947         switch (pixel_format) {
2948         case DRM_FORMAT_C8:
2949                 return PLANE_CTL_FORMAT_INDEXED;
2950         case DRM_FORMAT_RGB565:
2951                 return PLANE_CTL_FORMAT_RGB_565;
2952         case DRM_FORMAT_XBGR8888:
2953                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2954         case DRM_FORMAT_XRGB8888:
2955                 return PLANE_CTL_FORMAT_XRGB_8888;
2956         /*
2957          * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2958          * to be already pre-multiplied. We need to add a knob (or a different
2959          * DRM_FORMAT) for user-space to configure that.
2960          */
2961         case DRM_FORMAT_ABGR8888:
2962                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2963                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2964         case DRM_FORMAT_ARGB8888:
2965                 return PLANE_CTL_FORMAT_XRGB_8888 |
2966                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2967         case DRM_FORMAT_XRGB2101010:
2968                 return PLANE_CTL_FORMAT_XRGB_2101010;
2969         case DRM_FORMAT_XBGR2101010:
2970                 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
2971         case DRM_FORMAT_YUYV:
2972                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
2973         case DRM_FORMAT_YVYU:
2974                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
2975         case DRM_FORMAT_UYVY:
2976                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
2977         case DRM_FORMAT_VYUY:
2978                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
2979         default:
2980                 MISSING_CASE(pixel_format);
2981         }
2982
2983         return 0;
2984 }
2985
2986 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2987 {
2988         switch (fb_modifier) {
2989         case DRM_FORMAT_MOD_NONE:
2990                 break;
2991         case I915_FORMAT_MOD_X_TILED:
2992                 return PLANE_CTL_TILED_X;
2993         case I915_FORMAT_MOD_Y_TILED:
2994                 return PLANE_CTL_TILED_Y;
2995         case I915_FORMAT_MOD_Yf_TILED:
2996                 return PLANE_CTL_TILED_YF;
2997         default:
2998                 MISSING_CASE(fb_modifier);
2999         }
3000
3001         return 0;
3002 }
3003
3004 u32 skl_plane_ctl_rotation(unsigned int rotation)
3005 {
3006         switch (rotation) {
3007         case BIT(DRM_ROTATE_0):
3008                 break;
3009         /*
3010          * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3011          * while i915 HW rotation is clockwise, thats why this swapping.
3012          */
3013         case BIT(DRM_ROTATE_90):
3014                 return PLANE_CTL_ROTATE_270;
3015         case BIT(DRM_ROTATE_180):
3016                 return PLANE_CTL_ROTATE_180;
3017         case BIT(DRM_ROTATE_270):
3018                 return PLANE_CTL_ROTATE_90;
3019         default:
3020                 MISSING_CASE(rotation);
3021         }
3022
3023         return 0;
3024 }
3025
3026 static void skylake_update_primary_plane(struct drm_plane *plane,
3027                                          const struct intel_crtc_state *crtc_state,
3028                                          const struct intel_plane_state *plane_state)
3029 {
3030         struct drm_device *dev = plane->dev;
3031         struct drm_i915_private *dev_priv = dev->dev_private;
3032         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3033         struct drm_framebuffer *fb = plane_state->base.fb;
3034         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
3035         int pipe = intel_crtc->pipe;
3036         u32 plane_ctl, stride_div, stride;
3037         u32 tile_height, plane_offset, plane_size;
3038         unsigned int rotation = plane_state->base.rotation;
3039         int x_offset, y_offset;
3040         u32 surf_addr;
3041         int scaler_id = plane_state->scaler_id;
3042         int src_x = plane_state->src.x1 >> 16;
3043         int src_y = plane_state->src.y1 >> 16;
3044         int src_w = drm_rect_width(&plane_state->src) >> 16;
3045         int src_h = drm_rect_height(&plane_state->src) >> 16;
3046         int dst_x = plane_state->dst.x1;
3047         int dst_y = plane_state->dst.y1;
3048         int dst_w = drm_rect_width(&plane_state->dst);
3049         int dst_h = drm_rect_height(&plane_state->dst);
3050
3051         plane_ctl = PLANE_CTL_ENABLE |
3052                     PLANE_CTL_PIPE_GAMMA_ENABLE |
3053                     PLANE_CTL_PIPE_CSC_ENABLE;
3054
3055         plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3056         plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3057         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3058         plane_ctl |= skl_plane_ctl_rotation(rotation);
3059
3060         stride_div = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
3061                                                fb->pixel_format);
3062         surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
3063
3064         WARN_ON(drm_rect_width(&plane_state->src) == 0);
3065
3066         if (intel_rotation_90_or_270(rotation)) {
3067                 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
3068
3069                 /* stride = Surface height in tiles */
3070                 tile_height = intel_tile_height(dev_priv, fb->modifier[0], cpp);
3071                 stride = DIV_ROUND_UP(fb->height, tile_height);
3072                 x_offset = stride * tile_height - src_y - src_h;
3073                 y_offset = src_x;
3074                 plane_size = (src_w - 1) << 16 | (src_h - 1);
3075         } else {
3076                 stride = fb->pitches[0] / stride_div;
3077                 x_offset = src_x;
3078                 y_offset = src_y;
3079                 plane_size = (src_h - 1) << 16 | (src_w - 1);
3080         }
3081         plane_offset = y_offset << 16 | x_offset;
3082
3083         intel_crtc->adjusted_x = x_offset;
3084         intel_crtc->adjusted_y = y_offset;
3085
3086         I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3087         I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3088         I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3089         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3090
3091         if (scaler_id >= 0) {
3092                 uint32_t ps_ctrl = 0;
3093
3094                 WARN_ON(!dst_w || !dst_h);
3095                 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3096                         crtc_state->scaler_state.scalers[scaler_id].mode;
3097                 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3098                 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3099                 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3100                 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3101                 I915_WRITE(PLANE_POS(pipe, 0), 0);
3102         } else {
3103                 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3104         }
3105
3106         I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3107
3108         POSTING_READ(PLANE_SURF(pipe, 0));
3109 }
3110
3111 static void skylake_disable_primary_plane(struct drm_plane *primary,
3112                                           struct drm_crtc *crtc)
3113 {
3114         struct drm_device *dev = crtc->dev;
3115         struct drm_i915_private *dev_priv = dev->dev_private;
3116         int pipe = to_intel_crtc(crtc)->pipe;
3117
3118         I915_WRITE(PLANE_CTL(pipe, 0), 0);
3119         I915_WRITE(PLANE_SURF(pipe, 0), 0);
3120         POSTING_READ(PLANE_SURF(pipe, 0));
3121 }
3122
3123 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3124 static int
3125 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3126                            int x, int y, enum mode_set_atomic state)
3127 {
3128         /* Support for kgdboc is disabled, this needs a major rework. */
3129         DRM_ERROR("legacy panic handler not supported any more.\n");
3130
3131         return -ENODEV;
3132 }
3133
3134 static void intel_complete_page_flips(struct drm_device *dev)
3135 {
3136         struct drm_crtc *crtc;
3137
3138         for_each_crtc(dev, crtc) {
3139                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3140                 enum plane plane = intel_crtc->plane;
3141
3142                 intel_prepare_page_flip(dev, plane);
3143                 intel_finish_page_flip_plane(dev, plane);
3144         }
3145 }
3146
3147 static void intel_update_primary_planes(struct drm_device *dev)
3148 {
3149         struct drm_crtc *crtc;
3150
3151         for_each_crtc(dev, crtc) {
3152                 struct intel_plane *plane = to_intel_plane(crtc->primary);
3153                 struct intel_plane_state *plane_state;
3154
3155                 drm_modeset_lock_crtc(crtc, &plane->base);
3156                 plane_state = to_intel_plane_state(plane->base.state);
3157
3158                 if (plane_state->visible)
3159                         plane->update_plane(&plane->base,
3160                                             to_intel_crtc_state(crtc->state),
3161                                             plane_state);
3162
3163                 drm_modeset_unlock_crtc(crtc);
3164         }
3165 }
3166
3167 void intel_prepare_reset(struct drm_device *dev)
3168 {
3169         /* no reset support for gen2 */
3170         if (IS_GEN2(dev))
3171                 return;
3172
3173         /* reset doesn't touch the display */
3174         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3175                 return;
3176
3177         drm_modeset_lock_all(dev);
3178         /*
3179          * Disabling the crtcs gracefully seems nicer. Also the
3180          * g33 docs say we should at least disable all the planes.
3181          */
3182         intel_display_suspend(dev);
3183 }
3184
3185 void intel_finish_reset(struct drm_device *dev)
3186 {
3187         struct drm_i915_private *dev_priv = to_i915(dev);
3188
3189         /*
3190          * Flips in the rings will be nuked by the reset,
3191          * so complete all pending flips so that user space
3192          * will get its events and not get stuck.
3193          */
3194         intel_complete_page_flips(dev);
3195
3196         /* no reset support for gen2 */
3197         if (IS_GEN2(dev))
3198                 return;
3199
3200         /* reset doesn't touch the display */
3201         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3202                 /*
3203                  * Flips in the rings have been nuked by the reset,
3204                  * so update the base address of all primary
3205                  * planes to the the last fb to make sure we're
3206                  * showing the correct fb after a reset.
3207                  *
3208                  * FIXME: Atomic will make this obsolete since we won't schedule
3209                  * CS-based flips (which might get lost in gpu resets) any more.
3210                  */
3211                 intel_update_primary_planes(dev);
3212                 return;
3213         }
3214
3215         /*
3216          * The display has been reset as well,
3217          * so need a full re-initialization.
3218          */
3219         intel_runtime_pm_disable_interrupts(dev_priv);
3220         intel_runtime_pm_enable_interrupts(dev_priv);
3221
3222         intel_modeset_init_hw(dev);
3223
3224         spin_lock_irq(&dev_priv->irq_lock);
3225         if (dev_priv->display.hpd_irq_setup)
3226                 dev_priv->display.hpd_irq_setup(dev);
3227         spin_unlock_irq(&dev_priv->irq_lock);
3228
3229         intel_display_resume(dev);
3230
3231         intel_hpd_init(dev_priv);
3232
3233         drm_modeset_unlock_all(dev);
3234 }
3235
3236 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3237 {
3238         struct drm_device *dev = crtc->dev;
3239         struct drm_i915_private *dev_priv = dev->dev_private;
3240         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3241         bool pending;
3242
3243         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3244             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3245                 return false;
3246
3247         spin_lock_irq(&dev->event_lock);
3248         pending = to_intel_crtc(crtc)->unpin_work != NULL;
3249         spin_unlock_irq(&dev->event_lock);
3250
3251         return pending;
3252 }
3253
3254 static void intel_update_pipe_config(struct intel_crtc *crtc,
3255                                      struct intel_crtc_state *old_crtc_state)
3256 {
3257         struct drm_device *dev = crtc->base.dev;
3258         struct drm_i915_private *dev_priv = dev->dev_private;
3259         struct intel_crtc_state *pipe_config =
3260                 to_intel_crtc_state(crtc->base.state);
3261
3262         /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3263         crtc->base.mode = crtc->base.state->mode;
3264
3265         DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3266                       old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3267                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3268
3269         if (HAS_DDI(dev))
3270                 intel_set_pipe_csc(&crtc->base);
3271
3272         /*
3273          * Update pipe size and adjust fitter if needed: the reason for this is
3274          * that in compute_mode_changes we check the native mode (not the pfit
3275          * mode) to see if we can flip rather than do a full mode set. In the
3276          * fastboot case, we'll flip, but if we don't update the pipesrc and
3277          * pfit state, we'll end up with a big fb scanned out into the wrong
3278          * sized surface.
3279          */
3280
3281         I915_WRITE(PIPESRC(crtc->pipe),
3282                    ((pipe_config->pipe_src_w - 1) << 16) |
3283                    (pipe_config->pipe_src_h - 1));
3284
3285         /* on skylake this is done by detaching scalers */
3286         if (INTEL_INFO(dev)->gen >= 9) {
3287                 skl_detach_scalers(crtc);
3288
3289                 if (pipe_config->pch_pfit.enabled)
3290                         skylake_pfit_enable(crtc);
3291         } else if (HAS_PCH_SPLIT(dev)) {
3292                 if (pipe_config->pch_pfit.enabled)
3293                         ironlake_pfit_enable(crtc);
3294                 else if (old_crtc_state->pch_pfit.enabled)
3295                         ironlake_pfit_disable(crtc, true);
3296         }
3297 }
3298
3299 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3300 {
3301         struct drm_device *dev = crtc->dev;
3302         struct drm_i915_private *dev_priv = dev->dev_private;
3303         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3304         int pipe = intel_crtc->pipe;
3305         i915_reg_t reg;
3306         u32 temp;
3307
3308         /* enable normal train */
3309         reg = FDI_TX_CTL(pipe);
3310         temp = I915_READ(reg);
3311         if (IS_IVYBRIDGE(dev)) {
3312                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3313                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3314         } else {
3315                 temp &= ~FDI_LINK_TRAIN_NONE;
3316                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3317         }
3318         I915_WRITE(reg, temp);
3319
3320         reg = FDI_RX_CTL(pipe);
3321         temp = I915_READ(reg);
3322         if (HAS_PCH_CPT(dev)) {
3323                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3324                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3325         } else {
3326                 temp &= ~FDI_LINK_TRAIN_NONE;
3327                 temp |= FDI_LINK_TRAIN_NONE;
3328         }
3329         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3330
3331         /* wait one idle pattern time */
3332         POSTING_READ(reg);
3333         udelay(1000);
3334
3335         /* IVB wants error correction enabled */
3336         if (IS_IVYBRIDGE(dev))
3337                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3338                            FDI_FE_ERRC_ENABLE);
3339 }
3340
3341 /* The FDI link training functions for ILK/Ibexpeak. */
3342 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3343 {
3344         struct drm_device *dev = crtc->dev;
3345         struct drm_i915_private *dev_priv = dev->dev_private;
3346         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3347         int pipe = intel_crtc->pipe;
3348         i915_reg_t reg;
3349         u32 temp, tries;
3350
3351         /* FDI needs bits from pipe first */
3352         assert_pipe_enabled(dev_priv, pipe);
3353
3354         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3355            for train result */
3356         reg = FDI_RX_IMR(pipe);
3357         temp = I915_READ(reg);
3358         temp &= ~FDI_RX_SYMBOL_LOCK;
3359         temp &= ~FDI_RX_BIT_LOCK;
3360         I915_WRITE(reg, temp);
3361         I915_READ(reg);
3362         udelay(150);
3363
3364         /* enable CPU FDI TX and PCH FDI RX */
3365         reg = FDI_TX_CTL(pipe);
3366         temp = I915_READ(reg);
3367         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3368         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3369         temp &= ~FDI_LINK_TRAIN_NONE;
3370         temp |= FDI_LINK_TRAIN_PATTERN_1;
3371         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3372
3373         reg = FDI_RX_CTL(pipe);
3374         temp = I915_READ(reg);
3375         temp &= ~FDI_LINK_TRAIN_NONE;
3376         temp |= FDI_LINK_TRAIN_PATTERN_1;
3377         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3378
3379         POSTING_READ(reg);
3380         udelay(150);
3381
3382         /* Ironlake workaround, enable clock pointer after FDI enable*/
3383         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3384         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3385                    FDI_RX_PHASE_SYNC_POINTER_EN);
3386
3387         reg = FDI_RX_IIR(pipe);
3388         for (tries = 0; tries < 5; tries++) {
3389                 temp = I915_READ(reg);
3390                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3391
3392                 if ((temp & FDI_RX_BIT_LOCK)) {
3393                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3394                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3395                         break;
3396                 }
3397         }
3398         if (tries == 5)
3399                 DRM_ERROR("FDI train 1 fail!\n");
3400
3401         /* Train 2 */
3402         reg = FDI_TX_CTL(pipe);
3403         temp = I915_READ(reg);
3404         temp &= ~FDI_LINK_TRAIN_NONE;
3405         temp |= FDI_LINK_TRAIN_PATTERN_2;
3406         I915_WRITE(reg, temp);
3407
3408         reg = FDI_RX_CTL(pipe);
3409         temp = I915_READ(reg);
3410         temp &= ~FDI_LINK_TRAIN_NONE;
3411         temp |= FDI_LINK_TRAIN_PATTERN_2;
3412         I915_WRITE(reg, temp);
3413
3414         POSTING_READ(reg);
3415         udelay(150);
3416
3417         reg = FDI_RX_IIR(pipe);
3418         for (tries = 0; tries < 5; tries++) {
3419                 temp = I915_READ(reg);
3420                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3421
3422                 if (temp & FDI_RX_SYMBOL_LOCK) {
3423                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3424                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3425                         break;
3426                 }
3427         }
3428         if (tries == 5)
3429                 DRM_ERROR("FDI train 2 fail!\n");
3430
3431         DRM_DEBUG_KMS("FDI train done\n");
3432
3433 }
3434
3435 static const int snb_b_fdi_train_param[] = {
3436         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3437         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3438         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3439         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3440 };
3441
3442 /* The FDI link training functions for SNB/Cougarpoint. */
3443 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3444 {
3445         struct drm_device *dev = crtc->dev;
3446         struct drm_i915_private *dev_priv = dev->dev_private;
3447         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3448         int pipe = intel_crtc->pipe;
3449         i915_reg_t reg;
3450         u32 temp, i, retry;
3451
3452         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3453            for train result */
3454         reg = FDI_RX_IMR(pipe);
3455         temp = I915_READ(reg);
3456         temp &= ~FDI_RX_SYMBOL_LOCK;
3457         temp &= ~FDI_RX_BIT_LOCK;
3458         I915_WRITE(reg, temp);
3459
3460         POSTING_READ(reg);
3461         udelay(150);
3462
3463         /* enable CPU FDI TX and PCH FDI RX */
3464         reg = FDI_TX_CTL(pipe);
3465         temp = I915_READ(reg);
3466         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3467         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3468         temp &= ~FDI_LINK_TRAIN_NONE;
3469         temp |= FDI_LINK_TRAIN_PATTERN_1;
3470         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3471         /* SNB-B */
3472         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3473         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3474
3475         I915_WRITE(FDI_RX_MISC(pipe),
3476                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3477
3478         reg = FDI_RX_CTL(pipe);
3479         temp = I915_READ(reg);
3480         if (HAS_PCH_CPT(dev)) {
3481                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3482                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3483         } else {
3484                 temp &= ~FDI_LINK_TRAIN_NONE;
3485                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3486         }
3487         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3488
3489         POSTING_READ(reg);
3490         udelay(150);
3491
3492         for (i = 0; i < 4; i++) {
3493                 reg = FDI_TX_CTL(pipe);
3494                 temp = I915_READ(reg);
3495                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3496                 temp |= snb_b_fdi_train_param[i];
3497                 I915_WRITE(reg, temp);
3498
3499                 POSTING_READ(reg);
3500                 udelay(500);
3501
3502                 for (retry = 0; retry < 5; retry++) {
3503                         reg = FDI_RX_IIR(pipe);
3504                         temp = I915_READ(reg);
3505                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3506                         if (temp & FDI_RX_BIT_LOCK) {
3507                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3508                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3509                                 break;
3510                         }
3511                         udelay(50);
3512                 }
3513                 if (retry < 5)
3514                         break;
3515         }
3516         if (i == 4)
3517                 DRM_ERROR("FDI train 1 fail!\n");
3518
3519         /* Train 2 */
3520         reg = FDI_TX_CTL(pipe);
3521         temp = I915_READ(reg);
3522         temp &= ~FDI_LINK_TRAIN_NONE;
3523         temp |= FDI_LINK_TRAIN_PATTERN_2;
3524         if (IS_GEN6(dev)) {
3525                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3526                 /* SNB-B */
3527                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3528         }
3529         I915_WRITE(reg, temp);
3530
3531         reg = FDI_RX_CTL(pipe);
3532         temp = I915_READ(reg);
3533         if (HAS_PCH_CPT(dev)) {
3534                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3535                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3536         } else {
3537                 temp &= ~FDI_LINK_TRAIN_NONE;
3538                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3539         }
3540         I915_WRITE(reg, temp);
3541
3542         POSTING_READ(reg);
3543         udelay(150);
3544
3545         for (i = 0; i < 4; i++) {
3546                 reg = FDI_TX_CTL(pipe);
3547                 temp = I915_READ(reg);
3548                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3549                 temp |= snb_b_fdi_train_param[i];
3550                 I915_WRITE(reg, temp);
3551
3552                 POSTING_READ(reg);
3553                 udelay(500);
3554
3555                 for (retry = 0; retry < 5; retry++) {
3556                         reg = FDI_RX_IIR(pipe);
3557                         temp = I915_READ(reg);
3558                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3559                         if (temp & FDI_RX_SYMBOL_LOCK) {
3560                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3561                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3562                                 break;
3563                         }
3564                         udelay(50);
3565                 }
3566                 if (retry < 5)
3567                         break;
3568         }
3569         if (i == 4)
3570                 DRM_ERROR("FDI train 2 fail!\n");
3571
3572         DRM_DEBUG_KMS("FDI train done.\n");
3573 }
3574
3575 /* Manual link training for Ivy Bridge A0 parts */
3576 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3577 {
3578         struct drm_device *dev = crtc->dev;
3579         struct drm_i915_private *dev_priv = dev->dev_private;
3580         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3581         int pipe = intel_crtc->pipe;
3582         i915_reg_t reg;
3583         u32 temp, i, j;
3584
3585         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3586            for train result */
3587         reg = FDI_RX_IMR(pipe);
3588         temp = I915_READ(reg);
3589         temp &= ~FDI_RX_SYMBOL_LOCK;
3590         temp &= ~FDI_RX_BIT_LOCK;
3591         I915_WRITE(reg, temp);
3592
3593         POSTING_READ(reg);
3594         udelay(150);
3595
3596         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3597                       I915_READ(FDI_RX_IIR(pipe)));
3598
3599         /* Try each vswing and preemphasis setting twice before moving on */
3600         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3601                 /* disable first in case we need to retry */
3602                 reg = FDI_TX_CTL(pipe);
3603                 temp = I915_READ(reg);
3604                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3605                 temp &= ~FDI_TX_ENABLE;
3606                 I915_WRITE(reg, temp);
3607
3608                 reg = FDI_RX_CTL(pipe);
3609                 temp = I915_READ(reg);
3610                 temp &= ~FDI_LINK_TRAIN_AUTO;
3611                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3612                 temp &= ~FDI_RX_ENABLE;
3613                 I915_WRITE(reg, temp);
3614
3615                 /* enable CPU FDI TX and PCH FDI RX */
3616                 reg = FDI_TX_CTL(pipe);
3617                 temp = I915_READ(reg);
3618                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3619                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3620                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3621                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3622                 temp |= snb_b_fdi_train_param[j/2];
3623                 temp |= FDI_COMPOSITE_SYNC;
3624                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3625
3626                 I915_WRITE(FDI_RX_MISC(pipe),
3627                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3628
3629                 reg = FDI_RX_CTL(pipe);
3630                 temp = I915_READ(reg);
3631                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3632                 temp |= FDI_COMPOSITE_SYNC;
3633                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3634
3635                 POSTING_READ(reg);
3636                 udelay(1); /* should be 0.5us */
3637
3638                 for (i = 0; i < 4; i++) {
3639                         reg = FDI_RX_IIR(pipe);
3640                         temp = I915_READ(reg);
3641                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3642
3643                         if (temp & FDI_RX_BIT_LOCK ||
3644                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3645                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3646                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3647                                               i);
3648                                 break;
3649                         }
3650                         udelay(1); /* should be 0.5us */
3651                 }
3652                 if (i == 4) {
3653                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3654                         continue;
3655                 }
3656
3657                 /* Train 2 */
3658                 reg = FDI_TX_CTL(pipe);
3659                 temp = I915_READ(reg);
3660                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3661                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3662                 I915_WRITE(reg, temp);
3663
3664                 reg = FDI_RX_CTL(pipe);
3665                 temp = I915_READ(reg);
3666                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3667                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3668                 I915_WRITE(reg, temp);
3669
3670                 POSTING_READ(reg);
3671                 udelay(2); /* should be 1.5us */
3672
3673                 for (i = 0; i < 4; i++) {
3674                         reg = FDI_RX_IIR(pipe);
3675                         temp = I915_READ(reg);
3676                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3677
3678                         if (temp & FDI_RX_SYMBOL_LOCK ||
3679                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3680                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3681                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3682                                               i);
3683                                 goto train_done;
3684                         }
3685                         udelay(2); /* should be 1.5us */
3686                 }
3687                 if (i == 4)
3688                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3689         }
3690
3691 train_done:
3692         DRM_DEBUG_KMS("FDI train done.\n");
3693 }
3694
3695 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3696 {
3697         struct drm_device *dev = intel_crtc->base.dev;
3698         struct drm_i915_private *dev_priv = dev->dev_private;
3699         int pipe = intel_crtc->pipe;
3700         i915_reg_t reg;
3701         u32 temp;
3702
3703         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3704         reg = FDI_RX_CTL(pipe);
3705         temp = I915_READ(reg);
3706         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3707         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3708         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3709         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3710
3711         POSTING_READ(reg);
3712         udelay(200);
3713
3714         /* Switch from Rawclk to PCDclk */
3715         temp = I915_READ(reg);
3716         I915_WRITE(reg, temp | FDI_PCDCLK);
3717
3718         POSTING_READ(reg);
3719         udelay(200);
3720
3721         /* Enable CPU FDI TX PLL, always on for Ironlake */
3722         reg = FDI_TX_CTL(pipe);
3723         temp = I915_READ(reg);
3724         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3725                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3726
3727                 POSTING_READ(reg);
3728                 udelay(100);
3729         }
3730 }
3731
3732 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3733 {
3734         struct drm_device *dev = intel_crtc->base.dev;
3735         struct drm_i915_private *dev_priv = dev->dev_private;
3736         int pipe = intel_crtc->pipe;
3737         i915_reg_t reg;
3738         u32 temp;
3739
3740         /* Switch from PCDclk to Rawclk */
3741         reg = FDI_RX_CTL(pipe);
3742         temp = I915_READ(reg);
3743         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3744
3745         /* Disable CPU FDI TX PLL */
3746         reg = FDI_TX_CTL(pipe);
3747         temp = I915_READ(reg);
3748         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3749
3750         POSTING_READ(reg);
3751         udelay(100);
3752
3753         reg = FDI_RX_CTL(pipe);
3754         temp = I915_READ(reg);
3755         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3756
3757         /* Wait for the clocks to turn off. */
3758         POSTING_READ(reg);
3759         udelay(100);
3760 }
3761
3762 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3763 {
3764         struct drm_device *dev = crtc->dev;
3765         struct drm_i915_private *dev_priv = dev->dev_private;
3766         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3767         int pipe = intel_crtc->pipe;
3768         i915_reg_t reg;
3769         u32 temp;
3770
3771         /* disable CPU FDI tx and PCH FDI rx */
3772         reg = FDI_TX_CTL(pipe);
3773         temp = I915_READ(reg);
3774         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3775         POSTING_READ(reg);
3776
3777         reg = FDI_RX_CTL(pipe);
3778         temp = I915_READ(reg);
3779         temp &= ~(0x7 << 16);
3780         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3781         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3782
3783         POSTING_READ(reg);
3784         udelay(100);
3785
3786         /* Ironlake workaround, disable clock pointer after downing FDI */
3787         if (HAS_PCH_IBX(dev))
3788                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3789
3790         /* still set train pattern 1 */
3791         reg = FDI_TX_CTL(pipe);
3792         temp = I915_READ(reg);
3793         temp &= ~FDI_LINK_TRAIN_NONE;
3794         temp |= FDI_LINK_TRAIN_PATTERN_1;
3795         I915_WRITE(reg, temp);
3796
3797         reg = FDI_RX_CTL(pipe);
3798         temp = I915_READ(reg);
3799         if (HAS_PCH_CPT(dev)) {
3800                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3801                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3802         } else {
3803                 temp &= ~FDI_LINK_TRAIN_NONE;
3804                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3805         }
3806         /* BPC in FDI rx is consistent with that in PIPECONF */
3807         temp &= ~(0x07 << 16);
3808         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3809         I915_WRITE(reg, temp);
3810
3811         POSTING_READ(reg);
3812         udelay(100);
3813 }
3814
3815 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3816 {
3817         struct intel_crtc *crtc;
3818
3819         /* Note that we don't need to be called with mode_config.lock here
3820          * as our list of CRTC objects is static for the lifetime of the
3821          * device and so cannot disappear as we iterate. Similarly, we can
3822          * happily treat the predicates as racy, atomic checks as userspace
3823          * cannot claim and pin a new fb without at least acquring the
3824          * struct_mutex and so serialising with us.
3825          */
3826         for_each_intel_crtc(dev, crtc) {
3827                 if (atomic_read(&crtc->unpin_work_count) == 0)
3828                         continue;
3829
3830                 if (crtc->unpin_work)
3831                         intel_wait_for_vblank(dev, crtc->pipe);
3832
3833                 return true;
3834         }
3835
3836         return false;
3837 }
3838
3839 static void page_flip_completed(struct intel_crtc *intel_crtc)
3840 {
3841         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3842         struct intel_unpin_work *work = intel_crtc->unpin_work;
3843
3844         /* ensure that the unpin work is consistent wrt ->pending. */
3845         smp_rmb();
3846         intel_crtc->unpin_work = NULL;
3847
3848         if (work->event)
3849                 drm_send_vblank_event(intel_crtc->base.dev,
3850                                       intel_crtc->pipe,
3851                                       work->event);
3852
3853         drm_crtc_vblank_put(&intel_crtc->base);
3854
3855         wake_up_all(&dev_priv->pending_flip_queue);
3856         queue_work(dev_priv->wq, &work->work);
3857
3858         trace_i915_flip_complete(intel_crtc->plane,
3859                                  work->pending_flip_obj);
3860 }
3861
3862 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3863 {
3864         struct drm_device *dev = crtc->dev;
3865         struct drm_i915_private *dev_priv = dev->dev_private;
3866         long ret;
3867
3868         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3869
3870         ret = wait_event_interruptible_timeout(
3871                                         dev_priv->pending_flip_queue,
3872                                         !intel_crtc_has_pending_flip(crtc),
3873                                         60*HZ);
3874
3875         if (ret < 0)
3876                 return ret;
3877
3878         if (ret == 0) {
3879                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3880
3881                 spin_lock_irq(&dev->event_lock);
3882                 if (intel_crtc->unpin_work) {
3883                         WARN_ONCE(1, "Removing stuck page flip\n");
3884                         page_flip_completed(intel_crtc);
3885                 }
3886                 spin_unlock_irq(&dev->event_lock);
3887         }
3888
3889         return 0;
3890 }
3891
3892 static void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
3893 {
3894         u32 temp;
3895
3896         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3897
3898         mutex_lock(&dev_priv->sb_lock);
3899
3900         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3901         temp |= SBI_SSCCTL_DISABLE;
3902         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3903
3904         mutex_unlock(&dev_priv->sb_lock);
3905 }
3906
3907 /* Program iCLKIP clock to the desired frequency */
3908 static void lpt_program_iclkip(struct drm_crtc *crtc)
3909 {
3910         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
3911         int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3912         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3913         u32 temp;
3914
3915         lpt_disable_iclkip(dev_priv);
3916
3917         /* The iCLK virtual clock root frequency is in MHz,
3918          * but the adjusted_mode->crtc_clock in in KHz. To get the
3919          * divisors, it is necessary to divide one by another, so we
3920          * convert the virtual clock precision to KHz here for higher
3921          * precision.
3922          */
3923         for (auxdiv = 0; auxdiv < 2; auxdiv++) {
3924                 u32 iclk_virtual_root_freq = 172800 * 1000;
3925                 u32 iclk_pi_range = 64;
3926                 u32 desired_divisor;
3927
3928                 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
3929                                                     clock << auxdiv);
3930                 divsel = (desired_divisor / iclk_pi_range) - 2;
3931                 phaseinc = desired_divisor % iclk_pi_range;
3932
3933                 /*
3934                  * Near 20MHz is a corner case which is
3935                  * out of range for the 7-bit divisor
3936                  */
3937                 if (divsel <= 0x7f)
3938                         break;
3939         }
3940
3941         /* This should not happen with any sane values */
3942         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3943                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3944         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3945                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3946
3947         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3948                         clock,
3949                         auxdiv,
3950                         divsel,
3951                         phasedir,
3952                         phaseinc);
3953
3954         mutex_lock(&dev_priv->sb_lock);
3955
3956         /* Program SSCDIVINTPHASE6 */
3957         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3958         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3959         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3960         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3961         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3962         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3963         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3964         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3965
3966         /* Program SSCAUXDIV */
3967         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3968         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3969         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3970         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3971
3972         /* Enable modulator and associated divider */
3973         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3974         temp &= ~SBI_SSCCTL_DISABLE;
3975         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3976
3977         mutex_unlock(&dev_priv->sb_lock);
3978
3979         /* Wait for initialization time */
3980         udelay(24);
3981
3982         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3983 }
3984
3985 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
3986 {
3987         u32 divsel, phaseinc, auxdiv;
3988         u32 iclk_virtual_root_freq = 172800 * 1000;
3989         u32 iclk_pi_range = 64;
3990         u32 desired_divisor;
3991         u32 temp;
3992
3993         if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
3994                 return 0;
3995
3996         mutex_lock(&dev_priv->sb_lock);
3997
3998         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3999         if (temp & SBI_SSCCTL_DISABLE) {
4000                 mutex_unlock(&dev_priv->sb_lock);
4001                 return 0;
4002         }
4003
4004         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4005         divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
4006                 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
4007         phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
4008                 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
4009
4010         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4011         auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
4012                 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
4013
4014         mutex_unlock(&dev_priv->sb_lock);
4015
4016         desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
4017
4018         return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4019                                  desired_divisor << auxdiv);
4020 }
4021
4022 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4023                                                 enum pipe pch_transcoder)
4024 {
4025         struct drm_device *dev = crtc->base.dev;
4026         struct drm_i915_private *dev_priv = dev->dev_private;
4027         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4028
4029         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4030                    I915_READ(HTOTAL(cpu_transcoder)));
4031         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4032                    I915_READ(HBLANK(cpu_transcoder)));
4033         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4034                    I915_READ(HSYNC(cpu_transcoder)));
4035
4036         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4037                    I915_READ(VTOTAL(cpu_transcoder)));
4038         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4039                    I915_READ(VBLANK(cpu_transcoder)));
4040         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4041                    I915_READ(VSYNC(cpu_transcoder)));
4042         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4043                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
4044 }
4045
4046 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4047 {
4048         struct drm_i915_private *dev_priv = dev->dev_private;
4049         uint32_t temp;
4050
4051         temp = I915_READ(SOUTH_CHICKEN1);
4052         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4053                 return;
4054
4055         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4056         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4057
4058         temp &= ~FDI_BC_BIFURCATION_SELECT;
4059         if (enable)
4060                 temp |= FDI_BC_BIFURCATION_SELECT;
4061
4062         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4063         I915_WRITE(SOUTH_CHICKEN1, temp);
4064         POSTING_READ(SOUTH_CHICKEN1);
4065 }
4066
4067 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4068 {
4069         struct drm_device *dev = intel_crtc->base.dev;
4070
4071         switch (intel_crtc->pipe) {
4072         case PIPE_A:
4073                 break;
4074         case PIPE_B:
4075                 if (intel_crtc->config->fdi_lanes > 2)
4076                         cpt_set_fdi_bc_bifurcation(dev, false);
4077                 else
4078                         cpt_set_fdi_bc_bifurcation(dev, true);
4079
4080                 break;
4081         case PIPE_C:
4082                 cpt_set_fdi_bc_bifurcation(dev, true);
4083
4084                 break;
4085         default:
4086                 BUG();
4087         }
4088 }
4089
4090 /* Return which DP Port should be selected for Transcoder DP control */
4091 static enum port
4092 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4093 {
4094         struct drm_device *dev = crtc->dev;
4095         struct intel_encoder *encoder;
4096
4097         for_each_encoder_on_crtc(dev, crtc, encoder) {
4098                 if (encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4099                     encoder->type == INTEL_OUTPUT_EDP)
4100                         return enc_to_dig_port(&encoder->base)->port;
4101         }
4102
4103         return -1;
4104 }
4105
4106 /*
4107  * Enable PCH resources required for PCH ports:
4108  *   - PCH PLLs
4109  *   - FDI training & RX/TX
4110  *   - update transcoder timings
4111  *   - DP transcoding bits
4112  *   - transcoder
4113  */
4114 static void ironlake_pch_enable(struct drm_crtc *crtc)
4115 {
4116         struct drm_device *dev = crtc->dev;
4117         struct drm_i915_private *dev_priv = dev->dev_private;
4118         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4119         int pipe = intel_crtc->pipe;
4120         u32 temp;
4121
4122         assert_pch_transcoder_disabled(dev_priv, pipe);
4123
4124         if (IS_IVYBRIDGE(dev))
4125                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4126
4127         /* Write the TU size bits before fdi link training, so that error
4128          * detection works. */
4129         I915_WRITE(FDI_RX_TUSIZE1(pipe),
4130                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4131
4132         /*
4133          * Sometimes spurious CPU pipe underruns happen during FDI
4134          * training, at least with VGA+HDMI cloning. Suppress them.
4135          */
4136         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4137
4138         /* For PCH output, training FDI link */
4139         dev_priv->display.fdi_link_train(crtc);
4140
4141         /* We need to program the right clock selection before writing the pixel
4142          * mutliplier into the DPLL. */
4143         if (HAS_PCH_CPT(dev)) {
4144                 u32 sel;
4145
4146                 temp = I915_READ(PCH_DPLL_SEL);
4147                 temp |= TRANS_DPLL_ENABLE(pipe);
4148                 sel = TRANS_DPLLB_SEL(pipe);
4149                 if (intel_crtc->config->shared_dpll ==
4150                     intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4151                         temp |= sel;
4152                 else
4153                         temp &= ~sel;
4154                 I915_WRITE(PCH_DPLL_SEL, temp);
4155         }
4156
4157         /* XXX: pch pll's can be enabled any time before we enable the PCH
4158          * transcoder, and we actually should do this to not upset any PCH
4159          * transcoder that already use the clock when we share it.
4160          *
4161          * Note that enable_shared_dpll tries to do the right thing, but
4162          * get_shared_dpll unconditionally resets the pll - we need that to have
4163          * the right LVDS enable sequence. */
4164         intel_enable_shared_dpll(intel_crtc);
4165
4166         /* set transcoder timing, panel must allow it */
4167         assert_panel_unlocked(dev_priv, pipe);
4168         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4169
4170         intel_fdi_normal_train(crtc);
4171
4172         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4173
4174         /* For PCH DP, enable TRANS_DP_CTL */
4175         if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4176                 const struct drm_display_mode *adjusted_mode =
4177                         &intel_crtc->config->base.adjusted_mode;
4178                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4179                 i915_reg_t reg = TRANS_DP_CTL(pipe);
4180                 temp = I915_READ(reg);
4181                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4182                           TRANS_DP_SYNC_MASK |
4183                           TRANS_DP_BPC_MASK);
4184                 temp |= TRANS_DP_OUTPUT_ENABLE;
4185                 temp |= bpc << 9; /* same format but at 11:9 */
4186
4187                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4188                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4189                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4190                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4191
4192                 switch (intel_trans_dp_port_sel(crtc)) {
4193                 case PORT_B:
4194                         temp |= TRANS_DP_PORT_SEL_B;
4195                         break;
4196                 case PORT_C:
4197                         temp |= TRANS_DP_PORT_SEL_C;
4198                         break;
4199                 case PORT_D:
4200                         temp |= TRANS_DP_PORT_SEL_D;
4201                         break;
4202                 default:
4203                         BUG();
4204                 }
4205
4206                 I915_WRITE(reg, temp);
4207         }
4208
4209         ironlake_enable_pch_transcoder(dev_priv, pipe);
4210 }
4211
4212 static void lpt_pch_enable(struct drm_crtc *crtc)
4213 {
4214         struct drm_device *dev = crtc->dev;
4215         struct drm_i915_private *dev_priv = dev->dev_private;
4216         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4217         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4218
4219         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4220
4221         lpt_program_iclkip(crtc);
4222
4223         /* Set transcoder timing. */
4224         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4225
4226         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4227 }
4228
4229 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4230 {
4231         struct drm_i915_private *dev_priv = dev->dev_private;
4232         i915_reg_t dslreg = PIPEDSL(pipe);
4233         u32 temp;
4234
4235         temp = I915_READ(dslreg);
4236         udelay(500);
4237         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4238                 if (wait_for(I915_READ(dslreg) != temp, 5))
4239                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4240         }
4241 }
4242
4243 static int
4244 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4245                   unsigned scaler_user, int *scaler_id, unsigned int rotation,
4246                   int src_w, int src_h, int dst_w, int dst_h)
4247 {
4248         struct intel_crtc_scaler_state *scaler_state =
4249                 &crtc_state->scaler_state;
4250         struct intel_crtc *intel_crtc =
4251                 to_intel_crtc(crtc_state->base.crtc);
4252         int need_scaling;
4253
4254         need_scaling = intel_rotation_90_or_270(rotation) ?
4255                 (src_h != dst_w || src_w != dst_h):
4256                 (src_w != dst_w || src_h != dst_h);
4257
4258         /*
4259          * if plane is being disabled or scaler is no more required or force detach
4260          *  - free scaler binded to this plane/crtc
4261          *  - in order to do this, update crtc->scaler_usage
4262          *
4263          * Here scaler state in crtc_state is set free so that
4264          * scaler can be assigned to other user. Actual register
4265          * update to free the scaler is done in plane/panel-fit programming.
4266          * For this purpose crtc/plane_state->scaler_id isn't reset here.
4267          */
4268         if (force_detach || !need_scaling) {
4269                 if (*scaler_id >= 0) {
4270                         scaler_state->scaler_users &= ~(1 << scaler_user);
4271                         scaler_state->scalers[*scaler_id].in_use = 0;
4272
4273                         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4274                                 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4275                                 intel_crtc->pipe, scaler_user, *scaler_id,
4276                                 scaler_state->scaler_users);
4277                         *scaler_id = -1;
4278                 }
4279                 return 0;
4280         }
4281
4282         /* range checks */
4283         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4284                 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4285
4286                 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4287                 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4288                 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4289                         "size is out of scaler range\n",
4290                         intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4291                 return -EINVAL;
4292         }
4293
4294         /* mark this plane as a scaler user in crtc_state */
4295         scaler_state->scaler_users |= (1 << scaler_user);
4296         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4297                 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4298                 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4299                 scaler_state->scaler_users);
4300
4301         return 0;
4302 }
4303
4304 /**
4305  * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4306  *
4307  * @state: crtc's scaler state
4308  *
4309  * Return
4310  *     0 - scaler_usage updated successfully
4311  *    error - requested scaling cannot be supported or other error condition
4312  */
4313 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4314 {
4315         struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4316         const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4317
4318         DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4319                       intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4320
4321         return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4322                 &state->scaler_state.scaler_id, BIT(DRM_ROTATE_0),
4323                 state->pipe_src_w, state->pipe_src_h,
4324                 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4325 }
4326
4327 /**
4328  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4329  *
4330  * @state: crtc's scaler state
4331  * @plane_state: atomic plane state to update
4332  *
4333  * Return
4334  *     0 - scaler_usage updated successfully
4335  *    error - requested scaling cannot be supported or other error condition
4336  */
4337 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4338                                    struct intel_plane_state *plane_state)
4339 {
4340
4341         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4342         struct intel_plane *intel_plane =
4343                 to_intel_plane(plane_state->base.plane);
4344         struct drm_framebuffer *fb = plane_state->base.fb;
4345         int ret;
4346
4347         bool force_detach = !fb || !plane_state->visible;
4348
4349         DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4350                       intel_plane->base.base.id, intel_crtc->pipe,
4351                       drm_plane_index(&intel_plane->base));
4352
4353         ret = skl_update_scaler(crtc_state, force_detach,
4354                                 drm_plane_index(&intel_plane->base),
4355                                 &plane_state->scaler_id,
4356                                 plane_state->base.rotation,
4357                                 drm_rect_width(&plane_state->src) >> 16,
4358                                 drm_rect_height(&plane_state->src) >> 16,
4359                                 drm_rect_width(&plane_state->dst),
4360                                 drm_rect_height(&plane_state->dst));
4361
4362         if (ret || plane_state->scaler_id < 0)
4363                 return ret;
4364
4365         /* check colorkey */
4366         if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4367                 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4368                               intel_plane->base.base.id);
4369                 return -EINVAL;
4370         }
4371
4372         /* Check src format */
4373         switch (fb->pixel_format) {
4374         case DRM_FORMAT_RGB565:
4375         case DRM_FORMAT_XBGR8888:
4376         case DRM_FORMAT_XRGB8888:
4377         case DRM_FORMAT_ABGR8888:
4378         case DRM_FORMAT_ARGB8888:
4379         case DRM_FORMAT_XRGB2101010:
4380         case DRM_FORMAT_XBGR2101010:
4381         case DRM_FORMAT_YUYV:
4382         case DRM_FORMAT_YVYU:
4383         case DRM_FORMAT_UYVY:
4384         case DRM_FORMAT_VYUY:
4385                 break;
4386         default:
4387                 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4388                         intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4389                 return -EINVAL;
4390         }
4391
4392         return 0;
4393 }
4394
4395 static void skylake_scaler_disable(struct intel_crtc *crtc)
4396 {
4397         int i;
4398
4399         for (i = 0; i < crtc->num_scalers; i++)
4400                 skl_detach_scaler(crtc, i);
4401 }
4402
4403 static void skylake_pfit_enable(struct intel_crtc *crtc)
4404 {
4405         struct drm_device *dev = crtc->base.dev;
4406         struct drm_i915_private *dev_priv = dev->dev_private;
4407         int pipe = crtc->pipe;
4408         struct intel_crtc_scaler_state *scaler_state =
4409                 &crtc->config->scaler_state;
4410
4411         DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4412
4413         if (crtc->config->pch_pfit.enabled) {
4414                 int id;
4415
4416                 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4417                         DRM_ERROR("Requesting pfit without getting a scaler first\n");
4418                         return;
4419                 }
4420
4421                 id = scaler_state->scaler_id;
4422                 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4423                         PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4424                 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4425                 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4426
4427                 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4428         }
4429 }
4430
4431 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4432 {
4433         struct drm_device *dev = crtc->base.dev;
4434         struct drm_i915_private *dev_priv = dev->dev_private;
4435         int pipe = crtc->pipe;
4436
4437         if (crtc->config->pch_pfit.enabled) {
4438                 /* Force use of hard-coded filter coefficients
4439                  * as some pre-programmed values are broken,
4440                  * e.g. x201.
4441                  */
4442                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4443                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4444                                                  PF_PIPE_SEL_IVB(pipe));
4445                 else
4446                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4447                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4448                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4449         }
4450 }
4451
4452 void hsw_enable_ips(struct intel_crtc *crtc)
4453 {
4454         struct drm_device *dev = crtc->base.dev;
4455         struct drm_i915_private *dev_priv = dev->dev_private;
4456
4457         if (!crtc->config->ips_enabled)
4458                 return;
4459
4460         /* We can only enable IPS after we enable a plane and wait for a vblank */
4461         intel_wait_for_vblank(dev, crtc->pipe);
4462
4463         assert_plane_enabled(dev_priv, crtc->plane);
4464         if (IS_BROADWELL(dev)) {
4465                 mutex_lock(&dev_priv->rps.hw_lock);
4466                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4467                 mutex_unlock(&dev_priv->rps.hw_lock);
4468                 /* Quoting Art Runyan: "its not safe to expect any particular
4469                  * value in IPS_CTL bit 31 after enabling IPS through the
4470                  * mailbox." Moreover, the mailbox may return a bogus state,
4471                  * so we need to just enable it and continue on.
4472                  */
4473         } else {
4474                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4475                 /* The bit only becomes 1 in the next vblank, so this wait here
4476                  * is essentially intel_wait_for_vblank. If we don't have this
4477                  * and don't wait for vblanks until the end of crtc_enable, then
4478                  * the HW state readout code will complain that the expected
4479                  * IPS_CTL value is not the one we read. */
4480                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4481                         DRM_ERROR("Timed out waiting for IPS enable\n");
4482         }
4483 }
4484
4485 void hsw_disable_ips(struct intel_crtc *crtc)
4486 {
4487         struct drm_device *dev = crtc->base.dev;
4488         struct drm_i915_private *dev_priv = dev->dev_private;
4489
4490         if (!crtc->config->ips_enabled)
4491                 return;
4492
4493         assert_plane_enabled(dev_priv, crtc->plane);
4494         if (IS_BROADWELL(dev)) {
4495                 mutex_lock(&dev_priv->rps.hw_lock);
4496                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4497                 mutex_unlock(&dev_priv->rps.hw_lock);
4498                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4499                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4500                         DRM_ERROR("Timed out waiting for IPS disable\n");
4501         } else {
4502                 I915_WRITE(IPS_CTL, 0);
4503                 POSTING_READ(IPS_CTL);
4504         }
4505
4506         /* We need to wait for a vblank before we can disable the plane. */
4507         intel_wait_for_vblank(dev, crtc->pipe);
4508 }
4509
4510 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4511 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4512 {
4513         struct drm_device *dev = crtc->dev;
4514         struct drm_i915_private *dev_priv = dev->dev_private;
4515         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4516         enum pipe pipe = intel_crtc->pipe;
4517         int i;
4518         bool reenable_ips = false;
4519
4520         /* The clocks have to be on to load the palette. */
4521         if (!crtc->state->active)
4522                 return;
4523
4524         if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
4525                 if (intel_crtc->config->has_dsi_encoder)
4526                         assert_dsi_pll_enabled(dev_priv);
4527                 else
4528                         assert_pll_enabled(dev_priv, pipe);
4529         }
4530
4531         /* Workaround : Do not read or write the pipe palette/gamma data while
4532          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4533          */
4534         if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4535             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4536              GAMMA_MODE_MODE_SPLIT)) {
4537                 hsw_disable_ips(intel_crtc);
4538                 reenable_ips = true;
4539         }
4540
4541         for (i = 0; i < 256; i++) {
4542                 i915_reg_t palreg;
4543
4544                 if (HAS_GMCH_DISPLAY(dev))
4545                         palreg = PALETTE(pipe, i);
4546                 else
4547                         palreg = LGC_PALETTE(pipe, i);
4548
4549                 I915_WRITE(palreg,
4550                            (intel_crtc->lut_r[i] << 16) |
4551                            (intel_crtc->lut_g[i] << 8) |
4552                            intel_crtc->lut_b[i]);
4553         }
4554
4555         if (reenable_ips)
4556                 hsw_enable_ips(intel_crtc);
4557 }
4558
4559 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4560 {
4561         if (intel_crtc->overlay) {
4562                 struct drm_device *dev = intel_crtc->base.dev;
4563                 struct drm_i915_private *dev_priv = dev->dev_private;
4564
4565                 mutex_lock(&dev->struct_mutex);
4566                 dev_priv->mm.interruptible = false;
4567                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4568                 dev_priv->mm.interruptible = true;
4569                 mutex_unlock(&dev->struct_mutex);
4570         }
4571
4572         /* Let userspace switch the overlay on again. In most cases userspace
4573          * has to recompute where to put it anyway.
4574          */
4575 }
4576
4577 /**
4578  * intel_post_enable_primary - Perform operations after enabling primary plane
4579  * @crtc: the CRTC whose primary plane was just enabled
4580  *
4581  * Performs potentially sleeping operations that must be done after the primary
4582  * plane is enabled, such as updating FBC and IPS.  Note that this may be
4583  * called due to an explicit primary plane update, or due to an implicit
4584  * re-enable that is caused when a sprite plane is updated to no longer
4585  * completely hide the primary plane.
4586  */
4587 static void
4588 intel_post_enable_primary(struct drm_crtc *crtc)
4589 {
4590         struct drm_device *dev = crtc->dev;
4591         struct drm_i915_private *dev_priv = dev->dev_private;
4592         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4593         int pipe = intel_crtc->pipe;
4594
4595         /*
4596          * FIXME IPS should be fine as long as one plane is
4597          * enabled, but in practice it seems to have problems
4598          * when going from primary only to sprite only and vice
4599          * versa.
4600          */
4601         hsw_enable_ips(intel_crtc);
4602
4603         /*
4604          * Gen2 reports pipe underruns whenever all planes are disabled.
4605          * So don't enable underrun reporting before at least some planes
4606          * are enabled.
4607          * FIXME: Need to fix the logic to work when we turn off all planes
4608          * but leave the pipe running.
4609          */
4610         if (IS_GEN2(dev))
4611                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4612
4613         /* Underruns don't always raise interrupts, so check manually. */
4614         intel_check_cpu_fifo_underruns(dev_priv);
4615         intel_check_pch_fifo_underruns(dev_priv);
4616 }
4617
4618 /**
4619  * intel_pre_disable_primary - Perform operations before disabling primary plane
4620  * @crtc: the CRTC whose primary plane is to be disabled
4621  *
4622  * Performs potentially sleeping operations that must be done before the
4623  * primary plane is disabled, such as updating FBC and IPS.  Note that this may
4624  * be called due to an explicit primary plane update, or due to an implicit
4625  * disable that is caused when a sprite plane completely hides the primary
4626  * plane.
4627  */
4628 static void
4629 intel_pre_disable_primary(struct drm_crtc *crtc)
4630 {
4631         struct drm_device *dev = crtc->dev;
4632         struct drm_i915_private *dev_priv = dev->dev_private;
4633         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4634         int pipe = intel_crtc->pipe;
4635
4636         /*
4637          * Gen2 reports pipe underruns whenever all planes are disabled.
4638          * So diasble underrun reporting before all the planes get disabled.
4639          * FIXME: Need to fix the logic to work when we turn off all planes
4640          * but leave the pipe running.
4641          */
4642         if (IS_GEN2(dev))
4643                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4644
4645         /*
4646          * Vblank time updates from the shadow to live plane control register
4647          * are blocked if the memory self-refresh mode is active at that
4648          * moment. So to make sure the plane gets truly disabled, disable
4649          * first the self-refresh mode. The self-refresh enable bit in turn
4650          * will be checked/applied by the HW only at the next frame start
4651          * event which is after the vblank start event, so we need to have a
4652          * wait-for-vblank between disabling the plane and the pipe.
4653          */
4654         if (HAS_GMCH_DISPLAY(dev)) {
4655                 intel_set_memory_cxsr(dev_priv, false);
4656                 dev_priv->wm.vlv.cxsr = false;
4657                 intel_wait_for_vblank(dev, pipe);
4658         }
4659
4660         /*
4661          * FIXME IPS should be fine as long as one plane is
4662          * enabled, but in practice it seems to have problems
4663          * when going from primary only to sprite only and vice
4664          * versa.
4665          */
4666         hsw_disable_ips(intel_crtc);
4667 }
4668
4669 static void intel_post_plane_update(struct intel_crtc *crtc)
4670 {
4671         struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4672         struct intel_crtc_state *pipe_config =
4673                 to_intel_crtc_state(crtc->base.state);
4674         struct drm_device *dev = crtc->base.dev;
4675
4676         intel_frontbuffer_flip(dev, atomic->fb_bits);
4677
4678         crtc->wm.cxsr_allowed = true;
4679
4680         if (pipe_config->update_wm_post && pipe_config->base.active)
4681                 intel_update_watermarks(&crtc->base);
4682
4683         if (atomic->update_fbc)
4684                 intel_fbc_post_update(crtc);
4685
4686         if (atomic->post_enable_primary)
4687                 intel_post_enable_primary(&crtc->base);
4688
4689         memset(atomic, 0, sizeof(*atomic));
4690 }
4691
4692 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state)
4693 {
4694         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4695         struct drm_device *dev = crtc->base.dev;
4696         struct drm_i915_private *dev_priv = dev->dev_private;
4697         struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4698         struct intel_crtc_state *pipe_config =
4699                 to_intel_crtc_state(crtc->base.state);
4700         struct drm_atomic_state *old_state = old_crtc_state->base.state;
4701         struct drm_plane *primary = crtc->base.primary;
4702         struct drm_plane_state *old_pri_state =
4703                 drm_atomic_get_existing_plane_state(old_state, primary);
4704         bool modeset = needs_modeset(&pipe_config->base);
4705
4706         if (atomic->update_fbc)
4707                 intel_fbc_pre_update(crtc);
4708
4709         if (old_pri_state) {
4710                 struct intel_plane_state *primary_state =
4711                         to_intel_plane_state(primary->state);
4712                 struct intel_plane_state *old_primary_state =
4713                         to_intel_plane_state(old_pri_state);
4714
4715                 if (old_primary_state->visible &&
4716                     (modeset || !primary_state->visible))
4717                         intel_pre_disable_primary(&crtc->base);
4718         }
4719
4720         if (pipe_config->disable_cxsr) {
4721                 crtc->wm.cxsr_allowed = false;
4722
4723                 if (old_crtc_state->base.active)
4724                         intel_set_memory_cxsr(dev_priv, false);
4725         }
4726
4727         /*
4728          * IVB workaround: must disable low power watermarks for at least
4729          * one frame before enabling scaling.  LP watermarks can be re-enabled
4730          * when scaling is disabled.
4731          *
4732          * WaCxSRDisabledForSpriteScaling:ivb
4733          */
4734         if (pipe_config->disable_lp_wm) {
4735                 ilk_disable_lp_wm(dev);
4736                 intel_wait_for_vblank(dev, crtc->pipe);
4737         }
4738
4739         /*
4740          * If we're doing a modeset, we're done.  No need to do any pre-vblank
4741          * watermark programming here.
4742          */
4743         if (needs_modeset(&pipe_config->base))
4744                 return;
4745
4746         /*
4747          * For platforms that support atomic watermarks, program the
4748          * 'intermediate' watermarks immediately.  On pre-gen9 platforms, these
4749          * will be the intermediate values that are safe for both pre- and
4750          * post- vblank; when vblank happens, the 'active' values will be set
4751          * to the final 'target' values and we'll do this again to get the
4752          * optimal watermarks.  For gen9+ platforms, the values we program here
4753          * will be the final target values which will get automatically latched
4754          * at vblank time; no further programming will be necessary.
4755          *
4756          * If a platform hasn't been transitioned to atomic watermarks yet,
4757          * we'll continue to update watermarks the old way, if flags tell
4758          * us to.
4759          */
4760         if (dev_priv->display.initial_watermarks != NULL)
4761                 dev_priv->display.initial_watermarks(pipe_config);
4762         else if (pipe_config->update_wm_pre)
4763                 intel_update_watermarks(&crtc->base);
4764 }
4765
4766 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4767 {
4768         struct drm_device *dev = crtc->dev;
4769         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4770         struct drm_plane *p;
4771         int pipe = intel_crtc->pipe;
4772
4773         intel_crtc_dpms_overlay_disable(intel_crtc);
4774
4775         drm_for_each_plane_mask(p, dev, plane_mask)
4776                 to_intel_plane(p)->disable_plane(p, crtc);
4777
4778         /*
4779          * FIXME: Once we grow proper nuclear flip support out of this we need
4780          * to compute the mask of flip planes precisely. For the time being
4781          * consider this a flip to a NULL plane.
4782          */
4783         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4784 }
4785
4786 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4787 {
4788         struct drm_device *dev = crtc->dev;
4789         struct drm_i915_private *dev_priv = dev->dev_private;
4790         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4791         struct intel_encoder *encoder;
4792         int pipe = intel_crtc->pipe;
4793
4794         if (WARN_ON(intel_crtc->active))
4795                 return;
4796
4797         if (intel_crtc->config->has_pch_encoder)
4798                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4799
4800         if (intel_crtc->config->has_pch_encoder)
4801                 intel_prepare_shared_dpll(intel_crtc);
4802
4803         if (intel_crtc->config->has_dp_encoder)
4804                 intel_dp_set_m_n(intel_crtc, M1_N1);
4805
4806         intel_set_pipe_timings(intel_crtc);
4807
4808         if (intel_crtc->config->has_pch_encoder) {
4809                 intel_cpu_transcoder_set_m_n(intel_crtc,
4810                                      &intel_crtc->config->fdi_m_n, NULL);
4811         }
4812
4813         ironlake_set_pipeconf(crtc);
4814
4815         intel_crtc->active = true;
4816
4817         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4818
4819         for_each_encoder_on_crtc(dev, crtc, encoder)
4820                 if (encoder->pre_enable)
4821                         encoder->pre_enable(encoder);
4822
4823         if (intel_crtc->config->has_pch_encoder) {
4824                 /* Note: FDI PLL enabling _must_ be done before we enable the
4825                  * cpu pipes, hence this is separate from all the other fdi/pch
4826                  * enabling. */
4827                 ironlake_fdi_pll_enable(intel_crtc);
4828         } else {
4829                 assert_fdi_tx_disabled(dev_priv, pipe);
4830                 assert_fdi_rx_disabled(dev_priv, pipe);
4831         }
4832
4833         ironlake_pfit_enable(intel_crtc);
4834
4835         /*
4836          * On ILK+ LUT must be loaded before the pipe is running but with
4837          * clocks enabled
4838          */
4839         intel_crtc_load_lut(crtc);
4840
4841         if (dev_priv->display.initial_watermarks != NULL)
4842                 dev_priv->display.initial_watermarks(intel_crtc->config);
4843         intel_enable_pipe(intel_crtc);
4844
4845         if (intel_crtc->config->has_pch_encoder)
4846                 ironlake_pch_enable(crtc);
4847
4848         assert_vblank_disabled(crtc);
4849         drm_crtc_vblank_on(crtc);
4850
4851         for_each_encoder_on_crtc(dev, crtc, encoder)
4852                 encoder->enable(encoder);
4853
4854         if (HAS_PCH_CPT(dev))
4855                 cpt_verify_modeset(dev, intel_crtc->pipe);
4856
4857         /* Must wait for vblank to avoid spurious PCH FIFO underruns */
4858         if (intel_crtc->config->has_pch_encoder)
4859                 intel_wait_for_vblank(dev, pipe);
4860         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4861 }
4862
4863 /* IPS only exists on ULT machines and is tied to pipe A. */
4864 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4865 {
4866         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4867 }
4868
4869 static void haswell_crtc_enable(struct drm_crtc *crtc)
4870 {
4871         struct drm_device *dev = crtc->dev;
4872         struct drm_i915_private *dev_priv = dev->dev_private;
4873         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4874         struct intel_encoder *encoder;
4875         int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4876         struct intel_crtc_state *pipe_config =
4877                 to_intel_crtc_state(crtc->state);
4878
4879         if (WARN_ON(intel_crtc->active))
4880                 return;
4881
4882         if (intel_crtc->config->has_pch_encoder)
4883                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4884                                                       false);
4885
4886         if (intel_crtc->config->shared_dpll)
4887                 intel_enable_shared_dpll(intel_crtc);
4888
4889         if (intel_crtc->config->has_dp_encoder)
4890                 intel_dp_set_m_n(intel_crtc, M1_N1);
4891
4892         intel_set_pipe_timings(intel_crtc);
4893
4894         if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4895                 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4896                            intel_crtc->config->pixel_multiplier - 1);
4897         }
4898
4899         if (intel_crtc->config->has_pch_encoder) {
4900                 intel_cpu_transcoder_set_m_n(intel_crtc,
4901                                      &intel_crtc->config->fdi_m_n, NULL);
4902         }
4903
4904         haswell_set_pipeconf(crtc);
4905
4906         intel_set_pipe_csc(crtc);
4907
4908         intel_crtc->active = true;
4909
4910         if (intel_crtc->config->has_pch_encoder)
4911                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4912         else
4913                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4914
4915         for_each_encoder_on_crtc(dev, crtc, encoder) {
4916                 if (encoder->pre_enable)
4917                         encoder->pre_enable(encoder);
4918         }
4919
4920         if (intel_crtc->config->has_pch_encoder)
4921                 dev_priv->display.fdi_link_train(crtc);
4922
4923         if (!intel_crtc->config->has_dsi_encoder)
4924                 intel_ddi_enable_pipe_clock(intel_crtc);
4925
4926         if (INTEL_INFO(dev)->gen >= 9)
4927                 skylake_pfit_enable(intel_crtc);
4928         else
4929                 ironlake_pfit_enable(intel_crtc);
4930
4931         /*
4932          * On ILK+ LUT must be loaded before the pipe is running but with
4933          * clocks enabled
4934          */
4935         intel_crtc_load_lut(crtc);
4936
4937         intel_ddi_set_pipe_settings(crtc);
4938         if (!intel_crtc->config->has_dsi_encoder)
4939                 intel_ddi_enable_transcoder_func(crtc);
4940
4941         if (dev_priv->display.initial_watermarks != NULL)
4942                 dev_priv->display.initial_watermarks(pipe_config);
4943         else
4944                 intel_update_watermarks(crtc);
4945         intel_enable_pipe(intel_crtc);
4946
4947         if (intel_crtc->config->has_pch_encoder)
4948                 lpt_pch_enable(crtc);
4949
4950         if (intel_crtc->config->dp_encoder_is_mst)
4951                 intel_ddi_set_vc_payload_alloc(crtc, true);
4952
4953         assert_vblank_disabled(crtc);
4954         drm_crtc_vblank_on(crtc);
4955
4956         for_each_encoder_on_crtc(dev, crtc, encoder) {
4957                 encoder->enable(encoder);
4958                 intel_opregion_notify_encoder(encoder, true);
4959         }
4960
4961         if (intel_crtc->config->has_pch_encoder) {
4962                 intel_wait_for_vblank(dev, pipe);
4963                 intel_wait_for_vblank(dev, pipe);
4964                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4965                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4966                                                       true);
4967         }
4968
4969         /* If we change the relative order between pipe/planes enabling, we need
4970          * to change the workaround. */
4971         hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
4972         if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
4973                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4974                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4975         }
4976 }
4977
4978 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
4979 {
4980         struct drm_device *dev = crtc->base.dev;
4981         struct drm_i915_private *dev_priv = dev->dev_private;
4982         int pipe = crtc->pipe;
4983
4984         /* To avoid upsetting the power well on haswell only disable the pfit if
4985          * it's in use. The hw state code will make sure we get this right. */
4986         if (force || crtc->config->pch_pfit.enabled) {
4987                 I915_WRITE(PF_CTL(pipe), 0);
4988                 I915_WRITE(PF_WIN_POS(pipe), 0);
4989                 I915_WRITE(PF_WIN_SZ(pipe), 0);
4990         }
4991 }
4992
4993 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4994 {
4995         struct drm_device *dev = crtc->dev;
4996         struct drm_i915_private *dev_priv = dev->dev_private;
4997         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4998         struct intel_encoder *encoder;
4999         int pipe = intel_crtc->pipe;
5000
5001         if (intel_crtc->config->has_pch_encoder)
5002                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5003
5004         for_each_encoder_on_crtc(dev, crtc, encoder)
5005                 encoder->disable(encoder);
5006
5007         drm_crtc_vblank_off(crtc);
5008         assert_vblank_disabled(crtc);
5009
5010         /*
5011          * Sometimes spurious CPU pipe underruns happen when the
5012          * pipe is already disabled, but FDI RX/TX is still enabled.
5013          * Happens at least with VGA+HDMI cloning. Suppress them.
5014          */
5015         if (intel_crtc->config->has_pch_encoder)
5016                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5017
5018         intel_disable_pipe(intel_crtc);
5019
5020         ironlake_pfit_disable(intel_crtc, false);
5021
5022         if (intel_crtc->config->has_pch_encoder) {
5023                 ironlake_fdi_disable(crtc);
5024                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5025         }
5026
5027         for_each_encoder_on_crtc(dev, crtc, encoder)
5028                 if (encoder->post_disable)
5029                         encoder->post_disable(encoder);
5030
5031         if (intel_crtc->config->has_pch_encoder) {
5032                 ironlake_disable_pch_transcoder(dev_priv, pipe);
5033
5034                 if (HAS_PCH_CPT(dev)) {
5035                         i915_reg_t reg;
5036                         u32 temp;
5037
5038                         /* disable TRANS_DP_CTL */
5039                         reg = TRANS_DP_CTL(pipe);
5040                         temp = I915_READ(reg);
5041                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5042                                   TRANS_DP_PORT_SEL_MASK);
5043                         temp |= TRANS_DP_PORT_SEL_NONE;
5044                         I915_WRITE(reg, temp);
5045
5046                         /* disable DPLL_SEL */
5047                         temp = I915_READ(PCH_DPLL_SEL);
5048                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5049                         I915_WRITE(PCH_DPLL_SEL, temp);
5050                 }
5051
5052                 ironlake_fdi_pll_disable(intel_crtc);
5053         }
5054
5055         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5056 }
5057
5058 static void haswell_crtc_disable(struct drm_crtc *crtc)
5059 {
5060         struct drm_device *dev = crtc->dev;
5061         struct drm_i915_private *dev_priv = dev->dev_private;
5062         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5063         struct intel_encoder *encoder;
5064         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5065
5066         if (intel_crtc->config->has_pch_encoder)
5067                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5068                                                       false);
5069
5070         for_each_encoder_on_crtc(dev, crtc, encoder) {
5071                 intel_opregion_notify_encoder(encoder, false);
5072                 encoder->disable(encoder);
5073         }
5074
5075         drm_crtc_vblank_off(crtc);
5076         assert_vblank_disabled(crtc);
5077
5078         intel_disable_pipe(intel_crtc);
5079
5080         if (intel_crtc->config->dp_encoder_is_mst)
5081                 intel_ddi_set_vc_payload_alloc(crtc, false);
5082
5083         if (!intel_crtc->config->has_dsi_encoder)
5084                 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5085
5086         if (INTEL_INFO(dev)->gen >= 9)
5087                 skylake_scaler_disable(intel_crtc);
5088         else
5089                 ironlake_pfit_disable(intel_crtc, false);
5090
5091         if (!intel_crtc->config->has_dsi_encoder)
5092                 intel_ddi_disable_pipe_clock(intel_crtc);
5093
5094         for_each_encoder_on_crtc(dev, crtc, encoder)
5095                 if (encoder->post_disable)
5096                         encoder->post_disable(encoder);
5097
5098         if (intel_crtc->config->has_pch_encoder) {
5099                 lpt_disable_pch_transcoder(dev_priv);
5100                 lpt_disable_iclkip(dev_priv);
5101                 intel_ddi_fdi_disable(crtc);
5102
5103                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5104                                                       true);
5105         }
5106 }
5107
5108 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5109 {
5110         struct drm_device *dev = crtc->base.dev;
5111         struct drm_i915_private *dev_priv = dev->dev_private;
5112         struct intel_crtc_state *pipe_config = crtc->config;
5113
5114         if (!pipe_config->gmch_pfit.control)
5115                 return;
5116
5117         /*
5118          * The panel fitter should only be adjusted whilst the pipe is disabled,
5119          * according to register description and PRM.
5120          */
5121         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5122         assert_pipe_disabled(dev_priv, crtc->pipe);
5123
5124         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5125         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5126
5127         /* Border color in case we don't scale up to the full screen. Black by
5128          * default, change to something else for debugging. */
5129         I915_WRITE(BCLRPAT(crtc->pipe), 0);
5130 }
5131
5132 static enum intel_display_power_domain port_to_power_domain(enum port port)
5133 {
5134         switch (port) {
5135         case PORT_A:
5136                 return POWER_DOMAIN_PORT_DDI_A_LANES;
5137         case PORT_B:
5138                 return POWER_DOMAIN_PORT_DDI_B_LANES;
5139         case PORT_C:
5140                 return POWER_DOMAIN_PORT_DDI_C_LANES;
5141         case PORT_D:
5142                 return POWER_DOMAIN_PORT_DDI_D_LANES;
5143         case PORT_E:
5144                 return POWER_DOMAIN_PORT_DDI_E_LANES;
5145         default:
5146                 MISSING_CASE(port);
5147                 return POWER_DOMAIN_PORT_OTHER;
5148         }
5149 }
5150
5151 static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
5152 {
5153         switch (port) {
5154         case PORT_A:
5155                 return POWER_DOMAIN_AUX_A;
5156         case PORT_B:
5157                 return POWER_DOMAIN_AUX_B;
5158         case PORT_C:
5159                 return POWER_DOMAIN_AUX_C;
5160         case PORT_D:
5161                 return POWER_DOMAIN_AUX_D;
5162         case PORT_E:
5163                 /* FIXME: Check VBT for actual wiring of PORT E */
5164                 return POWER_DOMAIN_AUX_D;
5165         default:
5166                 MISSING_CASE(port);
5167                 return POWER_DOMAIN_AUX_A;
5168         }
5169 }
5170
5171 enum intel_display_power_domain
5172 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5173 {
5174         struct drm_device *dev = intel_encoder->base.dev;
5175         struct intel_digital_port *intel_dig_port;
5176
5177         switch (intel_encoder->type) {
5178         case INTEL_OUTPUT_UNKNOWN:
5179                 /* Only DDI platforms should ever use this output type */
5180                 WARN_ON_ONCE(!HAS_DDI(dev));
5181         case INTEL_OUTPUT_DISPLAYPORT:
5182         case INTEL_OUTPUT_HDMI:
5183         case INTEL_OUTPUT_EDP:
5184                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5185                 return port_to_power_domain(intel_dig_port->port);
5186         case INTEL_OUTPUT_DP_MST:
5187                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5188                 return port_to_power_domain(intel_dig_port->port);
5189         case INTEL_OUTPUT_ANALOG:
5190                 return POWER_DOMAIN_PORT_CRT;
5191         case INTEL_OUTPUT_DSI:
5192                 return POWER_DOMAIN_PORT_DSI;
5193         default:
5194                 return POWER_DOMAIN_PORT_OTHER;
5195         }
5196 }
5197
5198 enum intel_display_power_domain
5199 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
5200 {
5201         struct drm_device *dev = intel_encoder->base.dev;
5202         struct intel_digital_port *intel_dig_port;
5203
5204         switch (intel_encoder->type) {
5205         case INTEL_OUTPUT_UNKNOWN:
5206         case INTEL_OUTPUT_HDMI:
5207                 /*
5208                  * Only DDI platforms should ever use these output types.
5209                  * We can get here after the HDMI detect code has already set
5210                  * the type of the shared encoder. Since we can't be sure
5211                  * what's the status of the given connectors, play safe and
5212                  * run the DP detection too.
5213                  */
5214                 WARN_ON_ONCE(!HAS_DDI(dev));
5215         case INTEL_OUTPUT_DISPLAYPORT:
5216         case INTEL_OUTPUT_EDP:
5217                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5218                 return port_to_aux_power_domain(intel_dig_port->port);
5219         case INTEL_OUTPUT_DP_MST:
5220                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5221                 return port_to_aux_power_domain(intel_dig_port->port);
5222         default:
5223                 MISSING_CASE(intel_encoder->type);
5224                 return POWER_DOMAIN_AUX_A;
5225         }
5226 }
5227
5228 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc,
5229                                             struct intel_crtc_state *crtc_state)
5230 {
5231         struct drm_device *dev = crtc->dev;
5232         struct drm_encoder *encoder;
5233         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5234         enum pipe pipe = intel_crtc->pipe;
5235         unsigned long mask;
5236         enum transcoder transcoder = crtc_state->cpu_transcoder;
5237
5238         if (!crtc_state->base.active)
5239                 return 0;
5240
5241         mask = BIT(POWER_DOMAIN_PIPE(pipe));
5242         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5243         if (crtc_state->pch_pfit.enabled ||
5244             crtc_state->pch_pfit.force_thru)
5245                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5246
5247         drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5248                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5249
5250                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5251         }
5252
5253         return mask;
5254 }
5255
5256 static unsigned long
5257 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5258                                struct intel_crtc_state *crtc_state)
5259 {
5260         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5261         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5262         enum intel_display_power_domain domain;
5263         unsigned long domains, new_domains, old_domains;
5264
5265         old_domains = intel_crtc->enabled_power_domains;
5266         intel_crtc->enabled_power_domains = new_domains =
5267                 get_crtc_power_domains(crtc, crtc_state);
5268
5269         domains = new_domains & ~old_domains;
5270
5271         for_each_power_domain(domain, domains)
5272                 intel_display_power_get(dev_priv, domain);
5273
5274         return old_domains & ~new_domains;
5275 }
5276
5277 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5278                                       unsigned long domains)
5279 {
5280         enum intel_display_power_domain domain;
5281
5282         for_each_power_domain(domain, domains)
5283                 intel_display_power_put(dev_priv, domain);
5284 }
5285
5286 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5287 {
5288         int max_cdclk_freq = dev_priv->max_cdclk_freq;
5289
5290         if (INTEL_INFO(dev_priv)->gen >= 9 ||
5291             IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5292                 return max_cdclk_freq;
5293         else if (IS_CHERRYVIEW(dev_priv))
5294                 return max_cdclk_freq*95/100;
5295         else if (INTEL_INFO(dev_priv)->gen < 4)
5296                 return 2*max_cdclk_freq*90/100;
5297         else
5298                 return max_cdclk_freq*90/100;
5299 }
5300
5301 static void intel_update_max_cdclk(struct drm_device *dev)
5302 {
5303         struct drm_i915_private *dev_priv = dev->dev_private;
5304
5305         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
5306                 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5307
5308                 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5309                         dev_priv->max_cdclk_freq = 675000;
5310                 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5311                         dev_priv->max_cdclk_freq = 540000;
5312                 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5313                         dev_priv->max_cdclk_freq = 450000;
5314                 else
5315                         dev_priv->max_cdclk_freq = 337500;
5316         } else if (IS_BROADWELL(dev))  {
5317                 /*
5318                  * FIXME with extra cooling we can allow
5319                  * 540 MHz for ULX and 675 Mhz for ULT.
5320                  * How can we know if extra cooling is
5321                  * available? PCI ID, VTB, something else?
5322                  */
5323                 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5324                         dev_priv->max_cdclk_freq = 450000;
5325                 else if (IS_BDW_ULX(dev))
5326                         dev_priv->max_cdclk_freq = 450000;
5327                 else if (IS_BDW_ULT(dev))
5328                         dev_priv->max_cdclk_freq = 540000;
5329                 else
5330                         dev_priv->max_cdclk_freq = 675000;
5331         } else if (IS_CHERRYVIEW(dev)) {
5332                 dev_priv->max_cdclk_freq = 320000;
5333         } else if (IS_VALLEYVIEW(dev)) {
5334                 dev_priv->max_cdclk_freq = 400000;
5335         } else {
5336                 /* otherwise assume cdclk is fixed */
5337                 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5338         }
5339
5340         dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5341
5342         DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5343                          dev_priv->max_cdclk_freq);
5344
5345         DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5346                          dev_priv->max_dotclk_freq);
5347 }
5348
5349 static void intel_update_cdclk(struct drm_device *dev)
5350 {
5351         struct drm_i915_private *dev_priv = dev->dev_private;
5352
5353         dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5354         DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5355                          dev_priv->cdclk_freq);
5356
5357         /*
5358          * Program the gmbus_freq based on the cdclk frequency.
5359          * BSpec erroneously claims we should aim for 4MHz, but
5360          * in fact 1MHz is the correct frequency.
5361          */
5362         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
5363                 /*
5364                  * Program the gmbus_freq based on the cdclk frequency.
5365                  * BSpec erroneously claims we should aim for 4MHz, but
5366                  * in fact 1MHz is the correct frequency.
5367                  */
5368                 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5369         }
5370
5371         if (dev_priv->max_cdclk_freq == 0)
5372                 intel_update_max_cdclk(dev);
5373 }
5374
5375 static void broxton_set_cdclk(struct drm_device *dev, int frequency)
5376 {
5377         struct drm_i915_private *dev_priv = dev->dev_private;
5378         uint32_t divider;
5379         uint32_t ratio;
5380         uint32_t current_freq;
5381         int ret;
5382
5383         /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5384         switch (frequency) {
5385         case 144000:
5386                 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5387                 ratio = BXT_DE_PLL_RATIO(60);
5388                 break;
5389         case 288000:
5390                 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5391                 ratio = BXT_DE_PLL_RATIO(60);
5392                 break;
5393         case 384000:
5394                 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5395                 ratio = BXT_DE_PLL_RATIO(60);
5396                 break;
5397         case 576000:
5398                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5399                 ratio = BXT_DE_PLL_RATIO(60);
5400                 break;
5401         case 624000:
5402                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5403                 ratio = BXT_DE_PLL_RATIO(65);
5404                 break;
5405         case 19200:
5406                 /*
5407                  * Bypass frequency with DE PLL disabled. Init ratio, divider
5408                  * to suppress GCC warning.
5409                  */
5410                 ratio = 0;
5411                 divider = 0;
5412                 break;
5413         default:
5414                 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5415
5416                 return;
5417         }
5418
5419         mutex_lock(&dev_priv->rps.hw_lock);
5420         /* Inform power controller of upcoming frequency change */
5421         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5422                                       0x80000000);
5423         mutex_unlock(&dev_priv->rps.hw_lock);
5424
5425         if (ret) {
5426                 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5427                           ret, frequency);
5428                 return;
5429         }
5430
5431         current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5432         /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5433         current_freq = current_freq * 500 + 1000;
5434
5435         /*
5436          * DE PLL has to be disabled when
5437          * - setting to 19.2MHz (bypass, PLL isn't used)
5438          * - before setting to 624MHz (PLL needs toggling)
5439          * - before setting to any frequency from 624MHz (PLL needs toggling)
5440          */
5441         if (frequency == 19200 || frequency == 624000 ||
5442             current_freq == 624000) {
5443                 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5444                 /* Timeout 200us */
5445                 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5446                              1))
5447                         DRM_ERROR("timout waiting for DE PLL unlock\n");
5448         }
5449
5450         if (frequency != 19200) {
5451                 uint32_t val;
5452
5453                 val = I915_READ(BXT_DE_PLL_CTL);
5454                 val &= ~BXT_DE_PLL_RATIO_MASK;
5455                 val |= ratio;
5456                 I915_WRITE(BXT_DE_PLL_CTL, val);
5457
5458                 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5459                 /* Timeout 200us */
5460                 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5461                         DRM_ERROR("timeout waiting for DE PLL lock\n");
5462
5463                 val = I915_READ(CDCLK_CTL);
5464                 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5465                 val |= divider;
5466                 /*
5467                  * Disable SSA Precharge when CD clock frequency < 500 MHz,
5468                  * enable otherwise.
5469                  */
5470                 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5471                 if (frequency >= 500000)
5472                         val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5473
5474                 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5475                 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5476                 val |= (frequency - 1000) / 500;
5477                 I915_WRITE(CDCLK_CTL, val);
5478         }
5479
5480         mutex_lock(&dev_priv->rps.hw_lock);
5481         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5482                                       DIV_ROUND_UP(frequency, 25000));
5483         mutex_unlock(&dev_priv->rps.hw_lock);
5484
5485         if (ret) {
5486                 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5487                           ret, frequency);
5488                 return;
5489         }
5490
5491         intel_update_cdclk(dev);
5492 }
5493
5494 void broxton_init_cdclk(struct drm_device *dev)
5495 {
5496         struct drm_i915_private *dev_priv = dev->dev_private;
5497         uint32_t val;
5498
5499         /*
5500          * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5501          * or else the reset will hang because there is no PCH to respond.
5502          * Move the handshake programming to initialization sequence.
5503          * Previously was left up to BIOS.
5504          */
5505         val = I915_READ(HSW_NDE_RSTWRN_OPT);
5506         val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5507         I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5508
5509         /* Enable PG1 for cdclk */
5510         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5511
5512         /* check if cd clock is enabled */
5513         if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5514                 DRM_DEBUG_KMS("Display already initialized\n");
5515                 return;
5516         }
5517
5518         /*
5519          * FIXME:
5520          * - The initial CDCLK needs to be read from VBT.
5521          *   Need to make this change after VBT has changes for BXT.
5522          * - check if setting the max (or any) cdclk freq is really necessary
5523          *   here, it belongs to modeset time
5524          */
5525         broxton_set_cdclk(dev, 624000);
5526
5527         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5528         POSTING_READ(DBUF_CTL);
5529
5530         udelay(10);
5531
5532         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5533                 DRM_ERROR("DBuf power enable timeout!\n");
5534 }
5535
5536 void broxton_uninit_cdclk(struct drm_device *dev)
5537 {
5538         struct drm_i915_private *dev_priv = dev->dev_private;
5539
5540         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5541         POSTING_READ(DBUF_CTL);
5542
5543         udelay(10);
5544
5545         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5546                 DRM_ERROR("DBuf power disable timeout!\n");
5547
5548         /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5549         broxton_set_cdclk(dev, 19200);
5550
5551         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5552 }
5553
5554 static const struct skl_cdclk_entry {
5555         unsigned int freq;
5556         unsigned int vco;
5557 } skl_cdclk_frequencies[] = {
5558         { .freq = 308570, .vco = 8640 },
5559         { .freq = 337500, .vco = 8100 },
5560         { .freq = 432000, .vco = 8640 },
5561         { .freq = 450000, .vco = 8100 },
5562         { .freq = 540000, .vco = 8100 },
5563         { .freq = 617140, .vco = 8640 },
5564         { .freq = 675000, .vco = 8100 },
5565 };
5566
5567 static unsigned int skl_cdclk_decimal(unsigned int freq)
5568 {
5569         return (freq - 1000) / 500;
5570 }
5571
5572 static unsigned int skl_cdclk_get_vco(unsigned int freq)
5573 {
5574         unsigned int i;
5575
5576         for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5577                 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5578
5579                 if (e->freq == freq)
5580                         return e->vco;
5581         }
5582
5583         return 8100;
5584 }
5585
5586 static void
5587 skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5588 {
5589         unsigned int min_freq;
5590         u32 val;
5591
5592         /* select the minimum CDCLK before enabling DPLL 0 */
5593         val = I915_READ(CDCLK_CTL);
5594         val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5595         val |= CDCLK_FREQ_337_308;
5596
5597         if (required_vco == 8640)
5598                 min_freq = 308570;
5599         else
5600                 min_freq = 337500;
5601
5602         val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5603
5604         I915_WRITE(CDCLK_CTL, val);
5605         POSTING_READ(CDCLK_CTL);
5606
5607         /*
5608          * We always enable DPLL0 with the lowest link rate possible, but still
5609          * taking into account the VCO required to operate the eDP panel at the
5610          * desired frequency. The usual DP link rates operate with a VCO of
5611          * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5612          * The modeset code is responsible for the selection of the exact link
5613          * rate later on, with the constraint of choosing a frequency that
5614          * works with required_vco.
5615          */
5616         val = I915_READ(DPLL_CTRL1);
5617
5618         val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5619                  DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5620         val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5621         if (required_vco == 8640)
5622                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5623                                             SKL_DPLL0);
5624         else
5625                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5626                                             SKL_DPLL0);
5627
5628         I915_WRITE(DPLL_CTRL1, val);
5629         POSTING_READ(DPLL_CTRL1);
5630
5631         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5632
5633         if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5634                 DRM_ERROR("DPLL0 not locked\n");
5635 }
5636
5637 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5638 {
5639         int ret;
5640         u32 val;
5641
5642         /* inform PCU we want to change CDCLK */
5643         val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5644         mutex_lock(&dev_priv->rps.hw_lock);
5645         ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5646         mutex_unlock(&dev_priv->rps.hw_lock);
5647
5648         return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5649 }
5650
5651 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5652 {
5653         unsigned int i;
5654
5655         for (i = 0; i < 15; i++) {
5656                 if (skl_cdclk_pcu_ready(dev_priv))
5657                         return true;
5658                 udelay(10);
5659         }
5660
5661         return false;
5662 }
5663
5664 static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5665 {
5666         struct drm_device *dev = dev_priv->dev;
5667         u32 freq_select, pcu_ack;
5668
5669         DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5670
5671         if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5672                 DRM_ERROR("failed to inform PCU about cdclk change\n");
5673                 return;
5674         }
5675
5676         /* set CDCLK_CTL */
5677         switch(freq) {
5678         case 450000:
5679         case 432000:
5680                 freq_select = CDCLK_FREQ_450_432;
5681                 pcu_ack = 1;
5682                 break;
5683         case 540000:
5684                 freq_select = CDCLK_FREQ_540;
5685                 pcu_ack = 2;
5686                 break;
5687         case 308570:
5688         case 337500:
5689         default:
5690                 freq_select = CDCLK_FREQ_337_308;
5691                 pcu_ack = 0;
5692                 break;
5693         case 617140:
5694         case 675000:
5695                 freq_select = CDCLK_FREQ_675_617;
5696                 pcu_ack = 3;
5697                 break;
5698         }
5699
5700         I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5701         POSTING_READ(CDCLK_CTL);
5702
5703         /* inform PCU of the change */
5704         mutex_lock(&dev_priv->rps.hw_lock);
5705         sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5706         mutex_unlock(&dev_priv->rps.hw_lock);
5707
5708         intel_update_cdclk(dev);
5709 }
5710
5711 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5712 {
5713         /* disable DBUF power */
5714         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5715         POSTING_READ(DBUF_CTL);
5716
5717         udelay(10);
5718
5719         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5720                 DRM_ERROR("DBuf power disable timeout\n");
5721
5722         /* disable DPLL0 */
5723         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5724         if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5725                 DRM_ERROR("Couldn't disable DPLL0\n");
5726 }
5727
5728 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5729 {
5730         unsigned int required_vco;
5731
5732         /* DPLL0 not enabled (happens on early BIOS versions) */
5733         if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
5734                 /* enable DPLL0 */
5735                 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5736                 skl_dpll0_enable(dev_priv, required_vco);
5737         }
5738
5739         /* set CDCLK to the frequency the BIOS chose */
5740         skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5741
5742         /* enable DBUF power */
5743         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5744         POSTING_READ(DBUF_CTL);
5745
5746         udelay(10);
5747
5748         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5749                 DRM_ERROR("DBuf power enable timeout\n");
5750 }
5751
5752 int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
5753 {
5754         uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
5755         uint32_t cdctl = I915_READ(CDCLK_CTL);
5756         int freq = dev_priv->skl_boot_cdclk;
5757
5758         /*
5759          * check if the pre-os intialized the display
5760          * There is SWF18 scratchpad register defined which is set by the
5761          * pre-os which can be used by the OS drivers to check the status
5762          */
5763         if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
5764                 goto sanitize;
5765
5766         /* Is PLL enabled and locked ? */
5767         if (!((lcpll1 & LCPLL_PLL_ENABLE) && (lcpll1 & LCPLL_PLL_LOCK)))
5768                 goto sanitize;
5769
5770         /* DPLL okay; verify the cdclock
5771          *
5772          * Noticed in some instances that the freq selection is correct but
5773          * decimal part is programmed wrong from BIOS where pre-os does not
5774          * enable display. Verify the same as well.
5775          */
5776         if (cdctl == ((cdctl & CDCLK_FREQ_SEL_MASK) | skl_cdclk_decimal(freq)))
5777                 /* All well; nothing to sanitize */
5778                 return false;
5779 sanitize:
5780         /*
5781          * As of now initialize with max cdclk till
5782          * we get dynamic cdclk support
5783          * */
5784         dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq;
5785         skl_init_cdclk(dev_priv);
5786
5787         /* we did have to sanitize */
5788         return true;
5789 }
5790
5791 /* Adjust CDclk dividers to allow high res or save power if possible */
5792 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5793 {
5794         struct drm_i915_private *dev_priv = dev->dev_private;
5795         u32 val, cmd;
5796
5797         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5798                                         != dev_priv->cdclk_freq);
5799
5800         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5801                 cmd = 2;
5802         else if (cdclk == 266667)
5803                 cmd = 1;
5804         else
5805                 cmd = 0;
5806
5807         mutex_lock(&dev_priv->rps.hw_lock);
5808         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5809         val &= ~DSPFREQGUAR_MASK;
5810         val |= (cmd << DSPFREQGUAR_SHIFT);
5811         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5812         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5813                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5814                      50)) {
5815                 DRM_ERROR("timed out waiting for CDclk change\n");
5816         }
5817         mutex_unlock(&dev_priv->rps.hw_lock);
5818
5819         mutex_lock(&dev_priv->sb_lock);
5820
5821         if (cdclk == 400000) {
5822                 u32 divider;
5823
5824                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5825
5826                 /* adjust cdclk divider */
5827                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5828                 val &= ~CCK_FREQUENCY_VALUES;
5829                 val |= divider;
5830                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5831
5832                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5833                               CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
5834                              50))
5835                         DRM_ERROR("timed out waiting for CDclk change\n");
5836         }
5837
5838         /* adjust self-refresh exit latency value */
5839         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5840         val &= ~0x7f;
5841
5842         /*
5843          * For high bandwidth configs, we set a higher latency in the bunit
5844          * so that the core display fetch happens in time to avoid underruns.
5845          */
5846         if (cdclk == 400000)
5847                 val |= 4500 / 250; /* 4.5 usec */
5848         else
5849                 val |= 3000 / 250; /* 3.0 usec */
5850         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5851
5852         mutex_unlock(&dev_priv->sb_lock);
5853
5854         intel_update_cdclk(dev);
5855 }
5856
5857 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5858 {
5859         struct drm_i915_private *dev_priv = dev->dev_private;
5860         u32 val, cmd;
5861
5862         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5863                                                 != dev_priv->cdclk_freq);
5864
5865         switch (cdclk) {
5866         case 333333:
5867         case 320000:
5868         case 266667:
5869         case 200000:
5870                 break;
5871         default:
5872                 MISSING_CASE(cdclk);
5873                 return;
5874         }
5875
5876         /*
5877          * Specs are full of misinformation, but testing on actual
5878          * hardware has shown that we just need to write the desired
5879          * CCK divider into the Punit register.
5880          */
5881         cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5882
5883         mutex_lock(&dev_priv->rps.hw_lock);
5884         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5885         val &= ~DSPFREQGUAR_MASK_CHV;
5886         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5887         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5888         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5889                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5890                      50)) {
5891                 DRM_ERROR("timed out waiting for CDclk change\n");
5892         }
5893         mutex_unlock(&dev_priv->rps.hw_lock);
5894
5895         intel_update_cdclk(dev);
5896 }
5897
5898 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5899                                  int max_pixclk)
5900 {
5901         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
5902         int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5903
5904         /*
5905          * Really only a few cases to deal with, as only 4 CDclks are supported:
5906          *   200MHz
5907          *   267MHz
5908          *   320/333MHz (depends on HPLL freq)
5909          *   400MHz (VLV only)
5910          * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5911          * of the lower bin and adjust if needed.
5912          *
5913          * We seem to get an unstable or solid color picture at 200MHz.
5914          * Not sure what's wrong. For now use 200MHz only when all pipes
5915          * are off.
5916          */
5917         if (!IS_CHERRYVIEW(dev_priv) &&
5918             max_pixclk > freq_320*limit/100)
5919                 return 400000;
5920         else if (max_pixclk > 266667*limit/100)
5921                 return freq_320;
5922         else if (max_pixclk > 0)
5923                 return 266667;
5924         else
5925                 return 200000;
5926 }
5927
5928 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5929                               int max_pixclk)
5930 {
5931         /*
5932          * FIXME:
5933          * - remove the guardband, it's not needed on BXT
5934          * - set 19.2MHz bypass frequency if there are no active pipes
5935          */
5936         if (max_pixclk > 576000*9/10)
5937                 return 624000;
5938         else if (max_pixclk > 384000*9/10)
5939                 return 576000;
5940         else if (max_pixclk > 288000*9/10)
5941                 return 384000;
5942         else if (max_pixclk > 144000*9/10)
5943                 return 288000;
5944         else
5945                 return 144000;
5946 }
5947
5948 /* Compute the max pixel clock for new configuration. */
5949 static int intel_mode_max_pixclk(struct drm_device *dev,
5950                                  struct drm_atomic_state *state)
5951 {
5952         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
5953         struct drm_i915_private *dev_priv = dev->dev_private;
5954         struct drm_crtc *crtc;
5955         struct drm_crtc_state *crtc_state;
5956         unsigned max_pixclk = 0, i;
5957         enum pipe pipe;
5958
5959         memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
5960                sizeof(intel_state->min_pixclk));
5961
5962         for_each_crtc_in_state(state, crtc, crtc_state, i) {
5963                 int pixclk = 0;
5964
5965                 if (crtc_state->enable)
5966                         pixclk = crtc_state->adjusted_mode.crtc_clock;
5967
5968                 intel_state->min_pixclk[i] = pixclk;
5969         }
5970
5971         for_each_pipe(dev_priv, pipe)
5972                 max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk);
5973
5974         return max_pixclk;
5975 }
5976
5977 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
5978 {
5979         struct drm_device *dev = state->dev;
5980         struct drm_i915_private *dev_priv = dev->dev_private;
5981         int max_pixclk = intel_mode_max_pixclk(dev, state);
5982         struct intel_atomic_state *intel_state =
5983                 to_intel_atomic_state(state);
5984
5985         if (max_pixclk < 0)
5986                 return max_pixclk;
5987
5988         intel_state->cdclk = intel_state->dev_cdclk =
5989                 valleyview_calc_cdclk(dev_priv, max_pixclk);
5990
5991         if (!intel_state->active_crtcs)
5992                 intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0);
5993
5994         return 0;
5995 }
5996
5997 static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
5998 {
5999         struct drm_device *dev = state->dev;
6000         struct drm_i915_private *dev_priv = dev->dev_private;
6001         int max_pixclk = intel_mode_max_pixclk(dev, state);
6002         struct intel_atomic_state *intel_state =
6003                 to_intel_atomic_state(state);
6004
6005         if (max_pixclk < 0)
6006                 return max_pixclk;
6007
6008         intel_state->cdclk = intel_state->dev_cdclk =
6009                 broxton_calc_cdclk(dev_priv, max_pixclk);
6010
6011         if (!intel_state->active_crtcs)
6012                 intel_state->dev_cdclk = broxton_calc_cdclk(dev_priv, 0);
6013
6014         return 0;
6015 }
6016
6017 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
6018 {
6019         unsigned int credits, default_credits;
6020
6021         if (IS_CHERRYVIEW(dev_priv))
6022                 default_credits = PFI_CREDIT(12);
6023         else
6024                 default_credits = PFI_CREDIT(8);
6025
6026         if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
6027                 /* CHV suggested value is 31 or 63 */
6028                 if (IS_CHERRYVIEW(dev_priv))
6029                         credits = PFI_CREDIT_63;
6030                 else
6031                         credits = PFI_CREDIT(15);
6032         } else {
6033                 credits = default_credits;
6034         }
6035
6036         /*
6037          * WA - write default credits before re-programming
6038          * FIXME: should we also set the resend bit here?
6039          */
6040         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6041                    default_credits);
6042
6043         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6044                    credits | PFI_CREDIT_RESEND);
6045
6046         /*
6047          * FIXME is this guaranteed to clear
6048          * immediately or should we poll for it?
6049          */
6050         WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6051 }
6052
6053 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6054 {
6055         struct drm_device *dev = old_state->dev;
6056         struct drm_i915_private *dev_priv = dev->dev_private;
6057         struct intel_atomic_state *old_intel_state =
6058                 to_intel_atomic_state(old_state);
6059         unsigned req_cdclk = old_intel_state->dev_cdclk;
6060
6061         /*
6062          * FIXME: We can end up here with all power domains off, yet
6063          * with a CDCLK frequency other than the minimum. To account
6064          * for this take the PIPE-A power domain, which covers the HW
6065          * blocks needed for the following programming. This can be
6066          * removed once it's guaranteed that we get here either with
6067          * the minimum CDCLK set, or the required power domains
6068          * enabled.
6069          */
6070         intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6071
6072         if (IS_CHERRYVIEW(dev))
6073                 cherryview_set_cdclk(dev, req_cdclk);
6074         else
6075                 valleyview_set_cdclk(dev, req_cdclk);
6076
6077         vlv_program_pfi_credits(dev_priv);
6078
6079         intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6080 }
6081
6082 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6083 {
6084         struct drm_device *dev = crtc->dev;
6085         struct drm_i915_private *dev_priv = to_i915(dev);
6086         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6087         struct intel_encoder *encoder;
6088         int pipe = intel_crtc->pipe;
6089
6090         if (WARN_ON(intel_crtc->active))
6091                 return;
6092
6093         if (intel_crtc->config->has_dp_encoder)
6094                 intel_dp_set_m_n(intel_crtc, M1_N1);
6095
6096         intel_set_pipe_timings(intel_crtc);
6097
6098         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6099                 struct drm_i915_private *dev_priv = dev->dev_private;
6100
6101                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6102                 I915_WRITE(CHV_CANVAS(pipe), 0);
6103         }
6104
6105         i9xx_set_pipeconf(intel_crtc);
6106
6107         intel_crtc->active = true;
6108
6109         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6110
6111         for_each_encoder_on_crtc(dev, crtc, encoder)
6112                 if (encoder->pre_pll_enable)
6113                         encoder->pre_pll_enable(encoder);
6114
6115         if (!intel_crtc->config->has_dsi_encoder) {
6116                 if (IS_CHERRYVIEW(dev)) {
6117                         chv_prepare_pll(intel_crtc, intel_crtc->config);
6118                         chv_enable_pll(intel_crtc, intel_crtc->config);
6119                 } else {
6120                         vlv_prepare_pll(intel_crtc, intel_crtc->config);
6121                         vlv_enable_pll(intel_crtc, intel_crtc->config);
6122                 }
6123         }
6124
6125         for_each_encoder_on_crtc(dev, crtc, encoder)
6126                 if (encoder->pre_enable)
6127                         encoder->pre_enable(encoder);
6128
6129         i9xx_pfit_enable(intel_crtc);
6130
6131         intel_crtc_load_lut(crtc);
6132
6133         intel_update_watermarks(crtc);
6134         intel_enable_pipe(intel_crtc);
6135
6136         assert_vblank_disabled(crtc);
6137         drm_crtc_vblank_on(crtc);
6138
6139         for_each_encoder_on_crtc(dev, crtc, encoder)
6140                 encoder->enable(encoder);
6141 }
6142
6143 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6144 {
6145         struct drm_device *dev = crtc->base.dev;
6146         struct drm_i915_private *dev_priv = dev->dev_private;
6147
6148         I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6149         I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6150 }
6151
6152 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6153 {
6154         struct drm_device *dev = crtc->dev;
6155         struct drm_i915_private *dev_priv = to_i915(dev);
6156         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6157         struct intel_encoder *encoder;
6158         int pipe = intel_crtc->pipe;
6159
6160         if (WARN_ON(intel_crtc->active))
6161                 return;
6162
6163         i9xx_set_pll_dividers(intel_crtc);
6164
6165         if (intel_crtc->config->has_dp_encoder)
6166                 intel_dp_set_m_n(intel_crtc, M1_N1);
6167
6168         intel_set_pipe_timings(intel_crtc);
6169
6170         i9xx_set_pipeconf(intel_crtc);
6171
6172         intel_crtc->active = true;
6173
6174         if (!IS_GEN2(dev))
6175                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6176
6177         for_each_encoder_on_crtc(dev, crtc, encoder)
6178                 if (encoder->pre_enable)
6179                         encoder->pre_enable(encoder);
6180
6181         i9xx_enable_pll(intel_crtc);
6182
6183         i9xx_pfit_enable(intel_crtc);
6184
6185         intel_crtc_load_lut(crtc);
6186
6187         intel_update_watermarks(crtc);
6188         intel_enable_pipe(intel_crtc);
6189
6190         assert_vblank_disabled(crtc);
6191         drm_crtc_vblank_on(crtc);
6192
6193         for_each_encoder_on_crtc(dev, crtc, encoder)
6194                 encoder->enable(encoder);
6195 }
6196
6197 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6198 {
6199         struct drm_device *dev = crtc->base.dev;
6200         struct drm_i915_private *dev_priv = dev->dev_private;
6201
6202         if (!crtc->config->gmch_pfit.control)
6203                 return;
6204
6205         assert_pipe_disabled(dev_priv, crtc->pipe);
6206
6207         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6208                          I915_READ(PFIT_CONTROL));
6209         I915_WRITE(PFIT_CONTROL, 0);
6210 }
6211
6212 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6213 {
6214         struct drm_device *dev = crtc->dev;
6215         struct drm_i915_private *dev_priv = dev->dev_private;
6216         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6217         struct intel_encoder *encoder;
6218         int pipe = intel_crtc->pipe;
6219
6220         /*
6221          * On gen2 planes are double buffered but the pipe isn't, so we must
6222          * wait for planes to fully turn off before disabling the pipe.
6223          * We also need to wait on all gmch platforms because of the
6224          * self-refresh mode constraint explained above.
6225          */
6226         intel_wait_for_vblank(dev, pipe);
6227
6228         for_each_encoder_on_crtc(dev, crtc, encoder)
6229                 encoder->disable(encoder);
6230
6231         drm_crtc_vblank_off(crtc);
6232         assert_vblank_disabled(crtc);
6233
6234         intel_disable_pipe(intel_crtc);
6235
6236         i9xx_pfit_disable(intel_crtc);
6237
6238         for_each_encoder_on_crtc(dev, crtc, encoder)
6239                 if (encoder->post_disable)
6240                         encoder->post_disable(encoder);
6241
6242         if (!intel_crtc->config->has_dsi_encoder) {
6243                 if (IS_CHERRYVIEW(dev))
6244                         chv_disable_pll(dev_priv, pipe);
6245                 else if (IS_VALLEYVIEW(dev))
6246                         vlv_disable_pll(dev_priv, pipe);
6247                 else
6248                         i9xx_disable_pll(intel_crtc);
6249         }
6250
6251         for_each_encoder_on_crtc(dev, crtc, encoder)
6252                 if (encoder->post_pll_disable)
6253                         encoder->post_pll_disable(encoder);
6254
6255         if (!IS_GEN2(dev))
6256                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6257 }
6258
6259 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6260 {
6261         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6262         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6263         enum intel_display_power_domain domain;
6264         unsigned long domains;
6265
6266         if (!intel_crtc->active)
6267                 return;
6268
6269         if (to_intel_plane_state(crtc->primary->state)->visible) {
6270                 WARN_ON(intel_crtc->unpin_work);
6271
6272                 intel_pre_disable_primary(crtc);
6273
6274                 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
6275                 to_intel_plane_state(crtc->primary->state)->visible = false;
6276         }
6277
6278         dev_priv->display.crtc_disable(crtc);
6279         intel_crtc->active = false;
6280         intel_fbc_disable(intel_crtc);
6281         intel_update_watermarks(crtc);
6282         intel_disable_shared_dpll(intel_crtc);
6283
6284         domains = intel_crtc->enabled_power_domains;
6285         for_each_power_domain(domain, domains)
6286                 intel_display_power_put(dev_priv, domain);
6287         intel_crtc->enabled_power_domains = 0;
6288
6289         dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
6290         dev_priv->min_pixclk[intel_crtc->pipe] = 0;
6291 }
6292
6293 /*
6294  * turn all crtc's off, but do not adjust state
6295  * This has to be paired with a call to intel_modeset_setup_hw_state.
6296  */
6297 int intel_display_suspend(struct drm_device *dev)
6298 {
6299         struct drm_i915_private *dev_priv = to_i915(dev);
6300         struct drm_atomic_state *state;
6301         int ret;
6302
6303         state = drm_atomic_helper_suspend(dev);
6304         ret = PTR_ERR_OR_ZERO(state);
6305         if (ret)
6306                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6307         else
6308                 dev_priv->modeset_restore_state = state;
6309         return ret;
6310 }
6311
6312 void intel_encoder_destroy(struct drm_encoder *encoder)
6313 {
6314         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6315
6316         drm_encoder_cleanup(encoder);
6317         kfree(intel_encoder);
6318 }
6319
6320 /* Cross check the actual hw state with our own modeset state tracking (and it's
6321  * internal consistency). */
6322 static void intel_connector_check_state(struct intel_connector *connector)
6323 {
6324         struct drm_crtc *crtc = connector->base.state->crtc;
6325
6326         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6327                       connector->base.base.id,
6328                       connector->base.name);
6329
6330         if (connector->get_hw_state(connector)) {
6331                 struct intel_encoder *encoder = connector->encoder;
6332                 struct drm_connector_state *conn_state = connector->base.state;
6333
6334                 I915_STATE_WARN(!crtc,
6335                          "connector enabled without attached crtc\n");
6336
6337                 if (!crtc)
6338                         return;
6339
6340                 I915_STATE_WARN(!crtc->state->active,
6341                       "connector is active, but attached crtc isn't\n");
6342
6343                 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6344                         return;
6345
6346                 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6347                         "atomic encoder doesn't match attached encoder\n");
6348
6349                 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6350                         "attached encoder crtc differs from connector crtc\n");
6351         } else {
6352                 I915_STATE_WARN(crtc && crtc->state->active,
6353                         "attached crtc is active, but connector isn't\n");
6354                 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6355                         "best encoder set without crtc!\n");
6356         }
6357 }
6358
6359 int intel_connector_init(struct intel_connector *connector)
6360 {
6361         drm_atomic_helper_connector_reset(&connector->base);
6362
6363         if (!connector->base.state)
6364                 return -ENOMEM;
6365
6366         return 0;
6367 }
6368
6369 struct intel_connector *intel_connector_alloc(void)
6370 {
6371         struct intel_connector *connector;
6372
6373         connector = kzalloc(sizeof *connector, GFP_KERNEL);
6374         if (!connector)
6375                 return NULL;
6376
6377         if (intel_connector_init(connector) < 0) {
6378                 kfree(connector);
6379                 return NULL;
6380         }
6381
6382         return connector;
6383 }
6384
6385 /* Simple connector->get_hw_state implementation for encoders that support only
6386  * one connector and no cloning and hence the encoder state determines the state
6387  * of the connector. */
6388 bool intel_connector_get_hw_state(struct intel_connector *connector)
6389 {
6390         enum pipe pipe = 0;
6391         struct intel_encoder *encoder = connector->encoder;
6392
6393         return encoder->get_hw_state(encoder, &pipe);
6394 }
6395
6396 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6397 {
6398         if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6399                 return crtc_state->fdi_lanes;
6400
6401         return 0;
6402 }
6403
6404 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6405                                      struct intel_crtc_state *pipe_config)
6406 {
6407         struct drm_atomic_state *state = pipe_config->base.state;
6408         struct intel_crtc *other_crtc;
6409         struct intel_crtc_state *other_crtc_state;
6410
6411         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6412                       pipe_name(pipe), pipe_config->fdi_lanes);
6413         if (pipe_config->fdi_lanes > 4) {
6414                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6415                               pipe_name(pipe), pipe_config->fdi_lanes);
6416                 return -EINVAL;
6417         }
6418
6419         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6420                 if (pipe_config->fdi_lanes > 2) {
6421                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6422                                       pipe_config->fdi_lanes);
6423                         return -EINVAL;
6424                 } else {
6425                         return 0;
6426                 }
6427         }
6428
6429         if (INTEL_INFO(dev)->num_pipes == 2)
6430                 return 0;
6431
6432         /* Ivybridge 3 pipe is really complicated */
6433         switch (pipe) {
6434         case PIPE_A:
6435                 return 0;
6436         case PIPE_B:
6437                 if (pipe_config->fdi_lanes <= 2)
6438                         return 0;
6439
6440                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6441                 other_crtc_state =
6442                         intel_atomic_get_crtc_state(state, other_crtc);
6443                 if (IS_ERR(other_crtc_state))
6444                         return PTR_ERR(other_crtc_state);
6445
6446                 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6447                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6448                                       pipe_name(pipe), pipe_config->fdi_lanes);
6449                         return -EINVAL;
6450                 }
6451                 return 0;
6452         case PIPE_C:
6453                 if (pipe_config->fdi_lanes > 2) {
6454                         DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6455                                       pipe_name(pipe), pipe_config->fdi_lanes);
6456                         return -EINVAL;
6457                 }
6458
6459                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6460                 other_crtc_state =
6461                         intel_atomic_get_crtc_state(state, other_crtc);
6462                 if (IS_ERR(other_crtc_state))
6463                         return PTR_ERR(other_crtc_state);
6464
6465                 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6466                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6467                         return -EINVAL;
6468                 }
6469                 return 0;
6470         default:
6471                 BUG();
6472         }
6473 }
6474
6475 #define RETRY 1
6476 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6477                                        struct intel_crtc_state *pipe_config)
6478 {
6479         struct drm_device *dev = intel_crtc->base.dev;
6480         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6481         int lane, link_bw, fdi_dotclock, ret;
6482         bool needs_recompute = false;
6483
6484 retry:
6485         /* FDI is a binary signal running at ~2.7GHz, encoding
6486          * each output octet as 10 bits. The actual frequency
6487          * is stored as a divider into a 100MHz clock, and the
6488          * mode pixel clock is stored in units of 1KHz.
6489          * Hence the bw of each lane in terms of the mode signal
6490          * is:
6491          */
6492         link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
6493
6494         fdi_dotclock = adjusted_mode->crtc_clock;
6495
6496         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6497                                            pipe_config->pipe_bpp);
6498
6499         pipe_config->fdi_lanes = lane;
6500
6501         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6502                                link_bw, &pipe_config->fdi_m_n);
6503
6504         ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
6505         if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6506                 pipe_config->pipe_bpp -= 2*3;
6507                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6508                               pipe_config->pipe_bpp);
6509                 needs_recompute = true;
6510                 pipe_config->bw_constrained = true;
6511
6512                 goto retry;
6513         }
6514
6515         if (needs_recompute)
6516                 return RETRY;
6517
6518         return ret;
6519 }
6520
6521 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6522                                      struct intel_crtc_state *pipe_config)
6523 {
6524         if (pipe_config->pipe_bpp > 24)
6525                 return false;
6526
6527         /* HSW can handle pixel rate up to cdclk? */
6528         if (IS_HASWELL(dev_priv->dev))
6529                 return true;
6530
6531         /*
6532          * We compare against max which means we must take
6533          * the increased cdclk requirement into account when
6534          * calculating the new cdclk.
6535          *
6536          * Should measure whether using a lower cdclk w/o IPS
6537          */
6538         return ilk_pipe_pixel_rate(pipe_config) <=
6539                 dev_priv->max_cdclk_freq * 95 / 100;
6540 }
6541
6542 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6543                                    struct intel_crtc_state *pipe_config)
6544 {
6545         struct drm_device *dev = crtc->base.dev;
6546         struct drm_i915_private *dev_priv = dev->dev_private;
6547
6548         pipe_config->ips_enabled = i915.enable_ips &&
6549                 hsw_crtc_supports_ips(crtc) &&
6550                 pipe_config_supports_ips(dev_priv, pipe_config);
6551 }
6552
6553 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6554 {
6555         const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6556
6557         /* GDG double wide on either pipe, otherwise pipe A only */
6558         return INTEL_INFO(dev_priv)->gen < 4 &&
6559                 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6560 }
6561
6562 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6563                                      struct intel_crtc_state *pipe_config)
6564 {
6565         struct drm_device *dev = crtc->base.dev;
6566         struct drm_i915_private *dev_priv = dev->dev_private;
6567         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6568
6569         /* FIXME should check pixel clock limits on all platforms */
6570         if (INTEL_INFO(dev)->gen < 4) {
6571                 int clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6572
6573                 /*
6574                  * Enable double wide mode when the dot clock
6575                  * is > 90% of the (display) core speed.
6576                  */
6577                 if (intel_crtc_supports_double_wide(crtc) &&
6578                     adjusted_mode->crtc_clock > clock_limit) {
6579                         clock_limit *= 2;
6580                         pipe_config->double_wide = true;
6581                 }
6582
6583                 if (adjusted_mode->crtc_clock > clock_limit) {
6584                         DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6585                                       adjusted_mode->crtc_clock, clock_limit,
6586                                       yesno(pipe_config->double_wide));
6587                         return -EINVAL;
6588                 }
6589         }
6590
6591         /*
6592          * Pipe horizontal size must be even in:
6593          * - DVO ganged mode
6594          * - LVDS dual channel mode
6595          * - Double wide pipe
6596          */
6597         if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6598              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6599                 pipe_config->pipe_src_w &= ~1;
6600
6601         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6602          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6603          */
6604         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6605                 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6606                 return -EINVAL;
6607
6608         if (HAS_IPS(dev))
6609                 hsw_compute_ips_config(crtc, pipe_config);
6610
6611         if (pipe_config->has_pch_encoder)
6612                 return ironlake_fdi_compute_config(crtc, pipe_config);
6613
6614         return 0;
6615 }
6616
6617 static int skylake_get_display_clock_speed(struct drm_device *dev)
6618 {
6619         struct drm_i915_private *dev_priv = to_i915(dev);
6620         uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6621         uint32_t cdctl = I915_READ(CDCLK_CTL);
6622         uint32_t linkrate;
6623
6624         if (!(lcpll1 & LCPLL_PLL_ENABLE))
6625                 return 24000; /* 24MHz is the cd freq with NSSC ref */
6626
6627         if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6628                 return 540000;
6629
6630         linkrate = (I915_READ(DPLL_CTRL1) &
6631                     DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6632
6633         if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6634             linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6635                 /* vco 8640 */
6636                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6637                 case CDCLK_FREQ_450_432:
6638                         return 432000;
6639                 case CDCLK_FREQ_337_308:
6640                         return 308570;
6641                 case CDCLK_FREQ_675_617:
6642                         return 617140;
6643                 default:
6644                         WARN(1, "Unknown cd freq selection\n");
6645                 }
6646         } else {
6647                 /* vco 8100 */
6648                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6649                 case CDCLK_FREQ_450_432:
6650                         return 450000;
6651                 case CDCLK_FREQ_337_308:
6652                         return 337500;
6653                 case CDCLK_FREQ_675_617:
6654                         return 675000;
6655                 default:
6656                         WARN(1, "Unknown cd freq selection\n");
6657                 }
6658         }
6659
6660         /* error case, do as if DPLL0 isn't enabled */
6661         return 24000;
6662 }
6663
6664 static int broxton_get_display_clock_speed(struct drm_device *dev)
6665 {
6666         struct drm_i915_private *dev_priv = to_i915(dev);
6667         uint32_t cdctl = I915_READ(CDCLK_CTL);
6668         uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6669         uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6670         int cdclk;
6671
6672         if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6673                 return 19200;
6674
6675         cdclk = 19200 * pll_ratio / 2;
6676
6677         switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6678         case BXT_CDCLK_CD2X_DIV_SEL_1:
6679                 return cdclk;  /* 576MHz or 624MHz */
6680         case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6681                 return cdclk * 2 / 3; /* 384MHz */
6682         case BXT_CDCLK_CD2X_DIV_SEL_2:
6683                 return cdclk / 2; /* 288MHz */
6684         case BXT_CDCLK_CD2X_DIV_SEL_4:
6685                 return cdclk / 4; /* 144MHz */
6686         }
6687
6688         /* error case, do as if DE PLL isn't enabled */
6689         return 19200;
6690 }
6691
6692 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6693 {
6694         struct drm_i915_private *dev_priv = dev->dev_private;
6695         uint32_t lcpll = I915_READ(LCPLL_CTL);
6696         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6697
6698         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6699                 return 800000;
6700         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6701                 return 450000;
6702         else if (freq == LCPLL_CLK_FREQ_450)
6703                 return 450000;
6704         else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6705                 return 540000;
6706         else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6707                 return 337500;
6708         else
6709                 return 675000;
6710 }
6711
6712 static int haswell_get_display_clock_speed(struct drm_device *dev)
6713 {
6714         struct drm_i915_private *dev_priv = dev->dev_private;
6715         uint32_t lcpll = I915_READ(LCPLL_CTL);
6716         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6717
6718         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6719                 return 800000;
6720         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6721                 return 450000;
6722         else if (freq == LCPLL_CLK_FREQ_450)
6723                 return 450000;
6724         else if (IS_HSW_ULT(dev))
6725                 return 337500;
6726         else
6727                 return 540000;
6728 }
6729
6730 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6731 {
6732         return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
6733                                       CCK_DISPLAY_CLOCK_CONTROL);
6734 }
6735
6736 static int ilk_get_display_clock_speed(struct drm_device *dev)
6737 {
6738         return 450000;
6739 }
6740
6741 static int i945_get_display_clock_speed(struct drm_device *dev)
6742 {
6743         return 400000;
6744 }
6745
6746 static int i915_get_display_clock_speed(struct drm_device *dev)
6747 {
6748         return 333333;
6749 }
6750
6751 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6752 {
6753         return 200000;
6754 }
6755
6756 static int pnv_get_display_clock_speed(struct drm_device *dev)
6757 {
6758         u16 gcfgc = 0;
6759
6760         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6761
6762         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6763         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6764                 return 266667;
6765         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6766                 return 333333;
6767         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6768                 return 444444;
6769         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6770                 return 200000;
6771         default:
6772                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6773         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6774                 return 133333;
6775         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6776                 return 166667;
6777         }
6778 }
6779
6780 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6781 {
6782         u16 gcfgc = 0;
6783
6784         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6785
6786         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6787                 return 133333;
6788         else {
6789                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6790                 case GC_DISPLAY_CLOCK_333_MHZ:
6791                         return 333333;
6792                 default:
6793                 case GC_DISPLAY_CLOCK_190_200_MHZ:
6794                         return 190000;
6795                 }
6796         }
6797 }
6798
6799 static int i865_get_display_clock_speed(struct drm_device *dev)
6800 {
6801         return 266667;
6802 }
6803
6804 static int i85x_get_display_clock_speed(struct drm_device *dev)
6805 {
6806         u16 hpllcc = 0;
6807
6808         /*
6809          * 852GM/852GMV only supports 133 MHz and the HPLLCC
6810          * encoding is different :(
6811          * FIXME is this the right way to detect 852GM/852GMV?
6812          */
6813         if (dev->pdev->revision == 0x1)
6814                 return 133333;
6815
6816         pci_bus_read_config_word(dev->pdev->bus,
6817                                  PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6818
6819         /* Assume that the hardware is in the high speed state.  This
6820          * should be the default.
6821          */
6822         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6823         case GC_CLOCK_133_200:
6824         case GC_CLOCK_133_200_2:
6825         case GC_CLOCK_100_200:
6826                 return 200000;
6827         case GC_CLOCK_166_250:
6828                 return 250000;
6829         case GC_CLOCK_100_133:
6830                 return 133333;
6831         case GC_CLOCK_133_266:
6832         case GC_CLOCK_133_266_2:
6833         case GC_CLOCK_166_266:
6834                 return 266667;
6835         }
6836
6837         /* Shouldn't happen */
6838         return 0;
6839 }
6840
6841 static int i830_get_display_clock_speed(struct drm_device *dev)
6842 {
6843         return 133333;
6844 }
6845
6846 static unsigned int intel_hpll_vco(struct drm_device *dev)
6847 {
6848         struct drm_i915_private *dev_priv = dev->dev_private;
6849         static const unsigned int blb_vco[8] = {
6850                 [0] = 3200000,
6851                 [1] = 4000000,
6852                 [2] = 5333333,
6853                 [3] = 4800000,
6854                 [4] = 6400000,
6855         };
6856         static const unsigned int pnv_vco[8] = {
6857                 [0] = 3200000,
6858                 [1] = 4000000,
6859                 [2] = 5333333,
6860                 [3] = 4800000,
6861                 [4] = 2666667,
6862         };
6863         static const unsigned int cl_vco[8] = {
6864                 [0] = 3200000,
6865                 [1] = 4000000,
6866                 [2] = 5333333,
6867                 [3] = 6400000,
6868                 [4] = 3333333,
6869                 [5] = 3566667,
6870                 [6] = 4266667,
6871         };
6872         static const unsigned int elk_vco[8] = {
6873                 [0] = 3200000,
6874                 [1] = 4000000,
6875                 [2] = 5333333,
6876                 [3] = 4800000,
6877         };
6878         static const unsigned int ctg_vco[8] = {
6879                 [0] = 3200000,
6880                 [1] = 4000000,
6881                 [2] = 5333333,
6882                 [3] = 6400000,
6883                 [4] = 2666667,
6884                 [5] = 4266667,
6885         };
6886         const unsigned int *vco_table;
6887         unsigned int vco;
6888         uint8_t tmp = 0;
6889
6890         /* FIXME other chipsets? */
6891         if (IS_GM45(dev))
6892                 vco_table = ctg_vco;
6893         else if (IS_G4X(dev))
6894                 vco_table = elk_vco;
6895         else if (IS_CRESTLINE(dev))
6896                 vco_table = cl_vco;
6897         else if (IS_PINEVIEW(dev))
6898                 vco_table = pnv_vco;
6899         else if (IS_G33(dev))
6900                 vco_table = blb_vco;
6901         else
6902                 return 0;
6903
6904         tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6905
6906         vco = vco_table[tmp & 0x7];
6907         if (vco == 0)
6908                 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6909         else
6910                 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6911
6912         return vco;
6913 }
6914
6915 static int gm45_get_display_clock_speed(struct drm_device *dev)
6916 {
6917         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6918         uint16_t tmp = 0;
6919
6920         pci_read_config_word(dev->pdev, GCFGC, &tmp);
6921
6922         cdclk_sel = (tmp >> 12) & 0x1;
6923
6924         switch (vco) {
6925         case 2666667:
6926         case 4000000:
6927         case 5333333:
6928                 return cdclk_sel ? 333333 : 222222;
6929         case 3200000:
6930                 return cdclk_sel ? 320000 : 228571;
6931         default:
6932                 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6933                 return 222222;
6934         }
6935 }
6936
6937 static int i965gm_get_display_clock_speed(struct drm_device *dev)
6938 {
6939         static const uint8_t div_3200[] = { 16, 10,  8 };
6940         static const uint8_t div_4000[] = { 20, 12, 10 };
6941         static const uint8_t div_5333[] = { 24, 16, 14 };
6942         const uint8_t *div_table;
6943         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6944         uint16_t tmp = 0;
6945
6946         pci_read_config_word(dev->pdev, GCFGC, &tmp);
6947
6948         cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
6949
6950         if (cdclk_sel >= ARRAY_SIZE(div_3200))
6951                 goto fail;
6952
6953         switch (vco) {
6954         case 3200000:
6955                 div_table = div_3200;
6956                 break;
6957         case 4000000:
6958                 div_table = div_4000;
6959                 break;
6960         case 5333333:
6961                 div_table = div_5333;
6962                 break;
6963         default:
6964                 goto fail;
6965         }
6966
6967         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6968
6969 fail:
6970         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
6971         return 200000;
6972 }
6973
6974 static int g33_get_display_clock_speed(struct drm_device *dev)
6975 {
6976         static const uint8_t div_3200[] = { 12, 10,  8,  7, 5, 16 };
6977         static const uint8_t div_4000[] = { 14, 12, 10,  8, 6, 20 };
6978         static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
6979         static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
6980         const uint8_t *div_table;
6981         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6982         uint16_t tmp = 0;
6983
6984         pci_read_config_word(dev->pdev, GCFGC, &tmp);
6985
6986         cdclk_sel = (tmp >> 4) & 0x7;
6987
6988         if (cdclk_sel >= ARRAY_SIZE(div_3200))
6989                 goto fail;
6990
6991         switch (vco) {
6992         case 3200000:
6993                 div_table = div_3200;
6994                 break;
6995         case 4000000:
6996                 div_table = div_4000;
6997                 break;
6998         case 4800000:
6999                 div_table = div_4800;
7000                 break;
7001         case 5333333:
7002                 div_table = div_5333;
7003                 break;
7004         default:
7005                 goto fail;
7006         }
7007
7008         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7009
7010 fail:
7011         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7012         return 190476;
7013 }
7014
7015 static void
7016 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7017 {
7018         while (*num > DATA_LINK_M_N_MASK ||
7019                *den > DATA_LINK_M_N_MASK) {
7020                 *num >>= 1;
7021                 *den >>= 1;
7022         }
7023 }
7024
7025 static void compute_m_n(unsigned int m, unsigned int n,
7026                         uint32_t *ret_m, uint32_t *ret_n)
7027 {
7028         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7029         *ret_m = div_u64((uint64_t) m * *ret_n, n);
7030         intel_reduce_m_n_ratio(ret_m, ret_n);
7031 }
7032
7033 void
7034 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7035                        int pixel_clock, int link_clock,
7036                        struct intel_link_m_n *m_n)
7037 {
7038         m_n->tu = 64;
7039
7040         compute_m_n(bits_per_pixel * pixel_clock,
7041                     link_clock * nlanes * 8,
7042                     &m_n->gmch_m, &m_n->gmch_n);
7043
7044         compute_m_n(pixel_clock, link_clock,
7045                     &m_n->link_m, &m_n->link_n);
7046 }
7047
7048 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7049 {
7050         if (i915.panel_use_ssc >= 0)
7051                 return i915.panel_use_ssc != 0;
7052         return dev_priv->vbt.lvds_use_ssc
7053                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7054 }
7055
7056 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7057                            int num_connectors)
7058 {
7059         struct drm_device *dev = crtc_state->base.crtc->dev;
7060         struct drm_i915_private *dev_priv = dev->dev_private;
7061         int refclk;
7062
7063         WARN_ON(!crtc_state->base.state);
7064
7065         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || IS_BROXTON(dev)) {
7066                 refclk = 100000;
7067         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7068             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7069                 refclk = dev_priv->vbt.lvds_ssc_freq;
7070                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7071         } else if (!IS_GEN2(dev)) {
7072                 refclk = 96000;
7073         } else {
7074                 refclk = 48000;
7075         }
7076
7077         return refclk;
7078 }
7079
7080 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7081 {
7082         return (1 << dpll->n) << 16 | dpll->m2;
7083 }
7084
7085 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7086 {
7087         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7088 }
7089
7090 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7091                                      struct intel_crtc_state *crtc_state,
7092                                      intel_clock_t *reduced_clock)
7093 {
7094         struct drm_device *dev = crtc->base.dev;
7095         u32 fp, fp2 = 0;
7096
7097         if (IS_PINEVIEW(dev)) {
7098                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7099                 if (reduced_clock)
7100                         fp2 = pnv_dpll_compute_fp(reduced_clock);
7101         } else {
7102                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7103                 if (reduced_clock)
7104                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
7105         }
7106
7107         crtc_state->dpll_hw_state.fp0 = fp;
7108
7109         crtc->lowfreq_avail = false;
7110         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7111             reduced_clock) {
7112                 crtc_state->dpll_hw_state.fp1 = fp2;
7113                 crtc->lowfreq_avail = true;
7114         } else {
7115                 crtc_state->dpll_hw_state.fp1 = fp;
7116         }
7117 }
7118
7119 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7120                 pipe)
7121 {
7122         u32 reg_val;
7123
7124         /*
7125          * PLLB opamp always calibrates to max value of 0x3f, force enable it
7126          * and set it to a reasonable value instead.
7127          */
7128         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7129         reg_val &= 0xffffff00;
7130         reg_val |= 0x00000030;
7131         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7132
7133         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7134         reg_val &= 0x8cffffff;
7135         reg_val = 0x8c000000;
7136         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7137
7138         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7139         reg_val &= 0xffffff00;
7140         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7141
7142         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7143         reg_val &= 0x00ffffff;
7144         reg_val |= 0xb0000000;
7145         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7146 }
7147
7148 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7149                                          struct intel_link_m_n *m_n)
7150 {
7151         struct drm_device *dev = crtc->base.dev;
7152         struct drm_i915_private *dev_priv = dev->dev_private;
7153         int pipe = crtc->pipe;
7154
7155         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7156         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7157         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7158         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7159 }
7160
7161 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7162                                          struct intel_link_m_n *m_n,
7163                                          struct intel_link_m_n *m2_n2)
7164 {
7165         struct drm_device *dev = crtc->base.dev;
7166         struct drm_i915_private *dev_priv = dev->dev_private;
7167         int pipe = crtc->pipe;
7168         enum transcoder transcoder = crtc->config->cpu_transcoder;
7169
7170         if (INTEL_INFO(dev)->gen >= 5) {
7171                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7172                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7173                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7174                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7175                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7176                  * for gen < 8) and if DRRS is supported (to make sure the
7177                  * registers are not unnecessarily accessed).
7178                  */
7179                 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7180                         crtc->config->has_drrs) {
7181                         I915_WRITE(PIPE_DATA_M2(transcoder),
7182                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7183                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7184                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7185                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7186                 }
7187         } else {
7188                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7189                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7190                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7191                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7192         }
7193 }
7194
7195 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7196 {
7197         struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7198
7199         if (m_n == M1_N1) {
7200                 dp_m_n = &crtc->config->dp_m_n;
7201                 dp_m2_n2 = &crtc->config->dp_m2_n2;
7202         } else if (m_n == M2_N2) {
7203
7204                 /*
7205                  * M2_N2 registers are not supported. Hence m2_n2 divider value
7206                  * needs to be programmed into M1_N1.
7207                  */
7208                 dp_m_n = &crtc->config->dp_m2_n2;
7209         } else {
7210                 DRM_ERROR("Unsupported divider value\n");
7211                 return;
7212         }
7213
7214         if (crtc->config->has_pch_encoder)
7215                 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7216         else
7217                 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7218 }
7219
7220 static void vlv_compute_dpll(struct intel_crtc *crtc,
7221                              struct intel_crtc_state *pipe_config)
7222 {
7223         u32 dpll, dpll_md;
7224
7225         /*
7226          * Enable DPIO clock input. We should never disable the reference
7227          * clock for pipe B, since VGA hotplug / manual detection depends
7228          * on it.
7229          */
7230         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV |
7231                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV;
7232         /* We should never disable this, set it here for state tracking */
7233         if (crtc->pipe == PIPE_B)
7234                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7235         dpll |= DPLL_VCO_ENABLE;
7236         pipe_config->dpll_hw_state.dpll = dpll;
7237
7238         dpll_md = (pipe_config->pixel_multiplier - 1)
7239                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7240         pipe_config->dpll_hw_state.dpll_md = dpll_md;
7241 }
7242
7243 static void vlv_prepare_pll(struct intel_crtc *crtc,
7244                             const struct intel_crtc_state *pipe_config)
7245 {
7246         struct drm_device *dev = crtc->base.dev;
7247         struct drm_i915_private *dev_priv = dev->dev_private;
7248         int pipe = crtc->pipe;
7249         u32 mdiv;
7250         u32 bestn, bestm1, bestm2, bestp1, bestp2;
7251         u32 coreclk, reg_val;
7252
7253         mutex_lock(&dev_priv->sb_lock);
7254
7255         bestn = pipe_config->dpll.n;
7256         bestm1 = pipe_config->dpll.m1;
7257         bestm2 = pipe_config->dpll.m2;
7258         bestp1 = pipe_config->dpll.p1;
7259         bestp2 = pipe_config->dpll.p2;
7260
7261         /* See eDP HDMI DPIO driver vbios notes doc */
7262
7263         /* PLL B needs special handling */
7264         if (pipe == PIPE_B)
7265                 vlv_pllb_recal_opamp(dev_priv, pipe);
7266
7267         /* Set up Tx target for periodic Rcomp update */
7268         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7269
7270         /* Disable target IRef on PLL */
7271         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7272         reg_val &= 0x00ffffff;
7273         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7274
7275         /* Disable fast lock */
7276         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7277
7278         /* Set idtafcrecal before PLL is enabled */
7279         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7280         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7281         mdiv |= ((bestn << DPIO_N_SHIFT));
7282         mdiv |= (1 << DPIO_K_SHIFT);
7283
7284         /*
7285          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7286          * but we don't support that).
7287          * Note: don't use the DAC post divider as it seems unstable.
7288          */
7289         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7290         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7291
7292         mdiv |= DPIO_ENABLE_CALIBRATION;
7293         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7294
7295         /* Set HBR and RBR LPF coefficients */
7296         if (pipe_config->port_clock == 162000 ||
7297             intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7298             intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7299                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7300                                  0x009f0003);
7301         else
7302                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7303                                  0x00d0000f);
7304
7305         if (pipe_config->has_dp_encoder) {
7306                 /* Use SSC source */
7307                 if (pipe == PIPE_A)
7308                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7309                                          0x0df40000);
7310                 else
7311                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7312                                          0x0df70000);
7313         } else { /* HDMI or VGA */
7314                 /* Use bend source */
7315                 if (pipe == PIPE_A)
7316                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7317                                          0x0df70000);
7318                 else
7319                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7320                                          0x0df40000);
7321         }
7322
7323         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7324         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7325         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7326             intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7327                 coreclk |= 0x01000000;
7328         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7329
7330         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7331         mutex_unlock(&dev_priv->sb_lock);
7332 }
7333
7334 static void chv_compute_dpll(struct intel_crtc *crtc,
7335                              struct intel_crtc_state *pipe_config)
7336 {
7337         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7338                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7339                 DPLL_VCO_ENABLE;
7340         if (crtc->pipe != PIPE_A)
7341                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7342
7343         pipe_config->dpll_hw_state.dpll_md =
7344                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7345 }
7346
7347 static void chv_prepare_pll(struct intel_crtc *crtc,
7348                             const struct intel_crtc_state *pipe_config)
7349 {
7350         struct drm_device *dev = crtc->base.dev;
7351         struct drm_i915_private *dev_priv = dev->dev_private;
7352         int pipe = crtc->pipe;
7353         i915_reg_t dpll_reg = DPLL(crtc->pipe);
7354         enum dpio_channel port = vlv_pipe_to_channel(pipe);
7355         u32 loopfilter, tribuf_calcntr;
7356         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7357         u32 dpio_val;
7358         int vco;
7359
7360         bestn = pipe_config->dpll.n;
7361         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7362         bestm1 = pipe_config->dpll.m1;
7363         bestm2 = pipe_config->dpll.m2 >> 22;
7364         bestp1 = pipe_config->dpll.p1;
7365         bestp2 = pipe_config->dpll.p2;
7366         vco = pipe_config->dpll.vco;
7367         dpio_val = 0;
7368         loopfilter = 0;
7369
7370         /*
7371          * Enable Refclk and SSC
7372          */
7373         I915_WRITE(dpll_reg,
7374                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7375
7376         mutex_lock(&dev_priv->sb_lock);
7377
7378         /* p1 and p2 divider */
7379         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7380                         5 << DPIO_CHV_S1_DIV_SHIFT |
7381                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7382                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7383                         1 << DPIO_CHV_K_DIV_SHIFT);
7384
7385         /* Feedback post-divider - m2 */
7386         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7387
7388         /* Feedback refclk divider - n and m1 */
7389         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7390                         DPIO_CHV_M1_DIV_BY_2 |
7391                         1 << DPIO_CHV_N_DIV_SHIFT);
7392
7393         /* M2 fraction division */
7394         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7395
7396         /* M2 fraction division enable */
7397         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7398         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7399         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7400         if (bestm2_frac)
7401                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7402         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7403
7404         /* Program digital lock detect threshold */
7405         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7406         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7407                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7408         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7409         if (!bestm2_frac)
7410                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7411         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7412
7413         /* Loop filter */
7414         if (vco == 5400000) {
7415                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7416                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7417                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7418                 tribuf_calcntr = 0x9;
7419         } else if (vco <= 6200000) {
7420                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7421                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7422                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7423                 tribuf_calcntr = 0x9;
7424         } else if (vco <= 6480000) {
7425                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7426                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7427                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7428                 tribuf_calcntr = 0x8;
7429         } else {
7430                 /* Not supported. Apply the same limits as in the max case */
7431                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7432                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7433                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7434                 tribuf_calcntr = 0;
7435         }
7436         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7437
7438         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7439         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7440         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7441         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7442
7443         /* AFC Recal */
7444         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7445                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7446                         DPIO_AFC_RECAL);
7447
7448         mutex_unlock(&dev_priv->sb_lock);
7449 }
7450
7451 /**
7452  * vlv_force_pll_on - forcibly enable just the PLL
7453  * @dev_priv: i915 private structure
7454  * @pipe: pipe PLL to enable
7455  * @dpll: PLL configuration
7456  *
7457  * Enable the PLL for @pipe using the supplied @dpll config. To be used
7458  * in cases where we need the PLL enabled even when @pipe is not going to
7459  * be enabled.
7460  */
7461 int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7462                      const struct dpll *dpll)
7463 {
7464         struct intel_crtc *crtc =
7465                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7466         struct intel_crtc_state *pipe_config;
7467
7468         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7469         if (!pipe_config)
7470                 return -ENOMEM;
7471
7472         pipe_config->base.crtc = &crtc->base;
7473         pipe_config->pixel_multiplier = 1;
7474         pipe_config->dpll = *dpll;
7475
7476         if (IS_CHERRYVIEW(dev)) {
7477                 chv_compute_dpll(crtc, pipe_config);
7478                 chv_prepare_pll(crtc, pipe_config);
7479                 chv_enable_pll(crtc, pipe_config);
7480         } else {
7481                 vlv_compute_dpll(crtc, pipe_config);
7482                 vlv_prepare_pll(crtc, pipe_config);
7483                 vlv_enable_pll(crtc, pipe_config);
7484         }
7485
7486         kfree(pipe_config);
7487
7488         return 0;
7489 }
7490
7491 /**
7492  * vlv_force_pll_off - forcibly disable just the PLL
7493  * @dev_priv: i915 private structure
7494  * @pipe: pipe PLL to disable
7495  *
7496  * Disable the PLL for @pipe. To be used in cases where we need
7497  * the PLL enabled even when @pipe is not going to be enabled.
7498  */
7499 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7500 {
7501         if (IS_CHERRYVIEW(dev))
7502                 chv_disable_pll(to_i915(dev), pipe);
7503         else
7504                 vlv_disable_pll(to_i915(dev), pipe);
7505 }
7506
7507 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7508                               struct intel_crtc_state *crtc_state,
7509                               intel_clock_t *reduced_clock,
7510                               int num_connectors)
7511 {
7512         struct drm_device *dev = crtc->base.dev;
7513         struct drm_i915_private *dev_priv = dev->dev_private;
7514         u32 dpll;
7515         bool is_sdvo;
7516         struct dpll *clock = &crtc_state->dpll;
7517
7518         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7519
7520         is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7521                 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7522
7523         dpll = DPLL_VGA_MODE_DIS;
7524
7525         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7526                 dpll |= DPLLB_MODE_LVDS;
7527         else
7528                 dpll |= DPLLB_MODE_DAC_SERIAL;
7529
7530         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7531                 dpll |= (crtc_state->pixel_multiplier - 1)
7532                         << SDVO_MULTIPLIER_SHIFT_HIRES;
7533         }
7534
7535         if (is_sdvo)
7536                 dpll |= DPLL_SDVO_HIGH_SPEED;
7537
7538         if (crtc_state->has_dp_encoder)
7539                 dpll |= DPLL_SDVO_HIGH_SPEED;
7540
7541         /* compute bitmask from p1 value */
7542         if (IS_PINEVIEW(dev))
7543                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7544         else {
7545                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7546                 if (IS_G4X(dev) && reduced_clock)
7547                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7548         }
7549         switch (clock->p2) {
7550         case 5:
7551                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7552                 break;
7553         case 7:
7554                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7555                 break;
7556         case 10:
7557                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7558                 break;
7559         case 14:
7560                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7561                 break;
7562         }
7563         if (INTEL_INFO(dev)->gen >= 4)
7564                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7565
7566         if (crtc_state->sdvo_tv_clock)
7567                 dpll |= PLL_REF_INPUT_TVCLKINBC;
7568         else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7569                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7570                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7571         else
7572                 dpll |= PLL_REF_INPUT_DREFCLK;
7573
7574         dpll |= DPLL_VCO_ENABLE;
7575         crtc_state->dpll_hw_state.dpll = dpll;
7576
7577         if (INTEL_INFO(dev)->gen >= 4) {
7578                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7579                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7580                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7581         }
7582 }
7583
7584 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7585                               struct intel_crtc_state *crtc_state,
7586                               intel_clock_t *reduced_clock,
7587                               int num_connectors)
7588 {
7589         struct drm_device *dev = crtc->base.dev;
7590         struct drm_i915_private *dev_priv = dev->dev_private;
7591         u32 dpll;
7592         struct dpll *clock = &crtc_state->dpll;
7593
7594         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7595
7596         dpll = DPLL_VGA_MODE_DIS;
7597
7598         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7599                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7600         } else {
7601                 if (clock->p1 == 2)
7602                         dpll |= PLL_P1_DIVIDE_BY_TWO;
7603                 else
7604                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7605                 if (clock->p2 == 4)
7606                         dpll |= PLL_P2_DIVIDE_BY_4;
7607         }
7608
7609         if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7610                 dpll |= DPLL_DVO_2X_MODE;
7611
7612         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7613                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7614                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7615         else
7616                 dpll |= PLL_REF_INPUT_DREFCLK;
7617
7618         dpll |= DPLL_VCO_ENABLE;
7619         crtc_state->dpll_hw_state.dpll = dpll;
7620 }
7621
7622 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7623 {
7624         struct drm_device *dev = intel_crtc->base.dev;
7625         struct drm_i915_private *dev_priv = dev->dev_private;
7626         enum pipe pipe = intel_crtc->pipe;
7627         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7628         const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
7629         uint32_t crtc_vtotal, crtc_vblank_end;
7630         int vsyncshift = 0;
7631
7632         /* We need to be careful not to changed the adjusted mode, for otherwise
7633          * the hw state checker will get angry at the mismatch. */
7634         crtc_vtotal = adjusted_mode->crtc_vtotal;
7635         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7636
7637         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7638                 /* the chip adds 2 halflines automatically */
7639                 crtc_vtotal -= 1;
7640                 crtc_vblank_end -= 1;
7641
7642                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7643                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7644                 else
7645                         vsyncshift = adjusted_mode->crtc_hsync_start -
7646                                 adjusted_mode->crtc_htotal / 2;
7647                 if (vsyncshift < 0)
7648                         vsyncshift += adjusted_mode->crtc_htotal;
7649         }
7650
7651         if (INTEL_INFO(dev)->gen > 3)
7652                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7653
7654         I915_WRITE(HTOTAL(cpu_transcoder),
7655                    (adjusted_mode->crtc_hdisplay - 1) |
7656                    ((adjusted_mode->crtc_htotal - 1) << 16));
7657         I915_WRITE(HBLANK(cpu_transcoder),
7658                    (adjusted_mode->crtc_hblank_start - 1) |
7659                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
7660         I915_WRITE(HSYNC(cpu_transcoder),
7661                    (adjusted_mode->crtc_hsync_start - 1) |
7662                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
7663
7664         I915_WRITE(VTOTAL(cpu_transcoder),
7665                    (adjusted_mode->crtc_vdisplay - 1) |
7666                    ((crtc_vtotal - 1) << 16));
7667         I915_WRITE(VBLANK(cpu_transcoder),
7668                    (adjusted_mode->crtc_vblank_start - 1) |
7669                    ((crtc_vblank_end - 1) << 16));
7670         I915_WRITE(VSYNC(cpu_transcoder),
7671                    (adjusted_mode->crtc_vsync_start - 1) |
7672                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
7673
7674         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7675          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7676          * documented on the DDI_FUNC_CTL register description, EDP Input Select
7677          * bits. */
7678         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7679             (pipe == PIPE_B || pipe == PIPE_C))
7680                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7681
7682         /* pipesrc controls the size that is scaled from, which should
7683          * always be the user's requested size.
7684          */
7685         I915_WRITE(PIPESRC(pipe),
7686                    ((intel_crtc->config->pipe_src_w - 1) << 16) |
7687                    (intel_crtc->config->pipe_src_h - 1));
7688 }
7689
7690 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7691                                    struct intel_crtc_state *pipe_config)
7692 {
7693         struct drm_device *dev = crtc->base.dev;
7694         struct drm_i915_private *dev_priv = dev->dev_private;
7695         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7696         uint32_t tmp;
7697
7698         tmp = I915_READ(HTOTAL(cpu_transcoder));
7699         pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7700         pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7701         tmp = I915_READ(HBLANK(cpu_transcoder));
7702         pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7703         pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7704         tmp = I915_READ(HSYNC(cpu_transcoder));
7705         pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7706         pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7707
7708         tmp = I915_READ(VTOTAL(cpu_transcoder));
7709         pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7710         pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7711         tmp = I915_READ(VBLANK(cpu_transcoder));
7712         pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7713         pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7714         tmp = I915_READ(VSYNC(cpu_transcoder));
7715         pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7716         pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7717
7718         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7719                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7720                 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7721                 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7722         }
7723
7724         tmp = I915_READ(PIPESRC(crtc->pipe));
7725         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7726         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7727
7728         pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7729         pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7730 }
7731
7732 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7733                                  struct intel_crtc_state *pipe_config)
7734 {
7735         mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7736         mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7737         mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7738         mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7739
7740         mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7741         mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7742         mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7743         mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7744
7745         mode->flags = pipe_config->base.adjusted_mode.flags;
7746         mode->type = DRM_MODE_TYPE_DRIVER;
7747
7748         mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7749         mode->flags |= pipe_config->base.adjusted_mode.flags;
7750
7751         mode->hsync = drm_mode_hsync(mode);
7752         mode->vrefresh = drm_mode_vrefresh(mode);
7753         drm_mode_set_name(mode);
7754 }
7755
7756 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7757 {
7758         struct drm_device *dev = intel_crtc->base.dev;
7759         struct drm_i915_private *dev_priv = dev->dev_private;
7760         uint32_t pipeconf;
7761
7762         pipeconf = 0;
7763
7764         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7765             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7766                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7767
7768         if (intel_crtc->config->double_wide)
7769                 pipeconf |= PIPECONF_DOUBLE_WIDE;
7770
7771         /* only g4x and later have fancy bpc/dither controls */
7772         if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
7773                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7774                 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7775                         pipeconf |= PIPECONF_DITHER_EN |
7776                                     PIPECONF_DITHER_TYPE_SP;
7777
7778                 switch (intel_crtc->config->pipe_bpp) {
7779                 case 18:
7780                         pipeconf |= PIPECONF_6BPC;
7781                         break;
7782                 case 24:
7783                         pipeconf |= PIPECONF_8BPC;
7784                         break;
7785                 case 30:
7786                         pipeconf |= PIPECONF_10BPC;
7787                         break;
7788                 default:
7789                         /* Case prevented by intel_choose_pipe_bpp_dither. */
7790                         BUG();
7791                 }
7792         }
7793
7794         if (HAS_PIPE_CXSR(dev)) {
7795                 if (intel_crtc->lowfreq_avail) {
7796                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7797                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7798                 } else {
7799                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7800                 }
7801         }
7802
7803         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7804                 if (INTEL_INFO(dev)->gen < 4 ||
7805                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7806                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7807                 else
7808                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7809         } else
7810                 pipeconf |= PIPECONF_PROGRESSIVE;
7811
7812         if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
7813              intel_crtc->config->limited_color_range)
7814                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7815
7816         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7817         POSTING_READ(PIPECONF(intel_crtc->pipe));
7818 }
7819
7820 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7821                                    struct intel_crtc_state *crtc_state)
7822 {
7823         struct drm_device *dev = crtc->base.dev;
7824         struct drm_i915_private *dev_priv = dev->dev_private;
7825         int refclk, num_connectors = 0;
7826         intel_clock_t clock;
7827         bool ok;
7828         const intel_limit_t *limit;
7829         struct drm_atomic_state *state = crtc_state->base.state;
7830         struct drm_connector *connector;
7831         struct drm_connector_state *connector_state;
7832         int i;
7833
7834         memset(&crtc_state->dpll_hw_state, 0,
7835                sizeof(crtc_state->dpll_hw_state));
7836
7837         if (crtc_state->has_dsi_encoder)
7838                 return 0;
7839
7840         for_each_connector_in_state(state, connector, connector_state, i) {
7841                 if (connector_state->crtc == &crtc->base)
7842                         num_connectors++;
7843         }
7844
7845         if (!crtc_state->clock_set) {
7846                 refclk = i9xx_get_refclk(crtc_state, num_connectors);
7847
7848                 /*
7849                  * Returns a set of divisors for the desired target clock with
7850                  * the given refclk, or FALSE.  The returned values represent
7851                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7852                  * 2) / p1 / p2.
7853                  */
7854                 limit = intel_limit(crtc_state, refclk);
7855                 ok = dev_priv->display.find_dpll(limit, crtc_state,
7856                                                  crtc_state->port_clock,
7857                                                  refclk, NULL, &clock);
7858                 if (!ok) {
7859                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
7860                         return -EINVAL;
7861                 }
7862
7863                 /* Compat-code for transition, will disappear. */
7864                 crtc_state->dpll.n = clock.n;
7865                 crtc_state->dpll.m1 = clock.m1;
7866                 crtc_state->dpll.m2 = clock.m2;
7867                 crtc_state->dpll.p1 = clock.p1;
7868                 crtc_state->dpll.p2 = clock.p2;
7869         }
7870
7871         if (IS_GEN2(dev)) {
7872                 i8xx_compute_dpll(crtc, crtc_state, NULL,
7873                                   num_connectors);
7874         } else if (IS_CHERRYVIEW(dev)) {
7875                 chv_compute_dpll(crtc, crtc_state);
7876         } else if (IS_VALLEYVIEW(dev)) {
7877                 vlv_compute_dpll(crtc, crtc_state);
7878         } else {
7879                 i9xx_compute_dpll(crtc, crtc_state, NULL,
7880                                   num_connectors);
7881         }
7882
7883         return 0;
7884 }
7885
7886 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7887                                  struct intel_crtc_state *pipe_config)
7888 {
7889         struct drm_device *dev = crtc->base.dev;
7890         struct drm_i915_private *dev_priv = dev->dev_private;
7891         uint32_t tmp;
7892
7893         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7894                 return;
7895
7896         tmp = I915_READ(PFIT_CONTROL);
7897         if (!(tmp & PFIT_ENABLE))
7898                 return;
7899
7900         /* Check whether the pfit is attached to our pipe. */
7901         if (INTEL_INFO(dev)->gen < 4) {
7902                 if (crtc->pipe != PIPE_B)
7903                         return;
7904         } else {
7905                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7906                         return;
7907         }
7908
7909         pipe_config->gmch_pfit.control = tmp;
7910         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7911         if (INTEL_INFO(dev)->gen < 5)
7912                 pipe_config->gmch_pfit.lvds_border_bits =
7913                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7914 }
7915
7916 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7917                                struct intel_crtc_state *pipe_config)
7918 {
7919         struct drm_device *dev = crtc->base.dev;
7920         struct drm_i915_private *dev_priv = dev->dev_private;
7921         int pipe = pipe_config->cpu_transcoder;
7922         intel_clock_t clock;
7923         u32 mdiv;
7924         int refclk = 100000;
7925
7926         /* In case of MIPI DPLL will not even be used */
7927         if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7928                 return;
7929
7930         mutex_lock(&dev_priv->sb_lock);
7931         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7932         mutex_unlock(&dev_priv->sb_lock);
7933
7934         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7935         clock.m2 = mdiv & DPIO_M2DIV_MASK;
7936         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7937         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7938         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7939
7940         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
7941 }
7942
7943 static void
7944 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7945                               struct intel_initial_plane_config *plane_config)
7946 {
7947         struct drm_device *dev = crtc->base.dev;
7948         struct drm_i915_private *dev_priv = dev->dev_private;
7949         u32 val, base, offset;
7950         int pipe = crtc->pipe, plane = crtc->plane;
7951         int fourcc, pixel_format;
7952         unsigned int aligned_height;
7953         struct drm_framebuffer *fb;
7954         struct intel_framebuffer *intel_fb;
7955
7956         val = I915_READ(DSPCNTR(plane));
7957         if (!(val & DISPLAY_PLANE_ENABLE))
7958                 return;
7959
7960         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7961         if (!intel_fb) {
7962                 DRM_DEBUG_KMS("failed to alloc fb\n");
7963                 return;
7964         }
7965
7966         fb = &intel_fb->base;
7967
7968         if (INTEL_INFO(dev)->gen >= 4) {
7969                 if (val & DISPPLANE_TILED) {
7970                         plane_config->tiling = I915_TILING_X;
7971                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7972                 }
7973         }
7974
7975         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7976         fourcc = i9xx_format_to_fourcc(pixel_format);
7977         fb->pixel_format = fourcc;
7978         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7979
7980         if (INTEL_INFO(dev)->gen >= 4) {
7981                 if (plane_config->tiling)
7982                         offset = I915_READ(DSPTILEOFF(plane));
7983                 else
7984                         offset = I915_READ(DSPLINOFF(plane));
7985                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7986         } else {
7987                 base = I915_READ(DSPADDR(plane));
7988         }
7989         plane_config->base = base;
7990
7991         val = I915_READ(PIPESRC(pipe));
7992         fb->width = ((val >> 16) & 0xfff) + 1;
7993         fb->height = ((val >> 0) & 0xfff) + 1;
7994
7995         val = I915_READ(DSPSTRIDE(pipe));
7996         fb->pitches[0] = val & 0xffffffc0;
7997
7998         aligned_height = intel_fb_align_height(dev, fb->height,
7999                                                fb->pixel_format,
8000                                                fb->modifier[0]);
8001
8002         plane_config->size = fb->pitches[0] * aligned_height;
8003
8004         DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8005                       pipe_name(pipe), plane, fb->width, fb->height,
8006                       fb->bits_per_pixel, base, fb->pitches[0],
8007                       plane_config->size);
8008
8009         plane_config->fb = intel_fb;
8010 }
8011
8012 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8013                                struct intel_crtc_state *pipe_config)
8014 {
8015         struct drm_device *dev = crtc->base.dev;
8016         struct drm_i915_private *dev_priv = dev->dev_private;
8017         int pipe = pipe_config->cpu_transcoder;
8018         enum dpio_channel port = vlv_pipe_to_channel(pipe);
8019         intel_clock_t clock;
8020         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8021         int refclk = 100000;
8022
8023         mutex_lock(&dev_priv->sb_lock);
8024         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8025         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8026         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8027         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8028         pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8029         mutex_unlock(&dev_priv->sb_lock);
8030
8031         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8032         clock.m2 = (pll_dw0 & 0xff) << 22;
8033         if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8034                 clock.m2 |= pll_dw2 & 0x3fffff;
8035         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8036         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8037         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8038
8039         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8040 }
8041
8042 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8043                                  struct intel_crtc_state *pipe_config)
8044 {
8045         struct drm_device *dev = crtc->base.dev;
8046         struct drm_i915_private *dev_priv = dev->dev_private;
8047         enum intel_display_power_domain power_domain;
8048         uint32_t tmp;
8049         bool ret;
8050
8051         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8052         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8053                 return false;
8054
8055         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8056         pipe_config->shared_dpll = NULL;
8057
8058         ret = false;
8059
8060         tmp = I915_READ(PIPECONF(crtc->pipe));
8061         if (!(tmp & PIPECONF_ENABLE))
8062                 goto out;
8063
8064         if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
8065                 switch (tmp & PIPECONF_BPC_MASK) {
8066                 case PIPECONF_6BPC:
8067                         pipe_config->pipe_bpp = 18;
8068                         break;
8069                 case PIPECONF_8BPC:
8070                         pipe_config->pipe_bpp = 24;
8071                         break;
8072                 case PIPECONF_10BPC:
8073                         pipe_config->pipe_bpp = 30;
8074                         break;
8075                 default:
8076                         break;
8077                 }
8078         }
8079
8080         if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
8081             (tmp & PIPECONF_COLOR_RANGE_SELECT))
8082                 pipe_config->limited_color_range = true;
8083
8084         if (INTEL_INFO(dev)->gen < 4)
8085                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8086
8087         intel_get_pipe_timings(crtc, pipe_config);
8088
8089         i9xx_get_pfit_config(crtc, pipe_config);
8090
8091         if (INTEL_INFO(dev)->gen >= 4) {
8092                 tmp = I915_READ(DPLL_MD(crtc->pipe));
8093                 pipe_config->pixel_multiplier =
8094                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8095                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8096                 pipe_config->dpll_hw_state.dpll_md = tmp;
8097         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8098                 tmp = I915_READ(DPLL(crtc->pipe));
8099                 pipe_config->pixel_multiplier =
8100                         ((tmp & SDVO_MULTIPLIER_MASK)
8101                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8102         } else {
8103                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8104                  * port and will be fixed up in the encoder->get_config
8105                  * function. */
8106                 pipe_config->pixel_multiplier = 1;
8107         }
8108         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8109         if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
8110                 /*
8111                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8112                  * on 830. Filter it out here so that we don't
8113                  * report errors due to that.
8114                  */
8115                 if (IS_I830(dev))
8116                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8117
8118                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8119                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8120         } else {
8121                 /* Mask out read-only status bits. */
8122                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8123                                                      DPLL_PORTC_READY_MASK |
8124                                                      DPLL_PORTB_READY_MASK);
8125         }
8126
8127         if (IS_CHERRYVIEW(dev))
8128                 chv_crtc_clock_get(crtc, pipe_config);
8129         else if (IS_VALLEYVIEW(dev))
8130                 vlv_crtc_clock_get(crtc, pipe_config);
8131         else
8132                 i9xx_crtc_clock_get(crtc, pipe_config);
8133
8134         /*
8135          * Normally the dotclock is filled in by the encoder .get_config()
8136          * but in case the pipe is enabled w/o any ports we need a sane
8137          * default.
8138          */
8139         pipe_config->base.adjusted_mode.crtc_clock =
8140                 pipe_config->port_clock / pipe_config->pixel_multiplier;
8141
8142         ret = true;
8143
8144 out:
8145         intel_display_power_put(dev_priv, power_domain);
8146
8147         return ret;
8148 }
8149
8150 static void ironlake_init_pch_refclk(struct drm_device *dev)
8151 {
8152         struct drm_i915_private *dev_priv = dev->dev_private;
8153         struct intel_encoder *encoder;
8154         u32 val, final;
8155         bool has_lvds = false;
8156         bool has_cpu_edp = false;
8157         bool has_panel = false;
8158         bool has_ck505 = false;
8159         bool can_ssc = false;
8160
8161         /* We need to take the global config into account */
8162         for_each_intel_encoder(dev, encoder) {
8163                 switch (encoder->type) {
8164                 case INTEL_OUTPUT_LVDS:
8165                         has_panel = true;
8166                         has_lvds = true;
8167                         break;
8168                 case INTEL_OUTPUT_EDP:
8169                         has_panel = true;
8170                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8171                                 has_cpu_edp = true;
8172                         break;
8173                 default:
8174                         break;
8175                 }
8176         }
8177
8178         if (HAS_PCH_IBX(dev)) {
8179                 has_ck505 = dev_priv->vbt.display_clock_mode;
8180                 can_ssc = has_ck505;
8181         } else {
8182                 has_ck505 = false;
8183                 can_ssc = true;
8184         }
8185
8186         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8187                       has_panel, has_lvds, has_ck505);
8188
8189         /* Ironlake: try to setup display ref clock before DPLL
8190          * enabling. This is only under driver's control after
8191          * PCH B stepping, previous chipset stepping should be
8192          * ignoring this setting.
8193          */
8194         val = I915_READ(PCH_DREF_CONTROL);
8195
8196         /* As we must carefully and slowly disable/enable each source in turn,
8197          * compute the final state we want first and check if we need to
8198          * make any changes at all.
8199          */
8200         final = val;
8201         final &= ~DREF_NONSPREAD_SOURCE_MASK;
8202         if (has_ck505)
8203                 final |= DREF_NONSPREAD_CK505_ENABLE;
8204         else
8205                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8206
8207         final &= ~DREF_SSC_SOURCE_MASK;
8208         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8209         final &= ~DREF_SSC1_ENABLE;
8210
8211         if (has_panel) {
8212                 final |= DREF_SSC_SOURCE_ENABLE;
8213
8214                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8215                         final |= DREF_SSC1_ENABLE;
8216
8217                 if (has_cpu_edp) {
8218                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
8219                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8220                         else
8221                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8222                 } else
8223                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8224         } else {
8225                 final |= DREF_SSC_SOURCE_DISABLE;
8226                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8227         }
8228
8229         if (final == val)
8230                 return;
8231
8232         /* Always enable nonspread source */
8233         val &= ~DREF_NONSPREAD_SOURCE_MASK;
8234
8235         if (has_ck505)
8236                 val |= DREF_NONSPREAD_CK505_ENABLE;
8237         else
8238                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8239
8240         if (has_panel) {
8241                 val &= ~DREF_SSC_SOURCE_MASK;
8242                 val |= DREF_SSC_SOURCE_ENABLE;
8243
8244                 /* SSC must be turned on before enabling the CPU output  */
8245                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8246                         DRM_DEBUG_KMS("Using SSC on panel\n");
8247                         val |= DREF_SSC1_ENABLE;
8248                 } else
8249                         val &= ~DREF_SSC1_ENABLE;
8250
8251                 /* Get SSC going before enabling the outputs */
8252                 I915_WRITE(PCH_DREF_CONTROL, val);
8253                 POSTING_READ(PCH_DREF_CONTROL);
8254                 udelay(200);
8255
8256                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8257
8258                 /* Enable CPU source on CPU attached eDP */
8259                 if (has_cpu_edp) {
8260                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8261                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
8262                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8263                         } else
8264                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8265                 } else
8266                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8267
8268                 I915_WRITE(PCH_DREF_CONTROL, val);
8269                 POSTING_READ(PCH_DREF_CONTROL);
8270                 udelay(200);
8271         } else {
8272                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8273
8274                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8275
8276                 /* Turn off CPU output */
8277                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8278
8279                 I915_WRITE(PCH_DREF_CONTROL, val);
8280                 POSTING_READ(PCH_DREF_CONTROL);
8281                 udelay(200);
8282
8283                 /* Turn off the SSC source */
8284                 val &= ~DREF_SSC_SOURCE_MASK;
8285                 val |= DREF_SSC_SOURCE_DISABLE;
8286
8287                 /* Turn off SSC1 */
8288                 val &= ~DREF_SSC1_ENABLE;
8289
8290                 I915_WRITE(PCH_DREF_CONTROL, val);
8291                 POSTING_READ(PCH_DREF_CONTROL);
8292                 udelay(200);
8293         }
8294
8295         BUG_ON(val != final);
8296 }
8297
8298 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8299 {
8300         uint32_t tmp;
8301
8302         tmp = I915_READ(SOUTH_CHICKEN2);
8303         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8304         I915_WRITE(SOUTH_CHICKEN2, tmp);
8305
8306         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8307                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8308                 DRM_ERROR("FDI mPHY reset assert timeout\n");
8309
8310         tmp = I915_READ(SOUTH_CHICKEN2);
8311         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8312         I915_WRITE(SOUTH_CHICKEN2, tmp);
8313
8314         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8315                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8316                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8317 }
8318
8319 /* WaMPhyProgramming:hsw */
8320 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8321 {
8322         uint32_t tmp;
8323
8324         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8325         tmp &= ~(0xFF << 24);
8326         tmp |= (0x12 << 24);
8327         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8328
8329         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8330         tmp |= (1 << 11);
8331         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8332
8333         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8334         tmp |= (1 << 11);
8335         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8336
8337         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8338         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8339         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8340
8341         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8342         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8343         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8344
8345         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8346         tmp &= ~(7 << 13);
8347         tmp |= (5 << 13);
8348         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8349
8350         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8351         tmp &= ~(7 << 13);
8352         tmp |= (5 << 13);
8353         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8354
8355         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8356         tmp &= ~0xFF;
8357         tmp |= 0x1C;
8358         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8359
8360         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8361         tmp &= ~0xFF;
8362         tmp |= 0x1C;
8363         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8364
8365         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8366         tmp &= ~(0xFF << 16);
8367         tmp |= (0x1C << 16);
8368         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8369
8370         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8371         tmp &= ~(0xFF << 16);
8372         tmp |= (0x1C << 16);
8373         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8374
8375         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8376         tmp |= (1 << 27);
8377         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8378
8379         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8380         tmp |= (1 << 27);
8381         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8382
8383         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8384         tmp &= ~(0xF << 28);
8385         tmp |= (4 << 28);
8386         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8387
8388         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8389         tmp &= ~(0xF << 28);
8390         tmp |= (4 << 28);
8391         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8392 }
8393
8394 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8395  * Programming" based on the parameters passed:
8396  * - Sequence to enable CLKOUT_DP
8397  * - Sequence to enable CLKOUT_DP without spread
8398  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8399  */
8400 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8401                                  bool with_fdi)
8402 {
8403         struct drm_i915_private *dev_priv = dev->dev_private;
8404         uint32_t reg, tmp;
8405
8406         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8407                 with_spread = true;
8408         if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
8409                 with_fdi = false;
8410
8411         mutex_lock(&dev_priv->sb_lock);
8412
8413         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8414         tmp &= ~SBI_SSCCTL_DISABLE;
8415         tmp |= SBI_SSCCTL_PATHALT;
8416         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8417
8418         udelay(24);
8419
8420         if (with_spread) {
8421                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8422                 tmp &= ~SBI_SSCCTL_PATHALT;
8423                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8424
8425                 if (with_fdi) {
8426                         lpt_reset_fdi_mphy(dev_priv);
8427                         lpt_program_fdi_mphy(dev_priv);
8428                 }
8429         }
8430
8431         reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8432         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8433         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8434         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8435
8436         mutex_unlock(&dev_priv->sb_lock);
8437 }
8438
8439 /* Sequence to disable CLKOUT_DP */
8440 static void lpt_disable_clkout_dp(struct drm_device *dev)
8441 {
8442         struct drm_i915_private *dev_priv = dev->dev_private;
8443         uint32_t reg, tmp;
8444
8445         mutex_lock(&dev_priv->sb_lock);
8446
8447         reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8448         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8449         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8450         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8451
8452         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8453         if (!(tmp & SBI_SSCCTL_DISABLE)) {
8454                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8455                         tmp |= SBI_SSCCTL_PATHALT;
8456                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8457                         udelay(32);
8458                 }
8459                 tmp |= SBI_SSCCTL_DISABLE;
8460                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8461         }
8462
8463         mutex_unlock(&dev_priv->sb_lock);
8464 }
8465
8466 #define BEND_IDX(steps) ((50 + (steps)) / 5)
8467
8468 static const uint16_t sscdivintphase[] = {
8469         [BEND_IDX( 50)] = 0x3B23,
8470         [BEND_IDX( 45)] = 0x3B23,
8471         [BEND_IDX( 40)] = 0x3C23,
8472         [BEND_IDX( 35)] = 0x3C23,
8473         [BEND_IDX( 30)] = 0x3D23,
8474         [BEND_IDX( 25)] = 0x3D23,
8475         [BEND_IDX( 20)] = 0x3E23,
8476         [BEND_IDX( 15)] = 0x3E23,
8477         [BEND_IDX( 10)] = 0x3F23,
8478         [BEND_IDX(  5)] = 0x3F23,
8479         [BEND_IDX(  0)] = 0x0025,
8480         [BEND_IDX( -5)] = 0x0025,
8481         [BEND_IDX(-10)] = 0x0125,
8482         [BEND_IDX(-15)] = 0x0125,
8483         [BEND_IDX(-20)] = 0x0225,
8484         [BEND_IDX(-25)] = 0x0225,
8485         [BEND_IDX(-30)] = 0x0325,
8486         [BEND_IDX(-35)] = 0x0325,
8487         [BEND_IDX(-40)] = 0x0425,
8488         [BEND_IDX(-45)] = 0x0425,
8489         [BEND_IDX(-50)] = 0x0525,
8490 };
8491
8492 /*
8493  * Bend CLKOUT_DP
8494  * steps -50 to 50 inclusive, in steps of 5
8495  * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
8496  * change in clock period = -(steps / 10) * 5.787 ps
8497  */
8498 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
8499 {
8500         uint32_t tmp;
8501         int idx = BEND_IDX(steps);
8502
8503         if (WARN_ON(steps % 5 != 0))
8504                 return;
8505
8506         if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
8507                 return;
8508
8509         mutex_lock(&dev_priv->sb_lock);
8510
8511         if (steps % 10 != 0)
8512                 tmp = 0xAAAAAAAB;
8513         else
8514                 tmp = 0x00000000;
8515         intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
8516
8517         tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
8518         tmp &= 0xffff0000;
8519         tmp |= sscdivintphase[idx];
8520         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
8521
8522         mutex_unlock(&dev_priv->sb_lock);
8523 }
8524
8525 #undef BEND_IDX
8526
8527 static void lpt_init_pch_refclk(struct drm_device *dev)
8528 {
8529         struct intel_encoder *encoder;
8530         bool has_vga = false;
8531
8532         for_each_intel_encoder(dev, encoder) {
8533                 switch (encoder->type) {
8534                 case INTEL_OUTPUT_ANALOG:
8535                         has_vga = true;
8536                         break;
8537                 default:
8538                         break;
8539                 }
8540         }
8541
8542         if (has_vga) {
8543                 lpt_bend_clkout_dp(to_i915(dev), 0);
8544                 lpt_enable_clkout_dp(dev, true, true);
8545         } else {
8546                 lpt_disable_clkout_dp(dev);
8547         }
8548 }
8549
8550 /*
8551  * Initialize reference clocks when the driver loads
8552  */
8553 void intel_init_pch_refclk(struct drm_device *dev)
8554 {
8555         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8556                 ironlake_init_pch_refclk(dev);
8557         else if (HAS_PCH_LPT(dev))
8558                 lpt_init_pch_refclk(dev);
8559 }
8560
8561 static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
8562 {
8563         struct drm_device *dev = crtc_state->base.crtc->dev;
8564         struct drm_i915_private *dev_priv = dev->dev_private;
8565         struct drm_atomic_state *state = crtc_state->base.state;
8566         struct drm_connector *connector;
8567         struct drm_connector_state *connector_state;
8568         struct intel_encoder *encoder;
8569         int num_connectors = 0, i;
8570         bool is_lvds = false;
8571
8572         for_each_connector_in_state(state, connector, connector_state, i) {
8573                 if (connector_state->crtc != crtc_state->base.crtc)
8574                         continue;
8575
8576                 encoder = to_intel_encoder(connector_state->best_encoder);
8577
8578                 switch (encoder->type) {
8579                 case INTEL_OUTPUT_LVDS:
8580                         is_lvds = true;
8581                         break;
8582                 default:
8583                         break;
8584                 }
8585                 num_connectors++;
8586         }
8587
8588         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
8589                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8590                               dev_priv->vbt.lvds_ssc_freq);
8591                 return dev_priv->vbt.lvds_ssc_freq;
8592         }
8593
8594         return 120000;
8595 }
8596
8597 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8598 {
8599         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8600         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8601         int pipe = intel_crtc->pipe;
8602         uint32_t val;
8603
8604         val = 0;
8605
8606         switch (intel_crtc->config->pipe_bpp) {
8607         case 18:
8608                 val |= PIPECONF_6BPC;
8609                 break;
8610         case 24:
8611                 val |= PIPECONF_8BPC;
8612                 break;
8613         case 30:
8614                 val |= PIPECONF_10BPC;
8615                 break;
8616         case 36:
8617                 val |= PIPECONF_12BPC;
8618                 break;
8619         default:
8620                 /* Case prevented by intel_choose_pipe_bpp_dither. */
8621                 BUG();
8622         }
8623
8624         if (intel_crtc->config->dither)
8625                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8626
8627         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8628                 val |= PIPECONF_INTERLACED_ILK;
8629         else
8630                 val |= PIPECONF_PROGRESSIVE;
8631
8632         if (intel_crtc->config->limited_color_range)
8633                 val |= PIPECONF_COLOR_RANGE_SELECT;
8634
8635         I915_WRITE(PIPECONF(pipe), val);
8636         POSTING_READ(PIPECONF(pipe));
8637 }
8638
8639 /*
8640  * Set up the pipe CSC unit.
8641  *
8642  * Currently only full range RGB to limited range RGB conversion
8643  * is supported, but eventually this should handle various
8644  * RGB<->YCbCr scenarios as well.
8645  */
8646 static void intel_set_pipe_csc(struct drm_crtc *crtc)
8647 {
8648         struct drm_device *dev = crtc->dev;
8649         struct drm_i915_private *dev_priv = dev->dev_private;
8650         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8651         int pipe = intel_crtc->pipe;
8652         uint16_t coeff = 0x7800; /* 1.0 */
8653
8654         /*
8655          * TODO: Check what kind of values actually come out of the pipe
8656          * with these coeff/postoff values and adjust to get the best
8657          * accuracy. Perhaps we even need to take the bpc value into
8658          * consideration.
8659          */
8660
8661         if (intel_crtc->config->limited_color_range)
8662                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8663
8664         /*
8665          * GY/GU and RY/RU should be the other way around according
8666          * to BSpec, but reality doesn't agree. Just set them up in
8667          * a way that results in the correct picture.
8668          */
8669         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8670         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8671
8672         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8673         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8674
8675         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8676         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8677
8678         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8679         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8680         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8681
8682         if (INTEL_INFO(dev)->gen > 6) {
8683                 uint16_t postoff = 0;
8684
8685                 if (intel_crtc->config->limited_color_range)
8686                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
8687
8688                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8689                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8690                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8691
8692                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8693         } else {
8694                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8695
8696                 if (intel_crtc->config->limited_color_range)
8697                         mode |= CSC_BLACK_SCREEN_OFFSET;
8698
8699                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8700         }
8701 }
8702
8703 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8704 {
8705         struct drm_device *dev = crtc->dev;
8706         struct drm_i915_private *dev_priv = dev->dev_private;
8707         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8708         enum pipe pipe = intel_crtc->pipe;
8709         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8710         uint32_t val;
8711
8712         val = 0;
8713
8714         if (IS_HASWELL(dev) && intel_crtc->config->dither)
8715                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8716
8717         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8718                 val |= PIPECONF_INTERLACED_ILK;
8719         else
8720                 val |= PIPECONF_PROGRESSIVE;
8721
8722         I915_WRITE(PIPECONF(cpu_transcoder), val);
8723         POSTING_READ(PIPECONF(cpu_transcoder));
8724
8725         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8726         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
8727
8728         if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
8729                 val = 0;
8730
8731                 switch (intel_crtc->config->pipe_bpp) {
8732                 case 18:
8733                         val |= PIPEMISC_DITHER_6_BPC;
8734                         break;
8735                 case 24:
8736                         val |= PIPEMISC_DITHER_8_BPC;
8737                         break;
8738                 case 30:
8739                         val |= PIPEMISC_DITHER_10_BPC;
8740                         break;
8741                 case 36:
8742                         val |= PIPEMISC_DITHER_12_BPC;
8743                         break;
8744                 default:
8745                         /* Case prevented by pipe_config_set_bpp. */
8746                         BUG();
8747                 }
8748
8749                 if (intel_crtc->config->dither)
8750                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8751
8752                 I915_WRITE(PIPEMISC(pipe), val);
8753         }
8754 }
8755
8756 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
8757                                     struct intel_crtc_state *crtc_state,
8758                                     intel_clock_t *clock,
8759                                     bool *has_reduced_clock,
8760                                     intel_clock_t *reduced_clock)
8761 {
8762         struct drm_device *dev = crtc->dev;
8763         struct drm_i915_private *dev_priv = dev->dev_private;
8764         int refclk;
8765         const intel_limit_t *limit;
8766         bool ret;
8767
8768         refclk = ironlake_get_refclk(crtc_state);
8769
8770         /*
8771          * Returns a set of divisors for the desired target clock with the given
8772          * refclk, or FALSE.  The returned values represent the clock equation:
8773          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8774          */
8775         limit = intel_limit(crtc_state, refclk);
8776         ret = dev_priv->display.find_dpll(limit, crtc_state,
8777                                           crtc_state->port_clock,
8778                                           refclk, NULL, clock);
8779         if (!ret)
8780                 return false;
8781
8782         return true;
8783 }
8784
8785 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8786 {
8787         /*
8788          * Account for spread spectrum to avoid
8789          * oversubscribing the link. Max center spread
8790          * is 2.5%; use 5% for safety's sake.
8791          */
8792         u32 bps = target_clock * bpp * 21 / 20;
8793         return DIV_ROUND_UP(bps, link_bw * 8);
8794 }
8795
8796 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8797 {
8798         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8799 }
8800
8801 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8802                                       struct intel_crtc_state *crtc_state,
8803                                       u32 *fp,
8804                                       intel_clock_t *reduced_clock, u32 *fp2)
8805 {
8806         struct drm_crtc *crtc = &intel_crtc->base;
8807         struct drm_device *dev = crtc->dev;
8808         struct drm_i915_private *dev_priv = dev->dev_private;
8809         struct drm_atomic_state *state = crtc_state->base.state;
8810         struct drm_connector *connector;
8811         struct drm_connector_state *connector_state;
8812         struct intel_encoder *encoder;
8813         uint32_t dpll;
8814         int factor, num_connectors = 0, i;
8815         bool is_lvds = false, is_sdvo = false;
8816
8817         for_each_connector_in_state(state, connector, connector_state, i) {
8818                 if (connector_state->crtc != crtc_state->base.crtc)
8819                         continue;
8820
8821                 encoder = to_intel_encoder(connector_state->best_encoder);
8822
8823                 switch (encoder->type) {
8824                 case INTEL_OUTPUT_LVDS:
8825                         is_lvds = true;
8826                         break;
8827                 case INTEL_OUTPUT_SDVO:
8828                 case INTEL_OUTPUT_HDMI:
8829                         is_sdvo = true;
8830                         break;
8831                 default:
8832                         break;
8833                 }
8834
8835                 num_connectors++;
8836         }
8837
8838         /* Enable autotuning of the PLL clock (if permissible) */
8839         factor = 21;
8840         if (is_lvds) {
8841                 if ((intel_panel_use_ssc(dev_priv) &&
8842                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
8843                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8844                         factor = 25;
8845         } else if (crtc_state->sdvo_tv_clock)
8846                 factor = 20;
8847
8848         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8849                 *fp |= FP_CB_TUNE;
8850
8851         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8852                 *fp2 |= FP_CB_TUNE;
8853
8854         dpll = 0;
8855
8856         if (is_lvds)
8857                 dpll |= DPLLB_MODE_LVDS;
8858         else
8859                 dpll |= DPLLB_MODE_DAC_SERIAL;
8860
8861         dpll |= (crtc_state->pixel_multiplier - 1)
8862                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8863
8864         if (is_sdvo)
8865                 dpll |= DPLL_SDVO_HIGH_SPEED;
8866         if (crtc_state->has_dp_encoder)
8867                 dpll |= DPLL_SDVO_HIGH_SPEED;
8868
8869         /* compute bitmask from p1 value */
8870         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8871         /* also FPA1 */
8872         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8873
8874         switch (crtc_state->dpll.p2) {
8875         case 5:
8876                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8877                 break;
8878         case 7:
8879                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8880                 break;
8881         case 10:
8882                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8883                 break;
8884         case 14:
8885                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8886                 break;
8887         }
8888
8889         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
8890                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8891         else
8892                 dpll |= PLL_REF_INPUT_DREFCLK;
8893
8894         return dpll | DPLL_VCO_ENABLE;
8895 }
8896
8897 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8898                                        struct intel_crtc_state *crtc_state)
8899 {
8900         struct drm_device *dev = crtc->base.dev;
8901         intel_clock_t clock, reduced_clock;
8902         u32 dpll = 0, fp = 0, fp2 = 0;
8903         bool ok, has_reduced_clock = false;
8904         bool is_lvds = false;
8905         struct intel_shared_dpll *pll;
8906
8907         memset(&crtc_state->dpll_hw_state, 0,
8908                sizeof(crtc_state->dpll_hw_state));
8909
8910         is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS);
8911
8912         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8913              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
8914
8915         ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
8916                                      &has_reduced_clock, &reduced_clock);
8917         if (!ok && !crtc_state->clock_set) {
8918                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8919                 return -EINVAL;
8920         }
8921         /* Compat-code for transition, will disappear. */
8922         if (!crtc_state->clock_set) {
8923                 crtc_state->dpll.n = clock.n;
8924                 crtc_state->dpll.m1 = clock.m1;
8925                 crtc_state->dpll.m2 = clock.m2;
8926                 crtc_state->dpll.p1 = clock.p1;
8927                 crtc_state->dpll.p2 = clock.p2;
8928         }
8929
8930         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8931         if (crtc_state->has_pch_encoder) {
8932                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8933                 if (has_reduced_clock)
8934                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
8935
8936                 dpll = ironlake_compute_dpll(crtc, crtc_state,
8937                                              &fp, &reduced_clock,
8938                                              has_reduced_clock ? &fp2 : NULL);
8939
8940                 crtc_state->dpll_hw_state.dpll = dpll;
8941                 crtc_state->dpll_hw_state.fp0 = fp;
8942                 if (has_reduced_clock)
8943                         crtc_state->dpll_hw_state.fp1 = fp2;
8944                 else
8945                         crtc_state->dpll_hw_state.fp1 = fp;
8946
8947                 pll = intel_get_shared_dpll(crtc, crtc_state, NULL);
8948                 if (pll == NULL) {
8949                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8950                                          pipe_name(crtc->pipe));
8951                         return -EINVAL;
8952                 }
8953         }
8954
8955         if (is_lvds && has_reduced_clock)
8956                 crtc->lowfreq_avail = true;
8957         else
8958                 crtc->lowfreq_avail = false;
8959
8960         return 0;
8961 }
8962
8963 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8964                                          struct intel_link_m_n *m_n)
8965 {
8966         struct drm_device *dev = crtc->base.dev;
8967         struct drm_i915_private *dev_priv = dev->dev_private;
8968         enum pipe pipe = crtc->pipe;
8969
8970         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8971         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8972         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8973                 & ~TU_SIZE_MASK;
8974         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8975         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8976                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8977 }
8978
8979 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8980                                          enum transcoder transcoder,
8981                                          struct intel_link_m_n *m_n,
8982                                          struct intel_link_m_n *m2_n2)
8983 {
8984         struct drm_device *dev = crtc->base.dev;
8985         struct drm_i915_private *dev_priv = dev->dev_private;
8986         enum pipe pipe = crtc->pipe;
8987
8988         if (INTEL_INFO(dev)->gen >= 5) {
8989                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8990                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8991                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8992                         & ~TU_SIZE_MASK;
8993                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8994                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8995                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8996                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8997                  * gen < 8) and if DRRS is supported (to make sure the
8998                  * registers are not unnecessarily read).
8999                  */
9000                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
9001                         crtc->config->has_drrs) {
9002                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9003                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9004                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9005                                         & ~TU_SIZE_MASK;
9006                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9007                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9008                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9009                 }
9010         } else {
9011                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9012                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9013                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9014                         & ~TU_SIZE_MASK;
9015                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9016                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9017                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9018         }
9019 }
9020
9021 void intel_dp_get_m_n(struct intel_crtc *crtc,
9022                       struct intel_crtc_state *pipe_config)
9023 {
9024         if (pipe_config->has_pch_encoder)
9025                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9026         else
9027                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9028                                              &pipe_config->dp_m_n,
9029                                              &pipe_config->dp_m2_n2);
9030 }
9031
9032 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9033                                         struct intel_crtc_state *pipe_config)
9034 {
9035         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9036                                      &pipe_config->fdi_m_n, NULL);
9037 }
9038
9039 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9040                                     struct intel_crtc_state *pipe_config)
9041 {
9042         struct drm_device *dev = crtc->base.dev;
9043         struct drm_i915_private *dev_priv = dev->dev_private;
9044         struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9045         uint32_t ps_ctrl = 0;
9046         int id = -1;
9047         int i;
9048
9049         /* find scaler attached to this pipe */
9050         for (i = 0; i < crtc->num_scalers; i++) {
9051                 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9052                 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9053                         id = i;
9054                         pipe_config->pch_pfit.enabled = true;
9055                         pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9056                         pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9057                         break;
9058                 }
9059         }
9060
9061         scaler_state->scaler_id = id;
9062         if (id >= 0) {
9063                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9064         } else {
9065                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9066         }
9067 }
9068
9069 static void
9070 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9071                                  struct intel_initial_plane_config *plane_config)
9072 {
9073         struct drm_device *dev = crtc->base.dev;
9074         struct drm_i915_private *dev_priv = dev->dev_private;
9075         u32 val, base, offset, stride_mult, tiling;
9076         int pipe = crtc->pipe;
9077         int fourcc, pixel_format;
9078         unsigned int aligned_height;
9079         struct drm_framebuffer *fb;
9080         struct intel_framebuffer *intel_fb;
9081
9082         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9083         if (!intel_fb) {
9084                 DRM_DEBUG_KMS("failed to alloc fb\n");
9085                 return;
9086         }
9087
9088         fb = &intel_fb->base;
9089
9090         val = I915_READ(PLANE_CTL(pipe, 0));
9091         if (!(val & PLANE_CTL_ENABLE))
9092                 goto error;
9093
9094         pixel_format = val & PLANE_CTL_FORMAT_MASK;
9095         fourcc = skl_format_to_fourcc(pixel_format,
9096                                       val & PLANE_CTL_ORDER_RGBX,
9097                                       val & PLANE_CTL_ALPHA_MASK);
9098         fb->pixel_format = fourcc;
9099         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9100
9101         tiling = val & PLANE_CTL_TILED_MASK;
9102         switch (tiling) {
9103         case PLANE_CTL_TILED_LINEAR:
9104                 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9105                 break;
9106         case PLANE_CTL_TILED_X:
9107                 plane_config->tiling = I915_TILING_X;
9108                 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9109                 break;
9110         case PLANE_CTL_TILED_Y:
9111                 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9112                 break;
9113         case PLANE_CTL_TILED_YF:
9114                 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9115                 break;
9116         default:
9117                 MISSING_CASE(tiling);
9118                 goto error;
9119         }
9120
9121         base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9122         plane_config->base = base;
9123
9124         offset = I915_READ(PLANE_OFFSET(pipe, 0));
9125
9126         val = I915_READ(PLANE_SIZE(pipe, 0));
9127         fb->height = ((val >> 16) & 0xfff) + 1;
9128         fb->width = ((val >> 0) & 0x1fff) + 1;
9129
9130         val = I915_READ(PLANE_STRIDE(pipe, 0));
9131         stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
9132                                                 fb->pixel_format);
9133         fb->pitches[0] = (val & 0x3ff) * stride_mult;
9134
9135         aligned_height = intel_fb_align_height(dev, fb->height,
9136                                                fb->pixel_format,
9137                                                fb->modifier[0]);
9138
9139         plane_config->size = fb->pitches[0] * aligned_height;
9140
9141         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9142                       pipe_name(pipe), fb->width, fb->height,
9143                       fb->bits_per_pixel, base, fb->pitches[0],
9144                       plane_config->size);
9145
9146         plane_config->fb = intel_fb;
9147         return;
9148
9149 error:
9150         kfree(fb);
9151 }
9152
9153 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9154                                      struct intel_crtc_state *pipe_config)
9155 {
9156         struct drm_device *dev = crtc->base.dev;
9157         struct drm_i915_private *dev_priv = dev->dev_private;
9158         uint32_t tmp;
9159
9160         tmp = I915_READ(PF_CTL(crtc->pipe));
9161
9162         if (tmp & PF_ENABLE) {
9163                 pipe_config->pch_pfit.enabled = true;
9164                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9165                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9166
9167                 /* We currently do not free assignements of panel fitters on
9168                  * ivb/hsw (since we don't use the higher upscaling modes which
9169                  * differentiates them) so just WARN about this case for now. */
9170                 if (IS_GEN7(dev)) {
9171                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9172                                 PF_PIPE_SEL_IVB(crtc->pipe));
9173                 }
9174         }
9175 }
9176
9177 static void
9178 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9179                                   struct intel_initial_plane_config *plane_config)
9180 {
9181         struct drm_device *dev = crtc->base.dev;
9182         struct drm_i915_private *dev_priv = dev->dev_private;
9183         u32 val, base, offset;
9184         int pipe = crtc->pipe;
9185         int fourcc, pixel_format;
9186         unsigned int aligned_height;
9187         struct drm_framebuffer *fb;
9188         struct intel_framebuffer *intel_fb;
9189
9190         val = I915_READ(DSPCNTR(pipe));
9191         if (!(val & DISPLAY_PLANE_ENABLE))
9192                 return;
9193
9194         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9195         if (!intel_fb) {
9196                 DRM_DEBUG_KMS("failed to alloc fb\n");
9197                 return;
9198         }
9199
9200         fb = &intel_fb->base;
9201
9202         if (INTEL_INFO(dev)->gen >= 4) {
9203                 if (val & DISPPLANE_TILED) {
9204                         plane_config->tiling = I915_TILING_X;
9205                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9206                 }
9207         }
9208
9209         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9210         fourcc = i9xx_format_to_fourcc(pixel_format);
9211         fb->pixel_format = fourcc;
9212         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9213
9214         base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9215         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9216                 offset = I915_READ(DSPOFFSET(pipe));
9217         } else {
9218                 if (plane_config->tiling)
9219                         offset = I915_READ(DSPTILEOFF(pipe));
9220                 else
9221                         offset = I915_READ(DSPLINOFF(pipe));
9222         }
9223         plane_config->base = base;
9224
9225         val = I915_READ(PIPESRC(pipe));
9226         fb->width = ((val >> 16) & 0xfff) + 1;
9227         fb->height = ((val >> 0) & 0xfff) + 1;
9228
9229         val = I915_READ(DSPSTRIDE(pipe));
9230         fb->pitches[0] = val & 0xffffffc0;
9231
9232         aligned_height = intel_fb_align_height(dev, fb->height,
9233                                                fb->pixel_format,
9234                                                fb->modifier[0]);
9235
9236         plane_config->size = fb->pitches[0] * aligned_height;
9237
9238         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9239                       pipe_name(pipe), fb->width, fb->height,
9240                       fb->bits_per_pixel, base, fb->pitches[0],
9241                       plane_config->size);
9242
9243         plane_config->fb = intel_fb;
9244 }
9245
9246 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9247                                      struct intel_crtc_state *pipe_config)
9248 {
9249         struct drm_device *dev = crtc->base.dev;
9250         struct drm_i915_private *dev_priv = dev->dev_private;
9251         enum intel_display_power_domain power_domain;
9252         uint32_t tmp;
9253         bool ret;
9254
9255         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9256         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9257                 return false;
9258
9259         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9260         pipe_config->shared_dpll = NULL;
9261
9262         ret = false;
9263         tmp = I915_READ(PIPECONF(crtc->pipe));
9264         if (!(tmp & PIPECONF_ENABLE))
9265                 goto out;
9266
9267         switch (tmp & PIPECONF_BPC_MASK) {
9268         case PIPECONF_6BPC:
9269                 pipe_config->pipe_bpp = 18;
9270                 break;
9271         case PIPECONF_8BPC:
9272                 pipe_config->pipe_bpp = 24;
9273                 break;
9274         case PIPECONF_10BPC:
9275                 pipe_config->pipe_bpp = 30;
9276                 break;
9277         case PIPECONF_12BPC:
9278                 pipe_config->pipe_bpp = 36;
9279                 break;
9280         default:
9281                 break;
9282         }
9283
9284         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9285                 pipe_config->limited_color_range = true;
9286
9287         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9288                 struct intel_shared_dpll *pll;
9289                 enum intel_dpll_id pll_id;
9290
9291                 pipe_config->has_pch_encoder = true;
9292
9293                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9294                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9295                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9296
9297                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9298
9299                 if (HAS_PCH_IBX(dev_priv->dev)) {
9300                         pll_id = (enum intel_dpll_id) crtc->pipe;
9301                 } else {
9302                         tmp = I915_READ(PCH_DPLL_SEL);
9303                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9304                                 pll_id = DPLL_ID_PCH_PLL_B;
9305                         else
9306                                 pll_id= DPLL_ID_PCH_PLL_A;
9307                 }
9308
9309                 pipe_config->shared_dpll =
9310                         intel_get_shared_dpll_by_id(dev_priv, pll_id);
9311                 pll = pipe_config->shared_dpll;
9312
9313                 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9314                                                  &pipe_config->dpll_hw_state));
9315
9316                 tmp = pipe_config->dpll_hw_state.dpll;
9317                 pipe_config->pixel_multiplier =
9318                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9319                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9320
9321                 ironlake_pch_clock_get(crtc, pipe_config);
9322         } else {
9323                 pipe_config->pixel_multiplier = 1;
9324         }
9325
9326         intel_get_pipe_timings(crtc, pipe_config);
9327
9328         ironlake_get_pfit_config(crtc, pipe_config);
9329
9330         ret = true;
9331
9332 out:
9333         intel_display_power_put(dev_priv, power_domain);
9334
9335         return ret;
9336 }
9337
9338 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9339 {
9340         struct drm_device *dev = dev_priv->dev;
9341         struct intel_crtc *crtc;
9342
9343         for_each_intel_crtc(dev, crtc)
9344                 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9345                      pipe_name(crtc->pipe));
9346
9347         I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9348         I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9349         I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9350         I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9351         I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9352         I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9353              "CPU PWM1 enabled\n");
9354         if (IS_HASWELL(dev))
9355                 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9356                      "CPU PWM2 enabled\n");
9357         I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9358              "PCH PWM1 enabled\n");
9359         I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9360              "Utility pin enabled\n");
9361         I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9362
9363         /*
9364          * In theory we can still leave IRQs enabled, as long as only the HPD
9365          * interrupts remain enabled. We used to check for that, but since it's
9366          * gen-specific and since we only disable LCPLL after we fully disable
9367          * the interrupts, the check below should be enough.
9368          */
9369         I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9370 }
9371
9372 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9373 {
9374         struct drm_device *dev = dev_priv->dev;
9375
9376         if (IS_HASWELL(dev))
9377                 return I915_READ(D_COMP_HSW);
9378         else
9379                 return I915_READ(D_COMP_BDW);
9380 }
9381
9382 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9383 {
9384         struct drm_device *dev = dev_priv->dev;
9385
9386         if (IS_HASWELL(dev)) {
9387                 mutex_lock(&dev_priv->rps.hw_lock);
9388                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9389                                             val))
9390                         DRM_ERROR("Failed to write to D_COMP\n");
9391                 mutex_unlock(&dev_priv->rps.hw_lock);
9392         } else {
9393                 I915_WRITE(D_COMP_BDW, val);
9394                 POSTING_READ(D_COMP_BDW);
9395         }
9396 }
9397
9398 /*
9399  * This function implements pieces of two sequences from BSpec:
9400  * - Sequence for display software to disable LCPLL
9401  * - Sequence for display software to allow package C8+
9402  * The steps implemented here are just the steps that actually touch the LCPLL
9403  * register. Callers should take care of disabling all the display engine
9404  * functions, doing the mode unset, fixing interrupts, etc.
9405  */
9406 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9407                               bool switch_to_fclk, bool allow_power_down)
9408 {
9409         uint32_t val;
9410
9411         assert_can_disable_lcpll(dev_priv);
9412
9413         val = I915_READ(LCPLL_CTL);
9414
9415         if (switch_to_fclk) {
9416                 val |= LCPLL_CD_SOURCE_FCLK;
9417                 I915_WRITE(LCPLL_CTL, val);
9418
9419                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9420                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
9421                         DRM_ERROR("Switching to FCLK failed\n");
9422
9423                 val = I915_READ(LCPLL_CTL);
9424         }
9425
9426         val |= LCPLL_PLL_DISABLE;
9427         I915_WRITE(LCPLL_CTL, val);
9428         POSTING_READ(LCPLL_CTL);
9429
9430         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9431                 DRM_ERROR("LCPLL still locked\n");
9432
9433         val = hsw_read_dcomp(dev_priv);
9434         val |= D_COMP_COMP_DISABLE;
9435         hsw_write_dcomp(dev_priv, val);
9436         ndelay(100);
9437
9438         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9439                      1))
9440                 DRM_ERROR("D_COMP RCOMP still in progress\n");
9441
9442         if (allow_power_down) {
9443                 val = I915_READ(LCPLL_CTL);
9444                 val |= LCPLL_POWER_DOWN_ALLOW;
9445                 I915_WRITE(LCPLL_CTL, val);
9446                 POSTING_READ(LCPLL_CTL);
9447         }
9448 }
9449
9450 /*
9451  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9452  * source.
9453  */
9454 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9455 {
9456         uint32_t val;
9457
9458         val = I915_READ(LCPLL_CTL);
9459
9460         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9461                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9462                 return;
9463
9464         /*
9465          * Make sure we're not on PC8 state before disabling PC8, otherwise
9466          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9467          */
9468         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9469
9470         if (val & LCPLL_POWER_DOWN_ALLOW) {
9471                 val &= ~LCPLL_POWER_DOWN_ALLOW;
9472                 I915_WRITE(LCPLL_CTL, val);
9473                 POSTING_READ(LCPLL_CTL);
9474         }
9475
9476         val = hsw_read_dcomp(dev_priv);
9477         val |= D_COMP_COMP_FORCE;
9478         val &= ~D_COMP_COMP_DISABLE;
9479         hsw_write_dcomp(dev_priv, val);
9480
9481         val = I915_READ(LCPLL_CTL);
9482         val &= ~LCPLL_PLL_DISABLE;
9483         I915_WRITE(LCPLL_CTL, val);
9484
9485         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9486                 DRM_ERROR("LCPLL not locked yet\n");
9487
9488         if (val & LCPLL_CD_SOURCE_FCLK) {
9489                 val = I915_READ(LCPLL_CTL);
9490                 val &= ~LCPLL_CD_SOURCE_FCLK;
9491                 I915_WRITE(LCPLL_CTL, val);
9492
9493                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9494                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9495                         DRM_ERROR("Switching back to LCPLL failed\n");
9496         }
9497
9498         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9499         intel_update_cdclk(dev_priv->dev);
9500 }
9501
9502 /*
9503  * Package states C8 and deeper are really deep PC states that can only be
9504  * reached when all the devices on the system allow it, so even if the graphics
9505  * device allows PC8+, it doesn't mean the system will actually get to these
9506  * states. Our driver only allows PC8+ when going into runtime PM.
9507  *
9508  * The requirements for PC8+ are that all the outputs are disabled, the power
9509  * well is disabled and most interrupts are disabled, and these are also
9510  * requirements for runtime PM. When these conditions are met, we manually do
9511  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9512  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9513  * hang the machine.
9514  *
9515  * When we really reach PC8 or deeper states (not just when we allow it) we lose
9516  * the state of some registers, so when we come back from PC8+ we need to
9517  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9518  * need to take care of the registers kept by RC6. Notice that this happens even
9519  * if we don't put the device in PCI D3 state (which is what currently happens
9520  * because of the runtime PM support).
9521  *
9522  * For more, read "Display Sequences for Package C8" on the hardware
9523  * documentation.
9524  */
9525 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9526 {
9527         struct drm_device *dev = dev_priv->dev;
9528         uint32_t val;
9529
9530         DRM_DEBUG_KMS("Enabling package C8+\n");
9531
9532         if (HAS_PCH_LPT_LP(dev)) {
9533                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9534                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9535                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9536         }
9537
9538         lpt_disable_clkout_dp(dev);
9539         hsw_disable_lcpll(dev_priv, true, true);
9540 }
9541
9542 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9543 {
9544         struct drm_device *dev = dev_priv->dev;
9545         uint32_t val;
9546
9547         DRM_DEBUG_KMS("Disabling package C8+\n");
9548
9549         hsw_restore_lcpll(dev_priv);
9550         lpt_init_pch_refclk(dev);
9551
9552         if (HAS_PCH_LPT_LP(dev)) {
9553                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9554                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9555                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9556         }
9557 }
9558
9559 static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9560 {
9561         struct drm_device *dev = old_state->dev;
9562         struct intel_atomic_state *old_intel_state =
9563                 to_intel_atomic_state(old_state);
9564         unsigned int req_cdclk = old_intel_state->dev_cdclk;
9565
9566         broxton_set_cdclk(dev, req_cdclk);
9567 }
9568
9569 /* compute the max rate for new configuration */
9570 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9571 {
9572         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9573         struct drm_i915_private *dev_priv = state->dev->dev_private;
9574         struct drm_crtc *crtc;
9575         struct drm_crtc_state *cstate;
9576         struct intel_crtc_state *crtc_state;
9577         unsigned max_pixel_rate = 0, i;
9578         enum pipe pipe;
9579
9580         memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
9581                sizeof(intel_state->min_pixclk));
9582
9583         for_each_crtc_in_state(state, crtc, cstate, i) {
9584                 int pixel_rate;
9585
9586                 crtc_state = to_intel_crtc_state(cstate);
9587                 if (!crtc_state->base.enable) {
9588                         intel_state->min_pixclk[i] = 0;
9589                         continue;
9590                 }
9591
9592                 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
9593
9594                 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9595                 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
9596                         pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9597
9598                 intel_state->min_pixclk[i] = pixel_rate;
9599         }
9600
9601         for_each_pipe(dev_priv, pipe)
9602                 max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate);
9603
9604         return max_pixel_rate;
9605 }
9606
9607 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9608 {
9609         struct drm_i915_private *dev_priv = dev->dev_private;
9610         uint32_t val, data;
9611         int ret;
9612
9613         if (WARN((I915_READ(LCPLL_CTL) &
9614                   (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9615                    LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9616                    LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9617                    LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9618                  "trying to change cdclk frequency with cdclk not enabled\n"))
9619                 return;
9620
9621         mutex_lock(&dev_priv->rps.hw_lock);
9622         ret = sandybridge_pcode_write(dev_priv,
9623                                       BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9624         mutex_unlock(&dev_priv->rps.hw_lock);
9625         if (ret) {
9626                 DRM_ERROR("failed to inform pcode about cdclk change\n");
9627                 return;
9628         }
9629
9630         val = I915_READ(LCPLL_CTL);
9631         val |= LCPLL_CD_SOURCE_FCLK;
9632         I915_WRITE(LCPLL_CTL, val);
9633
9634         if (wait_for_us(I915_READ(LCPLL_CTL) &
9635                         LCPLL_CD_SOURCE_FCLK_DONE, 1))
9636                 DRM_ERROR("Switching to FCLK failed\n");
9637
9638         val = I915_READ(LCPLL_CTL);
9639         val &= ~LCPLL_CLK_FREQ_MASK;
9640
9641         switch (cdclk) {
9642         case 450000:
9643                 val |= LCPLL_CLK_FREQ_450;
9644                 data = 0;
9645                 break;
9646         case 540000:
9647                 val |= LCPLL_CLK_FREQ_54O_BDW;
9648                 data = 1;
9649                 break;
9650         case 337500:
9651                 val |= LCPLL_CLK_FREQ_337_5_BDW;
9652                 data = 2;
9653                 break;
9654         case 675000:
9655                 val |= LCPLL_CLK_FREQ_675_BDW;
9656                 data = 3;
9657                 break;
9658         default:
9659                 WARN(1, "invalid cdclk frequency\n");
9660                 return;
9661         }
9662
9663         I915_WRITE(LCPLL_CTL, val);
9664
9665         val = I915_READ(LCPLL_CTL);
9666         val &= ~LCPLL_CD_SOURCE_FCLK;
9667         I915_WRITE(LCPLL_CTL, val);
9668
9669         if (wait_for_us((I915_READ(LCPLL_CTL) &
9670                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9671                 DRM_ERROR("Switching back to LCPLL failed\n");
9672
9673         mutex_lock(&dev_priv->rps.hw_lock);
9674         sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9675         mutex_unlock(&dev_priv->rps.hw_lock);
9676
9677         intel_update_cdclk(dev);
9678
9679         WARN(cdclk != dev_priv->cdclk_freq,
9680              "cdclk requested %d kHz but got %d kHz\n",
9681              cdclk, dev_priv->cdclk_freq);
9682 }
9683
9684 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
9685 {
9686         struct drm_i915_private *dev_priv = to_i915(state->dev);
9687         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9688         int max_pixclk = ilk_max_pixel_rate(state);
9689         int cdclk;
9690
9691         /*
9692          * FIXME should also account for plane ratio
9693          * once 64bpp pixel formats are supported.
9694          */
9695         if (max_pixclk > 540000)
9696                 cdclk = 675000;
9697         else if (max_pixclk > 450000)
9698                 cdclk = 540000;
9699         else if (max_pixclk > 337500)
9700                 cdclk = 450000;
9701         else
9702                 cdclk = 337500;
9703
9704         if (cdclk > dev_priv->max_cdclk_freq) {
9705                 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9706                               cdclk, dev_priv->max_cdclk_freq);
9707                 return -EINVAL;
9708         }
9709
9710         intel_state->cdclk = intel_state->dev_cdclk = cdclk;
9711         if (!intel_state->active_crtcs)
9712                 intel_state->dev_cdclk = 337500;
9713
9714         return 0;
9715 }
9716
9717 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9718 {
9719         struct drm_device *dev = old_state->dev;
9720         struct intel_atomic_state *old_intel_state =
9721                 to_intel_atomic_state(old_state);
9722         unsigned req_cdclk = old_intel_state->dev_cdclk;
9723
9724         broadwell_set_cdclk(dev, req_cdclk);
9725 }
9726
9727 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9728                                       struct intel_crtc_state *crtc_state)
9729 {
9730         struct intel_encoder *intel_encoder =
9731                 intel_ddi_get_crtc_new_encoder(crtc_state);
9732
9733         if (intel_encoder->type != INTEL_OUTPUT_DSI) {
9734                 if (!intel_ddi_pll_select(crtc, crtc_state))
9735                         return -EINVAL;
9736         }
9737
9738         crtc->lowfreq_avail = false;
9739
9740         return 0;
9741 }
9742
9743 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9744                                 enum port port,
9745                                 struct intel_crtc_state *pipe_config)
9746 {
9747         enum intel_dpll_id id;
9748
9749         switch (port) {
9750         case PORT_A:
9751                 pipe_config->ddi_pll_sel = SKL_DPLL0;
9752                 id = DPLL_ID_SKL_DPLL1;
9753                 break;
9754         case PORT_B:
9755                 pipe_config->ddi_pll_sel = SKL_DPLL1;
9756                 id = DPLL_ID_SKL_DPLL2;
9757                 break;
9758         case PORT_C:
9759                 pipe_config->ddi_pll_sel = SKL_DPLL2;
9760                 id = DPLL_ID_SKL_DPLL3;
9761                 break;
9762         default:
9763                 DRM_ERROR("Incorrect port type\n");
9764                 return;
9765         }
9766
9767         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9768 }
9769
9770 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9771                                 enum port port,
9772                                 struct intel_crtc_state *pipe_config)
9773 {
9774         enum intel_dpll_id id;
9775         u32 temp;
9776
9777         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9778         pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9779
9780         switch (pipe_config->ddi_pll_sel) {
9781         case SKL_DPLL0:
9782                 id = DPLL_ID_SKL_DPLL0;
9783                 break;
9784         case SKL_DPLL1:
9785                 id = DPLL_ID_SKL_DPLL1;
9786                 break;
9787         case SKL_DPLL2:
9788                 id = DPLL_ID_SKL_DPLL2;
9789                 break;
9790         case SKL_DPLL3:
9791                 id = DPLL_ID_SKL_DPLL3;
9792                 break;
9793         default:
9794                 MISSING_CASE(pipe_config->ddi_pll_sel);
9795                 return;
9796         }
9797
9798         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9799 }
9800
9801 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9802                                 enum port port,
9803                                 struct intel_crtc_state *pipe_config)
9804 {
9805         enum intel_dpll_id id;
9806
9807         pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9808
9809         switch (pipe_config->ddi_pll_sel) {
9810         case PORT_CLK_SEL_WRPLL1:
9811                 id = DPLL_ID_WRPLL1;
9812                 break;
9813         case PORT_CLK_SEL_WRPLL2:
9814                 id = DPLL_ID_WRPLL2;
9815                 break;
9816         case PORT_CLK_SEL_SPLL:
9817                 id = DPLL_ID_SPLL;
9818                 break;
9819         case PORT_CLK_SEL_LCPLL_810:
9820                 id = DPLL_ID_LCPLL_810;
9821                 break;
9822         case PORT_CLK_SEL_LCPLL_1350:
9823                 id = DPLL_ID_LCPLL_1350;
9824                 break;
9825         case PORT_CLK_SEL_LCPLL_2700:
9826                 id = DPLL_ID_LCPLL_2700;
9827                 break;
9828         default:
9829                 MISSING_CASE(pipe_config->ddi_pll_sel);
9830                 /* fall through */
9831         case PORT_CLK_SEL_NONE:
9832                 return;
9833         }
9834
9835         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9836 }
9837
9838 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9839                                        struct intel_crtc_state *pipe_config)
9840 {
9841         struct drm_device *dev = crtc->base.dev;
9842         struct drm_i915_private *dev_priv = dev->dev_private;
9843         struct intel_shared_dpll *pll;
9844         enum port port;
9845         uint32_t tmp;
9846
9847         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9848
9849         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9850
9851         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
9852                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9853         else if (IS_BROXTON(dev))
9854                 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9855         else
9856                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9857
9858         pll = pipe_config->shared_dpll;
9859         if (pll) {
9860                 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9861                                                  &pipe_config->dpll_hw_state));
9862         }
9863
9864         /*
9865          * Haswell has only FDI/PCH transcoder A. It is which is connected to
9866          * DDI E. So just check whether this pipe is wired to DDI E and whether
9867          * the PCH transcoder is on.
9868          */
9869         if (INTEL_INFO(dev)->gen < 9 &&
9870             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9871                 pipe_config->has_pch_encoder = true;
9872
9873                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9874                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9875                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9876
9877                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9878         }
9879 }
9880
9881 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9882                                     struct intel_crtc_state *pipe_config)
9883 {
9884         struct drm_device *dev = crtc->base.dev;
9885         struct drm_i915_private *dev_priv = dev->dev_private;
9886         enum intel_display_power_domain power_domain;
9887         unsigned long power_domain_mask;
9888         uint32_t tmp;
9889         bool ret;
9890
9891         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9892         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9893                 return false;
9894         power_domain_mask = BIT(power_domain);
9895
9896         ret = false;
9897
9898         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9899         pipe_config->shared_dpll = NULL;
9900
9901         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9902         if (tmp & TRANS_DDI_FUNC_ENABLE) {
9903                 enum pipe trans_edp_pipe;
9904                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9905                 default:
9906                         WARN(1, "unknown pipe linked to edp transcoder\n");
9907                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9908                 case TRANS_DDI_EDP_INPUT_A_ON:
9909                         trans_edp_pipe = PIPE_A;
9910                         break;
9911                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9912                         trans_edp_pipe = PIPE_B;
9913                         break;
9914                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9915                         trans_edp_pipe = PIPE_C;
9916                         break;
9917                 }
9918
9919                 if (trans_edp_pipe == crtc->pipe)
9920                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
9921         }
9922
9923         power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
9924         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9925                 goto out;
9926         power_domain_mask |= BIT(power_domain);
9927
9928         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9929         if (!(tmp & PIPECONF_ENABLE))
9930                 goto out;
9931
9932         haswell_get_ddi_port_state(crtc, pipe_config);
9933
9934         intel_get_pipe_timings(crtc, pipe_config);
9935
9936         if (INTEL_INFO(dev)->gen >= 9) {
9937                 skl_init_scalers(dev, crtc, pipe_config);
9938         }
9939
9940         if (INTEL_INFO(dev)->gen >= 9) {
9941                 pipe_config->scaler_state.scaler_id = -1;
9942                 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9943         }
9944
9945         power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9946         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
9947                 power_domain_mask |= BIT(power_domain);
9948                 if (INTEL_INFO(dev)->gen >= 9)
9949                         skylake_get_pfit_config(crtc, pipe_config);
9950                 else
9951                         ironlake_get_pfit_config(crtc, pipe_config);
9952         }
9953
9954         if (IS_HASWELL(dev))
9955                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9956                         (I915_READ(IPS_CTL) & IPS_ENABLE);
9957
9958         if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9959                 pipe_config->pixel_multiplier =
9960                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9961         } else {
9962                 pipe_config->pixel_multiplier = 1;
9963         }
9964
9965         ret = true;
9966
9967 out:
9968         for_each_power_domain(power_domain, power_domain_mask)
9969                 intel_display_power_put(dev_priv, power_domain);
9970
9971         return ret;
9972 }
9973
9974 static void i845_update_cursor(struct drm_crtc *crtc, u32 base,
9975                                const struct intel_plane_state *plane_state)
9976 {
9977         struct drm_device *dev = crtc->dev;
9978         struct drm_i915_private *dev_priv = dev->dev_private;
9979         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9980         uint32_t cntl = 0, size = 0;
9981
9982         if (plane_state && plane_state->visible) {
9983                 unsigned int width = plane_state->base.crtc_w;
9984                 unsigned int height = plane_state->base.crtc_h;
9985                 unsigned int stride = roundup_pow_of_two(width) * 4;
9986
9987                 switch (stride) {
9988                 default:
9989                         WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9990                                   width, stride);
9991                         stride = 256;
9992                         /* fallthrough */
9993                 case 256:
9994                 case 512:
9995                 case 1024:
9996                 case 2048:
9997                         break;
9998                 }
9999
10000                 cntl |= CURSOR_ENABLE |
10001                         CURSOR_GAMMA_ENABLE |
10002                         CURSOR_FORMAT_ARGB |
10003                         CURSOR_STRIDE(stride);
10004
10005                 size = (height << 12) | width;
10006         }
10007
10008         if (intel_crtc->cursor_cntl != 0 &&
10009             (intel_crtc->cursor_base != base ||
10010              intel_crtc->cursor_size != size ||
10011              intel_crtc->cursor_cntl != cntl)) {
10012                 /* On these chipsets we can only modify the base/size/stride
10013                  * whilst the cursor is disabled.
10014                  */
10015                 I915_WRITE(CURCNTR(PIPE_A), 0);
10016                 POSTING_READ(CURCNTR(PIPE_A));
10017                 intel_crtc->cursor_cntl = 0;
10018         }
10019
10020         if (intel_crtc->cursor_base != base) {
10021                 I915_WRITE(CURBASE(PIPE_A), base);
10022                 intel_crtc->cursor_base = base;
10023         }
10024
10025         if (intel_crtc->cursor_size != size) {
10026                 I915_WRITE(CURSIZE, size);
10027                 intel_crtc->cursor_size = size;
10028         }
10029
10030         if (intel_crtc->cursor_cntl != cntl) {
10031                 I915_WRITE(CURCNTR(PIPE_A), cntl);
10032                 POSTING_READ(CURCNTR(PIPE_A));
10033                 intel_crtc->cursor_cntl = cntl;
10034         }
10035 }
10036
10037 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base,
10038                                const struct intel_plane_state *plane_state)
10039 {
10040         struct drm_device *dev = crtc->dev;
10041         struct drm_i915_private *dev_priv = dev->dev_private;
10042         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10043         int pipe = intel_crtc->pipe;
10044         uint32_t cntl = 0;
10045
10046         if (plane_state && plane_state->visible) {
10047                 cntl = MCURSOR_GAMMA_ENABLE;
10048                 switch (plane_state->base.crtc_w) {
10049                         case 64:
10050                                 cntl |= CURSOR_MODE_64_ARGB_AX;
10051                                 break;
10052                         case 128:
10053                                 cntl |= CURSOR_MODE_128_ARGB_AX;
10054                                 break;
10055                         case 256:
10056                                 cntl |= CURSOR_MODE_256_ARGB_AX;
10057                                 break;
10058                         default:
10059                                 MISSING_CASE(plane_state->base.crtc_w);
10060                                 return;
10061                 }
10062                 cntl |= pipe << 28; /* Connect to correct pipe */
10063
10064                 if (HAS_DDI(dev))
10065                         cntl |= CURSOR_PIPE_CSC_ENABLE;
10066
10067                 if (plane_state->base.rotation == BIT(DRM_ROTATE_180))
10068                         cntl |= CURSOR_ROTATE_180;
10069         }
10070
10071         if (intel_crtc->cursor_cntl != cntl) {
10072                 I915_WRITE(CURCNTR(pipe), cntl);
10073                 POSTING_READ(CURCNTR(pipe));
10074                 intel_crtc->cursor_cntl = cntl;
10075         }
10076
10077         /* and commit changes on next vblank */
10078         I915_WRITE(CURBASE(pipe), base);
10079         POSTING_READ(CURBASE(pipe));
10080
10081         intel_crtc->cursor_base = base;
10082 }
10083
10084 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10085 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10086                                      const struct intel_plane_state *plane_state)
10087 {
10088         struct drm_device *dev = crtc->dev;
10089         struct drm_i915_private *dev_priv = dev->dev_private;
10090         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10091         int pipe = intel_crtc->pipe;
10092         u32 base = intel_crtc->cursor_addr;
10093         u32 pos = 0;
10094
10095         if (plane_state) {
10096                 int x = plane_state->base.crtc_x;
10097                 int y = plane_state->base.crtc_y;
10098
10099                 if (x < 0) {
10100                         pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10101                         x = -x;
10102                 }
10103                 pos |= x << CURSOR_X_SHIFT;
10104
10105                 if (y < 0) {
10106                         pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10107                         y = -y;
10108                 }
10109                 pos |= y << CURSOR_Y_SHIFT;
10110
10111                 /* ILK+ do this automagically */
10112                 if (HAS_GMCH_DISPLAY(dev) &&
10113                     plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
10114                         base += (plane_state->base.crtc_h *
10115                                  plane_state->base.crtc_w - 1) * 4;
10116                 }
10117         }
10118
10119         I915_WRITE(CURPOS(pipe), pos);
10120
10121         if (IS_845G(dev) || IS_I865G(dev))
10122                 i845_update_cursor(crtc, base, plane_state);
10123         else
10124                 i9xx_update_cursor(crtc, base, plane_state);
10125 }
10126
10127 static bool cursor_size_ok(struct drm_device *dev,
10128                            uint32_t width, uint32_t height)
10129 {
10130         if (width == 0 || height == 0)
10131                 return false;
10132
10133         /*
10134          * 845g/865g are special in that they are only limited by
10135          * the width of their cursors, the height is arbitrary up to
10136          * the precision of the register. Everything else requires
10137          * square cursors, limited to a few power-of-two sizes.
10138          */
10139         if (IS_845G(dev) || IS_I865G(dev)) {
10140                 if ((width & 63) != 0)
10141                         return false;
10142
10143                 if (width > (IS_845G(dev) ? 64 : 512))
10144                         return false;
10145
10146                 if (height > 1023)
10147                         return false;
10148         } else {
10149                 switch (width | height) {
10150                 case 256:
10151                 case 128:
10152                         if (IS_GEN2(dev))
10153                                 return false;
10154                 case 64:
10155                         break;
10156                 default:
10157                         return false;
10158                 }
10159         }
10160
10161         return true;
10162 }
10163
10164 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
10165                                  u16 *blue, uint32_t start, uint32_t size)
10166 {
10167         int end = (start + size > 256) ? 256 : start + size, i;
10168         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10169
10170         for (i = start; i < end; i++) {
10171                 intel_crtc->lut_r[i] = red[i] >> 8;
10172                 intel_crtc->lut_g[i] = green[i] >> 8;
10173                 intel_crtc->lut_b[i] = blue[i] >> 8;
10174         }
10175
10176         intel_crtc_load_lut(crtc);
10177 }
10178
10179 /* VESA 640x480x72Hz mode to set on the pipe */
10180 static struct drm_display_mode load_detect_mode = {
10181         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10182                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10183 };
10184
10185 struct drm_framebuffer *
10186 __intel_framebuffer_create(struct drm_device *dev,
10187                            struct drm_mode_fb_cmd2 *mode_cmd,
10188                            struct drm_i915_gem_object *obj)
10189 {
10190         struct intel_framebuffer *intel_fb;
10191         int ret;
10192
10193         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10194         if (!intel_fb)
10195                 return ERR_PTR(-ENOMEM);
10196
10197         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10198         if (ret)
10199                 goto err;
10200
10201         return &intel_fb->base;
10202
10203 err:
10204         kfree(intel_fb);
10205         return ERR_PTR(ret);
10206 }
10207
10208 static struct drm_framebuffer *
10209 intel_framebuffer_create(struct drm_device *dev,
10210                          struct drm_mode_fb_cmd2 *mode_cmd,
10211                          struct drm_i915_gem_object *obj)
10212 {
10213         struct drm_framebuffer *fb;
10214         int ret;
10215
10216         ret = i915_mutex_lock_interruptible(dev);
10217         if (ret)
10218                 return ERR_PTR(ret);
10219         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10220         mutex_unlock(&dev->struct_mutex);
10221
10222         return fb;
10223 }
10224
10225 static u32
10226 intel_framebuffer_pitch_for_width(int width, int bpp)
10227 {
10228         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10229         return ALIGN(pitch, 64);
10230 }
10231
10232 static u32
10233 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10234 {
10235         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10236         return PAGE_ALIGN(pitch * mode->vdisplay);
10237 }
10238
10239 static struct drm_framebuffer *
10240 intel_framebuffer_create_for_mode(struct drm_device *dev,
10241                                   struct drm_display_mode *mode,
10242                                   int depth, int bpp)
10243 {
10244         struct drm_framebuffer *fb;
10245         struct drm_i915_gem_object *obj;
10246         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10247
10248         obj = i915_gem_alloc_object(dev,
10249                                     intel_framebuffer_size_for_mode(mode, bpp));
10250         if (obj == NULL)
10251                 return ERR_PTR(-ENOMEM);
10252
10253         mode_cmd.width = mode->hdisplay;
10254         mode_cmd.height = mode->vdisplay;
10255         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10256                                                                 bpp);
10257         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10258
10259         fb = intel_framebuffer_create(dev, &mode_cmd, obj);
10260         if (IS_ERR(fb))
10261                 drm_gem_object_unreference_unlocked(&obj->base);
10262
10263         return fb;
10264 }
10265
10266 static struct drm_framebuffer *
10267 mode_fits_in_fbdev(struct drm_device *dev,
10268                    struct drm_display_mode *mode)
10269 {
10270 #ifdef CONFIG_DRM_FBDEV_EMULATION
10271         struct drm_i915_private *dev_priv = dev->dev_private;
10272         struct drm_i915_gem_object *obj;
10273         struct drm_framebuffer *fb;
10274
10275         if (!dev_priv->fbdev)
10276                 return NULL;
10277
10278         if (!dev_priv->fbdev->fb)
10279                 return NULL;
10280
10281         obj = dev_priv->fbdev->fb->obj;
10282         BUG_ON(!obj);
10283
10284         fb = &dev_priv->fbdev->fb->base;
10285         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10286                                                                fb->bits_per_pixel))
10287                 return NULL;
10288
10289         if (obj->base.size < mode->vdisplay * fb->pitches[0])
10290                 return NULL;
10291
10292         drm_framebuffer_reference(fb);
10293         return fb;
10294 #else
10295         return NULL;
10296 #endif
10297 }
10298
10299 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10300                                            struct drm_crtc *crtc,
10301                                            struct drm_display_mode *mode,
10302                                            struct drm_framebuffer *fb,
10303                                            int x, int y)
10304 {
10305         struct drm_plane_state *plane_state;
10306         int hdisplay, vdisplay;
10307         int ret;
10308
10309         plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10310         if (IS_ERR(plane_state))
10311                 return PTR_ERR(plane_state);
10312
10313         if (mode)
10314                 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10315         else
10316                 hdisplay = vdisplay = 0;
10317
10318         ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10319         if (ret)
10320                 return ret;
10321         drm_atomic_set_fb_for_plane(plane_state, fb);
10322         plane_state->crtc_x = 0;
10323         plane_state->crtc_y = 0;
10324         plane_state->crtc_w = hdisplay;
10325         plane_state->crtc_h = vdisplay;
10326         plane_state->src_x = x << 16;
10327         plane_state->src_y = y << 16;
10328         plane_state->src_w = hdisplay << 16;
10329         plane_state->src_h = vdisplay << 16;
10330
10331         return 0;
10332 }
10333
10334 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10335                                 struct drm_display_mode *mode,
10336                                 struct intel_load_detect_pipe *old,
10337                                 struct drm_modeset_acquire_ctx *ctx)
10338 {
10339         struct intel_crtc *intel_crtc;
10340         struct intel_encoder *intel_encoder =
10341                 intel_attached_encoder(connector);
10342         struct drm_crtc *possible_crtc;
10343         struct drm_encoder *encoder = &intel_encoder->base;
10344         struct drm_crtc *crtc = NULL;
10345         struct drm_device *dev = encoder->dev;
10346         struct drm_framebuffer *fb;
10347         struct drm_mode_config *config = &dev->mode_config;
10348         struct drm_atomic_state *state = NULL, *restore_state = NULL;
10349         struct drm_connector_state *connector_state;
10350         struct intel_crtc_state *crtc_state;
10351         int ret, i = -1;
10352
10353         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10354                       connector->base.id, connector->name,
10355                       encoder->base.id, encoder->name);
10356
10357         old->restore_state = NULL;
10358
10359 retry:
10360         ret = drm_modeset_lock(&config->connection_mutex, ctx);
10361         if (ret)
10362                 goto fail;
10363
10364         /*
10365          * Algorithm gets a little messy:
10366          *
10367          *   - if the connector already has an assigned crtc, use it (but make
10368          *     sure it's on first)
10369          *
10370          *   - try to find the first unused crtc that can drive this connector,
10371          *     and use that if we find one
10372          */
10373
10374         /* See if we already have a CRTC for this connector */
10375         if (connector->state->crtc) {
10376                 crtc = connector->state->crtc;
10377
10378                 ret = drm_modeset_lock(&crtc->mutex, ctx);
10379                 if (ret)
10380                         goto fail;
10381
10382                 /* Make sure the crtc and connector are running */
10383                 goto found;
10384         }
10385
10386         /* Find an unused one (if possible) */
10387         for_each_crtc(dev, possible_crtc) {
10388                 i++;
10389                 if (!(encoder->possible_crtcs & (1 << i)))
10390                         continue;
10391
10392                 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
10393                 if (ret)
10394                         goto fail;
10395
10396                 if (possible_crtc->state->enable) {
10397                         drm_modeset_unlock(&possible_crtc->mutex);
10398                         continue;
10399                 }
10400
10401                 crtc = possible_crtc;
10402                 break;
10403         }
10404
10405         /*
10406          * If we didn't find an unused CRTC, don't use any.
10407          */
10408         if (!crtc) {
10409                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10410                 goto fail;
10411         }
10412
10413 found:
10414         intel_crtc = to_intel_crtc(crtc);
10415
10416         ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10417         if (ret)
10418                 goto fail;
10419
10420         state = drm_atomic_state_alloc(dev);
10421         restore_state = drm_atomic_state_alloc(dev);
10422         if (!state || !restore_state) {
10423                 ret = -ENOMEM;
10424                 goto fail;
10425         }
10426
10427         state->acquire_ctx = ctx;
10428         restore_state->acquire_ctx = ctx;
10429
10430         connector_state = drm_atomic_get_connector_state(state, connector);
10431         if (IS_ERR(connector_state)) {
10432                 ret = PTR_ERR(connector_state);
10433                 goto fail;
10434         }
10435
10436         ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
10437         if (ret)
10438                 goto fail;
10439
10440         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10441         if (IS_ERR(crtc_state)) {
10442                 ret = PTR_ERR(crtc_state);
10443                 goto fail;
10444         }
10445
10446         crtc_state->base.active = crtc_state->base.enable = true;
10447
10448         if (!mode)
10449                 mode = &load_detect_mode;
10450
10451         /* We need a framebuffer large enough to accommodate all accesses
10452          * that the plane may generate whilst we perform load detection.
10453          * We can not rely on the fbcon either being present (we get called
10454          * during its initialisation to detect all boot displays, or it may
10455          * not even exist) or that it is large enough to satisfy the
10456          * requested mode.
10457          */
10458         fb = mode_fits_in_fbdev(dev, mode);
10459         if (fb == NULL) {
10460                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10461                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10462         } else
10463                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10464         if (IS_ERR(fb)) {
10465                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10466                 goto fail;
10467         }
10468
10469         ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10470         if (ret)
10471                 goto fail;
10472
10473         drm_framebuffer_unreference(fb);
10474
10475         ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
10476         if (ret)
10477                 goto fail;
10478
10479         ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
10480         if (!ret)
10481                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
10482         if (!ret)
10483                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
10484         if (ret) {
10485                 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
10486                 goto fail;
10487         }
10488
10489         ret = drm_atomic_commit(state);
10490         if (ret) {
10491                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10492                 goto fail;
10493         }
10494
10495         old->restore_state = restore_state;
10496
10497         /* let the connector get through one full cycle before testing */
10498         intel_wait_for_vblank(dev, intel_crtc->pipe);
10499         return true;
10500
10501 fail:
10502         drm_atomic_state_free(state);
10503         drm_atomic_state_free(restore_state);
10504         restore_state = state = NULL;
10505
10506         if (ret == -EDEADLK) {
10507                 drm_modeset_backoff(ctx);
10508                 goto retry;
10509         }
10510
10511         return false;
10512 }
10513
10514 void intel_release_load_detect_pipe(struct drm_connector *connector,
10515                                     struct intel_load_detect_pipe *old,
10516                                     struct drm_modeset_acquire_ctx *ctx)
10517 {
10518         struct intel_encoder *intel_encoder =
10519                 intel_attached_encoder(connector);
10520         struct drm_encoder *encoder = &intel_encoder->base;
10521         struct drm_atomic_state *state = old->restore_state;
10522         int ret;
10523
10524         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10525                       connector->base.id, connector->name,
10526                       encoder->base.id, encoder->name);
10527
10528         if (!state)
10529                 return;
10530
10531         ret = drm_atomic_commit(state);
10532         if (ret) {
10533                 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
10534                 drm_atomic_state_free(state);
10535         }
10536 }
10537
10538 static int i9xx_pll_refclk(struct drm_device *dev,
10539                            const struct intel_crtc_state *pipe_config)
10540 {
10541         struct drm_i915_private *dev_priv = dev->dev_private;
10542         u32 dpll = pipe_config->dpll_hw_state.dpll;
10543
10544         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10545                 return dev_priv->vbt.lvds_ssc_freq;
10546         else if (HAS_PCH_SPLIT(dev))
10547                 return 120000;
10548         else if (!IS_GEN2(dev))
10549                 return 96000;
10550         else
10551                 return 48000;
10552 }
10553
10554 /* Returns the clock of the currently programmed mode of the given pipe. */
10555 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10556                                 struct intel_crtc_state *pipe_config)
10557 {
10558         struct drm_device *dev = crtc->base.dev;
10559         struct drm_i915_private *dev_priv = dev->dev_private;
10560         int pipe = pipe_config->cpu_transcoder;
10561         u32 dpll = pipe_config->dpll_hw_state.dpll;
10562         u32 fp;
10563         intel_clock_t clock;
10564         int port_clock;
10565         int refclk = i9xx_pll_refclk(dev, pipe_config);
10566
10567         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10568                 fp = pipe_config->dpll_hw_state.fp0;
10569         else
10570                 fp = pipe_config->dpll_hw_state.fp1;
10571
10572         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10573         if (IS_PINEVIEW(dev)) {
10574                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10575                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10576         } else {
10577                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10578                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10579         }
10580
10581         if (!IS_GEN2(dev)) {
10582                 if (IS_PINEVIEW(dev))
10583                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10584                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10585                 else
10586                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10587                                DPLL_FPA01_P1_POST_DIV_SHIFT);
10588
10589                 switch (dpll & DPLL_MODE_MASK) {
10590                 case DPLLB_MODE_DAC_SERIAL:
10591                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10592                                 5 : 10;
10593                         break;
10594                 case DPLLB_MODE_LVDS:
10595                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10596                                 7 : 14;
10597                         break;
10598                 default:
10599                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10600                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
10601                         return;
10602                 }
10603
10604                 if (IS_PINEVIEW(dev))
10605                         port_clock = pnv_calc_dpll_params(refclk, &clock);
10606                 else
10607                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
10608         } else {
10609                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10610                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10611
10612                 if (is_lvds) {
10613                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10614                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
10615
10616                         if (lvds & LVDS_CLKB_POWER_UP)
10617                                 clock.p2 = 7;
10618                         else
10619                                 clock.p2 = 14;
10620                 } else {
10621                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
10622                                 clock.p1 = 2;
10623                         else {
10624                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10625                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10626                         }
10627                         if (dpll & PLL_P2_DIVIDE_BY_4)
10628                                 clock.p2 = 4;
10629                         else
10630                                 clock.p2 = 2;
10631                 }
10632
10633                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10634         }
10635
10636         /*
10637          * This value includes pixel_multiplier. We will use
10638          * port_clock to compute adjusted_mode.crtc_clock in the
10639          * encoder's get_config() function.
10640          */
10641         pipe_config->port_clock = port_clock;
10642 }
10643
10644 int intel_dotclock_calculate(int link_freq,
10645                              const struct intel_link_m_n *m_n)
10646 {
10647         /*
10648          * The calculation for the data clock is:
10649          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10650          * But we want to avoid losing precison if possible, so:
10651          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10652          *
10653          * and the link clock is simpler:
10654          * link_clock = (m * link_clock) / n
10655          */
10656
10657         if (!m_n->link_n)
10658                 return 0;
10659
10660         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10661 }
10662
10663 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10664                                    struct intel_crtc_state *pipe_config)
10665 {
10666         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10667
10668         /* read out port_clock from the DPLL */
10669         i9xx_crtc_clock_get(crtc, pipe_config);
10670
10671         /*
10672          * In case there is an active pipe without active ports,
10673          * we may need some idea for the dotclock anyway.
10674          * Calculate one based on the FDI configuration.
10675          */
10676         pipe_config->base.adjusted_mode.crtc_clock =
10677                 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
10678                                          &pipe_config->fdi_m_n);
10679 }
10680
10681 /** Returns the currently programmed mode of the given pipe. */
10682 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10683                                              struct drm_crtc *crtc)
10684 {
10685         struct drm_i915_private *dev_priv = dev->dev_private;
10686         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10687         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10688         struct drm_display_mode *mode;
10689         struct intel_crtc_state *pipe_config;
10690         int htot = I915_READ(HTOTAL(cpu_transcoder));
10691         int hsync = I915_READ(HSYNC(cpu_transcoder));
10692         int vtot = I915_READ(VTOTAL(cpu_transcoder));
10693         int vsync = I915_READ(VSYNC(cpu_transcoder));
10694         enum pipe pipe = intel_crtc->pipe;
10695
10696         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10697         if (!mode)
10698                 return NULL;
10699
10700         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10701         if (!pipe_config) {
10702                 kfree(mode);
10703                 return NULL;
10704         }
10705
10706         /*
10707          * Construct a pipe_config sufficient for getting the clock info
10708          * back out of crtc_clock_get.
10709          *
10710          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10711          * to use a real value here instead.
10712          */
10713         pipe_config->cpu_transcoder = (enum transcoder) pipe;
10714         pipe_config->pixel_multiplier = 1;
10715         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10716         pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10717         pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10718         i9xx_crtc_clock_get(intel_crtc, pipe_config);
10719
10720         mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
10721         mode->hdisplay = (htot & 0xffff) + 1;
10722         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10723         mode->hsync_start = (hsync & 0xffff) + 1;
10724         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10725         mode->vdisplay = (vtot & 0xffff) + 1;
10726         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10727         mode->vsync_start = (vsync & 0xffff) + 1;
10728         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10729
10730         drm_mode_set_name(mode);
10731
10732         kfree(pipe_config);
10733
10734         return mode;
10735 }
10736
10737 void intel_mark_busy(struct drm_device *dev)
10738 {
10739         struct drm_i915_private *dev_priv = dev->dev_private;
10740
10741         if (dev_priv->mm.busy)
10742                 return;
10743
10744         intel_runtime_pm_get(dev_priv);
10745         i915_update_gfx_val(dev_priv);
10746         if (INTEL_INFO(dev)->gen >= 6)
10747                 gen6_rps_busy(dev_priv);
10748         dev_priv->mm.busy = true;
10749 }
10750
10751 void intel_mark_idle(struct drm_device *dev)
10752 {
10753         struct drm_i915_private *dev_priv = dev->dev_private;
10754
10755         if (!dev_priv->mm.busy)
10756                 return;
10757
10758         dev_priv->mm.busy = false;
10759
10760         if (INTEL_INFO(dev)->gen >= 6)
10761                 gen6_rps_idle(dev->dev_private);
10762
10763         intel_runtime_pm_put(dev_priv);
10764 }
10765
10766 static void intel_crtc_destroy(struct drm_crtc *crtc)
10767 {
10768         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10769         struct drm_device *dev = crtc->dev;
10770         struct intel_unpin_work *work;
10771
10772         spin_lock_irq(&dev->event_lock);
10773         work = intel_crtc->unpin_work;
10774         intel_crtc->unpin_work = NULL;
10775         spin_unlock_irq(&dev->event_lock);
10776
10777         if (work) {
10778                 cancel_work_sync(&work->work);
10779                 kfree(work);
10780         }
10781
10782         drm_crtc_cleanup(crtc);
10783
10784         kfree(intel_crtc);
10785 }
10786
10787 static void intel_unpin_work_fn(struct work_struct *__work)
10788 {
10789         struct intel_unpin_work *work =
10790                 container_of(__work, struct intel_unpin_work, work);
10791         struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10792         struct drm_device *dev = crtc->base.dev;
10793         struct drm_plane *primary = crtc->base.primary;
10794
10795         mutex_lock(&dev->struct_mutex);
10796         intel_unpin_fb_obj(work->old_fb, primary->state->rotation);
10797         drm_gem_object_unreference(&work->pending_flip_obj->base);
10798
10799         if (work->flip_queued_req)
10800                 i915_gem_request_assign(&work->flip_queued_req, NULL);
10801         mutex_unlock(&dev->struct_mutex);
10802
10803         intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
10804         intel_fbc_post_update(crtc);
10805         drm_framebuffer_unreference(work->old_fb);
10806
10807         BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10808         atomic_dec(&crtc->unpin_work_count);
10809
10810         kfree(work);
10811 }
10812
10813 static void do_intel_finish_page_flip(struct drm_device *dev,
10814                                       struct drm_crtc *crtc)
10815 {
10816         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10817         struct intel_unpin_work *work;
10818         unsigned long flags;
10819
10820         /* Ignore early vblank irqs */
10821         if (intel_crtc == NULL)
10822                 return;
10823
10824         /*
10825          * This is called both by irq handlers and the reset code (to complete
10826          * lost pageflips) so needs the full irqsave spinlocks.
10827          */
10828         spin_lock_irqsave(&dev->event_lock, flags);
10829         work = intel_crtc->unpin_work;
10830
10831         /* Ensure we don't miss a work->pending update ... */
10832         smp_rmb();
10833
10834         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10835                 spin_unlock_irqrestore(&dev->event_lock, flags);
10836                 return;
10837         }
10838
10839         page_flip_completed(intel_crtc);
10840
10841         spin_unlock_irqrestore(&dev->event_lock, flags);
10842 }
10843
10844 void intel_finish_page_flip(struct drm_device *dev, int pipe)
10845 {
10846         struct drm_i915_private *dev_priv = dev->dev_private;
10847         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10848
10849         do_intel_finish_page_flip(dev, crtc);
10850 }
10851
10852 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10853 {
10854         struct drm_i915_private *dev_priv = dev->dev_private;
10855         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10856
10857         do_intel_finish_page_flip(dev, crtc);
10858 }
10859
10860 /* Is 'a' after or equal to 'b'? */
10861 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10862 {
10863         return !((a - b) & 0x80000000);
10864 }
10865
10866 static bool page_flip_finished(struct intel_crtc *crtc)
10867 {
10868         struct drm_device *dev = crtc->base.dev;
10869         struct drm_i915_private *dev_priv = dev->dev_private;
10870
10871         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10872             crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10873                 return true;
10874
10875         /*
10876          * The relevant registers doen't exist on pre-ctg.
10877          * As the flip done interrupt doesn't trigger for mmio
10878          * flips on gmch platforms, a flip count check isn't
10879          * really needed there. But since ctg has the registers,
10880          * include it in the check anyway.
10881          */
10882         if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10883                 return true;
10884
10885         /*
10886          * BDW signals flip done immediately if the plane
10887          * is disabled, even if the plane enable is already
10888          * armed to occur at the next vblank :(
10889          */
10890
10891         /*
10892          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10893          * used the same base address. In that case the mmio flip might
10894          * have completed, but the CS hasn't even executed the flip yet.
10895          *
10896          * A flip count check isn't enough as the CS might have updated
10897          * the base address just after start of vblank, but before we
10898          * managed to process the interrupt. This means we'd complete the
10899          * CS flip too soon.
10900          *
10901          * Combining both checks should get us a good enough result. It may
10902          * still happen that the CS flip has been executed, but has not
10903          * yet actually completed. But in case the base address is the same
10904          * anyway, we don't really care.
10905          */
10906         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10907                 crtc->unpin_work->gtt_offset &&
10908                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
10909                                     crtc->unpin_work->flip_count);
10910 }
10911
10912 void intel_prepare_page_flip(struct drm_device *dev, int plane)
10913 {
10914         struct drm_i915_private *dev_priv = dev->dev_private;
10915         struct intel_crtc *intel_crtc =
10916                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10917         unsigned long flags;
10918
10919
10920         /*
10921          * This is called both by irq handlers and the reset code (to complete
10922          * lost pageflips) so needs the full irqsave spinlocks.
10923          *
10924          * NB: An MMIO update of the plane base pointer will also
10925          * generate a page-flip completion irq, i.e. every modeset
10926          * is also accompanied by a spurious intel_prepare_page_flip().
10927          */
10928         spin_lock_irqsave(&dev->event_lock, flags);
10929         if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
10930                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
10931         spin_unlock_irqrestore(&dev->event_lock, flags);
10932 }
10933
10934 static inline void intel_mark_page_flip_active(struct intel_unpin_work *work)
10935 {
10936         /* Ensure that the work item is consistent when activating it ... */
10937         smp_wmb();
10938         atomic_set(&work->pending, INTEL_FLIP_PENDING);
10939         /* and that it is marked active as soon as the irq could fire. */
10940         smp_wmb();
10941 }
10942
10943 static int intel_gen2_queue_flip(struct drm_device *dev,
10944                                  struct drm_crtc *crtc,
10945                                  struct drm_framebuffer *fb,
10946                                  struct drm_i915_gem_object *obj,
10947                                  struct drm_i915_gem_request *req,
10948                                  uint32_t flags)
10949 {
10950         struct intel_engine_cs *ring = req->ring;
10951         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10952         u32 flip_mask;
10953         int ret;
10954
10955         ret = intel_ring_begin(req, 6);
10956         if (ret)
10957                 return ret;
10958
10959         /* Can't queue multiple flips, so wait for the previous
10960          * one to finish before executing the next.
10961          */
10962         if (intel_crtc->plane)
10963                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10964         else
10965                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10966         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10967         intel_ring_emit(ring, MI_NOOP);
10968         intel_ring_emit(ring, MI_DISPLAY_FLIP |
10969                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10970         intel_ring_emit(ring, fb->pitches[0]);
10971         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10972         intel_ring_emit(ring, 0); /* aux display base address, unused */
10973
10974         intel_mark_page_flip_active(intel_crtc->unpin_work);
10975         return 0;
10976 }
10977
10978 static int intel_gen3_queue_flip(struct drm_device *dev,
10979                                  struct drm_crtc *crtc,
10980                                  struct drm_framebuffer *fb,
10981                                  struct drm_i915_gem_object *obj,
10982                                  struct drm_i915_gem_request *req,
10983                                  uint32_t flags)
10984 {
10985         struct intel_engine_cs *ring = req->ring;
10986         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10987         u32 flip_mask;
10988         int ret;
10989
10990         ret = intel_ring_begin(req, 6);
10991         if (ret)
10992                 return ret;
10993
10994         if (intel_crtc->plane)
10995                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10996         else
10997                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10998         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10999         intel_ring_emit(ring, MI_NOOP);
11000         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
11001                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11002         intel_ring_emit(ring, fb->pitches[0]);
11003         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11004         intel_ring_emit(ring, MI_NOOP);
11005
11006         intel_mark_page_flip_active(intel_crtc->unpin_work);
11007         return 0;
11008 }
11009
11010 static int intel_gen4_queue_flip(struct drm_device *dev,
11011                                  struct drm_crtc *crtc,
11012                                  struct drm_framebuffer *fb,
11013                                  struct drm_i915_gem_object *obj,
11014                                  struct drm_i915_gem_request *req,
11015                                  uint32_t flags)
11016 {
11017         struct intel_engine_cs *ring = req->ring;
11018         struct drm_i915_private *dev_priv = dev->dev_private;
11019         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11020         uint32_t pf, pipesrc;
11021         int ret;
11022
11023         ret = intel_ring_begin(req, 4);
11024         if (ret)
11025                 return ret;
11026
11027         /* i965+ uses the linear or tiled offsets from the
11028          * Display Registers (which do not change across a page-flip)
11029          * so we need only reprogram the base address.
11030          */
11031         intel_ring_emit(ring, MI_DISPLAY_FLIP |
11032                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11033         intel_ring_emit(ring, fb->pitches[0]);
11034         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
11035                         obj->tiling_mode);
11036
11037         /* XXX Enabling the panel-fitter across page-flip is so far
11038          * untested on non-native modes, so ignore it for now.
11039          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11040          */
11041         pf = 0;
11042         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11043         intel_ring_emit(ring, pf | pipesrc);
11044
11045         intel_mark_page_flip_active(intel_crtc->unpin_work);
11046         return 0;
11047 }
11048
11049 static int intel_gen6_queue_flip(struct drm_device *dev,
11050                                  struct drm_crtc *crtc,
11051                                  struct drm_framebuffer *fb,
11052                                  struct drm_i915_gem_object *obj,
11053                                  struct drm_i915_gem_request *req,
11054                                  uint32_t flags)
11055 {
11056         struct intel_engine_cs *ring = req->ring;
11057         struct drm_i915_private *dev_priv = dev->dev_private;
11058         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11059         uint32_t pf, pipesrc;
11060         int ret;
11061
11062         ret = intel_ring_begin(req, 4);
11063         if (ret)
11064                 return ret;
11065
11066         intel_ring_emit(ring, MI_DISPLAY_FLIP |
11067                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11068         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
11069         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11070
11071         /* Contrary to the suggestions in the documentation,
11072          * "Enable Panel Fitter" does not seem to be required when page
11073          * flipping with a non-native mode, and worse causes a normal
11074          * modeset to fail.
11075          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11076          */
11077         pf = 0;
11078         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11079         intel_ring_emit(ring, pf | pipesrc);
11080
11081         intel_mark_page_flip_active(intel_crtc->unpin_work);
11082         return 0;
11083 }
11084
11085 static int intel_gen7_queue_flip(struct drm_device *dev,
11086                                  struct drm_crtc *crtc,
11087                                  struct drm_framebuffer *fb,
11088                                  struct drm_i915_gem_object *obj,
11089                                  struct drm_i915_gem_request *req,
11090                                  uint32_t flags)
11091 {
11092         struct intel_engine_cs *ring = req->ring;
11093         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11094         uint32_t plane_bit = 0;
11095         int len, ret;
11096
11097         switch (intel_crtc->plane) {
11098         case PLANE_A:
11099                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11100                 break;
11101         case PLANE_B:
11102                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11103                 break;
11104         case PLANE_C:
11105                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11106                 break;
11107         default:
11108                 WARN_ONCE(1, "unknown plane in flip command\n");
11109                 return -ENODEV;
11110         }
11111
11112         len = 4;
11113         if (ring->id == RCS) {
11114                 len += 6;
11115                 /*
11116                  * On Gen 8, SRM is now taking an extra dword to accommodate
11117                  * 48bits addresses, and we need a NOOP for the batch size to
11118                  * stay even.
11119                  */
11120                 if (IS_GEN8(dev))
11121                         len += 2;
11122         }
11123
11124         /*
11125          * BSpec MI_DISPLAY_FLIP for IVB:
11126          * "The full packet must be contained within the same cache line."
11127          *
11128          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11129          * cacheline, if we ever start emitting more commands before
11130          * the MI_DISPLAY_FLIP we may need to first emit everything else,
11131          * then do the cacheline alignment, and finally emit the
11132          * MI_DISPLAY_FLIP.
11133          */
11134         ret = intel_ring_cacheline_align(req);
11135         if (ret)
11136                 return ret;
11137
11138         ret = intel_ring_begin(req, len);
11139         if (ret)
11140                 return ret;
11141
11142         /* Unmask the flip-done completion message. Note that the bspec says that
11143          * we should do this for both the BCS and RCS, and that we must not unmask
11144          * more than one flip event at any time (or ensure that one flip message
11145          * can be sent by waiting for flip-done prior to queueing new flips).
11146          * Experimentation says that BCS works despite DERRMR masking all
11147          * flip-done completion events and that unmasking all planes at once
11148          * for the RCS also doesn't appear to drop events. Setting the DERRMR
11149          * to zero does lead to lockups within MI_DISPLAY_FLIP.
11150          */
11151         if (ring->id == RCS) {
11152                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11153                 intel_ring_emit_reg(ring, DERRMR);
11154                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11155                                         DERRMR_PIPEB_PRI_FLIP_DONE |
11156                                         DERRMR_PIPEC_PRI_FLIP_DONE));
11157                 if (IS_GEN8(dev))
11158                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |
11159                                               MI_SRM_LRM_GLOBAL_GTT);
11160                 else
11161                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM |
11162                                               MI_SRM_LRM_GLOBAL_GTT);
11163                 intel_ring_emit_reg(ring, DERRMR);
11164                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
11165                 if (IS_GEN8(dev)) {
11166                         intel_ring_emit(ring, 0);
11167                         intel_ring_emit(ring, MI_NOOP);
11168                 }
11169         }
11170
11171         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11172         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
11173         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11174         intel_ring_emit(ring, (MI_NOOP));
11175
11176         intel_mark_page_flip_active(intel_crtc->unpin_work);
11177         return 0;
11178 }
11179
11180 static bool use_mmio_flip(struct intel_engine_cs *ring,
11181                           struct drm_i915_gem_object *obj)
11182 {
11183         /*
11184          * This is not being used for older platforms, because
11185          * non-availability of flip done interrupt forces us to use
11186          * CS flips. Older platforms derive flip done using some clever
11187          * tricks involving the flip_pending status bits and vblank irqs.
11188          * So using MMIO flips there would disrupt this mechanism.
11189          */
11190
11191         if (ring == NULL)
11192                 return true;
11193
11194         if (INTEL_INFO(ring->dev)->gen < 5)
11195                 return false;
11196
11197         if (i915.use_mmio_flip < 0)
11198                 return false;
11199         else if (i915.use_mmio_flip > 0)
11200                 return true;
11201         else if (i915.enable_execlists)
11202                 return true;
11203         else if (obj->base.dma_buf &&
11204                  !reservation_object_test_signaled_rcu(obj->base.dma_buf->resv,
11205                                                        false))
11206                 return true;
11207         else
11208                 return ring != i915_gem_request_get_ring(obj->last_write_req);
11209 }
11210
11211 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
11212                              unsigned int rotation,
11213                              struct intel_unpin_work *work)
11214 {
11215         struct drm_device *dev = intel_crtc->base.dev;
11216         struct drm_i915_private *dev_priv = dev->dev_private;
11217         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11218         const enum pipe pipe = intel_crtc->pipe;
11219         u32 ctl, stride, tile_height;
11220
11221         ctl = I915_READ(PLANE_CTL(pipe, 0));
11222         ctl &= ~PLANE_CTL_TILED_MASK;
11223         switch (fb->modifier[0]) {
11224         case DRM_FORMAT_MOD_NONE:
11225                 break;
11226         case I915_FORMAT_MOD_X_TILED:
11227                 ctl |= PLANE_CTL_TILED_X;
11228                 break;
11229         case I915_FORMAT_MOD_Y_TILED:
11230                 ctl |= PLANE_CTL_TILED_Y;
11231                 break;
11232         case I915_FORMAT_MOD_Yf_TILED:
11233                 ctl |= PLANE_CTL_TILED_YF;
11234                 break;
11235         default:
11236                 MISSING_CASE(fb->modifier[0]);
11237         }
11238
11239         /*
11240          * The stride is either expressed as a multiple of 64 bytes chunks for
11241          * linear buffers or in number of tiles for tiled buffers.
11242          */
11243         if (intel_rotation_90_or_270(rotation)) {
11244                 /* stride = Surface height in tiles */
11245                 tile_height = intel_tile_height(dev_priv, fb->modifier[0], 0);
11246                 stride = DIV_ROUND_UP(fb->height, tile_height);
11247         } else {
11248                 stride = fb->pitches[0] /
11249                         intel_fb_stride_alignment(dev_priv, fb->modifier[0],
11250                                                   fb->pixel_format);
11251         }
11252
11253         /*
11254          * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11255          * PLANE_SURF updates, the update is then guaranteed to be atomic.
11256          */
11257         I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11258         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11259
11260         I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
11261         POSTING_READ(PLANE_SURF(pipe, 0));
11262 }
11263
11264 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
11265                              struct intel_unpin_work *work)
11266 {
11267         struct drm_device *dev = intel_crtc->base.dev;
11268         struct drm_i915_private *dev_priv = dev->dev_private;
11269         struct intel_framebuffer *intel_fb =
11270                 to_intel_framebuffer(intel_crtc->base.primary->fb);
11271         struct drm_i915_gem_object *obj = intel_fb->obj;
11272         i915_reg_t reg = DSPCNTR(intel_crtc->plane);
11273         u32 dspcntr;
11274
11275         dspcntr = I915_READ(reg);
11276
11277         if (obj->tiling_mode != I915_TILING_NONE)
11278                 dspcntr |= DISPPLANE_TILED;
11279         else
11280                 dspcntr &= ~DISPPLANE_TILED;
11281
11282         I915_WRITE(reg, dspcntr);
11283
11284         I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
11285         POSTING_READ(DSPSURF(intel_crtc->plane));
11286 }
11287
11288 /*
11289  * XXX: This is the temporary way to update the plane registers until we get
11290  * around to using the usual plane update functions for MMIO flips
11291  */
11292 static void intel_do_mmio_flip(struct intel_mmio_flip *mmio_flip)
11293 {
11294         struct intel_crtc *crtc = mmio_flip->crtc;
11295         struct intel_unpin_work *work;
11296
11297         spin_lock_irq(&crtc->base.dev->event_lock);
11298         work = crtc->unpin_work;
11299         spin_unlock_irq(&crtc->base.dev->event_lock);
11300         if (work == NULL)
11301                 return;
11302
11303         intel_mark_page_flip_active(work);
11304
11305         intel_pipe_update_start(crtc);
11306
11307         if (INTEL_INFO(mmio_flip->i915)->gen >= 9)
11308                 skl_do_mmio_flip(crtc, mmio_flip->rotation, work);
11309         else
11310                 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11311                 ilk_do_mmio_flip(crtc, work);
11312
11313         intel_pipe_update_end(crtc);
11314 }
11315
11316 static void intel_mmio_flip_work_func(struct work_struct *work)
11317 {
11318         struct intel_mmio_flip *mmio_flip =
11319                 container_of(work, struct intel_mmio_flip, work);
11320         struct intel_framebuffer *intel_fb =
11321                 to_intel_framebuffer(mmio_flip->crtc->base.primary->fb);
11322         struct drm_i915_gem_object *obj = intel_fb->obj;
11323
11324         if (mmio_flip->req) {
11325                 WARN_ON(__i915_wait_request(mmio_flip->req,
11326                                             mmio_flip->crtc->reset_counter,
11327                                             false, NULL,
11328                                             &mmio_flip->i915->rps.mmioflips));
11329                 i915_gem_request_unreference__unlocked(mmio_flip->req);
11330         }
11331
11332         /* For framebuffer backed by dmabuf, wait for fence */
11333         if (obj->base.dma_buf)
11334                 WARN_ON(reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv,
11335                                                             false, false,
11336                                                             MAX_SCHEDULE_TIMEOUT) < 0);
11337
11338         intel_do_mmio_flip(mmio_flip);
11339         kfree(mmio_flip);
11340 }
11341
11342 static int intel_queue_mmio_flip(struct drm_device *dev,
11343                                  struct drm_crtc *crtc,
11344                                  struct drm_i915_gem_object *obj)
11345 {
11346         struct intel_mmio_flip *mmio_flip;
11347
11348         mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11349         if (mmio_flip == NULL)
11350                 return -ENOMEM;
11351
11352         mmio_flip->i915 = to_i915(dev);
11353         mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
11354         mmio_flip->crtc = to_intel_crtc(crtc);
11355         mmio_flip->rotation = crtc->primary->state->rotation;
11356
11357         INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11358         schedule_work(&mmio_flip->work);
11359
11360         return 0;
11361 }
11362
11363 static int intel_default_queue_flip(struct drm_device *dev,
11364                                     struct drm_crtc *crtc,
11365                                     struct drm_framebuffer *fb,
11366                                     struct drm_i915_gem_object *obj,
11367                                     struct drm_i915_gem_request *req,
11368                                     uint32_t flags)
11369 {
11370         return -ENODEV;
11371 }
11372
11373 static bool __intel_pageflip_stall_check(struct drm_device *dev,
11374                                          struct drm_crtc *crtc)
11375 {
11376         struct drm_i915_private *dev_priv = dev->dev_private;
11377         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11378         struct intel_unpin_work *work = intel_crtc->unpin_work;
11379         u32 addr;
11380
11381         if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11382                 return true;
11383
11384         if (atomic_read(&work->pending) < INTEL_FLIP_PENDING)
11385                 return false;
11386
11387         if (!work->enable_stall_check)
11388                 return false;
11389
11390         if (work->flip_ready_vblank == 0) {
11391                 if (work->flip_queued_req &&
11392                     !i915_gem_request_completed(work->flip_queued_req, true))
11393                         return false;
11394
11395                 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
11396         }
11397
11398         if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
11399                 return false;
11400
11401         /* Potential stall - if we see that the flip has happened,
11402          * assume a missed interrupt. */
11403         if (INTEL_INFO(dev)->gen >= 4)
11404                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11405         else
11406                 addr = I915_READ(DSPADDR(intel_crtc->plane));
11407
11408         /* There is a potential issue here with a false positive after a flip
11409          * to the same address. We could address this by checking for a
11410          * non-incrementing frame counter.
11411          */
11412         return addr == work->gtt_offset;
11413 }
11414
11415 void intel_check_page_flip(struct drm_device *dev, int pipe)
11416 {
11417         struct drm_i915_private *dev_priv = dev->dev_private;
11418         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11419         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11420         struct intel_unpin_work *work;
11421
11422         WARN_ON(!in_interrupt());
11423
11424         if (crtc == NULL)
11425                 return;
11426
11427         spin_lock(&dev->event_lock);
11428         work = intel_crtc->unpin_work;
11429         if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
11430                 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11431                          work->flip_queued_vblank, drm_vblank_count(dev, pipe));
11432                 page_flip_completed(intel_crtc);
11433                 work = NULL;
11434         }
11435         if (work != NULL &&
11436             drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11437                 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
11438         spin_unlock(&dev->event_lock);
11439 }
11440
11441 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11442                                 struct drm_framebuffer *fb,
11443                                 struct drm_pending_vblank_event *event,
11444                                 uint32_t page_flip_flags)
11445 {
11446         struct drm_device *dev = crtc->dev;
11447         struct drm_i915_private *dev_priv = dev->dev_private;
11448         struct drm_framebuffer *old_fb = crtc->primary->fb;
11449         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11450         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11451         struct drm_plane *primary = crtc->primary;
11452         enum pipe pipe = intel_crtc->pipe;
11453         struct intel_unpin_work *work;
11454         struct intel_engine_cs *ring;
11455         bool mmio_flip;
11456         struct drm_i915_gem_request *request = NULL;
11457         int ret;
11458
11459         /*
11460          * drm_mode_page_flip_ioctl() should already catch this, but double
11461          * check to be safe.  In the future we may enable pageflipping from
11462          * a disabled primary plane.
11463          */
11464         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11465                 return -EBUSY;
11466
11467         /* Can't change pixel format via MI display flips. */
11468         if (fb->pixel_format != crtc->primary->fb->pixel_format)
11469                 return -EINVAL;
11470
11471         /*
11472          * TILEOFF/LINOFF registers can't be changed via MI display flips.
11473          * Note that pitch changes could also affect these register.
11474          */
11475         if (INTEL_INFO(dev)->gen > 3 &&
11476             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11477              fb->pitches[0] != crtc->primary->fb->pitches[0]))
11478                 return -EINVAL;
11479
11480         if (i915_terminally_wedged(&dev_priv->gpu_error))
11481                 goto out_hang;
11482
11483         work = kzalloc(sizeof(*work), GFP_KERNEL);
11484         if (work == NULL)
11485                 return -ENOMEM;
11486
11487         work->event = event;
11488         work->crtc = crtc;
11489         work->old_fb = old_fb;
11490         INIT_WORK(&work->work, intel_unpin_work_fn);
11491
11492         ret = drm_crtc_vblank_get(crtc);
11493         if (ret)
11494                 goto free_work;
11495
11496         /* We borrow the event spin lock for protecting unpin_work */
11497         spin_lock_irq(&dev->event_lock);
11498         if (intel_crtc->unpin_work) {
11499                 /* Before declaring the flip queue wedged, check if
11500                  * the hardware completed the operation behind our backs.
11501                  */
11502                 if (__intel_pageflip_stall_check(dev, crtc)) {
11503                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11504                         page_flip_completed(intel_crtc);
11505                 } else {
11506                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11507                         spin_unlock_irq(&dev->event_lock);
11508
11509                         drm_crtc_vblank_put(crtc);
11510                         kfree(work);
11511                         return -EBUSY;
11512                 }
11513         }
11514         intel_crtc->unpin_work = work;
11515         spin_unlock_irq(&dev->event_lock);
11516
11517         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11518                 flush_workqueue(dev_priv->wq);
11519
11520         /* Reference the objects for the scheduled work. */
11521         drm_framebuffer_reference(work->old_fb);
11522         drm_gem_object_reference(&obj->base);
11523
11524         crtc->primary->fb = fb;
11525         update_state_fb(crtc->primary);
11526         intel_fbc_pre_update(intel_crtc);
11527
11528         work->pending_flip_obj = obj;
11529
11530         ret = i915_mutex_lock_interruptible(dev);
11531         if (ret)
11532                 goto cleanup;
11533
11534         atomic_inc(&intel_crtc->unpin_work_count);
11535         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
11536
11537         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11538                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
11539
11540         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
11541                 ring = &dev_priv->ring[BCS];
11542                 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11543                         /* vlv: DISPLAY_FLIP fails to change tiling */
11544                         ring = NULL;
11545         } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11546                 ring = &dev_priv->ring[BCS];
11547         } else if (INTEL_INFO(dev)->gen >= 7) {
11548                 ring = i915_gem_request_get_ring(obj->last_write_req);
11549                 if (ring == NULL || ring->id != RCS)
11550                         ring = &dev_priv->ring[BCS];
11551         } else {
11552                 ring = &dev_priv->ring[RCS];
11553         }
11554
11555         mmio_flip = use_mmio_flip(ring, obj);
11556
11557         /* When using CS flips, we want to emit semaphores between rings.
11558          * However, when using mmio flips we will create a task to do the
11559          * synchronisation, so all we want here is to pin the framebuffer
11560          * into the display plane and skip any waits.
11561          */
11562         if (!mmio_flip) {
11563                 ret = i915_gem_object_sync(obj, ring, &request);
11564                 if (ret)
11565                         goto cleanup_pending;
11566         }
11567
11568         ret = intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
11569         if (ret)
11570                 goto cleanup_pending;
11571
11572         work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary),
11573                                                   obj, 0);
11574         work->gtt_offset += intel_crtc->dspaddr_offset;
11575
11576         if (mmio_flip) {
11577                 ret = intel_queue_mmio_flip(dev, crtc, obj);
11578                 if (ret)
11579                         goto cleanup_unpin;
11580
11581                 i915_gem_request_assign(&work->flip_queued_req,
11582                                         obj->last_write_req);
11583         } else {
11584                 if (!request) {
11585                         request = i915_gem_request_alloc(ring, NULL);
11586                         if (IS_ERR(request)) {
11587                                 ret = PTR_ERR(request);
11588                                 goto cleanup_unpin;
11589                         }
11590                 }
11591
11592                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
11593                                                    page_flip_flags);
11594                 if (ret)
11595                         goto cleanup_unpin;
11596
11597                 i915_gem_request_assign(&work->flip_queued_req, request);
11598         }
11599
11600         if (request)
11601                 i915_add_request_no_flush(request);
11602
11603         work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11604         work->enable_stall_check = true;
11605
11606         i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11607                           to_intel_plane(primary)->frontbuffer_bit);
11608         mutex_unlock(&dev->struct_mutex);
11609
11610         intel_frontbuffer_flip_prepare(dev,
11611                                        to_intel_plane(primary)->frontbuffer_bit);
11612
11613         trace_i915_flip_request(intel_crtc->plane, obj);
11614
11615         return 0;
11616
11617 cleanup_unpin:
11618         intel_unpin_fb_obj(fb, crtc->primary->state->rotation);
11619 cleanup_pending:
11620         if (!IS_ERR_OR_NULL(request))
11621                 i915_gem_request_cancel(request);
11622         atomic_dec(&intel_crtc->unpin_work_count);
11623         mutex_unlock(&dev->struct_mutex);
11624 cleanup:
11625         crtc->primary->fb = old_fb;
11626         update_state_fb(crtc->primary);
11627
11628         drm_gem_object_unreference_unlocked(&obj->base);
11629         drm_framebuffer_unreference(work->old_fb);
11630
11631         spin_lock_irq(&dev->event_lock);
11632         intel_crtc->unpin_work = NULL;
11633         spin_unlock_irq(&dev->event_lock);
11634
11635         drm_crtc_vblank_put(crtc);
11636 free_work:
11637         kfree(work);
11638
11639         if (ret == -EIO) {
11640                 struct drm_atomic_state *state;
11641                 struct drm_plane_state *plane_state;
11642
11643 out_hang:
11644                 state = drm_atomic_state_alloc(dev);
11645                 if (!state)
11646                         return -ENOMEM;
11647                 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11648
11649 retry:
11650                 plane_state = drm_atomic_get_plane_state(state, primary);
11651                 ret = PTR_ERR_OR_ZERO(plane_state);
11652                 if (!ret) {
11653                         drm_atomic_set_fb_for_plane(plane_state, fb);
11654
11655                         ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11656                         if (!ret)
11657                                 ret = drm_atomic_commit(state);
11658                 }
11659
11660                 if (ret == -EDEADLK) {
11661                         drm_modeset_backoff(state->acquire_ctx);
11662                         drm_atomic_state_clear(state);
11663                         goto retry;
11664                 }
11665
11666                 if (ret)
11667                         drm_atomic_state_free(state);
11668
11669                 if (ret == 0 && event) {
11670                         spin_lock_irq(&dev->event_lock);
11671                         drm_send_vblank_event(dev, pipe, event);
11672                         spin_unlock_irq(&dev->event_lock);
11673                 }
11674         }
11675         return ret;
11676 }
11677
11678
11679 /**
11680  * intel_wm_need_update - Check whether watermarks need updating
11681  * @plane: drm plane
11682  * @state: new plane state
11683  *
11684  * Check current plane state versus the new one to determine whether
11685  * watermarks need to be recalculated.
11686  *
11687  * Returns true or false.
11688  */
11689 static bool intel_wm_need_update(struct drm_plane *plane,
11690                                  struct drm_plane_state *state)
11691 {
11692         struct intel_plane_state *new = to_intel_plane_state(state);
11693         struct intel_plane_state *cur = to_intel_plane_state(plane->state);
11694
11695         /* Update watermarks on tiling or size changes. */
11696         if (new->visible != cur->visible)
11697                 return true;
11698
11699         if (!cur->base.fb || !new->base.fb)
11700                 return false;
11701
11702         if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] ||
11703             cur->base.rotation != new->base.rotation ||
11704             drm_rect_width(&new->src) != drm_rect_width(&cur->src) ||
11705             drm_rect_height(&new->src) != drm_rect_height(&cur->src) ||
11706             drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) ||
11707             drm_rect_height(&new->dst) != drm_rect_height(&cur->dst))
11708                 return true;
11709
11710         return false;
11711 }
11712
11713 static bool needs_scaling(struct intel_plane_state *state)
11714 {
11715         int src_w = drm_rect_width(&state->src) >> 16;
11716         int src_h = drm_rect_height(&state->src) >> 16;
11717         int dst_w = drm_rect_width(&state->dst);
11718         int dst_h = drm_rect_height(&state->dst);
11719
11720         return (src_w != dst_w || src_h != dst_h);
11721 }
11722
11723 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11724                                     struct drm_plane_state *plane_state)
11725 {
11726         struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
11727         struct drm_crtc *crtc = crtc_state->crtc;
11728         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11729         struct drm_plane *plane = plane_state->plane;
11730         struct drm_device *dev = crtc->dev;
11731         struct drm_i915_private *dev_priv = to_i915(dev);
11732         struct intel_plane_state *old_plane_state =
11733                 to_intel_plane_state(plane->state);
11734         int idx = intel_crtc->base.base.id, ret;
11735         bool mode_changed = needs_modeset(crtc_state);
11736         bool was_crtc_enabled = crtc->state->active;
11737         bool is_crtc_enabled = crtc_state->active;
11738         bool turn_off, turn_on, visible, was_visible;
11739         struct drm_framebuffer *fb = plane_state->fb;
11740
11741         if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11742             plane->type != DRM_PLANE_TYPE_CURSOR) {
11743                 ret = skl_update_scaler_plane(
11744                         to_intel_crtc_state(crtc_state),
11745                         to_intel_plane_state(plane_state));
11746                 if (ret)
11747                         return ret;
11748         }
11749
11750         was_visible = old_plane_state->visible;
11751         visible = to_intel_plane_state(plane_state)->visible;
11752
11753         if (!was_crtc_enabled && WARN_ON(was_visible))
11754                 was_visible = false;
11755
11756         /*
11757          * Visibility is calculated as if the crtc was on, but
11758          * after scaler setup everything depends on it being off
11759          * when the crtc isn't active.
11760          */
11761         if (!is_crtc_enabled)
11762                 to_intel_plane_state(plane_state)->visible = visible = false;
11763
11764         if (!was_visible && !visible)
11765                 return 0;
11766
11767         if (fb != old_plane_state->base.fb)
11768                 pipe_config->fb_changed = true;
11769
11770         turn_off = was_visible && (!visible || mode_changed);
11771         turn_on = visible && (!was_visible || mode_changed);
11772
11773         DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11774                          plane->base.id, fb ? fb->base.id : -1);
11775
11776         DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11777                          plane->base.id, was_visible, visible,
11778                          turn_off, turn_on, mode_changed);
11779
11780         if (turn_on) {
11781                 pipe_config->update_wm_pre = true;
11782
11783                 /* must disable cxsr around plane enable/disable */
11784                 if (plane->type != DRM_PLANE_TYPE_CURSOR)
11785                         pipe_config->disable_cxsr = true;
11786         } else if (turn_off) {
11787                 pipe_config->update_wm_post = true;
11788
11789                 /* must disable cxsr around plane enable/disable */
11790                 if (plane->type != DRM_PLANE_TYPE_CURSOR)
11791                         pipe_config->disable_cxsr = true;
11792         } else if (intel_wm_need_update(plane, plane_state)) {
11793                 /* FIXME bollocks */
11794                 pipe_config->update_wm_pre = true;
11795                 pipe_config->update_wm_post = true;
11796         }
11797
11798         /* Pre-gen9 platforms need two-step watermark updates */
11799         if ((pipe_config->update_wm_pre || pipe_config->update_wm_post) &&
11800             INTEL_INFO(dev)->gen < 9 && dev_priv->display.optimize_watermarks)
11801                 to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true;
11802
11803         if (visible || was_visible)
11804                 intel_crtc->atomic.fb_bits |=
11805                         to_intel_plane(plane)->frontbuffer_bit;
11806
11807         switch (plane->type) {
11808         case DRM_PLANE_TYPE_PRIMARY:
11809                 intel_crtc->atomic.post_enable_primary = turn_on;
11810                 intel_crtc->atomic.update_fbc = true;
11811
11812                 break;
11813         case DRM_PLANE_TYPE_CURSOR:
11814                 break;
11815         case DRM_PLANE_TYPE_OVERLAY:
11816                 /*
11817                  * WaCxSRDisabledForSpriteScaling:ivb
11818                  *
11819                  * cstate->update_wm was already set above, so this flag will
11820                  * take effect when we commit and program watermarks.
11821                  */
11822                 if (IS_IVYBRIDGE(dev) &&
11823                     needs_scaling(to_intel_plane_state(plane_state)) &&
11824                     !needs_scaling(old_plane_state))
11825                         pipe_config->disable_lp_wm = true;
11826
11827                 break;
11828         }
11829         return 0;
11830 }
11831
11832 static bool encoders_cloneable(const struct intel_encoder *a,
11833                                const struct intel_encoder *b)
11834 {
11835         /* masks could be asymmetric, so check both ways */
11836         return a == b || (a->cloneable & (1 << b->type) &&
11837                           b->cloneable & (1 << a->type));
11838 }
11839
11840 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11841                                          struct intel_crtc *crtc,
11842                                          struct intel_encoder *encoder)
11843 {
11844         struct intel_encoder *source_encoder;
11845         struct drm_connector *connector;
11846         struct drm_connector_state *connector_state;
11847         int i;
11848
11849         for_each_connector_in_state(state, connector, connector_state, i) {
11850                 if (connector_state->crtc != &crtc->base)
11851                         continue;
11852
11853                 source_encoder =
11854                         to_intel_encoder(connector_state->best_encoder);
11855                 if (!encoders_cloneable(encoder, source_encoder))
11856                         return false;
11857         }
11858
11859         return true;
11860 }
11861
11862 static bool check_encoder_cloning(struct drm_atomic_state *state,
11863                                   struct intel_crtc *crtc)
11864 {
11865         struct intel_encoder *encoder;
11866         struct drm_connector *connector;
11867         struct drm_connector_state *connector_state;
11868         int i;
11869
11870         for_each_connector_in_state(state, connector, connector_state, i) {
11871                 if (connector_state->crtc != &crtc->base)
11872                         continue;
11873
11874                 encoder = to_intel_encoder(connector_state->best_encoder);
11875                 if (!check_single_encoder_cloning(state, crtc, encoder))
11876                         return false;
11877         }
11878
11879         return true;
11880 }
11881
11882 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11883                                    struct drm_crtc_state *crtc_state)
11884 {
11885         struct drm_device *dev = crtc->dev;
11886         struct drm_i915_private *dev_priv = dev->dev_private;
11887         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11888         struct intel_crtc_state *pipe_config =
11889                 to_intel_crtc_state(crtc_state);
11890         struct drm_atomic_state *state = crtc_state->state;
11891         int ret;
11892         bool mode_changed = needs_modeset(crtc_state);
11893
11894         if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11895                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11896                 return -EINVAL;
11897         }
11898
11899         if (mode_changed && !crtc_state->active)
11900                 pipe_config->update_wm_post = true;
11901
11902         if (mode_changed && crtc_state->enable &&
11903             dev_priv->display.crtc_compute_clock &&
11904             !WARN_ON(pipe_config->shared_dpll)) {
11905                 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11906                                                            pipe_config);
11907                 if (ret)
11908                         return ret;
11909         }
11910
11911         ret = 0;
11912         if (dev_priv->display.compute_pipe_wm) {
11913                 ret = dev_priv->display.compute_pipe_wm(pipe_config);
11914                 if (ret) {
11915                         DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
11916                         return ret;
11917                 }
11918         }
11919
11920         if (dev_priv->display.compute_intermediate_wm &&
11921             !to_intel_atomic_state(state)->skip_intermediate_wm) {
11922                 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
11923                         return 0;
11924
11925                 /*
11926                  * Calculate 'intermediate' watermarks that satisfy both the
11927                  * old state and the new state.  We can program these
11928                  * immediately.
11929                  */
11930                 ret = dev_priv->display.compute_intermediate_wm(crtc->dev,
11931                                                                 intel_crtc,
11932                                                                 pipe_config);
11933                 if (ret) {
11934                         DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
11935                         return ret;
11936                 }
11937         }
11938
11939         if (INTEL_INFO(dev)->gen >= 9) {
11940                 if (mode_changed)
11941                         ret = skl_update_scaler_crtc(pipe_config);
11942
11943                 if (!ret)
11944                         ret = intel_atomic_setup_scalers(dev, intel_crtc,
11945                                                          pipe_config);
11946         }
11947
11948         return ret;
11949 }
11950
11951 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11952         .mode_set_base_atomic = intel_pipe_set_base_atomic,
11953         .load_lut = intel_crtc_load_lut,
11954         .atomic_begin = intel_begin_crtc_commit,
11955         .atomic_flush = intel_finish_crtc_commit,
11956         .atomic_check = intel_crtc_atomic_check,
11957 };
11958
11959 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11960 {
11961         struct intel_connector *connector;
11962
11963         for_each_intel_connector(dev, connector) {
11964                 if (connector->base.encoder) {
11965                         connector->base.state->best_encoder =
11966                                 connector->base.encoder;
11967                         connector->base.state->crtc =
11968                                 connector->base.encoder->crtc;
11969                 } else {
11970                         connector->base.state->best_encoder = NULL;
11971                         connector->base.state->crtc = NULL;
11972                 }
11973         }
11974 }
11975
11976 static void
11977 connected_sink_compute_bpp(struct intel_connector *connector,
11978                            struct intel_crtc_state *pipe_config)
11979 {
11980         int bpp = pipe_config->pipe_bpp;
11981
11982         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11983                 connector->base.base.id,
11984                 connector->base.name);
11985
11986         /* Don't use an invalid EDID bpc value */
11987         if (connector->base.display_info.bpc &&
11988             connector->base.display_info.bpc * 3 < bpp) {
11989                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11990                               bpp, connector->base.display_info.bpc*3);
11991                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11992         }
11993
11994         /* Clamp bpp to default limit on screens without EDID 1.4 */
11995         if (connector->base.display_info.bpc == 0) {
11996                 int type = connector->base.connector_type;
11997                 int clamp_bpp = 24;
11998
11999                 /* Fall back to 18 bpp when DP sink capability is unknown. */
12000                 if (type == DRM_MODE_CONNECTOR_DisplayPort ||
12001                     type == DRM_MODE_CONNECTOR_eDP)
12002                         clamp_bpp = 18;
12003
12004                 if (bpp > clamp_bpp) {
12005                         DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of %d\n",
12006                                       bpp, clamp_bpp);
12007                         pipe_config->pipe_bpp = clamp_bpp;
12008                 }
12009         }
12010 }
12011
12012 static int
12013 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
12014                           struct intel_crtc_state *pipe_config)
12015 {
12016         struct drm_device *dev = crtc->base.dev;
12017         struct drm_atomic_state *state;
12018         struct drm_connector *connector;
12019         struct drm_connector_state *connector_state;
12020         int bpp, i;
12021
12022         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)))
12023                 bpp = 10*3;
12024         else if (INTEL_INFO(dev)->gen >= 5)
12025                 bpp = 12*3;
12026         else
12027                 bpp = 8*3;
12028
12029
12030         pipe_config->pipe_bpp = bpp;
12031
12032         state = pipe_config->base.state;
12033
12034         /* Clamp display bpp to EDID value */
12035         for_each_connector_in_state(state, connector, connector_state, i) {
12036                 if (connector_state->crtc != &crtc->base)
12037                         continue;
12038
12039                 connected_sink_compute_bpp(to_intel_connector(connector),
12040                                            pipe_config);
12041         }
12042
12043         return bpp;
12044 }
12045
12046 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
12047 {
12048         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12049                         "type: 0x%x flags: 0x%x\n",
12050                 mode->crtc_clock,
12051                 mode->crtc_hdisplay, mode->crtc_hsync_start,
12052                 mode->crtc_hsync_end, mode->crtc_htotal,
12053                 mode->crtc_vdisplay, mode->crtc_vsync_start,
12054                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
12055 }
12056
12057 static void intel_dump_pipe_config(struct intel_crtc *crtc,
12058                                    struct intel_crtc_state *pipe_config,
12059                                    const char *context)
12060 {
12061         struct drm_device *dev = crtc->base.dev;
12062         struct drm_plane *plane;
12063         struct intel_plane *intel_plane;
12064         struct intel_plane_state *state;
12065         struct drm_framebuffer *fb;
12066
12067         DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
12068                       context, pipe_config, pipe_name(crtc->pipe));
12069
12070         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
12071         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
12072                       pipe_config->pipe_bpp, pipe_config->dither);
12073         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12074                       pipe_config->has_pch_encoder,
12075                       pipe_config->fdi_lanes,
12076                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
12077                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
12078                       pipe_config->fdi_m_n.tu);
12079         DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12080                       pipe_config->has_dp_encoder,
12081                       pipe_config->lane_count,
12082                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
12083                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
12084                       pipe_config->dp_m_n.tu);
12085
12086         DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
12087                       pipe_config->has_dp_encoder,
12088                       pipe_config->lane_count,
12089                       pipe_config->dp_m2_n2.gmch_m,
12090                       pipe_config->dp_m2_n2.gmch_n,
12091                       pipe_config->dp_m2_n2.link_m,
12092                       pipe_config->dp_m2_n2.link_n,
12093                       pipe_config->dp_m2_n2.tu);
12094
12095         DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12096                       pipe_config->has_audio,
12097                       pipe_config->has_infoframe);
12098
12099         DRM_DEBUG_KMS("requested mode:\n");
12100         drm_mode_debug_printmodeline(&pipe_config->base.mode);
12101         DRM_DEBUG_KMS("adjusted mode:\n");
12102         drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12103         intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
12104         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
12105         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12106                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
12107         DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12108                       crtc->num_scalers,
12109                       pipe_config->scaler_state.scaler_users,
12110                       pipe_config->scaler_state.scaler_id);
12111         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12112                       pipe_config->gmch_pfit.control,
12113                       pipe_config->gmch_pfit.pgm_ratios,
12114                       pipe_config->gmch_pfit.lvds_border_bits);
12115         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12116                       pipe_config->pch_pfit.pos,
12117                       pipe_config->pch_pfit.size,
12118                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
12119         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
12120         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
12121
12122         if (IS_BROXTON(dev)) {
12123                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
12124                               "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12125                               "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
12126                               pipe_config->ddi_pll_sel,
12127                               pipe_config->dpll_hw_state.ebb0,
12128                               pipe_config->dpll_hw_state.ebb4,
12129                               pipe_config->dpll_hw_state.pll0,
12130                               pipe_config->dpll_hw_state.pll1,
12131                               pipe_config->dpll_hw_state.pll2,
12132                               pipe_config->dpll_hw_state.pll3,
12133                               pipe_config->dpll_hw_state.pll6,
12134                               pipe_config->dpll_hw_state.pll8,
12135                               pipe_config->dpll_hw_state.pll9,
12136                               pipe_config->dpll_hw_state.pll10,
12137                               pipe_config->dpll_hw_state.pcsdw12);
12138         } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
12139                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12140                               "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12141                               pipe_config->ddi_pll_sel,
12142                               pipe_config->dpll_hw_state.ctrl1,
12143                               pipe_config->dpll_hw_state.cfgcr1,
12144                               pipe_config->dpll_hw_state.cfgcr2);
12145         } else if (HAS_DDI(dev)) {
12146                 DRM_DEBUG_KMS("ddi_pll_sel: 0x%x; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
12147                               pipe_config->ddi_pll_sel,
12148                               pipe_config->dpll_hw_state.wrpll,
12149                               pipe_config->dpll_hw_state.spll);
12150         } else {
12151                 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12152                               "fp0: 0x%x, fp1: 0x%x\n",
12153                               pipe_config->dpll_hw_state.dpll,
12154                               pipe_config->dpll_hw_state.dpll_md,
12155                               pipe_config->dpll_hw_state.fp0,
12156                               pipe_config->dpll_hw_state.fp1);
12157         }
12158
12159         DRM_DEBUG_KMS("planes on this crtc\n");
12160         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12161                 intel_plane = to_intel_plane(plane);
12162                 if (intel_plane->pipe != crtc->pipe)
12163                         continue;
12164
12165                 state = to_intel_plane_state(plane->state);
12166                 fb = state->base.fb;
12167                 if (!fb) {
12168                         DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12169                                 "disabled, scaler_id = %d\n",
12170                                 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12171                                 plane->base.id, intel_plane->pipe,
12172                                 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12173                                 drm_plane_index(plane), state->scaler_id);
12174                         continue;
12175                 }
12176
12177                 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12178                         plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12179                         plane->base.id, intel_plane->pipe,
12180                         crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12181                         drm_plane_index(plane));
12182                 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12183                         fb->base.id, fb->width, fb->height, fb->pixel_format);
12184                 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12185                         state->scaler_id,
12186                         state->src.x1 >> 16, state->src.y1 >> 16,
12187                         drm_rect_width(&state->src) >> 16,
12188                         drm_rect_height(&state->src) >> 16,
12189                         state->dst.x1, state->dst.y1,
12190                         drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12191         }
12192 }
12193
12194 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12195 {
12196         struct drm_device *dev = state->dev;
12197         struct drm_connector *connector;
12198         unsigned int used_ports = 0;
12199
12200         /*
12201          * Walk the connector list instead of the encoder
12202          * list to detect the problem on ddi platforms
12203          * where there's just one encoder per digital port.
12204          */
12205         drm_for_each_connector(connector, dev) {
12206                 struct drm_connector_state *connector_state;
12207                 struct intel_encoder *encoder;
12208
12209                 connector_state = drm_atomic_get_existing_connector_state(state, connector);
12210                 if (!connector_state)
12211                         connector_state = connector->state;
12212
12213                 if (!connector_state->best_encoder)
12214                         continue;
12215
12216                 encoder = to_intel_encoder(connector_state->best_encoder);
12217
12218                 WARN_ON(!connector_state->crtc);
12219
12220                 switch (encoder->type) {
12221                         unsigned int port_mask;
12222                 case INTEL_OUTPUT_UNKNOWN:
12223                         if (WARN_ON(!HAS_DDI(dev)))
12224                                 break;
12225                 case INTEL_OUTPUT_DISPLAYPORT:
12226                 case INTEL_OUTPUT_HDMI:
12227                 case INTEL_OUTPUT_EDP:
12228                         port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12229
12230                         /* the same port mustn't appear more than once */
12231                         if (used_ports & port_mask)
12232                                 return false;
12233
12234                         used_ports |= port_mask;
12235                 default:
12236                         break;
12237                 }
12238         }
12239
12240         return true;
12241 }
12242
12243 static void
12244 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12245 {
12246         struct drm_crtc_state tmp_state;
12247         struct intel_crtc_scaler_state scaler_state;
12248         struct intel_dpll_hw_state dpll_hw_state;
12249         struct intel_shared_dpll *shared_dpll;
12250         uint32_t ddi_pll_sel;
12251         bool force_thru;
12252
12253         /* FIXME: before the switch to atomic started, a new pipe_config was
12254          * kzalloc'd. Code that depends on any field being zero should be
12255          * fixed, so that the crtc_state can be safely duplicated. For now,
12256          * only fields that are know to not cause problems are preserved. */
12257
12258         tmp_state = crtc_state->base;
12259         scaler_state = crtc_state->scaler_state;
12260         shared_dpll = crtc_state->shared_dpll;
12261         dpll_hw_state = crtc_state->dpll_hw_state;
12262         ddi_pll_sel = crtc_state->ddi_pll_sel;
12263         force_thru = crtc_state->pch_pfit.force_thru;
12264
12265         memset(crtc_state, 0, sizeof *crtc_state);
12266
12267         crtc_state->base = tmp_state;
12268         crtc_state->scaler_state = scaler_state;
12269         crtc_state->shared_dpll = shared_dpll;
12270         crtc_state->dpll_hw_state = dpll_hw_state;
12271         crtc_state->ddi_pll_sel = ddi_pll_sel;
12272         crtc_state->pch_pfit.force_thru = force_thru;
12273 }
12274
12275 static int
12276 intel_modeset_pipe_config(struct drm_crtc *crtc,
12277                           struct intel_crtc_state *pipe_config)
12278 {
12279         struct drm_atomic_state *state = pipe_config->base.state;
12280         struct intel_encoder *encoder;
12281         struct drm_connector *connector;
12282         struct drm_connector_state *connector_state;
12283         int base_bpp, ret = -EINVAL;
12284         int i;
12285         bool retry = true;
12286
12287         clear_intel_crtc_state(pipe_config);
12288
12289         pipe_config->cpu_transcoder =
12290                 (enum transcoder) to_intel_crtc(crtc)->pipe;
12291
12292         /*
12293          * Sanitize sync polarity flags based on requested ones. If neither
12294          * positive or negative polarity is requested, treat this as meaning
12295          * negative polarity.
12296          */
12297         if (!(pipe_config->base.adjusted_mode.flags &
12298               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12299                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12300
12301         if (!(pipe_config->base.adjusted_mode.flags &
12302               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12303                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12304
12305         base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12306                                              pipe_config);
12307         if (base_bpp < 0)
12308                 goto fail;
12309
12310         /*
12311          * Determine the real pipe dimensions. Note that stereo modes can
12312          * increase the actual pipe size due to the frame doubling and
12313          * insertion of additional space for blanks between the frame. This
12314          * is stored in the crtc timings. We use the requested mode to do this
12315          * computation to clearly distinguish it from the adjusted mode, which
12316          * can be changed by the connectors in the below retry loop.
12317          */
12318         drm_crtc_get_hv_timing(&pipe_config->base.mode,
12319                                &pipe_config->pipe_src_w,
12320                                &pipe_config->pipe_src_h);
12321
12322 encoder_retry:
12323         /* Ensure the port clock defaults are reset when retrying. */
12324         pipe_config->port_clock = 0;
12325         pipe_config->pixel_multiplier = 1;
12326
12327         /* Fill in default crtc timings, allow encoders to overwrite them. */
12328         drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12329                               CRTC_STEREO_DOUBLE);
12330
12331         /* Pass our mode to the connectors and the CRTC to give them a chance to
12332          * adjust it according to limitations or connector properties, and also
12333          * a chance to reject the mode entirely.
12334          */
12335         for_each_connector_in_state(state, connector, connector_state, i) {
12336                 if (connector_state->crtc != crtc)
12337                         continue;
12338
12339                 encoder = to_intel_encoder(connector_state->best_encoder);
12340
12341                 if (!(encoder->compute_config(encoder, pipe_config))) {
12342                         DRM_DEBUG_KMS("Encoder config failure\n");
12343                         goto fail;
12344                 }
12345         }
12346
12347         /* Set default port clock if not overwritten by the encoder. Needs to be
12348          * done afterwards in case the encoder adjusts the mode. */
12349         if (!pipe_config->port_clock)
12350                 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12351                         * pipe_config->pixel_multiplier;
12352
12353         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12354         if (ret < 0) {
12355                 DRM_DEBUG_KMS("CRTC fixup failed\n");
12356                 goto fail;
12357         }
12358
12359         if (ret == RETRY) {
12360                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12361                         ret = -EINVAL;
12362                         goto fail;
12363                 }
12364
12365                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12366                 retry = false;
12367                 goto encoder_retry;
12368         }
12369
12370         /* Dithering seems to not pass-through bits correctly when it should, so
12371          * only enable it on 6bpc panels. */
12372         pipe_config->dither = pipe_config->pipe_bpp == 6*3;
12373         DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
12374                       base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12375
12376 fail:
12377         return ret;
12378 }
12379
12380 static void
12381 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
12382 {
12383         struct drm_crtc *crtc;
12384         struct drm_crtc_state *crtc_state;
12385         int i;
12386
12387         /* Double check state. */
12388         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12389                 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12390
12391                 /* Update hwmode for vblank functions */
12392                 if (crtc->state->active)
12393                         crtc->hwmode = crtc->state->adjusted_mode;
12394                 else
12395                         crtc->hwmode.crtc_clock = 0;
12396
12397                 /*
12398                  * Update legacy state to satisfy fbc code. This can
12399                  * be removed when fbc uses the atomic state.
12400                  */
12401                 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12402                         struct drm_plane_state *plane_state = crtc->primary->state;
12403
12404                         crtc->primary->fb = plane_state->fb;
12405                         crtc->x = plane_state->src_x >> 16;
12406                         crtc->y = plane_state->src_y >> 16;
12407                 }
12408         }
12409 }
12410
12411 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12412 {
12413         int diff;
12414
12415         if (clock1 == clock2)
12416                 return true;
12417
12418         if (!clock1 || !clock2)
12419                 return false;
12420
12421         diff = abs(clock1 - clock2);
12422
12423         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12424                 return true;
12425
12426         return false;
12427 }
12428
12429 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12430         list_for_each_entry((intel_crtc), \
12431                             &(dev)->mode_config.crtc_list, \
12432                             base.head) \
12433                 for_each_if (mask & (1 <<(intel_crtc)->pipe))
12434
12435 static bool
12436 intel_compare_m_n(unsigned int m, unsigned int n,
12437                   unsigned int m2, unsigned int n2,
12438                   bool exact)
12439 {
12440         if (m == m2 && n == n2)
12441                 return true;
12442
12443         if (exact || !m || !n || !m2 || !n2)
12444                 return false;
12445
12446         BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12447
12448         if (n > n2) {
12449                 while (n > n2) {
12450                         m2 <<= 1;
12451                         n2 <<= 1;
12452                 }
12453         } else if (n < n2) {
12454                 while (n < n2) {
12455                         m <<= 1;
12456                         n <<= 1;
12457                 }
12458         }
12459
12460         if (n != n2)
12461                 return false;
12462
12463         return intel_fuzzy_clock_check(m, m2);
12464 }
12465
12466 static bool
12467 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12468                        struct intel_link_m_n *m2_n2,
12469                        bool adjust)
12470 {
12471         if (m_n->tu == m2_n2->tu &&
12472             intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12473                               m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12474             intel_compare_m_n(m_n->link_m, m_n->link_n,
12475                               m2_n2->link_m, m2_n2->link_n, !adjust)) {
12476                 if (adjust)
12477                         *m2_n2 = *m_n;
12478
12479                 return true;
12480         }
12481
12482         return false;
12483 }
12484
12485 static bool
12486 intel_pipe_config_compare(struct drm_device *dev,
12487                           struct intel_crtc_state *current_config,
12488                           struct intel_crtc_state *pipe_config,
12489                           bool adjust)
12490 {
12491         bool ret = true;
12492
12493 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12494         do { \
12495                 if (!adjust) \
12496                         DRM_ERROR(fmt, ##__VA_ARGS__); \
12497                 else \
12498                         DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12499         } while (0)
12500
12501 #define PIPE_CONF_CHECK_X(name) \
12502         if (current_config->name != pipe_config->name) { \
12503                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12504                           "(expected 0x%08x, found 0x%08x)\n", \
12505                           current_config->name, \
12506                           pipe_config->name); \
12507                 ret = false; \
12508         }
12509
12510 #define PIPE_CONF_CHECK_I(name) \
12511         if (current_config->name != pipe_config->name) { \
12512                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12513                           "(expected %i, found %i)\n", \
12514                           current_config->name, \
12515                           pipe_config->name); \
12516                 ret = false; \
12517         }
12518
12519 #define PIPE_CONF_CHECK_P(name) \
12520         if (current_config->name != pipe_config->name) { \
12521                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12522                           "(expected %p, found %p)\n", \
12523                           current_config->name, \
12524                           pipe_config->name); \
12525                 ret = false; \
12526         }
12527
12528 #define PIPE_CONF_CHECK_M_N(name) \
12529         if (!intel_compare_link_m_n(&current_config->name, \
12530                                     &pipe_config->name,\
12531                                     adjust)) { \
12532                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12533                           "(expected tu %i gmch %i/%i link %i/%i, " \
12534                           "found tu %i, gmch %i/%i link %i/%i)\n", \
12535                           current_config->name.tu, \
12536                           current_config->name.gmch_m, \
12537                           current_config->name.gmch_n, \
12538                           current_config->name.link_m, \
12539                           current_config->name.link_n, \
12540                           pipe_config->name.tu, \
12541                           pipe_config->name.gmch_m, \
12542                           pipe_config->name.gmch_n, \
12543                           pipe_config->name.link_m, \
12544                           pipe_config->name.link_n); \
12545                 ret = false; \
12546         }
12547
12548 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12549         if (!intel_compare_link_m_n(&current_config->name, \
12550                                     &pipe_config->name, adjust) && \
12551             !intel_compare_link_m_n(&current_config->alt_name, \
12552                                     &pipe_config->name, adjust)) { \
12553                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12554                           "(expected tu %i gmch %i/%i link %i/%i, " \
12555                           "or tu %i gmch %i/%i link %i/%i, " \
12556                           "found tu %i, gmch %i/%i link %i/%i)\n", \
12557                           current_config->name.tu, \
12558                           current_config->name.gmch_m, \
12559                           current_config->name.gmch_n, \
12560                           current_config->name.link_m, \
12561                           current_config->name.link_n, \
12562                           current_config->alt_name.tu, \
12563                           current_config->alt_name.gmch_m, \
12564                           current_config->alt_name.gmch_n, \
12565                           current_config->alt_name.link_m, \
12566                           current_config->alt_name.link_n, \
12567                           pipe_config->name.tu, \
12568                           pipe_config->name.gmch_m, \
12569                           pipe_config->name.gmch_n, \
12570                           pipe_config->name.link_m, \
12571                           pipe_config->name.link_n); \
12572                 ret = false; \
12573         }
12574
12575 /* This is required for BDW+ where there is only one set of registers for
12576  * switching between high and low RR.
12577  * This macro can be used whenever a comparison has to be made between one
12578  * hw state and multiple sw state variables.
12579  */
12580 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12581         if ((current_config->name != pipe_config->name) && \
12582                 (current_config->alt_name != pipe_config->name)) { \
12583                         INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12584                                   "(expected %i or %i, found %i)\n", \
12585                                   current_config->name, \
12586                                   current_config->alt_name, \
12587                                   pipe_config->name); \
12588                         ret = false; \
12589         }
12590
12591 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
12592         if ((current_config->name ^ pipe_config->name) & (mask)) { \
12593                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
12594                           "(expected %i, found %i)\n", \
12595                           current_config->name & (mask), \
12596                           pipe_config->name & (mask)); \
12597                 ret = false; \
12598         }
12599
12600 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12601         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12602                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12603                           "(expected %i, found %i)\n", \
12604                           current_config->name, \
12605                           pipe_config->name); \
12606                 ret = false; \
12607         }
12608
12609 #define PIPE_CONF_QUIRK(quirk)  \
12610         ((current_config->quirks | pipe_config->quirks) & (quirk))
12611
12612         PIPE_CONF_CHECK_I(cpu_transcoder);
12613
12614         PIPE_CONF_CHECK_I(has_pch_encoder);
12615         PIPE_CONF_CHECK_I(fdi_lanes);
12616         PIPE_CONF_CHECK_M_N(fdi_m_n);
12617
12618         PIPE_CONF_CHECK_I(has_dp_encoder);
12619         PIPE_CONF_CHECK_I(lane_count);
12620
12621         if (INTEL_INFO(dev)->gen < 8) {
12622                 PIPE_CONF_CHECK_M_N(dp_m_n);
12623
12624                 if (current_config->has_drrs)
12625                         PIPE_CONF_CHECK_M_N(dp_m2_n2);
12626         } else
12627                 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
12628
12629         PIPE_CONF_CHECK_I(has_dsi_encoder);
12630
12631         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12632         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12633         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12634         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12635         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12636         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12637
12638         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12639         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12640         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12641         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12642         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12643         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12644
12645         PIPE_CONF_CHECK_I(pixel_multiplier);
12646         PIPE_CONF_CHECK_I(has_hdmi_sink);
12647         if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12648             IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
12649                 PIPE_CONF_CHECK_I(limited_color_range);
12650         PIPE_CONF_CHECK_I(has_infoframe);
12651
12652         PIPE_CONF_CHECK_I(has_audio);
12653
12654         PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12655                               DRM_MODE_FLAG_INTERLACE);
12656
12657         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12658                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12659                                       DRM_MODE_FLAG_PHSYNC);
12660                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12661                                       DRM_MODE_FLAG_NHSYNC);
12662                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12663                                       DRM_MODE_FLAG_PVSYNC);
12664                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12665                                       DRM_MODE_FLAG_NVSYNC);
12666         }
12667
12668         PIPE_CONF_CHECK_X(gmch_pfit.control);
12669         /* pfit ratios are autocomputed by the hw on gen4+ */
12670         if (INTEL_INFO(dev)->gen < 4)
12671                 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12672         PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
12673
12674         if (!adjust) {
12675                 PIPE_CONF_CHECK_I(pipe_src_w);
12676                 PIPE_CONF_CHECK_I(pipe_src_h);
12677
12678                 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12679                 if (current_config->pch_pfit.enabled) {
12680                         PIPE_CONF_CHECK_X(pch_pfit.pos);
12681                         PIPE_CONF_CHECK_X(pch_pfit.size);
12682                 }
12683
12684                 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12685         }
12686
12687         /* BDW+ don't expose a synchronous way to read the state */
12688         if (IS_HASWELL(dev))
12689                 PIPE_CONF_CHECK_I(ips_enabled);
12690
12691         PIPE_CONF_CHECK_I(double_wide);
12692
12693         PIPE_CONF_CHECK_X(ddi_pll_sel);
12694
12695         PIPE_CONF_CHECK_P(shared_dpll);
12696         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12697         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12698         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12699         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12700         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12701         PIPE_CONF_CHECK_X(dpll_hw_state.spll);
12702         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12703         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12704         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12705
12706         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12707                 PIPE_CONF_CHECK_I(pipe_bpp);
12708
12709         PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12710         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12711
12712 #undef PIPE_CONF_CHECK_X
12713 #undef PIPE_CONF_CHECK_I
12714 #undef PIPE_CONF_CHECK_P
12715 #undef PIPE_CONF_CHECK_I_ALT
12716 #undef PIPE_CONF_CHECK_FLAGS
12717 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12718 #undef PIPE_CONF_QUIRK
12719 #undef INTEL_ERR_OR_DBG_KMS
12720
12721         return ret;
12722 }
12723
12724 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
12725                                            const struct intel_crtc_state *pipe_config)
12726 {
12727         if (pipe_config->has_pch_encoder) {
12728                 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
12729                                                             &pipe_config->fdi_m_n);
12730                 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
12731
12732                 /*
12733                  * FDI already provided one idea for the dotclock.
12734                  * Yell if the encoder disagrees.
12735                  */
12736                 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
12737                      "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12738                      fdi_dotclock, dotclock);
12739         }
12740 }
12741
12742 static void check_wm_state(struct drm_device *dev)
12743 {
12744         struct drm_i915_private *dev_priv = dev->dev_private;
12745         struct skl_ddb_allocation hw_ddb, *sw_ddb;
12746         struct intel_crtc *intel_crtc;
12747         int plane;
12748
12749         if (INTEL_INFO(dev)->gen < 9)
12750                 return;
12751
12752         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12753         sw_ddb = &dev_priv->wm.skl_hw.ddb;
12754
12755         for_each_intel_crtc(dev, intel_crtc) {
12756                 struct skl_ddb_entry *hw_entry, *sw_entry;
12757                 const enum pipe pipe = intel_crtc->pipe;
12758
12759                 if (!intel_crtc->active)
12760                         continue;
12761
12762                 /* planes */
12763                 for_each_plane(dev_priv, pipe, plane) {
12764                         hw_entry = &hw_ddb.plane[pipe][plane];
12765                         sw_entry = &sw_ddb->plane[pipe][plane];
12766
12767                         if (skl_ddb_entry_equal(hw_entry, sw_entry))
12768                                 continue;
12769
12770                         DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12771                                   "(expected (%u,%u), found (%u,%u))\n",
12772                                   pipe_name(pipe), plane + 1,
12773                                   sw_entry->start, sw_entry->end,
12774                                   hw_entry->start, hw_entry->end);
12775                 }
12776
12777                 /* cursor */
12778                 hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
12779                 sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
12780
12781                 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12782                         continue;
12783
12784                 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12785                           "(expected (%u,%u), found (%u,%u))\n",
12786                           pipe_name(pipe),
12787                           sw_entry->start, sw_entry->end,
12788                           hw_entry->start, hw_entry->end);
12789         }
12790 }
12791
12792 static void
12793 check_connector_state(struct drm_device *dev,
12794                       struct drm_atomic_state *old_state)
12795 {
12796         struct drm_connector_state *old_conn_state;
12797         struct drm_connector *connector;
12798         int i;
12799
12800         for_each_connector_in_state(old_state, connector, old_conn_state, i) {
12801                 struct drm_encoder *encoder = connector->encoder;
12802                 struct drm_connector_state *state = connector->state;
12803
12804                 /* This also checks the encoder/connector hw state with the
12805                  * ->get_hw_state callbacks. */
12806                 intel_connector_check_state(to_intel_connector(connector));
12807
12808                 I915_STATE_WARN(state->best_encoder != encoder,
12809                      "connector's atomic encoder doesn't match legacy encoder\n");
12810         }
12811 }
12812
12813 static void
12814 check_encoder_state(struct drm_device *dev)
12815 {
12816         struct intel_encoder *encoder;
12817         struct intel_connector *connector;
12818
12819         for_each_intel_encoder(dev, encoder) {
12820                 bool enabled = false;
12821                 enum pipe pipe;
12822
12823                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12824                               encoder->base.base.id,
12825                               encoder->base.name);
12826
12827                 for_each_intel_connector(dev, connector) {
12828                         if (connector->base.state->best_encoder != &encoder->base)
12829                                 continue;
12830                         enabled = true;
12831
12832                         I915_STATE_WARN(connector->base.state->crtc !=
12833                                         encoder->base.crtc,
12834                              "connector's crtc doesn't match encoder crtc\n");
12835                 }
12836
12837                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12838                      "encoder's enabled state mismatch "
12839                      "(expected %i, found %i)\n",
12840                      !!encoder->base.crtc, enabled);
12841
12842                 if (!encoder->base.crtc) {
12843                         bool active;
12844
12845                         active = encoder->get_hw_state(encoder, &pipe);
12846                         I915_STATE_WARN(active,
12847                              "encoder detached but still enabled on pipe %c.\n",
12848                              pipe_name(pipe));
12849                 }
12850         }
12851 }
12852
12853 static void
12854 check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state)
12855 {
12856         struct drm_i915_private *dev_priv = dev->dev_private;
12857         struct intel_encoder *encoder;
12858         struct drm_crtc_state *old_crtc_state;
12859         struct drm_crtc *crtc;
12860         int i;
12861
12862         for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) {
12863                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12864                 struct intel_crtc_state *pipe_config, *sw_config;
12865                 bool active;
12866
12867                 if (!needs_modeset(crtc->state) &&
12868                     !to_intel_crtc_state(crtc->state)->update_pipe)
12869                         continue;
12870
12871                 __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state);
12872                 pipe_config = to_intel_crtc_state(old_crtc_state);
12873                 memset(pipe_config, 0, sizeof(*pipe_config));
12874                 pipe_config->base.crtc = crtc;
12875                 pipe_config->base.state = old_state;
12876
12877                 DRM_DEBUG_KMS("[CRTC:%d]\n",
12878                               crtc->base.id);
12879
12880                 active = dev_priv->display.get_pipe_config(intel_crtc,
12881                                                            pipe_config);
12882
12883                 /* hw state is inconsistent with the pipe quirk */
12884                 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12885                     (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12886                         active = crtc->state->active;
12887
12888                 I915_STATE_WARN(crtc->state->active != active,
12889                      "crtc active state doesn't match with hw state "
12890                      "(expected %i, found %i)\n", crtc->state->active, active);
12891
12892                 I915_STATE_WARN(intel_crtc->active != crtc->state->active,
12893                      "transitional active state does not match atomic hw state "
12894                      "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active);
12895
12896                 for_each_encoder_on_crtc(dev, crtc, encoder) {
12897                         enum pipe pipe;
12898
12899                         active = encoder->get_hw_state(encoder, &pipe);
12900                         I915_STATE_WARN(active != crtc->state->active,
12901                                 "[ENCODER:%i] active %i with crtc active %i\n",
12902                                 encoder->base.base.id, active, crtc->state->active);
12903
12904                         I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12905                                         "Encoder connected to wrong pipe %c\n",
12906                                         pipe_name(pipe));
12907
12908                         if (active)
12909                                 encoder->get_config(encoder, pipe_config);
12910                 }
12911
12912                 if (!crtc->state->active)
12913                         continue;
12914
12915                 intel_pipe_config_sanity_check(dev_priv, pipe_config);
12916
12917                 sw_config = to_intel_crtc_state(crtc->state);
12918                 if (!intel_pipe_config_compare(dev, sw_config,
12919                                                pipe_config, false)) {
12920                         I915_STATE_WARN(1, "pipe state doesn't match!\n");
12921                         intel_dump_pipe_config(intel_crtc, pipe_config,
12922                                                "[hw state]");
12923                         intel_dump_pipe_config(intel_crtc, sw_config,
12924                                                "[sw state]");
12925                 }
12926         }
12927 }
12928
12929 static void
12930 check_shared_dpll_state(struct drm_device *dev)
12931 {
12932         struct drm_i915_private *dev_priv = dev->dev_private;
12933         struct intel_crtc *crtc;
12934         struct intel_dpll_hw_state dpll_hw_state;
12935         int i;
12936
12937         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12938                 struct intel_shared_dpll *pll =
12939                         intel_get_shared_dpll_by_id(dev_priv, i);
12940                 int enabled_crtcs = 0, active_crtcs = 0;
12941                 bool active;
12942
12943                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12944
12945                 DRM_DEBUG_KMS("%s\n", pll->name);
12946
12947                 active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
12948
12949                 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
12950                      "more active pll users than references: %i vs %i\n",
12951                      pll->active, hweight32(pll->config.crtc_mask));
12952                 I915_STATE_WARN(pll->active && !pll->on,
12953                      "pll in active use but not on in sw tracking\n");
12954
12955                 if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
12956                         I915_STATE_WARN(pll->on && !pll->active,
12957                              "pll in on but not on in use in sw tracking\n");
12958                         I915_STATE_WARN(pll->on != active,
12959                              "pll on state mismatch (expected %i, found %i)\n",
12960                              pll->on, active);
12961                 }
12962
12963                 for_each_intel_crtc(dev, crtc) {
12964                         if (crtc->base.state->enable && crtc->config->shared_dpll == pll)
12965                                 enabled_crtcs++;
12966                         if (crtc->active && crtc->config->shared_dpll == pll)
12967                                 active_crtcs++;
12968                 }
12969                 I915_STATE_WARN(pll->active != active_crtcs,
12970                      "pll active crtcs mismatch (expected %i, found %i)\n",
12971                      pll->active, active_crtcs);
12972                 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
12973                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
12974                      hweight32(pll->config.crtc_mask), enabled_crtcs);
12975
12976                 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
12977                                        sizeof(dpll_hw_state)),
12978                      "pll hw state mismatch\n");
12979         }
12980 }
12981
12982 static void
12983 intel_modeset_check_state(struct drm_device *dev,
12984                           struct drm_atomic_state *old_state)
12985 {
12986         check_wm_state(dev);
12987         check_connector_state(dev, old_state);
12988         check_encoder_state(dev);
12989         check_crtc_state(dev, old_state);
12990         check_shared_dpll_state(dev);
12991 }
12992
12993 static void update_scanline_offset(struct intel_crtc *crtc)
12994 {
12995         struct drm_device *dev = crtc->base.dev;
12996
12997         /*
12998          * The scanline counter increments at the leading edge of hsync.
12999          *
13000          * On most platforms it starts counting from vtotal-1 on the
13001          * first active line. That means the scanline counter value is
13002          * always one less than what we would expect. Ie. just after
13003          * start of vblank, which also occurs at start of hsync (on the
13004          * last active line), the scanline counter will read vblank_start-1.
13005          *
13006          * On gen2 the scanline counter starts counting from 1 instead
13007          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
13008          * to keep the value positive), instead of adding one.
13009          *
13010          * On HSW+ the behaviour of the scanline counter depends on the output
13011          * type. For DP ports it behaves like most other platforms, but on HDMI
13012          * there's an extra 1 line difference. So we need to add two instead of
13013          * one to the value.
13014          */
13015         if (IS_GEN2(dev)) {
13016                 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
13017                 int vtotal;
13018
13019                 vtotal = adjusted_mode->crtc_vtotal;
13020                 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
13021                         vtotal /= 2;
13022
13023                 crtc->scanline_offset = vtotal - 1;
13024         } else if (HAS_DDI(dev) &&
13025                    intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
13026                 crtc->scanline_offset = 2;
13027         } else
13028                 crtc->scanline_offset = 1;
13029 }
13030
13031 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
13032 {
13033         struct drm_device *dev = state->dev;
13034         struct drm_i915_private *dev_priv = to_i915(dev);
13035         struct intel_shared_dpll_config *shared_dpll = NULL;
13036         struct drm_crtc *crtc;
13037         struct drm_crtc_state *crtc_state;
13038         int i;
13039
13040         if (!dev_priv->display.crtc_compute_clock)
13041                 return;
13042
13043         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13044                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13045                 struct intel_shared_dpll *old_dpll =
13046                         to_intel_crtc_state(crtc->state)->shared_dpll;
13047
13048                 if (!needs_modeset(crtc_state))
13049                         continue;
13050
13051                 to_intel_crtc_state(crtc_state)->shared_dpll = NULL;
13052
13053                 if (!old_dpll)
13054                         continue;
13055
13056                 if (!shared_dpll)
13057                         shared_dpll = intel_atomic_get_shared_dpll_state(state);
13058
13059                 intel_shared_dpll_config_put(shared_dpll, old_dpll, intel_crtc);
13060         }
13061 }
13062
13063 /*
13064  * This implements the workaround described in the "notes" section of the mode
13065  * set sequence documentation. When going from no pipes or single pipe to
13066  * multiple pipes, and planes are enabled after the pipe, we need to wait at
13067  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13068  */
13069 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
13070 {
13071         struct drm_crtc_state *crtc_state;
13072         struct intel_crtc *intel_crtc;
13073         struct drm_crtc *crtc;
13074         struct intel_crtc_state *first_crtc_state = NULL;
13075         struct intel_crtc_state *other_crtc_state = NULL;
13076         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13077         int i;
13078
13079         /* look at all crtc's that are going to be enabled in during modeset */
13080         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13081                 intel_crtc = to_intel_crtc(crtc);
13082
13083                 if (!crtc_state->active || !needs_modeset(crtc_state))
13084                         continue;
13085
13086                 if (first_crtc_state) {
13087                         other_crtc_state = to_intel_crtc_state(crtc_state);
13088                         break;
13089                 } else {
13090                         first_crtc_state = to_intel_crtc_state(crtc_state);
13091                         first_pipe = intel_crtc->pipe;
13092                 }
13093         }
13094
13095         /* No workaround needed? */
13096         if (!first_crtc_state)
13097                 return 0;
13098
13099         /* w/a possibly needed, check how many crtc's are already enabled. */
13100         for_each_intel_crtc(state->dev, intel_crtc) {
13101                 struct intel_crtc_state *pipe_config;
13102
13103                 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
13104                 if (IS_ERR(pipe_config))
13105                         return PTR_ERR(pipe_config);
13106
13107                 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
13108
13109                 if (!pipe_config->base.active ||
13110                     needs_modeset(&pipe_config->base))
13111                         continue;
13112
13113                 /* 2 or more enabled crtcs means no need for w/a */
13114                 if (enabled_pipe != INVALID_PIPE)
13115                         return 0;
13116
13117                 enabled_pipe = intel_crtc->pipe;
13118         }
13119
13120         if (enabled_pipe != INVALID_PIPE)
13121                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13122         else if (other_crtc_state)
13123                 other_crtc_state->hsw_workaround_pipe = first_pipe;
13124
13125         return 0;
13126 }
13127
13128 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
13129 {
13130         struct drm_crtc *crtc;
13131         struct drm_crtc_state *crtc_state;
13132         int ret = 0;
13133
13134         /* add all active pipes to the state */
13135         for_each_crtc(state->dev, crtc) {
13136                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13137                 if (IS_ERR(crtc_state))
13138                         return PTR_ERR(crtc_state);
13139
13140                 if (!crtc_state->active || needs_modeset(crtc_state))
13141                         continue;
13142
13143                 crtc_state->mode_changed = true;
13144
13145                 ret = drm_atomic_add_affected_connectors(state, crtc);
13146                 if (ret)
13147                         break;
13148
13149                 ret = drm_atomic_add_affected_planes(state, crtc);
13150                 if (ret)
13151                         break;
13152         }
13153
13154         return ret;
13155 }
13156
13157 static int intel_modeset_checks(struct drm_atomic_state *state)
13158 {
13159         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13160         struct drm_i915_private *dev_priv = state->dev->dev_private;
13161         struct drm_crtc *crtc;
13162         struct drm_crtc_state *crtc_state;
13163         int ret = 0, i;
13164
13165         if (!check_digital_port_conflicts(state)) {
13166                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13167                 return -EINVAL;
13168         }
13169
13170         intel_state->modeset = true;
13171         intel_state->active_crtcs = dev_priv->active_crtcs;
13172
13173         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13174                 if (crtc_state->active)
13175                         intel_state->active_crtcs |= 1 << i;
13176                 else
13177                         intel_state->active_crtcs &= ~(1 << i);
13178         }
13179
13180         /*
13181          * See if the config requires any additional preparation, e.g.
13182          * to adjust global state with pipes off.  We need to do this
13183          * here so we can get the modeset_pipe updated config for the new
13184          * mode set on this crtc.  For other crtcs we need to use the
13185          * adjusted_mode bits in the crtc directly.
13186          */
13187         if (dev_priv->display.modeset_calc_cdclk) {
13188                 ret = dev_priv->display.modeset_calc_cdclk(state);
13189
13190                 if (!ret && intel_state->dev_cdclk != dev_priv->cdclk_freq)
13191                         ret = intel_modeset_all_pipes(state);
13192
13193                 if (ret < 0)
13194                         return ret;
13195
13196                 DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n",
13197                               intel_state->cdclk, intel_state->dev_cdclk);
13198         } else
13199                 to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq;
13200
13201         intel_modeset_clear_plls(state);
13202
13203         if (IS_HASWELL(dev_priv))
13204                 return haswell_mode_set_planes_workaround(state);
13205
13206         return 0;
13207 }
13208
13209 /*
13210  * Handle calculation of various watermark data at the end of the atomic check
13211  * phase.  The code here should be run after the per-crtc and per-plane 'check'
13212  * handlers to ensure that all derived state has been updated.
13213  */
13214 static void calc_watermark_data(struct drm_atomic_state *state)
13215 {
13216         struct drm_device *dev = state->dev;
13217         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13218         struct drm_crtc *crtc;
13219         struct drm_crtc_state *cstate;
13220         struct drm_plane *plane;
13221         struct drm_plane_state *pstate;
13222
13223         /*
13224          * Calculate watermark configuration details now that derived
13225          * plane/crtc state is all properly updated.
13226          */
13227         drm_for_each_crtc(crtc, dev) {
13228                 cstate = drm_atomic_get_existing_crtc_state(state, crtc) ?:
13229                         crtc->state;
13230
13231                 if (cstate->active)
13232                         intel_state->wm_config.num_pipes_active++;
13233         }
13234         drm_for_each_legacy_plane(plane, dev) {
13235                 pstate = drm_atomic_get_existing_plane_state(state, plane) ?:
13236                         plane->state;
13237
13238                 if (!to_intel_plane_state(pstate)->visible)
13239                         continue;
13240
13241                 intel_state->wm_config.sprites_enabled = true;
13242                 if (pstate->crtc_w != pstate->src_w >> 16 ||
13243                     pstate->crtc_h != pstate->src_h >> 16)
13244                         intel_state->wm_config.sprites_scaled = true;
13245         }
13246 }
13247
13248 /**
13249  * intel_atomic_check - validate state object
13250  * @dev: drm device
13251  * @state: state to validate
13252  */
13253 static int intel_atomic_check(struct drm_device *dev,
13254                               struct drm_atomic_state *state)
13255 {
13256         struct drm_i915_private *dev_priv = to_i915(dev);
13257         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13258         struct drm_crtc *crtc;
13259         struct drm_crtc_state *crtc_state;
13260         int ret, i;
13261         bool any_ms = false;
13262
13263         ret = drm_atomic_helper_check_modeset(dev, state);
13264         if (ret)
13265                 return ret;
13266
13267         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13268                 struct intel_crtc_state *pipe_config =
13269                         to_intel_crtc_state(crtc_state);
13270
13271                 memset(&to_intel_crtc(crtc)->atomic, 0,
13272                        sizeof(struct intel_crtc_atomic_commit));
13273
13274                 /* Catch I915_MODE_FLAG_INHERITED */
13275                 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13276                         crtc_state->mode_changed = true;
13277
13278                 if (!crtc_state->enable) {
13279                         if (needs_modeset(crtc_state))
13280                                 any_ms = true;
13281                         continue;
13282                 }
13283
13284                 if (!needs_modeset(crtc_state))
13285                         continue;
13286
13287                 /* FIXME: For only active_changed we shouldn't need to do any
13288                  * state recomputation at all. */
13289
13290                 ret = drm_atomic_add_affected_connectors(state, crtc);
13291                 if (ret)
13292                         return ret;
13293
13294                 ret = intel_modeset_pipe_config(crtc, pipe_config);
13295                 if (ret)
13296                         return ret;
13297
13298                 if (i915.fastboot &&
13299                     intel_pipe_config_compare(dev,
13300                                         to_intel_crtc_state(crtc->state),
13301                                         pipe_config, true)) {
13302                         crtc_state->mode_changed = false;
13303                         to_intel_crtc_state(crtc_state)->update_pipe = true;
13304                 }
13305
13306                 if (needs_modeset(crtc_state)) {
13307                         any_ms = true;
13308
13309                         ret = drm_atomic_add_affected_planes(state, crtc);
13310                         if (ret)
13311                                 return ret;
13312                 }
13313
13314                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13315                                        needs_modeset(crtc_state) ?
13316                                        "[modeset]" : "[fastset]");
13317         }
13318
13319         if (any_ms) {
13320                 ret = intel_modeset_checks(state);
13321
13322                 if (ret)
13323                         return ret;
13324         } else
13325                 intel_state->cdclk = dev_priv->cdclk_freq;
13326
13327         ret = drm_atomic_helper_check_planes(dev, state);
13328         if (ret)
13329                 return ret;
13330
13331         intel_fbc_choose_crtc(dev_priv, state);
13332         calc_watermark_data(state);
13333
13334         return 0;
13335 }
13336
13337 static int intel_atomic_prepare_commit(struct drm_device *dev,
13338                                        struct drm_atomic_state *state,
13339                                        bool async)
13340 {
13341         struct drm_i915_private *dev_priv = dev->dev_private;
13342         struct drm_plane_state *plane_state;
13343         struct drm_crtc_state *crtc_state;
13344         struct drm_plane *plane;
13345         struct drm_crtc *crtc;
13346         int i, ret;
13347
13348         if (async) {
13349                 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
13350                 return -EINVAL;
13351         }
13352
13353         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13354                 ret = intel_crtc_wait_for_pending_flips(crtc);
13355                 if (ret)
13356                         return ret;
13357
13358                 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
13359                         flush_workqueue(dev_priv->wq);
13360         }
13361
13362         ret = mutex_lock_interruptible(&dev->struct_mutex);
13363         if (ret)
13364                 return ret;
13365
13366         ret = drm_atomic_helper_prepare_planes(dev, state);
13367         if (!ret && !async && !i915_reset_in_progress(&dev_priv->gpu_error)) {
13368                 u32 reset_counter;
13369
13370                 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
13371                 mutex_unlock(&dev->struct_mutex);
13372
13373                 for_each_plane_in_state(state, plane, plane_state, i) {
13374                         struct intel_plane_state *intel_plane_state =
13375                                 to_intel_plane_state(plane_state);
13376
13377                         if (!intel_plane_state->wait_req)
13378                                 continue;
13379
13380                         ret = __i915_wait_request(intel_plane_state->wait_req,
13381                                                   reset_counter, true,
13382                                                   NULL, NULL);
13383
13384                         /* Swallow -EIO errors to allow updates during hw lockup. */
13385                         if (ret == -EIO)
13386                                 ret = 0;
13387
13388                         if (ret)
13389                                 break;
13390                 }
13391
13392                 if (!ret)
13393                         return 0;
13394
13395                 mutex_lock(&dev->struct_mutex);
13396                 drm_atomic_helper_cleanup_planes(dev, state);
13397         }
13398
13399         mutex_unlock(&dev->struct_mutex);
13400         return ret;
13401 }
13402
13403 static void intel_atomic_wait_for_vblanks(struct drm_device *dev,
13404                                           struct drm_i915_private *dev_priv,
13405                                           unsigned crtc_mask)
13406 {
13407         unsigned last_vblank_count[I915_MAX_PIPES];
13408         enum pipe pipe;
13409         int ret;
13410
13411         if (!crtc_mask)
13412                 return;
13413
13414         for_each_pipe(dev_priv, pipe) {
13415                 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
13416
13417                 if (!((1 << pipe) & crtc_mask))
13418                         continue;
13419
13420                 ret = drm_crtc_vblank_get(crtc);
13421                 if (WARN_ON(ret != 0)) {
13422                         crtc_mask &= ~(1 << pipe);
13423                         continue;
13424                 }
13425
13426                 last_vblank_count[pipe] = drm_crtc_vblank_count(crtc);
13427         }
13428
13429         for_each_pipe(dev_priv, pipe) {
13430                 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
13431                 long lret;
13432
13433                 if (!((1 << pipe) & crtc_mask))
13434                         continue;
13435
13436                 lret = wait_event_timeout(dev->vblank[pipe].queue,
13437                                 last_vblank_count[pipe] !=
13438                                         drm_crtc_vblank_count(crtc),
13439                                 msecs_to_jiffies(50));
13440
13441                 WARN_ON(!lret);
13442
13443                 drm_crtc_vblank_put(crtc);
13444         }
13445 }
13446
13447 static bool needs_vblank_wait(struct intel_crtc_state *crtc_state)
13448 {
13449         /* fb updated, need to unpin old fb */
13450         if (crtc_state->fb_changed)
13451                 return true;
13452
13453         /* wm changes, need vblank before final wm's */
13454         if (crtc_state->update_wm_post)
13455                 return true;
13456
13457         /*
13458          * cxsr is re-enabled after vblank.
13459          * This is already handled by crtc_state->update_wm_post,
13460          * but added for clarity.
13461          */
13462         if (crtc_state->disable_cxsr)
13463                 return true;
13464
13465         return false;
13466 }
13467
13468 /**
13469  * intel_atomic_commit - commit validated state object
13470  * @dev: DRM device
13471  * @state: the top-level driver state object
13472  * @async: asynchronous commit
13473  *
13474  * This function commits a top-level state object that has been validated
13475  * with drm_atomic_helper_check().
13476  *
13477  * FIXME:  Atomic modeset support for i915 is not yet complete.  At the moment
13478  * we can only handle plane-related operations and do not yet support
13479  * asynchronous commit.
13480  *
13481  * RETURNS
13482  * Zero for success or -errno.
13483  */
13484 static int intel_atomic_commit(struct drm_device *dev,
13485                                struct drm_atomic_state *state,
13486                                bool async)
13487 {
13488         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13489         struct drm_i915_private *dev_priv = dev->dev_private;
13490         struct drm_crtc_state *crtc_state;
13491         struct drm_crtc *crtc;
13492         struct intel_crtc_state *intel_cstate;
13493         int ret = 0, i;
13494         bool hw_check = intel_state->modeset;
13495         unsigned long put_domains[I915_MAX_PIPES] = {};
13496         unsigned crtc_vblank_mask = 0;
13497
13498         ret = intel_atomic_prepare_commit(dev, state, async);
13499         if (ret) {
13500                 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
13501                 return ret;
13502         }
13503
13504         drm_atomic_helper_swap_state(dev, state);
13505         dev_priv->wm.config = to_intel_atomic_state(state)->wm_config;
13506
13507         if (intel_state->modeset) {
13508                 memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
13509                        sizeof(intel_state->min_pixclk));
13510                 dev_priv->active_crtcs = intel_state->active_crtcs;
13511                 dev_priv->atomic_cdclk_freq = intel_state->cdclk;
13512
13513                 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
13514         }
13515
13516         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13517                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13518
13519                 if (needs_modeset(crtc->state) ||
13520                     to_intel_crtc_state(crtc->state)->update_pipe) {
13521                         hw_check = true;
13522
13523                         put_domains[to_intel_crtc(crtc)->pipe] =
13524                                 modeset_get_crtc_power_domains(crtc,
13525                                         to_intel_crtc_state(crtc->state));
13526                 }
13527
13528                 if (!needs_modeset(crtc->state))
13529                         continue;
13530
13531                 intel_pre_plane_update(to_intel_crtc_state(crtc_state));
13532
13533                 if (crtc_state->active) {
13534                         intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
13535                         dev_priv->display.crtc_disable(crtc);
13536                         intel_crtc->active = false;
13537                         intel_fbc_disable(intel_crtc);
13538                         intel_disable_shared_dpll(intel_crtc);
13539
13540                         /*
13541                          * Underruns don't always raise
13542                          * interrupts, so check manually.
13543                          */
13544                         intel_check_cpu_fifo_underruns(dev_priv);
13545                         intel_check_pch_fifo_underruns(dev_priv);
13546
13547                         if (!crtc->state->active)
13548                                 intel_update_watermarks(crtc);
13549                 }
13550         }
13551
13552         /* Only after disabling all output pipelines that will be changed can we
13553          * update the the output configuration. */
13554         intel_modeset_update_crtc_state(state);
13555
13556         if (intel_state->modeset) {
13557                 intel_shared_dpll_commit(state);
13558
13559                 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
13560
13561                 if (dev_priv->display.modeset_commit_cdclk &&
13562                     intel_state->dev_cdclk != dev_priv->cdclk_freq)
13563                         dev_priv->display.modeset_commit_cdclk(state);
13564         }
13565
13566         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13567         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13568                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13569                 bool modeset = needs_modeset(crtc->state);
13570                 struct intel_crtc_state *pipe_config =
13571                         to_intel_crtc_state(crtc->state);
13572                 bool update_pipe = !modeset && pipe_config->update_pipe;
13573
13574                 if (modeset && crtc->state->active) {
13575                         update_scanline_offset(to_intel_crtc(crtc));
13576                         dev_priv->display.crtc_enable(crtc);
13577                 }
13578
13579                 if (!modeset)
13580                         intel_pre_plane_update(to_intel_crtc_state(crtc_state));
13581
13582                 if (crtc->state->active && intel_crtc->atomic.update_fbc)
13583                         intel_fbc_enable(intel_crtc);
13584
13585                 if (crtc->state->active &&
13586                     (crtc->state->planes_changed || update_pipe))
13587                         drm_atomic_helper_commit_planes_on_crtc(crtc_state);
13588
13589                 if (pipe_config->base.active && needs_vblank_wait(pipe_config))
13590                         crtc_vblank_mask |= 1 << i;
13591         }
13592
13593         /* FIXME: add subpixel order */
13594
13595         if (!state->legacy_cursor_update)
13596                 intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask);
13597
13598         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13599                 intel_post_plane_update(to_intel_crtc(crtc));
13600
13601                 if (put_domains[i])
13602                         modeset_put_power_domains(dev_priv, put_domains[i]);
13603         }
13604
13605         if (intel_state->modeset)
13606                 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
13607
13608         /*
13609          * Now that the vblank has passed, we can go ahead and program the
13610          * optimal watermarks on platforms that need two-step watermark
13611          * programming.
13612          *
13613          * TODO: Move this (and other cleanup) to an async worker eventually.
13614          */
13615         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13616                 intel_cstate = to_intel_crtc_state(crtc->state);
13617
13618                 if (dev_priv->display.optimize_watermarks)
13619                         dev_priv->display.optimize_watermarks(intel_cstate);
13620         }
13621
13622         mutex_lock(&dev->struct_mutex);
13623         drm_atomic_helper_cleanup_planes(dev, state);
13624         mutex_unlock(&dev->struct_mutex);
13625
13626         if (hw_check)
13627                 intel_modeset_check_state(dev, state);
13628
13629         drm_atomic_state_free(state);
13630
13631         /* As one of the primary mmio accessors, KMS has a high likelihood
13632          * of triggering bugs in unclaimed access. After we finish
13633          * modesetting, see if an error has been flagged, and if so
13634          * enable debugging for the next modeset - and hope we catch
13635          * the culprit.
13636          *
13637          * XXX note that we assume display power is on at this point.
13638          * This might hold true now but we need to add pm helper to check
13639          * unclaimed only when the hardware is on, as atomic commits
13640          * can happen also when the device is completely off.
13641          */
13642         intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
13643
13644         return 0;
13645 }
13646
13647 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13648 {
13649         struct drm_device *dev = crtc->dev;
13650         struct drm_atomic_state *state;
13651         struct drm_crtc_state *crtc_state;
13652         int ret;
13653
13654         state = drm_atomic_state_alloc(dev);
13655         if (!state) {
13656                 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
13657                               crtc->base.id);
13658                 return;
13659         }
13660
13661         state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
13662
13663 retry:
13664         crtc_state = drm_atomic_get_crtc_state(state, crtc);
13665         ret = PTR_ERR_OR_ZERO(crtc_state);
13666         if (!ret) {
13667                 if (!crtc_state->active)
13668                         goto out;
13669
13670                 crtc_state->mode_changed = true;
13671                 ret = drm_atomic_commit(state);
13672         }
13673
13674         if (ret == -EDEADLK) {
13675                 drm_atomic_state_clear(state);
13676                 drm_modeset_backoff(state->acquire_ctx);
13677                 goto retry;
13678         }
13679
13680         if (ret)
13681 out:
13682                 drm_atomic_state_free(state);
13683 }
13684
13685 #undef for_each_intel_crtc_masked
13686
13687 static const struct drm_crtc_funcs intel_crtc_funcs = {
13688         .gamma_set = intel_crtc_gamma_set,
13689         .set_config = drm_atomic_helper_set_config,
13690         .destroy = intel_crtc_destroy,
13691         .page_flip = intel_crtc_page_flip,
13692         .atomic_duplicate_state = intel_crtc_duplicate_state,
13693         .atomic_destroy_state = intel_crtc_destroy_state,
13694 };
13695
13696 /**
13697  * intel_prepare_plane_fb - Prepare fb for usage on plane
13698  * @plane: drm plane to prepare for
13699  * @fb: framebuffer to prepare for presentation
13700  *
13701  * Prepares a framebuffer for usage on a display plane.  Generally this
13702  * involves pinning the underlying object and updating the frontbuffer tracking
13703  * bits.  Some older platforms need special physical address handling for
13704  * cursor planes.
13705  *
13706  * Must be called with struct_mutex held.
13707  *
13708  * Returns 0 on success, negative error code on failure.
13709  */
13710 int
13711 intel_prepare_plane_fb(struct drm_plane *plane,
13712                        const struct drm_plane_state *new_state)
13713 {
13714         struct drm_device *dev = plane->dev;
13715         struct drm_framebuffer *fb = new_state->fb;
13716         struct intel_plane *intel_plane = to_intel_plane(plane);
13717         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13718         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
13719         int ret = 0;
13720
13721         if (!obj && !old_obj)
13722                 return 0;
13723
13724         if (old_obj) {
13725                 struct drm_crtc_state *crtc_state =
13726                         drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc);
13727
13728                 /* Big Hammer, we also need to ensure that any pending
13729                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
13730                  * current scanout is retired before unpinning the old
13731                  * framebuffer. Note that we rely on userspace rendering
13732                  * into the buffer attached to the pipe they are waiting
13733                  * on. If not, userspace generates a GPU hang with IPEHR
13734                  * point to the MI_WAIT_FOR_EVENT.
13735                  *
13736                  * This should only fail upon a hung GPU, in which case we
13737                  * can safely continue.
13738                  */
13739                 if (needs_modeset(crtc_state))
13740                         ret = i915_gem_object_wait_rendering(old_obj, true);
13741
13742                 /* Swallow -EIO errors to allow updates during hw lockup. */
13743                 if (ret && ret != -EIO)
13744                         return ret;
13745         }
13746
13747         /* For framebuffer backed by dmabuf, wait for fence */
13748         if (obj && obj->base.dma_buf) {
13749                 long lret;
13750
13751                 lret = reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv,
13752                                                            false, true,
13753                                                            MAX_SCHEDULE_TIMEOUT);
13754                 if (lret == -ERESTARTSYS)
13755                         return lret;
13756
13757                 WARN(lret < 0, "waiting returns %li\n", lret);
13758         }
13759
13760         if (!obj) {
13761                 ret = 0;
13762         } else if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13763             INTEL_INFO(dev)->cursor_needs_physical) {
13764                 int align = IS_I830(dev) ? 16 * 1024 : 256;
13765                 ret = i915_gem_object_attach_phys(obj, align);
13766                 if (ret)
13767                         DRM_DEBUG_KMS("failed to attach phys object\n");
13768         } else {
13769                 ret = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
13770         }
13771
13772         if (ret == 0) {
13773                 if (obj) {
13774                         struct intel_plane_state *plane_state =
13775                                 to_intel_plane_state(new_state);
13776
13777                         i915_gem_request_assign(&plane_state->wait_req,
13778                                                 obj->last_write_req);
13779                 }
13780
13781                 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13782         }
13783
13784         return ret;
13785 }
13786
13787 /**
13788  * intel_cleanup_plane_fb - Cleans up an fb after plane use
13789  * @plane: drm plane to clean up for
13790  * @fb: old framebuffer that was on plane
13791  *
13792  * Cleans up a framebuffer that has just been removed from a plane.
13793  *
13794  * Must be called with struct_mutex held.
13795  */
13796 void
13797 intel_cleanup_plane_fb(struct drm_plane *plane,
13798                        const struct drm_plane_state *old_state)
13799 {
13800         struct drm_device *dev = plane->dev;
13801         struct intel_plane *intel_plane = to_intel_plane(plane);
13802         struct intel_plane_state *old_intel_state;
13803         struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
13804         struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
13805
13806         old_intel_state = to_intel_plane_state(old_state);
13807
13808         if (!obj && !old_obj)
13809                 return;
13810
13811         if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
13812             !INTEL_INFO(dev)->cursor_needs_physical))
13813                 intel_unpin_fb_obj(old_state->fb, old_state->rotation);
13814
13815         /* prepare_fb aborted? */
13816         if ((old_obj && (old_obj->frontbuffer_bits & intel_plane->frontbuffer_bit)) ||
13817             (obj && !(obj->frontbuffer_bits & intel_plane->frontbuffer_bit)))
13818                 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13819
13820         i915_gem_request_assign(&old_intel_state->wait_req, NULL);
13821 }
13822
13823 int
13824 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13825 {
13826         int max_scale;
13827         struct drm_device *dev;
13828         struct drm_i915_private *dev_priv;
13829         int crtc_clock, cdclk;
13830
13831         if (!intel_crtc || !crtc_state->base.enable)
13832                 return DRM_PLANE_HELPER_NO_SCALING;
13833
13834         dev = intel_crtc->base.dev;
13835         dev_priv = dev->dev_private;
13836         crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13837         cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
13838
13839         if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock))
13840                 return DRM_PLANE_HELPER_NO_SCALING;
13841
13842         /*
13843          * skl max scale is lower of:
13844          *    close to 3 but not 3, -1 is for that purpose
13845          *            or
13846          *    cdclk/crtc_clock
13847          */
13848         max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13849
13850         return max_scale;
13851 }
13852
13853 static int
13854 intel_check_primary_plane(struct drm_plane *plane,
13855                           struct intel_crtc_state *crtc_state,
13856                           struct intel_plane_state *state)
13857 {
13858         struct drm_crtc *crtc = state->base.crtc;
13859         struct drm_framebuffer *fb = state->base.fb;
13860         int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13861         int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13862         bool can_position = false;
13863
13864         if (INTEL_INFO(plane->dev)->gen >= 9) {
13865                 /* use scaler when colorkey is not required */
13866                 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
13867                         min_scale = 1;
13868                         max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13869                 }
13870                 can_position = true;
13871         }
13872
13873         return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13874                                              &state->dst, &state->clip,
13875                                              min_scale, max_scale,
13876                                              can_position, true,
13877                                              &state->visible);
13878 }
13879
13880 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13881                                     struct drm_crtc_state *old_crtc_state)
13882 {
13883         struct drm_device *dev = crtc->dev;
13884         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13885         struct intel_crtc_state *old_intel_state =
13886                 to_intel_crtc_state(old_crtc_state);
13887         bool modeset = needs_modeset(crtc->state);
13888
13889         /* Perform vblank evasion around commit operation */
13890         intel_pipe_update_start(intel_crtc);
13891
13892         if (modeset)
13893                 return;
13894
13895         if (to_intel_crtc_state(crtc->state)->update_pipe)
13896                 intel_update_pipe_config(intel_crtc, old_intel_state);
13897         else if (INTEL_INFO(dev)->gen >= 9)
13898                 skl_detach_scalers(intel_crtc);
13899 }
13900
13901 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13902                                      struct drm_crtc_state *old_crtc_state)
13903 {
13904         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13905
13906         intel_pipe_update_end(intel_crtc);
13907 }
13908
13909 /**
13910  * intel_plane_destroy - destroy a plane
13911  * @plane: plane to destroy
13912  *
13913  * Common destruction function for all types of planes (primary, cursor,
13914  * sprite).
13915  */
13916 void intel_plane_destroy(struct drm_plane *plane)
13917 {
13918         struct intel_plane *intel_plane = to_intel_plane(plane);
13919         drm_plane_cleanup(plane);
13920         kfree(intel_plane);
13921 }
13922
13923 const struct drm_plane_funcs intel_plane_funcs = {
13924         .update_plane = drm_atomic_helper_update_plane,
13925         .disable_plane = drm_atomic_helper_disable_plane,
13926         .destroy = intel_plane_destroy,
13927         .set_property = drm_atomic_helper_plane_set_property,
13928         .atomic_get_property = intel_plane_atomic_get_property,
13929         .atomic_set_property = intel_plane_atomic_set_property,
13930         .atomic_duplicate_state = intel_plane_duplicate_state,
13931         .atomic_destroy_state = intel_plane_destroy_state,
13932
13933 };
13934
13935 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13936                                                     int pipe)
13937 {
13938         struct intel_plane *primary;
13939         struct intel_plane_state *state;
13940         const uint32_t *intel_primary_formats;
13941         unsigned int num_formats;
13942
13943         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13944         if (primary == NULL)
13945                 return NULL;
13946
13947         state = intel_create_plane_state(&primary->base);
13948         if (!state) {
13949                 kfree(primary);
13950                 return NULL;
13951         }
13952         primary->base.state = &state->base;
13953
13954         primary->can_scale = false;
13955         primary->max_downscale = 1;
13956         if (INTEL_INFO(dev)->gen >= 9) {
13957                 primary->can_scale = true;
13958                 state->scaler_id = -1;
13959         }
13960         primary->pipe = pipe;
13961         primary->plane = pipe;
13962         primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
13963         primary->check_plane = intel_check_primary_plane;
13964         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13965                 primary->plane = !pipe;
13966
13967         if (INTEL_INFO(dev)->gen >= 9) {
13968                 intel_primary_formats = skl_primary_formats;
13969                 num_formats = ARRAY_SIZE(skl_primary_formats);
13970
13971                 primary->update_plane = skylake_update_primary_plane;
13972                 primary->disable_plane = skylake_disable_primary_plane;
13973         } else if (HAS_PCH_SPLIT(dev)) {
13974                 intel_primary_formats = i965_primary_formats;
13975                 num_formats = ARRAY_SIZE(i965_primary_formats);
13976
13977                 primary->update_plane = ironlake_update_primary_plane;
13978                 primary->disable_plane = i9xx_disable_primary_plane;
13979         } else if (INTEL_INFO(dev)->gen >= 4) {
13980                 intel_primary_formats = i965_primary_formats;
13981                 num_formats = ARRAY_SIZE(i965_primary_formats);
13982
13983                 primary->update_plane = i9xx_update_primary_plane;
13984                 primary->disable_plane = i9xx_disable_primary_plane;
13985         } else {
13986                 intel_primary_formats = i8xx_primary_formats;
13987                 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13988
13989                 primary->update_plane = i9xx_update_primary_plane;
13990                 primary->disable_plane = i9xx_disable_primary_plane;
13991         }
13992
13993         drm_universal_plane_init(dev, &primary->base, 0,
13994                                  &intel_plane_funcs,
13995                                  intel_primary_formats, num_formats,
13996                                  DRM_PLANE_TYPE_PRIMARY, NULL);
13997
13998         if (INTEL_INFO(dev)->gen >= 4)
13999                 intel_create_rotation_property(dev, primary);
14000
14001         drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
14002
14003         return &primary->base;
14004 }
14005
14006 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
14007 {
14008         if (!dev->mode_config.rotation_property) {
14009                 unsigned long flags = BIT(DRM_ROTATE_0) |
14010                         BIT(DRM_ROTATE_180);
14011
14012                 if (INTEL_INFO(dev)->gen >= 9)
14013                         flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
14014
14015                 dev->mode_config.rotation_property =
14016                         drm_mode_create_rotation_property(dev, flags);
14017         }
14018         if (dev->mode_config.rotation_property)
14019                 drm_object_attach_property(&plane->base.base,
14020                                 dev->mode_config.rotation_property,
14021                                 plane->base.state->rotation);
14022 }
14023
14024 static int
14025 intel_check_cursor_plane(struct drm_plane *plane,
14026                          struct intel_crtc_state *crtc_state,
14027                          struct intel_plane_state *state)
14028 {
14029         struct drm_crtc *crtc = crtc_state->base.crtc;
14030         struct drm_framebuffer *fb = state->base.fb;
14031         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14032         enum pipe pipe = to_intel_plane(plane)->pipe;
14033         unsigned stride;
14034         int ret;
14035
14036         ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
14037                                             &state->dst, &state->clip,
14038                                             DRM_PLANE_HELPER_NO_SCALING,
14039                                             DRM_PLANE_HELPER_NO_SCALING,
14040                                             true, true, &state->visible);
14041         if (ret)
14042                 return ret;
14043
14044         /* if we want to turn off the cursor ignore width and height */
14045         if (!obj)
14046                 return 0;
14047
14048         /* Check for which cursor types we support */
14049         if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
14050                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
14051                           state->base.crtc_w, state->base.crtc_h);
14052                 return -EINVAL;
14053         }
14054
14055         stride = roundup_pow_of_two(state->base.crtc_w) * 4;
14056         if (obj->base.size < stride * state->base.crtc_h) {
14057                 DRM_DEBUG_KMS("buffer is too small\n");
14058                 return -ENOMEM;
14059         }
14060
14061         if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
14062                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
14063                 return -EINVAL;
14064         }
14065
14066         /*
14067          * There's something wrong with the cursor on CHV pipe C.
14068          * If it straddles the left edge of the screen then
14069          * moving it away from the edge or disabling it often
14070          * results in a pipe underrun, and often that can lead to
14071          * dead pipe (constant underrun reported, and it scans
14072          * out just a solid color). To recover from that, the
14073          * display power well must be turned off and on again.
14074          * Refuse the put the cursor into that compromised position.
14075          */
14076         if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C &&
14077             state->visible && state->base.crtc_x < 0) {
14078                 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
14079                 return -EINVAL;
14080         }
14081
14082         return 0;
14083 }
14084
14085 static void
14086 intel_disable_cursor_plane(struct drm_plane *plane,
14087                            struct drm_crtc *crtc)
14088 {
14089         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14090
14091         intel_crtc->cursor_addr = 0;
14092         intel_crtc_update_cursor(crtc, NULL);
14093 }
14094
14095 static void
14096 intel_update_cursor_plane(struct drm_plane *plane,
14097                           const struct intel_crtc_state *crtc_state,
14098                           const struct intel_plane_state *state)
14099 {
14100         struct drm_crtc *crtc = crtc_state->base.crtc;
14101         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14102         struct drm_device *dev = plane->dev;
14103         struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
14104         uint32_t addr;
14105
14106         if (!obj)
14107                 addr = 0;
14108         else if (!INTEL_INFO(dev)->cursor_needs_physical)
14109                 addr = i915_gem_obj_ggtt_offset(obj);
14110         else
14111                 addr = obj->phys_handle->busaddr;
14112
14113         intel_crtc->cursor_addr = addr;
14114         intel_crtc_update_cursor(crtc, state);
14115 }
14116
14117 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
14118                                                    int pipe)
14119 {
14120         struct intel_plane *cursor;
14121         struct intel_plane_state *state;
14122
14123         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
14124         if (cursor == NULL)
14125                 return NULL;
14126
14127         state = intel_create_plane_state(&cursor->base);
14128         if (!state) {
14129                 kfree(cursor);
14130                 return NULL;
14131         }
14132         cursor->base.state = &state->base;
14133
14134         cursor->can_scale = false;
14135         cursor->max_downscale = 1;
14136         cursor->pipe = pipe;
14137         cursor->plane = pipe;
14138         cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
14139         cursor->check_plane = intel_check_cursor_plane;
14140         cursor->update_plane = intel_update_cursor_plane;
14141         cursor->disable_plane = intel_disable_cursor_plane;
14142
14143         drm_universal_plane_init(dev, &cursor->base, 0,
14144                                  &intel_plane_funcs,
14145                                  intel_cursor_formats,
14146                                  ARRAY_SIZE(intel_cursor_formats),
14147                                  DRM_PLANE_TYPE_CURSOR, NULL);
14148
14149         if (INTEL_INFO(dev)->gen >= 4) {
14150                 if (!dev->mode_config.rotation_property)
14151                         dev->mode_config.rotation_property =
14152                                 drm_mode_create_rotation_property(dev,
14153                                                         BIT(DRM_ROTATE_0) |
14154                                                         BIT(DRM_ROTATE_180));
14155                 if (dev->mode_config.rotation_property)
14156                         drm_object_attach_property(&cursor->base.base,
14157                                 dev->mode_config.rotation_property,
14158                                 state->base.rotation);
14159         }
14160
14161         if (INTEL_INFO(dev)->gen >=9)
14162                 state->scaler_id = -1;
14163
14164         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
14165
14166         return &cursor->base;
14167 }
14168
14169 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
14170         struct intel_crtc_state *crtc_state)
14171 {
14172         int i;
14173         struct intel_scaler *intel_scaler;
14174         struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
14175
14176         for (i = 0; i < intel_crtc->num_scalers; i++) {
14177                 intel_scaler = &scaler_state->scalers[i];
14178                 intel_scaler->in_use = 0;
14179                 intel_scaler->mode = PS_SCALER_MODE_DYN;
14180         }
14181
14182         scaler_state->scaler_id = -1;
14183 }
14184
14185 static void intel_crtc_init(struct drm_device *dev, int pipe)
14186 {
14187         struct drm_i915_private *dev_priv = dev->dev_private;
14188         struct intel_crtc *intel_crtc;
14189         struct intel_crtc_state *crtc_state = NULL;
14190         struct drm_plane *primary = NULL;
14191         struct drm_plane *cursor = NULL;
14192         int i, ret;
14193
14194         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
14195         if (intel_crtc == NULL)
14196                 return;
14197
14198         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
14199         if (!crtc_state)
14200                 goto fail;
14201         intel_crtc->config = crtc_state;
14202         intel_crtc->base.state = &crtc_state->base;
14203         crtc_state->base.crtc = &intel_crtc->base;
14204
14205         /* initialize shared scalers */
14206         if (INTEL_INFO(dev)->gen >= 9) {
14207                 if (pipe == PIPE_C)
14208                         intel_crtc->num_scalers = 1;
14209                 else
14210                         intel_crtc->num_scalers = SKL_NUM_SCALERS;
14211
14212                 skl_init_scalers(dev, intel_crtc, crtc_state);
14213         }
14214
14215         primary = intel_primary_plane_create(dev, pipe);
14216         if (!primary)
14217                 goto fail;
14218
14219         cursor = intel_cursor_plane_create(dev, pipe);
14220         if (!cursor)
14221                 goto fail;
14222
14223         ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
14224                                         cursor, &intel_crtc_funcs, NULL);
14225         if (ret)
14226                 goto fail;
14227
14228         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
14229         for (i = 0; i < 256; i++) {
14230                 intel_crtc->lut_r[i] = i;
14231                 intel_crtc->lut_g[i] = i;
14232                 intel_crtc->lut_b[i] = i;
14233         }
14234
14235         /*
14236          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
14237          * is hooked to pipe B. Hence we want plane A feeding pipe B.
14238          */
14239         intel_crtc->pipe = pipe;
14240         intel_crtc->plane = pipe;
14241         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
14242                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
14243                 intel_crtc->plane = !pipe;
14244         }
14245
14246         intel_crtc->cursor_base = ~0;
14247         intel_crtc->cursor_cntl = ~0;
14248         intel_crtc->cursor_size = ~0;
14249
14250         intel_crtc->wm.cxsr_allowed = true;
14251
14252         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14253                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
14254         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
14255         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
14256
14257         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
14258
14259         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
14260         return;
14261
14262 fail:
14263         if (primary)
14264                 drm_plane_cleanup(primary);
14265         if (cursor)
14266                 drm_plane_cleanup(cursor);
14267         kfree(crtc_state);
14268         kfree(intel_crtc);
14269 }
14270
14271 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14272 {
14273         struct drm_encoder *encoder = connector->base.encoder;
14274         struct drm_device *dev = connector->base.dev;
14275
14276         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
14277
14278         if (!encoder || WARN_ON(!encoder->crtc))
14279                 return INVALID_PIPE;
14280
14281         return to_intel_crtc(encoder->crtc)->pipe;
14282 }
14283
14284 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
14285                                 struct drm_file *file)
14286 {
14287         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
14288         struct drm_crtc *drmmode_crtc;
14289         struct intel_crtc *crtc;
14290
14291         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
14292
14293         if (!drmmode_crtc) {
14294                 DRM_ERROR("no such CRTC id\n");
14295                 return -ENOENT;
14296         }
14297
14298         crtc = to_intel_crtc(drmmode_crtc);
14299         pipe_from_crtc_id->pipe = crtc->pipe;
14300
14301         return 0;
14302 }
14303
14304 static int intel_encoder_clones(struct intel_encoder *encoder)
14305 {
14306         struct drm_device *dev = encoder->base.dev;
14307         struct intel_encoder *source_encoder;
14308         int index_mask = 0;
14309         int entry = 0;
14310
14311         for_each_intel_encoder(dev, source_encoder) {
14312                 if (encoders_cloneable(encoder, source_encoder))
14313                         index_mask |= (1 << entry);
14314
14315                 entry++;
14316         }
14317
14318         return index_mask;
14319 }
14320
14321 static bool has_edp_a(struct drm_device *dev)
14322 {
14323         struct drm_i915_private *dev_priv = dev->dev_private;
14324
14325         if (!IS_MOBILE(dev))
14326                 return false;
14327
14328         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14329                 return false;
14330
14331         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14332                 return false;
14333
14334         return true;
14335 }
14336
14337 static bool intel_crt_present(struct drm_device *dev)
14338 {
14339         struct drm_i915_private *dev_priv = dev->dev_private;
14340
14341         if (INTEL_INFO(dev)->gen >= 9)
14342                 return false;
14343
14344         if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
14345                 return false;
14346
14347         if (IS_CHERRYVIEW(dev))
14348                 return false;
14349
14350         if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
14351                 return false;
14352
14353         /* DDI E can't be used if DDI A requires 4 lanes */
14354         if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
14355                 return false;
14356
14357         if (!dev_priv->vbt.int_crt_support)
14358                 return false;
14359
14360         return true;
14361 }
14362
14363 static void intel_setup_outputs(struct drm_device *dev)
14364 {
14365         struct drm_i915_private *dev_priv = dev->dev_private;
14366         struct intel_encoder *encoder;
14367         bool dpd_is_edp = false;
14368
14369         intel_lvds_init(dev);
14370
14371         if (intel_crt_present(dev))
14372                 intel_crt_init(dev);
14373
14374         if (IS_BROXTON(dev)) {
14375                 /*
14376                  * FIXME: Broxton doesn't support port detection via the
14377                  * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14378                  * detect the ports.
14379                  */
14380                 intel_ddi_init(dev, PORT_A);
14381                 intel_ddi_init(dev, PORT_B);
14382                 intel_ddi_init(dev, PORT_C);
14383         } else if (HAS_DDI(dev)) {
14384                 int found;
14385
14386                 /*
14387                  * Haswell uses DDI functions to detect digital outputs.
14388                  * On SKL pre-D0 the strap isn't connected, so we assume
14389                  * it's there.
14390                  */
14391                 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
14392                 /* WaIgnoreDDIAStrap: skl */
14393                 if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
14394                         intel_ddi_init(dev, PORT_A);
14395
14396                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14397                  * register */
14398                 found = I915_READ(SFUSE_STRAP);
14399
14400                 if (found & SFUSE_STRAP_DDIB_DETECTED)
14401                         intel_ddi_init(dev, PORT_B);
14402                 if (found & SFUSE_STRAP_DDIC_DETECTED)
14403                         intel_ddi_init(dev, PORT_C);
14404                 if (found & SFUSE_STRAP_DDID_DETECTED)
14405                         intel_ddi_init(dev, PORT_D);
14406                 /*
14407                  * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14408                  */
14409                 if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
14410                     (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14411                      dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14412                      dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14413                         intel_ddi_init(dev, PORT_E);
14414
14415         } else if (HAS_PCH_SPLIT(dev)) {
14416                 int found;
14417                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
14418
14419                 if (has_edp_a(dev))
14420                         intel_dp_init(dev, DP_A, PORT_A);
14421
14422                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14423                         /* PCH SDVOB multiplex with HDMIB */
14424                         found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B);
14425                         if (!found)
14426                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14427                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14428                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
14429                 }
14430
14431                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14432                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14433
14434                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14435                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14436
14437                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14438                         intel_dp_init(dev, PCH_DP_C, PORT_C);
14439
14440                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14441                         intel_dp_init(dev, PCH_DP_D, PORT_D);
14442         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
14443                 /*
14444                  * The DP_DETECTED bit is the latched state of the DDC
14445                  * SDA pin at boot. However since eDP doesn't require DDC
14446                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
14447                  * eDP ports may have been muxed to an alternate function.
14448                  * Thus we can't rely on the DP_DETECTED bit alone to detect
14449                  * eDP ports. Consult the VBT as well as DP_DETECTED to
14450                  * detect eDP ports.
14451                  */
14452                 if (I915_READ(VLV_HDMIB) & SDVO_DETECTED &&
14453                     !intel_dp_is_edp(dev, PORT_B))
14454                         intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
14455                 if (I915_READ(VLV_DP_B) & DP_DETECTED ||
14456                     intel_dp_is_edp(dev, PORT_B))
14457                         intel_dp_init(dev, VLV_DP_B, PORT_B);
14458
14459                 if (I915_READ(VLV_HDMIC) & SDVO_DETECTED &&
14460                     !intel_dp_is_edp(dev, PORT_C))
14461                         intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
14462                 if (I915_READ(VLV_DP_C) & DP_DETECTED ||
14463                     intel_dp_is_edp(dev, PORT_C))
14464                         intel_dp_init(dev, VLV_DP_C, PORT_C);
14465
14466                 if (IS_CHERRYVIEW(dev)) {
14467                         /* eDP not supported on port D, so don't check VBT */
14468                         if (I915_READ(CHV_HDMID) & SDVO_DETECTED)
14469                                 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
14470                         if (I915_READ(CHV_DP_D) & DP_DETECTED)
14471                                 intel_dp_init(dev, CHV_DP_D, PORT_D);
14472                 }
14473
14474                 intel_dsi_init(dev);
14475         } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
14476                 bool found = false;
14477
14478                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14479                         DRM_DEBUG_KMS("probing SDVOB\n");
14480                         found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B);
14481                         if (!found && IS_G4X(dev)) {
14482                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14483                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14484                         }
14485
14486                         if (!found && IS_G4X(dev))
14487                                 intel_dp_init(dev, DP_B, PORT_B);
14488                 }
14489
14490                 /* Before G4X SDVOC doesn't have its own detect register */
14491
14492                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14493                         DRM_DEBUG_KMS("probing SDVOC\n");
14494                         found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C);
14495                 }
14496
14497                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14498
14499                         if (IS_G4X(dev)) {
14500                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14501                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14502                         }
14503                         if (IS_G4X(dev))
14504                                 intel_dp_init(dev, DP_C, PORT_C);
14505                 }
14506
14507                 if (IS_G4X(dev) &&
14508                     (I915_READ(DP_D) & DP_DETECTED))
14509                         intel_dp_init(dev, DP_D, PORT_D);
14510         } else if (IS_GEN2(dev))
14511                 intel_dvo_init(dev);
14512
14513         if (SUPPORTS_TV(dev))
14514                 intel_tv_init(dev);
14515
14516         intel_psr_init(dev);
14517
14518         for_each_intel_encoder(dev, encoder) {
14519                 encoder->base.possible_crtcs = encoder->crtc_mask;
14520                 encoder->base.possible_clones =
14521                         intel_encoder_clones(encoder);
14522         }
14523
14524         intel_init_pch_refclk(dev);
14525
14526         drm_helper_move_panel_connectors_to_head(dev);
14527 }
14528
14529 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14530 {
14531         struct drm_device *dev = fb->dev;
14532         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14533
14534         drm_framebuffer_cleanup(fb);
14535         mutex_lock(&dev->struct_mutex);
14536         WARN_ON(!intel_fb->obj->framebuffer_references--);
14537         drm_gem_object_unreference(&intel_fb->obj->base);
14538         mutex_unlock(&dev->struct_mutex);
14539         kfree(intel_fb);
14540 }
14541
14542 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14543                                                 struct drm_file *file,
14544                                                 unsigned int *handle)
14545 {
14546         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14547         struct drm_i915_gem_object *obj = intel_fb->obj;
14548
14549         if (obj->userptr.mm) {
14550                 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14551                 return -EINVAL;
14552         }
14553
14554         return drm_gem_handle_create(file, &obj->base, handle);
14555 }
14556
14557 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14558                                         struct drm_file *file,
14559                                         unsigned flags, unsigned color,
14560                                         struct drm_clip_rect *clips,
14561                                         unsigned num_clips)
14562 {
14563         struct drm_device *dev = fb->dev;
14564         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14565         struct drm_i915_gem_object *obj = intel_fb->obj;
14566
14567         mutex_lock(&dev->struct_mutex);
14568         intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
14569         mutex_unlock(&dev->struct_mutex);
14570
14571         return 0;
14572 }
14573
14574 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14575         .destroy = intel_user_framebuffer_destroy,
14576         .create_handle = intel_user_framebuffer_create_handle,
14577         .dirty = intel_user_framebuffer_dirty,
14578 };
14579
14580 static
14581 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14582                          uint32_t pixel_format)
14583 {
14584         u32 gen = INTEL_INFO(dev)->gen;
14585
14586         if (gen >= 9) {
14587                 int cpp = drm_format_plane_cpp(pixel_format, 0);
14588
14589                 /* "The stride in bytes must not exceed the of the size of 8K
14590                  *  pixels and 32K bytes."
14591                  */
14592                 return min(8192 * cpp, 32768);
14593         } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
14594                 return 32*1024;
14595         } else if (gen >= 4) {
14596                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14597                         return 16*1024;
14598                 else
14599                         return 32*1024;
14600         } else if (gen >= 3) {
14601                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14602                         return 8*1024;
14603                 else
14604                         return 16*1024;
14605         } else {
14606                 /* XXX DSPC is limited to 4k tiled */
14607                 return 8*1024;
14608         }
14609 }
14610
14611 static int intel_framebuffer_init(struct drm_device *dev,
14612                                   struct intel_framebuffer *intel_fb,
14613                                   struct drm_mode_fb_cmd2 *mode_cmd,
14614                                   struct drm_i915_gem_object *obj)
14615 {
14616         struct drm_i915_private *dev_priv = to_i915(dev);
14617         unsigned int aligned_height;
14618         int ret;
14619         u32 pitch_limit, stride_alignment;
14620
14621         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14622
14623         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14624                 /* Enforce that fb modifier and tiling mode match, but only for
14625                  * X-tiled. This is needed for FBC. */
14626                 if (!!(obj->tiling_mode == I915_TILING_X) !=
14627                     !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14628                         DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14629                         return -EINVAL;
14630                 }
14631         } else {
14632                 if (obj->tiling_mode == I915_TILING_X)
14633                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14634                 else if (obj->tiling_mode == I915_TILING_Y) {
14635                         DRM_DEBUG("No Y tiling for legacy addfb\n");
14636                         return -EINVAL;
14637                 }
14638         }
14639
14640         /* Passed in modifier sanity checking. */
14641         switch (mode_cmd->modifier[0]) {
14642         case I915_FORMAT_MOD_Y_TILED:
14643         case I915_FORMAT_MOD_Yf_TILED:
14644                 if (INTEL_INFO(dev)->gen < 9) {
14645                         DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14646                                   mode_cmd->modifier[0]);
14647                         return -EINVAL;
14648                 }
14649         case DRM_FORMAT_MOD_NONE:
14650         case I915_FORMAT_MOD_X_TILED:
14651                 break;
14652         default:
14653                 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14654                           mode_cmd->modifier[0]);
14655                 return -EINVAL;
14656         }
14657
14658         stride_alignment = intel_fb_stride_alignment(dev_priv,
14659                                                      mode_cmd->modifier[0],
14660                                                      mode_cmd->pixel_format);
14661         if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14662                 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14663                           mode_cmd->pitches[0], stride_alignment);
14664                 return -EINVAL;
14665         }
14666
14667         pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14668                                            mode_cmd->pixel_format);
14669         if (mode_cmd->pitches[0] > pitch_limit) {
14670                 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14671                           mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14672                           "tiled" : "linear",
14673                           mode_cmd->pitches[0], pitch_limit);
14674                 return -EINVAL;
14675         }
14676
14677         if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14678             mode_cmd->pitches[0] != obj->stride) {
14679                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14680                           mode_cmd->pitches[0], obj->stride);
14681                 return -EINVAL;
14682         }
14683
14684         /* Reject formats not supported by any plane early. */
14685         switch (mode_cmd->pixel_format) {
14686         case DRM_FORMAT_C8:
14687         case DRM_FORMAT_RGB565:
14688         case DRM_FORMAT_XRGB8888:
14689         case DRM_FORMAT_ARGB8888:
14690                 break;
14691         case DRM_FORMAT_XRGB1555:
14692                 if (INTEL_INFO(dev)->gen > 3) {
14693                         DRM_DEBUG("unsupported pixel format: %s\n",
14694                                   drm_get_format_name(mode_cmd->pixel_format));
14695                         return -EINVAL;
14696                 }
14697                 break;
14698         case DRM_FORMAT_ABGR8888:
14699                 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
14700                     INTEL_INFO(dev)->gen < 9) {
14701                         DRM_DEBUG("unsupported pixel format: %s\n",
14702                                   drm_get_format_name(mode_cmd->pixel_format));
14703                         return -EINVAL;
14704                 }
14705                 break;
14706         case DRM_FORMAT_XBGR8888:
14707         case DRM_FORMAT_XRGB2101010:
14708         case DRM_FORMAT_XBGR2101010:
14709                 if (INTEL_INFO(dev)->gen < 4) {
14710                         DRM_DEBUG("unsupported pixel format: %s\n",
14711                                   drm_get_format_name(mode_cmd->pixel_format));
14712                         return -EINVAL;
14713                 }
14714                 break;
14715         case DRM_FORMAT_ABGR2101010:
14716                 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
14717                         DRM_DEBUG("unsupported pixel format: %s\n",
14718                                   drm_get_format_name(mode_cmd->pixel_format));
14719                         return -EINVAL;
14720                 }
14721                 break;
14722         case DRM_FORMAT_YUYV:
14723         case DRM_FORMAT_UYVY:
14724         case DRM_FORMAT_YVYU:
14725         case DRM_FORMAT_VYUY:
14726                 if (INTEL_INFO(dev)->gen < 5) {
14727                         DRM_DEBUG("unsupported pixel format: %s\n",
14728                                   drm_get_format_name(mode_cmd->pixel_format));
14729                         return -EINVAL;
14730                 }
14731                 break;
14732         default:
14733                 DRM_DEBUG("unsupported pixel format: %s\n",
14734                           drm_get_format_name(mode_cmd->pixel_format));
14735                 return -EINVAL;
14736         }
14737
14738         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14739         if (mode_cmd->offsets[0] != 0)
14740                 return -EINVAL;
14741
14742         aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14743                                                mode_cmd->pixel_format,
14744                                                mode_cmd->modifier[0]);
14745         /* FIXME drm helper for size checks (especially planar formats)? */
14746         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14747                 return -EINVAL;
14748
14749         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14750         intel_fb->obj = obj;
14751
14752         intel_fill_fb_info(dev_priv, &intel_fb->base);
14753
14754         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14755         if (ret) {
14756                 DRM_ERROR("framebuffer init failed %d\n", ret);
14757                 return ret;
14758         }
14759
14760         intel_fb->obj->framebuffer_references++;
14761
14762         return 0;
14763 }
14764
14765 static struct drm_framebuffer *
14766 intel_user_framebuffer_create(struct drm_device *dev,
14767                               struct drm_file *filp,
14768                               const struct drm_mode_fb_cmd2 *user_mode_cmd)
14769 {
14770         struct drm_framebuffer *fb;
14771         struct drm_i915_gem_object *obj;
14772         struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
14773
14774         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14775                                                 mode_cmd.handles[0]));
14776         if (&obj->base == NULL)
14777                 return ERR_PTR(-ENOENT);
14778
14779         fb = intel_framebuffer_create(dev, &mode_cmd, obj);
14780         if (IS_ERR(fb))
14781                 drm_gem_object_unreference_unlocked(&obj->base);
14782
14783         return fb;
14784 }
14785
14786 #ifndef CONFIG_DRM_FBDEV_EMULATION
14787 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14788 {
14789 }
14790 #endif
14791
14792 static const struct drm_mode_config_funcs intel_mode_funcs = {
14793         .fb_create = intel_user_framebuffer_create,
14794         .output_poll_changed = intel_fbdev_output_poll_changed,
14795         .atomic_check = intel_atomic_check,
14796         .atomic_commit = intel_atomic_commit,
14797         .atomic_state_alloc = intel_atomic_state_alloc,
14798         .atomic_state_clear = intel_atomic_state_clear,
14799 };
14800
14801 /* Set up chip specific display functions */
14802 static void intel_init_display(struct drm_device *dev)
14803 {
14804         struct drm_i915_private *dev_priv = dev->dev_private;
14805
14806         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14807                 dev_priv->display.find_dpll = g4x_find_best_dpll;
14808         else if (IS_CHERRYVIEW(dev))
14809                 dev_priv->display.find_dpll = chv_find_best_dpll;
14810         else if (IS_VALLEYVIEW(dev))
14811                 dev_priv->display.find_dpll = vlv_find_best_dpll;
14812         else if (IS_PINEVIEW(dev))
14813                 dev_priv->display.find_dpll = pnv_find_best_dpll;
14814         else
14815                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14816
14817         if (INTEL_INFO(dev)->gen >= 9) {
14818                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14819                 dev_priv->display.get_initial_plane_config =
14820                         skylake_get_initial_plane_config;
14821                 dev_priv->display.crtc_compute_clock =
14822                         haswell_crtc_compute_clock;
14823                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14824                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14825         } else if (HAS_DDI(dev)) {
14826                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14827                 dev_priv->display.get_initial_plane_config =
14828                         ironlake_get_initial_plane_config;
14829                 dev_priv->display.crtc_compute_clock =
14830                         haswell_crtc_compute_clock;
14831                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14832                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14833         } else if (HAS_PCH_SPLIT(dev)) {
14834                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14835                 dev_priv->display.get_initial_plane_config =
14836                         ironlake_get_initial_plane_config;
14837                 dev_priv->display.crtc_compute_clock =
14838                         ironlake_crtc_compute_clock;
14839                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14840                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14841         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
14842                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14843                 dev_priv->display.get_initial_plane_config =
14844                         i9xx_get_initial_plane_config;
14845                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14846                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14847                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14848         } else {
14849                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14850                 dev_priv->display.get_initial_plane_config =
14851                         i9xx_get_initial_plane_config;
14852                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14853                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14854                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14855         }
14856
14857         /* Returns the core display clock speed */
14858         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
14859                 dev_priv->display.get_display_clock_speed =
14860                         skylake_get_display_clock_speed;
14861         else if (IS_BROXTON(dev))
14862                 dev_priv->display.get_display_clock_speed =
14863                         broxton_get_display_clock_speed;
14864         else if (IS_BROADWELL(dev))
14865                 dev_priv->display.get_display_clock_speed =
14866                         broadwell_get_display_clock_speed;
14867         else if (IS_HASWELL(dev))
14868                 dev_priv->display.get_display_clock_speed =
14869                         haswell_get_display_clock_speed;
14870         else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
14871                 dev_priv->display.get_display_clock_speed =
14872                         valleyview_get_display_clock_speed;
14873         else if (IS_GEN5(dev))
14874                 dev_priv->display.get_display_clock_speed =
14875                         ilk_get_display_clock_speed;
14876         else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14877                  IS_GEN6(dev) || IS_IVYBRIDGE(dev))
14878                 dev_priv->display.get_display_clock_speed =
14879                         i945_get_display_clock_speed;
14880         else if (IS_GM45(dev))
14881                 dev_priv->display.get_display_clock_speed =
14882                         gm45_get_display_clock_speed;
14883         else if (IS_CRESTLINE(dev))
14884                 dev_priv->display.get_display_clock_speed =
14885                         i965gm_get_display_clock_speed;
14886         else if (IS_PINEVIEW(dev))
14887                 dev_priv->display.get_display_clock_speed =
14888                         pnv_get_display_clock_speed;
14889         else if (IS_G33(dev) || IS_G4X(dev))
14890                 dev_priv->display.get_display_clock_speed =
14891                         g33_get_display_clock_speed;
14892         else if (IS_I915G(dev))
14893                 dev_priv->display.get_display_clock_speed =
14894                         i915_get_display_clock_speed;
14895         else if (IS_I945GM(dev) || IS_845G(dev))
14896                 dev_priv->display.get_display_clock_speed =
14897                         i9xx_misc_get_display_clock_speed;
14898         else if (IS_I915GM(dev))
14899                 dev_priv->display.get_display_clock_speed =
14900                         i915gm_get_display_clock_speed;
14901         else if (IS_I865G(dev))
14902                 dev_priv->display.get_display_clock_speed =
14903                         i865_get_display_clock_speed;
14904         else if (IS_I85X(dev))
14905                 dev_priv->display.get_display_clock_speed =
14906                         i85x_get_display_clock_speed;
14907         else { /* 830 */
14908                 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
14909                 dev_priv->display.get_display_clock_speed =
14910                         i830_get_display_clock_speed;
14911         }
14912
14913         if (IS_GEN5(dev)) {
14914                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14915         } else if (IS_GEN6(dev)) {
14916                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14917         } else if (IS_IVYBRIDGE(dev)) {
14918                 /* FIXME: detect B0+ stepping and use auto training */
14919                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14920         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
14921                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14922                 if (IS_BROADWELL(dev)) {
14923                         dev_priv->display.modeset_commit_cdclk =
14924                                 broadwell_modeset_commit_cdclk;
14925                         dev_priv->display.modeset_calc_cdclk =
14926                                 broadwell_modeset_calc_cdclk;
14927                 }
14928         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
14929                 dev_priv->display.modeset_commit_cdclk =
14930                         valleyview_modeset_commit_cdclk;
14931                 dev_priv->display.modeset_calc_cdclk =
14932                         valleyview_modeset_calc_cdclk;
14933         } else if (IS_BROXTON(dev)) {
14934                 dev_priv->display.modeset_commit_cdclk =
14935                         broxton_modeset_commit_cdclk;
14936                 dev_priv->display.modeset_calc_cdclk =
14937                         broxton_modeset_calc_cdclk;
14938         }
14939
14940         switch (INTEL_INFO(dev)->gen) {
14941         case 2:
14942                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14943                 break;
14944
14945         case 3:
14946                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14947                 break;
14948
14949         case 4:
14950         case 5:
14951                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14952                 break;
14953
14954         case 6:
14955                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14956                 break;
14957         case 7:
14958         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14959                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14960                 break;
14961         case 9:
14962                 /* Drop through - unsupported since execlist only. */
14963         default:
14964                 /* Default just returns -ENODEV to indicate unsupported */
14965                 dev_priv->display.queue_flip = intel_default_queue_flip;
14966         }
14967
14968         mutex_init(&dev_priv->pps_mutex);
14969 }
14970
14971 /*
14972  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14973  * resume, or other times.  This quirk makes sure that's the case for
14974  * affected systems.
14975  */
14976 static void quirk_pipea_force(struct drm_device *dev)
14977 {
14978         struct drm_i915_private *dev_priv = dev->dev_private;
14979
14980         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14981         DRM_INFO("applying pipe a force quirk\n");
14982 }
14983
14984 static void quirk_pipeb_force(struct drm_device *dev)
14985 {
14986         struct drm_i915_private *dev_priv = dev->dev_private;
14987
14988         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14989         DRM_INFO("applying pipe b force quirk\n");
14990 }
14991
14992 /*
14993  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14994  */
14995 static void quirk_ssc_force_disable(struct drm_device *dev)
14996 {
14997         struct drm_i915_private *dev_priv = dev->dev_private;
14998         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14999         DRM_INFO("applying lvds SSC disable quirk\n");
15000 }
15001
15002 /*
15003  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
15004  * brightness value
15005  */
15006 static void quirk_invert_brightness(struct drm_device *dev)
15007 {
15008         struct drm_i915_private *dev_priv = dev->dev_private;
15009         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
15010         DRM_INFO("applying inverted panel brightness quirk\n");
15011 }
15012
15013 /* Some VBT's incorrectly indicate no backlight is present */
15014 static void quirk_backlight_present(struct drm_device *dev)
15015 {
15016         struct drm_i915_private *dev_priv = dev->dev_private;
15017         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
15018         DRM_INFO("applying backlight present quirk\n");
15019 }
15020
15021 struct intel_quirk {
15022         int device;
15023         int subsystem_vendor;
15024         int subsystem_device;
15025         void (*hook)(struct drm_device *dev);
15026 };
15027
15028 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
15029 struct intel_dmi_quirk {
15030         void (*hook)(struct drm_device *dev);
15031         const struct dmi_system_id (*dmi_id_list)[];
15032 };
15033
15034 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
15035 {
15036         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
15037         return 1;
15038 }
15039
15040 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
15041         {
15042                 .dmi_id_list = &(const struct dmi_system_id[]) {
15043                         {
15044                                 .callback = intel_dmi_reverse_brightness,
15045                                 .ident = "NCR Corporation",
15046                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
15047                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
15048                                 },
15049                         },
15050                         { }  /* terminating entry */
15051                 },
15052                 .hook = quirk_invert_brightness,
15053         },
15054 };
15055
15056 static struct intel_quirk intel_quirks[] = {
15057         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
15058         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
15059
15060         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
15061         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
15062
15063         /* 830 needs to leave pipe A & dpll A up */
15064         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
15065
15066         /* 830 needs to leave pipe B & dpll B up */
15067         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
15068
15069         /* Lenovo U160 cannot use SSC on LVDS */
15070         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
15071
15072         /* Sony Vaio Y cannot use SSC on LVDS */
15073         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
15074
15075         /* Acer Aspire 5734Z must invert backlight brightness */
15076         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
15077
15078         /* Acer/eMachines G725 */
15079         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
15080
15081         /* Acer/eMachines e725 */
15082         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
15083
15084         /* Acer/Packard Bell NCL20 */
15085         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
15086
15087         /* Acer Aspire 4736Z */
15088         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
15089
15090         /* Acer Aspire 5336 */
15091         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
15092
15093         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
15094         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
15095
15096         /* Acer C720 Chromebook (Core i3 4005U) */
15097         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
15098
15099         /* Apple Macbook 2,1 (Core 2 T7400) */
15100         { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
15101
15102         /* Apple Macbook 4,1 */
15103         { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
15104
15105         /* Toshiba CB35 Chromebook (Celeron 2955U) */
15106         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
15107
15108         /* HP Chromebook 14 (Celeron 2955U) */
15109         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
15110
15111         /* Dell Chromebook 11 */
15112         { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
15113
15114         /* Dell Chromebook 11 (2015 version) */
15115         { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
15116 };
15117
15118 static void intel_init_quirks(struct drm_device *dev)
15119 {
15120         struct pci_dev *d = dev->pdev;
15121         int i;
15122
15123         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
15124                 struct intel_quirk *q = &intel_quirks[i];
15125
15126                 if (d->device == q->device &&
15127                     (d->subsystem_vendor == q->subsystem_vendor ||
15128                      q->subsystem_vendor == PCI_ANY_ID) &&
15129                     (d->subsystem_device == q->subsystem_device ||
15130                      q->subsystem_device == PCI_ANY_ID))
15131                         q->hook(dev);
15132         }
15133         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
15134                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
15135                         intel_dmi_quirks[i].hook(dev);
15136         }
15137 }
15138
15139 /* Disable the VGA plane that we never use */
15140 static void i915_disable_vga(struct drm_device *dev)
15141 {
15142         struct drm_i915_private *dev_priv = dev->dev_private;
15143         u8 sr1;
15144         i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15145
15146         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
15147         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
15148         outb(SR01, VGA_SR_INDEX);
15149         sr1 = inb(VGA_SR_DATA);
15150         outb(sr1 | 1<<5, VGA_SR_DATA);
15151         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
15152         udelay(300);
15153
15154         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
15155         POSTING_READ(vga_reg);
15156 }
15157
15158 void intel_modeset_init_hw(struct drm_device *dev)
15159 {
15160         struct drm_i915_private *dev_priv = dev->dev_private;
15161
15162         intel_update_cdclk(dev);
15163
15164         dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq;
15165
15166         intel_init_clock_gating(dev);
15167         intel_enable_gt_powersave(dev);
15168 }
15169
15170 /*
15171  * Calculate what we think the watermarks should be for the state we've read
15172  * out of the hardware and then immediately program those watermarks so that
15173  * we ensure the hardware settings match our internal state.
15174  *
15175  * We can calculate what we think WM's should be by creating a duplicate of the
15176  * current state (which was constructed during hardware readout) and running it
15177  * through the atomic check code to calculate new watermark values in the
15178  * state object.
15179  */
15180 static void sanitize_watermarks(struct drm_device *dev)
15181 {
15182         struct drm_i915_private *dev_priv = to_i915(dev);
15183         struct drm_atomic_state *state;
15184         struct drm_crtc *crtc;
15185         struct drm_crtc_state *cstate;
15186         struct drm_modeset_acquire_ctx ctx;
15187         int ret;
15188         int i;
15189
15190         /* Only supported on platforms that use atomic watermark design */
15191         if (!dev_priv->display.optimize_watermarks)
15192                 return;
15193
15194         /*
15195          * We need to hold connection_mutex before calling duplicate_state so
15196          * that the connector loop is protected.
15197          */
15198         drm_modeset_acquire_init(&ctx, 0);
15199 retry:
15200         ret = drm_modeset_lock_all_ctx(dev, &ctx);
15201         if (ret == -EDEADLK) {
15202                 drm_modeset_backoff(&ctx);
15203                 goto retry;
15204         } else if (WARN_ON(ret)) {
15205                 goto fail;
15206         }
15207
15208         state = drm_atomic_helper_duplicate_state(dev, &ctx);
15209         if (WARN_ON(IS_ERR(state)))
15210                 goto fail;
15211
15212         /*
15213          * Hardware readout is the only time we don't want to calculate
15214          * intermediate watermarks (since we don't trust the current
15215          * watermarks).
15216          */
15217         to_intel_atomic_state(state)->skip_intermediate_wm = true;
15218
15219         ret = intel_atomic_check(dev, state);
15220         if (ret) {
15221                 /*
15222                  * If we fail here, it means that the hardware appears to be
15223                  * programmed in a way that shouldn't be possible, given our
15224                  * understanding of watermark requirements.  This might mean a
15225                  * mistake in the hardware readout code or a mistake in the
15226                  * watermark calculations for a given platform.  Raise a WARN
15227                  * so that this is noticeable.
15228                  *
15229                  * If this actually happens, we'll have to just leave the
15230                  * BIOS-programmed watermarks untouched and hope for the best.
15231                  */
15232                 WARN(true, "Could not determine valid watermarks for inherited state\n");
15233                 goto fail;
15234         }
15235
15236         /* Write calculated watermark values back */
15237         to_i915(dev)->wm.config = to_intel_atomic_state(state)->wm_config;
15238         for_each_crtc_in_state(state, crtc, cstate, i) {
15239                 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
15240
15241                 cs->wm.need_postvbl_update = true;
15242                 dev_priv->display.optimize_watermarks(cs);
15243         }
15244
15245         drm_atomic_state_free(state);
15246 fail:
15247         drm_modeset_drop_locks(&ctx);
15248         drm_modeset_acquire_fini(&ctx);
15249 }
15250
15251 void intel_modeset_init(struct drm_device *dev)
15252 {
15253         struct drm_i915_private *dev_priv = dev->dev_private;
15254         int sprite, ret;
15255         enum pipe pipe;
15256         struct intel_crtc *crtc;
15257
15258         drm_mode_config_init(dev);
15259
15260         dev->mode_config.min_width = 0;
15261         dev->mode_config.min_height = 0;
15262
15263         dev->mode_config.preferred_depth = 24;
15264         dev->mode_config.prefer_shadow = 1;
15265
15266         dev->mode_config.allow_fb_modifiers = true;
15267
15268         dev->mode_config.funcs = &intel_mode_funcs;
15269
15270         intel_init_quirks(dev);
15271
15272         intel_init_pm(dev);
15273
15274         if (INTEL_INFO(dev)->num_pipes == 0)
15275                 return;
15276
15277         /*
15278          * There may be no VBT; and if the BIOS enabled SSC we can
15279          * just keep using it to avoid unnecessary flicker.  Whereas if the
15280          * BIOS isn't using it, don't assume it will work even if the VBT
15281          * indicates as much.
15282          */
15283         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
15284                 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15285                                             DREF_SSC1_ENABLE);
15286
15287                 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
15288                         DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
15289                                      bios_lvds_use_ssc ? "en" : "dis",
15290                                      dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
15291                         dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
15292                 }
15293         }
15294
15295         intel_init_display(dev);
15296         intel_init_audio(dev);
15297
15298         if (IS_GEN2(dev)) {
15299                 dev->mode_config.max_width = 2048;
15300                 dev->mode_config.max_height = 2048;
15301         } else if (IS_GEN3(dev)) {
15302                 dev->mode_config.max_width = 4096;
15303                 dev->mode_config.max_height = 4096;
15304         } else {
15305                 dev->mode_config.max_width = 8192;
15306                 dev->mode_config.max_height = 8192;
15307         }
15308
15309         if (IS_845G(dev) || IS_I865G(dev)) {
15310                 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
15311                 dev->mode_config.cursor_height = 1023;
15312         } else if (IS_GEN2(dev)) {
15313                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
15314                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
15315         } else {
15316                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
15317                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15318         }
15319
15320         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
15321
15322         DRM_DEBUG_KMS("%d display pipe%s available.\n",
15323                       INTEL_INFO(dev)->num_pipes,
15324                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
15325
15326         for_each_pipe(dev_priv, pipe) {
15327                 intel_crtc_init(dev, pipe);
15328                 for_each_sprite(dev_priv, pipe, sprite) {
15329                         ret = intel_plane_init(dev, pipe, sprite);
15330                         if (ret)
15331                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
15332                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
15333                 }
15334         }
15335
15336         intel_update_czclk(dev_priv);
15337         intel_update_rawclk(dev_priv);
15338         intel_update_cdclk(dev);
15339
15340         intel_shared_dpll_init(dev);
15341
15342         /* Just disable it once at startup */
15343         i915_disable_vga(dev);
15344         intel_setup_outputs(dev);
15345
15346         drm_modeset_lock_all(dev);
15347         intel_modeset_setup_hw_state(dev);
15348         drm_modeset_unlock_all(dev);
15349
15350         for_each_intel_crtc(dev, crtc) {
15351                 struct intel_initial_plane_config plane_config = {};
15352
15353                 if (!crtc->active)
15354                         continue;
15355
15356                 /*
15357                  * Note that reserving the BIOS fb up front prevents us
15358                  * from stuffing other stolen allocations like the ring
15359                  * on top.  This prevents some ugliness at boot time, and
15360                  * can even allow for smooth boot transitions if the BIOS
15361                  * fb is large enough for the active pipe configuration.
15362                  */
15363                 dev_priv->display.get_initial_plane_config(crtc,
15364                                                            &plane_config);
15365
15366                 /*
15367                  * If the fb is shared between multiple heads, we'll
15368                  * just get the first one.
15369                  */
15370                 intel_find_initial_plane_obj(crtc, &plane_config);
15371         }
15372
15373         /*
15374          * Make sure hardware watermarks really match the state we read out.
15375          * Note that we need to do this after reconstructing the BIOS fb's
15376          * since the watermark calculation done here will use pstate->fb.
15377          */
15378         sanitize_watermarks(dev);
15379 }
15380
15381 static void intel_enable_pipe_a(struct drm_device *dev)
15382 {
15383         struct intel_connector *connector;
15384         struct drm_connector *crt = NULL;
15385         struct intel_load_detect_pipe load_detect_temp;
15386         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
15387
15388         /* We can't just switch on the pipe A, we need to set things up with a
15389          * proper mode and output configuration. As a gross hack, enable pipe A
15390          * by enabling the load detect pipe once. */
15391         for_each_intel_connector(dev, connector) {
15392                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15393                         crt = &connector->base;
15394                         break;
15395                 }
15396         }
15397
15398         if (!crt)
15399                 return;
15400
15401         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
15402                 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
15403 }
15404
15405 static bool
15406 intel_check_plane_mapping(struct intel_crtc *crtc)
15407 {
15408         struct drm_device *dev = crtc->base.dev;
15409         struct drm_i915_private *dev_priv = dev->dev_private;
15410         u32 val;
15411
15412         if (INTEL_INFO(dev)->num_pipes == 1)
15413                 return true;
15414
15415         val = I915_READ(DSPCNTR(!crtc->plane));
15416
15417         if ((val & DISPLAY_PLANE_ENABLE) &&
15418             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15419                 return false;
15420
15421         return true;
15422 }
15423
15424 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15425 {
15426         struct drm_device *dev = crtc->base.dev;
15427         struct intel_encoder *encoder;
15428
15429         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15430                 return true;
15431
15432         return false;
15433 }
15434
15435 static bool intel_encoder_has_connectors(struct intel_encoder *encoder)
15436 {
15437         struct drm_device *dev = encoder->base.dev;
15438         struct intel_connector *connector;
15439
15440         for_each_connector_on_encoder(dev, &encoder->base, connector)
15441                 return true;
15442
15443         return false;
15444 }
15445
15446 static void intel_sanitize_crtc(struct intel_crtc *crtc)
15447 {
15448         struct drm_device *dev = crtc->base.dev;
15449         struct drm_i915_private *dev_priv = dev->dev_private;
15450         i915_reg_t reg = PIPECONF(crtc->config->cpu_transcoder);
15451
15452         /* Clear any frame start delays used for debugging left by the BIOS */
15453         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15454
15455         /* restore vblank interrupts to correct state */
15456         drm_crtc_vblank_reset(&crtc->base);
15457         if (crtc->active) {
15458                 struct intel_plane *plane;
15459
15460                 drm_crtc_vblank_on(&crtc->base);
15461
15462                 /* Disable everything but the primary plane */
15463                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15464                         if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
15465                                 continue;
15466
15467                         plane->disable_plane(&plane->base, &crtc->base);
15468                 }
15469         }
15470
15471         /* We need to sanitize the plane -> pipe mapping first because this will
15472          * disable the crtc (and hence change the state) if it is wrong. Note
15473          * that gen4+ has a fixed plane -> pipe mapping.  */
15474         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
15475                 bool plane;
15476
15477                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15478                               crtc->base.base.id);
15479
15480                 /* Pipe has the wrong plane attached and the plane is active.
15481                  * Temporarily change the plane mapping and disable everything
15482                  * ...  */
15483                 plane = crtc->plane;
15484                 to_intel_plane_state(crtc->base.primary->state)->visible = true;
15485                 crtc->plane = !plane;
15486                 intel_crtc_disable_noatomic(&crtc->base);
15487                 crtc->plane = plane;
15488         }
15489
15490         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15491             crtc->pipe == PIPE_A && !crtc->active) {
15492                 /* BIOS forgot to enable pipe A, this mostly happens after
15493                  * resume. Force-enable the pipe to fix this, the update_dpms
15494                  * call below we restore the pipe to the right state, but leave
15495                  * the required bits on. */
15496                 intel_enable_pipe_a(dev);
15497         }
15498
15499         /* Adjust the state of the output pipe according to whether we
15500          * have active connectors/encoders. */
15501         if (!intel_crtc_has_encoders(crtc))
15502                 intel_crtc_disable_noatomic(&crtc->base);
15503
15504         if (crtc->active != crtc->base.state->active) {
15505                 struct intel_encoder *encoder;
15506
15507                 /* This can happen either due to bugs in the get_hw_state
15508                  * functions or because of calls to intel_crtc_disable_noatomic,
15509                  * or because the pipe is force-enabled due to the
15510                  * pipe A quirk. */
15511                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
15512                               crtc->base.base.id,
15513                               crtc->base.state->enable ? "enabled" : "disabled",
15514                               crtc->active ? "enabled" : "disabled");
15515
15516                 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0);
15517                 crtc->base.state->active = crtc->active;
15518                 crtc->base.enabled = crtc->active;
15519                 crtc->base.state->connector_mask = 0;
15520                 crtc->base.state->encoder_mask = 0;
15521
15522                 /* Because we only establish the connector -> encoder ->
15523                  * crtc links if something is active, this means the
15524                  * crtc is now deactivated. Break the links. connector
15525                  * -> encoder links are only establish when things are
15526                  *  actually up, hence no need to break them. */
15527                 WARN_ON(crtc->active);
15528
15529                 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15530                         encoder->base.crtc = NULL;
15531         }
15532
15533         if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
15534                 /*
15535                  * We start out with underrun reporting disabled to avoid races.
15536                  * For correct bookkeeping mark this on active crtcs.
15537                  *
15538                  * Also on gmch platforms we dont have any hardware bits to
15539                  * disable the underrun reporting. Which means we need to start
15540                  * out with underrun reporting disabled also on inactive pipes,
15541                  * since otherwise we'll complain about the garbage we read when
15542                  * e.g. coming up after runtime pm.
15543                  *
15544                  * No protection against concurrent access is required - at
15545                  * worst a fifo underrun happens which also sets this to false.
15546                  */
15547                 crtc->cpu_fifo_underrun_disabled = true;
15548                 crtc->pch_fifo_underrun_disabled = true;
15549         }
15550 }
15551
15552 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15553 {
15554         struct intel_connector *connector;
15555         struct drm_device *dev = encoder->base.dev;
15556
15557         /* We need to check both for a crtc link (meaning that the
15558          * encoder is active and trying to read from a pipe) and the
15559          * pipe itself being active. */
15560         bool has_active_crtc = encoder->base.crtc &&
15561                 to_intel_crtc(encoder->base.crtc)->active;
15562
15563         if (intel_encoder_has_connectors(encoder) && !has_active_crtc) {
15564                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15565                               encoder->base.base.id,
15566                               encoder->base.name);
15567
15568                 /* Connector is active, but has no active pipe. This is
15569                  * fallout from our resume register restoring. Disable
15570                  * the encoder manually again. */
15571                 if (encoder->base.crtc) {
15572                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15573                                       encoder->base.base.id,
15574                                       encoder->base.name);
15575                         encoder->disable(encoder);
15576                         if (encoder->post_disable)
15577                                 encoder->post_disable(encoder);
15578                 }
15579                 encoder->base.crtc = NULL;
15580
15581                 /* Inconsistent output/port/pipe state happens presumably due to
15582                  * a bug in one of the get_hw_state functions. Or someplace else
15583                  * in our code, like the register restore mess on resume. Clamp
15584                  * things to off as a safer default. */
15585                 for_each_intel_connector(dev, connector) {
15586                         if (connector->encoder != encoder)
15587                                 continue;
15588                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15589                         connector->base.encoder = NULL;
15590                 }
15591         }
15592         /* Enabled encoders without active connectors will be fixed in
15593          * the crtc fixup. */
15594 }
15595
15596 void i915_redisable_vga_power_on(struct drm_device *dev)
15597 {
15598         struct drm_i915_private *dev_priv = dev->dev_private;
15599         i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15600
15601         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15602                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15603                 i915_disable_vga(dev);
15604         }
15605 }
15606
15607 void i915_redisable_vga(struct drm_device *dev)
15608 {
15609         struct drm_i915_private *dev_priv = dev->dev_private;
15610
15611         /* This function can be called both from intel_modeset_setup_hw_state or
15612          * at a very early point in our resume sequence, where the power well
15613          * structures are not yet restored. Since this function is at a very
15614          * paranoid "someone might have enabled VGA while we were not looking"
15615          * level, just check if the power well is enabled instead of trying to
15616          * follow the "don't touch the power well if we don't need it" policy
15617          * the rest of the driver uses. */
15618         if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
15619                 return;
15620
15621         i915_redisable_vga_power_on(dev);
15622
15623         intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
15624 }
15625
15626 static bool primary_get_hw_state(struct intel_plane *plane)
15627 {
15628         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15629
15630         return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
15631 }
15632
15633 /* FIXME read out full plane state for all planes */
15634 static void readout_plane_state(struct intel_crtc *crtc)
15635 {
15636         struct drm_plane *primary = crtc->base.primary;
15637         struct intel_plane_state *plane_state =
15638                 to_intel_plane_state(primary->state);
15639
15640         plane_state->visible = crtc->active &&
15641                 primary_get_hw_state(to_intel_plane(primary));
15642
15643         if (plane_state->visible)
15644                 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
15645 }
15646
15647 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15648 {
15649         struct drm_i915_private *dev_priv = dev->dev_private;
15650         enum pipe pipe;
15651         struct intel_crtc *crtc;
15652         struct intel_encoder *encoder;
15653         struct intel_connector *connector;
15654         int i;
15655
15656         dev_priv->active_crtcs = 0;
15657
15658         for_each_intel_crtc(dev, crtc) {
15659                 struct intel_crtc_state *crtc_state = crtc->config;
15660                 int pixclk = 0;
15661
15662                 __drm_atomic_helper_crtc_destroy_state(&crtc->base, &crtc_state->base);
15663                 memset(crtc_state, 0, sizeof(*crtc_state));
15664                 crtc_state->base.crtc = &crtc->base;
15665
15666                 crtc_state->base.active = crtc_state->base.enable =
15667                         dev_priv->display.get_pipe_config(crtc, crtc_state);
15668
15669                 crtc->base.enabled = crtc_state->base.enable;
15670                 crtc->active = crtc_state->base.active;
15671
15672                 if (crtc_state->base.active) {
15673                         dev_priv->active_crtcs |= 1 << crtc->pipe;
15674
15675                         if (IS_BROADWELL(dev_priv)) {
15676                                 pixclk = ilk_pipe_pixel_rate(crtc_state);
15677
15678                                 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
15679                                 if (crtc_state->ips_enabled)
15680                                         pixclk = DIV_ROUND_UP(pixclk * 100, 95);
15681                         } else if (IS_VALLEYVIEW(dev_priv) ||
15682                                    IS_CHERRYVIEW(dev_priv) ||
15683                                    IS_BROXTON(dev_priv))
15684                                 pixclk = crtc_state->base.adjusted_mode.crtc_clock;
15685                         else
15686                                 WARN_ON(dev_priv->display.modeset_calc_cdclk);
15687                 }
15688
15689                 dev_priv->min_pixclk[crtc->pipe] = pixclk;
15690
15691                 readout_plane_state(crtc);
15692
15693                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15694                               crtc->base.base.id,
15695                               crtc->active ? "enabled" : "disabled");
15696         }
15697
15698         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15699                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15700
15701                 pll->on = pll->funcs.get_hw_state(dev_priv, pll,
15702                                                   &pll->config.hw_state);
15703                 pll->active = 0;
15704                 pll->config.crtc_mask = 0;
15705                 for_each_intel_crtc(dev, crtc) {
15706                         if (crtc->active && crtc->config->shared_dpll == pll) {
15707                                 pll->active++;
15708                                 pll->config.crtc_mask |= 1 << crtc->pipe;
15709                         }
15710                 }
15711
15712                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15713                               pll->name, pll->config.crtc_mask, pll->on);
15714
15715                 if (pll->config.crtc_mask)
15716                         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
15717         }
15718
15719         for_each_intel_encoder(dev, encoder) {
15720                 pipe = 0;
15721
15722                 if (encoder->get_hw_state(encoder, &pipe)) {
15723                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15724                         encoder->base.crtc = &crtc->base;
15725                         encoder->get_config(encoder, crtc->config);
15726                 } else {
15727                         encoder->base.crtc = NULL;
15728                 }
15729
15730                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15731                               encoder->base.base.id,
15732                               encoder->base.name,
15733                               encoder->base.crtc ? "enabled" : "disabled",
15734                               pipe_name(pipe));
15735         }
15736
15737         for_each_intel_connector(dev, connector) {
15738                 if (connector->get_hw_state(connector)) {
15739                         connector->base.dpms = DRM_MODE_DPMS_ON;
15740
15741                         encoder = connector->encoder;
15742                         connector->base.encoder = &encoder->base;
15743
15744                         if (encoder->base.crtc &&
15745                             encoder->base.crtc->state->active) {
15746                                 /*
15747                                  * This has to be done during hardware readout
15748                                  * because anything calling .crtc_disable may
15749                                  * rely on the connector_mask being accurate.
15750                                  */
15751                                 encoder->base.crtc->state->connector_mask |=
15752                                         1 << drm_connector_index(&connector->base);
15753                                 encoder->base.crtc->state->encoder_mask |=
15754                                         1 << drm_encoder_index(&encoder->base);
15755                         }
15756
15757                 } else {
15758                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15759                         connector->base.encoder = NULL;
15760                 }
15761                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15762                               connector->base.base.id,
15763                               connector->base.name,
15764                               connector->base.encoder ? "enabled" : "disabled");
15765         }
15766
15767         for_each_intel_crtc(dev, crtc) {
15768                 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15769
15770                 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15771                 if (crtc->base.state->active) {
15772                         intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15773                         intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15774                         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15775
15776                         /*
15777                          * The initial mode needs to be set in order to keep
15778                          * the atomic core happy. It wants a valid mode if the
15779                          * crtc's enabled, so we do the above call.
15780                          *
15781                          * At this point some state updated by the connectors
15782                          * in their ->detect() callback has not run yet, so
15783                          * no recalculation can be done yet.
15784                          *
15785                          * Even if we could do a recalculation and modeset
15786                          * right now it would cause a double modeset if
15787                          * fbdev or userspace chooses a different initial mode.
15788                          *
15789                          * If that happens, someone indicated they wanted a
15790                          * mode change, which means it's safe to do a full
15791                          * recalculation.
15792                          */
15793                         crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
15794
15795                         drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
15796                         update_scanline_offset(crtc);
15797                 }
15798
15799                 intel_pipe_config_sanity_check(dev_priv, crtc->config);
15800         }
15801 }
15802
15803 /* Scan out the current hw modeset state,
15804  * and sanitizes it to the current state
15805  */
15806 static void
15807 intel_modeset_setup_hw_state(struct drm_device *dev)
15808 {
15809         struct drm_i915_private *dev_priv = dev->dev_private;
15810         enum pipe pipe;
15811         struct intel_crtc *crtc;
15812         struct intel_encoder *encoder;
15813         int i;
15814
15815         intel_modeset_readout_hw_state(dev);
15816
15817         /* HW state is read out, now we need to sanitize this mess. */
15818         for_each_intel_encoder(dev, encoder) {
15819                 intel_sanitize_encoder(encoder);
15820         }
15821
15822         for_each_pipe(dev_priv, pipe) {
15823                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15824                 intel_sanitize_crtc(crtc);
15825                 intel_dump_pipe_config(crtc, crtc->config,
15826                                        "[setup_hw_state]");
15827         }
15828
15829         intel_modeset_update_connector_atomic_state(dev);
15830
15831         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15832                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15833
15834                 if (!pll->on || pll->active)
15835                         continue;
15836
15837                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15838
15839                 pll->funcs.disable(dev_priv, pll);
15840                 pll->on = false;
15841         }
15842
15843         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
15844                 vlv_wm_get_hw_state(dev);
15845         else if (IS_GEN9(dev))
15846                 skl_wm_get_hw_state(dev);
15847         else if (HAS_PCH_SPLIT(dev))
15848                 ilk_wm_get_hw_state(dev);
15849
15850         for_each_intel_crtc(dev, crtc) {
15851                 unsigned long put_domains;
15852
15853                 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
15854                 if (WARN_ON(put_domains))
15855                         modeset_put_power_domains(dev_priv, put_domains);
15856         }
15857         intel_display_set_init_power(dev_priv, false);
15858
15859         intel_fbc_init_pipe_state(dev_priv);
15860 }
15861
15862 void intel_display_resume(struct drm_device *dev)
15863 {
15864         struct drm_i915_private *dev_priv = to_i915(dev);
15865         struct drm_atomic_state *state = dev_priv->modeset_restore_state;
15866         struct drm_modeset_acquire_ctx ctx;
15867         int ret;
15868         bool setup = false;
15869
15870         dev_priv->modeset_restore_state = NULL;
15871
15872         /*
15873          * This is a cludge because with real atomic modeset mode_config.mutex
15874          * won't be taken. Unfortunately some probed state like
15875          * audio_codec_enable is still protected by mode_config.mutex, so lock
15876          * it here for now.
15877          */
15878         mutex_lock(&dev->mode_config.mutex);
15879         drm_modeset_acquire_init(&ctx, 0);
15880
15881 retry:
15882         ret = drm_modeset_lock_all_ctx(dev, &ctx);
15883
15884         if (ret == 0 && !setup) {
15885                 setup = true;
15886
15887                 intel_modeset_setup_hw_state(dev);
15888                 i915_redisable_vga(dev);
15889         }
15890
15891         if (ret == 0 && state) {
15892                 struct drm_crtc_state *crtc_state;
15893                 struct drm_crtc *crtc;
15894                 int i;
15895
15896                 state->acquire_ctx = &ctx;
15897
15898                 for_each_crtc_in_state(state, crtc, crtc_state, i) {
15899                         /*
15900                          * Force recalculation even if we restore
15901                          * current state. With fast modeset this may not result
15902                          * in a modeset when the state is compatible.
15903                          */
15904                         crtc_state->mode_changed = true;
15905                 }
15906
15907                 ret = drm_atomic_commit(state);
15908         }
15909
15910         if (ret == -EDEADLK) {
15911                 drm_modeset_backoff(&ctx);
15912                 goto retry;
15913         }
15914
15915         drm_modeset_drop_locks(&ctx);
15916         drm_modeset_acquire_fini(&ctx);
15917         mutex_unlock(&dev->mode_config.mutex);
15918
15919         if (ret) {
15920                 DRM_ERROR("Restoring old state failed with %i\n", ret);
15921                 drm_atomic_state_free(state);
15922         }
15923 }
15924
15925 void intel_modeset_gem_init(struct drm_device *dev)
15926 {
15927         struct drm_crtc *c;
15928         struct drm_i915_gem_object *obj;
15929         int ret;
15930
15931         intel_init_gt_powersave(dev);
15932
15933         intel_modeset_init_hw(dev);
15934
15935         intel_setup_overlay(dev);
15936
15937         /*
15938          * Make sure any fbs we allocated at startup are properly
15939          * pinned & fenced.  When we do the allocation it's too early
15940          * for this.
15941          */
15942         for_each_crtc(dev, c) {
15943                 obj = intel_fb_obj(c->primary->fb);
15944                 if (obj == NULL)
15945                         continue;
15946
15947                 mutex_lock(&dev->struct_mutex);
15948                 ret = intel_pin_and_fence_fb_obj(c->primary->fb,
15949                                                  c->primary->state->rotation);
15950                 mutex_unlock(&dev->struct_mutex);
15951                 if (ret) {
15952                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
15953                                   to_intel_crtc(c)->pipe);
15954                         drm_framebuffer_unreference(c->primary->fb);
15955                         c->primary->fb = NULL;
15956                         c->primary->crtc = c->primary->state->crtc = NULL;
15957                         update_state_fb(c->primary);
15958                         c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
15959                 }
15960         }
15961
15962         intel_backlight_register(dev);
15963 }
15964
15965 void intel_connector_unregister(struct intel_connector *intel_connector)
15966 {
15967         struct drm_connector *connector = &intel_connector->base;
15968
15969         intel_panel_destroy_backlight(connector);
15970         drm_connector_unregister(connector);
15971 }
15972
15973 void intel_modeset_cleanup(struct drm_device *dev)
15974 {
15975         struct drm_i915_private *dev_priv = dev->dev_private;
15976         struct intel_connector *connector;
15977
15978         intel_disable_gt_powersave(dev);
15979
15980         intel_backlight_unregister(dev);
15981
15982         /*
15983          * Interrupts and polling as the first thing to avoid creating havoc.
15984          * Too much stuff here (turning of connectors, ...) would
15985          * experience fancy races otherwise.
15986          */
15987         intel_irq_uninstall(dev_priv);
15988
15989         /*
15990          * Due to the hpd irq storm handling the hotplug work can re-arm the
15991          * poll handlers. Hence disable polling after hpd handling is shut down.
15992          */
15993         drm_kms_helper_poll_fini(dev);
15994
15995         intel_unregister_dsm_handler();
15996
15997         intel_fbc_global_disable(dev_priv);
15998
15999         /* flush any delayed tasks or pending work */
16000         flush_scheduled_work();
16001
16002         /* destroy the backlight and sysfs files before encoders/connectors */
16003         for_each_intel_connector(dev, connector)
16004                 connector->unregister(connector);
16005
16006         drm_mode_config_cleanup(dev);
16007
16008         intel_cleanup_overlay(dev);
16009
16010         intel_cleanup_gt_powersave(dev);
16011
16012         intel_teardown_gmbus(dev);
16013 }
16014
16015 /*
16016  * Return which encoder is currently attached for connector.
16017  */
16018 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
16019 {
16020         return &intel_attached_encoder(connector)->base;
16021 }
16022
16023 void intel_connector_attach_encoder(struct intel_connector *connector,
16024                                     struct intel_encoder *encoder)
16025 {
16026         connector->encoder = encoder;
16027         drm_mode_connector_attach_encoder(&connector->base,
16028                                           &encoder->base);
16029 }
16030
16031 /*
16032  * set vga decode state - true == enable VGA decode
16033  */
16034 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
16035 {
16036         struct drm_i915_private *dev_priv = dev->dev_private;
16037         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
16038         u16 gmch_ctrl;
16039
16040         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
16041                 DRM_ERROR("failed to read control word\n");
16042                 return -EIO;
16043         }
16044
16045         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
16046                 return 0;
16047
16048         if (state)
16049                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
16050         else
16051                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
16052
16053         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
16054                 DRM_ERROR("failed to write control word\n");
16055                 return -EIO;
16056         }
16057
16058         return 0;
16059 }
16060
16061 struct intel_display_error_state {
16062
16063         u32 power_well_driver;
16064
16065         int num_transcoders;
16066
16067         struct intel_cursor_error_state {
16068                 u32 control;
16069                 u32 position;
16070                 u32 base;
16071                 u32 size;
16072         } cursor[I915_MAX_PIPES];
16073
16074         struct intel_pipe_error_state {
16075                 bool power_domain_on;
16076                 u32 source;
16077                 u32 stat;
16078         } pipe[I915_MAX_PIPES];
16079
16080         struct intel_plane_error_state {
16081                 u32 control;
16082                 u32 stride;
16083                 u32 size;
16084                 u32 pos;
16085                 u32 addr;
16086                 u32 surface;
16087                 u32 tile_offset;
16088         } plane[I915_MAX_PIPES];
16089
16090         struct intel_transcoder_error_state {
16091                 bool power_domain_on;
16092                 enum transcoder cpu_transcoder;
16093
16094                 u32 conf;
16095
16096                 u32 htotal;
16097                 u32 hblank;
16098                 u32 hsync;
16099                 u32 vtotal;
16100                 u32 vblank;
16101                 u32 vsync;
16102         } transcoder[4];
16103 };
16104
16105 struct intel_display_error_state *
16106 intel_display_capture_error_state(struct drm_device *dev)
16107 {
16108         struct drm_i915_private *dev_priv = dev->dev_private;
16109         struct intel_display_error_state *error;
16110         int transcoders[] = {
16111                 TRANSCODER_A,
16112                 TRANSCODER_B,
16113                 TRANSCODER_C,
16114                 TRANSCODER_EDP,
16115         };
16116         int i;
16117
16118         if (INTEL_INFO(dev)->num_pipes == 0)
16119                 return NULL;
16120
16121         error = kzalloc(sizeof(*error), GFP_ATOMIC);
16122         if (error == NULL)
16123                 return NULL;
16124
16125         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
16126                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
16127
16128         for_each_pipe(dev_priv, i) {
16129                 error->pipe[i].power_domain_on =
16130                         __intel_display_power_is_enabled(dev_priv,
16131                                                          POWER_DOMAIN_PIPE(i));
16132                 if (!error->pipe[i].power_domain_on)
16133                         continue;
16134
16135                 error->cursor[i].control = I915_READ(CURCNTR(i));
16136                 error->cursor[i].position = I915_READ(CURPOS(i));
16137                 error->cursor[i].base = I915_READ(CURBASE(i));
16138
16139                 error->plane[i].control = I915_READ(DSPCNTR(i));
16140                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
16141                 if (INTEL_INFO(dev)->gen <= 3) {
16142                         error->plane[i].size = I915_READ(DSPSIZE(i));
16143                         error->plane[i].pos = I915_READ(DSPPOS(i));
16144                 }
16145                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
16146                         error->plane[i].addr = I915_READ(DSPADDR(i));
16147                 if (INTEL_INFO(dev)->gen >= 4) {
16148                         error->plane[i].surface = I915_READ(DSPSURF(i));
16149                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
16150                 }
16151
16152                 error->pipe[i].source = I915_READ(PIPESRC(i));
16153
16154                 if (HAS_GMCH_DISPLAY(dev))
16155                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
16156         }
16157
16158         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
16159         if (HAS_DDI(dev_priv->dev))
16160                 error->num_transcoders++; /* Account for eDP. */
16161
16162         for (i = 0; i < error->num_transcoders; i++) {
16163                 enum transcoder cpu_transcoder = transcoders[i];
16164
16165                 error->transcoder[i].power_domain_on =
16166                         __intel_display_power_is_enabled(dev_priv,
16167                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
16168                 if (!error->transcoder[i].power_domain_on)
16169                         continue;
16170
16171                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
16172
16173                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
16174                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
16175                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
16176                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
16177                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
16178                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
16179                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
16180         }
16181
16182         return error;
16183 }
16184
16185 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
16186
16187 void
16188 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
16189                                 struct drm_device *dev,
16190                                 struct intel_display_error_state *error)
16191 {
16192         struct drm_i915_private *dev_priv = dev->dev_private;
16193         int i;
16194
16195         if (!error)
16196                 return;
16197
16198         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
16199         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
16200                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
16201                            error->power_well_driver);
16202         for_each_pipe(dev_priv, i) {
16203                 err_printf(m, "Pipe [%d]:\n", i);
16204                 err_printf(m, "  Power: %s\n",
16205                            onoff(error->pipe[i].power_domain_on));
16206                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
16207                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
16208
16209                 err_printf(m, "Plane [%d]:\n", i);
16210                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
16211                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
16212                 if (INTEL_INFO(dev)->gen <= 3) {
16213                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
16214                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
16215                 }
16216                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
16217                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
16218                 if (INTEL_INFO(dev)->gen >= 4) {
16219                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
16220                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
16221                 }
16222
16223                 err_printf(m, "Cursor [%d]:\n", i);
16224                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
16225                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
16226                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
16227         }
16228
16229         for (i = 0; i < error->num_transcoders; i++) {
16230                 err_printf(m, "CPU transcoder: %c\n",
16231                            transcoder_name(error->transcoder[i].cpu_transcoder));
16232                 err_printf(m, "  Power: %s\n",
16233                            onoff(error->transcoder[i].power_domain_on));
16234                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
16235                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
16236                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
16237                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
16238                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
16239                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
16240                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
16241         }
16242 }