drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/module.h>
  28 #include <linux/input.h>
  29 #include <linux/i2c.h>
  30 #include <linux/kernel.h>
  31 #include <linux/slab.h>
  32 #include <linux/vgaarb.h>
  33 #include "drmP.h"
  34 #include "intel_drv.h"
  35 #include "i915_drm.h"
  36 #include "i915_drv.h"
  37 #include "i915_trace.h"
  38 #include "drm_dp_helper.h"
  39
  40 #include "drm_crtc_helper.h"
  41
  42 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  43
  44 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
  45 static void intel_update_watermarks(struct drm_device *dev);
  46 static void intel_increase_pllclock(struct drm_crtc *crtc);
  47 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  48
  49 typedef struct {
  50     /* given values */
  51     int n;
  52     int m1, m2;
  53     int p1, p2;
  54     /* derived values */
  55     int dot;
  56     int vco;
  57     int m;
  58     int p;
  59 } intel_clock_t;
  60
  61 typedef struct {
  62     int min, max;
  63 } intel_range_t;
  64
  65 typedef struct {
  66     int dot_limit;
  67     int p2_slow, p2_fast;
  68 } intel_p2_t;
  69
  70 #define INTEL_P2_NUM                  2
  71 typedef struct intel_limit intel_limit_t;
  72 struct intel_limit {
  73     intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  74     intel_p2_t      p2;
  75     bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  76                       int, int, intel_clock_t *);
  77 };
  78
  79 #define I8XX_DOT_MIN              25000
  80 #define I8XX_DOT_MAX             350000
  81 #define I8XX_VCO_MIN             930000
  82 #define I8XX_VCO_MAX            1400000
  83 #define I8XX_N_MIN                    3
  84 #define I8XX_N_MAX                   16
  85 #define I8XX_M_MIN                   96
  86 #define I8XX_M_MAX                  140
  87 #define I8XX_M1_MIN                  18
  88 #define I8XX_M1_MAX                  26
  89 #define I8XX_M2_MIN                   6
  90 #define I8XX_M2_MAX                  16
  91 #define I8XX_P_MIN                    4
  92 #define I8XX_P_MAX                  128
  93 #define I8XX_P1_MIN                   2
  94 #define I8XX_P1_MAX                  33
  95 #define I8XX_P1_LVDS_MIN              1
  96 #define I8XX_P1_LVDS_MAX              6
  97 #define I8XX_P2_SLOW                  4
  98 #define I8XX_P2_FAST                  2
  99 #define I8XX_P2_LVDS_SLOW             14
 100 #define I8XX_P2_LVDS_FAST             7
 101 #define I8XX_P2_SLOW_LIMIT       165000
 102
 103 #define I9XX_DOT_MIN              20000
 104 #define I9XX_DOT_MAX             400000
 105 #define I9XX_VCO_MIN            1400000
 106 #define I9XX_VCO_MAX            2800000
 107 #define PINEVIEW_VCO_MIN                1700000
 108 #define PINEVIEW_VCO_MAX                3500000
 109 #define I9XX_N_MIN                    1
 110 #define I9XX_N_MAX                    6
 111 /* Pineview's Ncounter is a ring counter */
 112 #define PINEVIEW_N_MIN                3
 113 #define PINEVIEW_N_MAX                6
 114 #define I9XX_M_MIN                   70
 115 #define I9XX_M_MAX                  120
 116 #define PINEVIEW_M_MIN                2
 117 #define PINEVIEW_M_MAX              256
 118 #define I9XX_M1_MIN                  10
 119 #define I9XX_M1_MAX                  22
 120 #define I9XX_M2_MIN                   5
 121 #define I9XX_M2_MAX                   9
 122 /* Pineview M1 is reserved, and must be 0 */
 123 #define PINEVIEW_M1_MIN               0
 124 #define PINEVIEW_M1_MAX               0
 125 #define PINEVIEW_M2_MIN               0
 126 #define PINEVIEW_M2_MAX               254
 127 #define I9XX_P_SDVO_DAC_MIN           5
 128 #define I9XX_P_SDVO_DAC_MAX          80
 129 #define I9XX_P_LVDS_MIN               7
 130 #define I9XX_P_LVDS_MAX              98
 131 #define PINEVIEW_P_LVDS_MIN                   7
 132 #define PINEVIEW_P_LVDS_MAX                  112
 133 #define I9XX_P1_MIN                   1
 134 #define I9XX_P1_MAX                   8
 135 #define I9XX_P2_SDVO_DAC_SLOW                10
 136 #define I9XX_P2_SDVO_DAC_FAST                 5
 137 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT      200000
 138 #define I9XX_P2_LVDS_SLOW                    14
 139 #define I9XX_P2_LVDS_FAST                     7
 140 #define I9XX_P2_LVDS_SLOW_LIMIT          112000
 141
 142 /*The parameter is for SDVO on G4x platform*/
 143 #define G4X_DOT_SDVO_MIN           25000
 144 #define G4X_DOT_SDVO_MAX           270000
 145 #define G4X_VCO_MIN                1750000
 146 #define G4X_VCO_MAX                3500000
 147 #define G4X_N_SDVO_MIN             1
 148 #define G4X_N_SDVO_MAX             4
 149 #define G4X_M_SDVO_MIN             104
 150 #define G4X_M_SDVO_MAX             138
 151 #define G4X_M1_SDVO_MIN            17
 152 #define G4X_M1_SDVO_MAX            23
 153 #define G4X_M2_SDVO_MIN            5
 154 #define G4X_M2_SDVO_MAX            11
 155 #define G4X_P_SDVO_MIN             10
 156 #define G4X_P_SDVO_MAX             30
 157 #define G4X_P1_SDVO_MIN            1
 158 #define G4X_P1_SDVO_MAX            3
 159 #define G4X_P2_SDVO_SLOW           10
 160 #define G4X_P2_SDVO_FAST           10
 161 #define G4X_P2_SDVO_LIMIT          270000
 162
 163 /*The parameter is for HDMI_DAC on G4x platform*/
 164 #define G4X_DOT_HDMI_DAC_MIN           22000
 165 #define G4X_DOT_HDMI_DAC_MAX           400000
 166 #define G4X_N_HDMI_DAC_MIN             1
 167 #define G4X_N_HDMI_DAC_MAX             4
 168 #define G4X_M_HDMI_DAC_MIN             104
 169 #define G4X_M_HDMI_DAC_MAX             138
 170 #define G4X_M1_HDMI_DAC_MIN            16
 171 #define G4X_M1_HDMI_DAC_MAX            23
 172 #define G4X_M2_HDMI_DAC_MIN            5
 173 #define G4X_M2_HDMI_DAC_MAX            11
 174 #define G4X_P_HDMI_DAC_MIN             5
 175 #define G4X_P_HDMI_DAC_MAX             80
 176 #define G4X_P1_HDMI_DAC_MIN            1
 177 #define G4X_P1_HDMI_DAC_MAX            8
 178 #define G4X_P2_HDMI_DAC_SLOW           10
 179 #define G4X_P2_HDMI_DAC_FAST           5
 180 #define G4X_P2_HDMI_DAC_LIMIT          165000
 181
 182 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
 183 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN           20000
 184 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX           115000
 185 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN             1
 186 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX             3
 187 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN             104
 188 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX             138
 189 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN            17
 190 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX            23
 191 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN            5
 192 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX            11
 193 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN             28
 194 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX             112
 195 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN            2
 196 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX            8
 197 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW           14
 198 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST           14
 199 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT          0
 200
 201 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
 202 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN           80000
 203 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX           224000
 204 #define G4X_N_DUAL_CHANNEL_LVDS_MIN             1
 205 #define G4X_N_DUAL_CHANNEL_LVDS_MAX             3
 206 #define G4X_M_DUAL_CHANNEL_LVDS_MIN             104
 207 #define G4X_M_DUAL_CHANNEL_LVDS_MAX             138
 208 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN            17
 209 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX            23
 210 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN            5
 211 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX            11
 212 #define G4X_P_DUAL_CHANNEL_LVDS_MIN             14
 213 #define G4X_P_DUAL_CHANNEL_LVDS_MAX             42
 214 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN            2
 215 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX            6
 216 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW           7
 217 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST           7
 218 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT          0
 219
 220 /*The parameter is for DISPLAY PORT on G4x platform*/
 221 #define G4X_DOT_DISPLAY_PORT_MIN           161670
 222 #define G4X_DOT_DISPLAY_PORT_MAX           227000
 223 #define G4X_N_DISPLAY_PORT_MIN             1
 224 #define G4X_N_DISPLAY_PORT_MAX             2
 225 #define G4X_M_DISPLAY_PORT_MIN             97
 226 #define G4X_M_DISPLAY_PORT_MAX             108
 227 #define G4X_M1_DISPLAY_PORT_MIN            0x10
 228 #define G4X_M1_DISPLAY_PORT_MAX            0x12
 229 #define G4X_M2_DISPLAY_PORT_MIN            0x05
 230 #define G4X_M2_DISPLAY_PORT_MAX            0x06
 231 #define G4X_P_DISPLAY_PORT_MIN             10
 232 #define G4X_P_DISPLAY_PORT_MAX             20
 233 #define G4X_P1_DISPLAY_PORT_MIN            1
 234 #define G4X_P1_DISPLAY_PORT_MAX            2
 235 #define G4X_P2_DISPLAY_PORT_SLOW           10
 236 #define G4X_P2_DISPLAY_PORT_FAST           10
 237 #define G4X_P2_DISPLAY_PORT_LIMIT          0
 238
 239 /* Ironlake / Sandybridge */
 240 /* as we calculate clock using (register_value + 2) for
 241    N/M1/M2, so here the range value for them is (actual_value-2).
 242  */
 243 #define IRONLAKE_DOT_MIN         25000
 244 #define IRONLAKE_DOT_MAX         350000
 245 #define IRONLAKE_VCO_MIN         1760000
 246 #define IRONLAKE_VCO_MAX         3510000
 247 #define IRONLAKE_M1_MIN          12
 248 #define IRONLAKE_M1_MAX          22
 249 #define IRONLAKE_M2_MIN          5
 250 #define IRONLAKE_M2_MAX          9
 251 #define IRONLAKE_P2_DOT_LIMIT    225000 /* 225Mhz */
 252
 253 /* We have parameter ranges for different type of outputs. */
 254
 255 /* DAC & HDMI Refclk 120Mhz */
 256 #define IRONLAKE_DAC_N_MIN      1
 257 #define IRONLAKE_DAC_N_MAX      5
 258 #define IRONLAKE_DAC_M_MIN      79
 259 #define IRONLAKE_DAC_M_MAX      127
 260 #define IRONLAKE_DAC_P_MIN      5
 261 #define IRONLAKE_DAC_P_MAX      80
 262 #define IRONLAKE_DAC_P1_MIN     1
 263 #define IRONLAKE_DAC_P1_MAX     8
 264 #define IRONLAKE_DAC_P2_SLOW    10
 265 #define IRONLAKE_DAC_P2_FAST    5
 266
 267 /* LVDS single-channel 120Mhz refclk */
 268 #define IRONLAKE_LVDS_S_N_MIN   1
 269 #define IRONLAKE_LVDS_S_N_MAX   3
 270 #define IRONLAKE_LVDS_S_M_MIN   79
 271 #define IRONLAKE_LVDS_S_M_MAX   118
 272 #define IRONLAKE_LVDS_S_P_MIN   28
 273 #define IRONLAKE_LVDS_S_P_MAX   112
 274 #define IRONLAKE_LVDS_S_P1_MIN  2
 275 #define IRONLAKE_LVDS_S_P1_MAX  8
 276 #define IRONLAKE_LVDS_S_P2_SLOW 14
 277 #define IRONLAKE_LVDS_S_P2_FAST 14
 278
 279 /* LVDS dual-channel 120Mhz refclk */
 280 #define IRONLAKE_LVDS_D_N_MIN   1
 281 #define IRONLAKE_LVDS_D_N_MAX   3
 282 #define IRONLAKE_LVDS_D_M_MIN   79
 283 #define IRONLAKE_LVDS_D_M_MAX   127
 284 #define IRONLAKE_LVDS_D_P_MIN   14
 285 #define IRONLAKE_LVDS_D_P_MAX   56
 286 #define IRONLAKE_LVDS_D_P1_MIN  2
 287 #define IRONLAKE_LVDS_D_P1_MAX  8
 288 #define IRONLAKE_LVDS_D_P2_SLOW 7
 289 #define IRONLAKE_LVDS_D_P2_FAST 7
 290
 291 /* LVDS single-channel 100Mhz refclk */
 292 #define IRONLAKE_LVDS_S_SSC_N_MIN       1
 293 #define IRONLAKE_LVDS_S_SSC_N_MAX       2
 294 #define IRONLAKE_LVDS_S_SSC_M_MIN       79
 295 #define IRONLAKE_LVDS_S_SSC_M_MAX       126
 296 #define IRONLAKE_LVDS_S_SSC_P_MIN       28
 297 #define IRONLAKE_LVDS_S_SSC_P_MAX       112
 298 #define IRONLAKE_LVDS_S_SSC_P1_MIN      2
 299 #define IRONLAKE_LVDS_S_SSC_P1_MAX      8
 300 #define IRONLAKE_LVDS_S_SSC_P2_SLOW     14
 301 #define IRONLAKE_LVDS_S_SSC_P2_FAST     14
 302
 303 /* LVDS dual-channel 100Mhz refclk */
 304 #define IRONLAKE_LVDS_D_SSC_N_MIN       1
 305 #define IRONLAKE_LVDS_D_SSC_N_MAX       3
 306 #define IRONLAKE_LVDS_D_SSC_M_MIN       79
 307 #define IRONLAKE_LVDS_D_SSC_M_MAX       126
 308 #define IRONLAKE_LVDS_D_SSC_P_MIN       14
 309 #define IRONLAKE_LVDS_D_SSC_P_MAX       42
 310 #define IRONLAKE_LVDS_D_SSC_P1_MIN      2
 311 #define IRONLAKE_LVDS_D_SSC_P1_MAX      6
 312 #define IRONLAKE_LVDS_D_SSC_P2_SLOW     7
 313 #define IRONLAKE_LVDS_D_SSC_P2_FAST     7
 314
 315 /* DisplayPort */
 316 #define IRONLAKE_DP_N_MIN               1
 317 #define IRONLAKE_DP_N_MAX               2
 318 #define IRONLAKE_DP_M_MIN               81
 319 #define IRONLAKE_DP_M_MAX               90
 320 #define IRONLAKE_DP_P_MIN               10
 321 #define IRONLAKE_DP_P_MAX               20
 322 #define IRONLAKE_DP_P2_FAST             10
 323 #define IRONLAKE_DP_P2_SLOW             10
 324 #define IRONLAKE_DP_P2_LIMIT            0
 325 #define IRONLAKE_DP_P1_MIN              1
 326 #define IRONLAKE_DP_P1_MAX              2
 327
 328 /* FDI */
 329 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
 330
 331 static bool
 332 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 333                     int target, int refclk, intel_clock_t *best_clock);
 334 static bool
 335 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 336                         int target, int refclk, intel_clock_t *best_clock);
 337
 338 static bool
 339 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 340                       int target, int refclk, intel_clock_t *best_clock);
 341 static bool
 342 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
 343                            int target, int refclk, intel_clock_t *best_clock);
 344
 345 static inline u32 /* units of 100MHz */
 346 intel_fdi_link_freq(struct drm_device *dev)
 347 {
 348         struct drm_i915_private *dev_priv = dev->dev_private;
 349         return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 350 }
 351
 352 static const intel_limit_t intel_limits_i8xx_dvo = {
 353         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 354         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 355         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 356         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 357         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 358         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 359         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 360         .p1  = { .min = I8XX_P1_MIN,            .max = I8XX_P1_MAX },
 361         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 362                  .p2_slow = I8XX_P2_SLOW,       .p2_fast = I8XX_P2_FAST },
 363         .find_pll = intel_find_best_PLL,
 364 };
 365
 366 static const intel_limit_t intel_limits_i8xx_lvds = {
 367         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 368         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 369         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 370         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 371         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 372         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 373         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 374         .p1  = { .min = I8XX_P1_LVDS_MIN,       .max = I8XX_P1_LVDS_MAX },
 375         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 376                  .p2_slow = I8XX_P2_LVDS_SLOW,  .p2_fast = I8XX_P2_LVDS_FAST },
 377         .find_pll = intel_find_best_PLL,
 378 };
 379
 380 static const intel_limit_t intel_limits_i9xx_sdvo = {
 381         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 382         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 383         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 384         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 385         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 386         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 387         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 388         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 389         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 390                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 391         .find_pll = intel_find_best_PLL,
 392 };
 393
 394 static const intel_limit_t intel_limits_i9xx_lvds = {
 395         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 396         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 397         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 398         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 399         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 400         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 401         .p   = { .min = I9XX_P_LVDS_MIN,        .max = I9XX_P_LVDS_MAX },
 402         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 403         /* The single-channel range is 25-112Mhz, and dual-channel
 404          * is 80-224Mhz.  Prefer single channel as much as possible.
 405          */
 406         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 407                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_FAST },
 408         .find_pll = intel_find_best_PLL,
 409 };
 410
 411     /* below parameter and function is for G4X Chipset Family*/
 412 static const intel_limit_t intel_limits_g4x_sdvo = {
 413         .dot = { .min = G4X_DOT_SDVO_MIN,       .max = G4X_DOT_SDVO_MAX },
 414         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 415         .n   = { .min = G4X_N_SDVO_MIN,         .max = G4X_N_SDVO_MAX },
 416         .m   = { .min = G4X_M_SDVO_MIN,         .max = G4X_M_SDVO_MAX },
 417         .m1  = { .min = G4X_M1_SDVO_MIN,        .max = G4X_M1_SDVO_MAX },
 418         .m2  = { .min = G4X_M2_SDVO_MIN,        .max = G4X_M2_SDVO_MAX },
 419         .p   = { .min = G4X_P_SDVO_MIN,         .max = G4X_P_SDVO_MAX },
 420         .p1  = { .min = G4X_P1_SDVO_MIN,        .max = G4X_P1_SDVO_MAX},
 421         .p2  = { .dot_limit = G4X_P2_SDVO_LIMIT,
 422                  .p2_slow = G4X_P2_SDVO_SLOW,
 423                  .p2_fast = G4X_P2_SDVO_FAST
 424         },
 425         .find_pll = intel_g4x_find_best_PLL,
 426 };
 427
 428 static const intel_limit_t intel_limits_g4x_hdmi = {
 429         .dot = { .min = G4X_DOT_HDMI_DAC_MIN,   .max = G4X_DOT_HDMI_DAC_MAX },
 430         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 431         .n   = { .min = G4X_N_HDMI_DAC_MIN,     .max = G4X_N_HDMI_DAC_MAX },
 432         .m   = { .min = G4X_M_HDMI_DAC_MIN,     .max = G4X_M_HDMI_DAC_MAX },
 433         .m1  = { .min = G4X_M1_HDMI_DAC_MIN,    .max = G4X_M1_HDMI_DAC_MAX },
 434         .m2  = { .min = G4X_M2_HDMI_DAC_MIN,    .max = G4X_M2_HDMI_DAC_MAX },
 435         .p   = { .min = G4X_P_HDMI_DAC_MIN,     .max = G4X_P_HDMI_DAC_MAX },
 436         .p1  = { .min = G4X_P1_HDMI_DAC_MIN,    .max = G4X_P1_HDMI_DAC_MAX},
 437         .p2  = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
 438                  .p2_slow = G4X_P2_HDMI_DAC_SLOW,
 439                  .p2_fast = G4X_P2_HDMI_DAC_FAST
 440         },
 441         .find_pll = intel_g4x_find_best_PLL,
 442 };
 443
 444 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 445         .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
 446                  .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
 447         .vco = { .min = G4X_VCO_MIN,
 448                  .max = G4X_VCO_MAX },
 449         .n   = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
 450                  .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
 451         .m   = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
 452                  .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
 453         .m1  = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
 454                  .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
 455         .m2  = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
 456                  .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
 457         .p   = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
 458                  .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
 459         .p1  = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
 460                  .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
 461         .p2  = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
 462                  .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
 463                  .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
 464         },
 465         .find_pll = intel_g4x_find_best_PLL,
 466 };
 467
 468 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 469         .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
 470                  .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
 471         .vco = { .min = G4X_VCO_MIN,
 472                  .max = G4X_VCO_MAX },
 473         .n   = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
 474                  .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
 475         .m   = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
 476                  .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
 477         .m1  = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
 478                  .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
 479         .m2  = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
 480                  .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
 481         .p   = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
 482                  .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
 483         .p1  = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
 484                  .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
 485         .p2  = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
 486                  .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
 487                  .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
 488         },
 489         .find_pll = intel_g4x_find_best_PLL,
 490 };
 491
 492 static const intel_limit_t intel_limits_g4x_display_port = {
 493         .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
 494                  .max = G4X_DOT_DISPLAY_PORT_MAX },
 495         .vco = { .min = G4X_VCO_MIN,
 496                  .max = G4X_VCO_MAX},
 497         .n   = { .min = G4X_N_DISPLAY_PORT_MIN,
 498                  .max = G4X_N_DISPLAY_PORT_MAX },
 499         .m   = { .min = G4X_M_DISPLAY_PORT_MIN,
 500                  .max = G4X_M_DISPLAY_PORT_MAX },
 501         .m1  = { .min = G4X_M1_DISPLAY_PORT_MIN,
 502                  .max = G4X_M1_DISPLAY_PORT_MAX },
 503         .m2  = { .min = G4X_M2_DISPLAY_PORT_MIN,
 504                  .max = G4X_M2_DISPLAY_PORT_MAX },
 505         .p   = { .min = G4X_P_DISPLAY_PORT_MIN,
 506                  .max = G4X_P_DISPLAY_PORT_MAX },
 507         .p1  = { .min = G4X_P1_DISPLAY_PORT_MIN,
 508                  .max = G4X_P1_DISPLAY_PORT_MAX},
 509         .p2  = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
 510                  .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
 511                  .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
 512         .find_pll = intel_find_pll_g4x_dp,
 513 };
 514
 515 static const intel_limit_t intel_limits_pineview_sdvo = {
 516         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX},
 517         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
 518         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
 519         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
 520         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
 521         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
 522         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 523         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 524         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 525                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 526         .find_pll = intel_find_best_PLL,
 527 };
 528
 529 static const intel_limit_t intel_limits_pineview_lvds = {
 530         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 531         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
 532         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
 533         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
 534         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
 535         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
 536         .p   = { .min = PINEVIEW_P_LVDS_MIN,    .max = PINEVIEW_P_LVDS_MAX },
 537         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 538         /* Pineview only supports single-channel mode. */
 539         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 540                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_SLOW },
 541         .find_pll = intel_find_best_PLL,
 542 };
 543
 544 static const intel_limit_t intel_limits_ironlake_dac = {
 545         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 546         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 547         .n   = { .min = IRONLAKE_DAC_N_MIN,        .max = IRONLAKE_DAC_N_MAX },
 548         .m   = { .min = IRONLAKE_DAC_M_MIN,        .max = IRONLAKE_DAC_M_MAX },
 549         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 550         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 551         .p   = { .min = IRONLAKE_DAC_P_MIN,        .max = IRONLAKE_DAC_P_MAX },
 552         .p1  = { .min = IRONLAKE_DAC_P1_MIN,       .max = IRONLAKE_DAC_P1_MAX },
 553         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 554                  .p2_slow = IRONLAKE_DAC_P2_SLOW,
 555                  .p2_fast = IRONLAKE_DAC_P2_FAST },
 556         .find_pll = intel_g4x_find_best_PLL,
 557 };
 558
 559 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 560         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 561         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 562         .n   = { .min = IRONLAKE_LVDS_S_N_MIN,     .max = IRONLAKE_LVDS_S_N_MAX },
 563         .m   = { .min = IRONLAKE_LVDS_S_M_MIN,     .max = IRONLAKE_LVDS_S_M_MAX },
 564         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 565         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 566         .p   = { .min = IRONLAKE_LVDS_S_P_MIN,     .max = IRONLAKE_LVDS_S_P_MAX },
 567         .p1  = { .min = IRONLAKE_LVDS_S_P1_MIN,    .max = IRONLAKE_LVDS_S_P1_MAX },
 568         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 569                  .p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
 570                  .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
 571         .find_pll = intel_g4x_find_best_PLL,
 572 };
 573
 574 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 575         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 576         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 577         .n   = { .min = IRONLAKE_LVDS_D_N_MIN,     .max = IRONLAKE_LVDS_D_N_MAX },
 578         .m   = { .min = IRONLAKE_LVDS_D_M_MIN,     .max = IRONLAKE_LVDS_D_M_MAX },
 579         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 580         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 581         .p   = { .min = IRONLAKE_LVDS_D_P_MIN,     .max = IRONLAKE_LVDS_D_P_MAX },
 582         .p1  = { .min = IRONLAKE_LVDS_D_P1_MIN,    .max = IRONLAKE_LVDS_D_P1_MAX },
 583         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 584                  .p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
 585                  .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
 586         .find_pll = intel_g4x_find_best_PLL,
 587 };
 588
 589 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 590         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 591         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 592         .n   = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
 593         .m   = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
 594         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 595         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 596         .p   = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
 597         .p1  = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
 598         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 599                  .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
 600                  .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
 601         .find_pll = intel_g4x_find_best_PLL,
 602 };
 603
 604 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 605         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 606         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 607         .n   = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
 608         .m   = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
 609         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 610         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 611         .p   = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
 612         .p1  = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
 613         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 614                  .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
 615                  .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
 616         .find_pll = intel_g4x_find_best_PLL,
 617 };
 618
 619 static const intel_limit_t intel_limits_ironlake_display_port = {
 620         .dot = { .min = IRONLAKE_DOT_MIN,
 621                  .max = IRONLAKE_DOT_MAX },
 622         .vco = { .min = IRONLAKE_VCO_MIN,
 623                  .max = IRONLAKE_VCO_MAX},
 624         .n   = { .min = IRONLAKE_DP_N_MIN,
 625                  .max = IRONLAKE_DP_N_MAX },
 626         .m   = { .min = IRONLAKE_DP_M_MIN,
 627                  .max = IRONLAKE_DP_M_MAX },
 628         .m1  = { .min = IRONLAKE_M1_MIN,
 629                  .max = IRONLAKE_M1_MAX },
 630         .m2  = { .min = IRONLAKE_M2_MIN,
 631                  .max = IRONLAKE_M2_MAX },
 632         .p   = { .min = IRONLAKE_DP_P_MIN,
 633                  .max = IRONLAKE_DP_P_MAX },
 634         .p1  = { .min = IRONLAKE_DP_P1_MIN,
 635                  .max = IRONLAKE_DP_P1_MAX},
 636         .p2  = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
 637                  .p2_slow = IRONLAKE_DP_P2_SLOW,
 638                  .p2_fast = IRONLAKE_DP_P2_FAST },
 639         .find_pll = intel_find_pll_ironlake_dp,
 640 };
 641
 642 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc)
 643 {
 644         struct drm_device *dev = crtc->dev;
 645         struct drm_i915_private *dev_priv = dev->dev_private;
 646         const intel_limit_t *limit;
 647         int refclk = 120;
 648
 649         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 650                 if (dev_priv->lvds_use_ssc && dev_priv->lvds_ssc_freq == 100)
 651                         refclk = 100;
 652
 653                 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
 654                     LVDS_CLKB_POWER_UP) {
 655                         /* LVDS dual channel */
 656                         if (refclk == 100)
 657                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 658                         else
 659                                 limit = &intel_limits_ironlake_dual_lvds;
 660                 } else {
 661                         if (refclk == 100)
 662                                 limit = &intel_limits_ironlake_single_lvds_100m;
 663                         else
 664                                 limit = &intel_limits_ironlake_single_lvds;
 665                 }
 666         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 667                         HAS_eDP)
 668                 limit = &intel_limits_ironlake_display_port;
 669         else
 670                 limit = &intel_limits_ironlake_dac;
 671
 672         return limit;
 673 }
 674
 675 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 676 {
 677         struct drm_device *dev = crtc->dev;
 678         struct drm_i915_private *dev_priv = dev->dev_private;
 679         const intel_limit_t *limit;
 680
 681         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 682                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 683                     LVDS_CLKB_POWER_UP)
 684                         /* LVDS with dual channel */
 685                         limit = &intel_limits_g4x_dual_channel_lvds;
 686                 else
 687                         /* LVDS with dual channel */
 688                         limit = &intel_limits_g4x_single_channel_lvds;
 689         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 690                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 691                 limit = &intel_limits_g4x_hdmi;
 692         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 693                 limit = &intel_limits_g4x_sdvo;
 694         } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 695                 limit = &intel_limits_g4x_display_port;
 696         } else /* The option is for other outputs */
 697                 limit = &intel_limits_i9xx_sdvo;
 698
 699         return limit;
 700 }
 701
 702 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
 703 {
 704         struct drm_device *dev = crtc->dev;
 705         const intel_limit_t *limit;
 706
 707         if (HAS_PCH_SPLIT(dev))
 708                 limit = intel_ironlake_limit(crtc);
 709         else if (IS_G4X(dev)) {
 710                 limit = intel_g4x_limit(crtc);
 711         } else if (IS_I9XX(dev) && !IS_PINEVIEW(dev)) {
 712                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 713                         limit = &intel_limits_i9xx_lvds;
 714                 else
 715                         limit = &intel_limits_i9xx_sdvo;
 716         } else if (IS_PINEVIEW(dev)) {
 717                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 718                         limit = &intel_limits_pineview_lvds;
 719                 else
 720                         limit = &intel_limits_pineview_sdvo;
 721         } else {
 722                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 723                         limit = &intel_limits_i8xx_lvds;
 724                 else
 725                         limit = &intel_limits_i8xx_dvo;
 726         }
 727         return limit;
 728 }
 729
 730 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 731 static void pineview_clock(int refclk, intel_clock_t *clock)
 732 {
 733         clock->m = clock->m2 + 2;
 734         clock->p = clock->p1 * clock->p2;
 735         clock->vco = refclk * clock->m / clock->n;
 736         clock->dot = clock->vco / clock->p;
 737 }
 738
 739 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 740 {
 741         if (IS_PINEVIEW(dev)) {
 742                 pineview_clock(refclk, clock);
 743                 return;
 744         }
 745         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 746         clock->p = clock->p1 * clock->p2;
 747         clock->vco = refclk * clock->m / (clock->n + 2);
 748         clock->dot = clock->vco / clock->p;
 749 }
 750
 751 /**
 752  * Returns whether any output on the specified pipe is of the specified type
 753  */
 754 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 755 {
 756         struct drm_device *dev = crtc->dev;
 757         struct drm_mode_config *mode_config = &dev->mode_config;
 758         struct intel_encoder *encoder;
 759
 760         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 761                 if (encoder->base.crtc == crtc && encoder->type == type)
 762                         return true;
 763
 764         return false;
 765 }
 766
 767 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 768 /**
 769  * Returns whether the given set of divisors are valid for a given refclk with
 770  * the given connectors.
 771  */
 772
 773 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
 774 {
 775         const intel_limit_t *limit = intel_limit (crtc);
 776         struct drm_device *dev = crtc->dev;
 777
 778         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 779                 INTELPllInvalid ("p1 out of range\n");
 780         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 781                 INTELPllInvalid ("p out of range\n");
 782         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 783                 INTELPllInvalid ("m2 out of range\n");
 784         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 785                 INTELPllInvalid ("m1 out of range\n");
 786         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 787                 INTELPllInvalid ("m1 <= m2\n");
 788         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 789                 INTELPllInvalid ("m out of range\n");
 790         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 791                 INTELPllInvalid ("n out of range\n");
 792         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 793                 INTELPllInvalid ("vco out of range\n");
 794         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 795          * connector, etc., rather than just a single range.
 796          */
 797         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 798                 INTELPllInvalid ("dot out of range\n");
 799
 800         return true;
 801 }
 802
 803 static bool
 804 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 805                     int target, int refclk, intel_clock_t *best_clock)
 806
 807 {
 808         struct drm_device *dev = crtc->dev;
 809         struct drm_i915_private *dev_priv = dev->dev_private;
 810         intel_clock_t clock;
 811         int err = target;
 812
 813         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 814             (I915_READ(LVDS)) != 0) {
 815                 /*
 816                  * For LVDS, if the panel is on, just rely on its current
 817                  * settings for dual-channel.  We haven't figured out how to
 818                  * reliably set up different single/dual channel state, if we
 819                  * even can.
 820                  */
 821                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 822                     LVDS_CLKB_POWER_UP)
 823                         clock.p2 = limit->p2.p2_fast;
 824                 else
 825                         clock.p2 = limit->p2.p2_slow;
 826         } else {
 827                 if (target < limit->p2.dot_limit)
 828                         clock.p2 = limit->p2.p2_slow;
 829                 else
 830                         clock.p2 = limit->p2.p2_fast;
 831         }
 832
 833         memset (best_clock, 0, sizeof (*best_clock));
 834
 835         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 836              clock.m1++) {
 837                 for (clock.m2 = limit->m2.min;
 838                      clock.m2 <= limit->m2.max; clock.m2++) {
 839                         /* m1 is always 0 in Pineview */
 840                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 841                                 break;
 842                         for (clock.n = limit->n.min;
 843                              clock.n <= limit->n.max; clock.n++) {
 844                                 for (clock.p1 = limit->p1.min;
 845                                         clock.p1 <= limit->p1.max; clock.p1++) {
 846                                         int this_err;
 847
 848                                         intel_clock(dev, refclk, &clock);
 849
 850                                         if (!intel_PLL_is_valid(crtc, &clock))
 851                                                 continue;
 852
 853                                         this_err = abs(clock.dot - target);
 854                                         if (this_err < err) {
 855                                                 *best_clock = clock;
 856                                                 err = this_err;
 857                                         }
 858                                 }
 859                         }
 860                 }
 861         }
 862
 863         return (err != target);
 864 }
 865
 866 static bool
 867 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 868                         int target, int refclk, intel_clock_t *best_clock)
 869 {
 870         struct drm_device *dev = crtc->dev;
 871         struct drm_i915_private *dev_priv = dev->dev_private;
 872         intel_clock_t clock;
 873         int max_n;
 874         bool found;
 875         /* approximately equals target * 0.00585 */
 876         int err_most = (target >> 8) + (target >> 9);
 877         found = false;
 878
 879         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 880                 int lvds_reg;
 881
 882                 if (HAS_PCH_SPLIT(dev))
 883                         lvds_reg = PCH_LVDS;
 884                 else
 885                         lvds_reg = LVDS;
 886                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 887                     LVDS_CLKB_POWER_UP)
 888                         clock.p2 = limit->p2.p2_fast;
 889                 else
 890                         clock.p2 = limit->p2.p2_slow;
 891         } else {
 892                 if (target < limit->p2.dot_limit)
 893                         clock.p2 = limit->p2.p2_slow;
 894                 else
 895                         clock.p2 = limit->p2.p2_fast;
 896         }
 897
 898         memset(best_clock, 0, sizeof(*best_clock));
 899         max_n = limit->n.max;
 900         /* based on hardware requirement, prefer smaller n to precision */
 901         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 902                 /* based on hardware requirement, prefere larger m1,m2 */
 903                 for (clock.m1 = limit->m1.max;
 904                      clock.m1 >= limit->m1.min; clock.m1--) {
 905                         for (clock.m2 = limit->m2.max;
 906                              clock.m2 >= limit->m2.min; clock.m2--) {
 907                                 for (clock.p1 = limit->p1.max;
 908                                      clock.p1 >= limit->p1.min; clock.p1--) {
 909                                         int this_err;
 910
 911                                         intel_clock(dev, refclk, &clock);
 912                                         if (!intel_PLL_is_valid(crtc, &clock))
 913                                                 continue;
 914                                         this_err = abs(clock.dot - target) ;
 915                                         if (this_err < err_most) {
 916                                                 *best_clock = clock;
 917                                                 err_most = this_err;
 918                                                 max_n = clock.n;
 919                                                 found = true;
 920                                         }
 921                                 }
 922                         }
 923                 }
 924         }
 925         return found;
 926 }
 927
 928 static bool
 929 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 930                            int target, int refclk, intel_clock_t *best_clock)
 931 {
 932         struct drm_device *dev = crtc->dev;
 933         intel_clock_t clock;
 934
 935         /* return directly when it is eDP */
 936         if (HAS_eDP)
 937                 return true;
 938
 939         if (target < 200000) {
 940                 clock.n = 1;
 941                 clock.p1 = 2;
 942                 clock.p2 = 10;
 943                 clock.m1 = 12;
 944                 clock.m2 = 9;
 945         } else {
 946                 clock.n = 2;
 947                 clock.p1 = 1;
 948                 clock.p2 = 10;
 949                 clock.m1 = 14;
 950                 clock.m2 = 8;
 951         }
 952         intel_clock(dev, refclk, &clock);
 953         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 954         return true;
 955 }
 956
 957 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 958 static bool
 959 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 960                       int target, int refclk, intel_clock_t *best_clock)
 961 {
 962         intel_clock_t clock;
 963         if (target < 200000) {
 964                 clock.p1 = 2;
 965                 clock.p2 = 10;
 966                 clock.n = 2;
 967                 clock.m1 = 23;
 968                 clock.m2 = 8;
 969         } else {
 970                 clock.p1 = 1;
 971                 clock.p2 = 10;
 972                 clock.n = 1;
 973                 clock.m1 = 14;
 974                 clock.m2 = 2;
 975         }
 976         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 977         clock.p = (clock.p1 * clock.p2);
 978         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 979         clock.vco = 0;
 980         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 981         return true;
 982 }
 983
 984 /**
 985  * intel_wait_for_vblank - wait for vblank on a given pipe
 986  * @dev: drm device
 987  * @pipe: pipe to wait for
 988  *
 989  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 990  * mode setting code.
 991  */
 992 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 993 {
 994         struct drm_i915_private *dev_priv = dev->dev_private;
 995         int pipestat_reg = (pipe == 0 ? PIPEASTAT : PIPEBSTAT);
 996
 997         /* Clear existing vblank status. Note this will clear any other
 998          * sticky status fields as well.
 999          *
1000          * This races with i915_driver_irq_handler() with the result
1001          * that either function could miss a vblank event.  Here it is not
1002          * fatal, as we will either wait upon the next vblank interrupt or
1003          * timeout.  Generally speaking intel_wait_for_vblank() is only
1004          * called during modeset at which time the GPU should be idle and
1005          * should *not* be performing page flips and thus not waiting on
1006          * vblanks...
1007          * Currently, the result of us stealing a vblank from the irq
1008          * handler is that a single frame will be skipped during swapbuffers.
1009          */
1010         I915_WRITE(pipestat_reg,
1011                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
1012
1013         /* Wait for vblank interrupt bit to set */
1014         if (wait_for(I915_READ(pipestat_reg) &
1015                      PIPE_VBLANK_INTERRUPT_STATUS,
1016                      50))
1017                 DRM_DEBUG_KMS("vblank wait timed out\n");
1018 }
1019
1020 /**
1021  * intel_wait_for_vblank_off - wait for vblank after disabling a pipe
1022  * @dev: drm device
1023  * @pipe: pipe to wait for
1024  *
1025  * After disabling a pipe, we can't wait for vblank in the usual way,
1026  * spinning on the vblank interrupt status bit, since we won't actually
1027  * see an interrupt when the pipe is disabled.
1028  *
1029  * So this function waits for the display line value to settle (it
1030  * usually ends up stopping at the start of the next frame).
1031  */
1032 void intel_wait_for_vblank_off(struct drm_device *dev, int pipe)
1033 {
1034         struct drm_i915_private *dev_priv = dev->dev_private;
1035         int pipedsl_reg = (pipe == 0 ? PIPEADSL : PIPEBDSL);
1036         unsigned long timeout = jiffies + msecs_to_jiffies(100);
1037         u32 last_line, line;
1038
1039         /* Wait for the display line to settle */
1040         line = I915_READ(pipedsl_reg) & DSL_LINEMASK;
1041         do {
1042                 last_line = line;
1043                 MSLEEP(5);
1044                 line = I915_READ(pipedsl_reg) & DSL_LINEMASK;
1045         } while (line != last_line && time_after(timeout, jiffies));
1046
1047         if (line != last_line)
1048                 DRM_DEBUG_KMS("vblank wait timed out\n");
1049 }
1050
1051 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1052 {
1053         struct drm_device *dev = crtc->dev;
1054         struct drm_i915_private *dev_priv = dev->dev_private;
1055         struct drm_framebuffer *fb = crtc->fb;
1056         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1057         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1058         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1059         int plane, i;
1060         u32 fbc_ctl, fbc_ctl2;
1061
1062         if (fb->pitch == dev_priv->cfb_pitch &&
1063             obj_priv->fence_reg == dev_priv->cfb_fence &&
1064             intel_crtc->plane == dev_priv->cfb_plane &&
1065             I915_READ(FBC_CONTROL) & FBC_CTL_EN)
1066                 return;
1067
1068         i8xx_disable_fbc(dev);
1069
1070         dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1071
1072         if (fb->pitch < dev_priv->cfb_pitch)
1073                 dev_priv->cfb_pitch = fb->pitch;
1074
1075         /* FBC_CTL wants 64B units */
1076         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1077         dev_priv->cfb_fence = obj_priv->fence_reg;
1078         dev_priv->cfb_plane = intel_crtc->plane;
1079         plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1080
1081         /* Clear old tags */
1082         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1083                 I915_WRITE(FBC_TAG + (i * 4), 0);
1084
1085         /* Set it up... */
1086         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
1087         if (obj_priv->tiling_mode != I915_TILING_NONE)
1088                 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1089         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1090         I915_WRITE(FBC_FENCE_OFF, crtc->y);
1091
1092         /* enable it... */
1093         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1094         if (IS_I945GM(dev))
1095                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1096         fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1097         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1098         if (obj_priv->tiling_mode != I915_TILING_NONE)
1099                 fbc_ctl |= dev_priv->cfb_fence;
1100         I915_WRITE(FBC_CONTROL, fbc_ctl);
1101
1102         DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1103                       dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1104 }
1105
1106 void i8xx_disable_fbc(struct drm_device *dev)
1107 {
1108         struct drm_i915_private *dev_priv = dev->dev_private;
1109         u32 fbc_ctl;
1110
1111         /* Disable compression */
1112         fbc_ctl = I915_READ(FBC_CONTROL);
1113         fbc_ctl &= ~FBC_CTL_EN;
1114         I915_WRITE(FBC_CONTROL, fbc_ctl);
1115
1116         /* Wait for compressing bit to clear */
1117         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1118                 DRM_DEBUG_KMS("FBC idle timed out\n");
1119                 return;
1120         }
1121
1122         DRM_DEBUG_KMS("disabled FBC\n");
1123 }
1124
1125 static bool i8xx_fbc_enabled(struct drm_device *dev)
1126 {
1127         struct drm_i915_private *dev_priv = dev->dev_private;
1128
1129         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1130 }
1131
1132 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1133 {
1134         struct drm_device *dev = crtc->dev;
1135         struct drm_i915_private *dev_priv = dev->dev_private;
1136         struct drm_framebuffer *fb = crtc->fb;
1137         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1138         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1139         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1140         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1141         unsigned long stall_watermark = 200;
1142         u32 dpfc_ctl;
1143
1144         dpfc_ctl = I915_READ(DPFC_CONTROL);
1145         if (dpfc_ctl & DPFC_CTL_EN) {
1146                 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
1147                     dev_priv->cfb_fence == obj_priv->fence_reg &&
1148                     dev_priv->cfb_plane == intel_crtc->plane &&
1149                     dev_priv->cfb_y == crtc->y)
1150                         return;
1151
1152                 I915_WRITE(DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
1153                 POSTING_READ(DPFC_CONTROL);
1154                 intel_wait_for_vblank(dev, intel_crtc->pipe);
1155         }
1156
1157         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1158         dev_priv->cfb_fence = obj_priv->fence_reg;
1159         dev_priv->cfb_plane = intel_crtc->plane;
1160         dev_priv->cfb_y = crtc->y;
1161
1162         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1163         if (obj_priv->tiling_mode != I915_TILING_NONE) {
1164                 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1165                 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1166         } else {
1167                 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1168         }
1169
1170         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1171                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1172                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1173         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1174
1175         /* enable it... */
1176         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1177
1178         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1179 }
1180
1181 void g4x_disable_fbc(struct drm_device *dev)
1182 {
1183         struct drm_i915_private *dev_priv = dev->dev_private;
1184         u32 dpfc_ctl;
1185
1186         /* Disable compression */
1187         dpfc_ctl = I915_READ(DPFC_CONTROL);
1188         if (dpfc_ctl & DPFC_CTL_EN) {
1189                 dpfc_ctl &= ~DPFC_CTL_EN;
1190                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1191
1192                 DRM_DEBUG_KMS("disabled FBC\n");
1193         }
1194 }
1195
1196 static bool g4x_fbc_enabled(struct drm_device *dev)
1197 {
1198         struct drm_i915_private *dev_priv = dev->dev_private;
1199
1200         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1201 }
1202
1203 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1204 {
1205         struct drm_device *dev = crtc->dev;
1206         struct drm_i915_private *dev_priv = dev->dev_private;
1207         struct drm_framebuffer *fb = crtc->fb;
1208         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1209         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1210         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1211         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1212         unsigned long stall_watermark = 200;
1213         u32 dpfc_ctl;
1214
1215         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1216         if (dpfc_ctl & DPFC_CTL_EN) {
1217                 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
1218                     dev_priv->cfb_fence == obj_priv->fence_reg &&
1219                     dev_priv->cfb_plane == intel_crtc->plane &&
1220                     dev_priv->cfb_offset == obj_priv->gtt_offset &&
1221                     dev_priv->cfb_y == crtc->y)
1222                         return;
1223
1224                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
1225                 POSTING_READ(ILK_DPFC_CONTROL);
1226                 intel_wait_for_vblank(dev, intel_crtc->pipe);
1227         }
1228
1229         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1230         dev_priv->cfb_fence = obj_priv->fence_reg;
1231         dev_priv->cfb_plane = intel_crtc->plane;
1232         dev_priv->cfb_offset = obj_priv->gtt_offset;
1233         dev_priv->cfb_y = crtc->y;
1234
1235         dpfc_ctl &= DPFC_RESERVED;
1236         dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1237         if (obj_priv->tiling_mode != I915_TILING_NONE) {
1238                 dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence);
1239                 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1240         } else {
1241                 I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1242         }
1243
1244         I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1245                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1246                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1247         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1248         I915_WRITE(ILK_FBC_RT_BASE, obj_priv->gtt_offset | ILK_FBC_RT_VALID);
1249         /* enable it... */
1250         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
1251
1252         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1253 }
1254
1255 void ironlake_disable_fbc(struct drm_device *dev)
1256 {
1257         struct drm_i915_private *dev_priv = dev->dev_private;
1258         u32 dpfc_ctl;
1259
1260         /* Disable compression */
1261         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1262         if (dpfc_ctl & DPFC_CTL_EN) {
1263                 dpfc_ctl &= ~DPFC_CTL_EN;
1264                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1265
1266                 DRM_DEBUG_KMS("disabled FBC\n");
1267         }
1268 }
1269
1270 static bool ironlake_fbc_enabled(struct drm_device *dev)
1271 {
1272         struct drm_i915_private *dev_priv = dev->dev_private;
1273
1274         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1275 }
1276
1277 bool intel_fbc_enabled(struct drm_device *dev)
1278 {
1279         struct drm_i915_private *dev_priv = dev->dev_private;
1280
1281         if (!dev_priv->display.fbc_enabled)
1282                 return false;
1283
1284         return dev_priv->display.fbc_enabled(dev);
1285 }
1286
1287 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1288 {
1289         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1290
1291         if (!dev_priv->display.enable_fbc)
1292                 return;
1293
1294         dev_priv->display.enable_fbc(crtc, interval);
1295 }
1296
1297 void intel_disable_fbc(struct drm_device *dev)
1298 {
1299         struct drm_i915_private *dev_priv = dev->dev_private;
1300
1301         if (!dev_priv->display.disable_fbc)
1302                 return;
1303
1304         dev_priv->display.disable_fbc(dev);
1305 }
1306
1307 /**
1308  * intel_update_fbc - enable/disable FBC as needed
1309  * @dev: the drm_device
1310  *
1311  * Set up the framebuffer compression hardware at mode set time.  We
1312  * enable it if possible:
1313  *   - plane A only (on pre-965)
1314  *   - no pixel mulitply/line duplication
1315  *   - no alpha buffer discard
1316  *   - no dual wide
1317  *   - framebuffer <= 2048 in width, 1536 in height
1318  *
1319  * We can't assume that any compression will take place (worst case),
1320  * so the compressed buffer has to be the same size as the uncompressed
1321  * one.  It also must reside (along with the line length buffer) in
1322  * stolen memory.
1323  *
1324  * We need to enable/disable FBC on a global basis.
1325  */
1326 static void intel_update_fbc(struct drm_device *dev)
1327 {
1328         struct drm_i915_private *dev_priv = dev->dev_private;
1329         struct drm_crtc *crtc = NULL, *tmp_crtc;
1330         struct intel_crtc *intel_crtc;
1331         struct drm_framebuffer *fb;
1332         struct intel_framebuffer *intel_fb;
1333         struct drm_i915_gem_object *obj_priv;
1334
1335         DRM_DEBUG_KMS("\n");
1336
1337         if (!i915_powersave)
1338                 return;
1339
1340         if (!I915_HAS_FBC(dev))
1341                 return;
1342
1343         /*
1344          * If FBC is already on, we just have to verify that we can
1345          * keep it that way...
1346          * Need to disable if:
1347          *   - more than one pipe is active
1348          *   - changing FBC params (stride, fence, mode)
1349          *   - new fb is too large to fit in compressed buffer
1350          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1351          */
1352         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1353                 if (tmp_crtc->enabled) {
1354                         if (crtc) {
1355                                 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1356                                 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1357                                 goto out_disable;
1358                         }
1359                         crtc = tmp_crtc;
1360                 }
1361         }
1362
1363         if (!crtc || crtc->fb == NULL) {
1364                 DRM_DEBUG_KMS("no output, disabling\n");
1365                 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
1366                 goto out_disable;
1367         }
1368
1369         intel_crtc = to_intel_crtc(crtc);
1370         fb = crtc->fb;
1371         intel_fb = to_intel_framebuffer(fb);
1372         obj_priv = to_intel_bo(intel_fb->obj);
1373
1374         if (intel_fb->obj->size > dev_priv->cfb_size) {
1375                 DRM_DEBUG_KMS("framebuffer too large, disabling "
1376                               "compression\n");
1377                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1378                 goto out_disable;
1379         }
1380         if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1381             (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
1382                 DRM_DEBUG_KMS("mode incompatible with compression, "
1383                               "disabling\n");
1384                 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1385                 goto out_disable;
1386         }
1387         if ((crtc->mode.hdisplay > 2048) ||
1388             (crtc->mode.vdisplay > 1536)) {
1389                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1390                 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1391                 goto out_disable;
1392         }
1393         if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
1394                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1395                 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1396                 goto out_disable;
1397         }
1398         if (obj_priv->tiling_mode != I915_TILING_X) {
1399                 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1400                 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1401                 goto out_disable;
1402         }
1403
1404         /* If the kernel debugger is active, always disable compression */
1405         if (in_dbg_master())
1406                 goto out_disable;
1407
1408         intel_enable_fbc(crtc, 500);
1409         return;
1410
1411 out_disable:
1412         /* Multiple disables should be harmless */
1413         if (intel_fbc_enabled(dev)) {
1414                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1415                 intel_disable_fbc(dev);
1416         }
1417 }
1418
1419 int
1420 intel_pin_and_fence_fb_obj(struct drm_device *dev, struct drm_gem_object *obj)
1421 {
1422         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1423         u32 alignment;
1424         int ret;
1425
1426         switch (obj_priv->tiling_mode) {
1427         case I915_TILING_NONE:
1428                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1429                         alignment = 128 * 1024;
1430                 else if (IS_I965G(dev))
1431                         alignment = 4 * 1024;
1432                 else
1433                         alignment = 64 * 1024;
1434                 break;
1435         case I915_TILING_X:
1436                 /* pin() will align the object as required by fence */
1437                 alignment = 0;
1438                 break;
1439         case I915_TILING_Y:
1440                 /* FIXME: Is this true? */
1441                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1442                 return -EINVAL;
1443         default:
1444                 BUG();
1445         }
1446
1447         ret = i915_gem_object_pin(obj, alignment);
1448         if (ret != 0)
1449                 return ret;
1450
1451         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1452          * fence, whereas 965+ only requires a fence if using
1453          * framebuffer compression.  For simplicity, we always install
1454          * a fence as the cost is not that onerous.
1455          */
1456         if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1457             obj_priv->tiling_mode != I915_TILING_NONE) {
1458                 ret = i915_gem_object_get_fence_reg(obj);
1459                 if (ret != 0) {
1460                         i915_gem_object_unpin(obj);
1461                         return ret;
1462                 }
1463         }
1464
1465         return 0;
1466 }
1467
1468 /* Assume fb object is pinned & idle & fenced and just update base pointers */
1469 static int
1470 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1471                            int x, int y)
1472 {
1473         struct drm_device *dev = crtc->dev;
1474         struct drm_i915_private *dev_priv = dev->dev_private;
1475         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1476         struct intel_framebuffer *intel_fb;
1477         struct drm_i915_gem_object *obj_priv;
1478         struct drm_gem_object *obj;
1479         int plane = intel_crtc->plane;
1480         unsigned long Start, Offset;
1481         u32 dspcntr;
1482         u32 reg;
1483
1484         switch (plane) {
1485         case 0:
1486         case 1:
1487                 break;
1488         default:
1489                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1490                 return -EINVAL;
1491         }
1492
1493         intel_fb = to_intel_framebuffer(fb);
1494         obj = intel_fb->obj;
1495         obj_priv = to_intel_bo(obj);
1496
1497         reg = DSPCNTR(plane);
1498         dspcntr = I915_READ(reg);
1499         /* Mask out pixel format bits in case we change it */
1500         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1501         switch (fb->bits_per_pixel) {
1502         case 8:
1503                 dspcntr |= DISPPLANE_8BPP;
1504                 break;
1505         case 16:
1506                 if (fb->depth == 15)
1507                         dspcntr |= DISPPLANE_15_16BPP;
1508                 else
1509                         dspcntr |= DISPPLANE_16BPP;
1510                 break;
1511         case 24:
1512         case 32:
1513                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1514                 break;
1515         default:
1516                 DRM_ERROR("Unknown color depth\n");
1517                 return -EINVAL;
1518         }
1519         if (IS_I965G(dev)) {
1520                 if (obj_priv->tiling_mode != I915_TILING_NONE)
1521                         dspcntr |= DISPPLANE_TILED;
1522                 else
1523                         dspcntr &= ~DISPPLANE_TILED;
1524         }
1525
1526         if (HAS_PCH_SPLIT(dev))
1527                 /* must disable */
1528                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1529
1530         I915_WRITE(reg, dspcntr);
1531
1532         Start = obj_priv->gtt_offset;
1533         Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
1534
1535         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1536                       Start, Offset, x, y, fb->pitch);
1537         I915_WRITE(DSPSTRIDE(plane), fb->pitch);
1538         if (IS_I965G(dev)) {
1539                 I915_WRITE(DSPSURF(plane), Start);
1540                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1541                 I915_WRITE(DSPADDR(plane), Offset);
1542         } else
1543                 I915_WRITE(DSPADDR(plane), Start + Offset);
1544         POSTING_READ(reg);
1545
1546         intel_update_fbc(dev);
1547         intel_increase_pllclock(crtc);
1548
1549         return 0;
1550 }
1551
1552 static int
1553 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1554                     struct drm_framebuffer *old_fb)
1555 {
1556         struct drm_device *dev = crtc->dev;
1557         struct drm_i915_master_private *master_priv;
1558         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1559         struct intel_framebuffer *intel_fb;
1560         struct drm_i915_gem_object *obj_priv;
1561         struct drm_gem_object *obj;
1562         int pipe = intel_crtc->pipe;
1563         int plane = intel_crtc->plane;
1564         int ret;
1565
1566         /* no fb bound */
1567         if (!crtc->fb) {
1568                 DRM_DEBUG_KMS("No FB bound\n");
1569                 return 0;
1570         }
1571
1572         switch (plane) {
1573         case 0:
1574         case 1:
1575                 break;
1576         default:
1577                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1578                 return -EINVAL;
1579         }
1580
1581         intel_fb = to_intel_framebuffer(crtc->fb);
1582         obj = intel_fb->obj;
1583         obj_priv = to_intel_bo(obj);
1584
1585         mutex_lock(&dev->struct_mutex);
1586         ret = intel_pin_and_fence_fb_obj(dev, obj);
1587         if (ret != 0) {
1588                 mutex_unlock(&dev->struct_mutex);
1589                 return ret;
1590         }
1591
1592         ret = i915_gem_object_set_to_display_plane(obj);
1593         if (ret != 0) {
1594                 i915_gem_object_unpin(obj);
1595                 mutex_unlock(&dev->struct_mutex);
1596                 return ret;
1597         }
1598
1599         ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y);
1600         if (ret) {
1601                 i915_gem_object_unpin(obj);
1602                 mutex_unlock(&dev->struct_mutex);
1603                 return ret;
1604         }
1605
1606         if (old_fb) {
1607                 intel_fb = to_intel_framebuffer(old_fb);
1608                 obj_priv = to_intel_bo(intel_fb->obj);
1609                 i915_gem_object_unpin(intel_fb->obj);
1610         }
1611
1612         mutex_unlock(&dev->struct_mutex);
1613
1614         if (!dev->primary->master)
1615                 return 0;
1616
1617         master_priv = dev->primary->master->driver_priv;
1618         if (!master_priv->sarea_priv)
1619                 return 0;
1620
1621         if (pipe) {
1622                 master_priv->sarea_priv->pipeB_x = x;
1623                 master_priv->sarea_priv->pipeB_y = y;
1624         } else {
1625                 master_priv->sarea_priv->pipeA_x = x;
1626                 master_priv->sarea_priv->pipeA_y = y;
1627         }
1628
1629         return 0;
1630 }
1631
1632 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
1633 {
1634         struct drm_device *dev = crtc->dev;
1635         struct drm_i915_private *dev_priv = dev->dev_private;
1636         u32 dpa_ctl;
1637
1638         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1639         dpa_ctl = I915_READ(DP_A);
1640         dpa_ctl &= ~DP_PLL_FREQ_MASK;
1641
1642         if (clock < 200000) {
1643                 u32 temp;
1644                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1645                 /* workaround for 160Mhz:
1646                    1) program 0x4600c bits 15:0 = 0x8124
1647                    2) program 0x46010 bit 0 = 1
1648                    3) program 0x46034 bit 24 = 1
1649                    4) program 0x64000 bit 14 = 1
1650                    */
1651                 temp = I915_READ(0x4600c);
1652                 temp &= 0xffff0000;
1653                 I915_WRITE(0x4600c, temp | 0x8124);
1654
1655                 temp = I915_READ(0x46010);
1656                 I915_WRITE(0x46010, temp | 1);
1657
1658                 temp = I915_READ(0x46034);
1659                 I915_WRITE(0x46034, temp | (1 << 24));
1660         } else {
1661                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1662         }
1663         I915_WRITE(DP_A, dpa_ctl);
1664
1665         POSTING_READ(DP_A);
1666         udelay(500);
1667 }
1668
1669 /* The FDI link training functions for ILK/Ibexpeak. */
1670 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
1671 {
1672         struct drm_device *dev = crtc->dev;
1673         struct drm_i915_private *dev_priv = dev->dev_private;
1674         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1675         int pipe = intel_crtc->pipe;
1676         u32 reg, temp, tries;
1677
1678         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1679            for train result */
1680         reg = FDI_RX_IMR(pipe);
1681         temp = I915_READ(reg);
1682         temp &= ~FDI_RX_SYMBOL_LOCK;
1683         temp &= ~FDI_RX_BIT_LOCK;
1684         I915_WRITE(reg, temp);
1685         I915_READ(reg);
1686         udelay(150);
1687
1688         /* enable CPU FDI TX and PCH FDI RX */
1689         reg = FDI_TX_CTL(pipe);
1690         temp = I915_READ(reg);
1691         temp &= ~(7 << 19);
1692         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1693         temp &= ~FDI_LINK_TRAIN_NONE;
1694         temp |= FDI_LINK_TRAIN_PATTERN_1;
1695         I915_WRITE(reg, temp | FDI_TX_ENABLE);
1696
1697         reg = FDI_RX_CTL(pipe);
1698         temp = I915_READ(reg);
1699         temp &= ~FDI_LINK_TRAIN_NONE;
1700         temp |= FDI_LINK_TRAIN_PATTERN_1;
1701         I915_WRITE(reg, temp | FDI_RX_ENABLE);
1702
1703         POSTING_READ(reg);
1704         udelay(150);
1705
1706         reg = FDI_RX_IIR(pipe);
1707         for (tries = 0; tries < 5; tries++) {
1708                 temp = I915_READ(reg);
1709                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1710
1711                 if ((temp & FDI_RX_BIT_LOCK)) {
1712                         DRM_DEBUG_KMS("FDI train 1 done.\n");
1713                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
1714                         break;
1715                 }
1716         }
1717         if (tries == 5)
1718                 DRM_ERROR("FDI train 1 fail!\n");
1719
1720         /* Train 2 */
1721         reg = FDI_TX_CTL(pipe);
1722         temp = I915_READ(reg);
1723         temp &= ~FDI_LINK_TRAIN_NONE;
1724         temp |= FDI_LINK_TRAIN_PATTERN_2;
1725         I915_WRITE(reg, temp);
1726
1727         reg = FDI_RX_CTL(pipe);
1728         temp = I915_READ(reg);
1729         temp &= ~FDI_LINK_TRAIN_NONE;
1730         temp |= FDI_LINK_TRAIN_PATTERN_2;
1731         I915_WRITE(reg, temp);
1732
1733         POSTING_READ(reg);
1734         udelay(150);
1735
1736         reg = FDI_RX_IIR(pipe);
1737         for (tries = 0; tries < 5; tries++) {
1738                 temp = I915_READ(reg);
1739                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1740
1741                 if (temp & FDI_RX_SYMBOL_LOCK) {
1742                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
1743                         DRM_DEBUG_KMS("FDI train 2 done.\n");
1744                         break;
1745                 }
1746         }
1747         if (tries == 5)
1748                 DRM_ERROR("FDI train 2 fail!\n");
1749
1750         DRM_DEBUG_KMS("FDI train done\n");
1751 }
1752
1753 static const int const snb_b_fdi_train_param [] = {
1754         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
1755         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
1756         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
1757         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
1758 };
1759
1760 /* The FDI link training functions for SNB/Cougarpoint. */
1761 static void gen6_fdi_link_train(struct drm_crtc *crtc)
1762 {
1763         struct drm_device *dev = crtc->dev;
1764         struct drm_i915_private *dev_priv = dev->dev_private;
1765         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1766         int pipe = intel_crtc->pipe;
1767         u32 reg, temp, i;
1768
1769         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1770            for train result */
1771         reg = FDI_RX_IMR(pipe);
1772         temp = I915_READ(reg);
1773         temp &= ~FDI_RX_SYMBOL_LOCK;
1774         temp &= ~FDI_RX_BIT_LOCK;
1775         I915_WRITE(reg, temp);
1776
1777         POSTING_READ(reg);
1778         udelay(150);
1779
1780         /* enable CPU FDI TX and PCH FDI RX */
1781         reg = FDI_TX_CTL(pipe);
1782         temp = I915_READ(reg);
1783         temp &= ~(7 << 19);
1784         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1785         temp &= ~FDI_LINK_TRAIN_NONE;
1786         temp |= FDI_LINK_TRAIN_PATTERN_1;
1787         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1788         /* SNB-B */
1789         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1790         I915_WRITE(reg, temp | FDI_TX_ENABLE);
1791
1792         reg = FDI_RX_CTL(pipe);
1793         temp = I915_READ(reg);
1794         if (HAS_PCH_CPT(dev)) {
1795                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1796                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
1797         } else {
1798                 temp &= ~FDI_LINK_TRAIN_NONE;
1799                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1800         }
1801         I915_WRITE(reg, temp | FDI_RX_ENABLE);
1802
1803         POSTING_READ(reg);
1804         udelay(150);
1805
1806         for (i = 0; i < 4; i++ ) {
1807                 reg = FDI_TX_CTL(pipe);
1808                 temp = I915_READ(reg);
1809                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1810                 temp |= snb_b_fdi_train_param[i];
1811                 I915_WRITE(reg, temp);
1812
1813                 POSTING_READ(reg);
1814                 udelay(500);
1815
1816                 reg = FDI_RX_IIR(pipe);
1817                 temp = I915_READ(reg);
1818                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1819
1820                 if (temp & FDI_RX_BIT_LOCK) {
1821                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
1822                         DRM_DEBUG_KMS("FDI train 1 done.\n");
1823                         break;
1824                 }
1825         }
1826         if (i == 4)
1827                 DRM_ERROR("FDI train 1 fail!\n");
1828
1829         /* Train 2 */
1830         reg = FDI_TX_CTL(pipe);
1831         temp = I915_READ(reg);
1832         temp &= ~FDI_LINK_TRAIN_NONE;
1833         temp |= FDI_LINK_TRAIN_PATTERN_2;
1834         if (IS_GEN6(dev)) {
1835                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1836                 /* SNB-B */
1837                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1838         }
1839         I915_WRITE(reg, temp);
1840
1841         reg = FDI_RX_CTL(pipe);
1842         temp = I915_READ(reg);
1843         if (HAS_PCH_CPT(dev)) {
1844                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1845                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
1846         } else {
1847                 temp &= ~FDI_LINK_TRAIN_NONE;
1848                 temp |= FDI_LINK_TRAIN_PATTERN_2;
1849         }
1850         I915_WRITE(reg, temp);
1851
1852         POSTING_READ(reg);
1853         udelay(150);
1854
1855         for (i = 0; i < 4; i++ ) {
1856                 reg = FDI_TX_CTL(pipe);
1857                 temp = I915_READ(reg);
1858                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1859                 temp |= snb_b_fdi_train_param[i];
1860                 I915_WRITE(reg, temp);
1861
1862                 POSTING_READ(reg);
1863                 udelay(500);
1864
1865                 reg = FDI_RX_IIR(pipe);
1866                 temp = I915_READ(reg);
1867                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1868
1869                 if (temp & FDI_RX_SYMBOL_LOCK) {
1870                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
1871                         DRM_DEBUG_KMS("FDI train 2 done.\n");
1872                         break;
1873                 }
1874         }
1875         if (i == 4)
1876                 DRM_ERROR("FDI train 2 fail!\n");
1877
1878         DRM_DEBUG_KMS("FDI train done.\n");
1879 }
1880
1881 static void ironlake_fdi_enable(struct drm_crtc *crtc)
1882 {
1883         struct drm_device *dev = crtc->dev;
1884         struct drm_i915_private *dev_priv = dev->dev_private;
1885         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1886         int pipe = intel_crtc->pipe;
1887         u32 reg, temp;
1888
1889         /* Write the TU size bits so error detection works */
1890         I915_WRITE(FDI_RX_TUSIZE1(pipe),
1891                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
1892
1893         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1894         reg = FDI_RX_CTL(pipe);
1895         temp = I915_READ(reg);
1896         temp &= ~((0x7 << 19) | (0x7 << 16));
1897         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1898         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
1899         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
1900
1901         POSTING_READ(reg);
1902         udelay(200);
1903
1904         /* Switch from Rawclk to PCDclk */
1905         temp = I915_READ(reg);
1906         I915_WRITE(reg, temp | FDI_PCDCLK);
1907
1908         POSTING_READ(reg);
1909         udelay(200);
1910
1911         /* Enable CPU FDI TX PLL, always on for Ironlake */
1912         reg = FDI_TX_CTL(pipe);
1913         temp = I915_READ(reg);
1914         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1915                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
1916
1917                 POSTING_READ(reg);
1918                 udelay(100);
1919         }
1920 }
1921
1922 static void intel_flush_display_plane(struct drm_device *dev,
1923                                       int plane)
1924 {
1925         struct drm_i915_private *dev_priv = dev->dev_private;
1926         u32 reg = DSPADDR(plane);
1927         I915_WRITE(reg, I915_READ(reg));
1928 }
1929
1930 /*
1931  * When we disable a pipe, we need to clear any pending scanline wait events
1932  * to avoid hanging the ring, which we assume we are waiting on.
1933  */
1934 static void intel_clear_scanline_wait(struct drm_device *dev)
1935 {
1936         struct drm_i915_private *dev_priv = dev->dev_private;
1937         u32 tmp;
1938
1939         if (IS_GEN2(dev))
1940                 /* Can't break the hang on i8xx */
1941                 return;
1942
1943         tmp = I915_READ(PRB0_CTL);
1944         if (tmp & RING_WAIT) {
1945                 I915_WRITE(PRB0_CTL, tmp);
1946                 POSTING_READ(PRB0_CTL);
1947         }
1948 }
1949
1950 static void ironlake_crtc_enable(struct drm_crtc *crtc)
1951 {
1952         struct drm_device *dev = crtc->dev;
1953         struct drm_i915_private *dev_priv = dev->dev_private;
1954         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1955         int pipe = intel_crtc->pipe;
1956         int plane = intel_crtc->plane;
1957         u32 reg, temp;
1958
1959         if (intel_crtc->active)
1960                 return;
1961
1962         intel_crtc->active = true;
1963         intel_update_watermarks(dev);
1964
1965         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1966                 temp = I915_READ(PCH_LVDS);
1967                 if ((temp & LVDS_PORT_EN) == 0)
1968                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
1969         }
1970
1971         ironlake_fdi_enable(crtc);
1972
1973         /* Enable panel fitting for LVDS */
1974         if (dev_priv->pch_pf_size &&
1975             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)
1976              || HAS_eDP || intel_pch_has_edp(crtc))) {
1977                 /* Force use of hard-coded filter coefficients
1978                  * as some pre-programmed values are broken,
1979                  * e.g. x201.
1980                  */
1981                 I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1,
1982                            PF_ENABLE | PF_FILTER_MED_3x3);
1983                 I915_WRITE(pipe ? PFB_WIN_POS : PFA_WIN_POS,
1984                            dev_priv->pch_pf_pos);
1985                 I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ,
1986                            dev_priv->pch_pf_size);
1987         }
1988
1989         /* Enable CPU pipe */
1990         reg = PIPECONF(pipe);
1991         temp = I915_READ(reg);
1992         if ((temp & PIPECONF_ENABLE) == 0) {
1993                 I915_WRITE(reg, temp | PIPECONF_ENABLE);
1994                 POSTING_READ(reg);
1995                 udelay(100);
1996         }
1997
1998         /* configure and enable CPU plane */
1999         reg = DSPCNTR(plane);
2000         temp = I915_READ(reg);
2001         if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2002                 I915_WRITE(reg, temp | DISPLAY_PLANE_ENABLE);
2003                 intel_flush_display_plane(dev, plane);
2004         }
2005
2006         /* For PCH output, training FDI link */
2007         if (IS_GEN6(dev))
2008                 gen6_fdi_link_train(crtc);
2009         else
2010                 ironlake_fdi_link_train(crtc);
2011
2012         /* enable PCH DPLL */
2013         reg = PCH_DPLL(pipe);
2014         temp = I915_READ(reg);
2015         if ((temp & DPLL_VCO_ENABLE) == 0) {
2016                 I915_WRITE(reg, temp | DPLL_VCO_ENABLE);
2017                 POSTING_READ(reg);
2018                 udelay(200);
2019         }
2020
2021         if (HAS_PCH_CPT(dev)) {
2022                 /* Be sure PCH DPLL SEL is set */
2023                 temp = I915_READ(PCH_DPLL_SEL);
2024                 if (pipe == 0 && (temp & TRANSA_DPLL_ENABLE) == 0)
2025                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2026                 else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0)
2027                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2028                 I915_WRITE(PCH_DPLL_SEL, temp);
2029         }
2030
2031         /* set transcoder timing */
2032         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2033         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2034         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
2035
2036         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2037         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2038         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
2039
2040         /* enable normal train */
2041         reg = FDI_TX_CTL(pipe);
2042         temp = I915_READ(reg);
2043         temp &= ~FDI_LINK_TRAIN_NONE;
2044         temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2045         I915_WRITE(reg, temp);
2046
2047         reg = FDI_RX_CTL(pipe);
2048         temp = I915_READ(reg);
2049         if (HAS_PCH_CPT(dev)) {
2050                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2051                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2052         } else {
2053                 temp &= ~FDI_LINK_TRAIN_NONE;
2054                 temp |= FDI_LINK_TRAIN_NONE;
2055         }
2056         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2057
2058         /* wait one idle pattern time */
2059         POSTING_READ(reg);
2060         udelay(100);
2061
2062         /* For PCH DP, enable TRANS_DP_CTL */
2063         if (HAS_PCH_CPT(dev) &&
2064             intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
2065                 reg = TRANS_DP_CTL(pipe);
2066                 temp = I915_READ(reg);
2067                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2068                           TRANS_DP_SYNC_MASK);
2069                 temp |= (TRANS_DP_OUTPUT_ENABLE |
2070                          TRANS_DP_ENH_FRAMING);
2071
2072                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2073                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2074                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2075                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2076
2077                 switch (intel_trans_dp_port_sel(crtc)) {
2078                 case PCH_DP_B:
2079                         temp |= TRANS_DP_PORT_SEL_B;
2080                         break;
2081                 case PCH_DP_C:
2082                         temp |= TRANS_DP_PORT_SEL_C;
2083                         break;
2084                 case PCH_DP_D:
2085                         temp |= TRANS_DP_PORT_SEL_D;
2086                         break;
2087                 default:
2088                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2089                         temp |= TRANS_DP_PORT_SEL_B;
2090                         break;
2091                 }
2092
2093                 I915_WRITE(reg, temp);
2094         }
2095
2096         /* enable PCH transcoder */
2097         reg = TRANSCONF(pipe);
2098         temp = I915_READ(reg);
2099         /*
2100          * make the BPC in transcoder be consistent with
2101          * that in pipeconf reg.
2102          */
2103         temp &= ~PIPE_BPC_MASK;
2104         temp |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
2105         I915_WRITE(reg, temp | TRANS_ENABLE);
2106         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2107                 DRM_ERROR("failed to enable transcoder\n");
2108
2109         intel_crtc_load_lut(crtc);
2110         intel_update_fbc(dev);
2111         intel_crtc_update_cursor(crtc, true);
2112 }
2113
2114 static void ironlake_crtc_disable(struct drm_crtc *crtc)
2115 {
2116         struct drm_device *dev = crtc->dev;
2117         struct drm_i915_private *dev_priv = dev->dev_private;
2118         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2119         int pipe = intel_crtc->pipe;
2120         int plane = intel_crtc->plane;
2121         u32 reg, temp;
2122
2123         if (!intel_crtc->active)
2124                 return;
2125
2126         drm_vblank_off(dev, pipe);
2127         intel_crtc_update_cursor(crtc, false);
2128
2129         /* Disable display plane */
2130         reg = DSPCNTR(plane);
2131         temp = I915_READ(reg);
2132         if (temp & DISPLAY_PLANE_ENABLE) {
2133                 I915_WRITE(reg, temp & ~DISPLAY_PLANE_ENABLE);
2134                 intel_flush_display_plane(dev, plane);
2135         }
2136
2137         if (dev_priv->cfb_plane == plane &&
2138             dev_priv->display.disable_fbc)
2139                 dev_priv->display.disable_fbc(dev);
2140
2141         /* disable cpu pipe, disable after all planes disabled */
2142         reg = PIPECONF(pipe);
2143         temp = I915_READ(reg);
2144         if (temp & PIPECONF_ENABLE) {
2145                 I915_WRITE(reg, temp & ~PIPECONF_ENABLE);
2146                 /* wait for cpu pipe off, pipe state */
2147                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, 50))
2148                         DRM_ERROR("failed to turn off cpu pipe\n");
2149         }
2150
2151         /* Disable PF */
2152         I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1, 0);
2153         I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ, 0);
2154
2155         /* disable CPU FDI tx and PCH FDI rx */
2156         reg = FDI_TX_CTL(pipe);
2157         temp = I915_READ(reg);
2158         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2159         POSTING_READ(reg);
2160
2161         reg = FDI_RX_CTL(pipe);
2162         temp = I915_READ(reg);
2163         temp &= ~(0x7 << 16);
2164         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2165         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2166
2167         POSTING_READ(reg);
2168         udelay(100);
2169
2170         /* still set train pattern 1 */
2171         reg = FDI_TX_CTL(pipe);
2172         temp = I915_READ(reg);
2173         temp &= ~FDI_LINK_TRAIN_NONE;
2174         temp |= FDI_LINK_TRAIN_PATTERN_1;
2175         I915_WRITE(reg, temp);
2176
2177         reg = FDI_RX_CTL(pipe);
2178         temp = I915_READ(reg);
2179         if (HAS_PCH_CPT(dev)) {
2180                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2181                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2182         } else {
2183                 temp &= ~FDI_LINK_TRAIN_NONE;
2184                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2185         }
2186         /* BPC in FDI rx is consistent with that in PIPECONF */
2187         temp &= ~(0x07 << 16);
2188         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2189         I915_WRITE(reg, temp);
2190
2191         POSTING_READ(reg);
2192         udelay(100);
2193
2194         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2195                 temp = I915_READ(PCH_LVDS);
2196                 if (temp & LVDS_PORT_EN) {
2197                         I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
2198                         POSTING_READ(PCH_LVDS);
2199                         udelay(100);
2200                 }
2201         }
2202
2203         /* disable PCH transcoder */
2204         reg = TRANSCONF(plane);
2205         temp = I915_READ(reg);
2206         if (temp & TRANS_ENABLE) {
2207                 I915_WRITE(reg, temp & ~TRANS_ENABLE);
2208                 /* wait for PCH transcoder off, transcoder state */
2209                 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2210                         DRM_ERROR("failed to disable transcoder\n");
2211         }
2212
2213         if (HAS_PCH_CPT(dev)) {
2214                 /* disable TRANS_DP_CTL */
2215                 reg = TRANS_DP_CTL(pipe);
2216                 temp = I915_READ(reg);
2217                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2218                 I915_WRITE(reg, temp);
2219
2220                 /* disable DPLL_SEL */
2221                 temp = I915_READ(PCH_DPLL_SEL);
2222                 if (pipe == 0)
2223                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
2224                 else
2225                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2226                 I915_WRITE(PCH_DPLL_SEL, temp);
2227         }
2228
2229         /* disable PCH DPLL */
2230         reg = PCH_DPLL(pipe);
2231         temp = I915_READ(reg);
2232         I915_WRITE(reg, temp & ~DPLL_VCO_ENABLE);
2233
2234         /* Switch from PCDclk to Rawclk */
2235         reg = FDI_RX_CTL(pipe);
2236         temp = I915_READ(reg);
2237         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2238
2239         /* Disable CPU FDI TX PLL */
2240         reg = FDI_TX_CTL(pipe);
2241         temp = I915_READ(reg);
2242         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2243
2244         POSTING_READ(reg);
2245         udelay(100);
2246
2247         reg = FDI_RX_CTL(pipe);
2248         temp = I915_READ(reg);
2249         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2250
2251         /* Wait for the clocks to turn off. */
2252         POSTING_READ(reg);
2253         udelay(100);
2254
2255         intel_crtc->active = false;
2256         intel_update_watermarks(dev);
2257         intel_update_fbc(dev);
2258         intel_clear_scanline_wait(dev);
2259 }
2260
2261 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2262 {
2263         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2264         int pipe = intel_crtc->pipe;
2265         int plane = intel_crtc->plane;
2266
2267         /* XXX: When our outputs are all unaware of DPMS modes other than off
2268          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2269          */
2270         switch (mode) {
2271         case DRM_MODE_DPMS_ON:
2272         case DRM_MODE_DPMS_STANDBY:
2273         case DRM_MODE_DPMS_SUSPEND:
2274                 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
2275                 ironlake_crtc_enable(crtc);
2276                 break;
2277
2278         case DRM_MODE_DPMS_OFF:
2279                 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
2280                 ironlake_crtc_disable(crtc);
2281                 break;
2282         }
2283 }
2284
2285 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2286 {
2287         if (!enable && intel_crtc->overlay) {
2288                 struct drm_device *dev = intel_crtc->base.dev;
2289
2290                 mutex_lock(&dev->struct_mutex);
2291                 (void) intel_overlay_switch_off(intel_crtc->overlay, false);
2292                 mutex_unlock(&dev->struct_mutex);
2293         }
2294
2295         /* Let userspace switch the overlay on again. In most cases userspace
2296          * has to recompute where to put it anyway.
2297          */
2298 }
2299
2300 static void i9xx_crtc_enable(struct drm_crtc *crtc)
2301 {
2302         struct drm_device *dev = crtc->dev;
2303         struct drm_i915_private *dev_priv = dev->dev_private;
2304         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2305         int pipe = intel_crtc->pipe;
2306         int plane = intel_crtc->plane;
2307         u32 reg, temp;
2308
2309         if (intel_crtc->active)
2310                 return;
2311
2312         intel_crtc->active = true;
2313         intel_update_watermarks(dev);
2314
2315         /* Enable the DPLL */
2316         reg = DPLL(pipe);
2317         temp = I915_READ(reg);
2318         if ((temp & DPLL_VCO_ENABLE) == 0) {
2319                 I915_WRITE(reg, temp);
2320
2321                 /* Wait for the clocks to stabilize. */
2322                 POSTING_READ(reg);
2323                 udelay(150);
2324
2325                 I915_WRITE(reg, temp | DPLL_VCO_ENABLE);
2326
2327                 /* Wait for the clocks to stabilize. */
2328                 POSTING_READ(reg);
2329                 udelay(150);
2330
2331                 I915_WRITE(reg, temp | DPLL_VCO_ENABLE);
2332
2333                 /* Wait for the clocks to stabilize. */
2334                 POSTING_READ(reg);
2335                 udelay(150);
2336         }
2337
2338         /* Enable the pipe */
2339         reg = PIPECONF(pipe);
2340         temp = I915_READ(reg);
2341         if ((temp & PIPECONF_ENABLE) == 0)
2342                 I915_WRITE(reg, temp | PIPECONF_ENABLE);
2343
2344         /* Enable the plane */
2345         reg = DSPCNTR(plane);
2346         temp = I915_READ(reg);
2347         if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2348                 I915_WRITE(reg, temp | DISPLAY_PLANE_ENABLE);
2349                 intel_flush_display_plane(dev, plane);
2350         }
2351
2352         intel_crtc_load_lut(crtc);
2353         intel_update_fbc(dev);
2354
2355         /* Give the overlay scaler a chance to enable if it's on this pipe */
2356         intel_crtc_dpms_overlay(intel_crtc, true);
2357         intel_crtc_update_cursor(crtc, true);
2358 }
2359
2360 static void i9xx_crtc_disable(struct drm_crtc *crtc)
2361 {
2362         struct drm_device *dev = crtc->dev;
2363         struct drm_i915_private *dev_priv = dev->dev_private;
2364         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2365         int pipe = intel_crtc->pipe;
2366         int plane = intel_crtc->plane;
2367         u32 reg, temp;
2368
2369         if (!intel_crtc->active)
2370                 return;
2371
2372         /* Give the overlay scaler a chance to disable if it's on this pipe */
2373         intel_crtc_dpms_overlay(intel_crtc, false);
2374         intel_crtc_update_cursor(crtc, false);
2375         drm_vblank_off(dev, pipe);
2376
2377         if (dev_priv->cfb_plane == plane &&
2378             dev_priv->display.disable_fbc)
2379                 dev_priv->display.disable_fbc(dev);
2380
2381         /* Disable display plane */
2382         reg = DSPCNTR(plane);
2383         temp = I915_READ(reg);
2384         if (temp & DISPLAY_PLANE_ENABLE) {
2385                 I915_WRITE(reg, temp & ~DISPLAY_PLANE_ENABLE);
2386                 /* Flush the plane changes */
2387                 intel_flush_display_plane(dev, plane);
2388
2389                 /* Wait for vblank for the disable to take effect */
2390                 if (!IS_I9XX(dev))
2391                         intel_wait_for_vblank_off(dev, pipe);
2392         }
2393
2394         /* Don't disable pipe A or pipe A PLLs if needed */
2395         if (pipe == 0 && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2396                 goto done;
2397
2398         /* Next, disable display pipes */
2399         reg = PIPECONF(pipe);
2400         temp = I915_READ(reg);
2401         if (temp & PIPECONF_ENABLE) {
2402                 I915_WRITE(reg, temp & ~PIPECONF_ENABLE);
2403
2404                 /* Wait for vblank for the disable to take effect. */
2405                 POSTING_READ(reg);
2406                 intel_wait_for_vblank_off(dev, pipe);
2407         }
2408
2409         reg = DPLL(pipe);
2410         temp = I915_READ(reg);
2411         if (temp & DPLL_VCO_ENABLE) {
2412                 I915_WRITE(reg, temp & ~DPLL_VCO_ENABLE);
2413
2414                 /* Wait for the clocks to turn off. */
2415                 POSTING_READ(reg);
2416                 udelay(150);
2417         }
2418
2419 done:
2420         intel_crtc->active = false;
2421         intel_update_fbc(dev);
2422         intel_update_watermarks(dev);
2423         intel_clear_scanline_wait(dev);
2424 }
2425
2426 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2427 {
2428         /* XXX: When our outputs are all unaware of DPMS modes other than off
2429          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2430          */
2431         switch (mode) {
2432         case DRM_MODE_DPMS_ON:
2433         case DRM_MODE_DPMS_STANDBY:
2434         case DRM_MODE_DPMS_SUSPEND:
2435                 i9xx_crtc_enable(crtc);
2436                 break;
2437         case DRM_MODE_DPMS_OFF:
2438                 i9xx_crtc_disable(crtc);
2439                 break;
2440         }
2441 }
2442
2443 /**
2444  * Sets the power management mode of the pipe and plane.
2445  */
2446 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2447 {
2448         struct drm_device *dev = crtc->dev;
2449         struct drm_i915_private *dev_priv = dev->dev_private;
2450         struct drm_i915_master_private *master_priv;
2451         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2452         int pipe = intel_crtc->pipe;
2453         bool enabled;
2454
2455         if (intel_crtc->dpms_mode == mode)
2456                 return;
2457
2458         intel_crtc->dpms_mode = mode;
2459
2460         dev_priv->display.dpms(crtc, mode);
2461
2462         if (!dev->primary->master)
2463                 return;
2464
2465         master_priv = dev->primary->master->driver_priv;
2466         if (!master_priv->sarea_priv)
2467                 return;
2468
2469         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2470
2471         switch (pipe) {
2472         case 0:
2473                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2474                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2475                 break;
2476         case 1:
2477                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2478                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2479                 break;
2480         default:
2481                 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
2482                 break;
2483         }
2484 }
2485
2486 /* Prepare for a mode set.
2487  *
2488  * Note we could be a lot smarter here.  We need to figure out which outputs
2489  * will be enabled, which disabled (in short, how the config will changes)
2490  * and perform the minimum necessary steps to accomplish that, e.g. updating
2491  * watermarks, FBC configuration, making sure PLLs are programmed correctly,
2492  * panel fitting is in the proper state, etc.
2493  */
2494 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
2495 {
2496         i9xx_crtc_disable(crtc);
2497 }
2498
2499 static void i9xx_crtc_commit(struct drm_crtc *crtc)
2500 {
2501         i9xx_crtc_enable(crtc);
2502 }
2503
2504 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
2505 {
2506         ironlake_crtc_disable(crtc);
2507 }
2508
2509 static void ironlake_crtc_commit(struct drm_crtc *crtc)
2510 {
2511         ironlake_crtc_enable(crtc);
2512 }
2513
2514 void intel_encoder_prepare (struct drm_encoder *encoder)
2515 {
2516         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2517         /* lvds has its own version of prepare see intel_lvds_prepare */
2518         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
2519 }
2520
2521 void intel_encoder_commit (struct drm_encoder *encoder)
2522 {
2523         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2524         /* lvds has its own version of commit see intel_lvds_commit */
2525         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2526 }
2527
2528 void intel_encoder_destroy(struct drm_encoder *encoder)
2529 {
2530         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
2531
2532         if (intel_encoder->ddc_bus)
2533                 intel_i2c_destroy(intel_encoder->ddc_bus);
2534
2535         if (intel_encoder->i2c_bus)
2536                 intel_i2c_destroy(intel_encoder->i2c_bus);
2537
2538         drm_encoder_cleanup(encoder);
2539         kfree(intel_encoder);
2540 }
2541
2542 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
2543                                   struct drm_display_mode *mode,
2544                                   struct drm_display_mode *adjusted_mode)
2545 {
2546         struct drm_device *dev = crtc->dev;
2547         if (HAS_PCH_SPLIT(dev)) {
2548                 /* FDI link clock is fixed at 2.7G */
2549                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
2550                         return false;
2551         }
2552         return true;
2553 }
2554
2555 static int i945_get_display_clock_speed(struct drm_device *dev)
2556 {
2557         return 400000;
2558 }
2559
2560 static int i915_get_display_clock_speed(struct drm_device *dev)
2561 {
2562         return 333000;
2563 }
2564
2565 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
2566 {
2567         return 200000;
2568 }
2569
2570 static int i915gm_get_display_clock_speed(struct drm_device *dev)
2571 {
2572         u16 gcfgc = 0;
2573
2574         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
2575
2576         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
2577                 return 133000;
2578         else {
2579                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
2580                 case GC_DISPLAY_CLOCK_333_MHZ:
2581                         return 333000;
2582                 default:
2583                 case GC_DISPLAY_CLOCK_190_200_MHZ:
2584                         return 190000;
2585                 }
2586         }
2587 }
2588
2589 static int i865_get_display_clock_speed(struct drm_device *dev)
2590 {
2591         return 266000;
2592 }
2593
2594 static int i855_get_display_clock_speed(struct drm_device *dev)
2595 {
2596         u16 hpllcc = 0;
2597         /* Assume that the hardware is in the high speed state.  This
2598          * should be the default.
2599          */
2600         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2601         case GC_CLOCK_133_200:
2602         case GC_CLOCK_100_200:
2603                 return 200000;
2604         case GC_CLOCK_166_250:
2605                 return 250000;
2606         case GC_CLOCK_100_133:
2607                 return 133000;
2608         }
2609
2610         /* Shouldn't happen */
2611         return 0;
2612 }
2613
2614 static int i830_get_display_clock_speed(struct drm_device *dev)
2615 {
2616         return 133000;
2617 }
2618
2619 struct fdi_m_n {
2620         u32        tu;
2621         u32        gmch_m;
2622         u32        gmch_n;
2623         u32        link_m;
2624         u32        link_n;
2625 };
2626
2627 static void
2628 fdi_reduce_ratio(u32 *num, u32 *den)
2629 {
2630         while (*num > 0xffffff || *den > 0xffffff) {
2631                 *num >>= 1;
2632                 *den >>= 1;
2633         }
2634 }
2635
2636 #define DATA_N 0x800000
2637 #define LINK_N 0x80000
2638
2639 static void
2640 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
2641                      int link_clock, struct fdi_m_n *m_n)
2642 {
2643         u64 temp;
2644
2645         m_n->tu = 64; /* default size */
2646
2647         temp = (u64) DATA_N * pixel_clock;
2648         temp = div_u64(temp, link_clock);
2649         m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
2650         m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
2651         m_n->gmch_n = DATA_N;
2652         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2653
2654         temp = (u64) LINK_N * pixel_clock;
2655         m_n->link_m = div_u64(temp, link_clock);
2656         m_n->link_n = LINK_N;
2657         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2658 }
2659
2660
2661 struct intel_watermark_params {
2662         unsigned long fifo_size;
2663         unsigned long max_wm;
2664         unsigned long default_wm;
2665         unsigned long guard_size;
2666         unsigned long cacheline_size;
2667 };
2668
2669 /* Pineview has different values for various configs */
2670 static struct intel_watermark_params pineview_display_wm = {
2671         PINEVIEW_DISPLAY_FIFO,
2672         PINEVIEW_MAX_WM,
2673         PINEVIEW_DFT_WM,
2674         PINEVIEW_GUARD_WM,
2675         PINEVIEW_FIFO_LINE_SIZE
2676 };
2677 static struct intel_watermark_params pineview_display_hplloff_wm = {
2678         PINEVIEW_DISPLAY_FIFO,
2679         PINEVIEW_MAX_WM,
2680         PINEVIEW_DFT_HPLLOFF_WM,
2681         PINEVIEW_GUARD_WM,
2682         PINEVIEW_FIFO_LINE_SIZE
2683 };
2684 static struct intel_watermark_params pineview_cursor_wm = {
2685         PINEVIEW_CURSOR_FIFO,
2686         PINEVIEW_CURSOR_MAX_WM,
2687         PINEVIEW_CURSOR_DFT_WM,
2688         PINEVIEW_CURSOR_GUARD_WM,
2689         PINEVIEW_FIFO_LINE_SIZE,
2690 };
2691 static struct intel_watermark_params pineview_cursor_hplloff_wm = {
2692         PINEVIEW_CURSOR_FIFO,
2693         PINEVIEW_CURSOR_MAX_WM,
2694         PINEVIEW_CURSOR_DFT_WM,
2695         PINEVIEW_CURSOR_GUARD_WM,
2696         PINEVIEW_FIFO_LINE_SIZE
2697 };
2698 static struct intel_watermark_params g4x_wm_info = {
2699         G4X_FIFO_SIZE,
2700         G4X_MAX_WM,
2701         G4X_MAX_WM,
2702         2,
2703         G4X_FIFO_LINE_SIZE,
2704 };
2705 static struct intel_watermark_params g4x_cursor_wm_info = {
2706         I965_CURSOR_FIFO,
2707         I965_CURSOR_MAX_WM,
2708         I965_CURSOR_DFT_WM,
2709         2,
2710         G4X_FIFO_LINE_SIZE,
2711 };
2712 static struct intel_watermark_params i965_cursor_wm_info = {
2713         I965_CURSOR_FIFO,
2714         I965_CURSOR_MAX_WM,
2715         I965_CURSOR_DFT_WM,
2716         2,
2717         I915_FIFO_LINE_SIZE,
2718 };
2719 static struct intel_watermark_params i945_wm_info = {
2720         I945_FIFO_SIZE,
2721         I915_MAX_WM,
2722         1,
2723         2,
2724         I915_FIFO_LINE_SIZE
2725 };
2726 static struct intel_watermark_params i915_wm_info = {
2727         I915_FIFO_SIZE,
2728         I915_MAX_WM,
2729         1,
2730         2,
2731         I915_FIFO_LINE_SIZE
2732 };
2733 static struct intel_watermark_params i855_wm_info = {
2734         I855GM_FIFO_SIZE,
2735         I915_MAX_WM,
2736         1,
2737         2,
2738         I830_FIFO_LINE_SIZE
2739 };
2740 static struct intel_watermark_params i830_wm_info = {
2741         I830_FIFO_SIZE,
2742         I915_MAX_WM,
2743         1,
2744         2,
2745         I830_FIFO_LINE_SIZE
2746 };
2747
2748 static struct intel_watermark_params ironlake_display_wm_info = {
2749         ILK_DISPLAY_FIFO,
2750         ILK_DISPLAY_MAXWM,
2751         ILK_DISPLAY_DFTWM,
2752         2,
2753         ILK_FIFO_LINE_SIZE
2754 };
2755
2756 static struct intel_watermark_params ironlake_cursor_wm_info = {
2757         ILK_CURSOR_FIFO,
2758         ILK_CURSOR_MAXWM,
2759         ILK_CURSOR_DFTWM,
2760         2,
2761         ILK_FIFO_LINE_SIZE
2762 };
2763
2764 static struct intel_watermark_params ironlake_display_srwm_info = {
2765         ILK_DISPLAY_SR_FIFO,
2766         ILK_DISPLAY_MAX_SRWM,
2767         ILK_DISPLAY_DFT_SRWM,
2768         2,
2769         ILK_FIFO_LINE_SIZE
2770 };
2771
2772 static struct intel_watermark_params ironlake_cursor_srwm_info = {
2773         ILK_CURSOR_SR_FIFO,
2774         ILK_CURSOR_MAX_SRWM,
2775         ILK_CURSOR_DFT_SRWM,
2776         2,
2777         ILK_FIFO_LINE_SIZE
2778 };
2779
2780 /**
2781  * intel_calculate_wm - calculate watermark level
2782  * @clock_in_khz: pixel clock
2783  * @wm: chip FIFO params
2784  * @pixel_size: display pixel size
2785  * @latency_ns: memory latency for the platform
2786  *
2787  * Calculate the watermark level (the level at which the display plane will
2788  * start fetching from memory again).  Each chip has a different display
2789  * FIFO size and allocation, so the caller needs to figure that out and pass
2790  * in the correct intel_watermark_params structure.
2791  *
2792  * As the pixel clock runs, the FIFO will be drained at a rate that depends
2793  * on the pixel size.  When it reaches the watermark level, it'll start
2794  * fetching FIFO line sized based chunks from memory until the FIFO fills
2795  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
2796  * will occur, and a display engine hang could result.
2797  */
2798 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2799                                         struct intel_watermark_params *wm,
2800                                         int pixel_size,
2801                                         unsigned long latency_ns)
2802 {
2803         long entries_required, wm_size;
2804
2805         /*
2806          * Note: we need to make sure we don't overflow for various clock &
2807          * latency values.
2808          * clocks go from a few thousand to several hundred thousand.
2809          * latency is usually a few thousand
2810          */
2811         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
2812                 1000;
2813         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
2814
2815         DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
2816
2817         wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2818
2819         DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
2820
2821         /* Don't promote wm_size to unsigned... */
2822         if (wm_size > (long)wm->max_wm)
2823                 wm_size = wm->max_wm;
2824         if (wm_size <= 0)
2825                 wm_size = wm->default_wm;
2826         return wm_size;
2827 }
2828
2829 struct cxsr_latency {
2830         int is_desktop;
2831         int is_ddr3;
2832         unsigned long fsb_freq;
2833         unsigned long mem_freq;
2834         unsigned long display_sr;
2835         unsigned long display_hpll_disable;
2836         unsigned long cursor_sr;
2837         unsigned long cursor_hpll_disable;
2838 };
2839
2840 static const struct cxsr_latency cxsr_latency_table[] = {
2841         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
2842         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
2843         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
2844         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
2845         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
2846
2847         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
2848         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
2849         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
2850         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
2851         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
2852
2853         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
2854         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
2855         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
2856         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
2857         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
2858
2859         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
2860         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
2861         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
2862         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
2863         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
2864
2865         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
2866         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
2867         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
2868         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
2869         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
2870
2871         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
2872         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
2873         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
2874         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
2875         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
2876 };
2877
2878 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
2879                                                          int is_ddr3,
2880                                                          int fsb,
2881                                                          int mem)
2882 {
2883         const struct cxsr_latency *latency;
2884         int i;
2885
2886         if (fsb == 0 || mem == 0)
2887                 return NULL;
2888
2889         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2890                 latency = &cxsr_latency_table[i];
2891                 if (is_desktop == latency->is_desktop &&
2892                     is_ddr3 == latency->is_ddr3 &&
2893                     fsb == latency->fsb_freq && mem == latency->mem_freq)
2894                         return latency;
2895         }
2896
2897         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2898
2899         return NULL;
2900 }
2901
2902 static void pineview_disable_cxsr(struct drm_device *dev)
2903 {
2904         struct drm_i915_private *dev_priv = dev->dev_private;
2905
2906         /* deactivate cxsr */
2907         I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
2908 }
2909
2910 /*
2911  * Latency for FIFO fetches is dependent on several factors:
2912  *   - memory configuration (speed, channels)
2913  *   - chipset
2914  *   - current MCH state
2915  * It can be fairly high in some situations, so here we assume a fairly
2916  * pessimal value.  It's a tradeoff between extra memory fetches (if we
2917  * set this value too high, the FIFO will fetch frequently to stay full)
2918  * and power consumption (set it too low to save power and we might see
2919  * FIFO underruns and display "flicker").
2920  *
2921  * A value of 5us seems to be a good balance; safe for very low end
2922  * platforms but not overly aggressive on lower latency configs.
2923  */
2924 static const int latency_ns = 5000;
2925
2926 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
2927 {
2928         struct drm_i915_private *dev_priv = dev->dev_private;
2929         uint32_t dsparb = I915_READ(DSPARB);
2930         int size;
2931
2932         size = dsparb & 0x7f;
2933         if (plane)
2934                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
2935
2936         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2937                       plane ? "B" : "A", size);
2938
2939         return size;
2940 }
2941
2942 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
2943 {
2944         struct drm_i915_private *dev_priv = dev->dev_private;
2945         uint32_t dsparb = I915_READ(DSPARB);
2946         int size;
2947
2948         size = dsparb & 0x1ff;
2949         if (plane)
2950                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
2951         size >>= 1; /* Convert to cachelines */
2952
2953         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2954                       plane ? "B" : "A", size);
2955
2956         return size;
2957 }
2958
2959 static int i845_get_fifo_size(struct drm_device *dev, int plane)
2960 {
2961         struct drm_i915_private *dev_priv = dev->dev_private;
2962         uint32_t dsparb = I915_READ(DSPARB);
2963         int size;
2964
2965         size = dsparb & 0x7f;
2966         size >>= 2; /* Convert to cachelines */
2967
2968         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2969                       plane ? "B" : "A",
2970                       size);
2971
2972         return size;
2973 }
2974
2975 static int i830_get_fifo_size(struct drm_device *dev, int plane)
2976 {
2977         struct drm_i915_private *dev_priv = dev->dev_private;
2978         uint32_t dsparb = I915_READ(DSPARB);
2979         int size;
2980
2981         size = dsparb & 0x7f;
2982         size >>= 1; /* Convert to cachelines */
2983
2984         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2985                       plane ? "B" : "A", size);
2986
2987         return size;
2988 }
2989
2990 static void pineview_update_wm(struct drm_device *dev,  int planea_clock,
2991                                int planeb_clock, int sr_hdisplay, int unused,
2992                                int pixel_size)
2993 {
2994         struct drm_i915_private *dev_priv = dev->dev_private;
2995         const struct cxsr_latency *latency;
2996         u32 reg;
2997         unsigned long wm;
2998         int sr_clock;
2999
3000         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3001                                          dev_priv->fsb_freq, dev_priv->mem_freq);
3002         if (!latency) {
3003                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3004                 pineview_disable_cxsr(dev);
3005                 return;
3006         }
3007
3008         if (!planea_clock || !planeb_clock) {
3009                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3010
3011                 /* Display SR */
3012                 wm = intel_calculate_wm(sr_clock, &pineview_display_wm,
3013                                         pixel_size, latency->display_sr);
3014                 reg = I915_READ(DSPFW1);
3015                 reg &= ~DSPFW_SR_MASK;
3016                 reg |= wm << DSPFW_SR_SHIFT;
3017                 I915_WRITE(DSPFW1, reg);
3018                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3019
3020                 /* cursor SR */
3021                 wm = intel_calculate_wm(sr_clock, &pineview_cursor_wm,
3022                                         pixel_size, latency->cursor_sr);
3023                 reg = I915_READ(DSPFW3);
3024                 reg &= ~DSPFW_CURSOR_SR_MASK;
3025                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3026                 I915_WRITE(DSPFW3, reg);
3027
3028                 /* Display HPLL off SR */
3029                 wm = intel_calculate_wm(sr_clock, &pineview_display_hplloff_wm,
3030                                         pixel_size, latency->display_hpll_disable);
3031                 reg = I915_READ(DSPFW3);
3032                 reg &= ~DSPFW_HPLL_SR_MASK;
3033                 reg |= wm & DSPFW_HPLL_SR_MASK;
3034                 I915_WRITE(DSPFW3, reg);
3035
3036                 /* cursor HPLL off SR */
3037                 wm = intel_calculate_wm(sr_clock, &pineview_cursor_hplloff_wm,
3038                                         pixel_size, latency->cursor_hpll_disable);
3039                 reg = I915_READ(DSPFW3);
3040                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3041                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3042                 I915_WRITE(DSPFW3, reg);
3043                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3044
3045                 /* activate cxsr */
3046                 I915_WRITE(DSPFW3,
3047                            I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
3048                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3049         } else {
3050                 pineview_disable_cxsr(dev);
3051                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3052         }
3053 }
3054
3055 static void g4x_update_wm(struct drm_device *dev,  int planea_clock,
3056                           int planeb_clock, int sr_hdisplay, int sr_htotal,
3057                           int pixel_size)
3058 {
3059         struct drm_i915_private *dev_priv = dev->dev_private;
3060         int total_size, cacheline_size;
3061         int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
3062         struct intel_watermark_params planea_params, planeb_params;
3063         unsigned long line_time_us;
3064         int sr_clock, sr_entries = 0, entries_required;
3065
3066         /* Create copies of the base settings for each pipe */
3067         planea_params = planeb_params = g4x_wm_info;
3068
3069         /* Grab a couple of global values before we overwrite them */
3070         total_size = planea_params.fifo_size;
3071         cacheline_size = planea_params.cacheline_size;
3072
3073         /*
3074          * Note: we need to make sure we don't overflow for various clock &
3075          * latency values.
3076          * clocks go from a few thousand to several hundred thousand.
3077          * latency is usually a few thousand
3078          */
3079         entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
3080                 1000;
3081         entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3082         planea_wm = entries_required + planea_params.guard_size;
3083
3084         entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
3085                 1000;
3086         entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3087         planeb_wm = entries_required + planeb_params.guard_size;
3088
3089         cursora_wm = cursorb_wm = 16;
3090         cursor_sr = 32;
3091
3092         DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3093
3094         /* Calc sr entries for one plane configs */
3095         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3096                 /* self-refresh has much higher latency */
3097                 static const int sr_latency_ns = 12000;
3098
3099                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3100                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3101
3102                 /* Use ns/us then divide to preserve precision */
3103                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3104                         pixel_size * sr_hdisplay;
3105                 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3106
3107                 entries_required = (((sr_latency_ns / line_time_us) +
3108                                      1000) / 1000) * pixel_size * 64;
3109                 entries_required = DIV_ROUND_UP(entries_required,
3110                                                 g4x_cursor_wm_info.cacheline_size);
3111                 cursor_sr = entries_required + g4x_cursor_wm_info.guard_size;
3112
3113                 if (cursor_sr > g4x_cursor_wm_info.max_wm)
3114                         cursor_sr = g4x_cursor_wm_info.max_wm;
3115                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3116                               "cursor %d\n", sr_entries, cursor_sr);
3117
3118                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3119         } else {
3120                 /* Turn off self refresh if both pipes are enabled */
3121                 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3122                            & ~FW_BLC_SELF_EN);
3123         }
3124
3125         DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
3126                   planea_wm, planeb_wm, sr_entries);
3127
3128         planea_wm &= 0x3f;
3129         planeb_wm &= 0x3f;
3130
3131         I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
3132                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
3133                    (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
3134         I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
3135                    (cursora_wm << DSPFW_CURSORA_SHIFT));
3136         /* HPLL off in SR has some issues on G4x... disable it */
3137         I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
3138                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3139 }
3140
3141 static void i965_update_wm(struct drm_device *dev, int planea_clock,
3142                            int planeb_clock, int sr_hdisplay, int sr_htotal,
3143                            int pixel_size)
3144 {
3145         struct drm_i915_private *dev_priv = dev->dev_private;
3146         unsigned long line_time_us;
3147         int sr_clock, sr_entries, srwm = 1;
3148         int cursor_sr = 16;
3149
3150         /* Calc sr entries for one plane configs */
3151         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3152                 /* self-refresh has much higher latency */
3153                 static const int sr_latency_ns = 12000;
3154
3155                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3156                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3157
3158                 /* Use ns/us then divide to preserve precision */
3159                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3160                         pixel_size * sr_hdisplay;
3161                 sr_entries = DIV_ROUND_UP(sr_entries, I915_FIFO_LINE_SIZE);
3162                 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
3163                 srwm = I965_FIFO_SIZE - sr_entries;
3164                 if (srwm < 0)
3165                         srwm = 1;
3166                 srwm &= 0x1ff;
3167
3168                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3169                         pixel_size * 64;
3170                 sr_entries = DIV_ROUND_UP(sr_entries,
3171                                           i965_cursor_wm_info.cacheline_size);
3172                 cursor_sr = i965_cursor_wm_info.fifo_size -
3173                         (sr_entries + i965_cursor_wm_info.guard_size);
3174
3175                 if (cursor_sr > i965_cursor_wm_info.max_wm)
3176                         cursor_sr = i965_cursor_wm_info.max_wm;
3177
3178                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3179                               "cursor %d\n", srwm, cursor_sr);
3180
3181                 if (IS_I965GM(dev))
3182                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3183         } else {
3184                 /* Turn off self refresh if both pipes are enabled */
3185                 if (IS_I965GM(dev))
3186                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3187                                    & ~FW_BLC_SELF_EN);
3188         }
3189
3190         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
3191                       srwm);
3192
3193         /* 965 has limitations... */
3194         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
3195                    (8 << 0));
3196         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
3197         /* update cursor SR watermark */
3198         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3199 }
3200
3201 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
3202                            int planeb_clock, int sr_hdisplay, int sr_htotal,
3203                            int pixel_size)
3204 {
3205         struct drm_i915_private *dev_priv = dev->dev_private;
3206         uint32_t fwater_lo;
3207         uint32_t fwater_hi;
3208         int total_size, cacheline_size, cwm, srwm = 1;
3209         int planea_wm, planeb_wm;
3210         struct intel_watermark_params planea_params, planeb_params;
3211         unsigned long line_time_us;
3212         int sr_clock, sr_entries = 0;
3213
3214         /* Create copies of the base settings for each pipe */
3215         if (IS_I965GM(dev) || IS_I945GM(dev))
3216                 planea_params = planeb_params = i945_wm_info;
3217         else if (IS_I9XX(dev))
3218                 planea_params = planeb_params = i915_wm_info;
3219         else
3220                 planea_params = planeb_params = i855_wm_info;
3221
3222         /* Grab a couple of global values before we overwrite them */
3223         total_size = planea_params.fifo_size;
3224         cacheline_size = planea_params.cacheline_size;
3225
3226         /* Update per-plane FIFO sizes */
3227         planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3228         planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
3229
3230         planea_wm = intel_calculate_wm(planea_clock, &planea_params,
3231                                        pixel_size, latency_ns);
3232         planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
3233                                        pixel_size, latency_ns);
3234         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3235
3236         /*
3237          * Overlay gets an aggressive default since video jitter is bad.
3238          */
3239         cwm = 2;
3240
3241         /* Calc sr entries for one plane configs */
3242         if (HAS_FW_BLC(dev) && sr_hdisplay &&
3243             (!planea_clock || !planeb_clock)) {
3244                 /* self-refresh has much higher latency */
3245                 static const int sr_latency_ns = 6000;
3246
3247                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3248                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3249
3250                 /* Use ns/us then divide to preserve precision */
3251                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3252                         pixel_size * sr_hdisplay;
3253                 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3254                 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
3255                 srwm = total_size - sr_entries;
3256                 if (srwm < 0)
3257                         srwm = 1;
3258
3259                 if (IS_I945G(dev) || IS_I945GM(dev))
3260                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
3261                 else if (IS_I915GM(dev)) {
3262                         /* 915M has a smaller SRWM field */
3263                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
3264                         I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
3265                 }
3266         } else {
3267                 /* Turn off self refresh if both pipes are enabled */
3268                 if (IS_I945G(dev) || IS_I945GM(dev)) {
3269                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3270                                    & ~FW_BLC_SELF_EN);
3271                 } else if (IS_I915GM(dev)) {
3272                         I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
3273                 }
3274         }
3275
3276         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
3277                       planea_wm, planeb_wm, cwm, srwm);
3278
3279         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
3280         fwater_hi = (cwm & 0x1f);
3281
3282         /* Set request length to 8 cachelines per fetch */
3283         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
3284         fwater_hi = fwater_hi | (1 << 8);
3285
3286         I915_WRITE(FW_BLC, fwater_lo);
3287         I915_WRITE(FW_BLC2, fwater_hi);
3288 }
3289
3290 static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
3291                            int unused2, int unused3, int pixel_size)
3292 {
3293         struct drm_i915_private *dev_priv = dev->dev_private;
3294         uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
3295         int planea_wm;
3296
3297         i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3298
3299         planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
3300                                        pixel_size, latency_ns);
3301         fwater_lo |= (3<<8) | planea_wm;
3302
3303         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
3304
3305         I915_WRITE(FW_BLC, fwater_lo);
3306 }
3307
3308 #define ILK_LP0_PLANE_LATENCY           700
3309 #define ILK_LP0_CURSOR_LATENCY          1300
3310
3311 static bool ironlake_compute_wm0(struct drm_device *dev,
3312                                  int pipe,
3313                                  int *plane_wm,
3314                                  int *cursor_wm)
3315 {
3316         struct drm_crtc *crtc;
3317         int htotal, hdisplay, clock, pixel_size = 0;
3318         int line_time_us, line_count, entries;
3319
3320         crtc = intel_get_crtc_for_pipe(dev, pipe);
3321         if (crtc->fb == NULL || !crtc->enabled)
3322                 return false;
3323
3324         htotal = crtc->mode.htotal;
3325         hdisplay = crtc->mode.hdisplay;
3326         clock = crtc->mode.clock;
3327         pixel_size = crtc->fb->bits_per_pixel / 8;
3328
3329         /* Use the small buffer method to calculate plane watermark */
3330         entries = ((clock * pixel_size / 1000) * ILK_LP0_PLANE_LATENCY) / 1000;
3331         entries = DIV_ROUND_UP(entries,
3332                                ironlake_display_wm_info.cacheline_size);
3333         *plane_wm = entries + ironlake_display_wm_info.guard_size;
3334         if (*plane_wm > (int)ironlake_display_wm_info.max_wm)
3335                 *plane_wm = ironlake_display_wm_info.max_wm;
3336
3337         /* Use the large buffer method to calculate cursor watermark */
3338         line_time_us = ((htotal * 1000) / clock);
3339         line_count = (ILK_LP0_CURSOR_LATENCY / line_time_us + 1000) / 1000;
3340         entries = line_count * 64 * pixel_size;
3341         entries = DIV_ROUND_UP(entries,
3342                                ironlake_cursor_wm_info.cacheline_size);
3343         *cursor_wm = entries + ironlake_cursor_wm_info.guard_size;
3344         if (*cursor_wm > ironlake_cursor_wm_info.max_wm)
3345                 *cursor_wm = ironlake_cursor_wm_info.max_wm;
3346
3347         return true;
3348 }
3349
3350 static void ironlake_update_wm(struct drm_device *dev,
3351                                int planea_clock, int planeb_clock,
3352                                int sr_hdisplay, int sr_htotal,
3353                                int pixel_size)
3354 {
3355         struct drm_i915_private *dev_priv = dev->dev_private;
3356         int plane_wm, cursor_wm, enabled;
3357         int tmp;
3358
3359         enabled = 0;
3360         if (ironlake_compute_wm0(dev, 0, &plane_wm, &cursor_wm)) {
3361                 I915_WRITE(WM0_PIPEA_ILK,
3362                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
3363                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
3364                               " plane %d, " "cursor: %d\n",
3365                               plane_wm, cursor_wm);
3366                 enabled++;
3367         }
3368
3369         if (ironlake_compute_wm0(dev, 1, &plane_wm, &cursor_wm)) {
3370                 I915_WRITE(WM0_PIPEB_ILK,
3371                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
3372                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
3373                               " plane %d, cursor: %d\n",
3374                               plane_wm, cursor_wm);
3375                 enabled++;
3376         }
3377
3378         /*
3379          * Calculate and update the self-refresh watermark only when one
3380          * display plane is used.
3381          */
3382         tmp = 0;
3383         if (enabled == 1 && /* XXX disabled due to buggy implmentation? */ 0) {
3384                 unsigned long line_time_us;
3385                 int small, large, plane_fbc;
3386                 int sr_clock, entries;
3387                 int line_count, line_size;
3388                 /* Read the self-refresh latency. The unit is 0.5us */
3389                 int ilk_sr_latency = I915_READ(MLTR_ILK) & ILK_SRLT_MASK;
3390
3391                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3392                 line_time_us = (sr_htotal * 1000) / sr_clock;
3393
3394                 /* Use ns/us then divide to preserve precision */
3395                 line_count = ((ilk_sr_latency * 500) / line_time_us + 1000)
3396                         / 1000;
3397                 line_size = sr_hdisplay * pixel_size;
3398
3399                 /* Use the minimum of the small and large buffer method for primary */
3400                 small = ((sr_clock * pixel_size / 1000) * (ilk_sr_latency * 500)) / 1000;
3401                 large = line_count * line_size;
3402
3403                 entries = DIV_ROUND_UP(min(small, large),
3404                                        ironlake_display_srwm_info.cacheline_size);
3405
3406                 plane_fbc = entries * 64;
3407                 plane_fbc = DIV_ROUND_UP(plane_fbc, line_size);
3408
3409                 plane_wm = entries + ironlake_display_srwm_info.guard_size;
3410                 if (plane_wm > (int)ironlake_display_srwm_info.max_wm)
3411                         plane_wm = ironlake_display_srwm_info.max_wm;
3412
3413                 /* calculate the self-refresh watermark for display cursor */
3414                 entries = line_count * pixel_size * 64;
3415                 entries = DIV_ROUND_UP(entries,
3416                                        ironlake_cursor_srwm_info.cacheline_size);
3417
3418                 cursor_wm = entries + ironlake_cursor_srwm_info.guard_size;
3419                 if (cursor_wm > (int)ironlake_cursor_srwm_info.max_wm)
3420                         cursor_wm = ironlake_cursor_srwm_info.max_wm;
3421
3422                 /* configure watermark and enable self-refresh */
3423                 tmp = (WM1_LP_SR_EN |
3424                        (ilk_sr_latency << WM1_LP_LATENCY_SHIFT) |
3425                        (plane_fbc << WM1_LP_FBC_SHIFT) |
3426                        (plane_wm << WM1_LP_SR_SHIFT) |
3427                        cursor_wm);
3428                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d, fbc lines %d,"
3429                               " cursor %d\n", plane_wm, plane_fbc, cursor_wm);
3430         }
3431         I915_WRITE(WM1_LP_ILK, tmp);
3432         /* XXX setup WM2 and WM3 */
3433 }
3434
3435 /**
3436  * intel_update_watermarks - update FIFO watermark values based on current modes
3437  *
3438  * Calculate watermark values for the various WM regs based on current mode
3439  * and plane configuration.
3440  *
3441  * There are several cases to deal with here:
3442  *   - normal (i.e. non-self-refresh)
3443  *   - self-refresh (SR) mode
3444  *   - lines are large relative to FIFO size (buffer can hold up to 2)
3445  *   - lines are small relative to FIFO size (buffer can hold more than 2
3446  *     lines), so need to account for TLB latency
3447  *
3448  *   The normal calculation is:
3449  *     watermark = dotclock * bytes per pixel * latency
3450  *   where latency is platform & configuration dependent (we assume pessimal
3451  *   values here).
3452  *
3453  *   The SR calculation is:
3454  *     watermark = (trunc(latency/line time)+1) * surface width *
3455  *       bytes per pixel
3456  *   where
3457  *     line time = htotal / dotclock
3458  *     surface width = hdisplay for normal plane and 64 for cursor
3459  *   and latency is assumed to be high, as above.
3460  *
3461  * The final value programmed to the register should always be rounded up,
3462  * and include an extra 2 entries to account for clock crossings.
3463  *
3464  * We don't use the sprite, so we can ignore that.  And on Crestline we have
3465  * to set the non-SR watermarks to 8.
3466  */
3467 static void intel_update_watermarks(struct drm_device *dev)
3468 {
3469         struct drm_i915_private *dev_priv = dev->dev_private;
3470         struct drm_crtc *crtc;
3471         int sr_hdisplay = 0;
3472         unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
3473         int enabled = 0, pixel_size = 0;
3474         int sr_htotal = 0;
3475
3476         if (!dev_priv->display.update_wm)
3477                 return;
3478
3479         /* Get the clock config from both planes */
3480         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3481                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3482                 if (intel_crtc->active) {
3483                         enabled++;
3484                         if (intel_crtc->plane == 0) {
3485                                 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
3486                                               intel_crtc->pipe, crtc->mode.clock);
3487                                 planea_clock = crtc->mode.clock;
3488                         } else {
3489                                 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
3490                                               intel_crtc->pipe, crtc->mode.clock);
3491                                 planeb_clock = crtc->mode.clock;
3492                         }
3493                         sr_hdisplay = crtc->mode.hdisplay;
3494                         sr_clock = crtc->mode.clock;
3495                         sr_htotal = crtc->mode.htotal;
3496                         if (crtc->fb)
3497                                 pixel_size = crtc->fb->bits_per_pixel / 8;
3498                         else
3499                                 pixel_size = 4; /* by default */
3500                 }
3501         }
3502
3503         if (enabled <= 0)
3504                 return;
3505
3506         dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
3507                                     sr_hdisplay, sr_htotal, pixel_size);
3508 }
3509
3510 static int intel_crtc_mode_set(struct drm_crtc *crtc,
3511                                struct drm_display_mode *mode,
3512                                struct drm_display_mode *adjusted_mode,
3513                                int x, int y,
3514                                struct drm_framebuffer *old_fb)
3515 {
3516         struct drm_device *dev = crtc->dev;
3517         struct drm_i915_private *dev_priv = dev->dev_private;
3518         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3519         int pipe = intel_crtc->pipe;
3520         int plane = intel_crtc->plane;
3521         u32 fp_reg, dpll_reg;
3522         int refclk, num_connectors = 0;
3523         intel_clock_t clock, reduced_clock;
3524         u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
3525         bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
3526         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
3527         struct intel_encoder *has_edp_encoder = NULL;
3528         struct drm_mode_config *mode_config = &dev->mode_config;
3529         struct intel_encoder *encoder;
3530         const intel_limit_t *limit;
3531         int ret;
3532         struct fdi_m_n m_n = {0};
3533         u32 reg, temp;
3534         int target_clock;
3535
3536         drm_vblank_pre_modeset(dev, pipe);
3537
3538         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
3539                 if (encoder->base.crtc != crtc)
3540                         continue;
3541
3542                 switch (encoder->type) {
3543                 case INTEL_OUTPUT_LVDS:
3544                         is_lvds = true;
3545                         break;
3546                 case INTEL_OUTPUT_SDVO:
3547                 case INTEL_OUTPUT_HDMI:
3548                         is_sdvo = true;
3549                         if (encoder->needs_tv_clock)
3550                                 is_tv = true;
3551                         break;
3552                 case INTEL_OUTPUT_DVO:
3553                         is_dvo = true;
3554                         break;
3555                 case INTEL_OUTPUT_TVOUT:
3556                         is_tv = true;
3557                         break;
3558                 case INTEL_OUTPUT_ANALOG:
3559                         is_crt = true;
3560                         break;
3561                 case INTEL_OUTPUT_DISPLAYPORT:
3562                         is_dp = true;
3563                         break;
3564                 case INTEL_OUTPUT_EDP:
3565                         has_edp_encoder = encoder;
3566                         break;
3567                 }
3568
3569                 num_connectors++;
3570         }
3571
3572         if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2) {
3573                 refclk = dev_priv->lvds_ssc_freq * 1000;
3574                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3575                               refclk / 1000);
3576         } else if (IS_I9XX(dev)) {
3577                 refclk = 96000;
3578                 if (HAS_PCH_SPLIT(dev))
3579                         refclk = 120000; /* 120Mhz refclk */
3580         } else {
3581                 refclk = 48000;
3582         }
3583
3584         /*
3585          * Returns a set of divisors for the desired target clock with the given
3586          * refclk, or FALSE.  The returned values represent the clock equation:
3587          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
3588          */
3589         limit = intel_limit(crtc);
3590         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
3591         if (!ok) {
3592                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
3593                 drm_vblank_post_modeset(dev, pipe);
3594                 return -EINVAL;
3595         }
3596
3597         /* Ensure that the cursor is valid for the new mode before changing... */
3598         intel_crtc_update_cursor(crtc, true);
3599
3600         if (is_lvds && dev_priv->lvds_downclock_avail) {
3601                 has_reduced_clock = limit->find_pll(limit, crtc,
3602                                                     dev_priv->lvds_downclock,
3603                                                     refclk,
3604                                                     &reduced_clock);
3605                 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
3606                         /*
3607                          * If the different P is found, it means that we can't
3608                          * switch the display clock by using the FP0/FP1.
3609                          * In such case we will disable the LVDS downclock
3610                          * feature.
3611                          */
3612                         DRM_DEBUG_KMS("Different P is found for "
3613                                       "LVDS clock/downclock\n");
3614                         has_reduced_clock = 0;
3615                 }
3616         }
3617         /* SDVO TV has fixed PLL values depend on its clock range,
3618            this mirrors vbios setting. */
3619         if (is_sdvo && is_tv) {
3620                 if (adjusted_mode->clock >= 100000
3621                     && adjusted_mode->clock < 140500) {
3622                         clock.p1 = 2;
3623                         clock.p2 = 10;
3624                         clock.n = 3;
3625                         clock.m1 = 16;
3626                         clock.m2 = 8;
3627                 } else if (adjusted_mode->clock >= 140500
3628                            && adjusted_mode->clock <= 200000) {
3629                         clock.p1 = 1;
3630                         clock.p2 = 10;
3631                         clock.n = 6;
3632                         clock.m1 = 12;
3633                         clock.m2 = 8;
3634                 }
3635         }
3636
3637         /* FDI link */
3638         if (HAS_PCH_SPLIT(dev)) {
3639                 int lane = 0, link_bw, bpp;
3640                 /* eDP doesn't require FDI link, so just set DP M/N
3641                    according to current link config */
3642                 if (has_edp_encoder) {
3643                         target_clock = mode->clock;
3644                         intel_edp_link_config(has_edp_encoder,
3645                                               &lane, &link_bw);
3646                 } else {
3647                         /* DP over FDI requires target mode clock
3648                            instead of link clock */
3649                         if (is_dp)
3650                                 target_clock = mode->clock;
3651                         else
3652                                 target_clock = adjusted_mode->clock;
3653
3654                         /* FDI is a binary signal running at ~2.7GHz, encoding
3655                          * each output octet as 10 bits. The actual frequency
3656                          * is stored as a divider into a 100MHz clock, and the
3657                          * mode pixel clock is stored in units of 1KHz.
3658                          * Hence the bw of each lane in terms of the mode signal
3659                          * is:
3660                          */
3661                         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
3662                 }
3663
3664                 /* determine panel color depth */
3665                 temp = I915_READ(PIPECONF(pipe));
3666                 temp &= ~PIPE_BPC_MASK;
3667                 if (is_lvds) {
3668                         /* the BPC will be 6 if it is 18-bit LVDS panel */
3669                         if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
3670                                 temp |= PIPE_8BPC;
3671                         else
3672                                 temp |= PIPE_6BPC;
3673                 } else if (has_edp_encoder || (is_dp && intel_pch_has_edp(crtc))) {
3674                         switch (dev_priv->edp_bpp/3) {
3675                         case 8:
3676                                 temp |= PIPE_8BPC;
3677                                 break;
3678                         case 10:
3679                                 temp |= PIPE_10BPC;
3680                                 break;
3681                         case 6:
3682                                 temp |= PIPE_6BPC;
3683                                 break;
3684                         case 12:
3685                                 temp |= PIPE_12BPC;
3686                                 break;
3687                         }
3688                 } else
3689                         temp |= PIPE_8BPC;
3690                 I915_WRITE(PIPECONF(pipe), temp);
3691
3692                 switch (temp & PIPE_BPC_MASK) {
3693                 case PIPE_8BPC:
3694                         bpp = 24;
3695                         break;
3696                 case PIPE_10BPC:
3697                         bpp = 30;
3698                         break;
3699                 case PIPE_6BPC:
3700                         bpp = 18;
3701                         break;
3702                 case PIPE_12BPC:
3703                         bpp = 36;
3704                         break;
3705                 default:
3706                         DRM_ERROR("unknown pipe bpc value\n");
3707                         bpp = 24;
3708                 }
3709
3710                 if (!lane) {
3711                         /*
3712                          * Account for spread spectrum to avoid
3713                          * oversubscribing the link. Max center spread
3714                          * is 2.5%; use 5% for safety's sake.
3715                          */
3716                         u32 bps = target_clock * bpp * 21 / 20;
3717                         lane = bps / (link_bw * 8) + 1;
3718                 }
3719
3720                 intel_crtc->fdi_lanes = lane;
3721
3722                 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
3723         }
3724
3725         /* Ironlake: try to setup display ref clock before DPLL
3726          * enabling. This is only under driver's control after
3727          * PCH B stepping, previous chipset stepping should be
3728          * ignoring this setting.
3729          */
3730         if (HAS_PCH_SPLIT(dev)) {
3731                 temp = I915_READ(PCH_DREF_CONTROL);
3732                 /* Always enable nonspread source */
3733                 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
3734                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
3735                 temp &= ~DREF_SSC_SOURCE_MASK;
3736                 temp |= DREF_SSC_SOURCE_ENABLE;
3737                 I915_WRITE(PCH_DREF_CONTROL, temp);
3738
3739                 POSTING_READ(PCH_DREF_CONTROL);
3740                 udelay(200);
3741
3742                 if (has_edp_encoder) {
3743                         if (dev_priv->lvds_use_ssc) {
3744                                 temp |= DREF_SSC1_ENABLE;
3745                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3746
3747                                 POSTING_READ(PCH_DREF_CONTROL);
3748                                 udelay(200);
3749
3750                                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
3751                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
3752                         } else {
3753                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
3754                         }
3755                         I915_WRITE(PCH_DREF_CONTROL, temp);
3756                 }
3757         }
3758
3759         if (IS_PINEVIEW(dev)) {
3760                 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
3761                 if (has_reduced_clock)
3762                         fp2 = (1 << reduced_clock.n) << 16 |
3763                                 reduced_clock.m1 << 8 | reduced_clock.m2;
3764         } else {
3765                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
3766                 if (has_reduced_clock)
3767                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
3768                                 reduced_clock.m2;
3769         }
3770
3771         dpll = 0;
3772         if (!HAS_PCH_SPLIT(dev))
3773                 dpll = DPLL_VGA_MODE_DIS;
3774
3775         if (IS_I9XX(dev)) {
3776                 if (is_lvds)
3777                         dpll |= DPLLB_MODE_LVDS;
3778                 else
3779                         dpll |= DPLLB_MODE_DAC_SERIAL;
3780                 if (is_sdvo) {
3781                         int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
3782                         if (pixel_multiplier > 1) {
3783                                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3784                                         dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3785                                 else if (HAS_PCH_SPLIT(dev))
3786                                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
3787                         }
3788                         dpll |= DPLL_DVO_HIGH_SPEED;
3789                 }
3790                 if (is_dp)
3791                         dpll |= DPLL_DVO_HIGH_SPEED;
3792
3793                 /* compute bitmask from p1 value */
3794                 if (IS_PINEVIEW(dev))
3795                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3796                 else {
3797                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3798                         /* also FPA1 */
3799                         if (HAS_PCH_SPLIT(dev))
3800                                 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3801                         if (IS_G4X(dev) && has_reduced_clock)
3802                                 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3803                 }
3804                 switch (clock.p2) {
3805                 case 5:
3806                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3807                         break;
3808                 case 7:
3809                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3810                         break;
3811                 case 10:
3812                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3813                         break;
3814                 case 14:
3815                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3816                         break;
3817                 }
3818                 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev))
3819                         dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3820         } else {
3821                 if (is_lvds) {
3822                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3823                 } else {
3824                         if (clock.p1 == 2)
3825                                 dpll |= PLL_P1_DIVIDE_BY_TWO;
3826                         else
3827                                 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3828                         if (clock.p2 == 4)
3829                                 dpll |= PLL_P2_DIVIDE_BY_4;
3830                 }
3831         }
3832
3833         if (is_sdvo && is_tv)
3834                 dpll |= PLL_REF_INPUT_TVCLKINBC;
3835         else if (is_tv)
3836                 /* XXX: just matching BIOS for now */
3837                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
3838                 dpll |= 3;
3839         else if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2)
3840                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3841         else
3842                 dpll |= PLL_REF_INPUT_DREFCLK;
3843
3844         /* setup pipeconf */
3845         pipeconf = I915_READ(PIPECONF(pipe));
3846
3847         /* Set up the display plane register */
3848         dspcntr = DISPPLANE_GAMMA_ENABLE;
3849
3850         /* Ironlake's plane is forced to pipe, bit 24 is to
3851            enable color space conversion */
3852         if (!HAS_PCH_SPLIT(dev)) {
3853                 if (pipe == 0)
3854                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3855                 else
3856                         dspcntr |= DISPPLANE_SEL_PIPE_B;
3857         }
3858
3859         if (pipe == 0 && !IS_I965G(dev)) {
3860                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3861                  * core speed.
3862                  *
3863                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3864                  * pipe == 0 check?
3865                  */
3866                 if (mode->clock >
3867                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
3868                         pipeconf |= PIPECONF_DOUBLE_WIDE;
3869                 else
3870                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
3871         }
3872
3873         dspcntr |= DISPLAY_PLANE_ENABLE;
3874         pipeconf |= PIPECONF_ENABLE;
3875         dpll |= DPLL_VCO_ENABLE;
3876
3877         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
3878         drm_mode_debug_printmodeline(mode);
3879
3880         /* assign to Ironlake registers */
3881         if (HAS_PCH_SPLIT(dev)) {
3882                 fp_reg = PCH_FP0(pipe);
3883                 dpll_reg = PCH_DPLL(pipe);
3884         } else {
3885                 fp_reg = FP0(pipe);
3886                 dpll_reg = DPLL(pipe);
3887         }
3888
3889         if (!has_edp_encoder) {
3890                 I915_WRITE(fp_reg, fp);
3891                 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
3892
3893                 POSTING_READ(dpll_reg);
3894                 udelay(150);
3895         }
3896
3897         /* enable transcoder DPLL */
3898         if (HAS_PCH_CPT(dev)) {
3899                 temp = I915_READ(PCH_DPLL_SEL);
3900                 if (pipe == 0)
3901                         temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL;
3902                 else
3903                         temp |= TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL;
3904                 I915_WRITE(PCH_DPLL_SEL, temp);
3905
3906                 POSTING_READ(PCH_DPLL_SEL);
3907                 udelay(150);
3908         }
3909
3910         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3911          * This is an exception to the general rule that mode_set doesn't turn
3912          * things on.
3913          */
3914         if (is_lvds) {
3915                 reg = LVDS;
3916                 if (HAS_PCH_SPLIT(dev))
3917                         reg = PCH_LVDS;
3918
3919                 temp = I915_READ(reg);
3920                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3921                 if (pipe == 1) {
3922                         if (HAS_PCH_CPT(dev))
3923                                 temp |= PORT_TRANS_B_SEL_CPT;
3924                         else
3925                                 temp |= LVDS_PIPEB_SELECT;
3926                 } else {
3927                         if (HAS_PCH_CPT(dev))
3928                                 temp &= ~PORT_TRANS_SEL_MASK;
3929                         else
3930                                 temp &= ~LVDS_PIPEB_SELECT;
3931                 }
3932                 /* set the corresponsding LVDS_BORDER bit */
3933                 temp |= dev_priv->lvds_border_bits;
3934                 /* Set the B0-B3 data pairs corresponding to whether we're going to
3935                  * set the DPLLs for dual-channel mode or not.
3936                  */
3937                 if (clock.p2 == 7)
3938                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3939                 else
3940                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3941
3942                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3943                  * appropriately here, but we need to look more thoroughly into how
3944                  * panels behave in the two modes.
3945                  */
3946                 /* set the dithering flag on non-PCH LVDS as needed */
3947                 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) {
3948                         if (dev_priv->lvds_dither)
3949                                 temp |= LVDS_ENABLE_DITHER;
3950                         else
3951                                 temp &= ~LVDS_ENABLE_DITHER;
3952                 }
3953                 I915_WRITE(reg, temp);
3954         }
3955
3956         /* set the dithering flag and clear for anything other than a panel. */
3957         if (HAS_PCH_SPLIT(dev)) {
3958                 pipeconf &= ~PIPECONF_DITHER_EN;
3959                 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
3960                 if (dev_priv->lvds_dither && (is_lvds || has_edp_encoder)) {
3961                         pipeconf |= PIPECONF_DITHER_EN;
3962                         pipeconf |= PIPECONF_DITHER_TYPE_ST1;
3963                 }
3964         }
3965
3966         if (is_dp)
3967                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
3968         else if (HAS_PCH_SPLIT(dev)) {
3969                 /* For non-DP output, clear any trans DP clock recovery setting.*/
3970                 if (pipe == 0) {
3971                         I915_WRITE(TRANSA_DATA_M1, 0);
3972                         I915_WRITE(TRANSA_DATA_N1, 0);
3973                         I915_WRITE(TRANSA_DP_LINK_M1, 0);
3974                         I915_WRITE(TRANSA_DP_LINK_N1, 0);
3975                 } else {
3976                         I915_WRITE(TRANSB_DATA_M1, 0);
3977                         I915_WRITE(TRANSB_DATA_N1, 0);
3978                         I915_WRITE(TRANSB_DP_LINK_M1, 0);
3979                         I915_WRITE(TRANSB_DP_LINK_N1, 0);
3980                 }
3981         }
3982
3983         if (!has_edp_encoder) {
3984                 I915_WRITE(fp_reg, fp);
3985                 I915_WRITE(dpll_reg, dpll);
3986
3987                 /* Wait for the clocks to stabilize. */
3988                 POSTING_READ(dpll_reg);
3989                 udelay(150);
3990
3991                 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) {
3992                         temp = 0;
3993                         if (is_sdvo) {
3994                                 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
3995                                 if (temp > 1)
3996                                         temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
3997                                 else
3998                                         temp = 0;
3999                         }
4000                         I915_WRITE(DPLL_MD(pipe), temp);
4001                 } else {
4002                         /* write it again -- the BIOS does, after all */
4003                         I915_WRITE(dpll_reg, dpll);
4004                 }
4005
4006                 /* Wait for the clocks to stabilize. */
4007                 POSTING_READ(dpll_reg);
4008                 udelay(150);
4009         }
4010
4011         intel_crtc->lowfreq_avail = false;
4012         if (is_lvds && has_reduced_clock && i915_powersave) {
4013                 I915_WRITE(fp_reg + 4, fp2);
4014                 intel_crtc->lowfreq_avail = true;
4015                 if (HAS_PIPE_CXSR(dev)) {
4016                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4017                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4018                 }
4019         } else {
4020                 I915_WRITE(fp_reg + 4, fp);
4021                 if (HAS_PIPE_CXSR(dev)) {
4022                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4023                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4024                 }
4025         }
4026
4027         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4028                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4029                 /* the chip adds 2 halflines automatically */
4030                 adjusted_mode->crtc_vdisplay -= 1;
4031                 adjusted_mode->crtc_vtotal -= 1;
4032                 adjusted_mode->crtc_vblank_start -= 1;
4033                 adjusted_mode->crtc_vblank_end -= 1;
4034                 adjusted_mode->crtc_vsync_end -= 1;
4035                 adjusted_mode->crtc_vsync_start -= 1;
4036         } else
4037                 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
4038
4039         I915_WRITE(HTOTAL(pipe),
4040                    (adjusted_mode->crtc_hdisplay - 1) |
4041                    ((adjusted_mode->crtc_htotal - 1) << 16));
4042         I915_WRITE(HBLANK(pipe),
4043                    (adjusted_mode->crtc_hblank_start - 1) |
4044                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4045         I915_WRITE(HSYNC(pipe),
4046                    (adjusted_mode->crtc_hsync_start - 1) |
4047                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4048
4049         I915_WRITE(VTOTAL(pipe),
4050                    (adjusted_mode->crtc_vdisplay - 1) |
4051                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4052         I915_WRITE(VBLANK(pipe),
4053                    (adjusted_mode->crtc_vblank_start - 1) |
4054                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4055         I915_WRITE(VSYNC(pipe),
4056                    (adjusted_mode->crtc_vsync_start - 1) |
4057                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4058
4059         /* pipesrc and dspsize control the size that is scaled from,
4060          * which should always be the user's requested size.
4061          */
4062         if (!HAS_PCH_SPLIT(dev)) {
4063                 I915_WRITE(DSPSIZE(plane),
4064                            ((mode->vdisplay - 1) << 16) |
4065                            (mode->hdisplay - 1));
4066                 I915_WRITE(DSPPOS(plane), 0);
4067         }
4068         I915_WRITE(PIPESRC(pipe),
4069                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4070
4071         if (HAS_PCH_SPLIT(dev)) {
4072                 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
4073                 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
4074                 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
4075                 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
4076
4077                 if (has_edp_encoder) {
4078                         ironlake_set_pll_edp(crtc, adjusted_mode->clock);
4079                 } else {
4080                         /* enable FDI RX PLL too */
4081                         reg = FDI_RX_CTL(pipe);
4082                         temp = I915_READ(reg);
4083                         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
4084
4085                         POSTING_READ(reg);
4086                         udelay(200);
4087
4088                         /* enable FDI TX PLL too */
4089                         reg = FDI_TX_CTL(pipe);
4090                         temp = I915_READ(reg);
4091                         I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
4092
4093                         /* enable FDI RX PCDCLK */
4094                         reg = FDI_RX_CTL(pipe);
4095                         temp = I915_READ(reg);
4096                         I915_WRITE(reg, temp | FDI_PCDCLK);
4097
4098                         POSTING_READ(reg);
4099                         udelay(200);
4100                 }
4101         }
4102
4103         I915_WRITE(PIPECONF(pipe), pipeconf);
4104         POSTING_READ(PIPECONF(pipe));
4105
4106         intel_wait_for_vblank(dev, pipe);
4107
4108         if (IS_IRONLAKE(dev)) {
4109                 /* enable address swizzle for tiling buffer */
4110                 temp = I915_READ(DISP_ARB_CTL);
4111                 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
4112         }
4113
4114         I915_WRITE(DSPCNTR(plane), dspcntr);
4115
4116         ret = intel_pipe_set_base(crtc, x, y, old_fb);
4117
4118         intel_update_watermarks(dev);
4119
4120         drm_vblank_post_modeset(dev, pipe);
4121
4122         return ret;
4123 }
4124
4125 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4126 void intel_crtc_load_lut(struct drm_crtc *crtc)
4127 {
4128         struct drm_device *dev = crtc->dev;
4129         struct drm_i915_private *dev_priv = dev->dev_private;
4130         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4131         int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
4132         int i;
4133
4134         /* The clocks have to be on to load the palette. */
4135         if (!crtc->enabled)
4136                 return;
4137
4138         /* use legacy palette for Ironlake */
4139         if (HAS_PCH_SPLIT(dev))
4140                 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
4141                                                    LGC_PALETTE_B;
4142
4143         for (i = 0; i < 256; i++) {
4144                 I915_WRITE(palreg + 4 * i,
4145                            (intel_crtc->lut_r[i] << 16) |
4146                            (intel_crtc->lut_g[i] << 8) |
4147                            intel_crtc->lut_b[i]);
4148         }
4149 }
4150
4151 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
4152 {
4153         struct drm_device *dev = crtc->dev;
4154         struct drm_i915_private *dev_priv = dev->dev_private;
4155         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4156         bool visible = base != 0;
4157         u32 cntl;
4158
4159         if (intel_crtc->cursor_visible == visible)
4160                 return;
4161
4162         cntl = I915_READ(CURACNTR);
4163         if (visible) {
4164                 /* On these chipsets we can only modify the base whilst
4165                  * the cursor is disabled.
4166                  */
4167                 I915_WRITE(CURABASE, base);
4168
4169                 cntl &= ~(CURSOR_FORMAT_MASK);
4170                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
4171                 cntl |= CURSOR_ENABLE |
4172                         CURSOR_GAMMA_ENABLE |
4173                         CURSOR_FORMAT_ARGB;
4174         } else
4175                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
4176         I915_WRITE(CURACNTR, cntl);
4177
4178         intel_crtc->cursor_visible = visible;
4179 }
4180
4181 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
4182 {
4183         struct drm_device *dev = crtc->dev;
4184         struct drm_i915_private *dev_priv = dev->dev_private;
4185         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4186         int pipe = intel_crtc->pipe;
4187         bool visible = base != 0;
4188
4189         if (intel_crtc->cursor_visible != visible) {
4190                 uint32_t cntl = I915_READ(pipe == 0 ? CURACNTR : CURBCNTR);
4191                 if (base) {
4192                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
4193                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4194                         cntl |= pipe << 28; /* Connect to correct pipe */
4195                 } else {
4196                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4197                         cntl |= CURSOR_MODE_DISABLE;
4198                 }
4199                 I915_WRITE(pipe == 0 ? CURACNTR : CURBCNTR, cntl);
4200
4201                 intel_crtc->cursor_visible = visible;
4202         }
4203         /* and commit changes on next vblank */
4204         I915_WRITE(pipe == 0 ? CURABASE : CURBBASE, base);
4205 }
4206
4207 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
4208 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
4209                                      bool on)
4210 {
4211         struct drm_device *dev = crtc->dev;
4212         struct drm_i915_private *dev_priv = dev->dev_private;
4213         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4214         int pipe = intel_crtc->pipe;
4215         int x = intel_crtc->cursor_x;
4216         int y = intel_crtc->cursor_y;
4217         u32 base, pos;
4218         bool visible;
4219
4220         pos = 0;
4221
4222         if (on && crtc->enabled && crtc->fb) {
4223                 base = intel_crtc->cursor_addr;
4224                 if (x > (int) crtc->fb->width)
4225                         base = 0;
4226
4227                 if (y > (int) crtc->fb->height)
4228                         base = 0;
4229         } else
4230                 base = 0;
4231
4232         if (x < 0) {
4233                 if (x + intel_crtc->cursor_width < 0)
4234                         base = 0;
4235
4236                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
4237                 x = -x;
4238         }
4239         pos |= x << CURSOR_X_SHIFT;
4240
4241         if (y < 0) {
4242                 if (y + intel_crtc->cursor_height < 0)
4243                         base = 0;
4244
4245                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
4246                 y = -y;
4247         }
4248         pos |= y << CURSOR_Y_SHIFT;
4249
4250         visible = base != 0;
4251         if (!visible && !intel_crtc->cursor_visible)
4252                 return;
4253
4254         I915_WRITE(pipe == 0 ? CURAPOS : CURBPOS, pos);
4255         if (IS_845G(dev) || IS_I865G(dev))
4256                 i845_update_cursor(crtc, base);
4257         else
4258                 i9xx_update_cursor(crtc, base);
4259
4260         if (visible)
4261                 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
4262 }
4263
4264 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
4265                                  struct drm_file *file_priv,
4266                                  uint32_t handle,
4267                                  uint32_t width, uint32_t height)
4268 {
4269         struct drm_device *dev = crtc->dev;
4270         struct drm_i915_private *dev_priv = dev->dev_private;
4271         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4272         struct drm_gem_object *bo;
4273         struct drm_i915_gem_object *obj_priv;
4274         uint32_t addr;
4275         int ret;
4276
4277         DRM_DEBUG_KMS("\n");
4278
4279         /* if we want to turn off the cursor ignore width and height */
4280         if (!handle) {
4281                 DRM_DEBUG_KMS("cursor off\n");
4282                 addr = 0;
4283                 bo = NULL;
4284                 mutex_lock(&dev->struct_mutex);
4285                 goto finish;
4286         }
4287
4288         /* Currently we only support 64x64 cursors */
4289         if (width != 64 || height != 64) {
4290                 DRM_ERROR("we currently only support 64x64 cursors\n");
4291                 return -EINVAL;
4292         }
4293
4294         bo = drm_gem_object_lookup(dev, file_priv, handle);
4295         if (!bo)
4296                 return -ENOENT;
4297
4298         obj_priv = to_intel_bo(bo);
4299
4300         if (bo->size < width * height * 4) {
4301                 DRM_ERROR("buffer is to small\n");
4302                 ret = -ENOMEM;
4303                 goto fail;
4304         }
4305
4306         /* we only need to pin inside GTT if cursor is non-phy */
4307         mutex_lock(&dev->struct_mutex);
4308         if (!dev_priv->info->cursor_needs_physical) {
4309                 ret = i915_gem_object_pin(bo, PAGE_SIZE);
4310                 if (ret) {
4311                         DRM_ERROR("failed to pin cursor bo\n");
4312                         goto fail_locked;
4313                 }
4314
4315                 ret = i915_gem_object_set_to_gtt_domain(bo, 0);
4316                 if (ret) {
4317                         DRM_ERROR("failed to move cursor bo into the GTT\n");
4318                         goto fail_unpin;
4319                 }
4320
4321                 addr = obj_priv->gtt_offset;
4322         } else {
4323                 int align = IS_I830(dev) ? 16 * 1024 : 256;
4324                 ret = i915_gem_attach_phys_object(dev, bo,
4325                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
4326                                                   align);
4327                 if (ret) {
4328                         DRM_ERROR("failed to attach phys object\n");
4329                         goto fail_locked;
4330                 }
4331                 addr = obj_priv->phys_obj->handle->busaddr;
4332         }
4333
4334         if (!IS_I9XX(dev))
4335                 I915_WRITE(CURSIZE, (height << 12) | width);
4336
4337  finish:
4338         if (intel_crtc->cursor_bo) {
4339                 if (dev_priv->info->cursor_needs_physical) {
4340                         if (intel_crtc->cursor_bo != bo)
4341                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
4342                 } else
4343                         i915_gem_object_unpin(intel_crtc->cursor_bo);
4344                 drm_gem_object_unreference(intel_crtc->cursor_bo);
4345         }
4346
4347         mutex_unlock(&dev->struct_mutex);
4348
4349         intel_crtc->cursor_addr = addr;
4350         intel_crtc->cursor_bo = bo;
4351         intel_crtc->cursor_width = width;
4352         intel_crtc->cursor_height = height;
4353
4354         intel_crtc_update_cursor(crtc, true);
4355
4356         return 0;
4357 fail_unpin:
4358         i915_gem_object_unpin(bo);
4359 fail_locked:
4360         mutex_unlock(&dev->struct_mutex);
4361 fail:
4362         drm_gem_object_unreference_unlocked(bo);
4363         return ret;
4364 }
4365
4366 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
4367 {
4368         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4369
4370         intel_crtc->cursor_x = x;
4371         intel_crtc->cursor_y = y;
4372
4373         intel_crtc_update_cursor(crtc, true);
4374
4375         return 0;
4376 }
4377
4378 /** Sets the color ramps on behalf of RandR */
4379 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
4380                                  u16 blue, int regno)
4381 {
4382         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4383
4384         intel_crtc->lut_r[regno] = red >> 8;
4385         intel_crtc->lut_g[regno] = green >> 8;
4386         intel_crtc->lut_b[regno] = blue >> 8;
4387 }
4388
4389 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
4390                              u16 *blue, int regno)
4391 {
4392         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4393
4394         *red = intel_crtc->lut_r[regno] << 8;
4395         *green = intel_crtc->lut_g[regno] << 8;
4396         *blue = intel_crtc->lut_b[regno] << 8;
4397 }
4398
4399 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
4400                                  u16 *blue, uint32_t start, uint32_t size)
4401 {
4402         int end = (start + size > 256) ? 256 : start + size, i;
4403         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4404
4405         for (i = start; i < end; i++) {
4406                 intel_crtc->lut_r[i] = red[i] >> 8;
4407                 intel_crtc->lut_g[i] = green[i] >> 8;
4408                 intel_crtc->lut_b[i] = blue[i] >> 8;
4409         }
4410
4411         intel_crtc_load_lut(crtc);
4412 }
4413
4414 /**
4415  * Get a pipe with a simple mode set on it for doing load-based monitor
4416  * detection.
4417  *
4418  * It will be up to the load-detect code to adjust the pipe as appropriate for
4419  * its requirements.  The pipe will be connected to no other encoders.
4420  *
4421  * Currently this code will only succeed if there is a pipe with no encoders
4422  * configured for it.  In the future, it could choose to temporarily disable
4423  * some outputs to free up a pipe for its use.
4424  *
4425  * \return crtc, or NULL if no pipes are available.
4426  */
4427
4428 /* VESA 640x480x72Hz mode to set on the pipe */
4429 static struct drm_display_mode load_detect_mode = {
4430         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
4431                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
4432 };
4433
4434 struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
4435                                             struct drm_connector *connector,
4436                                             struct drm_display_mode *mode,
4437                                             int *dpms_mode)
4438 {
4439         struct intel_crtc *intel_crtc;
4440         struct drm_crtc *possible_crtc;
4441         struct drm_crtc *supported_crtc =NULL;
4442         struct drm_encoder *encoder = &intel_encoder->base;
4443         struct drm_crtc *crtc = NULL;
4444         struct drm_device *dev = encoder->dev;
4445         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4446         struct drm_crtc_helper_funcs *crtc_funcs;
4447         int i = -1;
4448
4449         /*
4450          * Algorithm gets a little messy:
4451          *   - if the connector already has an assigned crtc, use it (but make
4452          *     sure it's on first)
4453          *   - try to find the first unused crtc that can drive this connector,
4454          *     and use that if we find one
4455          *   - if there are no unused crtcs available, try to use the first
4456          *     one we found that supports the connector
4457          */
4458
4459         /* See if we already have a CRTC for this connector */
4460         if (encoder->crtc) {
4461                 crtc = encoder->crtc;
4462                 /* Make sure the crtc and connector are running */
4463                 intel_crtc = to_intel_crtc(crtc);
4464                 *dpms_mode = intel_crtc->dpms_mode;
4465                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4466                         crtc_funcs = crtc->helper_private;
4467                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4468                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
4469                 }
4470                 return crtc;
4471         }
4472
4473         /* Find an unused one (if possible) */
4474         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
4475                 i++;
4476                 if (!(encoder->possible_crtcs & (1 << i)))
4477                         continue;
4478                 if (!possible_crtc->enabled) {
4479                         crtc = possible_crtc;
4480                         break;
4481                 }
4482                 if (!supported_crtc)
4483                         supported_crtc = possible_crtc;
4484         }
4485
4486         /*
4487          * If we didn't find an unused CRTC, don't use any.
4488          */
4489         if (!crtc) {
4490                 return NULL;
4491         }
4492
4493         encoder->crtc = crtc;
4494         connector->encoder = encoder;
4495         intel_encoder->load_detect_temp = true;
4496
4497         intel_crtc = to_intel_crtc(crtc);
4498         *dpms_mode = intel_crtc->dpms_mode;
4499
4500         if (!crtc->enabled) {
4501                 if (!mode)
4502                         mode = &load_detect_mode;
4503                 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
4504         } else {
4505                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4506                         crtc_funcs = crtc->helper_private;
4507                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4508                 }
4509
4510                 /* Add this connector to the crtc */
4511                 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
4512                 encoder_funcs->commit(encoder);
4513         }
4514         /* let the connector get through one full cycle before testing */
4515         intel_wait_for_vblank(dev, intel_crtc->pipe);
4516
4517         return crtc;
4518 }
4519
4520 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
4521                                     struct drm_connector *connector, int dpms_mode)
4522 {
4523         struct drm_encoder *encoder = &intel_encoder->base;
4524         struct drm_device *dev = encoder->dev;
4525         struct drm_crtc *crtc = encoder->crtc;
4526         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4527         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
4528
4529         if (intel_encoder->load_detect_temp) {
4530                 encoder->crtc = NULL;
4531                 connector->encoder = NULL;
4532                 intel_encoder->load_detect_temp = false;
4533                 crtc->enabled = drm_helper_crtc_in_use(crtc);
4534                 drm_helper_disable_unused_functions(dev);
4535         }
4536
4537         /* Switch crtc and encoder back off if necessary */
4538         if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
4539                 if (encoder->crtc == crtc)
4540                         encoder_funcs->dpms(encoder, dpms_mode);
4541                 crtc_funcs->dpms(crtc, dpms_mode);
4542         }
4543 }
4544
4545 /* Returns the clock of the currently programmed mode of the given pipe. */
4546 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
4547 {
4548         struct drm_i915_private *dev_priv = dev->dev_private;
4549         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4550         int pipe = intel_crtc->pipe;
4551         u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
4552         u32 fp;
4553         intel_clock_t clock;
4554
4555         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
4556                 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
4557         else
4558                 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
4559
4560         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
4561         if (IS_PINEVIEW(dev)) {
4562                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
4563                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
4564         } else {
4565                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
4566                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
4567         }
4568
4569         if (IS_I9XX(dev)) {
4570                 if (IS_PINEVIEW(dev))
4571                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
4572                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
4573                 else
4574                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
4575                                DPLL_FPA01_P1_POST_DIV_SHIFT);
4576
4577                 switch (dpll & DPLL_MODE_MASK) {
4578                 case DPLLB_MODE_DAC_SERIAL:
4579                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
4580                                 5 : 10;
4581                         break;
4582                 case DPLLB_MODE_LVDS:
4583                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
4584                                 7 : 14;
4585                         break;
4586                 default:
4587                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
4588                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
4589                         return 0;
4590                 }
4591
4592                 /* XXX: Handle the 100Mhz refclk */
4593                 intel_clock(dev, 96000, &clock);
4594         } else {
4595                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
4596
4597                 if (is_lvds) {
4598                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
4599                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
4600                         clock.p2 = 14;
4601
4602                         if ((dpll & PLL_REF_INPUT_MASK) ==
4603                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
4604                                 /* XXX: might not be 66MHz */
4605                                 intel_clock(dev, 66000, &clock);
4606                         } else
4607                                 intel_clock(dev, 48000, &clock);
4608                 } else {
4609                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
4610                                 clock.p1 = 2;
4611                         else {
4612                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
4613                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
4614                         }
4615                         if (dpll & PLL_P2_DIVIDE_BY_4)
4616                                 clock.p2 = 4;
4617                         else
4618                                 clock.p2 = 2;
4619
4620                         intel_clock(dev, 48000, &clock);
4621                 }
4622         }
4623
4624         /* XXX: It would be nice to validate the clocks, but we can't reuse
4625          * i830PllIsValid() because it relies on the xf86_config connector
4626          * configuration being accurate, which it isn't necessarily.
4627          */
4628
4629         return clock.dot;
4630 }
4631
4632 /** Returns the currently programmed mode of the given pipe. */
4633 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
4634                                              struct drm_crtc *crtc)
4635 {
4636         struct drm_i915_private *dev_priv = dev->dev_private;
4637         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4638         int pipe = intel_crtc->pipe;
4639         struct drm_display_mode *mode;
4640         int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
4641         int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
4642         int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
4643         int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
4644
4645         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
4646         if (!mode)
4647                 return NULL;
4648
4649         mode->clock = intel_crtc_clock_get(dev, crtc);
4650         mode->hdisplay = (htot & 0xffff) + 1;
4651         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
4652         mode->hsync_start = (hsync & 0xffff) + 1;
4653         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
4654         mode->vdisplay = (vtot & 0xffff) + 1;
4655         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
4656         mode->vsync_start = (vsync & 0xffff) + 1;
4657         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
4658
4659         drm_mode_set_name(mode);
4660         drm_mode_set_crtcinfo(mode, 0);
4661
4662         return mode;
4663 }
4664
4665 #define GPU_IDLE_TIMEOUT 500 /* ms */
4666
4667 /* When this timer fires, we've been idle for awhile */
4668 static void intel_gpu_idle_timer(unsigned long arg)
4669 {
4670         struct drm_device *dev = (struct drm_device *)arg;
4671         drm_i915_private_t *dev_priv = dev->dev_private;
4672
4673         DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
4674
4675         dev_priv->busy = false;
4676
4677         queue_work(dev_priv->wq, &dev_priv->idle_work);
4678 }
4679
4680 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
4681
4682 static void intel_crtc_idle_timer(unsigned long arg)
4683 {
4684         struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
4685         struct drm_crtc *crtc = &intel_crtc->base;
4686         drm_i915_private_t *dev_priv = crtc->dev->dev_private;
4687
4688         DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
4689
4690         intel_crtc->busy = false;
4691
4692         queue_work(dev_priv->wq, &dev_priv->idle_work);
4693 }
4694
4695 static void intel_increase_pllclock(struct drm_crtc *crtc)
4696 {
4697         struct drm_device *dev = crtc->dev;
4698         drm_i915_private_t *dev_priv = dev->dev_private;
4699         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4700         int pipe = intel_crtc->pipe;
4701         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4702         int dpll = I915_READ(dpll_reg);
4703
4704         if (HAS_PCH_SPLIT(dev))
4705                 return;
4706
4707         if (!dev_priv->lvds_downclock_avail)
4708                 return;
4709
4710         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
4711                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
4712
4713                 /* Unlock panel regs */
4714                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
4715                            PANEL_UNLOCK_REGS);
4716
4717                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
4718                 I915_WRITE(dpll_reg, dpll);
4719                 dpll = I915_READ(dpll_reg);
4720                 intel_wait_for_vblank(dev, pipe);
4721                 dpll = I915_READ(dpll_reg);
4722                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
4723                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
4724
4725                 /* ...and lock them again */
4726                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4727         }
4728
4729         /* Schedule downclock */
4730         mod_timer(&intel_crtc->idle_timer, jiffies +
4731                   msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4732 }
4733
4734 static void intel_decrease_pllclock(struct drm_crtc *crtc)
4735 {
4736         struct drm_device *dev = crtc->dev;
4737         drm_i915_private_t *dev_priv = dev->dev_private;
4738         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4739         int pipe = intel_crtc->pipe;
4740         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4741         int dpll = I915_READ(dpll_reg);
4742
4743         if (HAS_PCH_SPLIT(dev))
4744                 return;
4745
4746         if (!dev_priv->lvds_downclock_avail)
4747                 return;
4748
4749         /*
4750          * Since this is called by a timer, we should never get here in
4751          * the manual case.
4752          */
4753         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
4754                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
4755
4756                 /* Unlock panel regs */
4757                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
4758                            PANEL_UNLOCK_REGS);
4759
4760                 dpll |= DISPLAY_RATE_SELECT_FPA1;
4761                 I915_WRITE(dpll_reg, dpll);
4762                 dpll = I915_READ(dpll_reg);
4763                 intel_wait_for_vblank(dev, pipe);
4764                 dpll = I915_READ(dpll_reg);
4765                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
4766                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
4767
4768                 /* ...and lock them again */
4769                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4770         }
4771
4772 }
4773
4774 /**
4775  * intel_idle_update - adjust clocks for idleness
4776  * @work: work struct
4777  *
4778  * Either the GPU or display (or both) went idle.  Check the busy status
4779  * here and adjust the CRTC and GPU clocks as necessary.
4780  */
4781 static void intel_idle_update(struct work_struct *work)
4782 {
4783         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
4784                                                     idle_work);
4785         struct drm_device *dev = dev_priv->dev;
4786         struct drm_crtc *crtc;
4787         struct intel_crtc *intel_crtc;
4788         int enabled = 0;
4789
4790         if (!i915_powersave)
4791                 return;
4792
4793         mutex_lock(&dev->struct_mutex);
4794
4795         i915_update_gfx_val(dev_priv);
4796
4797         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4798                 /* Skip inactive CRTCs */
4799                 if (!crtc->fb)
4800                         continue;
4801
4802                 enabled++;
4803                 intel_crtc = to_intel_crtc(crtc);
4804                 if (!intel_crtc->busy)
4805                         intel_decrease_pllclock(crtc);
4806         }
4807
4808         if ((enabled == 1) && (IS_I945G(dev) || IS_I945GM(dev))) {
4809                 DRM_DEBUG_DRIVER("enable memory self refresh on 945\n");
4810                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4811         }
4812
4813         mutex_unlock(&dev->struct_mutex);
4814 }
4815
4816 /**
4817  * intel_mark_busy - mark the GPU and possibly the display busy
4818  * @dev: drm device
4819  * @obj: object we're operating on
4820  *
4821  * Callers can use this function to indicate that the GPU is busy processing
4822  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
4823  * buffer), we'll also mark the display as busy, so we know to increase its
4824  * clock frequency.
4825  */
4826 void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
4827 {
4828         drm_i915_private_t *dev_priv = dev->dev_private;
4829         struct drm_crtc *crtc = NULL;
4830         struct intel_framebuffer *intel_fb;
4831         struct intel_crtc *intel_crtc;
4832
4833         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4834                 return;
4835
4836         if (!dev_priv->busy) {
4837                 if (IS_I945G(dev) || IS_I945GM(dev)) {
4838                         u32 fw_blc_self;
4839
4840                         DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4841                         fw_blc_self = I915_READ(FW_BLC_SELF);
4842                         fw_blc_self &= ~FW_BLC_SELF_EN;
4843                         I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4844                 }
4845                 dev_priv->busy = true;
4846         } else
4847                 mod_timer(&dev_priv->idle_timer, jiffies +
4848                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
4849
4850         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4851                 if (!crtc->fb)
4852                         continue;
4853
4854                 intel_crtc = to_intel_crtc(crtc);
4855                 intel_fb = to_intel_framebuffer(crtc->fb);
4856                 if (intel_fb->obj == obj) {
4857                         if (!intel_crtc->busy) {
4858                                 if (IS_I945G(dev) || IS_I945GM(dev)) {
4859                                         u32 fw_blc_self;
4860
4861                                         DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4862                                         fw_blc_self = I915_READ(FW_BLC_SELF);
4863                                         fw_blc_self &= ~FW_BLC_SELF_EN;
4864                                         I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4865                                 }
4866                                 /* Non-busy -> busy, upclock */
4867                                 intel_increase_pllclock(crtc);
4868                                 intel_crtc->busy = true;
4869                         } else {
4870                                 /* Busy -> busy, put off timer */
4871                                 mod_timer(&intel_crtc->idle_timer, jiffies +
4872                                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4873                         }
4874                 }
4875         }
4876 }
4877
4878 static void intel_crtc_destroy(struct drm_crtc *crtc)
4879 {
4880         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4881         struct drm_device *dev = crtc->dev;
4882         struct intel_unpin_work *work;
4883         unsigned long flags;
4884
4885         spin_lock_irqsave(&dev->event_lock, flags);
4886         work = intel_crtc->unpin_work;
4887         intel_crtc->unpin_work = NULL;
4888         spin_unlock_irqrestore(&dev->event_lock, flags);
4889
4890         if (work) {
4891                 cancel_work_sync(&work->work);
4892                 kfree(work);
4893         }
4894
4895         drm_crtc_cleanup(crtc);
4896
4897         kfree(intel_crtc);
4898 }
4899
4900 static void intel_unpin_work_fn(struct work_struct *__work)
4901 {
4902         struct intel_unpin_work *work =
4903                 container_of(__work, struct intel_unpin_work, work);
4904
4905         mutex_lock(&work->dev->struct_mutex);
4906         i915_gem_object_unpin(work->old_fb_obj);
4907         drm_gem_object_unreference(work->pending_flip_obj);
4908         drm_gem_object_unreference(work->old_fb_obj);
4909         mutex_unlock(&work->dev->struct_mutex);
4910         kfree(work);
4911 }
4912
4913 static void do_intel_finish_page_flip(struct drm_device *dev,
4914                                       struct drm_crtc *crtc)
4915 {
4916         drm_i915_private_t *dev_priv = dev->dev_private;
4917         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4918         struct intel_unpin_work *work;
4919         struct drm_i915_gem_object *obj_priv;
4920         struct drm_pending_vblank_event *e;
4921         struct timeval now;
4922         unsigned long flags;
4923
4924         /* Ignore early vblank irqs */
4925         if (intel_crtc == NULL)
4926                 return;
4927
4928         spin_lock_irqsave(&dev->event_lock, flags);
4929         work = intel_crtc->unpin_work;
4930         if (work == NULL || !work->pending) {
4931                 spin_unlock_irqrestore(&dev->event_lock, flags);
4932                 return;
4933         }
4934
4935         intel_crtc->unpin_work = NULL;
4936         drm_vblank_put(dev, intel_crtc->pipe);
4937
4938         if (work->event) {
4939                 e = work->event;
4940                 do_gettimeofday(&now);
4941                 e->event.sequence = drm_vblank_count(dev, intel_crtc->pipe);
4942                 e->event.tv_sec = now.tv_sec;
4943                 e->event.tv_usec = now.tv_usec;
4944                 list_add_tail(&e->base.link,
4945                               &e->base.file_priv->event_list);
4946                 wake_up_interruptible(&e->base.file_priv->event_wait);
4947         }
4948
4949         spin_unlock_irqrestore(&dev->event_lock, flags);
4950
4951         obj_priv = to_intel_bo(work->pending_flip_obj);
4952
4953         /* Initial scanout buffer will have a 0 pending flip count */
4954         if ((atomic_read(&obj_priv->pending_flip) == 0) ||
4955             atomic_dec_and_test(&obj_priv->pending_flip))
4956                 DRM_WAKEUP(&dev_priv->pending_flip_queue);
4957         schedule_work(&work->work);
4958
4959         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
4960 }
4961
4962 void intel_finish_page_flip(struct drm_device *dev, int pipe)
4963 {
4964         drm_i915_private_t *dev_priv = dev->dev_private;
4965         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
4966
4967         do_intel_finish_page_flip(dev, crtc);
4968 }
4969
4970 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
4971 {
4972         drm_i915_private_t *dev_priv = dev->dev_private;
4973         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
4974
4975         do_intel_finish_page_flip(dev, crtc);
4976 }
4977
4978 void intel_prepare_page_flip(struct drm_device *dev, int plane)
4979 {
4980         drm_i915_private_t *dev_priv = dev->dev_private;
4981         struct intel_crtc *intel_crtc =
4982                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
4983         unsigned long flags;
4984
4985         spin_lock_irqsave(&dev->event_lock, flags);
4986         if (intel_crtc->unpin_work) {
4987                 if ((++intel_crtc->unpin_work->pending) > 1)
4988                         DRM_ERROR("Prepared flip multiple times\n");
4989         } else {
4990                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
4991         }
4992         spin_unlock_irqrestore(&dev->event_lock, flags);
4993 }
4994
4995 static int intel_crtc_page_flip(struct drm_crtc *crtc,
4996                                 struct drm_framebuffer *fb,
4997                                 struct drm_pending_vblank_event *event)
4998 {
4999         struct drm_device *dev = crtc->dev;
5000         struct drm_i915_private *dev_priv = dev->dev_private;
5001         struct intel_framebuffer *intel_fb;
5002         struct drm_i915_gem_object *obj_priv;
5003         struct drm_gem_object *obj;
5004         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5005         struct intel_unpin_work *work;
5006         unsigned long flags, offset;
5007         int pipe = intel_crtc->pipe;
5008         u32 pf, pipesrc;
5009         int ret;
5010
5011         work = kzalloc(sizeof *work, GFP_KERNEL);
5012         if (work == NULL)
5013                 return -ENOMEM;
5014
5015         work->event = event;
5016         work->dev = crtc->dev;
5017         intel_fb = to_intel_framebuffer(crtc->fb);
5018         work->old_fb_obj = intel_fb->obj;
5019         INIT_WORK(&work->work, intel_unpin_work_fn);
5020
5021         /* We borrow the event spin lock for protecting unpin_work */
5022         spin_lock_irqsave(&dev->event_lock, flags);
5023         if (intel_crtc->unpin_work) {
5024                 spin_unlock_irqrestore(&dev->event_lock, flags);
5025                 kfree(work);
5026
5027                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5028                 return -EBUSY;
5029         }
5030         intel_crtc->unpin_work = work;
5031         spin_unlock_irqrestore(&dev->event_lock, flags);
5032
5033         intel_fb = to_intel_framebuffer(fb);
5034         obj = intel_fb->obj;
5035
5036         mutex_lock(&dev->struct_mutex);
5037         ret = intel_pin_and_fence_fb_obj(dev, obj);
5038         if (ret)
5039                 goto cleanup_work;
5040
5041         /* Reference the objects for the scheduled work. */
5042         drm_gem_object_reference(work->old_fb_obj);
5043         drm_gem_object_reference(obj);
5044
5045         crtc->fb = fb;
5046         ret = i915_gem_object_flush_write_domain(obj);
5047         if (ret)
5048                 goto cleanup_objs;
5049
5050         ret = drm_vblank_get(dev, intel_crtc->pipe);
5051         if (ret)
5052                 goto cleanup_objs;
5053
5054         obj_priv = to_intel_bo(obj);
5055         atomic_inc(&obj_priv->pending_flip);
5056         work->pending_flip_obj = obj;
5057
5058         if (IS_GEN3(dev) || IS_GEN2(dev)) {
5059                 u32 flip_mask;
5060
5061                 if (intel_crtc->plane)
5062                         flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
5063                 else
5064                         flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
5065
5066                 BEGIN_LP_RING(2);
5067                 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
5068                 OUT_RING(0);
5069                 ADVANCE_LP_RING();
5070         }
5071
5072         work->enable_stall_check = true;
5073
5074         /* Offset into the new buffer for cases of shared fbs between CRTCs */
5075         offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
5076
5077         BEGIN_LP_RING(4);
5078         switch(INTEL_INFO(dev)->gen) {
5079         case 2:
5080                 OUT_RING(MI_DISPLAY_FLIP |
5081                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5082                 OUT_RING(fb->pitch);
5083                 OUT_RING(obj_priv->gtt_offset + offset);
5084                 OUT_RING(MI_NOOP);
5085                 break;
5086
5087         case 3:
5088                 OUT_RING(MI_DISPLAY_FLIP_I915 |
5089                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5090                 OUT_RING(fb->pitch);
5091                 OUT_RING(obj_priv->gtt_offset + offset);
5092                 OUT_RING(MI_NOOP);
5093                 break;
5094
5095         case 4:
5096         case 5:
5097                 /* i965+ uses the linear or tiled offsets from the
5098                  * Display Registers (which do not change across a page-flip)
5099                  * so we need only reprogram the base address.
5100                  */
5101                 OUT_RING(MI_DISPLAY_FLIP |
5102                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5103                 OUT_RING(fb->pitch);
5104                 OUT_RING(obj_priv->gtt_offset | obj_priv->tiling_mode);
5105
5106                 /* XXX Enabling the panel-fitter across page-flip is so far
5107                  * untested on non-native modes, so ignore it for now.
5108                  * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5109                  */
5110                 pf = 0;
5111                 pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
5112                 OUT_RING(pf | pipesrc);
5113                 break;
5114
5115         case 6:
5116                 OUT_RING(MI_DISPLAY_FLIP |
5117                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5118                 OUT_RING(fb->pitch | obj_priv->tiling_mode);
5119                 OUT_RING(obj_priv->gtt_offset);
5120
5121                 pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5122                 pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
5123                 OUT_RING(pf | pipesrc);
5124                 break;
5125         }
5126         ADVANCE_LP_RING();
5127
5128         mutex_unlock(&dev->struct_mutex);
5129
5130         trace_i915_flip_request(intel_crtc->plane, obj);
5131
5132         return 0;
5133
5134 cleanup_objs:
5135         drm_gem_object_unreference(work->old_fb_obj);
5136         drm_gem_object_unreference(obj);
5137 cleanup_work:
5138         mutex_unlock(&dev->struct_mutex);
5139
5140         spin_lock_irqsave(&dev->event_lock, flags);
5141         intel_crtc->unpin_work = NULL;
5142         spin_unlock_irqrestore(&dev->event_lock, flags);
5143
5144         kfree(work);
5145
5146         return ret;
5147 }
5148
5149 static struct drm_crtc_helper_funcs intel_helper_funcs = {
5150         .dpms = intel_crtc_dpms,
5151         .mode_fixup = intel_crtc_mode_fixup,
5152         .mode_set = intel_crtc_mode_set,
5153         .mode_set_base = intel_pipe_set_base,
5154         .mode_set_base_atomic = intel_pipe_set_base_atomic,
5155         .load_lut = intel_crtc_load_lut,
5156 };
5157
5158 static const struct drm_crtc_funcs intel_crtc_funcs = {
5159         .cursor_set = intel_crtc_cursor_set,
5160         .cursor_move = intel_crtc_cursor_move,
5161         .gamma_set = intel_crtc_gamma_set,
5162         .set_config = drm_crtc_helper_set_config,
5163         .destroy = intel_crtc_destroy,
5164         .page_flip = intel_crtc_page_flip,
5165 };
5166
5167
5168 static void intel_crtc_init(struct drm_device *dev, int pipe)
5169 {
5170         drm_i915_private_t *dev_priv = dev->dev_private;
5171         struct intel_crtc *intel_crtc;
5172         int i;
5173
5174         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
5175         if (intel_crtc == NULL)
5176                 return;
5177
5178         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
5179
5180         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
5181         intel_crtc->pipe = pipe;
5182         intel_crtc->plane = pipe;
5183         for (i = 0; i < 256; i++) {
5184                 intel_crtc->lut_r[i] = i;
5185                 intel_crtc->lut_g[i] = i;
5186                 intel_crtc->lut_b[i] = i;
5187         }
5188
5189         /* Swap pipes & planes for FBC on pre-965 */
5190         intel_crtc->pipe = pipe;
5191         intel_crtc->plane = pipe;
5192         if (IS_MOBILE(dev) && (IS_I9XX(dev) && !IS_I965G(dev))) {
5193                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
5194                 intel_crtc->plane = ((pipe == 0) ? 1 : 0);
5195         }
5196
5197         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
5198                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
5199         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
5200         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
5201
5202         intel_crtc->cursor_addr = 0;
5203         intel_crtc->dpms_mode = -1;
5204
5205         if (HAS_PCH_SPLIT(dev)) {
5206                 intel_helper_funcs.prepare = ironlake_crtc_prepare;
5207                 intel_helper_funcs.commit = ironlake_crtc_commit;
5208         } else {
5209                 intel_helper_funcs.prepare = i9xx_crtc_prepare;
5210                 intel_helper_funcs.commit = i9xx_crtc_commit;
5211         }
5212
5213         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
5214
5215         intel_crtc->busy = false;
5216
5217         setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
5218                     (unsigned long)intel_crtc);
5219 }
5220
5221 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
5222                                 struct drm_file *file_priv)
5223 {
5224         drm_i915_private_t *dev_priv = dev->dev_private;
5225         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
5226         struct drm_mode_object *drmmode_obj;
5227         struct intel_crtc *crtc;
5228
5229         if (!dev_priv) {
5230                 DRM_ERROR("called with no initialization\n");
5231                 return -EINVAL;
5232         }
5233
5234         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
5235                         DRM_MODE_OBJECT_CRTC);
5236
5237         if (!drmmode_obj) {
5238                 DRM_ERROR("no such CRTC id\n");
5239                 return -EINVAL;
5240         }
5241
5242         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
5243         pipe_from_crtc_id->pipe = crtc->pipe;
5244
5245         return 0;
5246 }
5247
5248 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
5249 {
5250         struct intel_encoder *encoder;
5251         int index_mask = 0;
5252         int entry = 0;
5253
5254         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
5255                 if (type_mask & encoder->clone_mask)
5256                         index_mask |= (1 << entry);
5257                 entry++;
5258         }
5259
5260         return index_mask;
5261 }
5262
5263 static void intel_setup_outputs(struct drm_device *dev)
5264 {
5265         struct drm_i915_private *dev_priv = dev->dev_private;
5266         struct intel_encoder *encoder;
5267         bool dpd_is_edp = false;
5268
5269         if (IS_MOBILE(dev) && !IS_I830(dev))
5270                 intel_lvds_init(dev);
5271
5272         if (HAS_PCH_SPLIT(dev)) {
5273                 dpd_is_edp = intel_dpd_is_edp(dev);
5274
5275                 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
5276                         intel_dp_init(dev, DP_A);
5277
5278                 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5279                         intel_dp_init(dev, PCH_DP_D);
5280         }
5281
5282         intel_crt_init(dev);
5283
5284         if (HAS_PCH_SPLIT(dev)) {
5285                 int found;
5286
5287                 if (I915_READ(HDMIB) & PORT_DETECTED) {
5288                         /* PCH SDVOB multiplex with HDMIB */
5289                         found = intel_sdvo_init(dev, PCH_SDVOB);
5290                         if (!found)
5291                                 intel_hdmi_init(dev, HDMIB);
5292                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
5293                                 intel_dp_init(dev, PCH_DP_B);
5294                 }
5295
5296                 if (I915_READ(HDMIC) & PORT_DETECTED)
5297                         intel_hdmi_init(dev, HDMIC);
5298
5299                 if (I915_READ(HDMID) & PORT_DETECTED)
5300                         intel_hdmi_init(dev, HDMID);
5301
5302                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
5303                         intel_dp_init(dev, PCH_DP_C);
5304
5305                 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5306                         intel_dp_init(dev, PCH_DP_D);
5307
5308         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
5309                 bool found = false;
5310
5311                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5312                         DRM_DEBUG_KMS("probing SDVOB\n");
5313                         found = intel_sdvo_init(dev, SDVOB);
5314                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
5315                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
5316                                 intel_hdmi_init(dev, SDVOB);
5317                         }
5318
5319                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
5320                                 DRM_DEBUG_KMS("probing DP_B\n");
5321                                 intel_dp_init(dev, DP_B);
5322                         }
5323                 }
5324
5325                 /* Before G4X SDVOC doesn't have its own detect register */
5326
5327                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5328                         DRM_DEBUG_KMS("probing SDVOC\n");
5329                         found = intel_sdvo_init(dev, SDVOC);
5330                 }
5331
5332                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
5333
5334                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
5335                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
5336                                 intel_hdmi_init(dev, SDVOC);
5337                         }
5338                         if (SUPPORTS_INTEGRATED_DP(dev)) {
5339                                 DRM_DEBUG_KMS("probing DP_C\n");
5340                                 intel_dp_init(dev, DP_C);
5341                         }
5342                 }
5343
5344                 if (SUPPORTS_INTEGRATED_DP(dev) &&
5345                     (I915_READ(DP_D) & DP_DETECTED)) {
5346                         DRM_DEBUG_KMS("probing DP_D\n");
5347                         intel_dp_init(dev, DP_D);
5348                 }
5349         } else if (IS_GEN2(dev))
5350                 intel_dvo_init(dev);
5351
5352         if (SUPPORTS_TV(dev))
5353                 intel_tv_init(dev);
5354
5355         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
5356                 encoder->base.possible_crtcs = encoder->crtc_mask;
5357                 encoder->base.possible_clones =
5358                         intel_encoder_clones(dev, encoder->clone_mask);
5359         }
5360 }
5361
5362 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
5363 {
5364         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5365
5366         drm_framebuffer_cleanup(fb);
5367         drm_gem_object_unreference_unlocked(intel_fb->obj);
5368
5369         kfree(intel_fb);
5370 }
5371
5372 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
5373                                                 struct drm_file *file_priv,
5374                                                 unsigned int *handle)
5375 {
5376         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5377         struct drm_gem_object *object = intel_fb->obj;
5378
5379         return drm_gem_handle_create(file_priv, object, handle);
5380 }
5381
5382 static const struct drm_framebuffer_funcs intel_fb_funcs = {
5383         .destroy = intel_user_framebuffer_destroy,
5384         .create_handle = intel_user_framebuffer_create_handle,
5385 };
5386
5387 int intel_framebuffer_init(struct drm_device *dev,
5388                            struct intel_framebuffer *intel_fb,
5389                            struct drm_mode_fb_cmd *mode_cmd,
5390                            struct drm_gem_object *obj)
5391 {
5392         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
5393         int ret;
5394
5395         if (obj_priv->tiling_mode == I915_TILING_Y)
5396                 return -EINVAL;
5397
5398         if (mode_cmd->pitch & 63)
5399                 return -EINVAL;
5400
5401         switch (mode_cmd->bpp) {
5402         case 8:
5403         case 16:
5404         case 24:
5405         case 32:
5406                 break;
5407         default:
5408                 return -EINVAL;
5409         }
5410
5411         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
5412         if (ret) {
5413                 DRM_ERROR("framebuffer init failed %d\n", ret);
5414                 return ret;
5415         }
5416
5417         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
5418         intel_fb->obj = obj;
5419         return 0;
5420 }
5421
5422 static struct drm_framebuffer *
5423 intel_user_framebuffer_create(struct drm_device *dev,
5424                               struct drm_file *filp,
5425                               struct drm_mode_fb_cmd *mode_cmd)
5426 {
5427         struct drm_gem_object *obj;
5428         struct intel_framebuffer *intel_fb;
5429         int ret;
5430
5431         obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
5432         if (!obj)
5433                 return ERR_PTR(-ENOENT);
5434
5435         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5436         if (!intel_fb)
5437                 return ERR_PTR(-ENOMEM);
5438
5439         ret = intel_framebuffer_init(dev, intel_fb,
5440                                      mode_cmd, obj);
5441         if (ret) {
5442                 drm_gem_object_unreference_unlocked(obj);
5443                 kfree(intel_fb);
5444                 return ERR_PTR(ret);
5445         }
5446
5447         return &intel_fb->base;
5448 }
5449
5450 static const struct drm_mode_config_funcs intel_mode_funcs = {
5451         .fb_create = intel_user_framebuffer_create,
5452         .output_poll_changed = intel_fb_output_poll_changed,
5453 };
5454
5455 static struct drm_gem_object *
5456 intel_alloc_context_page(struct drm_device *dev)
5457 {
5458         struct drm_gem_object *ctx;
5459         int ret;
5460
5461         ctx = i915_gem_alloc_object(dev, 4096);
5462         if (!ctx) {
5463                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
5464                 return NULL;
5465         }
5466
5467         mutex_lock(&dev->struct_mutex);
5468         ret = i915_gem_object_pin(ctx, 4096);
5469         if (ret) {
5470                 DRM_ERROR("failed to pin power context: %d\n", ret);
5471                 goto err_unref;
5472         }
5473
5474         ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
5475         if (ret) {
5476                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
5477                 goto err_unpin;
5478         }
5479         mutex_unlock(&dev->struct_mutex);
5480
5481         return ctx;
5482
5483 err_unpin:
5484         i915_gem_object_unpin(ctx);
5485 err_unref:
5486         drm_gem_object_unreference(ctx);
5487         mutex_unlock(&dev->struct_mutex);
5488         return NULL;
5489 }
5490
5491 bool ironlake_set_drps(struct drm_device *dev, u8 val)
5492 {
5493         struct drm_i915_private *dev_priv = dev->dev_private;
5494         u16 rgvswctl;
5495
5496         rgvswctl = I915_READ16(MEMSWCTL);
5497         if (rgvswctl & MEMCTL_CMD_STS) {
5498                 DRM_DEBUG("gpu busy, RCS change rejected\n");
5499                 return false; /* still busy with another command */
5500         }
5501
5502         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
5503                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
5504         I915_WRITE16(MEMSWCTL, rgvswctl);
5505         POSTING_READ16(MEMSWCTL);
5506
5507         rgvswctl |= MEMCTL_CMD_STS;
5508         I915_WRITE16(MEMSWCTL, rgvswctl);
5509
5510         return true;
5511 }
5512
5513 void ironlake_enable_drps(struct drm_device *dev)
5514 {
5515         struct drm_i915_private *dev_priv = dev->dev_private;
5516         u32 rgvmodectl = I915_READ(MEMMODECTL);
5517         u8 fmax, fmin, fstart, vstart;
5518
5519         /* Enable temp reporting */
5520         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
5521         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
5522
5523         /* 100ms RC evaluation intervals */
5524         I915_WRITE(RCUPEI, 100000);
5525         I915_WRITE(RCDNEI, 100000);
5526
5527         /* Set max/min thresholds to 90ms and 80ms respectively */
5528         I915_WRITE(RCBMAXAVG, 90000);
5529         I915_WRITE(RCBMINAVG, 80000);
5530
5531         I915_WRITE(MEMIHYST, 1);
5532
5533         /* Set up min, max, and cur for interrupt handling */
5534         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
5535         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
5536         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
5537                 MEMMODE_FSTART_SHIFT;
5538         fstart = fmax;
5539
5540         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
5541                 PXVFREQ_PX_SHIFT;
5542
5543         dev_priv->fmax = fstart; /* IPS callback will increase this */
5544         dev_priv->fstart = fstart;
5545
5546         dev_priv->max_delay = fmax;
5547         dev_priv->min_delay = fmin;
5548         dev_priv->cur_delay = fstart;
5549
5550         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", fmax, fmin,
5551                          fstart);
5552
5553         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
5554
5555         /*
5556          * Interrupts will be enabled in ironlake_irq_postinstall
5557          */
5558
5559         I915_WRITE(VIDSTART, vstart);
5560         POSTING_READ(VIDSTART);
5561
5562         rgvmodectl |= MEMMODE_SWMODE_EN;
5563         I915_WRITE(MEMMODECTL, rgvmodectl);
5564
5565         if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
5566                 DRM_ERROR("stuck trying to change perf mode\n");
5567         msleep(1);
5568
5569         ironlake_set_drps(dev, fstart);
5570
5571         dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
5572                 I915_READ(0x112e0);
5573         dev_priv->last_time1 = jiffies_to_msecs(jiffies);
5574         dev_priv->last_count2 = I915_READ(0x112f4);
5575         getrawmonotonic(&dev_priv->last_time2);
5576 }
5577
5578 void ironlake_disable_drps(struct drm_device *dev)
5579 {
5580         struct drm_i915_private *dev_priv = dev->dev_private;
5581         u16 rgvswctl = I915_READ16(MEMSWCTL);
5582
5583         /* Ack interrupts, disable EFC interrupt */
5584         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
5585         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
5586         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
5587         I915_WRITE(DEIIR, DE_PCU_EVENT);
5588         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
5589
5590         /* Go back to the starting frequency */
5591         ironlake_set_drps(dev, dev_priv->fstart);
5592         msleep(1);
5593         rgvswctl |= MEMCTL_CMD_STS;
5594         I915_WRITE(MEMSWCTL, rgvswctl);
5595         msleep(1);
5596
5597 }
5598
5599 static unsigned long intel_pxfreq(u32 vidfreq)
5600 {
5601         unsigned long freq;
5602         int div = (vidfreq & 0x3f0000) >> 16;
5603         int post = (vidfreq & 0x3000) >> 12;
5604         int pre = (vidfreq & 0x7);
5605
5606         if (!pre)
5607                 return 0;
5608
5609         freq = ((div * 133333) / ((1<<post) * pre));
5610
5611         return freq;
5612 }
5613
5614 void intel_init_emon(struct drm_device *dev)
5615 {
5616         struct drm_i915_private *dev_priv = dev->dev_private;
5617         u32 lcfuse;
5618         u8 pxw[16];
5619         int i;
5620
5621         /* Disable to program */
5622         I915_WRITE(ECR, 0);
5623         POSTING_READ(ECR);
5624
5625         /* Program energy weights for various events */
5626         I915_WRITE(SDEW, 0x15040d00);
5627         I915_WRITE(CSIEW0, 0x007f0000);
5628         I915_WRITE(CSIEW1, 0x1e220004);
5629         I915_WRITE(CSIEW2, 0x04000004);
5630
5631         for (i = 0; i < 5; i++)
5632                 I915_WRITE(PEW + (i * 4), 0);
5633         for (i = 0; i < 3; i++)
5634                 I915_WRITE(DEW + (i * 4), 0);
5635
5636         /* Program P-state weights to account for frequency power adjustment */
5637         for (i = 0; i < 16; i++) {
5638                 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
5639                 unsigned long freq = intel_pxfreq(pxvidfreq);
5640                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
5641                         PXVFREQ_PX_SHIFT;
5642                 unsigned long val;
5643
5644                 val = vid * vid;
5645                 val *= (freq / 1000);
5646                 val *= 255;
5647                 val /= (127*127*900);
5648                 if (val > 0xff)
5649                         DRM_ERROR("bad pxval: %ld\n", val);
5650                 pxw[i] = val;
5651         }
5652         /* Render standby states get 0 weight */
5653         pxw[14] = 0;
5654         pxw[15] = 0;
5655
5656         for (i = 0; i < 4; i++) {
5657                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
5658                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
5659                 I915_WRITE(PXW + (i * 4), val);
5660         }
5661
5662         /* Adjust magic regs to magic values (more experimental results) */
5663         I915_WRITE(OGW0, 0);
5664         I915_WRITE(OGW1, 0);
5665         I915_WRITE(EG0, 0x00007f00);
5666         I915_WRITE(EG1, 0x0000000e);
5667         I915_WRITE(EG2, 0x000e0000);
5668         I915_WRITE(EG3, 0x68000300);
5669         I915_WRITE(EG4, 0x42000000);
5670         I915_WRITE(EG5, 0x00140031);
5671         I915_WRITE(EG6, 0);
5672         I915_WRITE(EG7, 0);
5673
5674         for (i = 0; i < 8; i++)
5675                 I915_WRITE(PXWL + (i * 4), 0);
5676
5677         /* Enable PMON + select events */
5678         I915_WRITE(ECR, 0x80000019);
5679
5680         lcfuse = I915_READ(LCFUSE02);
5681
5682         dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
5683 }
5684
5685 void intel_init_clock_gating(struct drm_device *dev)
5686 {
5687         struct drm_i915_private *dev_priv = dev->dev_private;
5688
5689         /*
5690          * Disable clock gating reported to work incorrectly according to the
5691          * specs, but enable as much else as we can.
5692          */
5693         if (HAS_PCH_SPLIT(dev)) {
5694                 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
5695
5696                 if (IS_IRONLAKE(dev)) {
5697                         /* Required for FBC */
5698                         dspclk_gate |= DPFDUNIT_CLOCK_GATE_DISABLE;
5699                         /* Required for CxSR */
5700                         dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
5701
5702                         I915_WRITE(PCH_3DCGDIS0,
5703                                    MARIUNIT_CLOCK_GATE_DISABLE |
5704                                    SVSMUNIT_CLOCK_GATE_DISABLE);
5705                 }
5706
5707                 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
5708
5709                 /*
5710                  * According to the spec the following bits should be set in
5711                  * order to enable memory self-refresh
5712                  * The bit 22/21 of 0x42004
5713                  * The bit 5 of 0x42020
5714                  * The bit 15 of 0x45000
5715                  */
5716                 if (IS_IRONLAKE(dev)) {
5717                         I915_WRITE(ILK_DISPLAY_CHICKEN2,
5718                                         (I915_READ(ILK_DISPLAY_CHICKEN2) |
5719                                         ILK_DPARB_GATE | ILK_VSDPFD_FULL));
5720                         I915_WRITE(ILK_DSPCLK_GATE,
5721                                         (I915_READ(ILK_DSPCLK_GATE) |
5722                                                 ILK_DPARB_CLK_GATE));
5723                         I915_WRITE(DISP_ARB_CTL,
5724                                         (I915_READ(DISP_ARB_CTL) |
5725                                                 DISP_FBC_WM_DIS));
5726                 I915_WRITE(WM3_LP_ILK, 0);
5727                 I915_WRITE(WM2_LP_ILK, 0);
5728                 I915_WRITE(WM1_LP_ILK, 0);
5729                 }
5730                 /*
5731                  * Based on the document from hardware guys the following bits
5732                  * should be set unconditionally in order to enable FBC.
5733                  * The bit 22 of 0x42000
5734                  * The bit 22 of 0x42004
5735                  * The bit 7,8,9 of 0x42020.
5736                  */
5737                 if (IS_IRONLAKE_M(dev)) {
5738                         I915_WRITE(ILK_DISPLAY_CHICKEN1,
5739                                    I915_READ(ILK_DISPLAY_CHICKEN1) |
5740                                    ILK_FBCQ_DIS);
5741                         I915_WRITE(ILK_DISPLAY_CHICKEN2,
5742                                    I915_READ(ILK_DISPLAY_CHICKEN2) |
5743                                    ILK_DPARB_GATE);
5744                         I915_WRITE(ILK_DSPCLK_GATE,
5745                                    I915_READ(ILK_DSPCLK_GATE) |
5746                                    ILK_DPFC_DIS1 |
5747                                    ILK_DPFC_DIS2 |
5748                                    ILK_CLK_FBC);
5749                 }
5750                 return;
5751         } else if (IS_G4X(dev)) {
5752                 uint32_t dspclk_gate;
5753                 I915_WRITE(RENCLK_GATE_D1, 0);
5754                 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5755                        GS_UNIT_CLOCK_GATE_DISABLE |
5756                        CL_UNIT_CLOCK_GATE_DISABLE);
5757                 I915_WRITE(RAMCLK_GATE_D, 0);
5758                 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5759                         OVRUNIT_CLOCK_GATE_DISABLE |
5760                         OVCUNIT_CLOCK_GATE_DISABLE;
5761                 if (IS_GM45(dev))
5762                         dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5763                 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
5764         } else if (IS_I965GM(dev)) {
5765                 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5766                 I915_WRITE(RENCLK_GATE_D2, 0);
5767                 I915_WRITE(DSPCLK_GATE_D, 0);
5768                 I915_WRITE(RAMCLK_GATE_D, 0);
5769                 I915_WRITE16(DEUC, 0);
5770         } else if (IS_I965G(dev)) {
5771                 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5772                        I965_RCC_CLOCK_GATE_DISABLE |
5773                        I965_RCPB_CLOCK_GATE_DISABLE |
5774                        I965_ISC_CLOCK_GATE_DISABLE |
5775                        I965_FBC_CLOCK_GATE_DISABLE);
5776                 I915_WRITE(RENCLK_GATE_D2, 0);
5777         } else if (IS_I9XX(dev)) {
5778                 u32 dstate = I915_READ(D_STATE);
5779
5780                 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5781                         DSTATE_DOT_CLOCK_GATING;
5782                 I915_WRITE(D_STATE, dstate);
5783         } else if (IS_I85X(dev) || IS_I865G(dev)) {
5784                 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5785         } else if (IS_I830(dev)) {
5786                 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5787         }
5788
5789         /*
5790          * GPU can automatically power down the render unit if given a page
5791          * to save state.
5792          */
5793         if (IS_IRONLAKE_M(dev)) {
5794                 if (dev_priv->renderctx == NULL)
5795                         dev_priv->renderctx = intel_alloc_context_page(dev);
5796                 if (dev_priv->renderctx) {
5797                         struct drm_i915_gem_object *obj_priv;
5798                         obj_priv = to_intel_bo(dev_priv->renderctx);
5799                         if (obj_priv) {
5800                                 BEGIN_LP_RING(4);
5801                                 OUT_RING(MI_SET_CONTEXT);
5802                                 OUT_RING(obj_priv->gtt_offset |
5803                                                 MI_MM_SPACE_GTT |
5804                                                 MI_SAVE_EXT_STATE_EN |
5805                                                 MI_RESTORE_EXT_STATE_EN |
5806                                                 MI_RESTORE_INHIBIT);
5807                                 OUT_RING(MI_NOOP);
5808                                 OUT_RING(MI_FLUSH);
5809                                 ADVANCE_LP_RING();
5810                         }
5811                 } else
5812                         DRM_DEBUG_KMS("Failed to allocate render context."
5813                                        "Disable RC6\n");
5814         }
5815
5816         if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) {
5817                 struct drm_i915_gem_object *obj_priv = NULL;
5818
5819                 if (dev_priv->pwrctx) {
5820                         obj_priv = to_intel_bo(dev_priv->pwrctx);
5821                 } else {
5822                         struct drm_gem_object *pwrctx;
5823
5824                         pwrctx = intel_alloc_context_page(dev);
5825                         if (pwrctx) {
5826                                 dev_priv->pwrctx = pwrctx;
5827                                 obj_priv = to_intel_bo(pwrctx);
5828                         }
5829                 }
5830
5831                 if (obj_priv) {
5832                         I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN);
5833                         I915_WRITE(MCHBAR_RENDER_STANDBY,
5834                                    I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
5835                 }
5836         }
5837 }
5838
5839 /* Set up chip specific display functions */
5840 static void intel_init_display(struct drm_device *dev)
5841 {
5842         struct drm_i915_private *dev_priv = dev->dev_private;
5843
5844         /* We always want a DPMS function */
5845         if (HAS_PCH_SPLIT(dev))
5846                 dev_priv->display.dpms = ironlake_crtc_dpms;
5847         else
5848                 dev_priv->display.dpms = i9xx_crtc_dpms;
5849
5850         if (I915_HAS_FBC(dev)) {
5851                 if (IS_IRONLAKE_M(dev)) {
5852                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
5853                         dev_priv->display.enable_fbc = ironlake_enable_fbc;
5854                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
5855                 } else if (IS_GM45(dev)) {
5856                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
5857                         dev_priv->display.enable_fbc = g4x_enable_fbc;
5858                         dev_priv->display.disable_fbc = g4x_disable_fbc;
5859                 } else if (IS_I965GM(dev)) {
5860                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
5861                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
5862                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
5863                 }
5864                 /* 855GM needs testing */
5865         }
5866
5867         /* Returns the core display clock speed */
5868         if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
5869                 dev_priv->display.get_display_clock_speed =
5870                         i945_get_display_clock_speed;
5871         else if (IS_I915G(dev))
5872                 dev_priv->display.get_display_clock_speed =
5873                         i915_get_display_clock_speed;
5874         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
5875                 dev_priv->display.get_display_clock_speed =
5876                         i9xx_misc_get_display_clock_speed;
5877         else if (IS_I915GM(dev))
5878                 dev_priv->display.get_display_clock_speed =
5879                         i915gm_get_display_clock_speed;
5880         else if (IS_I865G(dev))
5881                 dev_priv->display.get_display_clock_speed =
5882                         i865_get_display_clock_speed;
5883         else if (IS_I85X(dev))
5884                 dev_priv->display.get_display_clock_speed =
5885                         i855_get_display_clock_speed;
5886         else /* 852, 830 */
5887                 dev_priv->display.get_display_clock_speed =
5888                         i830_get_display_clock_speed;
5889
5890         /* For FIFO watermark updates */
5891         if (HAS_PCH_SPLIT(dev)) {
5892                 if (IS_IRONLAKE(dev)) {
5893                         if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
5894                                 dev_priv->display.update_wm = ironlake_update_wm;
5895                         else {
5896                                 DRM_DEBUG_KMS("Failed to get proper latency. "
5897                                               "Disable CxSR\n");
5898                                 dev_priv->display.update_wm = NULL;
5899                         }
5900                 } else
5901                         dev_priv->display.update_wm = NULL;
5902         } else if (IS_PINEVIEW(dev)) {
5903                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
5904                                             dev_priv->is_ddr3,
5905                                             dev_priv->fsb_freq,
5906                                             dev_priv->mem_freq)) {
5907                         DRM_INFO("failed to find known CxSR latency "
5908                                  "(found ddr%s fsb freq %d, mem freq %d), "
5909                                  "disabling CxSR\n",
5910                                  (dev_priv->is_ddr3 == 1) ? "3": "2",
5911                                  dev_priv->fsb_freq, dev_priv->mem_freq);
5912                         /* Disable CxSR and never update its watermark again */
5913                         pineview_disable_cxsr(dev);
5914                         dev_priv->display.update_wm = NULL;
5915                 } else
5916                         dev_priv->display.update_wm = pineview_update_wm;
5917         } else if (IS_G4X(dev))
5918                 dev_priv->display.update_wm = g4x_update_wm;
5919         else if (IS_I965G(dev))
5920                 dev_priv->display.update_wm = i965_update_wm;
5921         else if (IS_I9XX(dev)) {
5922                 dev_priv->display.update_wm = i9xx_update_wm;
5923                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
5924         } else if (IS_I85X(dev)) {
5925                 dev_priv->display.update_wm = i9xx_update_wm;
5926                 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
5927         } else {
5928                 dev_priv->display.update_wm = i830_update_wm;
5929                 if (IS_845G(dev))
5930                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
5931                 else
5932                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
5933         }
5934 }
5935
5936 /*
5937  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
5938  * resume, or other times.  This quirk makes sure that's the case for
5939  * affected systems.
5940  */
5941 static void quirk_pipea_force (struct drm_device *dev)
5942 {
5943         struct drm_i915_private *dev_priv = dev->dev_private;
5944
5945         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
5946         DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
5947 }
5948
5949 struct intel_quirk {
5950         int device;
5951         int subsystem_vendor;
5952         int subsystem_device;
5953         void (*hook)(struct drm_device *dev);
5954 };
5955
5956 struct intel_quirk intel_quirks[] = {
5957         /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
5958         { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
5959         /* HP Mini needs pipe A force quirk (LP: #322104) */
5960         { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
5961
5962         /* Thinkpad R31 needs pipe A force quirk */
5963         { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
5964         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
5965         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
5966
5967         /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
5968         { 0x3577,  0x1014, 0x0513, quirk_pipea_force },
5969         /* ThinkPad X40 needs pipe A force quirk */
5970
5971         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
5972         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
5973
5974         /* 855 & before need to leave pipe A & dpll A up */
5975         { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
5976         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
5977 };
5978
5979 static void intel_init_quirks(struct drm_device *dev)
5980 {
5981         struct pci_dev *d = dev->pdev;
5982         int i;
5983
5984         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
5985                 struct intel_quirk *q = &intel_quirks[i];
5986
5987                 if (d->device == q->device &&
5988                     (d->subsystem_vendor == q->subsystem_vendor ||
5989                      q->subsystem_vendor == PCI_ANY_ID) &&
5990                     (d->subsystem_device == q->subsystem_device ||
5991                      q->subsystem_device == PCI_ANY_ID))
5992                         q->hook(dev);
5993         }
5994 }
5995
5996 /* Disable the VGA plane that we never use */
5997 static void i915_disable_vga(struct drm_device *dev)
5998 {
5999         struct drm_i915_private *dev_priv = dev->dev_private;
6000         u8 sr1;
6001         u32 vga_reg;
6002
6003         if (HAS_PCH_SPLIT(dev))
6004                 vga_reg = CPU_VGACNTRL;
6005         else
6006                 vga_reg = VGACNTRL;
6007
6008         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
6009         outb(1, VGA_SR_INDEX);
6010         sr1 = inb(VGA_SR_DATA);
6011         outb(sr1 | 1<<5, VGA_SR_DATA);
6012         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
6013         udelay(300);
6014
6015         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
6016         POSTING_READ(vga_reg);
6017 }
6018
6019 void intel_modeset_init(struct drm_device *dev)
6020 {
6021         struct drm_i915_private *dev_priv = dev->dev_private;
6022         int i;
6023
6024         drm_mode_config_init(dev);
6025
6026         dev->mode_config.min_width = 0;
6027         dev->mode_config.min_height = 0;
6028
6029         dev->mode_config.funcs = (void *)&intel_mode_funcs;
6030
6031         intel_init_quirks(dev);
6032
6033         intel_init_display(dev);
6034
6035         if (IS_I965G(dev)) {
6036                 dev->mode_config.max_width = 8192;
6037                 dev->mode_config.max_height = 8192;
6038         } else if (IS_I9XX(dev)) {
6039                 dev->mode_config.max_width = 4096;
6040                 dev->mode_config.max_height = 4096;
6041         } else {
6042                 dev->mode_config.max_width = 2048;
6043                 dev->mode_config.max_height = 2048;
6044         }
6045
6046         /* set memory base */
6047         if (IS_I9XX(dev))
6048                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
6049         else
6050                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
6051
6052         if (IS_MOBILE(dev) || IS_I9XX(dev))
6053                 dev_priv->num_pipe = 2;
6054         else
6055                 dev_priv->num_pipe = 1;
6056         DRM_DEBUG_KMS("%d display pipe%s available.\n",
6057                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
6058
6059         for (i = 0; i < dev_priv->num_pipe; i++) {
6060                 intel_crtc_init(dev, i);
6061         }
6062
6063         intel_setup_outputs(dev);
6064
6065         intel_init_clock_gating(dev);
6066
6067         /* Just disable it once at startup */
6068         i915_disable_vga(dev);
6069
6070         if (IS_IRONLAKE_M(dev)) {
6071                 ironlake_enable_drps(dev);
6072                 intel_init_emon(dev);
6073         }
6074
6075         INIT_WORK(&dev_priv->idle_work, intel_idle_update);
6076         setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
6077                     (unsigned long)dev);
6078
6079         intel_setup_overlay(dev);
6080 }
6081
6082 void intel_modeset_cleanup(struct drm_device *dev)
6083 {
6084         struct drm_i915_private *dev_priv = dev->dev_private;
6085         struct drm_crtc *crtc;
6086         struct intel_crtc *intel_crtc;
6087
6088         mutex_lock(&dev->struct_mutex);
6089
6090         drm_kms_helper_poll_fini(dev);
6091         intel_fbdev_fini(dev);
6092
6093         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6094                 /* Skip inactive CRTCs */
6095                 if (!crtc->fb)
6096                         continue;
6097
6098                 intel_crtc = to_intel_crtc(crtc);
6099                 intel_increase_pllclock(crtc);
6100         }
6101
6102         if (dev_priv->display.disable_fbc)
6103                 dev_priv->display.disable_fbc(dev);
6104
6105         if (dev_priv->renderctx) {
6106                 struct drm_i915_gem_object *obj_priv;
6107
6108                 obj_priv = to_intel_bo(dev_priv->renderctx);
6109                 I915_WRITE(CCID, obj_priv->gtt_offset &~ CCID_EN);
6110                 I915_READ(CCID);
6111                 i915_gem_object_unpin(dev_priv->renderctx);
6112                 drm_gem_object_unreference(dev_priv->renderctx);
6113         }
6114
6115         if (dev_priv->pwrctx) {
6116                 struct drm_i915_gem_object *obj_priv;
6117
6118                 obj_priv = to_intel_bo(dev_priv->pwrctx);
6119                 I915_WRITE(PWRCTXA, obj_priv->gtt_offset &~ PWRCTX_EN);
6120                 I915_READ(PWRCTXA);
6121                 i915_gem_object_unpin(dev_priv->pwrctx);
6122                 drm_gem_object_unreference(dev_priv->pwrctx);
6123         }
6124
6125         if (IS_IRONLAKE_M(dev))
6126                 ironlake_disable_drps(dev);
6127
6128         mutex_unlock(&dev->struct_mutex);
6129
6130         /* Disable the irq before mode object teardown, for the irq might
6131          * enqueue unpin/hotplug work. */
6132         drm_irq_uninstall(dev);
6133         cancel_work_sync(&dev_priv->hotplug_work);
6134
6135         /* Shut off idle work before the crtcs get freed. */
6136         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6137                 intel_crtc = to_intel_crtc(crtc);
6138                 del_timer_sync(&intel_crtc->idle_timer);
6139         }
6140         del_timer_sync(&dev_priv->idle_timer);
6141         cancel_work_sync(&dev_priv->idle_work);
6142
6143         drm_mode_config_cleanup(dev);
6144 }
6145
6146 /*
6147  * Return which encoder is currently attached for connector.
6148  */
6149 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
6150 {
6151         return &intel_attached_encoder(connector)->base;
6152 }
6153
6154 void intel_connector_attach_encoder(struct intel_connector *connector,
6155                                     struct intel_encoder *encoder)
6156 {
6157         connector->encoder = encoder;
6158         drm_mode_connector_attach_encoder(&connector->base,
6159                                           &encoder->base);
6160 }
6161
6162 /*
6163  * set vga decode state - true == enable VGA decode
6164  */
6165 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
6166 {
6167         struct drm_i915_private *dev_priv = dev->dev_private;
6168         u16 gmch_ctrl;
6169
6170         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
6171         if (state)
6172                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
6173         else
6174                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
6175         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
6176         return 0;
6177 }