drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <linux/export.h>
  31 #include <linux/notifier.h>
  32 #include <linux/reboot.h>
  33 #include <drm/drmP.h>
  34 #include <drm/drm_crtc.h>
  35 #include <drm/drm_crtc_helper.h>
  36 #include <drm/drm_edid.h>
  37 #include "intel_drv.h"
  38 #include <drm/i915_drm.h>
  39 #include "i915_drv.h"
  40
  41 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  42
  43 struct dp_link_dpll {
  44         int link_bw;
  45         struct dpll dpll;
  46 };
  47
  48 static const struct dp_link_dpll gen4_dpll[] = {
  49         { DP_LINK_BW_1_62,
  50                 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
  51         { DP_LINK_BW_2_7,
  52                 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
  53 };
  54
  55 static const struct dp_link_dpll pch_dpll[] = {
  56         { DP_LINK_BW_1_62,
  57                 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
  58         { DP_LINK_BW_2_7,
  59                 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
  60 };
  61
  62 static const struct dp_link_dpll vlv_dpll[] = {
  63         { DP_LINK_BW_1_62,
  64                 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
  65         { DP_LINK_BW_2_7,
  66                 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
  67 };
  68
  69 /*
  70  * CHV supports eDP 1.4 that have  more link rates.
  71  * Below only provides the fixed rate but exclude variable rate.
  72  */
  73 static const struct dp_link_dpll chv_dpll[] = {
  74         /*
  75          * CHV requires to program fractional division for m2.
  76          * m2 is stored in fixed point format using formula below
  77          * (m2_int << 22) | m2_fraction
  78          */
  79         { DP_LINK_BW_1_62,      /* m2_int = 32, m2_fraction = 1677722 */
  80                 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
  81         { DP_LINK_BW_2_7,       /* m2_int = 27, m2_fraction = 0 */
  82                 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
  83         { DP_LINK_BW_5_4,       /* m2_int = 27, m2_fraction = 0 */
  84                 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
  85 };
  86
  87 /**
  88  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
  89  * @intel_dp: DP struct
  90  *
  91  * If a CPU or PCH DP output is attached to an eDP panel, this function
  92  * will return true, and false otherwise.
  93  */
  94 static bool is_edp(struct intel_dp *intel_dp)
  95 {
  96         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  97
  98         return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
  99 }
 100
 101 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
 102 {
 103         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 104
 105         return intel_dig_port->base.base.dev;
 106 }
 107
 108 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
 109 {
 110         return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
 111 }
 112
 113 static void intel_dp_link_down(struct intel_dp *intel_dp);
 114 static bool _edp_panel_vdd_on(struct intel_dp *intel_dp);
 115 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 116
 117 int
 118 intel_dp_max_link_bw(struct intel_dp *intel_dp)
 119 {
 120         int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
 121         struct drm_device *dev = intel_dp->attached_connector->base.dev;
 122
 123         switch (max_link_bw) {
 124         case DP_LINK_BW_1_62:
 125         case DP_LINK_BW_2_7:
 126                 break;
 127         case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
 128                 if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
 129                      INTEL_INFO(dev)->gen >= 8) &&
 130                     intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
 131                         max_link_bw = DP_LINK_BW_5_4;
 132                 else
 133                         max_link_bw = DP_LINK_BW_2_7;
 134                 break;
 135         default:
 136                 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
 137                      max_link_bw);
 138                 max_link_bw = DP_LINK_BW_1_62;
 139                 break;
 140         }
 141         return max_link_bw;
 142 }
 143
 144 static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
 145 {
 146         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 147         struct drm_device *dev = intel_dig_port->base.base.dev;
 148         u8 source_max, sink_max;
 149
 150         source_max = 4;
 151         if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
 152             (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
 153                 source_max = 2;
 154
 155         sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
 156
 157         return min(source_max, sink_max);
 158 }
 159
 160 /*
 161  * The units on the numbers in the next two are... bizarre.  Examples will
 162  * make it clearer; this one parallels an example in the eDP spec.
 163  *
 164  * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
 165  *
 166  *     270000 * 1 * 8 / 10 == 216000
 167  *
 168  * The actual data capacity of that configuration is 2.16Gbit/s, so the
 169  * units are decakilobits.  ->clock in a drm_display_mode is in kilohertz -
 170  * or equivalently, kilopixels per second - so for 1680x1050R it'd be
 171  * 119000.  At 18bpp that's 2142000 kilobits per second.
 172  *
 173  * Thus the strange-looking division by 10 in intel_dp_link_required, to
 174  * get the result in decakilobits instead of kilobits.
 175  */
 176
 177 static int
 178 intel_dp_link_required(int pixel_clock, int bpp)
 179 {
 180         return (pixel_clock * bpp + 9) / 10;
 181 }
 182
 183 static int
 184 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 185 {
 186         return (max_link_clock * max_lanes * 8) / 10;
 187 }
 188
 189 static enum drm_mode_status
 190 intel_dp_mode_valid(struct drm_connector *connector,
 191                     struct drm_display_mode *mode)
 192 {
 193         struct intel_dp *intel_dp = intel_attached_dp(connector);
 194         struct intel_connector *intel_connector = to_intel_connector(connector);
 195         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 196         int target_clock = mode->clock;
 197         int max_rate, mode_rate, max_lanes, max_link_clock;
 198
 199         if (is_edp(intel_dp) && fixed_mode) {
 200                 if (mode->hdisplay > fixed_mode->hdisplay)
 201                         return MODE_PANEL;
 202
 203                 if (mode->vdisplay > fixed_mode->vdisplay)
 204                         return MODE_PANEL;
 205
 206                 target_clock = fixed_mode->clock;
 207         }
 208
 209         max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
 210         max_lanes = intel_dp_max_lane_count(intel_dp);
 211
 212         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 213         mode_rate = intel_dp_link_required(target_clock, 18);
 214
 215         if (mode_rate > max_rate)
 216                 return MODE_CLOCK_HIGH;
 217
 218         if (mode->clock < 10000)
 219                 return MODE_CLOCK_LOW;
 220
 221         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 222                 return MODE_H_ILLEGAL;
 223
 224         return MODE_OK;
 225 }
 226
 227 static uint32_t
 228 pack_aux(uint8_t *src, int src_bytes)
 229 {
 230         int     i;
 231         uint32_t v = 0;
 232
 233         if (src_bytes > 4)
 234                 src_bytes = 4;
 235         for (i = 0; i < src_bytes; i++)
 236                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 237         return v;
 238 }
 239
 240 static void
 241 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 242 {
 243         int i;
 244         if (dst_bytes > 4)
 245                 dst_bytes = 4;
 246         for (i = 0; i < dst_bytes; i++)
 247                 dst[i] = src >> ((3-i) * 8);
 248 }
 249
 250 /* hrawclock is 1/4 the FSB frequency */
 251 static int
 252 intel_hrawclk(struct drm_device *dev)
 253 {
 254         struct drm_i915_private *dev_priv = dev->dev_private;
 255         uint32_t clkcfg;
 256
 257         /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
 258         if (IS_VALLEYVIEW(dev))
 259                 return 200;
 260
 261         clkcfg = I915_READ(CLKCFG);
 262         switch (clkcfg & CLKCFG_FSB_MASK) {
 263         case CLKCFG_FSB_400:
 264                 return 100;
 265         case CLKCFG_FSB_533:
 266                 return 133;
 267         case CLKCFG_FSB_667:
 268                 return 166;
 269         case CLKCFG_FSB_800:
 270                 return 200;
 271         case CLKCFG_FSB_1067:
 272                 return 266;
 273         case CLKCFG_FSB_1333:
 274                 return 333;
 275         /* these two are just a guess; one of them might be right */
 276         case CLKCFG_FSB_1600:
 277         case CLKCFG_FSB_1600_ALT:
 278                 return 400;
 279         default:
 280                 return 133;
 281         }
 282 }
 283
 284 static void
 285 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
 286                                     struct intel_dp *intel_dp,
 287                                     struct edp_power_seq *out);
 288 static void
 289 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
 290                                               struct intel_dp *intel_dp,
 291                                               struct edp_power_seq *out);
 292
 293 static enum pipe
 294 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
 295 {
 296         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 297         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
 298         struct drm_device *dev = intel_dig_port->base.base.dev;
 299         struct drm_i915_private *dev_priv = dev->dev_private;
 300         enum port port = intel_dig_port->port;
 301         enum pipe pipe;
 302
 303         /* modeset should have pipe */
 304         if (crtc)
 305                 return to_intel_crtc(crtc)->pipe;
 306
 307         /* init time, try to find a pipe with this port selected */
 308         for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
 309                 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
 310                         PANEL_PORT_SELECT_MASK;
 311                 if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B)
 312                         return pipe;
 313                 if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C)
 314                         return pipe;
 315         }
 316
 317         /* shrug */
 318         return PIPE_A;
 319 }
 320
 321 static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
 322 {
 323         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 324
 325         if (HAS_PCH_SPLIT(dev))
 326                 return PCH_PP_CONTROL;
 327         else
 328                 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
 329 }
 330
 331 static u32 _pp_stat_reg(struct intel_dp *intel_dp)
 332 {
 333         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 334
 335         if (HAS_PCH_SPLIT(dev))
 336                 return PCH_PP_STATUS;
 337         else
 338                 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
 339 }
 340
 341 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
 342    This function only applicable when panel PM state is not to be tracked */
 343 static int edp_notify_handler(struct notifier_block *this, unsigned long code,
 344                               void *unused)
 345 {
 346         struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
 347                                                  edp_notifier);
 348         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 349         struct drm_i915_private *dev_priv = dev->dev_private;
 350         u32 pp_div;
 351         u32 pp_ctrl_reg, pp_div_reg;
 352         enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
 353
 354         if (!is_edp(intel_dp) || code != SYS_RESTART)
 355                 return 0;
 356
 357         if (IS_VALLEYVIEW(dev)) {
 358                 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
 359                 pp_div_reg  = VLV_PIPE_PP_DIVISOR(pipe);
 360                 pp_div = I915_READ(pp_div_reg);
 361                 pp_div &= PP_REFERENCE_DIVIDER_MASK;
 362
 363                 /* 0x1F write to PP_DIV_REG sets max cycle delay */
 364                 I915_WRITE(pp_div_reg, pp_div | 0x1F);
 365                 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
 366                 msleep(intel_dp->panel_power_cycle_delay);
 367         }
 368
 369         return 0;
 370 }
 371
 372 static bool edp_have_panel_power(struct intel_dp *intel_dp)
 373 {
 374         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 375         struct drm_i915_private *dev_priv = dev->dev_private;
 376
 377         return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
 378 }
 379
 380 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
 381 {
 382         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 383         struct drm_i915_private *dev_priv = dev->dev_private;
 384         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 385         struct intel_encoder *intel_encoder = &intel_dig_port->base;
 386         enum intel_display_power_domain power_domain;
 387
 388         power_domain = intel_display_port_power_domain(intel_encoder);
 389         return intel_display_power_enabled(dev_priv, power_domain) &&
 390                (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
 391 }
 392
 393 static void
 394 intel_dp_check_edp(struct intel_dp *intel_dp)
 395 {
 396         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 397         struct drm_i915_private *dev_priv = dev->dev_private;
 398
 399         if (!is_edp(intel_dp))
 400                 return;
 401
 402         if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
 403                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
 404                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
 405                               I915_READ(_pp_stat_reg(intel_dp)),
 406                               I915_READ(_pp_ctrl_reg(intel_dp)));
 407         }
 408 }
 409
 410 static uint32_t
 411 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
 412 {
 413         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 414         struct drm_device *dev = intel_dig_port->base.base.dev;
 415         struct drm_i915_private *dev_priv = dev->dev_private;
 416         uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 417         uint32_t status;
 418         bool done;
 419
 420 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 421         if (has_aux_irq)
 422                 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
 423                                           msecs_to_jiffies_timeout(10));
 424         else
 425                 done = wait_for_atomic(C, 10) == 0;
 426         if (!done)
 427                 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
 428                           has_aux_irq);
 429 #undef C
 430
 431         return status;
 432 }
 433
 434 static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 435 {
 436         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 437         struct drm_device *dev = intel_dig_port->base.base.dev;
 438
 439         /*
 440          * The clock divider is based off the hrawclk, and would like to run at
 441          * 2MHz.  So, take the hrawclk value and divide by 2 and use that
 442          */
 443         return index ? 0 : intel_hrawclk(dev) / 2;
 444 }
 445
 446 static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 447 {
 448         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 449         struct drm_device *dev = intel_dig_port->base.base.dev;
 450
 451         if (index)
 452                 return 0;
 453
 454         if (intel_dig_port->port == PORT_A) {
 455                 if (IS_GEN6(dev) || IS_GEN7(dev))
 456                         return 200; /* SNB & IVB eDP input clock at 400Mhz */
 457                 else
 458                         return 225; /* eDP input clock at 450Mhz */
 459         } else {
 460                 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
 461         }
 462 }
 463
 464 static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 465 {
 466         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 467         struct drm_device *dev = intel_dig_port->base.base.dev;
 468         struct drm_i915_private *dev_priv = dev->dev_private;
 469
 470         if (intel_dig_port->port == PORT_A) {
 471                 if (index)
 472                         return 0;
 473                 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
 474         } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 475                 /* Workaround for non-ULT HSW */
 476                 switch (index) {
 477                 case 0: return 63;
 478                 case 1: return 72;
 479                 default: return 0;
 480                 }
 481         } else  {
 482                 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
 483         }
 484 }
 485
 486 static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 487 {
 488         return index ? 0 : 100;
 489 }
 490
 491 static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
 492                                       bool has_aux_irq,
 493                                       int send_bytes,
 494                                       uint32_t aux_clock_divider)
 495 {
 496         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 497         struct drm_device *dev = intel_dig_port->base.base.dev;
 498         uint32_t precharge, timeout;
 499
 500         if (IS_GEN6(dev))
 501                 precharge = 3;
 502         else
 503                 precharge = 5;
 504
 505         if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
 506                 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
 507         else
 508                 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
 509
 510         return DP_AUX_CH_CTL_SEND_BUSY |
 511                DP_AUX_CH_CTL_DONE |
 512                (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
 513                DP_AUX_CH_CTL_TIME_OUT_ERROR |
 514                timeout |
 515                DP_AUX_CH_CTL_RECEIVE_ERROR |
 516                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 517                (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 518                (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
 519 }
 520
 521 static int
 522 intel_dp_aux_ch(struct intel_dp *intel_dp,
 523                 uint8_t *send, int send_bytes,
 524                 uint8_t *recv, int recv_size)
 525 {
 526         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 527         struct drm_device *dev = intel_dig_port->base.base.dev;
 528         struct drm_i915_private *dev_priv = dev->dev_private;
 529         uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 530         uint32_t ch_data = ch_ctl + 4;
 531         uint32_t aux_clock_divider;
 532         int i, ret, recv_bytes;
 533         uint32_t status;
 534         int try, clock = 0;
 535         bool has_aux_irq = HAS_AUX_IRQ(dev);
 536         bool vdd;
 537
 538         vdd = _edp_panel_vdd_on(intel_dp);
 539
 540         /* dp aux is extremely sensitive to irq latency, hence request the
 541          * lowest possible wakeup latency and so prevent the cpu from going into
 542          * deep sleep states.
 543          */
 544         pm_qos_update_request(&dev_priv->pm_qos, 0);
 545
 546         intel_dp_check_edp(intel_dp);
 547
 548         intel_aux_display_runtime_get(dev_priv);
 549
 550         /* Try to wait for any previous AUX channel activity */
 551         for (try = 0; try < 3; try++) {
 552                 status = I915_READ_NOTRACE(ch_ctl);
 553                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 554                         break;
 555                 msleep(1);
 556         }
 557
 558         if (try == 3) {
 559                 WARN(1, "dp_aux_ch not started status 0x%08x\n",
 560                      I915_READ(ch_ctl));
 561                 ret = -EBUSY;
 562                 goto out;
 563         }
 564
 565         /* Only 5 data registers! */
 566         if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
 567                 ret = -E2BIG;
 568                 goto out;
 569         }
 570
 571         while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
 572                 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
 573                                                           has_aux_irq,
 574                                                           send_bytes,
 575                                                           aux_clock_divider);
 576
 577                 /* Must try at least 3 times according to DP spec */
 578                 for (try = 0; try < 5; try++) {
 579                         /* Load the send data into the aux channel data registers */
 580                         for (i = 0; i < send_bytes; i += 4)
 581                                 I915_WRITE(ch_data + i,
 582                                            pack_aux(send + i, send_bytes - i));
 583
 584                         /* Send the command and wait for it to complete */
 585                         I915_WRITE(ch_ctl, send_ctl);
 586
 587                         status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
 588
 589                         /* Clear done status and any errors */
 590                         I915_WRITE(ch_ctl,
 591                                    status |
 592                                    DP_AUX_CH_CTL_DONE |
 593                                    DP_AUX_CH_CTL_TIME_OUT_ERROR |
 594                                    DP_AUX_CH_CTL_RECEIVE_ERROR);
 595
 596                         if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
 597                                       DP_AUX_CH_CTL_RECEIVE_ERROR))
 598                                 continue;
 599                         if (status & DP_AUX_CH_CTL_DONE)
 600                                 break;
 601                 }
 602                 if (status & DP_AUX_CH_CTL_DONE)
 603                         break;
 604         }
 605
 606         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
 607                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
 608                 ret = -EBUSY;
 609                 goto out;
 610         }
 611
 612         /* Check for timeout or receive error.
 613          * Timeouts occur when the sink is not connected
 614          */
 615         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 616                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
 617                 ret = -EIO;
 618                 goto out;
 619         }
 620
 621         /* Timeouts occur when the device isn't connected, so they're
 622          * "normal" -- don't fill the kernel log with these */
 623         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
 624                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
 625                 ret = -ETIMEDOUT;
 626                 goto out;
 627         }
 628
 629         /* Unload any bytes sent back from the other side */
 630         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
 631                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
 632         if (recv_bytes > recv_size)
 633                 recv_bytes = recv_size;
 634
 635         for (i = 0; i < recv_bytes; i += 4)
 636                 unpack_aux(I915_READ(ch_data + i),
 637                            recv + i, recv_bytes - i);
 638
 639         ret = recv_bytes;
 640 out:
 641         pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
 642         intel_aux_display_runtime_put(dev_priv);
 643
 644         if (vdd)
 645                 edp_panel_vdd_off(intel_dp, false);
 646
 647         return ret;
 648 }
 649
 650 #define BARE_ADDRESS_SIZE       3
 651 #define HEADER_SIZE             (BARE_ADDRESS_SIZE + 1)
 652 static ssize_t
 653 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
 654 {
 655         struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
 656         uint8_t txbuf[20], rxbuf[20];
 657         size_t txsize, rxsize;
 658         int ret;
 659
 660         txbuf[0] = msg->request << 4;
 661         txbuf[1] = msg->address >> 8;
 662         txbuf[2] = msg->address & 0xff;
 663         txbuf[3] = msg->size - 1;
 664
 665         switch (msg->request & ~DP_AUX_I2C_MOT) {
 666         case DP_AUX_NATIVE_WRITE:
 667         case DP_AUX_I2C_WRITE:
 668                 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
 669                 rxsize = 1;
 670
 671                 if (WARN_ON(txsize > 20))
 672                         return -E2BIG;
 673
 674                 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
 675
 676                 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
 677                 if (ret > 0) {
 678                         msg->reply = rxbuf[0] >> 4;
 679
 680                         /* Return payload size. */
 681                         ret = msg->size;
 682                 }
 683                 break;
 684
 685         case DP_AUX_NATIVE_READ:
 686         case DP_AUX_I2C_READ:
 687                 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
 688                 rxsize = msg->size + 1;
 689
 690                 if (WARN_ON(rxsize > 20))
 691                         return -E2BIG;
 692
 693                 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
 694                 if (ret > 0) {
 695                         msg->reply = rxbuf[0] >> 4;
 696                         /*
 697                          * Assume happy day, and copy the data. The caller is
 698                          * expected to check msg->reply before touching it.
 699                          *
 700                          * Return payload size.
 701                          */
 702                         ret--;
 703                         memcpy(msg->buffer, rxbuf + 1, ret);
 704                 }
 705                 break;
 706
 707         default:
 708                 ret = -EINVAL;
 709                 break;
 710         }
 711
 712         return ret;
 713 }
 714
 715 static void
 716 intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
 717 {
 718         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 719         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 720         enum port port = intel_dig_port->port;
 721         const char *name = NULL;
 722         int ret;
 723
 724         switch (port) {
 725         case PORT_A:
 726                 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
 727                 name = "DPDDC-A";
 728                 break;
 729         case PORT_B:
 730                 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
 731                 name = "DPDDC-B";
 732                 break;
 733         case PORT_C:
 734                 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
 735                 name = "DPDDC-C";
 736                 break;
 737         case PORT_D:
 738                 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
 739                 name = "DPDDC-D";
 740                 break;
 741         default:
 742                 BUG();
 743         }
 744
 745         if (!HAS_DDI(dev))
 746                 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
 747
 748         intel_dp->aux.name = name;
 749         intel_dp->aux.dev = dev->dev;
 750         intel_dp->aux.transfer = intel_dp_aux_transfer;
 751
 752         DRM_DEBUG_KMS("registering %s bus for %s\n", name,
 753                       connector->base.kdev->kobj.name);
 754
 755         ret = drm_dp_aux_register(&intel_dp->aux);
 756         if (ret < 0) {
 757                 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
 758                           name, ret);
 759                 return;
 760         }
 761
 762         ret = sysfs_create_link(&connector->base.kdev->kobj,
 763                                 &intel_dp->aux.ddc.dev.kobj,
 764                                 intel_dp->aux.ddc.dev.kobj.name);
 765         if (ret < 0) {
 766                 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
 767                 drm_dp_aux_unregister(&intel_dp->aux);
 768         }
 769 }
 770
 771 static void
 772 intel_dp_connector_unregister(struct intel_connector *intel_connector)
 773 {
 774         struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
 775
 776         if (!intel_connector->mst_port)
 777                 sysfs_remove_link(&intel_connector->base.kdev->kobj,
 778                                   intel_dp->aux.ddc.dev.kobj.name);
 779         intel_connector_unregister(intel_connector);
 780 }
 781
 782 static void
 783 hsw_dp_set_ddi_pll_sel(struct intel_crtc_config *pipe_config, int link_bw)
 784 {
 785         switch (link_bw) {
 786         case DP_LINK_BW_1_62:
 787                 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
 788                 break;
 789         case DP_LINK_BW_2_7:
 790                 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
 791                 break;
 792         case DP_LINK_BW_5_4:
 793                 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
 794                 break;
 795         }
 796 }
 797
 798 static void
 799 intel_dp_set_clock(struct intel_encoder *encoder,
 800                    struct intel_crtc_config *pipe_config, int link_bw)
 801 {
 802         struct drm_device *dev = encoder->base.dev;
 803         const struct dp_link_dpll *divisor = NULL;
 804         int i, count = 0;
 805
 806         if (IS_G4X(dev)) {
 807                 divisor = gen4_dpll;
 808                 count = ARRAY_SIZE(gen4_dpll);
 809         } else if (HAS_PCH_SPLIT(dev)) {
 810                 divisor = pch_dpll;
 811                 count = ARRAY_SIZE(pch_dpll);
 812         } else if (IS_CHERRYVIEW(dev)) {
 813                 divisor = chv_dpll;
 814                 count = ARRAY_SIZE(chv_dpll);
 815         } else if (IS_VALLEYVIEW(dev)) {
 816                 divisor = vlv_dpll;
 817                 count = ARRAY_SIZE(vlv_dpll);
 818         }
 819
 820         if (divisor && count) {
 821                 for (i = 0; i < count; i++) {
 822                         if (link_bw == divisor[i].link_bw) {
 823                                 pipe_config->dpll = divisor[i].dpll;
 824                                 pipe_config->clock_set = true;
 825                                 break;
 826                         }
 827                 }
 828         }
 829 }
 830
 831 bool
 832 intel_dp_compute_config(struct intel_encoder *encoder,
 833                         struct intel_crtc_config *pipe_config)
 834 {
 835         struct drm_device *dev = encoder->base.dev;
 836         struct drm_i915_private *dev_priv = dev->dev_private;
 837         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
 838         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 839         enum port port = dp_to_dig_port(intel_dp)->port;
 840         struct intel_crtc *intel_crtc = encoder->new_crtc;
 841         struct intel_connector *intel_connector = intel_dp->attached_connector;
 842         int lane_count, clock;
 843         int min_lane_count = 1;
 844         int max_lane_count = intel_dp_max_lane_count(intel_dp);
 845         /* Conveniently, the link BW constants become indices with a shift...*/
 846         int min_clock = 0;
 847         int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
 848         int bpp, mode_rate;
 849         static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
 850         int link_avail, link_clock;
 851
 852         if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
 853                 pipe_config->has_pch_encoder = true;
 854
 855         pipe_config->has_dp_encoder = true;
 856         pipe_config->has_drrs = false;
 857         pipe_config->has_audio = intel_dp->has_audio;
 858
 859         if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
 860                 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
 861                                        adjusted_mode);
 862                 if (!HAS_PCH_SPLIT(dev))
 863                         intel_gmch_panel_fitting(intel_crtc, pipe_config,
 864                                                  intel_connector->panel.fitting_mode);
 865                 else
 866                         intel_pch_panel_fitting(intel_crtc, pipe_config,
 867                                                 intel_connector->panel.fitting_mode);
 868         }
 869
 870         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
 871                 return false;
 872
 873         DRM_DEBUG_KMS("DP link computation with max lane count %i "
 874                       "max bw %02x pixel clock %iKHz\n",
 875                       max_lane_count, bws[max_clock],
 876                       adjusted_mode->crtc_clock);
 877
 878         /* Walk through all bpp values. Luckily they're all nicely spaced with 2
 879          * bpc in between. */
 880         bpp = pipe_config->pipe_bpp;
 881         if (is_edp(intel_dp)) {
 882                 if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) {
 883                         DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
 884                                       dev_priv->vbt.edp_bpp);
 885                         bpp = dev_priv->vbt.edp_bpp;
 886                 }
 887
 888                 if (IS_BROADWELL(dev)) {
 889                         /* Yes, it's an ugly hack. */
 890                         min_lane_count = max_lane_count;
 891                         DRM_DEBUG_KMS("forcing lane count to max (%u) on BDW\n",
 892                                       min_lane_count);
 893                 } else if (dev_priv->vbt.edp_lanes) {
 894                         min_lane_count = min(dev_priv->vbt.edp_lanes,
 895                                              max_lane_count);
 896                         DRM_DEBUG_KMS("using min %u lanes per VBT\n",
 897                                       min_lane_count);
 898                 }
 899
 900                 if (dev_priv->vbt.edp_rate) {
 901                         min_clock = min(dev_priv->vbt.edp_rate >> 3, max_clock);
 902                         DRM_DEBUG_KMS("using min %02x link bw per VBT\n",
 903                                       bws[min_clock]);
 904                 }
 905         }
 906
 907         for (; bpp >= 6*3; bpp -= 2*3) {
 908                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
 909                                                    bpp);
 910
 911                 for (clock = min_clock; clock <= max_clock; clock++) {
 912                         for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) {
 913                                 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
 914                                 link_avail = intel_dp_max_data_rate(link_clock,
 915                                                                     lane_count);
 916
 917                                 if (mode_rate <= link_avail) {
 918                                         goto found;
 919                                 }
 920                         }
 921                 }
 922         }
 923
 924         return false;
 925
 926 found:
 927         if (intel_dp->color_range_auto) {
 928                 /*
 929                  * See:
 930                  * CEA-861-E - 5.1 Default Encoding Parameters
 931                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
 932                  */
 933                 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
 934                         intel_dp->color_range = DP_COLOR_RANGE_16_235;
 935                 else
 936                         intel_dp->color_range = 0;
 937         }
 938
 939         if (intel_dp->color_range)
 940                 pipe_config->limited_color_range = true;
 941
 942         intel_dp->link_bw = bws[clock];
 943         intel_dp->lane_count = lane_count;
 944         pipe_config->pipe_bpp = bpp;
 945         pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
 946
 947         DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
 948                       intel_dp->link_bw, intel_dp->lane_count,
 949                       pipe_config->port_clock, bpp);
 950         DRM_DEBUG_KMS("DP link bw required %i available %i\n",
 951                       mode_rate, link_avail);
 952
 953         intel_link_compute_m_n(bpp, lane_count,
 954                                adjusted_mode->crtc_clock,
 955                                pipe_config->port_clock,
 956                                &pipe_config->dp_m_n);
 957
 958         if (intel_connector->panel.downclock_mode != NULL &&
 959                 intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) {
 960                         pipe_config->has_drrs = true;
 961                         intel_link_compute_m_n(bpp, lane_count,
 962                                 intel_connector->panel.downclock_mode->clock,
 963                                 pipe_config->port_clock,
 964                                 &pipe_config->dp_m2_n2);
 965         }
 966
 967         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
 968                 hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
 969         else
 970                 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
 971
 972         return true;
 973 }
 974
 975 static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
 976 {
 977         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 978         struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
 979         struct drm_device *dev = crtc->base.dev;
 980         struct drm_i915_private *dev_priv = dev->dev_private;
 981         u32 dpa_ctl;
 982
 983         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
 984         dpa_ctl = I915_READ(DP_A);
 985         dpa_ctl &= ~DP_PLL_FREQ_MASK;
 986
 987         if (crtc->config.port_clock == 162000) {
 988                 /* For a long time we've carried around a ILK-DevA w/a for the
 989                  * 160MHz clock. If we're really unlucky, it's still required.
 990                  */
 991                 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
 992                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
 993                 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
 994         } else {
 995                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
 996                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
 997         }
 998
 999         I915_WRITE(DP_A, dpa_ctl);
1000
1001         POSTING_READ(DP_A);
1002         udelay(500);
1003 }
1004
1005 static void intel_dp_prepare(struct intel_encoder *encoder)
1006 {
1007         struct drm_device *dev = encoder->base.dev;
1008         struct drm_i915_private *dev_priv = dev->dev_private;
1009         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1010         enum port port = dp_to_dig_port(intel_dp)->port;
1011         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1012         struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
1013
1014         /*
1015          * There are four kinds of DP registers:
1016          *
1017          *      IBX PCH
1018          *      SNB CPU
1019          *      IVB CPU
1020          *      CPT PCH
1021          *
1022          * IBX PCH and CPU are the same for almost everything,
1023          * except that the CPU DP PLL is configured in this
1024          * register
1025          *
1026          * CPT PCH is quite different, having many bits moved
1027          * to the TRANS_DP_CTL register instead. That
1028          * configuration happens (oddly) in ironlake_pch_enable
1029          */
1030
1031         /* Preserve the BIOS-computed detected bit. This is
1032          * supposed to be read-only.
1033          */
1034         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
1035
1036         /* Handle DP bits in common between all three register formats */
1037         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
1038         intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
1039
1040         if (crtc->config.has_audio) {
1041                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
1042                                  pipe_name(crtc->pipe));
1043                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
1044                 intel_write_eld(&encoder->base, adjusted_mode);
1045         }
1046
1047         /* Split out the IBX/CPU vs CPT settings */
1048
1049         if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1050                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1051                         intel_dp->DP |= DP_SYNC_HS_HIGH;
1052                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1053                         intel_dp->DP |= DP_SYNC_VS_HIGH;
1054                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1055
1056                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1057                         intel_dp->DP |= DP_ENHANCED_FRAMING;
1058
1059                 intel_dp->DP |= crtc->pipe << 29;
1060         } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1061                 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
1062                         intel_dp->DP |= intel_dp->color_range;
1063
1064                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1065                         intel_dp->DP |= DP_SYNC_HS_HIGH;
1066                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1067                         intel_dp->DP |= DP_SYNC_VS_HIGH;
1068                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1069
1070                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1071                         intel_dp->DP |= DP_ENHANCED_FRAMING;
1072
1073                 if (!IS_CHERRYVIEW(dev)) {
1074                         if (crtc->pipe == 1)
1075                                 intel_dp->DP |= DP_PIPEB_SELECT;
1076                 } else {
1077                         intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1078                 }
1079         } else {
1080                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1081         }
1082 }
1083
1084 #define IDLE_ON_MASK            (PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
1085 #define IDLE_ON_VALUE           (PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
1086
1087 #define IDLE_OFF_MASK           (PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
1088 #define IDLE_OFF_VALUE          (0     | PP_SEQUENCE_NONE | 0                     | 0)
1089
1090 #define IDLE_CYCLE_MASK         (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1091 #define IDLE_CYCLE_VALUE        (0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
1092
1093 static void wait_panel_status(struct intel_dp *intel_dp,
1094                                        u32 mask,
1095                                        u32 value)
1096 {
1097         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1098         struct drm_i915_private *dev_priv = dev->dev_private;
1099         u32 pp_stat_reg, pp_ctrl_reg;
1100
1101         pp_stat_reg = _pp_stat_reg(intel_dp);
1102         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1103
1104         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1105                         mask, value,
1106                         I915_READ(pp_stat_reg),
1107                         I915_READ(pp_ctrl_reg));
1108
1109         if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
1110                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1111                                 I915_READ(pp_stat_reg),
1112                                 I915_READ(pp_ctrl_reg));
1113         }
1114
1115         DRM_DEBUG_KMS("Wait complete\n");
1116 }
1117
1118 static void wait_panel_on(struct intel_dp *intel_dp)
1119 {
1120         DRM_DEBUG_KMS("Wait for panel power on\n");
1121         wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1122 }
1123
1124 static void wait_panel_off(struct intel_dp *intel_dp)
1125 {
1126         DRM_DEBUG_KMS("Wait for panel power off time\n");
1127         wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1128 }
1129
1130 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
1131 {
1132         DRM_DEBUG_KMS("Wait for panel power cycle\n");
1133
1134         /* When we disable the VDD override bit last we have to do the manual
1135          * wait. */
1136         wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1137                                        intel_dp->panel_power_cycle_delay);
1138
1139         wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1140 }
1141
1142 static void wait_backlight_on(struct intel_dp *intel_dp)
1143 {
1144         wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1145                                        intel_dp->backlight_on_delay);
1146 }
1147
1148 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
1149 {
1150         wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1151                                        intel_dp->backlight_off_delay);
1152 }
1153
1154 /* Read the current pp_control value, unlocking the register if it
1155  * is locked
1156  */
1157
1158 static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
1159 {
1160         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1161         struct drm_i915_private *dev_priv = dev->dev_private;
1162         u32 control;
1163
1164         control = I915_READ(_pp_ctrl_reg(intel_dp));
1165         control &= ~PANEL_UNLOCK_MASK;
1166         control |= PANEL_UNLOCK_REGS;
1167         return control;
1168 }
1169
1170 static bool _edp_panel_vdd_on(struct intel_dp *intel_dp)
1171 {
1172         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1173         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1174         struct intel_encoder *intel_encoder = &intel_dig_port->base;
1175         struct drm_i915_private *dev_priv = dev->dev_private;
1176         enum intel_display_power_domain power_domain;
1177         u32 pp;
1178         u32 pp_stat_reg, pp_ctrl_reg;
1179         bool need_to_disable = !intel_dp->want_panel_vdd;
1180
1181         if (!is_edp(intel_dp))
1182                 return false;
1183
1184         intel_dp->want_panel_vdd = true;
1185
1186         if (edp_have_panel_vdd(intel_dp))
1187                 return need_to_disable;
1188
1189         power_domain = intel_display_port_power_domain(intel_encoder);
1190         intel_display_power_get(dev_priv, power_domain);
1191
1192         DRM_DEBUG_KMS("Turning eDP VDD on\n");
1193
1194         if (!edp_have_panel_power(intel_dp))
1195                 wait_panel_power_cycle(intel_dp);
1196
1197         pp = ironlake_get_pp_control(intel_dp);
1198         pp |= EDP_FORCE_VDD;
1199
1200         pp_stat_reg = _pp_stat_reg(intel_dp);
1201         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1202
1203         I915_WRITE(pp_ctrl_reg, pp);
1204         POSTING_READ(pp_ctrl_reg);
1205         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1206                         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1207         /*
1208          * If the panel wasn't on, delay before accessing aux channel
1209          */
1210         if (!edp_have_panel_power(intel_dp)) {
1211                 DRM_DEBUG_KMS("eDP was not running\n");
1212                 msleep(intel_dp->panel_power_up_delay);
1213         }
1214
1215         return need_to_disable;
1216 }
1217
1218 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
1219 {
1220         if (is_edp(intel_dp)) {
1221                 bool vdd = _edp_panel_vdd_on(intel_dp);
1222
1223                 WARN(!vdd, "eDP VDD already requested on\n");
1224         }
1225 }
1226
1227 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
1228 {
1229         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1230         struct drm_i915_private *dev_priv = dev->dev_private;
1231         u32 pp;
1232         u32 pp_stat_reg, pp_ctrl_reg;
1233
1234         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
1235
1236         if (!intel_dp->want_panel_vdd && edp_have_panel_vdd(intel_dp)) {
1237                 struct intel_digital_port *intel_dig_port =
1238                                                 dp_to_dig_port(intel_dp);
1239                 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1240                 enum intel_display_power_domain power_domain;
1241
1242                 DRM_DEBUG_KMS("Turning eDP VDD off\n");
1243
1244                 pp = ironlake_get_pp_control(intel_dp);
1245                 pp &= ~EDP_FORCE_VDD;
1246
1247                 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1248                 pp_stat_reg = _pp_stat_reg(intel_dp);
1249
1250                 I915_WRITE(pp_ctrl_reg, pp);
1251                 POSTING_READ(pp_ctrl_reg);
1252
1253                 /* Make sure sequencer is idle before allowing subsequent activity */
1254                 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1255                 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1256
1257                 if ((pp & POWER_TARGET_ON) == 0)
1258                         intel_dp->last_power_cycle = jiffies;
1259
1260                 power_domain = intel_display_port_power_domain(intel_encoder);
1261                 intel_display_power_put(dev_priv, power_domain);
1262         }
1263 }
1264
1265 static void edp_panel_vdd_work(struct work_struct *__work)
1266 {
1267         struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1268                                                  struct intel_dp, panel_vdd_work);
1269         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1270
1271         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
1272         edp_panel_vdd_off_sync(intel_dp);
1273         drm_modeset_unlock(&dev->mode_config.connection_mutex);
1274 }
1275
1276 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
1277 {
1278         unsigned long delay;
1279
1280         /*
1281          * Queue the timer to fire a long time from now (relative to the power
1282          * down delay) to keep the panel power up across a sequence of
1283          * operations.
1284          */
1285         delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
1286         schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
1287 }
1288
1289 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1290 {
1291         if (!is_edp(intel_dp))
1292                 return;
1293
1294         WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1295
1296         intel_dp->want_panel_vdd = false;
1297
1298         if (sync)
1299                 edp_panel_vdd_off_sync(intel_dp);
1300         else
1301                 edp_panel_vdd_schedule_off(intel_dp);
1302 }
1303
1304 void intel_edp_panel_on(struct intel_dp *intel_dp)
1305 {
1306         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1307         struct drm_i915_private *dev_priv = dev->dev_private;
1308         u32 pp;
1309         u32 pp_ctrl_reg;
1310
1311         if (!is_edp(intel_dp))
1312                 return;
1313
1314         DRM_DEBUG_KMS("Turn eDP power on\n");
1315
1316         if (edp_have_panel_power(intel_dp)) {
1317                 DRM_DEBUG_KMS("eDP power already on\n");
1318                 return;
1319         }
1320
1321         wait_panel_power_cycle(intel_dp);
1322
1323         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1324         pp = ironlake_get_pp_control(intel_dp);
1325         if (IS_GEN5(dev)) {
1326                 /* ILK workaround: disable reset around power sequence */
1327                 pp &= ~PANEL_POWER_RESET;
1328                 I915_WRITE(pp_ctrl_reg, pp);
1329                 POSTING_READ(pp_ctrl_reg);
1330         }
1331
1332         pp |= POWER_TARGET_ON;
1333         if (!IS_GEN5(dev))
1334                 pp |= PANEL_POWER_RESET;
1335
1336         I915_WRITE(pp_ctrl_reg, pp);
1337         POSTING_READ(pp_ctrl_reg);
1338
1339         wait_panel_on(intel_dp);
1340         intel_dp->last_power_on = jiffies;
1341
1342         if (IS_GEN5(dev)) {
1343                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1344                 I915_WRITE(pp_ctrl_reg, pp);
1345                 POSTING_READ(pp_ctrl_reg);
1346         }
1347 }
1348
1349 void intel_edp_panel_off(struct intel_dp *intel_dp)
1350 {
1351         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1352         struct intel_encoder *intel_encoder = &intel_dig_port->base;
1353         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1354         struct drm_i915_private *dev_priv = dev->dev_private;
1355         enum intel_display_power_domain power_domain;
1356         u32 pp;
1357         u32 pp_ctrl_reg;
1358
1359         if (!is_edp(intel_dp))
1360                 return;
1361
1362         DRM_DEBUG_KMS("Turn eDP power off\n");
1363
1364         WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1365
1366         pp = ironlake_get_pp_control(intel_dp);
1367         /* We need to switch off panel power _and_ force vdd, for otherwise some
1368          * panels get very unhappy and cease to work. */
1369         pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1370                 EDP_BLC_ENABLE);
1371
1372         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1373
1374         intel_dp->want_panel_vdd = false;
1375
1376         I915_WRITE(pp_ctrl_reg, pp);
1377         POSTING_READ(pp_ctrl_reg);
1378
1379         intel_dp->last_power_cycle = jiffies;
1380         wait_panel_off(intel_dp);
1381
1382         /* We got a reference when we enabled the VDD. */
1383         power_domain = intel_display_port_power_domain(intel_encoder);
1384         intel_display_power_put(dev_priv, power_domain);
1385 }
1386
1387 void intel_edp_backlight_on(struct intel_dp *intel_dp)
1388 {
1389         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1390         struct drm_device *dev = intel_dig_port->base.base.dev;
1391         struct drm_i915_private *dev_priv = dev->dev_private;
1392         u32 pp;
1393         u32 pp_ctrl_reg;
1394
1395         if (!is_edp(intel_dp))
1396                 return;
1397
1398         DRM_DEBUG_KMS("\n");
1399
1400         intel_panel_enable_backlight(intel_dp->attached_connector);
1401
1402         /*
1403          * If we enable the backlight right away following a panel power
1404          * on, we may see slight flicker as the panel syncs with the eDP
1405          * link.  So delay a bit to make sure the image is solid before
1406          * allowing it to appear.
1407          */
1408         wait_backlight_on(intel_dp);
1409         pp = ironlake_get_pp_control(intel_dp);
1410         pp |= EDP_BLC_ENABLE;
1411
1412         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1413
1414         I915_WRITE(pp_ctrl_reg, pp);
1415         POSTING_READ(pp_ctrl_reg);
1416 }
1417
1418 void intel_edp_backlight_off(struct intel_dp *intel_dp)
1419 {
1420         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1421         struct drm_i915_private *dev_priv = dev->dev_private;
1422         u32 pp;
1423         u32 pp_ctrl_reg;
1424
1425         if (!is_edp(intel_dp))
1426                 return;
1427
1428         DRM_DEBUG_KMS("\n");
1429         pp = ironlake_get_pp_control(intel_dp);
1430         pp &= ~EDP_BLC_ENABLE;
1431
1432         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1433
1434         I915_WRITE(pp_ctrl_reg, pp);
1435         POSTING_READ(pp_ctrl_reg);
1436         intel_dp->last_backlight_off = jiffies;
1437
1438         edp_wait_backlight_off(intel_dp);
1439
1440         intel_panel_disable_backlight(intel_dp->attached_connector);
1441 }
1442
1443 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1444 {
1445         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1446         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1447         struct drm_device *dev = crtc->dev;
1448         struct drm_i915_private *dev_priv = dev->dev_private;
1449         u32 dpa_ctl;
1450
1451         assert_pipe_disabled(dev_priv,
1452                              to_intel_crtc(crtc)->pipe);
1453
1454         DRM_DEBUG_KMS("\n");
1455         dpa_ctl = I915_READ(DP_A);
1456         WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1457         WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1458
1459         /* We don't adjust intel_dp->DP while tearing down the link, to
1460          * facilitate link retraining (e.g. after hotplug). Hence clear all
1461          * enable bits here to ensure that we don't enable too much. */
1462         intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1463         intel_dp->DP |= DP_PLL_ENABLE;
1464         I915_WRITE(DP_A, intel_dp->DP);
1465         POSTING_READ(DP_A);
1466         udelay(200);
1467 }
1468
1469 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1470 {
1471         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1472         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1473         struct drm_device *dev = crtc->dev;
1474         struct drm_i915_private *dev_priv = dev->dev_private;
1475         u32 dpa_ctl;
1476
1477         assert_pipe_disabled(dev_priv,
1478                              to_intel_crtc(crtc)->pipe);
1479
1480         dpa_ctl = I915_READ(DP_A);
1481         WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1482              "dp pll off, should be on\n");
1483         WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1484
1485         /* We can't rely on the value tracked for the DP register in
1486          * intel_dp->DP because link_down must not change that (otherwise link
1487          * re-training will fail. */
1488         dpa_ctl &= ~DP_PLL_ENABLE;
1489         I915_WRITE(DP_A, dpa_ctl);
1490         POSTING_READ(DP_A);
1491         udelay(200);
1492 }
1493
1494 /* If the sink supports it, try to set the power state appropriately */
1495 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1496 {
1497         int ret, i;
1498
1499         /* Should have a valid DPCD by this point */
1500         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1501                 return;
1502
1503         if (mode != DRM_MODE_DPMS_ON) {
1504                 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1505                                          DP_SET_POWER_D3);
1506                 if (ret != 1)
1507                         DRM_DEBUG_DRIVER("failed to write sink power state\n");
1508         } else {
1509                 /*
1510                  * When turning on, we need to retry for 1ms to give the sink
1511                  * time to wake up.
1512                  */
1513                 for (i = 0; i < 3; i++) {
1514                         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1515                                                  DP_SET_POWER_D0);
1516                         if (ret == 1)
1517                                 break;
1518                         msleep(1);
1519                 }
1520         }
1521 }
1522
1523 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1524                                   enum pipe *pipe)
1525 {
1526         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1527         enum port port = dp_to_dig_port(intel_dp)->port;
1528         struct drm_device *dev = encoder->base.dev;
1529         struct drm_i915_private *dev_priv = dev->dev_private;
1530         enum intel_display_power_domain power_domain;
1531         u32 tmp;
1532
1533         power_domain = intel_display_port_power_domain(encoder);
1534         if (!intel_display_power_enabled(dev_priv, power_domain))
1535                 return false;
1536
1537         tmp = I915_READ(intel_dp->output_reg);
1538
1539         if (!(tmp & DP_PORT_EN))
1540                 return false;
1541
1542         if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1543                 *pipe = PORT_TO_PIPE_CPT(tmp);
1544         } else if (IS_CHERRYVIEW(dev)) {
1545                 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
1546         } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1547                 *pipe = PORT_TO_PIPE(tmp);
1548         } else {
1549                 u32 trans_sel;
1550                 u32 trans_dp;
1551                 int i;
1552
1553                 switch (intel_dp->output_reg) {
1554                 case PCH_DP_B:
1555                         trans_sel = TRANS_DP_PORT_SEL_B;
1556                         break;
1557                 case PCH_DP_C:
1558                         trans_sel = TRANS_DP_PORT_SEL_C;
1559                         break;
1560                 case PCH_DP_D:
1561                         trans_sel = TRANS_DP_PORT_SEL_D;
1562                         break;
1563                 default:
1564                         return true;
1565                 }
1566
1567                 for_each_pipe(i) {
1568                         trans_dp = I915_READ(TRANS_DP_CTL(i));
1569                         if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1570                                 *pipe = i;
1571                                 return true;
1572                         }
1573                 }
1574
1575                 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1576                               intel_dp->output_reg);
1577         }
1578
1579         return true;
1580 }
1581
1582 static void intel_dp_get_config(struct intel_encoder *encoder,
1583                                 struct intel_crtc_config *pipe_config)
1584 {
1585         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1586         u32 tmp, flags = 0;
1587         struct drm_device *dev = encoder->base.dev;
1588         struct drm_i915_private *dev_priv = dev->dev_private;
1589         enum port port = dp_to_dig_port(intel_dp)->port;
1590         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1591         int dotclock;
1592
1593         tmp = I915_READ(intel_dp->output_reg);
1594         if (tmp & DP_AUDIO_OUTPUT_ENABLE)
1595                 pipe_config->has_audio = true;
1596
1597         if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
1598                 if (tmp & DP_SYNC_HS_HIGH)
1599                         flags |= DRM_MODE_FLAG_PHSYNC;
1600                 else
1601                         flags |= DRM_MODE_FLAG_NHSYNC;
1602
1603                 if (tmp & DP_SYNC_VS_HIGH)
1604                         flags |= DRM_MODE_FLAG_PVSYNC;
1605                 else
1606                         flags |= DRM_MODE_FLAG_NVSYNC;
1607         } else {
1608                 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1609                 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1610                         flags |= DRM_MODE_FLAG_PHSYNC;
1611                 else
1612                         flags |= DRM_MODE_FLAG_NHSYNC;
1613
1614                 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1615                         flags |= DRM_MODE_FLAG_PVSYNC;
1616                 else
1617                         flags |= DRM_MODE_FLAG_NVSYNC;
1618         }
1619
1620         pipe_config->adjusted_mode.flags |= flags;
1621
1622         pipe_config->has_dp_encoder = true;
1623
1624         intel_dp_get_m_n(crtc, pipe_config);
1625
1626         if (port == PORT_A) {
1627                 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1628                         pipe_config->port_clock = 162000;
1629                 else
1630                         pipe_config->port_clock = 270000;
1631         }
1632
1633         dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1634                                             &pipe_config->dp_m_n);
1635
1636         if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1637                 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1638
1639         pipe_config->adjusted_mode.crtc_clock = dotclock;
1640
1641         if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1642             pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1643                 /*
1644                  * This is a big fat ugly hack.
1645                  *
1646                  * Some machines in UEFI boot mode provide us a VBT that has 18
1647                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1648                  * unknown we fail to light up. Yet the same BIOS boots up with
1649                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1650                  * max, not what it tells us to use.
1651                  *
1652                  * Note: This will still be broken if the eDP panel is not lit
1653                  * up by the BIOS, and thus we can't get the mode at module
1654                  * load.
1655                  */
1656                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1657                               pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1658                 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1659         }
1660 }
1661
1662 static bool is_edp_psr(struct intel_dp *intel_dp)
1663 {
1664         return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
1665 }
1666
1667 static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1668 {
1669         struct drm_i915_private *dev_priv = dev->dev_private;
1670
1671         if (!HAS_PSR(dev))
1672                 return false;
1673
1674         return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
1675 }
1676
1677 static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1678                                     struct edp_vsc_psr *vsc_psr)
1679 {
1680         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1681         struct drm_device *dev = dig_port->base.base.dev;
1682         struct drm_i915_private *dev_priv = dev->dev_private;
1683         struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1684         u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1685         u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1686         uint32_t *data = (uint32_t *) vsc_psr;
1687         unsigned int i;
1688
1689         /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1690            the video DIP being updated before program video DIP data buffer
1691            registers for DIP being updated. */
1692         I915_WRITE(ctl_reg, 0);
1693         POSTING_READ(ctl_reg);
1694
1695         for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1696                 if (i < sizeof(struct edp_vsc_psr))
1697                         I915_WRITE(data_reg + i, *data++);
1698                 else
1699                         I915_WRITE(data_reg + i, 0);
1700         }
1701
1702         I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1703         POSTING_READ(ctl_reg);
1704 }
1705
1706 static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1707 {
1708         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1709         struct drm_i915_private *dev_priv = dev->dev_private;
1710         struct edp_vsc_psr psr_vsc;
1711
1712         /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1713         memset(&psr_vsc, 0, sizeof(psr_vsc));
1714         psr_vsc.sdp_header.HB0 = 0;
1715         psr_vsc.sdp_header.HB1 = 0x7;
1716         psr_vsc.sdp_header.HB2 = 0x2;
1717         psr_vsc.sdp_header.HB3 = 0x8;
1718         intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1719
1720         /* Avoid continuous PSR exit by masking memup and hpd */
1721         I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
1722                    EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
1723 }
1724
1725 static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1726 {
1727         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1728         struct drm_device *dev = dig_port->base.base.dev;
1729         struct drm_i915_private *dev_priv = dev->dev_private;
1730         uint32_t aux_clock_divider;
1731         int precharge = 0x3;
1732         int msg_size = 5;       /* Header(4) + Message(1) */
1733         bool only_standby = false;
1734
1735         aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
1736
1737         if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
1738                 only_standby = true;
1739
1740         /* Enable PSR in sink */
1741         if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby)
1742                 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1743                                    DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
1744         else
1745                 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1746                                    DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
1747
1748         /* Setup AUX registers */
1749         I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
1750         I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
1751         I915_WRITE(EDP_PSR_AUX_CTL(dev),
1752                    DP_AUX_CH_CTL_TIME_OUT_400us |
1753                    (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1754                    (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1755                    (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1756 }
1757
1758 static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1759 {
1760         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1761         struct drm_device *dev = dig_port->base.base.dev;
1762         struct drm_i915_private *dev_priv = dev->dev_private;
1763         uint32_t max_sleep_time = 0x1f;
1764         uint32_t idle_frames = 1;
1765         uint32_t val = 0x0;
1766         const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
1767         bool only_standby = false;
1768
1769         if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
1770                 only_standby = true;
1771
1772         if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby) {
1773                 val |= EDP_PSR_LINK_STANDBY;
1774                 val |= EDP_PSR_TP2_TP3_TIME_0us;
1775                 val |= EDP_PSR_TP1_TIME_0us;
1776                 val |= EDP_PSR_SKIP_AUX_EXIT;
1777                 val |= IS_BROADWELL(dev) ? BDW_PSR_SINGLE_FRAME : 0;
1778         } else
1779                 val |= EDP_PSR_LINK_DISABLE;
1780
1781         I915_WRITE(EDP_PSR_CTL(dev), val |
1782                    (IS_BROADWELL(dev) ? 0 : link_entry_time) |
1783                    max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1784                    idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1785                    EDP_PSR_ENABLE);
1786 }
1787
1788 static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1789 {
1790         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1791         struct drm_device *dev = dig_port->base.base.dev;
1792         struct drm_i915_private *dev_priv = dev->dev_private;
1793         struct drm_crtc *crtc = dig_port->base.base.crtc;
1794         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1795
1796         lockdep_assert_held(&dev_priv->psr.lock);
1797         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
1798         WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
1799
1800         dev_priv->psr.source_ok = false;
1801
1802         if (IS_HASWELL(dev) && dig_port->port != PORT_A) {
1803                 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
1804                 return false;
1805         }
1806
1807         if (!i915.enable_psr) {
1808                 DRM_DEBUG_KMS("PSR disable by flag\n");
1809                 return false;
1810         }
1811
1812         /* Below limitations aren't valid for Broadwell */
1813         if (IS_BROADWELL(dev))
1814                 goto out;
1815
1816         if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1817             S3D_ENABLE) {
1818                 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
1819                 return false;
1820         }
1821
1822         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
1823                 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
1824                 return false;
1825         }
1826
1827  out:
1828         dev_priv->psr.source_ok = true;
1829         return true;
1830 }
1831
1832 static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
1833 {
1834         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1835         struct drm_device *dev = intel_dig_port->base.base.dev;
1836         struct drm_i915_private *dev_priv = dev->dev_private;
1837
1838         WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
1839         WARN_ON(dev_priv->psr.active);
1840         lockdep_assert_held(&dev_priv->psr.lock);
1841
1842         /* Enable PSR on the panel */
1843         intel_edp_psr_enable_sink(intel_dp);
1844
1845         /* Enable PSR on the host */
1846         intel_edp_psr_enable_source(intel_dp);
1847
1848         dev_priv->psr.active = true;
1849 }
1850
1851 void intel_edp_psr_enable(struct intel_dp *intel_dp)
1852 {
1853         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1854         struct drm_i915_private *dev_priv = dev->dev_private;
1855
1856         if (!HAS_PSR(dev)) {
1857                 DRM_DEBUG_KMS("PSR not supported on this platform\n");
1858                 return;
1859         }
1860
1861         if (!is_edp_psr(intel_dp)) {
1862                 DRM_DEBUG_KMS("PSR not supported by this panel\n");
1863                 return;
1864         }
1865
1866         mutex_lock(&dev_priv->psr.lock);
1867         if (dev_priv->psr.enabled) {
1868                 DRM_DEBUG_KMS("PSR already in use\n");
1869                 mutex_unlock(&dev_priv->psr.lock);
1870                 return;
1871         }
1872
1873         dev_priv->psr.busy_frontbuffer_bits = 0;
1874
1875         /* Setup PSR once */
1876         intel_edp_psr_setup(intel_dp);
1877
1878         if (intel_edp_psr_match_conditions(intel_dp))
1879                 dev_priv->psr.enabled = intel_dp;
1880         mutex_unlock(&dev_priv->psr.lock);
1881 }
1882
1883 void intel_edp_psr_disable(struct intel_dp *intel_dp)
1884 {
1885         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1886         struct drm_i915_private *dev_priv = dev->dev_private;
1887
1888         mutex_lock(&dev_priv->psr.lock);
1889         if (!dev_priv->psr.enabled) {
1890                 mutex_unlock(&dev_priv->psr.lock);
1891                 return;
1892         }
1893
1894         if (dev_priv->psr.active) {
1895                 I915_WRITE(EDP_PSR_CTL(dev),
1896                            I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
1897
1898                 /* Wait till PSR is idle */
1899                 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
1900                                EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
1901                         DRM_ERROR("Timed out waiting for PSR Idle State\n");
1902
1903                 dev_priv->psr.active = false;
1904         } else {
1905                 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
1906         }
1907
1908         dev_priv->psr.enabled = NULL;
1909         mutex_unlock(&dev_priv->psr.lock);
1910
1911         cancel_delayed_work_sync(&dev_priv->psr.work);
1912 }
1913
1914 static void intel_edp_psr_work(struct work_struct *work)
1915 {
1916         struct drm_i915_private *dev_priv =
1917                 container_of(work, typeof(*dev_priv), psr.work.work);
1918         struct intel_dp *intel_dp = dev_priv->psr.enabled;
1919
1920         mutex_lock(&dev_priv->psr.lock);
1921         intel_dp = dev_priv->psr.enabled;
1922
1923         if (!intel_dp)
1924                 goto unlock;
1925
1926         /*
1927          * The delayed work can race with an invalidate hence we need to
1928          * recheck. Since psr_flush first clears this and then reschedules we
1929          * won't ever miss a flush when bailing out here.
1930          */
1931         if (dev_priv->psr.busy_frontbuffer_bits)
1932                 goto unlock;
1933
1934         intel_edp_psr_do_enable(intel_dp);
1935 unlock:
1936         mutex_unlock(&dev_priv->psr.lock);
1937 }
1938
1939 static void intel_edp_psr_do_exit(struct drm_device *dev)
1940 {
1941         struct drm_i915_private *dev_priv = dev->dev_private;
1942
1943         if (dev_priv->psr.active) {
1944                 u32 val = I915_READ(EDP_PSR_CTL(dev));
1945
1946                 WARN_ON(!(val & EDP_PSR_ENABLE));
1947
1948                 I915_WRITE(EDP_PSR_CTL(dev), val & ~EDP_PSR_ENABLE);
1949
1950                 dev_priv->psr.active = false;
1951         }
1952
1953 }
1954
1955 void intel_edp_psr_invalidate(struct drm_device *dev,
1956                               unsigned frontbuffer_bits)
1957 {
1958         struct drm_i915_private *dev_priv = dev->dev_private;
1959         struct drm_crtc *crtc;
1960         enum pipe pipe;
1961
1962         mutex_lock(&dev_priv->psr.lock);
1963         if (!dev_priv->psr.enabled) {
1964                 mutex_unlock(&dev_priv->psr.lock);
1965                 return;
1966         }
1967
1968         crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
1969         pipe = to_intel_crtc(crtc)->pipe;
1970
1971         intel_edp_psr_do_exit(dev);
1972
1973         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
1974
1975         dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits;
1976         mutex_unlock(&dev_priv->psr.lock);
1977 }
1978
1979 void intel_edp_psr_flush(struct drm_device *dev,
1980                          unsigned frontbuffer_bits)
1981 {
1982         struct drm_i915_private *dev_priv = dev->dev_private;
1983         struct drm_crtc *crtc;
1984         enum pipe pipe;
1985
1986         mutex_lock(&dev_priv->psr.lock);
1987         if (!dev_priv->psr.enabled) {
1988                 mutex_unlock(&dev_priv->psr.lock);
1989                 return;
1990         }
1991
1992         crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
1993         pipe = to_intel_crtc(crtc)->pipe;
1994         dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits;
1995
1996         /*
1997          * On Haswell sprite plane updates don't result in a psr invalidating
1998          * signal in the hardware. Which means we need to manually fake this in
1999          * software for all flushes, not just when we've seen a preceding
2000          * invalidation through frontbuffer rendering.
2001          */
2002         if (IS_HASWELL(dev) &&
2003             (frontbuffer_bits & INTEL_FRONTBUFFER_SPRITE(pipe)))
2004                 intel_edp_psr_do_exit(dev);
2005
2006         if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
2007                 schedule_delayed_work(&dev_priv->psr.work,
2008                                       msecs_to_jiffies(100));
2009         mutex_unlock(&dev_priv->psr.lock);
2010 }
2011
2012 void intel_edp_psr_init(struct drm_device *dev)
2013 {
2014         struct drm_i915_private *dev_priv = dev->dev_private;
2015
2016         INIT_DELAYED_WORK(&dev_priv->psr.work, intel_edp_psr_work);
2017         mutex_init(&dev_priv->psr.lock);
2018 }
2019
2020 static void intel_disable_dp(struct intel_encoder *encoder)
2021 {
2022         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2023         enum port port = dp_to_dig_port(intel_dp)->port;
2024         struct drm_device *dev = encoder->base.dev;
2025
2026         /* Make sure the panel is off before trying to change the mode. But also
2027          * ensure that we have vdd while we switch off the panel. */
2028         intel_edp_panel_vdd_on(intel_dp);
2029         intel_edp_backlight_off(intel_dp);
2030         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2031         intel_edp_panel_off(intel_dp);
2032
2033         /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
2034         if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
2035                 intel_dp_link_down(intel_dp);
2036 }
2037
2038 static void g4x_post_disable_dp(struct intel_encoder *encoder)
2039 {
2040         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2041         enum port port = dp_to_dig_port(intel_dp)->port;
2042
2043         if (port != PORT_A)
2044                 return;
2045
2046         intel_dp_link_down(intel_dp);
2047         ironlake_edp_pll_off(intel_dp);
2048 }
2049
2050 static void vlv_post_disable_dp(struct intel_encoder *encoder)
2051 {
2052         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2053
2054         intel_dp_link_down(intel_dp);
2055 }
2056
2057 static void chv_post_disable_dp(struct intel_encoder *encoder)
2058 {
2059         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2060         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2061         struct drm_device *dev = encoder->base.dev;
2062         struct drm_i915_private *dev_priv = dev->dev_private;
2063         struct intel_crtc *intel_crtc =
2064                 to_intel_crtc(encoder->base.crtc);
2065         enum dpio_channel ch = vlv_dport_to_channel(dport);
2066         enum pipe pipe = intel_crtc->pipe;
2067         u32 val;
2068
2069         intel_dp_link_down(intel_dp);
2070
2071         mutex_lock(&dev_priv->dpio_lock);
2072
2073         /* Propagate soft reset to data lane reset */
2074         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
2075         val |= CHV_PCS_REQ_SOFTRESET_EN;
2076         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2077
2078         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2079         val |= CHV_PCS_REQ_SOFTRESET_EN;
2080         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2081
2082         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2083         val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2084         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2085
2086         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
2087         val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2088         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
2089
2090         mutex_unlock(&dev_priv->dpio_lock);
2091 }
2092
2093 static void intel_enable_dp(struct intel_encoder *encoder)
2094 {
2095         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2096         struct drm_device *dev = encoder->base.dev;
2097         struct drm_i915_private *dev_priv = dev->dev_private;
2098         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
2099
2100         if (WARN_ON(dp_reg & DP_PORT_EN))
2101                 return;
2102
2103         intel_edp_panel_vdd_on(intel_dp);
2104         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2105         intel_dp_start_link_train(intel_dp);
2106         intel_edp_panel_on(intel_dp);
2107         edp_panel_vdd_off(intel_dp, true);
2108         intel_dp_complete_link_train(intel_dp);
2109         intel_dp_stop_link_train(intel_dp);
2110 }
2111
2112 static void g4x_enable_dp(struct intel_encoder *encoder)
2113 {
2114         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2115
2116         intel_enable_dp(encoder);
2117         intel_edp_backlight_on(intel_dp);
2118 }
2119
2120 static void vlv_enable_dp(struct intel_encoder *encoder)
2121 {
2122         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2123
2124         intel_edp_backlight_on(intel_dp);
2125 }
2126
2127 static void g4x_pre_enable_dp(struct intel_encoder *encoder)
2128 {
2129         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2130         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2131
2132         intel_dp_prepare(encoder);
2133
2134         /* Only ilk+ has port A */
2135         if (dport->port == PORT_A) {
2136                 ironlake_set_pll_cpu_edp(intel_dp);
2137                 ironlake_edp_pll_on(intel_dp);
2138         }
2139 }
2140
2141 static void vlv_pre_enable_dp(struct intel_encoder *encoder)
2142 {
2143         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2144         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2145         struct drm_device *dev = encoder->base.dev;
2146         struct drm_i915_private *dev_priv = dev->dev_private;
2147         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
2148         enum dpio_channel port = vlv_dport_to_channel(dport);
2149         int pipe = intel_crtc->pipe;
2150         struct edp_power_seq power_seq;
2151         u32 val;
2152
2153         mutex_lock(&dev_priv->dpio_lock);
2154
2155         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
2156         val = 0;
2157         if (pipe)
2158                 val |= (1<<21);
2159         else
2160                 val &= ~(1<<21);
2161         val |= 0x001000c4;
2162         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
2163         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
2164         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
2165
2166         mutex_unlock(&dev_priv->dpio_lock);
2167
2168         if (is_edp(intel_dp)) {
2169                 /* init power sequencer on this pipe and port */
2170                 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2171                 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2172                                                               &power_seq);
2173         }
2174
2175         intel_enable_dp(encoder);
2176
2177         vlv_wait_port_ready(dev_priv, dport);
2178 }
2179
2180 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
2181 {
2182         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2183         struct drm_device *dev = encoder->base.dev;
2184         struct drm_i915_private *dev_priv = dev->dev_private;
2185         struct intel_crtc *intel_crtc =
2186                 to_intel_crtc(encoder->base.crtc);
2187         enum dpio_channel port = vlv_dport_to_channel(dport);
2188         int pipe = intel_crtc->pipe;
2189
2190         intel_dp_prepare(encoder);
2191
2192         /* Program Tx lane resets to default */
2193         mutex_lock(&dev_priv->dpio_lock);
2194         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
2195                          DPIO_PCS_TX_LANE2_RESET |
2196                          DPIO_PCS_TX_LANE1_RESET);
2197         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
2198                          DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2199                          DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2200                          (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2201                                  DPIO_PCS_CLK_SOFT_RESET);
2202
2203         /* Fix up inter-pair skew failure */
2204         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2205         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2206         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
2207         mutex_unlock(&dev_priv->dpio_lock);
2208 }
2209
2210 static void chv_pre_enable_dp(struct intel_encoder *encoder)
2211 {
2212         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2213         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2214         struct drm_device *dev = encoder->base.dev;
2215         struct drm_i915_private *dev_priv = dev->dev_private;
2216         struct edp_power_seq power_seq;
2217         struct intel_crtc *intel_crtc =
2218                 to_intel_crtc(encoder->base.crtc);
2219         enum dpio_channel ch = vlv_dport_to_channel(dport);
2220         int pipe = intel_crtc->pipe;
2221         int data, i;
2222         u32 val;
2223
2224         mutex_lock(&dev_priv->dpio_lock);
2225
2226         /* Deassert soft data lane reset*/
2227         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
2228         val |= CHV_PCS_REQ_SOFTRESET_EN;
2229         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2230
2231         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2232         val |= CHV_PCS_REQ_SOFTRESET_EN;
2233         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2234
2235         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2236         val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2237         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2238
2239         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
2240         val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2241         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
2242
2243         /* Program Tx lane latency optimal setting*/
2244         for (i = 0; i < 4; i++) {
2245                 /* Set the latency optimal bit */
2246                 data = (i == 1) ? 0x0 : 0x6;
2247                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
2248                                 data << DPIO_FRC_LATENCY_SHFIT);
2249
2250                 /* Set the upar bit */
2251                 data = (i == 1) ? 0x0 : 0x1;
2252                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
2253                                 data << DPIO_UPAR_SHIFT);
2254         }
2255
2256         /* Data lane stagger programming */
2257         /* FIXME: Fix up value only after power analysis */
2258
2259         mutex_unlock(&dev_priv->dpio_lock);
2260
2261         if (is_edp(intel_dp)) {
2262                 /* init power sequencer on this pipe and port */
2263                 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2264                 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2265                                                               &power_seq);
2266         }
2267
2268         intel_enable_dp(encoder);
2269
2270         vlv_wait_port_ready(dev_priv, dport);
2271 }
2272
2273 static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2274 {
2275         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2276         struct drm_device *dev = encoder->base.dev;
2277         struct drm_i915_private *dev_priv = dev->dev_private;
2278         struct intel_crtc *intel_crtc =
2279                 to_intel_crtc(encoder->base.crtc);
2280         enum dpio_channel ch = vlv_dport_to_channel(dport);
2281         enum pipe pipe = intel_crtc->pipe;
2282         u32 val;
2283
2284         intel_dp_prepare(encoder);
2285
2286         mutex_lock(&dev_priv->dpio_lock);
2287
2288         /* program left/right clock distribution */
2289         if (pipe != PIPE_B) {
2290                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
2291                 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
2292                 if (ch == DPIO_CH0)
2293                         val |= CHV_BUFLEFTENA1_FORCE;
2294                 if (ch == DPIO_CH1)
2295                         val |= CHV_BUFRIGHTENA1_FORCE;
2296                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
2297         } else {
2298                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
2299                 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
2300                 if (ch == DPIO_CH0)
2301                         val |= CHV_BUFLEFTENA2_FORCE;
2302                 if (ch == DPIO_CH1)
2303                         val |= CHV_BUFRIGHTENA2_FORCE;
2304                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
2305         }
2306
2307         /* program clock channel usage */
2308         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
2309         val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2310         if (pipe != PIPE_B)
2311                 val &= ~CHV_PCS_USEDCLKCHANNEL;
2312         else
2313                 val |= CHV_PCS_USEDCLKCHANNEL;
2314         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
2315
2316         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
2317         val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2318         if (pipe != PIPE_B)
2319                 val &= ~CHV_PCS_USEDCLKCHANNEL;
2320         else
2321                 val |= CHV_PCS_USEDCLKCHANNEL;
2322         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
2323
2324         /*
2325          * This a a bit weird since generally CL
2326          * matches the pipe, but here we need to
2327          * pick the CL based on the port.
2328          */
2329         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
2330         if (pipe != PIPE_B)
2331                 val &= ~CHV_CMN_USEDCLKCHANNEL;
2332         else
2333                 val |= CHV_CMN_USEDCLKCHANNEL;
2334         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
2335
2336         mutex_unlock(&dev_priv->dpio_lock);
2337 }
2338
2339 /*
2340  * Native read with retry for link status and receiver capability reads for
2341  * cases where the sink may still be asleep.
2342  *
2343  * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2344  * supposed to retry 3 times per the spec.
2345  */
2346 static ssize_t
2347 intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
2348                         void *buffer, size_t size)
2349 {
2350         ssize_t ret;
2351         int i;
2352
2353         for (i = 0; i < 3; i++) {
2354                 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
2355                 if (ret == size)
2356                         return ret;
2357                 msleep(1);
2358         }
2359
2360         return ret;
2361 }
2362
2363 /*
2364  * Fetch AUX CH registers 0x202 - 0x207 which contain
2365  * link status information
2366  */
2367 static bool
2368 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
2369 {
2370         return intel_dp_dpcd_read_wake(&intel_dp->aux,
2371                                        DP_LANE0_1_STATUS,
2372                                        link_status,
2373                                        DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
2374 }
2375
2376 /* These are source-specific values. */
2377 static uint8_t
2378 intel_dp_voltage_max(struct intel_dp *intel_dp)
2379 {
2380         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2381         enum port port = dp_to_dig_port(intel_dp)->port;
2382
2383         if (IS_VALLEYVIEW(dev))
2384                 return DP_TRAIN_VOLTAGE_SWING_1200;
2385         else if (IS_GEN7(dev) && port == PORT_A)
2386                 return DP_TRAIN_VOLTAGE_SWING_800;
2387         else if (HAS_PCH_CPT(dev) && port != PORT_A)
2388                 return DP_TRAIN_VOLTAGE_SWING_1200;
2389         else
2390                 return DP_TRAIN_VOLTAGE_SWING_800;
2391 }
2392
2393 static uint8_t
2394 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2395 {
2396         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2397         enum port port = dp_to_dig_port(intel_dp)->port;
2398
2399         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2400                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2401                 case DP_TRAIN_VOLTAGE_SWING_400:
2402                         return DP_TRAIN_PRE_EMPHASIS_9_5;
2403                 case DP_TRAIN_VOLTAGE_SWING_600:
2404                         return DP_TRAIN_PRE_EMPHASIS_6;
2405                 case DP_TRAIN_VOLTAGE_SWING_800:
2406                         return DP_TRAIN_PRE_EMPHASIS_3_5;
2407                 case DP_TRAIN_VOLTAGE_SWING_1200:
2408                 default:
2409                         return DP_TRAIN_PRE_EMPHASIS_0;
2410                 }
2411         } else if (IS_VALLEYVIEW(dev)) {
2412                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2413                 case DP_TRAIN_VOLTAGE_SWING_400:
2414                         return DP_TRAIN_PRE_EMPHASIS_9_5;
2415                 case DP_TRAIN_VOLTAGE_SWING_600:
2416                         return DP_TRAIN_PRE_EMPHASIS_6;
2417                 case DP_TRAIN_VOLTAGE_SWING_800:
2418                         return DP_TRAIN_PRE_EMPHASIS_3_5;
2419                 case DP_TRAIN_VOLTAGE_SWING_1200:
2420                 default:
2421                         return DP_TRAIN_PRE_EMPHASIS_0;
2422                 }
2423         } else if (IS_GEN7(dev) && port == PORT_A) {
2424                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2425                 case DP_TRAIN_VOLTAGE_SWING_400:
2426                         return DP_TRAIN_PRE_EMPHASIS_6;
2427                 case DP_TRAIN_VOLTAGE_SWING_600:
2428                 case DP_TRAIN_VOLTAGE_SWING_800:
2429                         return DP_TRAIN_PRE_EMPHASIS_3_5;
2430                 default:
2431                         return DP_TRAIN_PRE_EMPHASIS_0;
2432                 }
2433         } else {
2434                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2435                 case DP_TRAIN_VOLTAGE_SWING_400:
2436                         return DP_TRAIN_PRE_EMPHASIS_6;
2437                 case DP_TRAIN_VOLTAGE_SWING_600:
2438                         return DP_TRAIN_PRE_EMPHASIS_6;
2439                 case DP_TRAIN_VOLTAGE_SWING_800:
2440                         return DP_TRAIN_PRE_EMPHASIS_3_5;
2441                 case DP_TRAIN_VOLTAGE_SWING_1200:
2442                 default:
2443                         return DP_TRAIN_PRE_EMPHASIS_0;
2444                 }
2445         }
2446 }
2447
2448 static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2449 {
2450         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2451         struct drm_i915_private *dev_priv = dev->dev_private;
2452         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2453         struct intel_crtc *intel_crtc =
2454                 to_intel_crtc(dport->base.base.crtc);
2455         unsigned long demph_reg_value, preemph_reg_value,
2456                 uniqtranscale_reg_value;
2457         uint8_t train_set = intel_dp->train_set[0];
2458         enum dpio_channel port = vlv_dport_to_channel(dport);
2459         int pipe = intel_crtc->pipe;
2460
2461         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2462         case DP_TRAIN_PRE_EMPHASIS_0:
2463                 preemph_reg_value = 0x0004000;
2464                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2465                 case DP_TRAIN_VOLTAGE_SWING_400:
2466                         demph_reg_value = 0x2B405555;
2467                         uniqtranscale_reg_value = 0x552AB83A;
2468                         break;
2469                 case DP_TRAIN_VOLTAGE_SWING_600:
2470                         demph_reg_value = 0x2B404040;
2471                         uniqtranscale_reg_value = 0x5548B83A;
2472                         break;
2473                 case DP_TRAIN_VOLTAGE_SWING_800:
2474                         demph_reg_value = 0x2B245555;
2475                         uniqtranscale_reg_value = 0x5560B83A;
2476                         break;
2477                 case DP_TRAIN_VOLTAGE_SWING_1200:
2478                         demph_reg_value = 0x2B405555;
2479                         uniqtranscale_reg_value = 0x5598DA3A;
2480                         break;
2481                 default:
2482                         return 0;
2483                 }
2484                 break;
2485         case DP_TRAIN_PRE_EMPHASIS_3_5:
2486                 preemph_reg_value = 0x0002000;
2487                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2488                 case DP_TRAIN_VOLTAGE_SWING_400:
2489                         demph_reg_value = 0x2B404040;
2490                         uniqtranscale_reg_value = 0x5552B83A;
2491                         break;
2492                 case DP_TRAIN_VOLTAGE_SWING_600:
2493                         demph_reg_value = 0x2B404848;
2494                         uniqtranscale_reg_value = 0x5580B83A;
2495                         break;
2496                 case DP_TRAIN_VOLTAGE_SWING_800:
2497                         demph_reg_value = 0x2B404040;
2498                         uniqtranscale_reg_value = 0x55ADDA3A;
2499                         break;
2500                 default:
2501                         return 0;
2502                 }
2503                 break;
2504         case DP_TRAIN_PRE_EMPHASIS_6:
2505                 preemph_reg_value = 0x0000000;
2506                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2507                 case DP_TRAIN_VOLTAGE_SWING_400:
2508                         demph_reg_value = 0x2B305555;
2509                         uniqtranscale_reg_value = 0x5570B83A;
2510                         break;
2511                 case DP_TRAIN_VOLTAGE_SWING_600:
2512                         demph_reg_value = 0x2B2B4040;
2513                         uniqtranscale_reg_value = 0x55ADDA3A;
2514                         break;
2515                 default:
2516                         return 0;
2517                 }
2518                 break;
2519         case DP_TRAIN_PRE_EMPHASIS_9_5:
2520                 preemph_reg_value = 0x0006000;
2521                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2522                 case DP_TRAIN_VOLTAGE_SWING_400:
2523                         demph_reg_value = 0x1B405555;
2524                         uniqtranscale_reg_value = 0x55ADDA3A;
2525                         break;
2526                 default:
2527                         return 0;
2528                 }
2529                 break;
2530         default:
2531                 return 0;
2532         }
2533
2534         mutex_lock(&dev_priv->dpio_lock);
2535         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
2536         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
2537         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
2538                          uniqtranscale_reg_value);
2539         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
2540         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
2541         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
2542         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
2543         mutex_unlock(&dev_priv->dpio_lock);
2544
2545         return 0;
2546 }
2547
2548 static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
2549 {
2550         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2551         struct drm_i915_private *dev_priv = dev->dev_private;
2552         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2553         struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
2554         u32 deemph_reg_value, margin_reg_value, val;
2555         uint8_t train_set = intel_dp->train_set[0];
2556         enum dpio_channel ch = vlv_dport_to_channel(dport);
2557         enum pipe pipe = intel_crtc->pipe;
2558         int i;
2559
2560         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2561         case DP_TRAIN_PRE_EMPHASIS_0:
2562                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2563                 case DP_TRAIN_VOLTAGE_SWING_400:
2564                         deemph_reg_value = 128;
2565                         margin_reg_value = 52;
2566                         break;
2567                 case DP_TRAIN_VOLTAGE_SWING_600:
2568                         deemph_reg_value = 128;
2569                         margin_reg_value = 77;
2570                         break;
2571                 case DP_TRAIN_VOLTAGE_SWING_800:
2572                         deemph_reg_value = 128;
2573                         margin_reg_value = 102;
2574                         break;
2575                 case DP_TRAIN_VOLTAGE_SWING_1200:
2576                         deemph_reg_value = 128;
2577                         margin_reg_value = 154;
2578                         /* FIXME extra to set for 1200 */
2579                         break;
2580                 default:
2581                         return 0;
2582                 }
2583                 break;
2584         case DP_TRAIN_PRE_EMPHASIS_3_5:
2585                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2586                 case DP_TRAIN_VOLTAGE_SWING_400:
2587                         deemph_reg_value = 85;
2588                         margin_reg_value = 78;
2589                         break;
2590                 case DP_TRAIN_VOLTAGE_SWING_600:
2591                         deemph_reg_value = 85;
2592                         margin_reg_value = 116;
2593                         break;
2594                 case DP_TRAIN_VOLTAGE_SWING_800:
2595                         deemph_reg_value = 85;
2596                         margin_reg_value = 154;
2597                         break;
2598                 default:
2599                         return 0;
2600                 }
2601                 break;
2602         case DP_TRAIN_PRE_EMPHASIS_6:
2603                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2604                 case DP_TRAIN_VOLTAGE_SWING_400:
2605                         deemph_reg_value = 64;
2606                         margin_reg_value = 104;
2607                         break;
2608                 case DP_TRAIN_VOLTAGE_SWING_600:
2609                         deemph_reg_value = 64;
2610                         margin_reg_value = 154;
2611                         break;
2612                 default:
2613                         return 0;
2614                 }
2615                 break;
2616         case DP_TRAIN_PRE_EMPHASIS_9_5:
2617                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2618                 case DP_TRAIN_VOLTAGE_SWING_400:
2619                         deemph_reg_value = 43;
2620                         margin_reg_value = 154;
2621                         break;
2622                 default:
2623                         return 0;
2624                 }
2625                 break;
2626         default:
2627                 return 0;
2628         }
2629
2630         mutex_lock(&dev_priv->dpio_lock);
2631
2632         /* Clear calc init */
2633         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
2634         val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
2635         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
2636
2637         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
2638         val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
2639         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
2640
2641         /* Program swing deemph */
2642         for (i = 0; i < 4; i++) {
2643                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
2644                 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
2645                 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
2646                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
2647         }
2648
2649         /* Program swing margin */
2650         for (i = 0; i < 4; i++) {
2651                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
2652                 val &= ~DPIO_SWING_MARGIN000_MASK;
2653                 val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
2654                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
2655         }
2656
2657         /* Disable unique transition scale */
2658         for (i = 0; i < 4; i++) {
2659                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
2660                 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
2661                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
2662         }
2663
2664         if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
2665                         == DP_TRAIN_PRE_EMPHASIS_0) &&
2666                 ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
2667                         == DP_TRAIN_VOLTAGE_SWING_1200)) {
2668
2669                 /*
2670                  * The document said it needs to set bit 27 for ch0 and bit 26
2671                  * for ch1. Might be a typo in the doc.
2672                  * For now, for this unique transition scale selection, set bit
2673                  * 27 for ch0 and ch1.
2674                  */
2675                 for (i = 0; i < 4; i++) {
2676                         val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
2677                         val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
2678                         vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
2679                 }
2680
2681                 for (i = 0; i < 4; i++) {
2682                         val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
2683                         val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
2684                         val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT);
2685                         vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
2686                 }
2687         }
2688
2689         /* Start swing calculation */
2690         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
2691         val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
2692         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
2693
2694         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
2695         val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
2696         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
2697
2698         /* LRC Bypass */
2699         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
2700         val |= DPIO_LRC_BYPASS;
2701         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
2702
2703         mutex_unlock(&dev_priv->dpio_lock);
2704
2705         return 0;
2706 }
2707
2708 static void
2709 intel_get_adjust_train(struct intel_dp *intel_dp,
2710                        const uint8_t link_status[DP_LINK_STATUS_SIZE])
2711 {
2712         uint8_t v = 0;
2713         uint8_t p = 0;
2714         int lane;
2715         uint8_t voltage_max;
2716         uint8_t preemph_max;
2717
2718         for (lane = 0; lane < intel_dp->lane_count; lane++) {
2719                 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2720                 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
2721
2722                 if (this_v > v)
2723                         v = this_v;
2724                 if (this_p > p)
2725                         p = this_p;
2726         }
2727
2728         voltage_max = intel_dp_voltage_max(intel_dp);
2729         if (v >= voltage_max)
2730                 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
2731
2732         preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2733         if (p >= preemph_max)
2734                 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
2735
2736         for (lane = 0; lane < 4; lane++)
2737                 intel_dp->train_set[lane] = v | p;
2738 }
2739
2740 static uint32_t
2741 intel_gen4_signal_levels(uint8_t train_set)
2742 {
2743         uint32_t        signal_levels = 0;
2744
2745         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2746         case DP_TRAIN_VOLTAGE_SWING_400:
2747         default:
2748                 signal_levels |= DP_VOLTAGE_0_4;
2749                 break;
2750         case DP_TRAIN_VOLTAGE_SWING_600:
2751                 signal_levels |= DP_VOLTAGE_0_6;
2752                 break;
2753         case DP_TRAIN_VOLTAGE_SWING_800:
2754                 signal_levels |= DP_VOLTAGE_0_8;
2755                 break;
2756         case DP_TRAIN_VOLTAGE_SWING_1200:
2757                 signal_levels |= DP_VOLTAGE_1_2;
2758                 break;
2759         }
2760         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2761         case DP_TRAIN_PRE_EMPHASIS_0:
2762         default:
2763                 signal_levels |= DP_PRE_EMPHASIS_0;
2764                 break;
2765         case DP_TRAIN_PRE_EMPHASIS_3_5:
2766                 signal_levels |= DP_PRE_EMPHASIS_3_5;
2767                 break;
2768         case DP_TRAIN_PRE_EMPHASIS_6:
2769                 signal_levels |= DP_PRE_EMPHASIS_6;
2770                 break;
2771         case DP_TRAIN_PRE_EMPHASIS_9_5:
2772                 signal_levels |= DP_PRE_EMPHASIS_9_5;
2773                 break;
2774         }
2775         return signal_levels;
2776 }
2777
2778 /* Gen6's DP voltage swing and pre-emphasis control */
2779 static uint32_t
2780 intel_gen6_edp_signal_levels(uint8_t train_set)
2781 {
2782         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2783                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2784         switch (signal_levels) {
2785         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2786         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2787                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2788         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2789                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
2790         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2791         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2792                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
2793         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2794         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2795                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
2796         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2797         case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2798                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
2799         default:
2800                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2801                               "0x%x\n", signal_levels);
2802                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2803         }
2804 }
2805
2806 /* Gen7's DP voltage swing and pre-emphasis control */
2807 static uint32_t
2808 intel_gen7_edp_signal_levels(uint8_t train_set)
2809 {
2810         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2811                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2812         switch (signal_levels) {
2813         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2814                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
2815         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2816                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
2817         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2818                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2819
2820         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2821                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
2822         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2823                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2824
2825         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2826                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
2827         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2828                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2829
2830         default:
2831                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2832                               "0x%x\n", signal_levels);
2833                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2834         }
2835 }
2836
2837 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2838 static uint32_t
2839 intel_hsw_signal_levels(uint8_t train_set)
2840 {
2841         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2842                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2843         switch (signal_levels) {
2844         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2845                 return DDI_BUF_EMP_400MV_0DB_HSW;
2846         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2847                 return DDI_BUF_EMP_400MV_3_5DB_HSW;
2848         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2849                 return DDI_BUF_EMP_400MV_6DB_HSW;
2850         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
2851                 return DDI_BUF_EMP_400MV_9_5DB_HSW;
2852
2853         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2854                 return DDI_BUF_EMP_600MV_0DB_HSW;
2855         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2856                 return DDI_BUF_EMP_600MV_3_5DB_HSW;
2857         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2858                 return DDI_BUF_EMP_600MV_6DB_HSW;
2859
2860         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2861                 return DDI_BUF_EMP_800MV_0DB_HSW;
2862         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2863                 return DDI_BUF_EMP_800MV_3_5DB_HSW;
2864         default:
2865                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2866                               "0x%x\n", signal_levels);
2867                 return DDI_BUF_EMP_400MV_0DB_HSW;
2868         }
2869 }
2870
2871 /* Properly updates "DP" with the correct signal levels. */
2872 static void
2873 intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
2874 {
2875         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2876         enum port port = intel_dig_port->port;
2877         struct drm_device *dev = intel_dig_port->base.base.dev;
2878         uint32_t signal_levels, mask;
2879         uint8_t train_set = intel_dp->train_set[0];
2880
2881         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2882                 signal_levels = intel_hsw_signal_levels(train_set);
2883                 mask = DDI_BUF_EMP_MASK;
2884         } else if (IS_CHERRYVIEW(dev)) {
2885                 signal_levels = intel_chv_signal_levels(intel_dp);
2886                 mask = 0;
2887         } else if (IS_VALLEYVIEW(dev)) {
2888                 signal_levels = intel_vlv_signal_levels(intel_dp);
2889                 mask = 0;
2890         } else if (IS_GEN7(dev) && port == PORT_A) {
2891                 signal_levels = intel_gen7_edp_signal_levels(train_set);
2892                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
2893         } else if (IS_GEN6(dev) && port == PORT_A) {
2894                 signal_levels = intel_gen6_edp_signal_levels(train_set);
2895                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
2896         } else {
2897                 signal_levels = intel_gen4_signal_levels(train_set);
2898                 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
2899         }
2900
2901         DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
2902
2903         *DP = (*DP & ~mask) | signal_levels;
2904 }
2905
2906 static bool
2907 intel_dp_set_link_train(struct intel_dp *intel_dp,
2908                         uint32_t *DP,
2909                         uint8_t dp_train_pat)
2910 {
2911         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2912         struct drm_device *dev = intel_dig_port->base.base.dev;
2913         struct drm_i915_private *dev_priv = dev->dev_private;
2914         enum port port = intel_dig_port->port;
2915         uint8_t buf[sizeof(intel_dp->train_set) + 1];
2916         int ret, len;
2917
2918         if (HAS_DDI(dev)) {
2919                 uint32_t temp = I915_READ(DP_TP_CTL(port));
2920
2921                 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2922                         temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2923                 else
2924                         temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2925
2926                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2927                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2928                 case DP_TRAINING_PATTERN_DISABLE:
2929                         temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2930
2931                         break;
2932                 case DP_TRAINING_PATTERN_1:
2933                         temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2934                         break;
2935                 case DP_TRAINING_PATTERN_2:
2936                         temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2937                         break;
2938                 case DP_TRAINING_PATTERN_3:
2939                         temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2940                         break;
2941                 }
2942                 I915_WRITE(DP_TP_CTL(port), temp);
2943
2944         } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2945                 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2946
2947                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2948                 case DP_TRAINING_PATTERN_DISABLE:
2949                         *DP |= DP_LINK_TRAIN_OFF_CPT;
2950                         break;
2951                 case DP_TRAINING_PATTERN_1:
2952                         *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2953                         break;
2954                 case DP_TRAINING_PATTERN_2:
2955                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2956                         break;
2957                 case DP_TRAINING_PATTERN_3:
2958                         DRM_ERROR("DP training pattern 3 not supported\n");
2959                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2960                         break;
2961                 }
2962
2963         } else {
2964                 if (IS_CHERRYVIEW(dev))
2965                         *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2966                 else
2967                         *DP &= ~DP_LINK_TRAIN_MASK;
2968
2969                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2970                 case DP_TRAINING_PATTERN_DISABLE:
2971                         *DP |= DP_LINK_TRAIN_OFF;
2972                         break;
2973                 case DP_TRAINING_PATTERN_1:
2974                         *DP |= DP_LINK_TRAIN_PAT_1;
2975                         break;
2976                 case DP_TRAINING_PATTERN_2:
2977                         *DP |= DP_LINK_TRAIN_PAT_2;
2978                         break;
2979                 case DP_TRAINING_PATTERN_3:
2980                         if (IS_CHERRYVIEW(dev)) {
2981                                 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2982                         } else {
2983                                 DRM_ERROR("DP training pattern 3 not supported\n");
2984                                 *DP |= DP_LINK_TRAIN_PAT_2;
2985                         }
2986                         break;
2987                 }
2988         }
2989
2990         I915_WRITE(intel_dp->output_reg, *DP);
2991         POSTING_READ(intel_dp->output_reg);
2992
2993         buf[0] = dp_train_pat;
2994         if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
2995             DP_TRAINING_PATTERN_DISABLE) {
2996                 /* don't write DP_TRAINING_LANEx_SET on disable */
2997                 len = 1;
2998         } else {
2999                 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
3000                 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
3001                 len = intel_dp->lane_count + 1;
3002         }
3003
3004         ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
3005                                 buf, len);
3006
3007         return ret == len;
3008 }
3009
3010 static bool
3011 intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
3012                         uint8_t dp_train_pat)
3013 {
3014         memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
3015         intel_dp_set_signal_levels(intel_dp, DP);
3016         return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
3017 }
3018
3019 static bool
3020 intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
3021                            const uint8_t link_status[DP_LINK_STATUS_SIZE])
3022 {
3023         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3024         struct drm_device *dev = intel_dig_port->base.base.dev;
3025         struct drm_i915_private *dev_priv = dev->dev_private;
3026         int ret;
3027
3028         intel_get_adjust_train(intel_dp, link_status);
3029         intel_dp_set_signal_levels(intel_dp, DP);
3030
3031         I915_WRITE(intel_dp->output_reg, *DP);
3032         POSTING_READ(intel_dp->output_reg);
3033
3034         ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
3035                                 intel_dp->train_set, intel_dp->lane_count);
3036
3037         return ret == intel_dp->lane_count;
3038 }
3039
3040 static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3041 {
3042         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3043         struct drm_device *dev = intel_dig_port->base.base.dev;
3044         struct drm_i915_private *dev_priv = dev->dev_private;
3045         enum port port = intel_dig_port->port;
3046         uint32_t val;
3047
3048         if (!HAS_DDI(dev))
3049                 return;
3050
3051         val = I915_READ(DP_TP_CTL(port));
3052         val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3053         val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3054         I915_WRITE(DP_TP_CTL(port), val);
3055
3056         /*
3057          * On PORT_A we can have only eDP in SST mode. There the only reason
3058          * we need to set idle transmission mode is to work around a HW issue
3059          * where we enable the pipe while not in idle link-training mode.
3060          * In this case there is requirement to wait for a minimum number of
3061          * idle patterns to be sent.
3062          */
3063         if (port == PORT_A)
3064                 return;
3065
3066         if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
3067                      1))
3068                 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3069 }
3070
3071 /* Enable corresponding port and start training pattern 1 */
3072 void
3073 intel_dp_start_link_train(struct intel_dp *intel_dp)
3074 {
3075         struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
3076         struct drm_device *dev = encoder->dev;
3077         int i;
3078         uint8_t voltage;
3079         int voltage_tries, loop_tries;
3080         uint32_t DP = intel_dp->DP;
3081         uint8_t link_config[2];
3082
3083         if (HAS_DDI(dev))
3084                 intel_ddi_prepare_link_retrain(encoder);
3085
3086         /* Write the link configuration data */
3087         link_config[0] = intel_dp->link_bw;
3088         link_config[1] = intel_dp->lane_count;
3089         if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3090                 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
3091         drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
3092
3093         link_config[0] = 0;
3094         link_config[1] = DP_SET_ANSI_8B10B;
3095         drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
3096
3097         DP |= DP_PORT_EN;
3098
3099         /* clock recovery */
3100         if (!intel_dp_reset_link_train(intel_dp, &DP,
3101                                        DP_TRAINING_PATTERN_1 |
3102                                        DP_LINK_SCRAMBLING_DISABLE)) {
3103                 DRM_ERROR("failed to enable link training\n");
3104                 return;
3105         }
3106
3107         voltage = 0xff;
3108         voltage_tries = 0;
3109         loop_tries = 0;
3110         for (;;) {
3111                 uint8_t link_status[DP_LINK_STATUS_SIZE];
3112
3113                 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
3114                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3115                         DRM_ERROR("failed to get link status\n");
3116                         break;
3117                 }
3118
3119                 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
3120                         DRM_DEBUG_KMS("clock recovery OK\n");
3121                         break;
3122                 }
3123
3124                 /* Check to see if we've tried the max voltage */
3125                 for (i = 0; i < intel_dp->lane_count; i++)
3126                         if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
3127                                 break;
3128                 if (i == intel_dp->lane_count) {
3129                         ++loop_tries;
3130                         if (loop_tries == 5) {
3131                                 DRM_ERROR("too many full retries, give up\n");
3132                                 break;
3133                         }
3134                         intel_dp_reset_link_train(intel_dp, &DP,
3135                                                   DP_TRAINING_PATTERN_1 |
3136                                                   DP_LINK_SCRAMBLING_DISABLE);
3137                         voltage_tries = 0;
3138                         continue;
3139                 }
3140
3141                 /* Check to see if we've tried the same voltage 5 times */
3142                 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
3143                         ++voltage_tries;
3144                         if (voltage_tries == 5) {
3145                                 DRM_ERROR("too many voltage retries, give up\n");
3146                                 break;
3147                         }
3148                 } else
3149                         voltage_tries = 0;
3150                 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
3151
3152                 /* Update training set as requested by target */
3153                 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3154                         DRM_ERROR("failed to update link training\n");
3155                         break;
3156                 }
3157         }
3158
3159         intel_dp->DP = DP;
3160 }
3161
3162 void
3163 intel_dp_complete_link_train(struct intel_dp *intel_dp)
3164 {
3165         bool channel_eq = false;
3166         int tries, cr_tries;
3167         uint32_t DP = intel_dp->DP;
3168         uint32_t training_pattern = DP_TRAINING_PATTERN_2;
3169
3170         /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3171         if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
3172                 training_pattern = DP_TRAINING_PATTERN_3;
3173
3174         /* channel equalization */
3175         if (!intel_dp_set_link_train(intel_dp, &DP,
3176                                      training_pattern |
3177                                      DP_LINK_SCRAMBLING_DISABLE)) {
3178                 DRM_ERROR("failed to start channel equalization\n");
3179                 return;
3180         }
3181
3182         tries = 0;
3183         cr_tries = 0;
3184         channel_eq = false;
3185         for (;;) {
3186                 uint8_t link_status[DP_LINK_STATUS_SIZE];
3187
3188                 if (cr_tries > 5) {
3189                         DRM_ERROR("failed to train DP, aborting\n");
3190                         break;
3191                 }
3192
3193                 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
3194                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3195                         DRM_ERROR("failed to get link status\n");
3196                         break;
3197                 }
3198
3199                 /* Make sure clock is still ok */
3200                 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
3201                         intel_dp_start_link_train(intel_dp);
3202                         intel_dp_set_link_train(intel_dp, &DP,
3203                                                 training_pattern |
3204                                                 DP_LINK_SCRAMBLING_DISABLE);
3205                         cr_tries++;
3206                         continue;
3207                 }
3208
3209                 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3210                         channel_eq = true;
3211                         break;
3212                 }
3213
3214                 /* Try 5 times, then try clock recovery if that fails */
3215                 if (tries > 5) {
3216                         intel_dp_link_down(intel_dp);
3217                         intel_dp_start_link_train(intel_dp);
3218                         intel_dp_set_link_train(intel_dp, &DP,
3219                                                 training_pattern |
3220                                                 DP_LINK_SCRAMBLING_DISABLE);
3221                         tries = 0;
3222                         cr_tries++;
3223                         continue;
3224                 }
3225
3226                 /* Update training set as requested by target */
3227                 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3228                         DRM_ERROR("failed to update link training\n");
3229                         break;
3230                 }
3231                 ++tries;
3232         }
3233
3234         intel_dp_set_idle_link_train(intel_dp);
3235
3236         intel_dp->DP = DP;
3237
3238         if (channel_eq)
3239                 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
3240
3241 }
3242
3243 void intel_dp_stop_link_train(struct intel_dp *intel_dp)
3244 {
3245         intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3246                                 DP_TRAINING_PATTERN_DISABLE);
3247 }
3248
3249 static void
3250 intel_dp_link_down(struct intel_dp *intel_dp)
3251 {
3252         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3253         enum port port = intel_dig_port->port;
3254         struct drm_device *dev = intel_dig_port->base.base.dev;
3255         struct drm_i915_private *dev_priv = dev->dev_private;
3256         struct intel_crtc *intel_crtc =
3257                 to_intel_crtc(intel_dig_port->base.base.crtc);
3258         uint32_t DP = intel_dp->DP;
3259
3260         if (WARN_ON(HAS_DDI(dev)))
3261                 return;
3262
3263         if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
3264                 return;
3265
3266         DRM_DEBUG_KMS("\n");
3267
3268         if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
3269                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
3270                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
3271         } else {
3272                 if (IS_CHERRYVIEW(dev))
3273                         DP &= ~DP_LINK_TRAIN_MASK_CHV;
3274                 else
3275                         DP &= ~DP_LINK_TRAIN_MASK;
3276                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
3277         }
3278         POSTING_READ(intel_dp->output_reg);
3279
3280         if (HAS_PCH_IBX(dev) &&
3281             I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
3282                 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
3283
3284                 /* Hardware workaround: leaving our transcoder select
3285                  * set to transcoder B while it's off will prevent the
3286                  * corresponding HDMI output on transcoder A.
3287                  *
3288                  * Combine this with another hardware workaround:
3289                  * transcoder select bit can only be cleared while the
3290                  * port is enabled.
3291                  */
3292                 DP &= ~DP_PIPEB_SELECT;
3293                 I915_WRITE(intel_dp->output_reg, DP);
3294
3295                 /* Changes to enable or select take place the vblank
3296                  * after being written.
3297                  */
3298                 if (WARN_ON(crtc == NULL)) {
3299                         /* We should never try to disable a port without a crtc
3300                          * attached. For paranoia keep the code around for a
3301                          * bit. */
3302                         POSTING_READ(intel_dp->output_reg);
3303                         msleep(50);
3304                 } else
3305                         intel_wait_for_vblank(dev, intel_crtc->pipe);
3306         }
3307
3308         DP &= ~DP_AUDIO_OUTPUT_ENABLE;
3309         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
3310         POSTING_READ(intel_dp->output_reg);
3311         msleep(intel_dp->panel_power_down_delay);
3312 }
3313
3314 static bool
3315 intel_dp_get_dpcd(struct intel_dp *intel_dp)
3316 {
3317         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3318         struct drm_device *dev = dig_port->base.base.dev;
3319         struct drm_i915_private *dev_priv = dev->dev_private;
3320
3321         char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
3322
3323         if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3324                                     sizeof(intel_dp->dpcd)) < 0)
3325                 return false; /* aux transfer failed */
3326
3327         hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
3328                            32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
3329         DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
3330
3331         if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3332                 return false; /* DPCD not present */
3333
3334         /* Check if the panel supports PSR */
3335         memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
3336         if (is_edp(intel_dp)) {
3337                 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3338                                         intel_dp->psr_dpcd,
3339                                         sizeof(intel_dp->psr_dpcd));
3340                 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3341                         dev_priv->psr.sink_support = true;
3342                         DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3343                 }
3344         }
3345
3346         /* Training Pattern 3 support */
3347         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
3348             intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
3349                 intel_dp->use_tps3 = true;
3350                 DRM_DEBUG_KMS("Displayport TPS3 supported");
3351         } else
3352                 intel_dp->use_tps3 = false;
3353
3354         if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3355               DP_DWN_STRM_PORT_PRESENT))
3356                 return true; /* native DP sink */
3357
3358         if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3359                 return true; /* no per-port downstream info */
3360
3361         if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3362                                     intel_dp->downstream_ports,
3363                                     DP_MAX_DOWNSTREAM_PORTS) < 0)
3364                 return false; /* downstream port status fetch failed */
3365
3366         return true;
3367 }
3368
3369 static void
3370 intel_dp_probe_oui(struct intel_dp *intel_dp)
3371 {
3372         u8 buf[3];
3373
3374         if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3375                 return;
3376
3377         intel_edp_panel_vdd_on(intel_dp);
3378
3379         if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
3380                 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3381                               buf[0], buf[1], buf[2]);
3382
3383         if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
3384                 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3385                               buf[0], buf[1], buf[2]);
3386
3387         edp_panel_vdd_off(intel_dp, false);
3388 }
3389
3390 static bool
3391 intel_dp_probe_mst(struct intel_dp *intel_dp)
3392 {
3393         u8 buf[1];
3394
3395         if (!intel_dp->can_mst)
3396                 return false;
3397
3398         if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3399                 return false;
3400
3401         _edp_panel_vdd_on(intel_dp);
3402         if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
3403                 if (buf[0] & DP_MST_CAP) {
3404                         DRM_DEBUG_KMS("Sink is MST capable\n");
3405                         intel_dp->is_mst = true;
3406                 } else {
3407                         DRM_DEBUG_KMS("Sink is not MST capable\n");
3408                         intel_dp->is_mst = false;
3409                 }
3410         }
3411         edp_panel_vdd_off(intel_dp, false);
3412
3413         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3414         return intel_dp->is_mst;
3415 }
3416
3417 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3418 {
3419         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3420         struct drm_device *dev = intel_dig_port->base.base.dev;
3421         struct intel_crtc *intel_crtc =
3422                 to_intel_crtc(intel_dig_port->base.base.crtc);
3423         u8 buf[1];
3424
3425         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, buf) < 0)
3426                 return -EAGAIN;
3427
3428         if (!(buf[0] & DP_TEST_CRC_SUPPORTED))
3429                 return -ENOTTY;
3430
3431         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3432                                DP_TEST_SINK_START) < 0)
3433                 return -EAGAIN;
3434
3435         /* Wait 2 vblanks to be sure we will have the correct CRC value */
3436         intel_wait_for_vblank(dev, intel_crtc->pipe);
3437         intel_wait_for_vblank(dev, intel_crtc->pipe);
3438
3439         if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
3440                 return -EAGAIN;
3441
3442         drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 0);
3443         return 0;
3444 }
3445
3446 static bool
3447 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3448 {
3449         return intel_dp_dpcd_read_wake(&intel_dp->aux,
3450                                        DP_DEVICE_SERVICE_IRQ_VECTOR,
3451                                        sink_irq_vector, 1) == 1;
3452 }
3453
3454 static bool
3455 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3456 {
3457         int ret;
3458
3459         ret = intel_dp_dpcd_read_wake(&intel_dp->aux,
3460                                              DP_SINK_COUNT_ESI,
3461                                              sink_irq_vector, 14);
3462         if (ret != 14)
3463                 return false;
3464
3465         return true;
3466 }
3467
3468 static void
3469 intel_dp_handle_test_request(struct intel_dp *intel_dp)
3470 {
3471         /* NAK by default */
3472         drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
3473 }
3474
3475 static int
3476 intel_dp_check_mst_status(struct intel_dp *intel_dp)
3477 {
3478         bool bret;
3479
3480         if (intel_dp->is_mst) {
3481                 u8 esi[16] = { 0 };
3482                 int ret = 0;
3483                 int retry;
3484                 bool handled;
3485                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3486 go_again:
3487                 if (bret == true) {
3488
3489                         /* check link status - esi[10] = 0x200c */
3490                         if (intel_dp->active_mst_links && !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
3491                                 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
3492                                 intel_dp_start_link_train(intel_dp);
3493                                 intel_dp_complete_link_train(intel_dp);
3494                                 intel_dp_stop_link_train(intel_dp);
3495                         }
3496
3497                         DRM_DEBUG_KMS("got esi %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3498                         ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
3499
3500                         if (handled) {
3501                                 for (retry = 0; retry < 3; retry++) {
3502                                         int wret;
3503                                         wret = drm_dp_dpcd_write(&intel_dp->aux,
3504                                                                  DP_SINK_COUNT_ESI+1,
3505                                                                  &esi[1], 3);
3506                                         if (wret == 3) {
3507                                                 break;
3508                                         }
3509                                 }
3510
3511                                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3512                                 if (bret == true) {
3513                                         DRM_DEBUG_KMS("got esi2 %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3514                                         goto go_again;
3515                                 }
3516                         } else
3517                                 ret = 0;
3518
3519                         return ret;
3520                 } else {
3521                         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3522                         DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
3523                         intel_dp->is_mst = false;
3524                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3525                         /* send a hotplug event */
3526                         drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
3527                 }
3528         }
3529         return -EINVAL;
3530 }
3531
3532 /*
3533  * According to DP spec
3534  * 5.1.2:
3535  *  1. Read DPCD
3536  *  2. Configure link according to Receiver Capabilities
3537  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
3538  *  4. Check link status on receipt of hot-plug interrupt
3539  */
3540 void
3541 intel_dp_check_link_status(struct intel_dp *intel_dp)
3542 {
3543         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3544         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
3545         u8 sink_irq_vector;
3546         u8 link_status[DP_LINK_STATUS_SIZE];
3547
3548         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
3549
3550         if (!intel_encoder->connectors_active)
3551                 return;
3552
3553         if (WARN_ON(!intel_encoder->base.crtc))
3554                 return;
3555
3556         if (!to_intel_crtc(intel_encoder->base.crtc)->active)
3557                 return;
3558
3559         /* Try to read receiver status if the link appears to be up */
3560         if (!intel_dp_get_link_status(intel_dp, link_status)) {
3561                 return;
3562         }
3563
3564         /* Now read the DPCD to see if it's actually running */
3565         if (!intel_dp_get_dpcd(intel_dp)) {
3566                 return;
3567         }
3568
3569         /* Try to read the source of the interrupt */
3570         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3571             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
3572                 /* Clear interrupt source */
3573                 drm_dp_dpcd_writeb(&intel_dp->aux,
3574                                    DP_DEVICE_SERVICE_IRQ_VECTOR,
3575                                    sink_irq_vector);
3576
3577                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
3578                         intel_dp_handle_test_request(intel_dp);
3579                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
3580                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3581         }
3582
3583         if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3584                 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
3585                               intel_encoder->base.name);
3586                 intel_dp_start_link_train(intel_dp);
3587                 intel_dp_complete_link_train(intel_dp);
3588                 intel_dp_stop_link_train(intel_dp);
3589         }
3590 }
3591
3592 /* XXX this is probably wrong for multiple downstream ports */
3593 static enum drm_connector_status
3594 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
3595 {
3596         uint8_t *dpcd = intel_dp->dpcd;
3597         uint8_t type;
3598
3599         if (!intel_dp_get_dpcd(intel_dp))
3600                 return connector_status_disconnected;
3601
3602         /* if there's no downstream port, we're done */
3603         if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
3604                 return connector_status_connected;
3605
3606         /* If we're HPD-aware, SINK_COUNT changes dynamically */
3607         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3608             intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
3609                 uint8_t reg;
3610
3611                 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
3612                                             &reg, 1) < 0)
3613                         return connector_status_unknown;
3614
3615                 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
3616                                               : connector_status_disconnected;
3617         }
3618
3619         /* If no HPD, poke DDC gently */
3620         if (drm_probe_ddc(&intel_dp->aux.ddc))
3621                 return connector_status_connected;
3622
3623         /* Well we tried, say unknown for unreliable port types */
3624         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
3625                 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
3626                 if (type == DP_DS_PORT_TYPE_VGA ||
3627                     type == DP_DS_PORT_TYPE_NON_EDID)
3628                         return connector_status_unknown;
3629         } else {
3630                 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3631                         DP_DWN_STRM_PORT_TYPE_MASK;
3632                 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
3633                     type == DP_DWN_STRM_PORT_TYPE_OTHER)
3634                         return connector_status_unknown;
3635         }
3636
3637         /* Anything else is out of spec, warn and ignore */
3638         DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
3639         return connector_status_disconnected;
3640 }
3641
3642 static enum drm_connector_status
3643 ironlake_dp_detect(struct intel_dp *intel_dp)
3644 {
3645         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3646         struct drm_i915_private *dev_priv = dev->dev_private;
3647         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3648         enum drm_connector_status status;
3649
3650         /* Can't disconnect eDP, but you can close the lid... */
3651         if (is_edp(intel_dp)) {
3652                 status = intel_panel_detect(dev);
3653                 if (status == connector_status_unknown)
3654                         status = connector_status_connected;
3655                 return status;
3656         }
3657
3658         if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
3659                 return connector_status_disconnected;
3660
3661         return intel_dp_detect_dpcd(intel_dp);
3662 }
3663
3664 static enum drm_connector_status
3665 g4x_dp_detect(struct intel_dp *intel_dp)
3666 {
3667         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3668         struct drm_i915_private *dev_priv = dev->dev_private;
3669         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3670         uint32_t bit;
3671
3672         /* Can't disconnect eDP, but you can close the lid... */
3673         if (is_edp(intel_dp)) {
3674                 enum drm_connector_status status;
3675
3676                 status = intel_panel_detect(dev);
3677                 if (status == connector_status_unknown)
3678                         status = connector_status_connected;
3679                 return status;
3680         }
3681
3682         if (IS_VALLEYVIEW(dev)) {
3683                 switch (intel_dig_port->port) {
3684                 case PORT_B:
3685                         bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
3686                         break;
3687                 case PORT_C:
3688                         bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
3689                         break;
3690                 case PORT_D:
3691                         bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
3692                         break;
3693                 default:
3694                         return connector_status_unknown;
3695                 }
3696         } else {
3697                 switch (intel_dig_port->port) {
3698                 case PORT_B:
3699                         bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
3700                         break;
3701                 case PORT_C:
3702                         bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
3703                         break;
3704                 case PORT_D:
3705                         bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
3706                         break;
3707                 default:
3708                         return connector_status_unknown;
3709                 }
3710         }
3711
3712         if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
3713                 return connector_status_disconnected;
3714
3715         return intel_dp_detect_dpcd(intel_dp);
3716 }
3717
3718 static struct edid *
3719 intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
3720 {
3721         struct intel_connector *intel_connector = to_intel_connector(connector);
3722
3723         /* use cached edid if we have one */
3724         if (intel_connector->edid) {
3725                 /* invalid edid */
3726                 if (IS_ERR(intel_connector->edid))
3727                         return NULL;
3728
3729                 return drm_edid_duplicate(intel_connector->edid);
3730         }
3731
3732         return drm_get_edid(connector, adapter);
3733 }
3734
3735 static int
3736 intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
3737 {
3738         struct intel_connector *intel_connector = to_intel_connector(connector);
3739
3740         /* use cached edid if we have one */
3741         if (intel_connector->edid) {
3742                 /* invalid edid */
3743                 if (IS_ERR(intel_connector->edid))
3744                         return 0;
3745
3746                 return intel_connector_update_modes(connector,
3747                                                     intel_connector->edid);
3748         }
3749
3750         return intel_ddc_get_modes(connector, adapter);
3751 }
3752
3753 static enum drm_connector_status
3754 intel_dp_detect(struct drm_connector *connector, bool force)
3755 {
3756         struct intel_dp *intel_dp = intel_attached_dp(connector);
3757         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3758         struct intel_encoder *intel_encoder = &intel_dig_port->base;
3759         struct drm_device *dev = connector->dev;
3760         struct drm_i915_private *dev_priv = dev->dev_private;
3761         enum drm_connector_status status;
3762         enum intel_display_power_domain power_domain;
3763         struct edid *edid = NULL;
3764         bool ret;
3765
3766         power_domain = intel_display_port_power_domain(intel_encoder);
3767         intel_display_power_get(dev_priv, power_domain);
3768
3769         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3770                       connector->base.id, connector->name);
3771
3772         if (intel_dp->is_mst) {
3773                 /* MST devices are disconnected from a monitor POV */
3774                 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3775                         intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3776                 status = connector_status_disconnected;
3777                 goto out;
3778         }
3779
3780         intel_dp->has_audio = false;
3781
3782         if (HAS_PCH_SPLIT(dev))
3783                 status = ironlake_dp_detect(intel_dp);
3784         else
3785                 status = g4x_dp_detect(intel_dp);
3786
3787         if (status != connector_status_connected)
3788                 goto out;
3789
3790         intel_dp_probe_oui(intel_dp);
3791
3792         ret = intel_dp_probe_mst(intel_dp);
3793         if (ret) {
3794                 /* if we are in MST mode then this connector
3795                    won't appear connected or have anything with EDID on it */
3796                 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3797                         intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3798                 status = connector_status_disconnected;
3799                 goto out;
3800         }
3801
3802         if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
3803                 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
3804         } else {
3805                 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
3806                 if (edid) {
3807                         intel_dp->has_audio = drm_detect_monitor_audio(edid);
3808                         kfree(edid);
3809                 }
3810         }
3811
3812         if (intel_encoder->type != INTEL_OUTPUT_EDP)
3813                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3814         status = connector_status_connected;
3815
3816 out:
3817         intel_display_power_put(dev_priv, power_domain);
3818         return status;
3819 }
3820
3821 static int intel_dp_get_modes(struct drm_connector *connector)
3822 {
3823         struct intel_dp *intel_dp = intel_attached_dp(connector);
3824         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3825         struct intel_encoder *intel_encoder = &intel_dig_port->base;
3826         struct intel_connector *intel_connector = to_intel_connector(connector);
3827         struct drm_device *dev = connector->dev;
3828         struct drm_i915_private *dev_priv = dev->dev_private;
3829         enum intel_display_power_domain power_domain;
3830         int ret;
3831
3832         /* We should parse the EDID data and find out if it has an audio sink
3833          */
3834
3835         power_domain = intel_display_port_power_domain(intel_encoder);
3836         intel_display_power_get(dev_priv, power_domain);
3837
3838         ret = intel_dp_get_edid_modes(connector, &intel_dp->aux.ddc);
3839         intel_display_power_put(dev_priv, power_domain);
3840         if (ret)
3841                 return ret;
3842
3843         /* if eDP has no EDID, fall back to fixed mode */
3844         if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
3845                 struct drm_display_mode *mode;
3846                 mode = drm_mode_duplicate(dev,
3847                                           intel_connector->panel.fixed_mode);
3848                 if (mode) {
3849                         drm_mode_probed_add(connector, mode);
3850                         return 1;
3851                 }
3852         }
3853         return 0;
3854 }
3855
3856 static bool
3857 intel_dp_detect_audio(struct drm_connector *connector)
3858 {
3859         struct intel_dp *intel_dp = intel_attached_dp(connector);
3860         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3861         struct intel_encoder *intel_encoder = &intel_dig_port->base;
3862         struct drm_device *dev = connector->dev;
3863         struct drm_i915_private *dev_priv = dev->dev_private;
3864         enum intel_display_power_domain power_domain;
3865         struct edid *edid;
3866         bool has_audio = false;
3867
3868         power_domain = intel_display_port_power_domain(intel_encoder);
3869         intel_display_power_get(dev_priv, power_domain);
3870
3871         edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
3872         if (edid) {
3873                 has_audio = drm_detect_monitor_audio(edid);
3874                 kfree(edid);
3875         }
3876
3877         intel_display_power_put(dev_priv, power_domain);
3878
3879         return has_audio;
3880 }
3881
3882 static int
3883 intel_dp_set_property(struct drm_connector *connector,
3884                       struct drm_property *property,
3885                       uint64_t val)
3886 {
3887         struct drm_i915_private *dev_priv = connector->dev->dev_private;
3888         struct intel_connector *intel_connector = to_intel_connector(connector);
3889         struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
3890         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
3891         int ret;
3892
3893         ret = drm_object_property_set_value(&connector->base, property, val);
3894         if (ret)
3895                 return ret;
3896
3897         if (property == dev_priv->force_audio_property) {
3898                 int i = val;
3899                 bool has_audio;
3900
3901                 if (i == intel_dp->force_audio)
3902                         return 0;
3903
3904                 intel_dp->force_audio = i;
3905
3906                 if (i == HDMI_AUDIO_AUTO)
3907                         has_audio = intel_dp_detect_audio(connector);
3908                 else
3909                         has_audio = (i == HDMI_AUDIO_ON);
3910
3911                 if (has_audio == intel_dp->has_audio)
3912                         return 0;
3913
3914                 intel_dp->has_audio = has_audio;
3915                 goto done;
3916         }
3917
3918         if (property == dev_priv->broadcast_rgb_property) {
3919                 bool old_auto = intel_dp->color_range_auto;
3920                 uint32_t old_range = intel_dp->color_range;
3921
3922                 switch (val) {
3923                 case INTEL_BROADCAST_RGB_AUTO:
3924                         intel_dp->color_range_auto = true;
3925                         break;
3926                 case INTEL_BROADCAST_RGB_FULL:
3927                         intel_dp->color_range_auto = false;
3928                         intel_dp->color_range = 0;
3929                         break;
3930                 case INTEL_BROADCAST_RGB_LIMITED:
3931                         intel_dp->color_range_auto = false;
3932                         intel_dp->color_range = DP_COLOR_RANGE_16_235;
3933                         break;
3934                 default:
3935                         return -EINVAL;
3936                 }
3937
3938                 if (old_auto == intel_dp->color_range_auto &&
3939                     old_range == intel_dp->color_range)
3940                         return 0;
3941
3942                 goto done;
3943         }
3944
3945         if (is_edp(intel_dp) &&
3946             property == connector->dev->mode_config.scaling_mode_property) {
3947                 if (val == DRM_MODE_SCALE_NONE) {
3948                         DRM_DEBUG_KMS("no scaling not supported\n");
3949                         return -EINVAL;
3950                 }
3951
3952                 if (intel_connector->panel.fitting_mode == val) {
3953                         /* the eDP scaling property is not changed */
3954                         return 0;
3955                 }
3956                 intel_connector->panel.fitting_mode = val;
3957
3958                 goto done;
3959         }
3960
3961         return -EINVAL;
3962
3963 done:
3964         if (intel_encoder->base.crtc)
3965                 intel_crtc_restore_mode(intel_encoder->base.crtc);
3966
3967         return 0;
3968 }
3969
3970 static void
3971 intel_dp_connector_destroy(struct drm_connector *connector)
3972 {
3973         struct intel_connector *intel_connector = to_intel_connector(connector);
3974
3975         if (!IS_ERR_OR_NULL(intel_connector->edid))
3976                 kfree(intel_connector->edid);
3977
3978         /* Can't call is_edp() since the encoder may have been destroyed
3979          * already. */
3980         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3981                 intel_panel_fini(&intel_connector->panel);
3982
3983         drm_connector_cleanup(connector);
3984         kfree(connector);
3985 }
3986
3987 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
3988 {
3989         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
3990         struct intel_dp *intel_dp = &intel_dig_port->dp;
3991         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3992
3993         drm_dp_aux_unregister(&intel_dp->aux);
3994         intel_dp_mst_encoder_cleanup(intel_dig_port);
3995         drm_encoder_cleanup(encoder);
3996         if (is_edp(intel_dp)) {
3997                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3998                 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
3999                 edp_panel_vdd_off_sync(intel_dp);
4000                 drm_modeset_unlock(&dev->mode_config.connection_mutex);
4001                 if (intel_dp->edp_notifier.notifier_call) {
4002                         unregister_reboot_notifier(&intel_dp->edp_notifier);
4003                         intel_dp->edp_notifier.notifier_call = NULL;
4004                 }
4005         }
4006         kfree(intel_dig_port);
4007 }
4008
4009 static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4010 {
4011         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4012
4013         if (!is_edp(intel_dp))
4014                 return;
4015
4016         edp_panel_vdd_off_sync(intel_dp);
4017 }
4018
4019 static void intel_dp_encoder_reset(struct drm_encoder *encoder)
4020 {
4021         intel_edp_panel_vdd_sanitize(to_intel_encoder(encoder));
4022 }
4023
4024 static const struct drm_connector_funcs intel_dp_connector_funcs = {
4025         .dpms = intel_connector_dpms,
4026         .detect = intel_dp_detect,
4027         .fill_modes = drm_helper_probe_single_connector_modes,
4028         .set_property = intel_dp_set_property,
4029         .destroy = intel_dp_connector_destroy,
4030 };
4031
4032 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4033         .get_modes = intel_dp_get_modes,
4034         .mode_valid = intel_dp_mode_valid,
4035         .best_encoder = intel_best_encoder,
4036 };
4037
4038 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
4039         .reset = intel_dp_encoder_reset,
4040         .destroy = intel_dp_encoder_destroy,
4041 };
4042
4043 void
4044 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
4045 {
4046         return;
4047 }
4048
4049 bool
4050 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4051 {
4052         struct intel_dp *intel_dp = &intel_dig_port->dp;
4053         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4054         struct drm_device *dev = intel_dig_port->base.base.dev;
4055         struct drm_i915_private *dev_priv = dev->dev_private;
4056         enum intel_display_power_domain power_domain;
4057         bool ret = true;
4058
4059         if (intel_dig_port->base.type != INTEL_OUTPUT_EDP)
4060                 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
4061
4062         DRM_DEBUG_KMS("got hpd irq on port %d - %s\n", intel_dig_port->port,
4063                       long_hpd ? "long" : "short");
4064
4065         power_domain = intel_display_port_power_domain(intel_encoder);
4066         intel_display_power_get(dev_priv, power_domain);
4067
4068         if (long_hpd) {
4069                 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4070                         goto mst_fail;
4071
4072                 if (!intel_dp_get_dpcd(intel_dp)) {
4073                         goto mst_fail;
4074                 }
4075
4076                 intel_dp_probe_oui(intel_dp);
4077
4078                 if (!intel_dp_probe_mst(intel_dp))
4079                         goto mst_fail;
4080
4081         } else {
4082                 if (intel_dp->is_mst) {
4083                         if (intel_dp_check_mst_status(intel_dp) == -EINVAL)
4084                                 goto mst_fail;
4085                 }
4086
4087                 if (!intel_dp->is_mst) {
4088                         /*
4089                          * we'll check the link status via the normal hot plug path later -
4090                          * but for short hpds we should check it now
4091                          */
4092                         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4093                         intel_dp_check_link_status(intel_dp);
4094                         drm_modeset_unlock(&dev->mode_config.connection_mutex);
4095                 }
4096         }
4097         ret = false;
4098         goto put_power;
4099 mst_fail:
4100         /* if we were in MST mode, and device is not there get out of MST mode */
4101         if (intel_dp->is_mst) {
4102                 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4103                 intel_dp->is_mst = false;
4104                 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4105         }
4106 put_power:
4107         intel_display_power_put(dev_priv, power_domain);
4108
4109         return ret;
4110 }
4111
4112 /* Return which DP Port should be selected for Transcoder DP control */
4113 int
4114 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4115 {
4116         struct drm_device *dev = crtc->dev;
4117         struct intel_encoder *intel_encoder;
4118         struct intel_dp *intel_dp;
4119
4120         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4121                 intel_dp = enc_to_intel_dp(&intel_encoder->base);
4122
4123                 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4124                     intel_encoder->type == INTEL_OUTPUT_EDP)
4125                         return intel_dp->output_reg;
4126         }
4127
4128         return -1;
4129 }
4130
4131 /* check the VBT to see whether the eDP is on DP-D port */
4132 bool intel_dp_is_edp(struct drm_device *dev, enum port port)
4133 {
4134         struct drm_i915_private *dev_priv = dev->dev_private;
4135         union child_device_config *p_child;
4136         int i;
4137         static const short port_mapping[] = {
4138                 [PORT_B] = PORT_IDPB,
4139                 [PORT_C] = PORT_IDPC,
4140                 [PORT_D] = PORT_IDPD,
4141         };
4142
4143         if (port == PORT_A)
4144                 return true;
4145
4146         if (!dev_priv->vbt.child_dev_num)
4147                 return false;
4148
4149         for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
4150                 p_child = dev_priv->vbt.child_dev + i;
4151
4152                 if (p_child->common.dvo_port == port_mapping[port] &&
4153                     (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
4154                     (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
4155                         return true;
4156         }
4157         return false;
4158 }
4159
4160 void
4161 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
4162 {
4163         struct intel_connector *intel_connector = to_intel_connector(connector);
4164
4165         intel_attach_force_audio_property(connector);
4166         intel_attach_broadcast_rgb_property(connector);
4167         intel_dp->color_range_auto = true;
4168
4169         if (is_edp(intel_dp)) {
4170                 drm_mode_create_scaling_mode_property(connector->dev);
4171                 drm_object_attach_property(
4172                         &connector->base,
4173                         connector->dev->mode_config.scaling_mode_property,
4174                         DRM_MODE_SCALE_ASPECT);
4175                 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
4176         }
4177 }
4178
4179 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
4180 {
4181         intel_dp->last_power_cycle = jiffies;
4182         intel_dp->last_power_on = jiffies;
4183         intel_dp->last_backlight_off = jiffies;
4184 }
4185
4186 static void
4187 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
4188                                     struct intel_dp *intel_dp,
4189                                     struct edp_power_seq *out)
4190 {
4191         struct drm_i915_private *dev_priv = dev->dev_private;
4192         struct edp_power_seq cur, vbt, spec, final;
4193         u32 pp_on, pp_off, pp_div, pp;
4194         int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
4195
4196         if (HAS_PCH_SPLIT(dev)) {
4197                 pp_ctrl_reg = PCH_PP_CONTROL;
4198                 pp_on_reg = PCH_PP_ON_DELAYS;
4199                 pp_off_reg = PCH_PP_OFF_DELAYS;
4200                 pp_div_reg = PCH_PP_DIVISOR;
4201         } else {
4202                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4203
4204                 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
4205                 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4206                 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4207                 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
4208         }
4209
4210         /* Workaround: Need to write PP_CONTROL with the unlock key as
4211          * the very first thing. */
4212         pp = ironlake_get_pp_control(intel_dp);
4213         I915_WRITE(pp_ctrl_reg, pp);
4214
4215         pp_on = I915_READ(pp_on_reg);
4216         pp_off = I915_READ(pp_off_reg);
4217         pp_div = I915_READ(pp_div_reg);
4218
4219         /* Pull timing values out of registers */
4220         cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
4221                 PANEL_POWER_UP_DELAY_SHIFT;
4222
4223         cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
4224                 PANEL_LIGHT_ON_DELAY_SHIFT;
4225
4226         cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
4227                 PANEL_LIGHT_OFF_DELAY_SHIFT;
4228
4229         cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
4230                 PANEL_POWER_DOWN_DELAY_SHIFT;
4231
4232         cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
4233                        PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
4234
4235         DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4236                       cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
4237
4238         vbt = dev_priv->vbt.edp_pps;
4239
4240         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
4241          * our hw here, which are all in 100usec. */
4242         spec.t1_t3 = 210 * 10;
4243         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
4244         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
4245         spec.t10 = 500 * 10;
4246         /* This one is special and actually in units of 100ms, but zero
4247          * based in the hw (so we need to add 100 ms). But the sw vbt
4248          * table multiplies it with 1000 to make it in units of 100usec,
4249          * too. */
4250         spec.t11_t12 = (510 + 100) * 10;
4251
4252         DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4253                       vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
4254
4255         /* Use the max of the register settings and vbt. If both are
4256          * unset, fall back to the spec limits. */
4257 #define assign_final(field)     final.field = (max(cur.field, vbt.field) == 0 ? \
4258                                        spec.field : \
4259                                        max(cur.field, vbt.field))
4260         assign_final(t1_t3);
4261         assign_final(t8);
4262         assign_final(t9);
4263         assign_final(t10);
4264         assign_final(t11_t12);
4265 #undef assign_final
4266
4267 #define get_delay(field)        (DIV_ROUND_UP(final.field, 10))
4268         intel_dp->panel_power_up_delay = get_delay(t1_t3);
4269         intel_dp->backlight_on_delay = get_delay(t8);
4270         intel_dp->backlight_off_delay = get_delay(t9);
4271         intel_dp->panel_power_down_delay = get_delay(t10);
4272         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
4273 #undef get_delay
4274
4275         DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4276                       intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
4277                       intel_dp->panel_power_cycle_delay);
4278
4279         DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4280                       intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
4281
4282         if (out)
4283                 *out = final;
4284 }
4285
4286 static void
4287 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
4288                                               struct intel_dp *intel_dp,
4289                                               struct edp_power_seq *seq)
4290 {
4291         struct drm_i915_private *dev_priv = dev->dev_private;
4292         u32 pp_on, pp_off, pp_div, port_sel = 0;
4293         int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
4294         int pp_on_reg, pp_off_reg, pp_div_reg;
4295
4296         if (HAS_PCH_SPLIT(dev)) {
4297                 pp_on_reg = PCH_PP_ON_DELAYS;
4298                 pp_off_reg = PCH_PP_OFF_DELAYS;
4299                 pp_div_reg = PCH_PP_DIVISOR;
4300         } else {
4301                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4302
4303                 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4304                 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4305                 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
4306         }
4307
4308         /*
4309          * And finally store the new values in the power sequencer. The
4310          * backlight delays are set to 1 because we do manual waits on them. For
4311          * T8, even BSpec recommends doing it. For T9, if we don't do this,
4312          * we'll end up waiting for the backlight off delay twice: once when we
4313          * do the manual sleep, and once when we disable the panel and wait for
4314          * the PP_STATUS bit to become zero.
4315          */
4316         pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
4317                 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
4318         pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
4319                  (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
4320         /* Compute the divisor for the pp clock, simply match the Bspec
4321          * formula. */
4322         pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
4323         pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
4324                         << PANEL_POWER_CYCLE_DELAY_SHIFT);
4325
4326         /* Haswell doesn't have any port selection bits for the panel
4327          * power sequencer any more. */
4328         if (IS_VALLEYVIEW(dev)) {
4329                 if (dp_to_dig_port(intel_dp)->port == PORT_B)
4330                         port_sel = PANEL_PORT_SELECT_DPB_VLV;
4331                 else
4332                         port_sel = PANEL_PORT_SELECT_DPC_VLV;
4333         } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
4334                 if (dp_to_dig_port(intel_dp)->port == PORT_A)
4335                         port_sel = PANEL_PORT_SELECT_DPA;
4336                 else
4337                         port_sel = PANEL_PORT_SELECT_DPD;
4338         }
4339
4340         pp_on |= port_sel;
4341
4342         I915_WRITE(pp_on_reg, pp_on);
4343         I915_WRITE(pp_off_reg, pp_off);
4344         I915_WRITE(pp_div_reg, pp_div);
4345
4346         DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
4347                       I915_READ(pp_on_reg),
4348                       I915_READ(pp_off_reg),
4349                       I915_READ(pp_div_reg));
4350 }
4351
4352 void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
4353 {
4354         struct drm_i915_private *dev_priv = dev->dev_private;
4355         struct intel_encoder *encoder;
4356         struct intel_dp *intel_dp = NULL;
4357         struct intel_crtc_config *config = NULL;
4358         struct intel_crtc *intel_crtc = NULL;
4359         struct intel_connector *intel_connector = dev_priv->drrs.connector;
4360         u32 reg, val;
4361         enum edp_drrs_refresh_rate_type index = DRRS_HIGH_RR;
4362
4363         if (refresh_rate <= 0) {
4364                 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
4365                 return;
4366         }
4367
4368         if (intel_connector == NULL) {
4369                 DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
4370                 return;
4371         }
4372
4373         /*
4374          * FIXME: This needs proper synchronization with psr state. But really
4375          * hard to tell without seeing the user of this function of this code.
4376          * Check locking and ordering once that lands.
4377          */
4378         if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) {
4379                 DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
4380                 return;
4381         }
4382
4383         encoder = intel_attached_encoder(&intel_connector->base);
4384         intel_dp = enc_to_intel_dp(&encoder->base);
4385         intel_crtc = encoder->new_crtc;
4386
4387         if (!intel_crtc) {
4388                 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
4389                 return;
4390         }
4391
4392         config = &intel_crtc->config;
4393
4394         if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) {
4395                 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
4396                 return;
4397         }
4398
4399         if (intel_connector->panel.downclock_mode->vrefresh == refresh_rate)
4400                 index = DRRS_LOW_RR;
4401
4402         if (index == intel_dp->drrs_state.refresh_rate_type) {
4403                 DRM_DEBUG_KMS(
4404                         "DRRS requested for previously set RR...ignoring\n");
4405                 return;
4406         }
4407
4408         if (!intel_crtc->active) {
4409                 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
4410                 return;
4411         }
4412
4413         if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
4414                 reg = PIPECONF(intel_crtc->config.cpu_transcoder);
4415                 val = I915_READ(reg);
4416                 if (index > DRRS_HIGH_RR) {
4417                         val |= PIPECONF_EDP_RR_MODE_SWITCH;
4418                         intel_dp_set_m_n(intel_crtc);
4419                 } else {
4420                         val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
4421                 }
4422                 I915_WRITE(reg, val);
4423         }
4424
4425         /*
4426          * mutex taken to ensure that there is no race between differnt
4427          * drrs calls trying to update refresh rate. This scenario may occur
4428          * in future when idleness detection based DRRS in kernel and
4429          * possible calls from user space to set differnt RR are made.
4430          */
4431
4432         mutex_lock(&intel_dp->drrs_state.mutex);
4433
4434         intel_dp->drrs_state.refresh_rate_type = index;
4435
4436         mutex_unlock(&intel_dp->drrs_state.mutex);
4437
4438         DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
4439 }
4440
4441 static struct drm_display_mode *
4442 intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
4443                         struct intel_connector *intel_connector,
4444                         struct drm_display_mode *fixed_mode)
4445 {
4446         struct drm_connector *connector = &intel_connector->base;
4447         struct intel_dp *intel_dp = &intel_dig_port->dp;
4448         struct drm_device *dev = intel_dig_port->base.base.dev;
4449         struct drm_i915_private *dev_priv = dev->dev_private;
4450         struct drm_display_mode *downclock_mode = NULL;
4451
4452         if (INTEL_INFO(dev)->gen <= 6) {
4453                 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
4454                 return NULL;
4455         }
4456
4457         if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
4458                 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
4459                 return NULL;
4460         }
4461
4462         downclock_mode = intel_find_panel_downclock
4463                                         (dev, fixed_mode, connector);
4464
4465         if (!downclock_mode) {
4466                 DRM_DEBUG_KMS("DRRS not supported\n");
4467                 return NULL;
4468         }
4469
4470         dev_priv->drrs.connector = intel_connector;
4471
4472         mutex_init(&intel_dp->drrs_state.mutex);
4473
4474         intel_dp->drrs_state.type = dev_priv->vbt.drrs_type;
4475
4476         intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR;
4477         DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
4478         return downclock_mode;
4479 }
4480
4481 void intel_edp_panel_vdd_sanitize(struct intel_encoder *intel_encoder)
4482 {
4483         struct drm_device *dev = intel_encoder->base.dev;
4484         struct drm_i915_private *dev_priv = dev->dev_private;
4485         struct intel_dp *intel_dp;
4486         enum intel_display_power_domain power_domain;
4487
4488         if (intel_encoder->type != INTEL_OUTPUT_EDP)
4489                 return;
4490
4491         intel_dp = enc_to_intel_dp(&intel_encoder->base);
4492         if (!edp_have_panel_vdd(intel_dp))
4493                 return;
4494         /*
4495          * The VDD bit needs a power domain reference, so if the bit is
4496          * already enabled when we boot or resume, grab this reference and
4497          * schedule a vdd off, so we don't hold on to the reference
4498          * indefinitely.
4499          */
4500         DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4501         power_domain = intel_display_port_power_domain(intel_encoder);
4502         intel_display_power_get(dev_priv, power_domain);
4503
4504         edp_panel_vdd_schedule_off(intel_dp);
4505 }
4506
4507 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
4508                                      struct intel_connector *intel_connector,
4509                                      struct edp_power_seq *power_seq)
4510 {
4511         struct drm_connector *connector = &intel_connector->base;
4512         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4513         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4514         struct drm_device *dev = intel_encoder->base.dev;
4515         struct drm_i915_private *dev_priv = dev->dev_private;
4516         struct drm_display_mode *fixed_mode = NULL;
4517         struct drm_display_mode *downclock_mode = NULL;
4518         bool has_dpcd;
4519         struct drm_display_mode *scan;
4520         struct edid *edid;
4521
4522         intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED;
4523
4524         if (!is_edp(intel_dp))
4525                 return true;
4526
4527         intel_edp_panel_vdd_sanitize(intel_encoder);
4528
4529         /* Cache DPCD and EDID for edp. */
4530         intel_edp_panel_vdd_on(intel_dp);
4531         has_dpcd = intel_dp_get_dpcd(intel_dp);
4532         edp_panel_vdd_off(intel_dp, false);
4533
4534         if (has_dpcd) {
4535                 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
4536                         dev_priv->no_aux_handshake =
4537                                 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
4538                                 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
4539         } else {
4540                 /* if this fails, presume the device is a ghost */
4541                 DRM_INFO("failed to retrieve link info, disabling eDP\n");
4542                 return false;
4543         }
4544
4545         /* We now know it's not a ghost, init power sequence regs. */
4546         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq);
4547
4548         mutex_lock(&dev->mode_config.mutex);
4549         edid = drm_get_edid(connector, &intel_dp->aux.ddc);
4550         if (edid) {
4551                 if (drm_add_edid_modes(connector, edid)) {
4552                         drm_mode_connector_update_edid_property(connector,
4553                                                                 edid);
4554                         drm_edid_to_eld(connector, edid);
4555                 } else {
4556                         kfree(edid);
4557                         edid = ERR_PTR(-EINVAL);
4558                 }
4559         } else {
4560                 edid = ERR_PTR(-ENOENT);
4561         }
4562         intel_connector->edid = edid;
4563
4564         /* prefer fixed mode from EDID if available */
4565         list_for_each_entry(scan, &connector->probed_modes, head) {
4566                 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
4567                         fixed_mode = drm_mode_duplicate(dev, scan);
4568                         downclock_mode = intel_dp_drrs_init(
4569                                                 intel_dig_port,
4570                                                 intel_connector, fixed_mode);
4571                         break;
4572                 }
4573         }
4574
4575         /* fallback to VBT if available for eDP */
4576         if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
4577                 fixed_mode = drm_mode_duplicate(dev,
4578                                         dev_priv->vbt.lfp_lvds_vbt_mode);
4579                 if (fixed_mode)
4580                         fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
4581         }
4582         mutex_unlock(&dev->mode_config.mutex);
4583
4584         if (IS_VALLEYVIEW(dev)) {
4585                 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
4586                 register_reboot_notifier(&intel_dp->edp_notifier);
4587         }
4588
4589         intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
4590         intel_panel_setup_backlight(connector);
4591
4592         return true;
4593 }
4594
4595 bool
4596 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
4597                         struct intel_connector *intel_connector)
4598 {
4599         struct drm_connector *connector = &intel_connector->base;
4600         struct intel_dp *intel_dp = &intel_dig_port->dp;
4601         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4602         struct drm_device *dev = intel_encoder->base.dev;
4603         struct drm_i915_private *dev_priv = dev->dev_private;
4604         enum port port = intel_dig_port->port;
4605         struct edp_power_seq power_seq = { 0 };
4606         int type;
4607
4608         /* intel_dp vfuncs */
4609         if (IS_VALLEYVIEW(dev))
4610                 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
4611         else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4612                 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
4613         else if (HAS_PCH_SPLIT(dev))
4614                 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
4615         else
4616                 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
4617
4618         intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
4619
4620         /* Preserve the current hw state. */
4621         intel_dp->DP = I915_READ(intel_dp->output_reg);
4622         intel_dp->attached_connector = intel_connector;
4623
4624         if (intel_dp_is_edp(dev, port))
4625                 type = DRM_MODE_CONNECTOR_eDP;
4626         else
4627                 type = DRM_MODE_CONNECTOR_DisplayPort;
4628
4629         /*
4630          * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
4631          * for DP the encoder type can be set by the caller to
4632          * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
4633          */
4634         if (type == DRM_MODE_CONNECTOR_eDP)
4635                 intel_encoder->type = INTEL_OUTPUT_EDP;
4636
4637         DRM_DEBUG_KMS("Adding %s connector on port %c\n",
4638                         type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
4639                         port_name(port));
4640
4641         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
4642         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
4643
4644         connector->interlace_allowed = true;
4645         connector->doublescan_allowed = 0;
4646
4647         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4648                           edp_panel_vdd_work);
4649
4650         intel_connector_attach_encoder(intel_connector, intel_encoder);
4651         drm_connector_register(connector);
4652
4653         if (HAS_DDI(dev))
4654                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
4655         else
4656                 intel_connector->get_hw_state = intel_connector_get_hw_state;
4657         intel_connector->unregister = intel_dp_connector_unregister;
4658
4659         /* Set up the hotplug pin. */
4660         switch (port) {
4661         case PORT_A:
4662                 intel_encoder->hpd_pin = HPD_PORT_A;
4663                 break;
4664         case PORT_B:
4665                 intel_encoder->hpd_pin = HPD_PORT_B;
4666                 break;
4667         case PORT_C:
4668                 intel_encoder->hpd_pin = HPD_PORT_C;
4669                 break;
4670         case PORT_D:
4671                 intel_encoder->hpd_pin = HPD_PORT_D;
4672                 break;
4673         default:
4674                 BUG();
4675         }
4676
4677         if (is_edp(intel_dp)) {
4678                 intel_dp_init_panel_power_timestamps(intel_dp);
4679                 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
4680         }
4681
4682         intel_dp_aux_init(intel_dp, intel_connector);
4683
4684         /* init MST on ports that can support it */
4685         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
4686                 if (port == PORT_B || port == PORT_C || port == PORT_D) {
4687                         intel_dp_mst_encoder_init(intel_dig_port, intel_connector->base.base.id);
4688                 }
4689         }
4690
4691         if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) {
4692                 drm_dp_aux_unregister(&intel_dp->aux);
4693                 if (is_edp(intel_dp)) {
4694                         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4695                         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4696                         edp_panel_vdd_off_sync(intel_dp);
4697                         drm_modeset_unlock(&dev->mode_config.connection_mutex);
4698                 }
4699                 drm_connector_unregister(connector);
4700                 drm_connector_cleanup(connector);
4701                 return false;
4702         }
4703
4704         intel_dp_add_properties(intel_dp, connector);
4705
4706         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
4707          * 0xd.  Failure to do so will result in spurious interrupts being
4708          * generated on the port when a cable is not attached.
4709          */
4710         if (IS_G4X(dev) && !IS_GM45(dev)) {
4711                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
4712                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
4713         }
4714
4715         return true;
4716 }
4717
4718 void
4719 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
4720 {
4721         struct drm_i915_private *dev_priv = dev->dev_private;
4722         struct intel_digital_port *intel_dig_port;
4723         struct intel_encoder *intel_encoder;
4724         struct drm_encoder *encoder;
4725         struct intel_connector *intel_connector;
4726
4727         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
4728         if (!intel_dig_port)
4729                 return;
4730
4731         intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
4732         if (!intel_connector) {
4733                 kfree(intel_dig_port);
4734                 return;
4735         }
4736
4737         intel_encoder = &intel_dig_port->base;
4738         encoder = &intel_encoder->base;
4739
4740         drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
4741                          DRM_MODE_ENCODER_TMDS);
4742
4743         intel_encoder->compute_config = intel_dp_compute_config;
4744         intel_encoder->disable = intel_disable_dp;
4745         intel_encoder->get_hw_state = intel_dp_get_hw_state;
4746         intel_encoder->get_config = intel_dp_get_config;
4747         intel_encoder->suspend = intel_dp_encoder_suspend;
4748         if (IS_CHERRYVIEW(dev)) {
4749                 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
4750                 intel_encoder->pre_enable = chv_pre_enable_dp;
4751                 intel_encoder->enable = vlv_enable_dp;
4752                 intel_encoder->post_disable = chv_post_disable_dp;
4753         } else if (IS_VALLEYVIEW(dev)) {
4754                 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
4755                 intel_encoder->pre_enable = vlv_pre_enable_dp;
4756                 intel_encoder->enable = vlv_enable_dp;
4757                 intel_encoder->post_disable = vlv_post_disable_dp;
4758         } else {
4759                 intel_encoder->pre_enable = g4x_pre_enable_dp;
4760                 intel_encoder->enable = g4x_enable_dp;
4761                 intel_encoder->post_disable = g4x_post_disable_dp;
4762         }
4763
4764         intel_dig_port->port = port;
4765         intel_dig_port->dp.output_reg = output_reg;
4766
4767         intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4768         if (IS_CHERRYVIEW(dev)) {
4769                 if (port == PORT_D)
4770                         intel_encoder->crtc_mask = 1 << 2;
4771                 else
4772                         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
4773         } else {
4774                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
4775         }
4776         intel_encoder->cloneable = 0;
4777         intel_encoder->hot_plug = intel_dp_hot_plug;
4778
4779         intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
4780         dev_priv->hpd_irq_port[port] = intel_dig_port;
4781
4782         if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
4783                 drm_encoder_cleanup(encoder);
4784                 kfree(intel_dig_port);
4785                 kfree(intel_connector);
4786         }
4787 }
4788
4789 void intel_dp_mst_suspend(struct drm_device *dev)
4790 {
4791         struct drm_i915_private *dev_priv = dev->dev_private;
4792         int i;
4793
4794         /* disable MST */
4795         for (i = 0; i < I915_MAX_PORTS; i++) {
4796                 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
4797                 if (!intel_dig_port)
4798                         continue;
4799
4800                 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
4801                         if (!intel_dig_port->dp.can_mst)
4802                                 continue;
4803                         if (intel_dig_port->dp.is_mst)
4804                                 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
4805                 }
4806         }
4807 }
4808
4809 void intel_dp_mst_resume(struct drm_device *dev)
4810 {
4811         struct drm_i915_private *dev_priv = dev->dev_private;
4812         int i;
4813
4814         for (i = 0; i < I915_MAX_PORTS; i++) {
4815                 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
4816                 if (!intel_dig_port)
4817                         continue;
4818                 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
4819                         int ret;
4820
4821                         if (!intel_dig_port->dp.can_mst)
4822                                 continue;
4823
4824                         ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
4825                         if (ret != 0) {
4826                                 intel_dp_check_mst_status(&intel_dig_port->dp);
4827                         }
4828                 }
4829         }
4830 }