drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include "drmP.h"
  31 #include "drm.h"
  32 #include "drm_crtc.h"
  33 #include "drm_crtc_helper.h"
  34 #include "intel_drv.h"
  35 #include "i915_drm.h"
  36 #include "i915_drv.h"
  37 #include "drm_dp_helper.h"
  38
  39
  40 #define DP_LINK_STATUS_SIZE     6
  41 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  42
  43 #define DP_LINK_CONFIGURATION_SIZE      9
  44
  45 struct intel_dp {
  46         struct intel_encoder base;
  47         uint32_t output_reg;
  48         uint32_t DP;
  49         uint8_t  link_configuration[DP_LINK_CONFIGURATION_SIZE];
  50         bool has_audio;
  51         int force_audio;
  52         uint32_t color_range;
  53         int dpms_mode;
  54         uint8_t link_bw;
  55         uint8_t lane_count;
  56         uint8_t dpcd[8];
  57         struct i2c_adapter adapter;
  58         struct i2c_algo_dp_aux_data algo;
  59         bool is_pch_edp;
  60         uint8_t train_set[4];
  61         uint8_t link_status[DP_LINK_STATUS_SIZE];
  62         int panel_power_up_delay;
  63         int panel_power_down_delay;
  64         int panel_power_cycle_delay;
  65         int backlight_on_delay;
  66         int backlight_off_delay;
  67         struct drm_display_mode *panel_fixed_mode;  /* for eDP */
  68 };
  69
  70 /**
  71  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
  72  * @intel_dp: DP struct
  73  *
  74  * If a CPU or PCH DP output is attached to an eDP panel, this function
  75  * will return true, and false otherwise.
  76  */
  77 static bool is_edp(struct intel_dp *intel_dp)
  78 {
  79         return intel_dp->base.type == INTEL_OUTPUT_EDP;
  80 }
  81
  82 /**
  83  * is_pch_edp - is the port on the PCH and attached to an eDP panel?
  84  * @intel_dp: DP struct
  85  *
  86  * Returns true if the given DP struct corresponds to a PCH DP port attached
  87  * to an eDP panel, false otherwise.  Helpful for determining whether we
  88  * may need FDI resources for a given DP output or not.
  89  */
  90 static bool is_pch_edp(struct intel_dp *intel_dp)
  91 {
  92         return intel_dp->is_pch_edp;
  93 }
  94
  95 static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
  96 {
  97         return container_of(encoder, struct intel_dp, base.base);
  98 }
  99
 100 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
 101 {
 102         return container_of(intel_attached_encoder(connector),
 103                             struct intel_dp, base);
 104 }
 105
 106 /**
 107  * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
 108  * @encoder: DRM encoder
 109  *
 110  * Return true if @encoder corresponds to a PCH attached eDP panel.  Needed
 111  * by intel_display.c.
 112  */
 113 bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
 114 {
 115         struct intel_dp *intel_dp;
 116
 117         if (!encoder)
 118                 return false;
 119
 120         intel_dp = enc_to_intel_dp(encoder);
 121
 122         return is_pch_edp(intel_dp);
 123 }
 124
 125 static void intel_dp_start_link_train(struct intel_dp *intel_dp);
 126 static void intel_dp_complete_link_train(struct intel_dp *intel_dp);
 127 static void intel_dp_link_down(struct intel_dp *intel_dp);
 128
 129 void
 130 intel_edp_link_config (struct intel_encoder *intel_encoder,
 131                        int *lane_num, int *link_bw)
 132 {
 133         struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
 134
 135         *lane_num = intel_dp->lane_count;
 136         if (intel_dp->link_bw == DP_LINK_BW_1_62)
 137                 *link_bw = 162000;
 138         else if (intel_dp->link_bw == DP_LINK_BW_2_7)
 139                 *link_bw = 270000;
 140 }
 141
 142 static int
 143 intel_dp_max_lane_count(struct intel_dp *intel_dp)
 144 {
 145         int max_lane_count = 4;
 146
 147         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
 148                 max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;
 149                 switch (max_lane_count) {
 150                 case 1: case 2: case 4:
 151                         break;
 152                 default:
 153                         max_lane_count = 4;
 154                 }
 155         }
 156         return max_lane_count;
 157 }
 158
 159 static int
 160 intel_dp_max_link_bw(struct intel_dp *intel_dp)
 161 {
 162         int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
 163
 164         switch (max_link_bw) {
 165         case DP_LINK_BW_1_62:
 166         case DP_LINK_BW_2_7:
 167                 break;
 168         default:
 169                 max_link_bw = DP_LINK_BW_1_62;
 170                 break;
 171         }
 172         return max_link_bw;
 173 }
 174
 175 static int
 176 intel_dp_link_clock(uint8_t link_bw)
 177 {
 178         if (link_bw == DP_LINK_BW_2_7)
 179                 return 270000;
 180         else
 181                 return 162000;
 182 }
 183
 184 /* I think this is a fiction */
 185 static int
 186 intel_dp_link_required(struct drm_device *dev, struct intel_dp *intel_dp, int pixel_clock)
 187 {
 188         struct drm_crtc *crtc = intel_dp->base.base.crtc;
 189         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 190         int bpp = 24;
 191
 192         if (intel_crtc)
 193                 bpp = intel_crtc->bpp;
 194
 195         return (pixel_clock * bpp + 7) / 8;
 196 }
 197
 198 static int
 199 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 200 {
 201         return (max_link_clock * max_lanes * 8) / 10;
 202 }
 203
 204 static int
 205 intel_dp_mode_valid(struct drm_connector *connector,
 206                     struct drm_display_mode *mode)
 207 {
 208         struct intel_dp *intel_dp = intel_attached_dp(connector);
 209         int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
 210         int max_lanes = intel_dp_max_lane_count(intel_dp);
 211
 212         if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
 213                 if (mode->hdisplay > intel_dp->panel_fixed_mode->hdisplay)
 214                         return MODE_PANEL;
 215
 216                 if (mode->vdisplay > intel_dp->panel_fixed_mode->vdisplay)
 217                         return MODE_PANEL;
 218         }
 219
 220         /* only refuse the mode on non eDP since we have seen some weird eDP panels
 221            which are outside spec tolerances but somehow work by magic */
 222         if (!is_edp(intel_dp) &&
 223             (intel_dp_link_required(connector->dev, intel_dp, mode->clock)
 224              > intel_dp_max_data_rate(max_link_clock, max_lanes)))
 225                 return MODE_CLOCK_HIGH;
 226
 227         if (mode->clock < 10000)
 228                 return MODE_CLOCK_LOW;
 229
 230         return MODE_OK;
 231 }
 232
 233 static uint32_t
 234 pack_aux(uint8_t *src, int src_bytes)
 235 {
 236         int     i;
 237         uint32_t v = 0;
 238
 239         if (src_bytes > 4)
 240                 src_bytes = 4;
 241         for (i = 0; i < src_bytes; i++)
 242                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 243         return v;
 244 }
 245
 246 static void
 247 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 248 {
 249         int i;
 250         if (dst_bytes > 4)
 251                 dst_bytes = 4;
 252         for (i = 0; i < dst_bytes; i++)
 253                 dst[i] = src >> ((3-i) * 8);
 254 }
 255
 256 /* hrawclock is 1/4 the FSB frequency */
 257 static int
 258 intel_hrawclk(struct drm_device *dev)
 259 {
 260         struct drm_i915_private *dev_priv = dev->dev_private;
 261         uint32_t clkcfg;
 262
 263         clkcfg = I915_READ(CLKCFG);
 264         switch (clkcfg & CLKCFG_FSB_MASK) {
 265         case CLKCFG_FSB_400:
 266                 return 100;
 267         case CLKCFG_FSB_533:
 268                 return 133;
 269         case CLKCFG_FSB_667:
 270                 return 166;
 271         case CLKCFG_FSB_800:
 272                 return 200;
 273         case CLKCFG_FSB_1067:
 274                 return 266;
 275         case CLKCFG_FSB_1333:
 276                 return 333;
 277         /* these two are just a guess; one of them might be right */
 278         case CLKCFG_FSB_1600:
 279         case CLKCFG_FSB_1600_ALT:
 280                 return 400;
 281         default:
 282                 return 133;
 283         }
 284 }
 285
 286 static void
 287 intel_dp_check_edp(struct intel_dp *intel_dp)
 288 {
 289         struct drm_device *dev = intel_dp->base.base.dev;
 290         struct drm_i915_private *dev_priv = dev->dev_private;
 291         u32 pp_status, pp_control;
 292         if (!is_edp(intel_dp))
 293                 return;
 294         pp_status = I915_READ(PCH_PP_STATUS);
 295         pp_control = I915_READ(PCH_PP_CONTROL);
 296         if ((pp_status & PP_ON) == 0 && (pp_control & EDP_FORCE_VDD) == 0) {
 297                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
 298                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
 299                               pp_status,
 300                               I915_READ(PCH_PP_CONTROL));
 301         }
 302 }
 303
 304 static int
 305 intel_dp_aux_ch(struct intel_dp *intel_dp,
 306                 uint8_t *send, int send_bytes,
 307                 uint8_t *recv, int recv_size)
 308 {
 309         uint32_t output_reg = intel_dp->output_reg;
 310         struct drm_device *dev = intel_dp->base.base.dev;
 311         struct drm_i915_private *dev_priv = dev->dev_private;
 312         uint32_t ch_ctl = output_reg + 0x10;
 313         uint32_t ch_data = ch_ctl + 4;
 314         int i;
 315         int recv_bytes;
 316         uint32_t status;
 317         uint32_t aux_clock_divider;
 318         int try, precharge;
 319
 320         intel_dp_check_edp(intel_dp);
 321         /* The clock divider is based off the hrawclk,
 322          * and would like to run at 2MHz. So, take the
 323          * hrawclk value and divide by 2 and use that
 324          *
 325          * Note that PCH attached eDP panels should use a 125MHz input
 326          * clock divider.
 327          */
 328         if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) {
 329                 if (IS_GEN6(dev))
 330                         aux_clock_divider = 200; /* SNB eDP input clock at 400Mhz */
 331                 else
 332                         aux_clock_divider = 225; /* eDP input clock at 450Mhz */
 333         } else if (HAS_PCH_SPLIT(dev))
 334                 aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */
 335         else
 336                 aux_clock_divider = intel_hrawclk(dev) / 2;
 337
 338         if (IS_GEN6(dev))
 339                 precharge = 3;
 340         else
 341                 precharge = 5;
 342
 343         /* Try to wait for any previous AUX channel activity */
 344         for (try = 0; try < 3; try++) {
 345                 status = I915_READ(ch_ctl);
 346                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 347                         break;
 348                 msleep(1);
 349         }
 350
 351         if (try == 3) {
 352                 WARN(1, "dp_aux_ch not started status 0x%08x\n",
 353                      I915_READ(ch_ctl));
 354                 return -EBUSY;
 355         }
 356
 357         /* Must try at least 3 times according to DP spec */
 358         for (try = 0; try < 5; try++) {
 359                 /* Load the send data into the aux channel data registers */
 360                 for (i = 0; i < send_bytes; i += 4)
 361                         I915_WRITE(ch_data + i,
 362                                    pack_aux(send + i, send_bytes - i));
 363
 364                 /* Send the command and wait for it to complete */
 365                 I915_WRITE(ch_ctl,
 366                            DP_AUX_CH_CTL_SEND_BUSY |
 367                            DP_AUX_CH_CTL_TIME_OUT_400us |
 368                            (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 369                            (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 370                            (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
 371                            DP_AUX_CH_CTL_DONE |
 372                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
 373                            DP_AUX_CH_CTL_RECEIVE_ERROR);
 374                 for (;;) {
 375                         status = I915_READ(ch_ctl);
 376                         if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 377                                 break;
 378                         udelay(100);
 379                 }
 380
 381                 /* Clear done status and any errors */
 382                 I915_WRITE(ch_ctl,
 383                            status |
 384                            DP_AUX_CH_CTL_DONE |
 385                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
 386                            DP_AUX_CH_CTL_RECEIVE_ERROR);
 387                 if (status & DP_AUX_CH_CTL_DONE)
 388                         break;
 389         }
 390
 391         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
 392                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
 393                 return -EBUSY;
 394         }
 395
 396         /* Check for timeout or receive error.
 397          * Timeouts occur when the sink is not connected
 398          */
 399         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 400                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
 401                 return -EIO;
 402         }
 403
 404         /* Timeouts occur when the device isn't connected, so they're
 405          * "normal" -- don't fill the kernel log with these */
 406         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
 407                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
 408                 return -ETIMEDOUT;
 409         }
 410
 411         /* Unload any bytes sent back from the other side */
 412         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
 413                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
 414         if (recv_bytes > recv_size)
 415                 recv_bytes = recv_size;
 416
 417         for (i = 0; i < recv_bytes; i += 4)
 418                 unpack_aux(I915_READ(ch_data + i),
 419                            recv + i, recv_bytes - i);
 420
 421         return recv_bytes;
 422 }
 423
 424 /* Write data to the aux channel in native mode */
 425 static int
 426 intel_dp_aux_native_write(struct intel_dp *intel_dp,
 427                           uint16_t address, uint8_t *send, int send_bytes)
 428 {
 429         int ret;
 430         uint8_t msg[20];
 431         int msg_bytes;
 432         uint8_t ack;
 433
 434         intel_dp_check_edp(intel_dp);
 435         if (send_bytes > 16)
 436                 return -1;
 437         msg[0] = AUX_NATIVE_WRITE << 4;
 438         msg[1] = address >> 8;
 439         msg[2] = address & 0xff;
 440         msg[3] = send_bytes - 1;
 441         memcpy(&msg[4], send, send_bytes);
 442         msg_bytes = send_bytes + 4;
 443         for (;;) {
 444                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
 445                 if (ret < 0)
 446                         return ret;
 447                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
 448                         break;
 449                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 450                         udelay(100);
 451                 else
 452                         return -EIO;
 453         }
 454         return send_bytes;
 455 }
 456
 457 /* Write a single byte to the aux channel in native mode */
 458 static int
 459 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
 460                             uint16_t address, uint8_t byte)
 461 {
 462         return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
 463 }
 464
 465 /* read bytes from a native aux channel */
 466 static int
 467 intel_dp_aux_native_read(struct intel_dp *intel_dp,
 468                          uint16_t address, uint8_t *recv, int recv_bytes)
 469 {
 470         uint8_t msg[4];
 471         int msg_bytes;
 472         uint8_t reply[20];
 473         int reply_bytes;
 474         uint8_t ack;
 475         int ret;
 476
 477         intel_dp_check_edp(intel_dp);
 478         msg[0] = AUX_NATIVE_READ << 4;
 479         msg[1] = address >> 8;
 480         msg[2] = address & 0xff;
 481         msg[3] = recv_bytes - 1;
 482
 483         msg_bytes = 4;
 484         reply_bytes = recv_bytes + 1;
 485
 486         for (;;) {
 487                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
 488                                       reply, reply_bytes);
 489                 if (ret == 0)
 490                         return -EPROTO;
 491                 if (ret < 0)
 492                         return ret;
 493                 ack = reply[0];
 494                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
 495                         memcpy(recv, reply + 1, ret - 1);
 496                         return ret - 1;
 497                 }
 498                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 499                         udelay(100);
 500                 else
 501                         return -EIO;
 502         }
 503 }
 504
 505 static int
 506 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
 507                     uint8_t write_byte, uint8_t *read_byte)
 508 {
 509         struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
 510         struct intel_dp *intel_dp = container_of(adapter,
 511                                                 struct intel_dp,
 512                                                 adapter);
 513         uint16_t address = algo_data->address;
 514         uint8_t msg[5];
 515         uint8_t reply[2];
 516         unsigned retry;
 517         int msg_bytes;
 518         int reply_bytes;
 519         int ret;
 520
 521         intel_dp_check_edp(intel_dp);
 522         /* Set up the command byte */
 523         if (mode & MODE_I2C_READ)
 524                 msg[0] = AUX_I2C_READ << 4;
 525         else
 526                 msg[0] = AUX_I2C_WRITE << 4;
 527
 528         if (!(mode & MODE_I2C_STOP))
 529                 msg[0] |= AUX_I2C_MOT << 4;
 530
 531         msg[1] = address >> 8;
 532         msg[2] = address;
 533
 534         switch (mode) {
 535         case MODE_I2C_WRITE:
 536                 msg[3] = 0;
 537                 msg[4] = write_byte;
 538                 msg_bytes = 5;
 539                 reply_bytes = 1;
 540                 break;
 541         case MODE_I2C_READ:
 542                 msg[3] = 0;
 543                 msg_bytes = 4;
 544                 reply_bytes = 2;
 545                 break;
 546         default:
 547                 msg_bytes = 3;
 548                 reply_bytes = 1;
 549                 break;
 550         }
 551
 552         for (retry = 0; retry < 5; retry++) {
 553                 ret = intel_dp_aux_ch(intel_dp,
 554                                       msg, msg_bytes,
 555                                       reply, reply_bytes);
 556                 if (ret < 0) {
 557                         DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
 558                         return ret;
 559                 }
 560
 561                 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
 562                 case AUX_NATIVE_REPLY_ACK:
 563                         /* I2C-over-AUX Reply field is only valid
 564                          * when paired with AUX ACK.
 565                          */
 566                         break;
 567                 case AUX_NATIVE_REPLY_NACK:
 568                         DRM_DEBUG_KMS("aux_ch native nack\n");
 569                         return -EREMOTEIO;
 570                 case AUX_NATIVE_REPLY_DEFER:
 571                         udelay(100);
 572                         continue;
 573                 default:
 574                         DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
 575                                   reply[0]);
 576                         return -EREMOTEIO;
 577                 }
 578
 579                 switch (reply[0] & AUX_I2C_REPLY_MASK) {
 580                 case AUX_I2C_REPLY_ACK:
 581                         if (mode == MODE_I2C_READ) {
 582                                 *read_byte = reply[1];
 583                         }
 584                         return reply_bytes - 1;
 585                 case AUX_I2C_REPLY_NACK:
 586                         DRM_DEBUG_KMS("aux_i2c nack\n");
 587                         return -EREMOTEIO;
 588                 case AUX_I2C_REPLY_DEFER:
 589                         DRM_DEBUG_KMS("aux_i2c defer\n");
 590                         udelay(100);
 591                         break;
 592                 default:
 593                         DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
 594                         return -EREMOTEIO;
 595                 }
 596         }
 597
 598         DRM_ERROR("too many retries, giving up\n");
 599         return -EREMOTEIO;
 600 }
 601
 602 static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
 603 static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp);
 604
 605 static int
 606 intel_dp_i2c_init(struct intel_dp *intel_dp,
 607                   struct intel_connector *intel_connector, const char *name)
 608 {
 609         int     ret;
 610
 611         DRM_DEBUG_KMS("i2c_init %s\n", name);
 612         intel_dp->algo.running = false;
 613         intel_dp->algo.address = 0;
 614         intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
 615
 616         memset(&intel_dp->adapter, '\0', sizeof (intel_dp->adapter));
 617         intel_dp->adapter.owner = THIS_MODULE;
 618         intel_dp->adapter.class = I2C_CLASS_DDC;
 619         strncpy (intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
 620         intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
 621         intel_dp->adapter.algo_data = &intel_dp->algo;
 622         intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
 623
 624         ironlake_edp_panel_vdd_on(intel_dp);
 625         ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
 626         ironlake_edp_panel_vdd_off(intel_dp);
 627         return ret;
 628 }
 629
 630 static bool
 631 intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
 632                     struct drm_display_mode *adjusted_mode)
 633 {
 634         struct drm_device *dev = encoder->dev;
 635         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 636         int lane_count, clock;
 637         int max_lane_count = intel_dp_max_lane_count(intel_dp);
 638         int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
 639         static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
 640
 641         if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
 642                 intel_fixed_panel_mode(intel_dp->panel_fixed_mode, adjusted_mode);
 643                 intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
 644                                         mode, adjusted_mode);
 645                 /*
 646                  * the mode->clock is used to calculate the Data&Link M/N
 647                  * of the pipe. For the eDP the fixed clock should be used.
 648                  */
 649                 mode->clock = intel_dp->panel_fixed_mode->clock;
 650         }
 651
 652         for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
 653                 for (clock = 0; clock <= max_clock; clock++) {
 654                         int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
 655
 656                         if (intel_dp_link_required(encoder->dev, intel_dp, mode->clock)
 657                                         <= link_avail) {
 658                                 intel_dp->link_bw = bws[clock];
 659                                 intel_dp->lane_count = lane_count;
 660                                 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
 661                                 DRM_DEBUG_KMS("Display port link bw %02x lane "
 662                                                 "count %d clock %d\n",
 663                                        intel_dp->link_bw, intel_dp->lane_count,
 664                                        adjusted_mode->clock);
 665                                 return true;
 666                         }
 667                 }
 668         }
 669
 670         if (is_edp(intel_dp)) {
 671                 /* okay we failed just pick the highest */
 672                 intel_dp->lane_count = max_lane_count;
 673                 intel_dp->link_bw = bws[max_clock];
 674                 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
 675                 DRM_DEBUG_KMS("Force picking display port link bw %02x lane "
 676                               "count %d clock %d\n",
 677                               intel_dp->link_bw, intel_dp->lane_count,
 678                               adjusted_mode->clock);
 679
 680                 return true;
 681         }
 682
 683         return false;
 684 }
 685
 686 struct intel_dp_m_n {
 687         uint32_t        tu;
 688         uint32_t        gmch_m;
 689         uint32_t        gmch_n;
 690         uint32_t        link_m;
 691         uint32_t        link_n;
 692 };
 693
 694 static void
 695 intel_reduce_ratio(uint32_t *num, uint32_t *den)
 696 {
 697         while (*num > 0xffffff || *den > 0xffffff) {
 698                 *num >>= 1;
 699                 *den >>= 1;
 700         }
 701 }
 702
 703 static void
 704 intel_dp_compute_m_n(int bpp,
 705                      int nlanes,
 706                      int pixel_clock,
 707                      int link_clock,
 708                      struct intel_dp_m_n *m_n)
 709 {
 710         m_n->tu = 64;
 711         m_n->gmch_m = (pixel_clock * bpp) >> 3;
 712         m_n->gmch_n = link_clock * nlanes;
 713         intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
 714         m_n->link_m = pixel_clock;
 715         m_n->link_n = link_clock;
 716         intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
 717 }
 718
 719 void
 720 intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
 721                  struct drm_display_mode *adjusted_mode)
 722 {
 723         struct drm_device *dev = crtc->dev;
 724         struct drm_mode_config *mode_config = &dev->mode_config;
 725         struct drm_encoder *encoder;
 726         struct drm_i915_private *dev_priv = dev->dev_private;
 727         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 728         int lane_count = 4;
 729         struct intel_dp_m_n m_n;
 730         int pipe = intel_crtc->pipe;
 731
 732         /*
 733          * Find the lane count in the intel_encoder private
 734          */
 735         list_for_each_entry(encoder, &mode_config->encoder_list, head) {
 736                 struct intel_dp *intel_dp;
 737
 738                 if (encoder->crtc != crtc)
 739                         continue;
 740
 741                 intel_dp = enc_to_intel_dp(encoder);
 742                 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) {
 743                         lane_count = intel_dp->lane_count;
 744                         break;
 745                 } else if (is_edp(intel_dp)) {
 746                         lane_count = dev_priv->edp.lanes;
 747                         break;
 748                 }
 749         }
 750
 751         /*
 752          * Compute the GMCH and Link ratios. The '3' here is
 753          * the number of bytes_per_pixel post-LUT, which we always
 754          * set up for 8-bits of R/G/B, or 3 bytes total.
 755          */
 756         intel_dp_compute_m_n(intel_crtc->bpp, lane_count,
 757                              mode->clock, adjusted_mode->clock, &m_n);
 758
 759         if (HAS_PCH_SPLIT(dev)) {
 760                 I915_WRITE(TRANSDATA_M1(pipe),
 761                            ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
 762                            m_n.gmch_m);
 763                 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
 764                 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
 765                 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
 766         } else {
 767                 I915_WRITE(PIPE_GMCH_DATA_M(pipe),
 768                            ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
 769                            m_n.gmch_m);
 770                 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
 771                 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
 772                 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
 773         }
 774 }
 775
 776 static void ironlake_edp_pll_on(struct drm_encoder *encoder);
 777 static void ironlake_edp_pll_off(struct drm_encoder *encoder);
 778
 779 static void
 780 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
 781                   struct drm_display_mode *adjusted_mode)
 782 {
 783         struct drm_device *dev = encoder->dev;
 784         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 785         struct drm_crtc *crtc = intel_dp->base.base.crtc;
 786         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 787
 788         /* Turn on the eDP PLL if needed */
 789         if (is_edp(intel_dp)) {
 790                 if (!is_pch_edp(intel_dp))
 791                         ironlake_edp_pll_on(encoder);
 792                 else
 793                         ironlake_edp_pll_off(encoder);
 794         }
 795
 796         intel_dp->DP = DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 797         intel_dp->DP |= intel_dp->color_range;
 798
 799         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 800                 intel_dp->DP |= DP_SYNC_HS_HIGH;
 801         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 802                 intel_dp->DP |= DP_SYNC_VS_HIGH;
 803
 804         if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
 805                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
 806         else
 807                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
 808
 809         switch (intel_dp->lane_count) {
 810         case 1:
 811                 intel_dp->DP |= DP_PORT_WIDTH_1;
 812                 break;
 813         case 2:
 814                 intel_dp->DP |= DP_PORT_WIDTH_2;
 815                 break;
 816         case 4:
 817                 intel_dp->DP |= DP_PORT_WIDTH_4;
 818                 break;
 819         }
 820         if (intel_dp->has_audio)
 821                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
 822
 823         memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
 824         intel_dp->link_configuration[0] = intel_dp->link_bw;
 825         intel_dp->link_configuration[1] = intel_dp->lane_count;
 826         intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
 827
 828         /*
 829          * Check for DPCD version > 1.1 and enhanced framing support
 830          */
 831         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
 832             (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
 833                 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 834                 intel_dp->DP |= DP_ENHANCED_FRAMING;
 835         }
 836
 837         /* CPT DP's pipe select is decided in TRANS_DP_CTL */
 838         if (intel_crtc->pipe == 1 && !HAS_PCH_CPT(dev))
 839                 intel_dp->DP |= DP_PIPEB_SELECT;
 840
 841         if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) {
 842                 /* don't miss out required setting for eDP */
 843                 intel_dp->DP |= DP_PLL_ENABLE;
 844                 if (adjusted_mode->clock < 200000)
 845                         intel_dp->DP |= DP_PLL_FREQ_160MHZ;
 846                 else
 847                         intel_dp->DP |= DP_PLL_FREQ_270MHZ;
 848         }
 849 }
 850
 851 static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
 852 {
 853         struct drm_device *dev = intel_dp->base.base.dev;
 854         struct drm_i915_private *dev_priv = dev->dev_private;
 855         u32 pp, pp_status;
 856
 857         if (!is_edp(intel_dp))
 858                 return;
 859         DRM_DEBUG_KMS("Turn eDP VDD on\n");
 860         /*
 861          * If the panel wasn't on, make sure there's not a currently
 862          * active PP sequence before enabling AUX VDD.
 863          */
 864         pp_status = I915_READ(PCH_PP_STATUS);
 865
 866         pp = I915_READ(PCH_PP_CONTROL);
 867         pp &= ~PANEL_UNLOCK_MASK;
 868         pp |= PANEL_UNLOCK_REGS;
 869         pp |= EDP_FORCE_VDD;
 870         I915_WRITE(PCH_PP_CONTROL, pp);
 871         POSTING_READ(PCH_PP_CONTROL);
 872         DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
 873                       I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
 874         if (!(pp_status & PP_ON)) {
 875                 msleep(intel_dp->panel_power_up_delay);
 876                 DRM_DEBUG_KMS("eDP VDD was not on\n");
 877         }
 878 }
 879
 880 static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp)
 881 {
 882         struct drm_device *dev = intel_dp->base.base.dev;
 883         struct drm_i915_private *dev_priv = dev->dev_private;
 884         u32 pp;
 885
 886         if (!is_edp(intel_dp))
 887                 return;
 888         DRM_DEBUG_KMS("Turn eDP VDD off\n");
 889         pp = I915_READ(PCH_PP_CONTROL);
 890         pp &= ~PANEL_UNLOCK_MASK;
 891         pp |= PANEL_UNLOCK_REGS;
 892         pp &= ~EDP_FORCE_VDD;
 893         I915_WRITE(PCH_PP_CONTROL, pp);
 894         POSTING_READ(PCH_PP_CONTROL);
 895
 896         /* Make sure sequencer is idle before allowing subsequent activity */
 897         DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
 898                       I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
 899         msleep(intel_dp->panel_power_cycle_delay);
 900 }
 901
 902 /* Returns true if the panel was already on when called */
 903 static bool ironlake_edp_panel_on (struct intel_dp *intel_dp)
 904 {
 905         struct drm_device *dev = intel_dp->base.base.dev;
 906         struct drm_i915_private *dev_priv = dev->dev_private;
 907         u32 pp, idle_on_mask = PP_ON | PP_SEQUENCE_STATE_ON_IDLE;
 908
 909         if (!is_edp(intel_dp))
 910                 return true;
 911         if (I915_READ(PCH_PP_STATUS) & PP_ON)
 912                 return true;
 913
 914         pp = I915_READ(PCH_PP_CONTROL);
 915         pp &= ~PANEL_UNLOCK_MASK;
 916         pp |= PANEL_UNLOCK_REGS;
 917
 918         /* ILK workaround: disable reset around power sequence */
 919         pp &= ~PANEL_POWER_RESET;
 920         I915_WRITE(PCH_PP_CONTROL, pp);
 921         POSTING_READ(PCH_PP_CONTROL);
 922
 923         pp |= POWER_TARGET_ON;
 924         I915_WRITE(PCH_PP_CONTROL, pp);
 925         POSTING_READ(PCH_PP_CONTROL);
 926
 927         if (wait_for((I915_READ(PCH_PP_STATUS) & idle_on_mask) == idle_on_mask,
 928                      5000))
 929                 DRM_ERROR("panel on wait timed out: 0x%08x\n",
 930                           I915_READ(PCH_PP_STATUS));
 931
 932         pp |= PANEL_POWER_RESET; /* restore panel reset bit */
 933         I915_WRITE(PCH_PP_CONTROL, pp);
 934         POSTING_READ(PCH_PP_CONTROL);
 935
 936         return false;
 937 }
 938
 939 static void ironlake_edp_panel_off(struct drm_encoder *encoder)
 940 {
 941         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 942         struct drm_device *dev = encoder->dev;
 943         struct drm_i915_private *dev_priv = dev->dev_private;
 944         u32 pp, idle_off_mask = PP_ON | PP_SEQUENCE_MASK |
 945                 PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK;
 946
 947         if (!is_edp(intel_dp))
 948                 return;
 949         pp = I915_READ(PCH_PP_CONTROL);
 950         pp &= ~PANEL_UNLOCK_MASK;
 951         pp |= PANEL_UNLOCK_REGS;
 952
 953         /* ILK workaround: disable reset around power sequence */
 954         pp &= ~PANEL_POWER_RESET;
 955         I915_WRITE(PCH_PP_CONTROL, pp);
 956         POSTING_READ(PCH_PP_CONTROL);
 957
 958         pp &= ~POWER_TARGET_ON;
 959         I915_WRITE(PCH_PP_CONTROL, pp);
 960         POSTING_READ(PCH_PP_CONTROL);
 961         msleep(intel_dp->panel_power_cycle_delay);
 962
 963         if (wait_for((I915_READ(PCH_PP_STATUS) & idle_off_mask) == 0, 5000))
 964                 DRM_ERROR("panel off wait timed out: 0x%08x\n",
 965                           I915_READ(PCH_PP_STATUS));
 966
 967         pp |= PANEL_POWER_RESET; /* restore panel reset bit */
 968         I915_WRITE(PCH_PP_CONTROL, pp);
 969         POSTING_READ(PCH_PP_CONTROL);
 970 }
 971
 972 static void ironlake_edp_backlight_on (struct intel_dp *intel_dp)
 973 {
 974         struct drm_device *dev = intel_dp->base.base.dev;
 975         struct drm_i915_private *dev_priv = dev->dev_private;
 976         u32 pp;
 977
 978         if (!is_edp(intel_dp))
 979                 return;
 980
 981         DRM_DEBUG_KMS("\n");
 982         /*
 983          * If we enable the backlight right away following a panel power
 984          * on, we may see slight flicker as the panel syncs with the eDP
 985          * link.  So delay a bit to make sure the image is solid before
 986          * allowing it to appear.
 987          */
 988         msleep(intel_dp->backlight_on_delay);
 989         pp = I915_READ(PCH_PP_CONTROL);
 990         pp &= ~PANEL_UNLOCK_MASK;
 991         pp |= PANEL_UNLOCK_REGS;
 992         pp |= EDP_BLC_ENABLE;
 993         I915_WRITE(PCH_PP_CONTROL, pp);
 994         POSTING_READ(PCH_PP_CONTROL);
 995 }
 996
 997 static void ironlake_edp_backlight_off (struct intel_dp *intel_dp)
 998 {
 999         struct drm_device *dev = intel_dp->base.base.dev;
1000         struct drm_i915_private *dev_priv = dev->dev_private;
1001         u32 pp;
1002
1003         if (!is_edp(intel_dp))
1004                 return;
1005
1006         DRM_DEBUG_KMS("\n");
1007         pp = I915_READ(PCH_PP_CONTROL);
1008         pp &= ~PANEL_UNLOCK_MASK;
1009         pp |= PANEL_UNLOCK_REGS;
1010         pp &= ~EDP_BLC_ENABLE;
1011         I915_WRITE(PCH_PP_CONTROL, pp);
1012         POSTING_READ(PCH_PP_CONTROL);
1013         msleep(intel_dp->backlight_off_delay);
1014 }
1015
1016 static void ironlake_edp_pll_on(struct drm_encoder *encoder)
1017 {
1018         struct drm_device *dev = encoder->dev;
1019         struct drm_i915_private *dev_priv = dev->dev_private;
1020         u32 dpa_ctl;
1021
1022         DRM_DEBUG_KMS("\n");
1023         dpa_ctl = I915_READ(DP_A);
1024         dpa_ctl |= DP_PLL_ENABLE;
1025         I915_WRITE(DP_A, dpa_ctl);
1026         POSTING_READ(DP_A);
1027         udelay(200);
1028 }
1029
1030 static void ironlake_edp_pll_off(struct drm_encoder *encoder)
1031 {
1032         struct drm_device *dev = encoder->dev;
1033         struct drm_i915_private *dev_priv = dev->dev_private;
1034         u32 dpa_ctl;
1035
1036         dpa_ctl = I915_READ(DP_A);
1037         dpa_ctl &= ~DP_PLL_ENABLE;
1038         I915_WRITE(DP_A, dpa_ctl);
1039         POSTING_READ(DP_A);
1040         udelay(200);
1041 }
1042
1043 /* If the sink supports it, try to set the power state appropriately */
1044 static void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1045 {
1046         int ret, i;
1047
1048         /* Should have a valid DPCD by this point */
1049         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1050                 return;
1051
1052         if (mode != DRM_MODE_DPMS_ON) {
1053                 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1054                                                   DP_SET_POWER_D3);
1055                 if (ret != 1)
1056                         DRM_DEBUG_DRIVER("failed to write sink power state\n");
1057         } else {
1058                 /*
1059                  * When turning on, we need to retry for 1ms to give the sink
1060                  * time to wake up.
1061                  */
1062                 for (i = 0; i < 3; i++) {
1063                         ret = intel_dp_aux_native_write_1(intel_dp,
1064                                                           DP_SET_POWER,
1065                                                           DP_SET_POWER_D0);
1066                         if (ret == 1)
1067                                 break;
1068                         msleep(1);
1069                 }
1070         }
1071 }
1072
1073 static void intel_dp_prepare(struct drm_encoder *encoder)
1074 {
1075         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1076
1077         /* Wake up the sink first */
1078         ironlake_edp_panel_vdd_on(intel_dp);
1079         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1080         ironlake_edp_panel_vdd_off(intel_dp);
1081
1082         /* Make sure the panel is off before trying to
1083          * change the mode
1084          */
1085         ironlake_edp_backlight_off(intel_dp);
1086         intel_dp_link_down(intel_dp);
1087         ironlake_edp_panel_off(encoder);
1088 }
1089
1090 static void intel_dp_commit(struct drm_encoder *encoder)
1091 {
1092         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1093
1094         ironlake_edp_panel_vdd_on(intel_dp);
1095         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1096         intel_dp_start_link_train(intel_dp);
1097         ironlake_edp_panel_on(intel_dp);
1098         ironlake_edp_panel_vdd_off(intel_dp);
1099         intel_dp_complete_link_train(intel_dp);
1100         ironlake_edp_backlight_on(intel_dp);
1101
1102         intel_dp->dpms_mode = DRM_MODE_DPMS_ON;
1103 }
1104
1105 static void
1106 intel_dp_dpms(struct drm_encoder *encoder, int mode)
1107 {
1108         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1109         struct drm_device *dev = encoder->dev;
1110         struct drm_i915_private *dev_priv = dev->dev_private;
1111         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1112
1113         if (mode != DRM_MODE_DPMS_ON) {
1114                 ironlake_edp_panel_vdd_on(intel_dp);
1115                 if (is_edp(intel_dp))
1116                         ironlake_edp_backlight_off(intel_dp);
1117                 intel_dp_sink_dpms(intel_dp, mode);
1118                 intel_dp_link_down(intel_dp);
1119                 ironlake_edp_panel_off(encoder);
1120                 if (is_edp(intel_dp) && !is_pch_edp(intel_dp))
1121                         ironlake_edp_pll_off(encoder);
1122                 ironlake_edp_panel_vdd_off(intel_dp);
1123         } else {
1124                 ironlake_edp_panel_vdd_on(intel_dp);
1125                 intel_dp_sink_dpms(intel_dp, mode);
1126                 if (!(dp_reg & DP_PORT_EN)) {
1127                         intel_dp_start_link_train(intel_dp);
1128                         ironlake_edp_panel_on(intel_dp);
1129                         ironlake_edp_panel_vdd_off(intel_dp);
1130                         intel_dp_complete_link_train(intel_dp);
1131                         ironlake_edp_backlight_on(intel_dp);
1132                 } else
1133                         ironlake_edp_panel_vdd_off(intel_dp);
1134         }
1135         intel_dp->dpms_mode = mode;
1136 }
1137
1138 /*
1139  * Native read with retry for link status and receiver capability reads for
1140  * cases where the sink may still be asleep.
1141  */
1142 static bool
1143 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1144                                uint8_t *recv, int recv_bytes)
1145 {
1146         int ret, i;
1147
1148         /*
1149          * Sinks are *supposed* to come up within 1ms from an off state,
1150          * but we're also supposed to retry 3 times per the spec.
1151          */
1152         for (i = 0; i < 3; i++) {
1153                 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1154                                                recv_bytes);
1155                 if (ret == recv_bytes)
1156                         return true;
1157                 msleep(1);
1158         }
1159
1160         return false;
1161 }
1162
1163 /*
1164  * Fetch AUX CH registers 0x202 - 0x207 which contain
1165  * link status information
1166  */
1167 static bool
1168 intel_dp_get_link_status(struct intel_dp *intel_dp)
1169 {
1170         return intel_dp_aux_native_read_retry(intel_dp,
1171                                               DP_LANE0_1_STATUS,
1172                                               intel_dp->link_status,
1173                                               DP_LINK_STATUS_SIZE);
1174 }
1175
1176 static uint8_t
1177 intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1178                      int r)
1179 {
1180         return link_status[r - DP_LANE0_1_STATUS];
1181 }
1182
1183 static uint8_t
1184 intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE],
1185                                  int lane)
1186 {
1187         int         i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
1188         int         s = ((lane & 1) ?
1189                          DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
1190                          DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
1191         uint8_t l = intel_dp_link_status(link_status, i);
1192
1193         return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
1194 }
1195
1196 static uint8_t
1197 intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE],
1198                                       int lane)
1199 {
1200         int         i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
1201         int         s = ((lane & 1) ?
1202                          DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
1203                          DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
1204         uint8_t l = intel_dp_link_status(link_status, i);
1205
1206         return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
1207 }
1208
1209
1210 #if 0
1211 static char     *voltage_names[] = {
1212         "0.4V", "0.6V", "0.8V", "1.2V"
1213 };
1214 static char     *pre_emph_names[] = {
1215         "0dB", "3.5dB", "6dB", "9.5dB"
1216 };
1217 static char     *link_train_names[] = {
1218         "pattern 1", "pattern 2", "idle", "off"
1219 };
1220 #endif
1221
1222 /*
1223  * These are source-specific values; current Intel hardware supports
1224  * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1225  */
1226 #define I830_DP_VOLTAGE_MAX         DP_TRAIN_VOLTAGE_SWING_800
1227
1228 static uint8_t
1229 intel_dp_pre_emphasis_max(uint8_t voltage_swing)
1230 {
1231         switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1232         case DP_TRAIN_VOLTAGE_SWING_400:
1233                 return DP_TRAIN_PRE_EMPHASIS_6;
1234         case DP_TRAIN_VOLTAGE_SWING_600:
1235                 return DP_TRAIN_PRE_EMPHASIS_6;
1236         case DP_TRAIN_VOLTAGE_SWING_800:
1237                 return DP_TRAIN_PRE_EMPHASIS_3_5;
1238         case DP_TRAIN_VOLTAGE_SWING_1200:
1239         default:
1240                 return DP_TRAIN_PRE_EMPHASIS_0;
1241         }
1242 }
1243
1244 static void
1245 intel_get_adjust_train(struct intel_dp *intel_dp)
1246 {
1247         uint8_t v = 0;
1248         uint8_t p = 0;
1249         int lane;
1250
1251         for (lane = 0; lane < intel_dp->lane_count; lane++) {
1252                 uint8_t this_v = intel_get_adjust_request_voltage(intel_dp->link_status, lane);
1253                 uint8_t this_p = intel_get_adjust_request_pre_emphasis(intel_dp->link_status, lane);
1254
1255                 if (this_v > v)
1256                         v = this_v;
1257                 if (this_p > p)
1258                         p = this_p;
1259         }
1260
1261         if (v >= I830_DP_VOLTAGE_MAX)
1262                 v = I830_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED;
1263
1264         if (p >= intel_dp_pre_emphasis_max(v))
1265                 p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1266
1267         for (lane = 0; lane < 4; lane++)
1268                 intel_dp->train_set[lane] = v | p;
1269 }
1270
1271 static uint32_t
1272 intel_dp_signal_levels(uint8_t train_set, int lane_count)
1273 {
1274         uint32_t        signal_levels = 0;
1275
1276         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1277         case DP_TRAIN_VOLTAGE_SWING_400:
1278         default:
1279                 signal_levels |= DP_VOLTAGE_0_4;
1280                 break;
1281         case DP_TRAIN_VOLTAGE_SWING_600:
1282                 signal_levels |= DP_VOLTAGE_0_6;
1283                 break;
1284         case DP_TRAIN_VOLTAGE_SWING_800:
1285                 signal_levels |= DP_VOLTAGE_0_8;
1286                 break;
1287         case DP_TRAIN_VOLTAGE_SWING_1200:
1288                 signal_levels |= DP_VOLTAGE_1_2;
1289                 break;
1290         }
1291         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1292         case DP_TRAIN_PRE_EMPHASIS_0:
1293         default:
1294                 signal_levels |= DP_PRE_EMPHASIS_0;
1295                 break;
1296         case DP_TRAIN_PRE_EMPHASIS_3_5:
1297                 signal_levels |= DP_PRE_EMPHASIS_3_5;
1298                 break;
1299         case DP_TRAIN_PRE_EMPHASIS_6:
1300                 signal_levels |= DP_PRE_EMPHASIS_6;
1301                 break;
1302         case DP_TRAIN_PRE_EMPHASIS_9_5:
1303                 signal_levels |= DP_PRE_EMPHASIS_9_5;
1304                 break;
1305         }
1306         return signal_levels;
1307 }
1308
1309 /* Gen6's DP voltage swing and pre-emphasis control */
1310 static uint32_t
1311 intel_gen6_edp_signal_levels(uint8_t train_set)
1312 {
1313         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1314                                          DP_TRAIN_PRE_EMPHASIS_MASK);
1315         switch (signal_levels) {
1316         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1317         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1318                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1319         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1320                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
1321         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1322         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1323                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
1324         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1325         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1326                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
1327         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1328         case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1329                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
1330         default:
1331                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1332                               "0x%x\n", signal_levels);
1333                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1334         }
1335 }
1336
1337 static uint8_t
1338 intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1339                       int lane)
1340 {
1341         int i = DP_LANE0_1_STATUS + (lane >> 1);
1342         int s = (lane & 1) * 4;
1343         uint8_t l = intel_dp_link_status(link_status, i);
1344
1345         return (l >> s) & 0xf;
1346 }
1347
1348 /* Check for clock recovery is done on all channels */
1349 static bool
1350 intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
1351 {
1352         int lane;
1353         uint8_t lane_status;
1354
1355         for (lane = 0; lane < lane_count; lane++) {
1356                 lane_status = intel_get_lane_status(link_status, lane);
1357                 if ((lane_status & DP_LANE_CR_DONE) == 0)
1358                         return false;
1359         }
1360         return true;
1361 }
1362
1363 /* Check to see if channel eq is done on all channels */
1364 #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1365                          DP_LANE_CHANNEL_EQ_DONE|\
1366                          DP_LANE_SYMBOL_LOCKED)
1367 static bool
1368 intel_channel_eq_ok(struct intel_dp *intel_dp)
1369 {
1370         uint8_t lane_align;
1371         uint8_t lane_status;
1372         int lane;
1373
1374         lane_align = intel_dp_link_status(intel_dp->link_status,
1375                                           DP_LANE_ALIGN_STATUS_UPDATED);
1376         if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
1377                 return false;
1378         for (lane = 0; lane < intel_dp->lane_count; lane++) {
1379                 lane_status = intel_get_lane_status(intel_dp->link_status, lane);
1380                 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
1381                         return false;
1382         }
1383         return true;
1384 }
1385
1386 static bool
1387 intel_dp_set_link_train(struct intel_dp *intel_dp,
1388                         uint32_t dp_reg_value,
1389                         uint8_t dp_train_pat)
1390 {
1391         struct drm_device *dev = intel_dp->base.base.dev;
1392         struct drm_i915_private *dev_priv = dev->dev_private;
1393         int ret;
1394
1395         I915_WRITE(intel_dp->output_reg, dp_reg_value);
1396         POSTING_READ(intel_dp->output_reg);
1397
1398         intel_dp_aux_native_write_1(intel_dp,
1399                                     DP_TRAINING_PATTERN_SET,
1400                                     dp_train_pat);
1401
1402         ret = intel_dp_aux_native_write(intel_dp,
1403                                         DP_TRAINING_LANE0_SET,
1404                                         intel_dp->train_set, 4);
1405         if (ret != 4)
1406                 return false;
1407
1408         return true;
1409 }
1410
1411 /* Enable corresponding port and start training pattern 1 */
1412 static void
1413 intel_dp_start_link_train(struct intel_dp *intel_dp)
1414 {
1415         struct drm_device *dev = intel_dp->base.base.dev;
1416         struct drm_i915_private *dev_priv = dev->dev_private;
1417         struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
1418         int i;
1419         uint8_t voltage;
1420         bool clock_recovery = false;
1421         int tries;
1422         u32 reg;
1423         uint32_t DP = intel_dp->DP;
1424
1425         /*
1426          * On CPT we have to enable the port in training pattern 1, which
1427          * will happen below in intel_dp_set_link_train.  Otherwise, enable
1428          * the port and wait for it to become active.
1429          */
1430         if (!HAS_PCH_CPT(dev)) {
1431                 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
1432                 POSTING_READ(intel_dp->output_reg);
1433                 intel_wait_for_vblank(dev, intel_crtc->pipe);
1434         }
1435
1436         /* Write the link configuration data */
1437         intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1438                                   intel_dp->link_configuration,
1439                                   DP_LINK_CONFIGURATION_SIZE);
1440
1441         DP |= DP_PORT_EN;
1442         if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1443                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1444         else
1445                 DP &= ~DP_LINK_TRAIN_MASK;
1446         memset(intel_dp->train_set, 0, 4);
1447         voltage = 0xff;
1448         tries = 0;
1449         clock_recovery = false;
1450         for (;;) {
1451                 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1452                 uint32_t    signal_levels;
1453                 if (IS_GEN6(dev) && is_edp(intel_dp)) {
1454                         signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1455                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1456                 } else {
1457                         signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count);
1458                         DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1459                 }
1460
1461                 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1462                         reg = DP | DP_LINK_TRAIN_PAT_1_CPT;
1463                 else
1464                         reg = DP | DP_LINK_TRAIN_PAT_1;
1465
1466                 if (!intel_dp_set_link_train(intel_dp, reg,
1467                                              DP_TRAINING_PATTERN_1 |
1468                                              DP_LINK_SCRAMBLING_DISABLE))
1469                         break;
1470                 /* Set training pattern 1 */
1471
1472                 udelay(100);
1473                 if (!intel_dp_get_link_status(intel_dp))
1474                         break;
1475
1476                 if (intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {
1477                         clock_recovery = true;
1478                         break;
1479                 }
1480
1481                 /* Check to see if we've tried the max voltage */
1482                 for (i = 0; i < intel_dp->lane_count; i++)
1483                         if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1484                                 break;
1485                 if (i == intel_dp->lane_count)
1486                         break;
1487
1488                 /* Check to see if we've tried the same voltage 5 times */
1489                 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1490                         ++tries;
1491                         if (tries == 5)
1492                                 break;
1493                 } else
1494                         tries = 0;
1495                 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1496
1497                 /* Compute new intel_dp->train_set as requested by target */
1498                 intel_get_adjust_train(intel_dp);
1499         }
1500
1501         intel_dp->DP = DP;
1502 }
1503
1504 static void
1505 intel_dp_complete_link_train(struct intel_dp *intel_dp)
1506 {
1507         struct drm_device *dev = intel_dp->base.base.dev;
1508         struct drm_i915_private *dev_priv = dev->dev_private;
1509         bool channel_eq = false;
1510         int tries, cr_tries;
1511         u32 reg;
1512         uint32_t DP = intel_dp->DP;
1513
1514         /* channel equalization */
1515         tries = 0;
1516         cr_tries = 0;
1517         channel_eq = false;
1518         for (;;) {
1519                 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1520                 uint32_t    signal_levels;
1521
1522                 if (cr_tries > 5) {
1523                         DRM_ERROR("failed to train DP, aborting\n");
1524                         intel_dp_link_down(intel_dp);
1525                         break;
1526                 }
1527
1528                 if (IS_GEN6(dev) && is_edp(intel_dp)) {
1529                         signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1530                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1531                 } else {
1532                         signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count);
1533                         DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1534                 }
1535
1536                 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1537                         reg = DP | DP_LINK_TRAIN_PAT_2_CPT;
1538                 else
1539                         reg = DP | DP_LINK_TRAIN_PAT_2;
1540
1541                 /* channel eq pattern */
1542                 if (!intel_dp_set_link_train(intel_dp, reg,
1543                                              DP_TRAINING_PATTERN_2 |
1544                                              DP_LINK_SCRAMBLING_DISABLE))
1545                         break;
1546
1547                 udelay(400);
1548                 if (!intel_dp_get_link_status(intel_dp))
1549                         break;
1550
1551                 /* Make sure clock is still ok */
1552                 if (!intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {
1553                         intel_dp_start_link_train(intel_dp);
1554                         cr_tries++;
1555                         continue;
1556                 }
1557
1558                 if (intel_channel_eq_ok(intel_dp)) {
1559                         channel_eq = true;
1560                         break;
1561                 }
1562
1563                 /* Try 5 times, then try clock recovery if that fails */
1564                 if (tries > 5) {
1565                         intel_dp_link_down(intel_dp);
1566                         intel_dp_start_link_train(intel_dp);
1567                         tries = 0;
1568                         cr_tries++;
1569                         continue;
1570                 }
1571
1572                 /* Compute new intel_dp->train_set as requested by target */
1573                 intel_get_adjust_train(intel_dp);
1574                 ++tries;
1575         }
1576
1577         if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1578                 reg = DP | DP_LINK_TRAIN_OFF_CPT;
1579         else
1580                 reg = DP | DP_LINK_TRAIN_OFF;
1581
1582         I915_WRITE(intel_dp->output_reg, reg);
1583         POSTING_READ(intel_dp->output_reg);
1584         intel_dp_aux_native_write_1(intel_dp,
1585                                     DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
1586 }
1587
1588 static void
1589 intel_dp_link_down(struct intel_dp *intel_dp)
1590 {
1591         struct drm_device *dev = intel_dp->base.base.dev;
1592         struct drm_i915_private *dev_priv = dev->dev_private;
1593         uint32_t DP = intel_dp->DP;
1594
1595         if ((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)
1596                 return;
1597
1598         DRM_DEBUG_KMS("\n");
1599
1600         if (is_edp(intel_dp)) {
1601                 DP &= ~DP_PLL_ENABLE;
1602                 I915_WRITE(intel_dp->output_reg, DP);
1603                 POSTING_READ(intel_dp->output_reg);
1604                 udelay(100);
1605         }
1606
1607         if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) {
1608                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1609                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
1610         } else {
1611                 DP &= ~DP_LINK_TRAIN_MASK;
1612                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
1613         }
1614         POSTING_READ(intel_dp->output_reg);
1615
1616         msleep(17);
1617
1618         if (is_edp(intel_dp))
1619                 DP |= DP_LINK_TRAIN_OFF;
1620
1621         if (!HAS_PCH_CPT(dev) &&
1622             I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
1623                 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1624
1625                 /* Hardware workaround: leaving our transcoder select
1626                  * set to transcoder B while it's off will prevent the
1627                  * corresponding HDMI output on transcoder A.
1628                  *
1629                  * Combine this with another hardware workaround:
1630                  * transcoder select bit can only be cleared while the
1631                  * port is enabled.
1632                  */
1633                 DP &= ~DP_PIPEB_SELECT;
1634                 I915_WRITE(intel_dp->output_reg, DP);
1635
1636                 /* Changes to enable or select take place the vblank
1637                  * after being written.
1638                  */
1639                 if (crtc == NULL) {
1640                         /* We can arrive here never having been attached
1641                          * to a CRTC, for instance, due to inheriting
1642                          * random state from the BIOS.
1643                          *
1644                          * If the pipe is not running, play safe and
1645                          * wait for the clocks to stabilise before
1646                          * continuing.
1647                          */
1648                         POSTING_READ(intel_dp->output_reg);
1649                         msleep(50);
1650                 } else
1651                         intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
1652         }
1653
1654         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
1655         POSTING_READ(intel_dp->output_reg);
1656         msleep(intel_dp->panel_power_down_delay);
1657 }
1658
1659 static bool
1660 intel_dp_get_dpcd(struct intel_dp *intel_dp)
1661 {
1662         if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
1663                                            sizeof (intel_dp->dpcd)) &&
1664             (intel_dp->dpcd[DP_DPCD_REV] != 0)) {
1665                 return true;
1666         }
1667
1668         return false;
1669 }
1670
1671 /*
1672  * According to DP spec
1673  * 5.1.2:
1674  *  1. Read DPCD
1675  *  2. Configure link according to Receiver Capabilities
1676  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
1677  *  4. Check link status on receipt of hot-plug interrupt
1678  */
1679
1680 static void
1681 intel_dp_check_link_status(struct intel_dp *intel_dp)
1682 {
1683         if (intel_dp->dpms_mode != DRM_MODE_DPMS_ON)
1684                 return;
1685
1686         if (!intel_dp->base.base.crtc)
1687                 return;
1688
1689         /* Try to read receiver status if the link appears to be up */
1690         if (!intel_dp_get_link_status(intel_dp)) {
1691                 intel_dp_link_down(intel_dp);
1692                 return;
1693         }
1694
1695         /* Now read the DPCD to see if it's actually running */
1696         if (!intel_dp_get_dpcd(intel_dp)) {
1697                 intel_dp_link_down(intel_dp);
1698                 return;
1699         }
1700
1701         if (!intel_channel_eq_ok(intel_dp)) {
1702                 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
1703                               drm_get_encoder_name(&intel_dp->base.base));
1704                 intel_dp_start_link_train(intel_dp);
1705                 intel_dp_complete_link_train(intel_dp);
1706         }
1707 }
1708
1709 static enum drm_connector_status
1710 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
1711 {
1712         if (intel_dp_get_dpcd(intel_dp))
1713                 return connector_status_connected;
1714         return connector_status_disconnected;
1715 }
1716
1717 static enum drm_connector_status
1718 ironlake_dp_detect(struct intel_dp *intel_dp)
1719 {
1720         enum drm_connector_status status;
1721
1722         /* Can't disconnect eDP, but you can close the lid... */
1723         if (is_edp(intel_dp)) {
1724                 status = intel_panel_detect(intel_dp->base.base.dev);
1725                 if (status == connector_status_unknown)
1726                         status = connector_status_connected;
1727                 return status;
1728         }
1729
1730         return intel_dp_detect_dpcd(intel_dp);
1731 }
1732
1733 static enum drm_connector_status
1734 g4x_dp_detect(struct intel_dp *intel_dp)
1735 {
1736         struct drm_device *dev = intel_dp->base.base.dev;
1737         struct drm_i915_private *dev_priv = dev->dev_private;
1738         uint32_t temp, bit;
1739
1740         switch (intel_dp->output_reg) {
1741         case DP_B:
1742                 bit = DPB_HOTPLUG_INT_STATUS;
1743                 break;
1744         case DP_C:
1745                 bit = DPC_HOTPLUG_INT_STATUS;
1746                 break;
1747         case DP_D:
1748                 bit = DPD_HOTPLUG_INT_STATUS;
1749                 break;
1750         default:
1751                 return connector_status_unknown;
1752         }
1753
1754         temp = I915_READ(PORT_HOTPLUG_STAT);
1755
1756         if ((temp & bit) == 0)
1757                 return connector_status_disconnected;
1758
1759         return intel_dp_detect_dpcd(intel_dp);
1760 }
1761
1762 static struct edid *
1763 intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
1764 {
1765         struct intel_dp *intel_dp = intel_attached_dp(connector);
1766         struct edid     *edid;
1767
1768         ironlake_edp_panel_vdd_on(intel_dp);
1769         edid = drm_get_edid(connector, adapter);
1770         ironlake_edp_panel_vdd_off(intel_dp);
1771         return edid;
1772 }
1773
1774 static int
1775 intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
1776 {
1777         struct intel_dp *intel_dp = intel_attached_dp(connector);
1778         int     ret;
1779
1780         ironlake_edp_panel_vdd_on(intel_dp);
1781         ret = intel_ddc_get_modes(connector, adapter);
1782         ironlake_edp_panel_vdd_off(intel_dp);
1783         return ret;
1784 }
1785
1786
1787 /**
1788  * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
1789  *
1790  * \return true if DP port is connected.
1791  * \return false if DP port is disconnected.
1792  */
1793 static enum drm_connector_status
1794 intel_dp_detect(struct drm_connector *connector, bool force)
1795 {
1796         struct intel_dp *intel_dp = intel_attached_dp(connector);
1797         struct drm_device *dev = intel_dp->base.base.dev;
1798         enum drm_connector_status status;
1799         struct edid *edid = NULL;
1800
1801         intel_dp->has_audio = false;
1802
1803         if (HAS_PCH_SPLIT(dev))
1804                 status = ironlake_dp_detect(intel_dp);
1805         else
1806                 status = g4x_dp_detect(intel_dp);
1807
1808         DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n",
1809                       intel_dp->dpcd[0], intel_dp->dpcd[1], intel_dp->dpcd[2],
1810                       intel_dp->dpcd[3], intel_dp->dpcd[4], intel_dp->dpcd[5],
1811                       intel_dp->dpcd[6], intel_dp->dpcd[7]);
1812
1813         if (status != connector_status_connected)
1814                 return status;
1815
1816         if (intel_dp->force_audio) {
1817                 intel_dp->has_audio = intel_dp->force_audio > 0;
1818         } else {
1819                 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
1820                 if (edid) {
1821                         intel_dp->has_audio = drm_detect_monitor_audio(edid);
1822                         connector->display_info.raw_edid = NULL;
1823                         kfree(edid);
1824                 }
1825         }
1826
1827         return connector_status_connected;
1828 }
1829
1830 static int intel_dp_get_modes(struct drm_connector *connector)
1831 {
1832         struct intel_dp *intel_dp = intel_attached_dp(connector);
1833         struct drm_device *dev = intel_dp->base.base.dev;
1834         struct drm_i915_private *dev_priv = dev->dev_private;
1835         int ret;
1836
1837         /* We should parse the EDID data and find out if it has an audio sink
1838          */
1839
1840         ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
1841         if (ret) {
1842                 if (is_edp(intel_dp) && !intel_dp->panel_fixed_mode) {
1843                         struct drm_display_mode *newmode;
1844                         list_for_each_entry(newmode, &connector->probed_modes,
1845                                             head) {
1846                                 if ((newmode->type & DRM_MODE_TYPE_PREFERRED)) {
1847                                         intel_dp->panel_fixed_mode =
1848                                                 drm_mode_duplicate(dev, newmode);
1849                                         break;
1850                                 }
1851                         }
1852                 }
1853                 return ret;
1854         }
1855
1856         /* if eDP has no EDID, try to use fixed panel mode from VBT */
1857         if (is_edp(intel_dp)) {
1858                 /* initialize panel mode from VBT if available for eDP */
1859                 if (intel_dp->panel_fixed_mode == NULL && dev_priv->lfp_lvds_vbt_mode != NULL) {
1860                         intel_dp->panel_fixed_mode =
1861                                 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
1862                         if (intel_dp->panel_fixed_mode) {
1863                                 intel_dp->panel_fixed_mode->type |=
1864                                         DRM_MODE_TYPE_PREFERRED;
1865                         }
1866                 }
1867                 if (intel_dp->panel_fixed_mode) {
1868                         struct drm_display_mode *mode;
1869                         mode = drm_mode_duplicate(dev, intel_dp->panel_fixed_mode);
1870                         drm_mode_probed_add(connector, mode);
1871                         return 1;
1872                 }
1873         }
1874         return 0;
1875 }
1876
1877 static bool
1878 intel_dp_detect_audio(struct drm_connector *connector)
1879 {
1880         struct intel_dp *intel_dp = intel_attached_dp(connector);
1881         struct edid *edid;
1882         bool has_audio = false;
1883
1884         edid = intel_dp_get_edid(connector, &intel_dp->adapter);
1885         if (edid) {
1886                 has_audio = drm_detect_monitor_audio(edid);
1887
1888                 connector->display_info.raw_edid = NULL;
1889                 kfree(edid);
1890         }
1891
1892         return has_audio;
1893 }
1894
1895 static int
1896 intel_dp_set_property(struct drm_connector *connector,
1897                       struct drm_property *property,
1898                       uint64_t val)
1899 {
1900         struct drm_i915_private *dev_priv = connector->dev->dev_private;
1901         struct intel_dp *intel_dp = intel_attached_dp(connector);
1902         int ret;
1903
1904         ret = drm_connector_property_set_value(connector, property, val);
1905         if (ret)
1906                 return ret;
1907
1908         if (property == dev_priv->force_audio_property) {
1909                 int i = val;
1910                 bool has_audio;
1911
1912                 if (i == intel_dp->force_audio)
1913                         return 0;
1914
1915                 intel_dp->force_audio = i;
1916
1917                 if (i == 0)
1918                         has_audio = intel_dp_detect_audio(connector);
1919                 else
1920                         has_audio = i > 0;
1921
1922                 if (has_audio == intel_dp->has_audio)
1923                         return 0;
1924
1925                 intel_dp->has_audio = has_audio;
1926                 goto done;
1927         }
1928
1929         if (property == dev_priv->broadcast_rgb_property) {
1930                 if (val == !!intel_dp->color_range)
1931                         return 0;
1932
1933                 intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
1934                 goto done;
1935         }
1936
1937         return -EINVAL;
1938
1939 done:
1940         if (intel_dp->base.base.crtc) {
1941                 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1942                 drm_crtc_helper_set_mode(crtc, &crtc->mode,
1943                                          crtc->x, crtc->y,
1944                                          crtc->fb);
1945         }
1946
1947         return 0;
1948 }
1949
1950 static void
1951 intel_dp_destroy (struct drm_connector *connector)
1952 {
1953         struct drm_device *dev = connector->dev;
1954
1955         if (intel_dpd_is_edp(dev))
1956                 intel_panel_destroy_backlight(dev);
1957
1958         drm_sysfs_connector_remove(connector);
1959         drm_connector_cleanup(connector);
1960         kfree(connector);
1961 }
1962
1963 static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
1964 {
1965         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1966
1967         i2c_del_adapter(&intel_dp->adapter);
1968         drm_encoder_cleanup(encoder);
1969         kfree(intel_dp);
1970 }
1971
1972 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
1973         .dpms = intel_dp_dpms,
1974         .mode_fixup = intel_dp_mode_fixup,
1975         .prepare = intel_dp_prepare,
1976         .mode_set = intel_dp_mode_set,
1977         .commit = intel_dp_commit,
1978 };
1979
1980 static const struct drm_connector_funcs intel_dp_connector_funcs = {
1981         .dpms = drm_helper_connector_dpms,
1982         .detect = intel_dp_detect,
1983         .fill_modes = drm_helper_probe_single_connector_modes,
1984         .set_property = intel_dp_set_property,
1985         .destroy = intel_dp_destroy,
1986 };
1987
1988 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
1989         .get_modes = intel_dp_get_modes,
1990         .mode_valid = intel_dp_mode_valid,
1991         .best_encoder = intel_best_encoder,
1992 };
1993
1994 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
1995         .destroy = intel_dp_encoder_destroy,
1996 };
1997
1998 static void
1999 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
2000 {
2001         struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
2002
2003         intel_dp_check_link_status(intel_dp);
2004 }
2005
2006 /* Return which DP Port should be selected for Transcoder DP control */
2007 int
2008 intel_trans_dp_port_sel (struct drm_crtc *crtc)
2009 {
2010         struct drm_device *dev = crtc->dev;
2011         struct drm_mode_config *mode_config = &dev->mode_config;
2012         struct drm_encoder *encoder;
2013
2014         list_for_each_entry(encoder, &mode_config->encoder_list, head) {
2015                 struct intel_dp *intel_dp;
2016
2017                 if (encoder->crtc != crtc)
2018                         continue;
2019
2020                 intel_dp = enc_to_intel_dp(encoder);
2021                 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT)
2022                         return intel_dp->output_reg;
2023         }
2024
2025         return -1;
2026 }
2027
2028 /* check the VBT to see whether the eDP is on DP-D port */
2029 bool intel_dpd_is_edp(struct drm_device *dev)
2030 {
2031         struct drm_i915_private *dev_priv = dev->dev_private;
2032         struct child_device_config *p_child;
2033         int i;
2034
2035         if (!dev_priv->child_dev_num)
2036                 return false;
2037
2038         for (i = 0; i < dev_priv->child_dev_num; i++) {
2039                 p_child = dev_priv->child_dev + i;
2040
2041                 if (p_child->dvo_port == PORT_IDPD &&
2042                     p_child->device_type == DEVICE_TYPE_eDP)
2043                         return true;
2044         }
2045         return false;
2046 }
2047
2048 static void
2049 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2050 {
2051         intel_attach_force_audio_property(connector);
2052         intel_attach_broadcast_rgb_property(connector);
2053 }
2054
2055 void
2056 intel_dp_init(struct drm_device *dev, int output_reg)
2057 {
2058         struct drm_i915_private *dev_priv = dev->dev_private;
2059         struct drm_connector *connector;
2060         struct intel_dp *intel_dp;
2061         struct intel_encoder *intel_encoder;
2062         struct intel_connector *intel_connector;
2063         const char *name = NULL;
2064         int type;
2065
2066         intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL);
2067         if (!intel_dp)
2068                 return;
2069
2070         intel_dp->output_reg = output_reg;
2071         intel_dp->dpms_mode = -1;
2072
2073         intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
2074         if (!intel_connector) {
2075                 kfree(intel_dp);
2076                 return;
2077         }
2078         intel_encoder = &intel_dp->base;
2079
2080         if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D)
2081                 if (intel_dpd_is_edp(dev))
2082                         intel_dp->is_pch_edp = true;
2083
2084         if (output_reg == DP_A || is_pch_edp(intel_dp)) {
2085                 type = DRM_MODE_CONNECTOR_eDP;
2086                 intel_encoder->type = INTEL_OUTPUT_EDP;
2087         } else {
2088                 type = DRM_MODE_CONNECTOR_DisplayPort;
2089                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2090         }
2091
2092         connector = &intel_connector->base;
2093         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
2094         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
2095
2096         connector->polled = DRM_CONNECTOR_POLL_HPD;
2097
2098         if (output_reg == DP_B || output_reg == PCH_DP_B)
2099                 intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT);
2100         else if (output_reg == DP_C || output_reg == PCH_DP_C)
2101                 intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT);
2102         else if (output_reg == DP_D || output_reg == PCH_DP_D)
2103                 intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT);
2104
2105         if (is_edp(intel_dp))
2106                 intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT);
2107
2108         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
2109         connector->interlace_allowed = true;
2110         connector->doublescan_allowed = 0;
2111
2112         drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
2113                          DRM_MODE_ENCODER_TMDS);
2114         drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
2115
2116         intel_connector_attach_encoder(intel_connector, intel_encoder);
2117         drm_sysfs_connector_add(connector);
2118
2119         /* Set up the DDC bus. */
2120         switch (output_reg) {
2121                 case DP_A:
2122                         name = "DPDDC-A";
2123                         break;
2124                 case DP_B:
2125                 case PCH_DP_B:
2126                         dev_priv->hotplug_supported_mask |=
2127                                 HDMIB_HOTPLUG_INT_STATUS;
2128                         name = "DPDDC-B";
2129                         break;
2130                 case DP_C:
2131                 case PCH_DP_C:
2132                         dev_priv->hotplug_supported_mask |=
2133                                 HDMIC_HOTPLUG_INT_STATUS;
2134                         name = "DPDDC-C";
2135                         break;
2136                 case DP_D:
2137                 case PCH_DP_D:
2138                         dev_priv->hotplug_supported_mask |=
2139                                 HDMID_HOTPLUG_INT_STATUS;
2140                         name = "DPDDC-D";
2141                         break;
2142         }
2143
2144         /* Cache some DPCD data in the eDP case */
2145         if (is_edp(intel_dp)) {
2146                 bool ret;
2147                 struct edp_power_seq    cur, vbt;
2148                 u32 pp_on, pp_off, pp_div;
2149
2150                 pp_on = I915_READ(PCH_PP_ON_DELAYS);
2151                 pp_off = I915_READ(PCH_PP_OFF_DELAYS);
2152                 pp_div = I915_READ(PCH_PP_DIVISOR);
2153
2154                 /* Pull timing values out of registers */
2155                 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2156                         PANEL_POWER_UP_DELAY_SHIFT;
2157
2158                 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2159                         PANEL_LIGHT_ON_DELAY_SHIFT;
2160
2161                 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2162                         PANEL_LIGHT_OFF_DELAY_SHIFT;
2163
2164                 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2165                         PANEL_POWER_DOWN_DELAY_SHIFT;
2166
2167                 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2168                                PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2169
2170                 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2171                               cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2172
2173                 vbt = dev_priv->edp.pps;
2174
2175                 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2176                               vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2177
2178 #define get_delay(field)        ((max(cur.field, vbt.field) + 9) / 10)
2179
2180                 intel_dp->panel_power_up_delay = get_delay(t1_t3);
2181                 intel_dp->backlight_on_delay = get_delay(t8);
2182                 intel_dp->backlight_off_delay = get_delay(t9);
2183                 intel_dp->panel_power_down_delay = get_delay(t10);
2184                 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2185
2186                 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2187                               intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2188                               intel_dp->panel_power_cycle_delay);
2189
2190                 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2191                               intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
2192
2193                 ironlake_edp_panel_vdd_on(intel_dp);
2194                 ret = intel_dp_get_dpcd(intel_dp);
2195                 ironlake_edp_panel_vdd_off(intel_dp);
2196                 if (ret) {
2197                         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2198                                 dev_priv->no_aux_handshake =
2199                                         intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
2200                                         DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
2201                 } else {
2202                         /* if this fails, presume the device is a ghost */
2203                         DRM_INFO("failed to retrieve link info, disabling eDP\n");
2204                         intel_dp_encoder_destroy(&intel_dp->base.base);
2205                         intel_dp_destroy(&intel_connector->base);
2206                         return;
2207                 }
2208         }
2209
2210         intel_dp_i2c_init(intel_dp, intel_connector, name);
2211
2212         intel_encoder->hot_plug = intel_dp_hot_plug;
2213
2214         if (is_edp(intel_dp)) {
2215                 dev_priv->int_edp_connector = connector;
2216                 intel_panel_setup_backlight(dev);
2217         }
2218
2219         intel_dp_add_properties(intel_dp, connector);
2220
2221         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2222          * 0xd.  Failure to do so will result in spurious interrupts being
2223          * generated on the port when a cable is not attached.
2224          */
2225         if (IS_G4X(dev) && !IS_GM45(dev)) {
2226                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2227                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2228         }
2229 }