drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <linux/export.h>
  31 #include <linux/notifier.h>
  32 #include <linux/reboot.h>
  33 #include <drm/drmP.h>
  34 #include <drm/drm_atomic_helper.h>
  35 #include <drm/drm_crtc.h>
  36 #include <drm/drm_crtc_helper.h>
  37 #include <drm/drm_edid.h>
  38 #include "intel_drv.h"
  39 #include <drm/i915_drm.h>
  40 #include "i915_drv.h"
  41
  42 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  43
  44 /* Compliance test status bits  */
  45 #define INTEL_DP_RESOLUTION_SHIFT_MASK  0
  46 #define INTEL_DP_RESOLUTION_PREFERRED   (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  47 #define INTEL_DP_RESOLUTION_STANDARD    (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  48 #define INTEL_DP_RESOLUTION_FAILSAFE    (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  49
  50 struct dp_link_dpll {
  51         int clock;
  52         struct dpll dpll;
  53 };
  54
  55 static const struct dp_link_dpll gen4_dpll[] = {
  56         { 162000,
  57                 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
  58         { 270000,
  59                 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
  60 };
  61
  62 static const struct dp_link_dpll pch_dpll[] = {
  63         { 162000,
  64                 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
  65         { 270000,
  66                 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
  67 };
  68
  69 static const struct dp_link_dpll vlv_dpll[] = {
  70         { 162000,
  71                 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
  72         { 270000,
  73                 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
  74 };
  75
  76 /*
  77  * CHV supports eDP 1.4 that have  more link rates.
  78  * Below only provides the fixed rate but exclude variable rate.
  79  */
  80 static const struct dp_link_dpll chv_dpll[] = {
  81         /*
  82          * CHV requires to program fractional division for m2.
  83          * m2 is stored in fixed point format using formula below
  84          * (m2_int << 22) | m2_fraction
  85          */
  86         { 162000,       /* m2_int = 32, m2_fraction = 1677722 */
  87                 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
  88         { 270000,       /* m2_int = 27, m2_fraction = 0 */
  89                 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
  90         { 540000,       /* m2_int = 27, m2_fraction = 0 */
  91                 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
  92 };
  93
  94 static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
  95                                   324000, 432000, 540000 };
  96 static const int skl_rates[] = { 162000, 216000, 270000,
  97                                   324000, 432000, 540000 };
  98 static const int default_rates[] = { 162000, 270000, 540000 };
  99
 100 /**
 101  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
 102  * @intel_dp: DP struct
 103  *
 104  * If a CPU or PCH DP output is attached to an eDP panel, this function
 105  * will return true, and false otherwise.
 106  */
 107 static bool is_edp(struct intel_dp *intel_dp)
 108 {
 109         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 110
 111         return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
 112 }
 113
 114 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
 115 {
 116         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 117
 118         return intel_dig_port->base.base.dev;
 119 }
 120
 121 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
 122 {
 123         return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
 124 }
 125
 126 static void intel_dp_link_down(struct intel_dp *intel_dp);
 127 static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
 128 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 129 static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp);
 130 static void vlv_steal_power_sequencer(struct drm_device *dev,
 131                                       enum pipe pipe);
 132 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
 133
 134 static unsigned int intel_dp_unused_lane_mask(int lane_count)
 135 {
 136         return ~((1 << lane_count) - 1) & 0xf;
 137 }
 138
 139 static int
 140 intel_dp_max_link_bw(struct intel_dp  *intel_dp)
 141 {
 142         int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
 143
 144         switch (max_link_bw) {
 145         case DP_LINK_BW_1_62:
 146         case DP_LINK_BW_2_7:
 147         case DP_LINK_BW_5_4:
 148                 break;
 149         default:
 150                 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
 151                      max_link_bw);
 152                 max_link_bw = DP_LINK_BW_1_62;
 153                 break;
 154         }
 155         return max_link_bw;
 156 }
 157
 158 static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
 159 {
 160         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 161         u8 source_max, sink_max;
 162
 163         source_max = intel_dig_port->max_lanes;
 164         sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
 165
 166         return min(source_max, sink_max);
 167 }
 168
 169 /*
 170  * The units on the numbers in the next two are... bizarre.  Examples will
 171  * make it clearer; this one parallels an example in the eDP spec.
 172  *
 173  * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
 174  *
 175  *     270000 * 1 * 8 / 10 == 216000
 176  *
 177  * The actual data capacity of that configuration is 2.16Gbit/s, so the
 178  * units are decakilobits.  ->clock in a drm_display_mode is in kilohertz -
 179  * or equivalently, kilopixels per second - so for 1680x1050R it'd be
 180  * 119000.  At 18bpp that's 2142000 kilobits per second.
 181  *
 182  * Thus the strange-looking division by 10 in intel_dp_link_required, to
 183  * get the result in decakilobits instead of kilobits.
 184  */
 185
 186 static int
 187 intel_dp_link_required(int pixel_clock, int bpp)
 188 {
 189         return (pixel_clock * bpp + 9) / 10;
 190 }
 191
 192 static int
 193 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 194 {
 195         return (max_link_clock * max_lanes * 8) / 10;
 196 }
 197
 198 static enum drm_mode_status
 199 intel_dp_mode_valid(struct drm_connector *connector,
 200                     struct drm_display_mode *mode)
 201 {
 202         struct intel_dp *intel_dp = intel_attached_dp(connector);
 203         struct intel_connector *intel_connector = to_intel_connector(connector);
 204         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 205         int target_clock = mode->clock;
 206         int max_rate, mode_rate, max_lanes, max_link_clock;
 207         int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
 208
 209         if (is_edp(intel_dp) && fixed_mode) {
 210                 if (mode->hdisplay > fixed_mode->hdisplay)
 211                         return MODE_PANEL;
 212
 213                 if (mode->vdisplay > fixed_mode->vdisplay)
 214                         return MODE_PANEL;
 215
 216                 target_clock = fixed_mode->clock;
 217         }
 218
 219         max_link_clock = intel_dp_max_link_rate(intel_dp);
 220         max_lanes = intel_dp_max_lane_count(intel_dp);
 221
 222         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 223         mode_rate = intel_dp_link_required(target_clock, 18);
 224
 225         if (mode_rate > max_rate || target_clock > max_dotclk)
 226                 return MODE_CLOCK_HIGH;
 227
 228         if (mode->clock < 10000)
 229                 return MODE_CLOCK_LOW;
 230
 231         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 232                 return MODE_H_ILLEGAL;
 233
 234         return MODE_OK;
 235 }
 236
 237 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
 238 {
 239         int     i;
 240         uint32_t v = 0;
 241
 242         if (src_bytes > 4)
 243                 src_bytes = 4;
 244         for (i = 0; i < src_bytes; i++)
 245                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 246         return v;
 247 }
 248
 249 static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 250 {
 251         int i;
 252         if (dst_bytes > 4)
 253                 dst_bytes = 4;
 254         for (i = 0; i < dst_bytes; i++)
 255                 dst[i] = src >> ((3-i) * 8);
 256 }
 257
 258 static void
 259 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
 260                                     struct intel_dp *intel_dp);
 261 static void
 262 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
 263                                               struct intel_dp *intel_dp);
 264
 265 static void pps_lock(struct intel_dp *intel_dp)
 266 {
 267         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 268         struct intel_encoder *encoder = &intel_dig_port->base;
 269         struct drm_device *dev = encoder->base.dev;
 270         struct drm_i915_private *dev_priv = dev->dev_private;
 271         enum intel_display_power_domain power_domain;
 272
 273         /*
 274          * See vlv_power_sequencer_reset() why we need
 275          * a power domain reference here.
 276          */
 277         power_domain = intel_display_port_aux_power_domain(encoder);
 278         intel_display_power_get(dev_priv, power_domain);
 279
 280         mutex_lock(&dev_priv->pps_mutex);
 281 }
 282
 283 static void pps_unlock(struct intel_dp *intel_dp)
 284 {
 285         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 286         struct intel_encoder *encoder = &intel_dig_port->base;
 287         struct drm_device *dev = encoder->base.dev;
 288         struct drm_i915_private *dev_priv = dev->dev_private;
 289         enum intel_display_power_domain power_domain;
 290
 291         mutex_unlock(&dev_priv->pps_mutex);
 292
 293         power_domain = intel_display_port_aux_power_domain(encoder);
 294         intel_display_power_put(dev_priv, power_domain);
 295 }
 296
 297 static void
 298 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
 299 {
 300         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 301         struct drm_device *dev = intel_dig_port->base.base.dev;
 302         struct drm_i915_private *dev_priv = dev->dev_private;
 303         enum pipe pipe = intel_dp->pps_pipe;
 304         bool pll_enabled, release_cl_override = false;
 305         enum dpio_phy phy = DPIO_PHY(pipe);
 306         enum dpio_channel ch = vlv_pipe_to_channel(pipe);
 307         uint32_t DP;
 308
 309         if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
 310                  "skipping pipe %c power seqeuncer kick due to port %c being active\n",
 311                  pipe_name(pipe), port_name(intel_dig_port->port)))
 312                 return;
 313
 314         DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
 315                       pipe_name(pipe), port_name(intel_dig_port->port));
 316
 317         /* Preserve the BIOS-computed detected bit. This is
 318          * supposed to be read-only.
 319          */
 320         DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
 321         DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 322         DP |= DP_PORT_WIDTH(1);
 323         DP |= DP_LINK_TRAIN_PAT_1;
 324
 325         if (IS_CHERRYVIEW(dev))
 326                 DP |= DP_PIPE_SELECT_CHV(pipe);
 327         else if (pipe == PIPE_B)
 328                 DP |= DP_PIPEB_SELECT;
 329
 330         pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
 331
 332         /*
 333          * The DPLL for the pipe must be enabled for this to work.
 334          * So enable temporarily it if it's not already enabled.
 335          */
 336         if (!pll_enabled) {
 337                 release_cl_override = IS_CHERRYVIEW(dev) &&
 338                         !chv_phy_powergate_ch(dev_priv, phy, ch, true);
 339
 340                 if (vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev) ?
 341                                      &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
 342                         DRM_ERROR("Failed to force on pll for pipe %c!\n",
 343                                   pipe_name(pipe));
 344                         return;
 345                 }
 346         }
 347
 348         /*
 349          * Similar magic as in intel_dp_enable_port().
 350          * We _must_ do this port enable + disable trick
 351          * to make this power seqeuencer lock onto the port.
 352          * Otherwise even VDD force bit won't work.
 353          */
 354         I915_WRITE(intel_dp->output_reg, DP);
 355         POSTING_READ(intel_dp->output_reg);
 356
 357         I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
 358         POSTING_READ(intel_dp->output_reg);
 359
 360         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
 361         POSTING_READ(intel_dp->output_reg);
 362
 363         if (!pll_enabled) {
 364                 vlv_force_pll_off(dev, pipe);
 365
 366                 if (release_cl_override)
 367                         chv_phy_powergate_ch(dev_priv, phy, ch, false);
 368         }
 369 }
 370
 371 static enum pipe
 372 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
 373 {
 374         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 375         struct drm_device *dev = intel_dig_port->base.base.dev;
 376         struct drm_i915_private *dev_priv = dev->dev_private;
 377         struct intel_encoder *encoder;
 378         unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
 379         enum pipe pipe;
 380
 381         lockdep_assert_held(&dev_priv->pps_mutex);
 382
 383         /* We should never land here with regular DP ports */
 384         WARN_ON(!is_edp(intel_dp));
 385
 386         if (intel_dp->pps_pipe != INVALID_PIPE)
 387                 return intel_dp->pps_pipe;
 388
 389         /*
 390          * We don't have power sequencer currently.
 391          * Pick one that's not used by other ports.
 392          */
 393         for_each_intel_encoder(dev, encoder) {
 394                 struct intel_dp *tmp;
 395
 396                 if (encoder->type != INTEL_OUTPUT_EDP)
 397                         continue;
 398
 399                 tmp = enc_to_intel_dp(&encoder->base);
 400
 401                 if (tmp->pps_pipe != INVALID_PIPE)
 402                         pipes &= ~(1 << tmp->pps_pipe);
 403         }
 404
 405         /*
 406          * Didn't find one. This should not happen since there
 407          * are two power sequencers and up to two eDP ports.
 408          */
 409         if (WARN_ON(pipes == 0))
 410                 pipe = PIPE_A;
 411         else
 412                 pipe = ffs(pipes) - 1;
 413
 414         vlv_steal_power_sequencer(dev, pipe);
 415         intel_dp->pps_pipe = pipe;
 416
 417         DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
 418                       pipe_name(intel_dp->pps_pipe),
 419                       port_name(intel_dig_port->port));
 420
 421         /* init power sequencer on this pipe and port */
 422         intel_dp_init_panel_power_sequencer(dev, intel_dp);
 423         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
 424
 425         /*
 426          * Even vdd force doesn't work until we've made
 427          * the power sequencer lock in on the port.
 428          */
 429         vlv_power_sequencer_kick(intel_dp);
 430
 431         return intel_dp->pps_pipe;
 432 }
 433
 434 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
 435                                enum pipe pipe);
 436
 437 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
 438                                enum pipe pipe)
 439 {
 440         return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON;
 441 }
 442
 443 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
 444                                 enum pipe pipe)
 445 {
 446         return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD;
 447 }
 448
 449 static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
 450                          enum pipe pipe)
 451 {
 452         return true;
 453 }
 454
 455 static enum pipe
 456 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
 457                      enum port port,
 458                      vlv_pipe_check pipe_check)
 459 {
 460         enum pipe pipe;
 461
 462         for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
 463                 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
 464                         PANEL_PORT_SELECT_MASK;
 465
 466                 if (port_sel != PANEL_PORT_SELECT_VLV(port))
 467                         continue;
 468
 469                 if (!pipe_check(dev_priv, pipe))
 470                         continue;
 471
 472                 return pipe;
 473         }
 474
 475         return INVALID_PIPE;
 476 }
 477
 478 static void
 479 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
 480 {
 481         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 482         struct drm_device *dev = intel_dig_port->base.base.dev;
 483         struct drm_i915_private *dev_priv = dev->dev_private;
 484         enum port port = intel_dig_port->port;
 485
 486         lockdep_assert_held(&dev_priv->pps_mutex);
 487
 488         /* try to find a pipe with this port selected */
 489         /* first pick one where the panel is on */
 490         intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 491                                                   vlv_pipe_has_pp_on);
 492         /* didn't find one? pick one where vdd is on */
 493         if (intel_dp->pps_pipe == INVALID_PIPE)
 494                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 495                                                           vlv_pipe_has_vdd_on);
 496         /* didn't find one? pick one with just the correct port */
 497         if (intel_dp->pps_pipe == INVALID_PIPE)
 498                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 499                                                           vlv_pipe_any);
 500
 501         /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
 502         if (intel_dp->pps_pipe == INVALID_PIPE) {
 503                 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
 504                               port_name(port));
 505                 return;
 506         }
 507
 508         DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
 509                       port_name(port), pipe_name(intel_dp->pps_pipe));
 510
 511         intel_dp_init_panel_power_sequencer(dev, intel_dp);
 512         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
 513 }
 514
 515 void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv)
 516 {
 517         struct drm_device *dev = dev_priv->dev;
 518         struct intel_encoder *encoder;
 519
 520         if (WARN_ON(!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)))
 521                 return;
 522
 523         /*
 524          * We can't grab pps_mutex here due to deadlock with power_domain
 525          * mutex when power_domain functions are called while holding pps_mutex.
 526          * That also means that in order to use pps_pipe the code needs to
 527          * hold both a power domain reference and pps_mutex, and the power domain
 528          * reference get/put must be done while _not_ holding pps_mutex.
 529          * pps_{lock,unlock}() do these steps in the correct order, so one
 530          * should use them always.
 531          */
 532
 533         for_each_intel_encoder(dev, encoder) {
 534                 struct intel_dp *intel_dp;
 535
 536                 if (encoder->type != INTEL_OUTPUT_EDP)
 537                         continue;
 538
 539                 intel_dp = enc_to_intel_dp(&encoder->base);
 540                 intel_dp->pps_pipe = INVALID_PIPE;
 541         }
 542 }
 543
 544 static i915_reg_t
 545 _pp_ctrl_reg(struct intel_dp *intel_dp)
 546 {
 547         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 548
 549         if (IS_BROXTON(dev))
 550                 return BXT_PP_CONTROL(0);
 551         else if (HAS_PCH_SPLIT(dev))
 552                 return PCH_PP_CONTROL;
 553         else
 554                 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
 555 }
 556
 557 static i915_reg_t
 558 _pp_stat_reg(struct intel_dp *intel_dp)
 559 {
 560         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 561
 562         if (IS_BROXTON(dev))
 563                 return BXT_PP_STATUS(0);
 564         else if (HAS_PCH_SPLIT(dev))
 565                 return PCH_PP_STATUS;
 566         else
 567                 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
 568 }
 569
 570 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
 571    This function only applicable when panel PM state is not to be tracked */
 572 static int edp_notify_handler(struct notifier_block *this, unsigned long code,
 573                               void *unused)
 574 {
 575         struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
 576                                                  edp_notifier);
 577         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 578         struct drm_i915_private *dev_priv = dev->dev_private;
 579
 580         if (!is_edp(intel_dp) || code != SYS_RESTART)
 581                 return 0;
 582
 583         pps_lock(intel_dp);
 584
 585         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 586                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
 587                 i915_reg_t pp_ctrl_reg, pp_div_reg;
 588                 u32 pp_div;
 589
 590                 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
 591                 pp_div_reg  = VLV_PIPE_PP_DIVISOR(pipe);
 592                 pp_div = I915_READ(pp_div_reg);
 593                 pp_div &= PP_REFERENCE_DIVIDER_MASK;
 594
 595                 /* 0x1F write to PP_DIV_REG sets max cycle delay */
 596                 I915_WRITE(pp_div_reg, pp_div | 0x1F);
 597                 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
 598                 msleep(intel_dp->panel_power_cycle_delay);
 599         }
 600
 601         pps_unlock(intel_dp);
 602
 603         return 0;
 604 }
 605
 606 static bool edp_have_panel_power(struct intel_dp *intel_dp)
 607 {
 608         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 609         struct drm_i915_private *dev_priv = dev->dev_private;
 610
 611         lockdep_assert_held(&dev_priv->pps_mutex);
 612
 613         if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
 614             intel_dp->pps_pipe == INVALID_PIPE)
 615                 return false;
 616
 617         return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
 618 }
 619
 620 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
 621 {
 622         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 623         struct drm_i915_private *dev_priv = dev->dev_private;
 624
 625         lockdep_assert_held(&dev_priv->pps_mutex);
 626
 627         if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
 628             intel_dp->pps_pipe == INVALID_PIPE)
 629                 return false;
 630
 631         return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
 632 }
 633
 634 static void
 635 intel_dp_check_edp(struct intel_dp *intel_dp)
 636 {
 637         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 638         struct drm_i915_private *dev_priv = dev->dev_private;
 639
 640         if (!is_edp(intel_dp))
 641                 return;
 642
 643         if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
 644                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
 645                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
 646                               I915_READ(_pp_stat_reg(intel_dp)),
 647                               I915_READ(_pp_ctrl_reg(intel_dp)));
 648         }
 649 }
 650
 651 static uint32_t
 652 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
 653 {
 654         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 655         struct drm_device *dev = intel_dig_port->base.base.dev;
 656         struct drm_i915_private *dev_priv = dev->dev_private;
 657         i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 658         uint32_t status;
 659         bool done;
 660
 661 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 662         if (has_aux_irq)
 663                 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
 664                                           msecs_to_jiffies_timeout(10));
 665         else
 666                 done = wait_for_atomic(C, 10) == 0;
 667         if (!done)
 668                 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
 669                           has_aux_irq);
 670 #undef C
 671
 672         return status;
 673 }
 674
 675 static uint32_t g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 676 {
 677         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 678         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
 679
 680         if (index)
 681                 return 0;
 682
 683         /*
 684          * The clock divider is based off the hrawclk, and would like to run at
 685          * 2MHz.  So, take the hrawclk value and divide by 2000 and use that
 686          */
 687         return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
 688 }
 689
 690 static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 691 {
 692         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 693         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
 694
 695         if (index)
 696                 return 0;
 697
 698         /*
 699          * The clock divider is based off the cdclk or PCH rawclk, and would
 700          * like to run at 2MHz.  So, take the cdclk or PCH rawclk value and
 701          * divide by 2000 and use that
 702          */
 703         if (intel_dig_port->port == PORT_A)
 704                 return DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 2000);
 705         else
 706                 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
 707 }
 708
 709 static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 710 {
 711         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 712         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
 713
 714         if (intel_dig_port->port != PORT_A && HAS_PCH_LPT_H(dev_priv)) {
 715                 /* Workaround for non-ULT HSW */
 716                 switch (index) {
 717                 case 0: return 63;
 718                 case 1: return 72;
 719                 default: return 0;
 720                 }
 721         }
 722
 723         return ilk_get_aux_clock_divider(intel_dp, index);
 724 }
 725
 726 static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 727 {
 728         /*
 729          * SKL doesn't need us to program the AUX clock divider (Hardware will
 730          * derive the clock from CDCLK automatically). We still implement the
 731          * get_aux_clock_divider vfunc to plug-in into the existing code.
 732          */
 733         return index ? 0 : 1;
 734 }
 735
 736 static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
 737                                      bool has_aux_irq,
 738                                      int send_bytes,
 739                                      uint32_t aux_clock_divider)
 740 {
 741         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 742         struct drm_device *dev = intel_dig_port->base.base.dev;
 743         uint32_t precharge, timeout;
 744
 745         if (IS_GEN6(dev))
 746                 precharge = 3;
 747         else
 748                 precharge = 5;
 749
 750         if (IS_BROADWELL(dev) && intel_dig_port->port == PORT_A)
 751                 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
 752         else
 753                 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
 754
 755         return DP_AUX_CH_CTL_SEND_BUSY |
 756                DP_AUX_CH_CTL_DONE |
 757                (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
 758                DP_AUX_CH_CTL_TIME_OUT_ERROR |
 759                timeout |
 760                DP_AUX_CH_CTL_RECEIVE_ERROR |
 761                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 762                (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 763                (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
 764 }
 765
 766 static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
 767                                       bool has_aux_irq,
 768                                       int send_bytes,
 769                                       uint32_t unused)
 770 {
 771         return DP_AUX_CH_CTL_SEND_BUSY |
 772                DP_AUX_CH_CTL_DONE |
 773                (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
 774                DP_AUX_CH_CTL_TIME_OUT_ERROR |
 775                DP_AUX_CH_CTL_TIME_OUT_1600us |
 776                DP_AUX_CH_CTL_RECEIVE_ERROR |
 777                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 778                DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
 779 }
 780
 781 static int
 782 intel_dp_aux_ch(struct intel_dp *intel_dp,
 783                 const uint8_t *send, int send_bytes,
 784                 uint8_t *recv, int recv_size)
 785 {
 786         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 787         struct drm_device *dev = intel_dig_port->base.base.dev;
 788         struct drm_i915_private *dev_priv = dev->dev_private;
 789         i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 790         uint32_t aux_clock_divider;
 791         int i, ret, recv_bytes;
 792         uint32_t status;
 793         int try, clock = 0;
 794         bool has_aux_irq = HAS_AUX_IRQ(dev);
 795         bool vdd;
 796
 797         pps_lock(intel_dp);
 798
 799         /*
 800          * We will be called with VDD already enabled for dpcd/edid/oui reads.
 801          * In such cases we want to leave VDD enabled and it's up to upper layers
 802          * to turn it off. But for eg. i2c-dev access we need to turn it on/off
 803          * ourselves.
 804          */
 805         vdd = edp_panel_vdd_on(intel_dp);
 806
 807         /* dp aux is extremely sensitive to irq latency, hence request the
 808          * lowest possible wakeup latency and so prevent the cpu from going into
 809          * deep sleep states.
 810          */
 811         pm_qos_update_request(&dev_priv->pm_qos, 0);
 812
 813         intel_dp_check_edp(intel_dp);
 814
 815         /* Try to wait for any previous AUX channel activity */
 816         for (try = 0; try < 3; try++) {
 817                 status = I915_READ_NOTRACE(ch_ctl);
 818                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 819                         break;
 820                 msleep(1);
 821         }
 822
 823         if (try == 3) {
 824                 static u32 last_status = -1;
 825                 const u32 status = I915_READ(ch_ctl);
 826
 827                 if (status != last_status) {
 828                         WARN(1, "dp_aux_ch not started status 0x%08x\n",
 829                              status);
 830                         last_status = status;
 831                 }
 832
 833                 ret = -EBUSY;
 834                 goto out;
 835         }
 836
 837         /* Only 5 data registers! */
 838         if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
 839                 ret = -E2BIG;
 840                 goto out;
 841         }
 842
 843         while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
 844                 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
 845                                                           has_aux_irq,
 846                                                           send_bytes,
 847                                                           aux_clock_divider);
 848
 849                 /* Must try at least 3 times according to DP spec */
 850                 for (try = 0; try < 5; try++) {
 851                         /* Load the send data into the aux channel data registers */
 852                         for (i = 0; i < send_bytes; i += 4)
 853                                 I915_WRITE(intel_dp->aux_ch_data_reg[i >> 2],
 854                                            intel_dp_pack_aux(send + i,
 855                                                              send_bytes - i));
 856
 857                         /* Send the command and wait for it to complete */
 858                         I915_WRITE(ch_ctl, send_ctl);
 859
 860                         status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
 861
 862                         /* Clear done status and any errors */
 863                         I915_WRITE(ch_ctl,
 864                                    status |
 865                                    DP_AUX_CH_CTL_DONE |
 866                                    DP_AUX_CH_CTL_TIME_OUT_ERROR |
 867                                    DP_AUX_CH_CTL_RECEIVE_ERROR);
 868
 869                         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
 870                                 continue;
 871
 872                         /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
 873                          *   400us delay required for errors and timeouts
 874                          *   Timeout errors from the HW already meet this
 875                          *   requirement so skip to next iteration
 876                          */
 877                         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 878                                 usleep_range(400, 500);
 879                                 continue;
 880                         }
 881                         if (status & DP_AUX_CH_CTL_DONE)
 882                                 goto done;
 883                 }
 884         }
 885
 886         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
 887                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
 888                 ret = -EBUSY;
 889                 goto out;
 890         }
 891
 892 done:
 893         /* Check for timeout or receive error.
 894          * Timeouts occur when the sink is not connected
 895          */
 896         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 897                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
 898                 ret = -EIO;
 899                 goto out;
 900         }
 901
 902         /* Timeouts occur when the device isn't connected, so they're
 903          * "normal" -- don't fill the kernel log with these */
 904         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
 905                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
 906                 ret = -ETIMEDOUT;
 907                 goto out;
 908         }
 909
 910         /* Unload any bytes sent back from the other side */
 911         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
 912                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
 913
 914         /*
 915          * By BSpec: "Message sizes of 0 or >20 are not allowed."
 916          * We have no idea of what happened so we return -EBUSY so
 917          * drm layer takes care for the necessary retries.
 918          */
 919         if (recv_bytes == 0 || recv_bytes > 20) {
 920                 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
 921                               recv_bytes);
 922                 /*
 923                  * FIXME: This patch was created on top of a series that
 924                  * organize the retries at drm level. There EBUSY should
 925                  * also take care for 1ms wait before retrying.
 926                  * That aux retries re-org is still needed and after that is
 927                  * merged we remove this sleep from here.
 928                  */
 929                 usleep_range(1000, 1500);
 930                 ret = -EBUSY;
 931                 goto out;
 932         }
 933
 934         if (recv_bytes > recv_size)
 935                 recv_bytes = recv_size;
 936
 937         for (i = 0; i < recv_bytes; i += 4)
 938                 intel_dp_unpack_aux(I915_READ(intel_dp->aux_ch_data_reg[i >> 2]),
 939                                     recv + i, recv_bytes - i);
 940
 941         ret = recv_bytes;
 942 out:
 943         pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
 944
 945         if (vdd)
 946                 edp_panel_vdd_off(intel_dp, false);
 947
 948         pps_unlock(intel_dp);
 949
 950         return ret;
 951 }
 952
 953 #define BARE_ADDRESS_SIZE       3
 954 #define HEADER_SIZE             (BARE_ADDRESS_SIZE + 1)
 955 static ssize_t
 956 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
 957 {
 958         struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
 959         uint8_t txbuf[20], rxbuf[20];
 960         size_t txsize, rxsize;
 961         int ret;
 962
 963         txbuf[0] = (msg->request << 4) |
 964                 ((msg->address >> 16) & 0xf);
 965         txbuf[1] = (msg->address >> 8) & 0xff;
 966         txbuf[2] = msg->address & 0xff;
 967         txbuf[3] = msg->size - 1;
 968
 969         switch (msg->request & ~DP_AUX_I2C_MOT) {
 970         case DP_AUX_NATIVE_WRITE:
 971         case DP_AUX_I2C_WRITE:
 972         case DP_AUX_I2C_WRITE_STATUS_UPDATE:
 973                 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
 974                 rxsize = 2; /* 0 or 1 data bytes */
 975
 976                 if (WARN_ON(txsize > 20))
 977                         return -E2BIG;
 978
 979                 if (msg->buffer)
 980                         memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
 981                 else
 982                         WARN_ON(msg->size);
 983
 984                 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
 985                 if (ret > 0) {
 986                         msg->reply = rxbuf[0] >> 4;
 987
 988                         if (ret > 1) {
 989                                 /* Number of bytes written in a short write. */
 990                                 ret = clamp_t(int, rxbuf[1], 0, msg->size);
 991                         } else {
 992                                 /* Return payload size. */
 993                                 ret = msg->size;
 994                         }
 995                 }
 996                 break;
 997
 998         case DP_AUX_NATIVE_READ:
 999         case DP_AUX_I2C_READ:
1000                 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
1001                 rxsize = msg->size + 1;
1002
1003                 if (WARN_ON(rxsize > 20))
1004                         return -E2BIG;
1005
1006                 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
1007                 if (ret > 0) {
1008                         msg->reply = rxbuf[0] >> 4;
1009                         /*
1010                          * Assume happy day, and copy the data. The caller is
1011                          * expected to check msg->reply before touching it.
1012                          *
1013                          * Return payload size.
1014                          */
1015                         ret--;
1016                         memcpy(msg->buffer, rxbuf + 1, ret);
1017                 }
1018                 break;
1019
1020         default:
1021                 ret = -EINVAL;
1022                 break;
1023         }
1024
1025         return ret;
1026 }
1027
1028 static i915_reg_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv,
1029                                        enum port port)
1030 {
1031         switch (port) {
1032         case PORT_B:
1033         case PORT_C:
1034         case PORT_D:
1035                 return DP_AUX_CH_CTL(port);
1036         default:
1037                 MISSING_CASE(port);
1038                 return DP_AUX_CH_CTL(PORT_B);
1039         }
1040 }
1041
1042 static i915_reg_t g4x_aux_data_reg(struct drm_i915_private *dev_priv,
1043                                         enum port port, int index)
1044 {
1045         switch (port) {
1046         case PORT_B:
1047         case PORT_C:
1048         case PORT_D:
1049                 return DP_AUX_CH_DATA(port, index);
1050         default:
1051                 MISSING_CASE(port);
1052                 return DP_AUX_CH_DATA(PORT_B, index);
1053         }
1054 }
1055
1056 static i915_reg_t ilk_aux_ctl_reg(struct drm_i915_private *dev_priv,
1057                                        enum port port)
1058 {
1059         switch (port) {
1060         case PORT_A:
1061                 return DP_AUX_CH_CTL(port);
1062         case PORT_B:
1063         case PORT_C:
1064         case PORT_D:
1065                 return PCH_DP_AUX_CH_CTL(port);
1066         default:
1067                 MISSING_CASE(port);
1068                 return DP_AUX_CH_CTL(PORT_A);
1069         }
1070 }
1071
1072 static i915_reg_t ilk_aux_data_reg(struct drm_i915_private *dev_priv,
1073                                         enum port port, int index)
1074 {
1075         switch (port) {
1076         case PORT_A:
1077                 return DP_AUX_CH_DATA(port, index);
1078         case PORT_B:
1079         case PORT_C:
1080         case PORT_D:
1081                 return PCH_DP_AUX_CH_DATA(port, index);
1082         default:
1083                 MISSING_CASE(port);
1084                 return DP_AUX_CH_DATA(PORT_A, index);
1085         }
1086 }
1087
1088 /*
1089  * On SKL we don't have Aux for port E so we rely
1090  * on VBT to set a proper alternate aux channel.
1091  */
1092 static enum port skl_porte_aux_port(struct drm_i915_private *dev_priv)
1093 {
1094         const struct ddi_vbt_port_info *info =
1095                 &dev_priv->vbt.ddi_port_info[PORT_E];
1096
1097         switch (info->alternate_aux_channel) {
1098         case DP_AUX_A:
1099                 return PORT_A;
1100         case DP_AUX_B:
1101                 return PORT_B;
1102         case DP_AUX_C:
1103                 return PORT_C;
1104         case DP_AUX_D:
1105                 return PORT_D;
1106         default:
1107                 MISSING_CASE(info->alternate_aux_channel);
1108                 return PORT_A;
1109         }
1110 }
1111
1112 static i915_reg_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv,
1113                                        enum port port)
1114 {
1115         if (port == PORT_E)
1116                 port = skl_porte_aux_port(dev_priv);
1117
1118         switch (port) {
1119         case PORT_A:
1120         case PORT_B:
1121         case PORT_C:
1122         case PORT_D:
1123                 return DP_AUX_CH_CTL(port);
1124         default:
1125                 MISSING_CASE(port);
1126                 return DP_AUX_CH_CTL(PORT_A);
1127         }
1128 }
1129
1130 static i915_reg_t skl_aux_data_reg(struct drm_i915_private *dev_priv,
1131                                         enum port port, int index)
1132 {
1133         if (port == PORT_E)
1134                 port = skl_porte_aux_port(dev_priv);
1135
1136         switch (port) {
1137         case PORT_A:
1138         case PORT_B:
1139         case PORT_C:
1140         case PORT_D:
1141                 return DP_AUX_CH_DATA(port, index);
1142         default:
1143                 MISSING_CASE(port);
1144                 return DP_AUX_CH_DATA(PORT_A, index);
1145         }
1146 }
1147
1148 static i915_reg_t intel_aux_ctl_reg(struct drm_i915_private *dev_priv,
1149                                          enum port port)
1150 {
1151         if (INTEL_INFO(dev_priv)->gen >= 9)
1152                 return skl_aux_ctl_reg(dev_priv, port);
1153         else if (HAS_PCH_SPLIT(dev_priv))
1154                 return ilk_aux_ctl_reg(dev_priv, port);
1155         else
1156                 return g4x_aux_ctl_reg(dev_priv, port);
1157 }
1158
1159 static i915_reg_t intel_aux_data_reg(struct drm_i915_private *dev_priv,
1160                                           enum port port, int index)
1161 {
1162         if (INTEL_INFO(dev_priv)->gen >= 9)
1163                 return skl_aux_data_reg(dev_priv, port, index);
1164         else if (HAS_PCH_SPLIT(dev_priv))
1165                 return ilk_aux_data_reg(dev_priv, port, index);
1166         else
1167                 return g4x_aux_data_reg(dev_priv, port, index);
1168 }
1169
1170 static void intel_aux_reg_init(struct intel_dp *intel_dp)
1171 {
1172         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1173         enum port port = dp_to_dig_port(intel_dp)->port;
1174         int i;
1175
1176         intel_dp->aux_ch_ctl_reg = intel_aux_ctl_reg(dev_priv, port);
1177         for (i = 0; i < ARRAY_SIZE(intel_dp->aux_ch_data_reg); i++)
1178                 intel_dp->aux_ch_data_reg[i] = intel_aux_data_reg(dev_priv, port, i);
1179 }
1180
1181 static void
1182 intel_dp_aux_fini(struct intel_dp *intel_dp)
1183 {
1184         drm_dp_aux_unregister(&intel_dp->aux);
1185         kfree(intel_dp->aux.name);
1186 }
1187
1188 static int
1189 intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
1190 {
1191         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1192         enum port port = intel_dig_port->port;
1193         int ret;
1194
1195         intel_aux_reg_init(intel_dp);
1196
1197         intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c", port_name(port));
1198         if (!intel_dp->aux.name)
1199                 return -ENOMEM;
1200
1201         intel_dp->aux.dev = connector->base.kdev;
1202         intel_dp->aux.transfer = intel_dp_aux_transfer;
1203
1204         DRM_DEBUG_KMS("registering %s bus for %s\n",
1205                       intel_dp->aux.name,
1206                       connector->base.kdev->kobj.name);
1207
1208         ret = drm_dp_aux_register(&intel_dp->aux);
1209         if (ret < 0) {
1210                 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
1211                           intel_dp->aux.name, ret);
1212                 kfree(intel_dp->aux.name);
1213                 return ret;
1214         }
1215
1216         return 0;
1217 }
1218
1219 static void
1220 intel_dp_connector_unregister(struct intel_connector *intel_connector)
1221 {
1222         struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
1223
1224         intel_dp_aux_fini(intel_dp);
1225         intel_connector_unregister(intel_connector);
1226 }
1227
1228 static int
1229 intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
1230 {
1231         if (intel_dp->num_sink_rates) {
1232                 *sink_rates = intel_dp->sink_rates;
1233                 return intel_dp->num_sink_rates;
1234         }
1235
1236         *sink_rates = default_rates;
1237
1238         return (intel_dp_max_link_bw(intel_dp) >> 3) + 1;
1239 }
1240
1241 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
1242 {
1243         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1244         struct drm_device *dev = dig_port->base.base.dev;
1245
1246         /* WaDisableHBR2:skl */
1247         if (IS_SKL_REVID(dev, 0, SKL_REVID_B0))
1248                 return false;
1249
1250         if ((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) || IS_BROADWELL(dev) ||
1251             (INTEL_INFO(dev)->gen >= 9))
1252                 return true;
1253         else
1254                 return false;
1255 }
1256
1257 static int
1258 intel_dp_source_rates(struct intel_dp *intel_dp, const int **source_rates)
1259 {
1260         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1261         struct drm_device *dev = dig_port->base.base.dev;
1262         int size;
1263
1264         if (IS_BROXTON(dev)) {
1265                 *source_rates = bxt_rates;
1266                 size = ARRAY_SIZE(bxt_rates);
1267         } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
1268                 *source_rates = skl_rates;
1269                 size = ARRAY_SIZE(skl_rates);
1270         } else {
1271                 *source_rates = default_rates;
1272                 size = ARRAY_SIZE(default_rates);
1273         }
1274
1275         /* This depends on the fact that 5.4 is last value in the array */
1276         if (!intel_dp_source_supports_hbr2(intel_dp))
1277                 size--;
1278
1279         return size;
1280 }
1281
1282 static void
1283 intel_dp_set_clock(struct intel_encoder *encoder,
1284                    struct intel_crtc_state *pipe_config)
1285 {
1286         struct drm_device *dev = encoder->base.dev;
1287         const struct dp_link_dpll *divisor = NULL;
1288         int i, count = 0;
1289
1290         if (IS_G4X(dev)) {
1291                 divisor = gen4_dpll;
1292                 count = ARRAY_SIZE(gen4_dpll);
1293         } else if (HAS_PCH_SPLIT(dev)) {
1294                 divisor = pch_dpll;
1295                 count = ARRAY_SIZE(pch_dpll);
1296         } else if (IS_CHERRYVIEW(dev)) {
1297                 divisor = chv_dpll;
1298                 count = ARRAY_SIZE(chv_dpll);
1299         } else if (IS_VALLEYVIEW(dev)) {
1300                 divisor = vlv_dpll;
1301                 count = ARRAY_SIZE(vlv_dpll);
1302         }
1303
1304         if (divisor && count) {
1305                 for (i = 0; i < count; i++) {
1306                         if (pipe_config->port_clock == divisor[i].clock) {
1307                                 pipe_config->dpll = divisor[i].dpll;
1308                                 pipe_config->clock_set = true;
1309                                 break;
1310                         }
1311                 }
1312         }
1313 }
1314
1315 static int intersect_rates(const int *source_rates, int source_len,
1316                            const int *sink_rates, int sink_len,
1317                            int *common_rates)
1318 {
1319         int i = 0, j = 0, k = 0;
1320
1321         while (i < source_len && j < sink_len) {
1322                 if (source_rates[i] == sink_rates[j]) {
1323                         if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
1324                                 return k;
1325                         common_rates[k] = source_rates[i];
1326                         ++k;
1327                         ++i;
1328                         ++j;
1329                 } else if (source_rates[i] < sink_rates[j]) {
1330                         ++i;
1331                 } else {
1332                         ++j;
1333                 }
1334         }
1335         return k;
1336 }
1337
1338 static int intel_dp_common_rates(struct intel_dp *intel_dp,
1339                                  int *common_rates)
1340 {
1341         const int *source_rates, *sink_rates;
1342         int source_len, sink_len;
1343
1344         sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
1345         source_len = intel_dp_source_rates(intel_dp, &source_rates);
1346
1347         return intersect_rates(source_rates, source_len,
1348                                sink_rates, sink_len,
1349                                common_rates);
1350 }
1351
1352 static void snprintf_int_array(char *str, size_t len,
1353                                const int *array, int nelem)
1354 {
1355         int i;
1356
1357         str[0] = '\0';
1358
1359         for (i = 0; i < nelem; i++) {
1360                 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1361                 if (r >= len)
1362                         return;
1363                 str += r;
1364                 len -= r;
1365         }
1366 }
1367
1368 static void intel_dp_print_rates(struct intel_dp *intel_dp)
1369 {
1370         const int *source_rates, *sink_rates;
1371         int source_len, sink_len, common_len;
1372         int common_rates[DP_MAX_SUPPORTED_RATES];
1373         char str[128]; /* FIXME: too big for stack? */
1374
1375         if ((drm_debug & DRM_UT_KMS) == 0)
1376                 return;
1377
1378         source_len = intel_dp_source_rates(intel_dp, &source_rates);
1379         snprintf_int_array(str, sizeof(str), source_rates, source_len);
1380         DRM_DEBUG_KMS("source rates: %s\n", str);
1381
1382         sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
1383         snprintf_int_array(str, sizeof(str), sink_rates, sink_len);
1384         DRM_DEBUG_KMS("sink rates: %s\n", str);
1385
1386         common_len = intel_dp_common_rates(intel_dp, common_rates);
1387         snprintf_int_array(str, sizeof(str), common_rates, common_len);
1388         DRM_DEBUG_KMS("common rates: %s\n", str);
1389 }
1390
1391 static int rate_to_index(int find, const int *rates)
1392 {
1393         int i = 0;
1394
1395         for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i)
1396                 if (find == rates[i])
1397                         break;
1398
1399         return i;
1400 }
1401
1402 int
1403 intel_dp_max_link_rate(struct intel_dp *intel_dp)
1404 {
1405         int rates[DP_MAX_SUPPORTED_RATES] = {};
1406         int len;
1407
1408         len = intel_dp_common_rates(intel_dp, rates);
1409         if (WARN_ON(len <= 0))
1410                 return 162000;
1411
1412         return rates[rate_to_index(0, rates) - 1];
1413 }
1414
1415 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1416 {
1417         return rate_to_index(rate, intel_dp->sink_rates);
1418 }
1419
1420 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1421                            uint8_t *link_bw, uint8_t *rate_select)
1422 {
1423         if (intel_dp->num_sink_rates) {
1424                 *link_bw = 0;
1425                 *rate_select =
1426                         intel_dp_rate_select(intel_dp, port_clock);
1427         } else {
1428                 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1429                 *rate_select = 0;
1430         }
1431 }
1432
1433 bool
1434 intel_dp_compute_config(struct intel_encoder *encoder,
1435                         struct intel_crtc_state *pipe_config)
1436 {
1437         struct drm_device *dev = encoder->base.dev;
1438         struct drm_i915_private *dev_priv = dev->dev_private;
1439         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1440         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1441         enum port port = dp_to_dig_port(intel_dp)->port;
1442         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
1443         struct intel_connector *intel_connector = intel_dp->attached_connector;
1444         int lane_count, clock;
1445         int min_lane_count = 1;
1446         int max_lane_count = intel_dp_max_lane_count(intel_dp);
1447         /* Conveniently, the link BW constants become indices with a shift...*/
1448         int min_clock = 0;
1449         int max_clock;
1450         int bpp, mode_rate;
1451         int link_avail, link_clock;
1452         int common_rates[DP_MAX_SUPPORTED_RATES] = {};
1453         int common_len;
1454         uint8_t link_bw, rate_select;
1455
1456         common_len = intel_dp_common_rates(intel_dp, common_rates);
1457
1458         /* No common link rates between source and sink */
1459         WARN_ON(common_len <= 0);
1460
1461         max_clock = common_len - 1;
1462
1463         if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
1464                 pipe_config->has_pch_encoder = true;
1465
1466         pipe_config->has_dp_encoder = true;
1467         pipe_config->has_drrs = false;
1468         pipe_config->has_audio = intel_dp->has_audio && port != PORT_A;
1469
1470         if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1471                 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1472                                        adjusted_mode);
1473
1474                 if (INTEL_INFO(dev)->gen >= 9) {
1475                         int ret;
1476                         ret = skl_update_scaler_crtc(pipe_config);
1477                         if (ret)
1478                                 return ret;
1479                 }
1480
1481                 if (HAS_GMCH_DISPLAY(dev))
1482                         intel_gmch_panel_fitting(intel_crtc, pipe_config,
1483                                                  intel_connector->panel.fitting_mode);
1484                 else
1485                         intel_pch_panel_fitting(intel_crtc, pipe_config,
1486                                                 intel_connector->panel.fitting_mode);
1487         }
1488
1489         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
1490                 return false;
1491
1492         DRM_DEBUG_KMS("DP link computation with max lane count %i "
1493                       "max bw %d pixel clock %iKHz\n",
1494                       max_lane_count, common_rates[max_clock],
1495                       adjusted_mode->crtc_clock);
1496
1497         /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1498          * bpc in between. */
1499         bpp = pipe_config->pipe_bpp;
1500         if (is_edp(intel_dp)) {
1501
1502                 /* Get bpp from vbt only for panels that dont have bpp in edid */
1503                 if (intel_connector->base.display_info.bpc == 0 &&
1504                         (dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp)) {
1505                         DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1506                                       dev_priv->vbt.edp.bpp);
1507                         bpp = dev_priv->vbt.edp.bpp;
1508                 }
1509
1510                 /*
1511                  * Use the maximum clock and number of lanes the eDP panel
1512                  * advertizes being capable of. The panels are generally
1513                  * designed to support only a single clock and lane
1514                  * configuration, and typically these values correspond to the
1515                  * native resolution of the panel.
1516                  */
1517                 min_lane_count = max_lane_count;
1518                 min_clock = max_clock;
1519         }
1520
1521         for (; bpp >= 6*3; bpp -= 2*3) {
1522                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1523                                                    bpp);
1524
1525                 for (clock = min_clock; clock <= max_clock; clock++) {
1526                         for (lane_count = min_lane_count;
1527                                 lane_count <= max_lane_count;
1528                                 lane_count <<= 1) {
1529
1530                                 link_clock = common_rates[clock];
1531                                 link_avail = intel_dp_max_data_rate(link_clock,
1532                                                                     lane_count);
1533
1534                                 if (mode_rate <= link_avail) {
1535                                         goto found;
1536                                 }
1537                         }
1538                 }
1539         }
1540
1541         return false;
1542
1543 found:
1544         if (intel_dp->color_range_auto) {
1545                 /*
1546                  * See:
1547                  * CEA-861-E - 5.1 Default Encoding Parameters
1548                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1549                  */
1550                 pipe_config->limited_color_range =
1551                         bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1;
1552         } else {
1553                 pipe_config->limited_color_range =
1554                         intel_dp->limited_color_range;
1555         }
1556
1557         pipe_config->lane_count = lane_count;
1558
1559         pipe_config->pipe_bpp = bpp;
1560         pipe_config->port_clock = common_rates[clock];
1561
1562         intel_dp_compute_rate(intel_dp, pipe_config->port_clock,
1563                               &link_bw, &rate_select);
1564
1565         DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n",
1566                       link_bw, rate_select, pipe_config->lane_count,
1567                       pipe_config->port_clock, bpp);
1568         DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1569                       mode_rate, link_avail);
1570
1571         intel_link_compute_m_n(bpp, lane_count,
1572                                adjusted_mode->crtc_clock,
1573                                pipe_config->port_clock,
1574                                &pipe_config->dp_m_n);
1575
1576         if (intel_connector->panel.downclock_mode != NULL &&
1577                 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
1578                         pipe_config->has_drrs = true;
1579                         intel_link_compute_m_n(bpp, lane_count,
1580                                 intel_connector->panel.downclock_mode->clock,
1581                                 pipe_config->port_clock,
1582                                 &pipe_config->dp_m2_n2);
1583         }
1584
1585         if (!HAS_DDI(dev))
1586                 intel_dp_set_clock(encoder, pipe_config);
1587
1588         return true;
1589 }
1590
1591 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1592                               const struct intel_crtc_state *pipe_config)
1593 {
1594         intel_dp->link_rate = pipe_config->port_clock;
1595         intel_dp->lane_count = pipe_config->lane_count;
1596 }
1597
1598 static void intel_dp_prepare(struct intel_encoder *encoder)
1599 {
1600         struct drm_device *dev = encoder->base.dev;
1601         struct drm_i915_private *dev_priv = dev->dev_private;
1602         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1603         enum port port = dp_to_dig_port(intel_dp)->port;
1604         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1605         const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
1606
1607         intel_dp_set_link_params(intel_dp, crtc->config);
1608
1609         /*
1610          * There are four kinds of DP registers:
1611          *
1612          *      IBX PCH
1613          *      SNB CPU
1614          *      IVB CPU
1615          *      CPT PCH
1616          *
1617          * IBX PCH and CPU are the same for almost everything,
1618          * except that the CPU DP PLL is configured in this
1619          * register
1620          *
1621          * CPT PCH is quite different, having many bits moved
1622          * to the TRANS_DP_CTL register instead. That
1623          * configuration happens (oddly) in ironlake_pch_enable
1624          */
1625
1626         /* Preserve the BIOS-computed detected bit. This is
1627          * supposed to be read-only.
1628          */
1629         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
1630
1631         /* Handle DP bits in common between all three register formats */
1632         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
1633         intel_dp->DP |= DP_PORT_WIDTH(crtc->config->lane_count);
1634
1635         /* Split out the IBX/CPU vs CPT settings */
1636
1637         if (IS_GEN7(dev) && port == PORT_A) {
1638                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1639                         intel_dp->DP |= DP_SYNC_HS_HIGH;
1640                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1641                         intel_dp->DP |= DP_SYNC_VS_HIGH;
1642                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1643
1644                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1645                         intel_dp->DP |= DP_ENHANCED_FRAMING;
1646
1647                 intel_dp->DP |= crtc->pipe << 29;
1648         } else if (HAS_PCH_CPT(dev) && port != PORT_A) {
1649                 u32 trans_dp;
1650
1651                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1652
1653                 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1654                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1655                         trans_dp |= TRANS_DP_ENH_FRAMING;
1656                 else
1657                         trans_dp &= ~TRANS_DP_ENH_FRAMING;
1658                 I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
1659         } else {
1660                 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
1661                     !IS_CHERRYVIEW(dev) && crtc->config->limited_color_range)
1662                         intel_dp->DP |= DP_COLOR_RANGE_16_235;
1663
1664                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1665                         intel_dp->DP |= DP_SYNC_HS_HIGH;
1666                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1667                         intel_dp->DP |= DP_SYNC_VS_HIGH;
1668                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1669
1670                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1671                         intel_dp->DP |= DP_ENHANCED_FRAMING;
1672
1673                 if (IS_CHERRYVIEW(dev))
1674                         intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1675                 else if (crtc->pipe == PIPE_B)
1676                         intel_dp->DP |= DP_PIPEB_SELECT;
1677         }
1678 }
1679
1680 #define IDLE_ON_MASK            (PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
1681 #define IDLE_ON_VALUE           (PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
1682
1683 #define IDLE_OFF_MASK           (PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
1684 #define IDLE_OFF_VALUE          (0     | PP_SEQUENCE_NONE | 0                     | 0)
1685
1686 #define IDLE_CYCLE_MASK         (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1687 #define IDLE_CYCLE_VALUE        (0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
1688
1689 static void wait_panel_status(struct intel_dp *intel_dp,
1690                                        u32 mask,
1691                                        u32 value)
1692 {
1693         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1694         struct drm_i915_private *dev_priv = dev->dev_private;
1695         i915_reg_t pp_stat_reg, pp_ctrl_reg;
1696
1697         lockdep_assert_held(&dev_priv->pps_mutex);
1698
1699         pp_stat_reg = _pp_stat_reg(intel_dp);
1700         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1701
1702         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1703                         mask, value,
1704                         I915_READ(pp_stat_reg),
1705                         I915_READ(pp_ctrl_reg));
1706
1707         if (_wait_for((I915_READ(pp_stat_reg) & mask) == value,
1708                       5 * USEC_PER_SEC, 10 * USEC_PER_MSEC))
1709                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1710                                 I915_READ(pp_stat_reg),
1711                                 I915_READ(pp_ctrl_reg));
1712
1713         DRM_DEBUG_KMS("Wait complete\n");
1714 }
1715
1716 static void wait_panel_on(struct intel_dp *intel_dp)
1717 {
1718         DRM_DEBUG_KMS("Wait for panel power on\n");
1719         wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1720 }
1721
1722 static void wait_panel_off(struct intel_dp *intel_dp)
1723 {
1724         DRM_DEBUG_KMS("Wait for panel power off time\n");
1725         wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1726 }
1727
1728 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
1729 {
1730         ktime_t panel_power_on_time;
1731         s64 panel_power_off_duration;
1732
1733         DRM_DEBUG_KMS("Wait for panel power cycle\n");
1734
1735         /* take the difference of currrent time and panel power off time
1736          * and then make panel wait for t11_t12 if needed. */
1737         panel_power_on_time = ktime_get_boottime();
1738         panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
1739
1740         /* When we disable the VDD override bit last we have to do the manual
1741          * wait. */
1742         if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
1743                 wait_remaining_ms_from_jiffies(jiffies,
1744                                        intel_dp->panel_power_cycle_delay - panel_power_off_duration);
1745
1746         wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1747 }
1748
1749 static void wait_backlight_on(struct intel_dp *intel_dp)
1750 {
1751         wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1752                                        intel_dp->backlight_on_delay);
1753 }
1754
1755 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
1756 {
1757         wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1758                                        intel_dp->backlight_off_delay);
1759 }
1760
1761 /* Read the current pp_control value, unlocking the register if it
1762  * is locked
1763  */
1764
1765 static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
1766 {
1767         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1768         struct drm_i915_private *dev_priv = dev->dev_private;
1769         u32 control;
1770
1771         lockdep_assert_held(&dev_priv->pps_mutex);
1772
1773         control = I915_READ(_pp_ctrl_reg(intel_dp));
1774         if (!IS_BROXTON(dev)) {
1775                 control &= ~PANEL_UNLOCK_MASK;
1776                 control |= PANEL_UNLOCK_REGS;
1777         }
1778         return control;
1779 }
1780
1781 /*
1782  * Must be paired with edp_panel_vdd_off().
1783  * Must hold pps_mutex around the whole on/off sequence.
1784  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1785  */
1786 static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
1787 {
1788         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1789         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1790         struct intel_encoder *intel_encoder = &intel_dig_port->base;
1791         struct drm_i915_private *dev_priv = dev->dev_private;
1792         enum intel_display_power_domain power_domain;
1793         u32 pp;
1794         i915_reg_t pp_stat_reg, pp_ctrl_reg;
1795         bool need_to_disable = !intel_dp->want_panel_vdd;
1796
1797         lockdep_assert_held(&dev_priv->pps_mutex);
1798
1799         if (!is_edp(intel_dp))
1800                 return false;
1801
1802         cancel_delayed_work(&intel_dp->panel_vdd_work);
1803         intel_dp->want_panel_vdd = true;
1804
1805         if (edp_have_panel_vdd(intel_dp))
1806                 return need_to_disable;
1807
1808         power_domain = intel_display_port_aux_power_domain(intel_encoder);
1809         intel_display_power_get(dev_priv, power_domain);
1810
1811         DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
1812                       port_name(intel_dig_port->port));
1813
1814         if (!edp_have_panel_power(intel_dp))
1815                 wait_panel_power_cycle(intel_dp);
1816
1817         pp = ironlake_get_pp_control(intel_dp);
1818         pp |= EDP_FORCE_VDD;
1819
1820         pp_stat_reg = _pp_stat_reg(intel_dp);
1821         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1822
1823         I915_WRITE(pp_ctrl_reg, pp);
1824         POSTING_READ(pp_ctrl_reg);
1825         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1826                         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1827         /*
1828          * If the panel wasn't on, delay before accessing aux channel
1829          */
1830         if (!edp_have_panel_power(intel_dp)) {
1831                 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
1832                               port_name(intel_dig_port->port));
1833                 msleep(intel_dp->panel_power_up_delay);
1834         }
1835
1836         return need_to_disable;
1837 }
1838
1839 /*
1840  * Must be paired with intel_edp_panel_vdd_off() or
1841  * intel_edp_panel_off().
1842  * Nested calls to these functions are not allowed since
1843  * we drop the lock. Caller must use some higher level
1844  * locking to prevent nested calls from other threads.
1845  */
1846 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
1847 {
1848         bool vdd;
1849
1850         if (!is_edp(intel_dp))
1851                 return;
1852
1853         pps_lock(intel_dp);
1854         vdd = edp_panel_vdd_on(intel_dp);
1855         pps_unlock(intel_dp);
1856
1857         I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
1858              port_name(dp_to_dig_port(intel_dp)->port));
1859 }
1860
1861 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
1862 {
1863         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1864         struct drm_i915_private *dev_priv = dev->dev_private;
1865         struct intel_digital_port *intel_dig_port =
1866                 dp_to_dig_port(intel_dp);
1867         struct intel_encoder *intel_encoder = &intel_dig_port->base;
1868         enum intel_display_power_domain power_domain;
1869         u32 pp;
1870         i915_reg_t pp_stat_reg, pp_ctrl_reg;
1871
1872         lockdep_assert_held(&dev_priv->pps_mutex);
1873
1874         WARN_ON(intel_dp->want_panel_vdd);
1875
1876         if (!edp_have_panel_vdd(intel_dp))
1877                 return;
1878
1879         DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
1880                       port_name(intel_dig_port->port));
1881
1882         pp = ironlake_get_pp_control(intel_dp);
1883         pp &= ~EDP_FORCE_VDD;
1884
1885         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1886         pp_stat_reg = _pp_stat_reg(intel_dp);
1887
1888         I915_WRITE(pp_ctrl_reg, pp);
1889         POSTING_READ(pp_ctrl_reg);
1890
1891         /* Make sure sequencer is idle before allowing subsequent activity */
1892         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1893         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1894
1895         if ((pp & POWER_TARGET_ON) == 0)
1896                 intel_dp->panel_power_off_time = ktime_get_boottime();
1897
1898         power_domain = intel_display_port_aux_power_domain(intel_encoder);
1899         intel_display_power_put(dev_priv, power_domain);
1900 }
1901
1902 static void edp_panel_vdd_work(struct work_struct *__work)
1903 {
1904         struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1905                                                  struct intel_dp, panel_vdd_work);
1906
1907         pps_lock(intel_dp);
1908         if (!intel_dp->want_panel_vdd)
1909                 edp_panel_vdd_off_sync(intel_dp);
1910         pps_unlock(intel_dp);
1911 }
1912
1913 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
1914 {
1915         unsigned long delay;
1916
1917         /*
1918          * Queue the timer to fire a long time from now (relative to the power
1919          * down delay) to keep the panel power up across a sequence of
1920          * operations.
1921          */
1922         delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
1923         schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
1924 }
1925
1926 /*
1927  * Must be paired with edp_panel_vdd_on().
1928  * Must hold pps_mutex around the whole on/off sequence.
1929  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1930  */
1931 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1932 {
1933         struct drm_i915_private *dev_priv =
1934                 intel_dp_to_dev(intel_dp)->dev_private;
1935
1936         lockdep_assert_held(&dev_priv->pps_mutex);
1937
1938         if (!is_edp(intel_dp))
1939                 return;
1940
1941         I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
1942              port_name(dp_to_dig_port(intel_dp)->port));
1943
1944         intel_dp->want_panel_vdd = false;
1945
1946         if (sync)
1947                 edp_panel_vdd_off_sync(intel_dp);
1948         else
1949                 edp_panel_vdd_schedule_off(intel_dp);
1950 }
1951
1952 static void edp_panel_on(struct intel_dp *intel_dp)
1953 {
1954         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1955         struct drm_i915_private *dev_priv = dev->dev_private;
1956         u32 pp;
1957         i915_reg_t pp_ctrl_reg;
1958
1959         lockdep_assert_held(&dev_priv->pps_mutex);
1960
1961         if (!is_edp(intel_dp))
1962                 return;
1963
1964         DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
1965                       port_name(dp_to_dig_port(intel_dp)->port));
1966
1967         if (WARN(edp_have_panel_power(intel_dp),
1968                  "eDP port %c panel power already on\n",
1969                  port_name(dp_to_dig_port(intel_dp)->port)))
1970                 return;
1971
1972         wait_panel_power_cycle(intel_dp);
1973
1974         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1975         pp = ironlake_get_pp_control(intel_dp);
1976         if (IS_GEN5(dev)) {
1977                 /* ILK workaround: disable reset around power sequence */
1978                 pp &= ~PANEL_POWER_RESET;
1979                 I915_WRITE(pp_ctrl_reg, pp);
1980                 POSTING_READ(pp_ctrl_reg);
1981         }
1982
1983         pp |= POWER_TARGET_ON;
1984         if (!IS_GEN5(dev))
1985                 pp |= PANEL_POWER_RESET;
1986
1987         I915_WRITE(pp_ctrl_reg, pp);
1988         POSTING_READ(pp_ctrl_reg);
1989
1990         wait_panel_on(intel_dp);
1991         intel_dp->last_power_on = jiffies;
1992
1993         if (IS_GEN5(dev)) {
1994                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1995                 I915_WRITE(pp_ctrl_reg, pp);
1996                 POSTING_READ(pp_ctrl_reg);
1997         }
1998 }
1999
2000 void intel_edp_panel_on(struct intel_dp *intel_dp)
2001 {
2002         if (!is_edp(intel_dp))
2003                 return;
2004
2005         pps_lock(intel_dp);
2006         edp_panel_on(intel_dp);
2007         pps_unlock(intel_dp);
2008 }
2009
2010
2011 static void edp_panel_off(struct intel_dp *intel_dp)
2012 {
2013         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2014         struct intel_encoder *intel_encoder = &intel_dig_port->base;
2015         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2016         struct drm_i915_private *dev_priv = dev->dev_private;
2017         enum intel_display_power_domain power_domain;
2018         u32 pp;
2019         i915_reg_t pp_ctrl_reg;
2020
2021         lockdep_assert_held(&dev_priv->pps_mutex);
2022
2023         if (!is_edp(intel_dp))
2024                 return;
2025
2026         DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2027                       port_name(dp_to_dig_port(intel_dp)->port));
2028
2029         WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
2030              port_name(dp_to_dig_port(intel_dp)->port));
2031
2032         pp = ironlake_get_pp_control(intel_dp);
2033         /* We need to switch off panel power _and_ force vdd, for otherwise some
2034          * panels get very unhappy and cease to work. */
2035         pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
2036                 EDP_BLC_ENABLE);
2037
2038         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2039
2040         intel_dp->want_panel_vdd = false;
2041
2042         I915_WRITE(pp_ctrl_reg, pp);
2043         POSTING_READ(pp_ctrl_reg);
2044
2045         intel_dp->panel_power_off_time = ktime_get_boottime();
2046         wait_panel_off(intel_dp);
2047
2048         /* We got a reference when we enabled the VDD. */
2049         power_domain = intel_display_port_aux_power_domain(intel_encoder);
2050         intel_display_power_put(dev_priv, power_domain);
2051 }
2052
2053 void intel_edp_panel_off(struct intel_dp *intel_dp)
2054 {
2055         if (!is_edp(intel_dp))
2056                 return;
2057
2058         pps_lock(intel_dp);
2059         edp_panel_off(intel_dp);
2060         pps_unlock(intel_dp);
2061 }
2062
2063 /* Enable backlight in the panel power control. */
2064 static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
2065 {
2066         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2067         struct drm_device *dev = intel_dig_port->base.base.dev;
2068         struct drm_i915_private *dev_priv = dev->dev_private;
2069         u32 pp;
2070         i915_reg_t pp_ctrl_reg;
2071
2072         /*
2073          * If we enable the backlight right away following a panel power
2074          * on, we may see slight flicker as the panel syncs with the eDP
2075          * link.  So delay a bit to make sure the image is solid before
2076          * allowing it to appear.
2077          */
2078         wait_backlight_on(intel_dp);
2079
2080         pps_lock(intel_dp);
2081
2082         pp = ironlake_get_pp_control(intel_dp);
2083         pp |= EDP_BLC_ENABLE;
2084
2085         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2086
2087         I915_WRITE(pp_ctrl_reg, pp);
2088         POSTING_READ(pp_ctrl_reg);
2089
2090         pps_unlock(intel_dp);
2091 }
2092
2093 /* Enable backlight PWM and backlight PP control. */
2094 void intel_edp_backlight_on(struct intel_dp *intel_dp)
2095 {
2096         if (!is_edp(intel_dp))
2097                 return;
2098
2099         DRM_DEBUG_KMS("\n");
2100
2101         intel_panel_enable_backlight(intel_dp->attached_connector);
2102         _intel_edp_backlight_on(intel_dp);
2103 }
2104
2105 /* Disable backlight in the panel power control. */
2106 static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
2107 {
2108         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2109         struct drm_i915_private *dev_priv = dev->dev_private;
2110         u32 pp;
2111         i915_reg_t pp_ctrl_reg;
2112
2113         if (!is_edp(intel_dp))
2114                 return;
2115
2116         pps_lock(intel_dp);
2117
2118         pp = ironlake_get_pp_control(intel_dp);
2119         pp &= ~EDP_BLC_ENABLE;
2120
2121         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2122
2123         I915_WRITE(pp_ctrl_reg, pp);
2124         POSTING_READ(pp_ctrl_reg);
2125
2126         pps_unlock(intel_dp);
2127
2128         intel_dp->last_backlight_off = jiffies;
2129         edp_wait_backlight_off(intel_dp);
2130 }
2131
2132 /* Disable backlight PP control and backlight PWM. */
2133 void intel_edp_backlight_off(struct intel_dp *intel_dp)
2134 {
2135         if (!is_edp(intel_dp))
2136                 return;
2137
2138         DRM_DEBUG_KMS("\n");
2139
2140         _intel_edp_backlight_off(intel_dp);
2141         intel_panel_disable_backlight(intel_dp->attached_connector);
2142 }
2143
2144 /*
2145  * Hook for controlling the panel power control backlight through the bl_power
2146  * sysfs attribute. Take care to handle multiple calls.
2147  */
2148 static void intel_edp_backlight_power(struct intel_connector *connector,
2149                                       bool enable)
2150 {
2151         struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
2152         bool is_enabled;
2153
2154         pps_lock(intel_dp);
2155         is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
2156         pps_unlock(intel_dp);
2157
2158         if (is_enabled == enable)
2159                 return;
2160
2161         DRM_DEBUG_KMS("panel power control backlight %s\n",
2162                       enable ? "enable" : "disable");
2163
2164         if (enable)
2165                 _intel_edp_backlight_on(intel_dp);
2166         else
2167                 _intel_edp_backlight_off(intel_dp);
2168 }
2169
2170 static void assert_dp_port(struct intel_dp *intel_dp, bool state)
2171 {
2172         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2173         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2174         bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN;
2175
2176         I915_STATE_WARN(cur_state != state,
2177                         "DP port %c state assertion failure (expected %s, current %s)\n",
2178                         port_name(dig_port->port),
2179                         onoff(state), onoff(cur_state));
2180 }
2181 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
2182
2183 static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
2184 {
2185         bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE;
2186
2187         I915_STATE_WARN(cur_state != state,
2188                         "eDP PLL state assertion failure (expected %s, current %s)\n",
2189                         onoff(state), onoff(cur_state));
2190 }
2191 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2192 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2193
2194 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
2195 {
2196         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2197         struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
2198         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2199
2200         assert_pipe_disabled(dev_priv, crtc->pipe);
2201         assert_dp_port_disabled(intel_dp);
2202         assert_edp_pll_disabled(dev_priv);
2203
2204         DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
2205                       crtc->config->port_clock);
2206
2207         intel_dp->DP &= ~DP_PLL_FREQ_MASK;
2208
2209         if (crtc->config->port_clock == 162000)
2210                 intel_dp->DP |= DP_PLL_FREQ_162MHZ;
2211         else
2212                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
2213
2214         I915_WRITE(DP_A, intel_dp->DP);
2215         POSTING_READ(DP_A);
2216         udelay(500);
2217
2218         /*
2219          * [DevILK] Work around required when enabling DP PLL
2220          * while a pipe is enabled going to FDI:
2221          * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
2222          * 2. Program DP PLL enable
2223          */
2224         if (IS_GEN5(dev_priv))
2225                 intel_wait_for_vblank_if_active(dev_priv->dev, !crtc->pipe);
2226
2227         intel_dp->DP |= DP_PLL_ENABLE;
2228
2229         I915_WRITE(DP_A, intel_dp->DP);
2230         POSTING_READ(DP_A);
2231         udelay(200);
2232 }
2233
2234 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
2235 {
2236         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2237         struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
2238         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2239
2240         assert_pipe_disabled(dev_priv, crtc->pipe);
2241         assert_dp_port_disabled(intel_dp);
2242         assert_edp_pll_enabled(dev_priv);
2243
2244         DRM_DEBUG_KMS("disabling eDP PLL\n");
2245
2246         intel_dp->DP &= ~DP_PLL_ENABLE;
2247
2248         I915_WRITE(DP_A, intel_dp->DP);
2249         POSTING_READ(DP_A);
2250         udelay(200);
2251 }
2252
2253 /* If the sink supports it, try to set the power state appropriately */
2254 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
2255 {
2256         int ret, i;
2257
2258         /* Should have a valid DPCD by this point */
2259         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2260                 return;
2261
2262         if (mode != DRM_MODE_DPMS_ON) {
2263                 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2264                                          DP_SET_POWER_D3);
2265         } else {
2266                 /*
2267                  * When turning on, we need to retry for 1ms to give the sink
2268                  * time to wake up.
2269                  */
2270                 for (i = 0; i < 3; i++) {
2271                         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2272                                                  DP_SET_POWER_D0);
2273                         if (ret == 1)
2274                                 break;
2275                         msleep(1);
2276                 }
2277         }
2278
2279         if (ret != 1)
2280                 DRM_DEBUG_KMS("failed to %s sink power state\n",
2281                               mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
2282 }
2283
2284 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
2285                                   enum pipe *pipe)
2286 {
2287         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2288         enum port port = dp_to_dig_port(intel_dp)->port;
2289         struct drm_device *dev = encoder->base.dev;
2290         struct drm_i915_private *dev_priv = dev->dev_private;
2291         enum intel_display_power_domain power_domain;
2292         u32 tmp;
2293         bool ret;
2294
2295         power_domain = intel_display_port_power_domain(encoder);
2296         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
2297                 return false;
2298
2299         ret = false;
2300
2301         tmp = I915_READ(intel_dp->output_reg);
2302
2303         if (!(tmp & DP_PORT_EN))
2304                 goto out;
2305
2306         if (IS_GEN7(dev) && port == PORT_A) {
2307                 *pipe = PORT_TO_PIPE_CPT(tmp);
2308         } else if (HAS_PCH_CPT(dev) && port != PORT_A) {
2309                 enum pipe p;
2310
2311                 for_each_pipe(dev_priv, p) {
2312                         u32 trans_dp = I915_READ(TRANS_DP_CTL(p));
2313                         if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) {
2314                                 *pipe = p;
2315                                 ret = true;
2316
2317                                 goto out;
2318                         }
2319                 }
2320
2321                 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
2322                               i915_mmio_reg_offset(intel_dp->output_reg));
2323         } else if (IS_CHERRYVIEW(dev)) {
2324                 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
2325         } else {
2326                 *pipe = PORT_TO_PIPE(tmp);
2327         }
2328
2329         ret = true;
2330
2331 out:
2332         intel_display_power_put(dev_priv, power_domain);
2333
2334         return ret;
2335 }
2336
2337 static void intel_dp_get_config(struct intel_encoder *encoder,
2338                                 struct intel_crtc_state *pipe_config)
2339 {
2340         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2341         u32 tmp, flags = 0;
2342         struct drm_device *dev = encoder->base.dev;
2343         struct drm_i915_private *dev_priv = dev->dev_private;
2344         enum port port = dp_to_dig_port(intel_dp)->port;
2345         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2346
2347         tmp = I915_READ(intel_dp->output_reg);
2348
2349         pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
2350
2351         if (HAS_PCH_CPT(dev) && port != PORT_A) {
2352                 u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2353
2354                 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
2355                         flags |= DRM_MODE_FLAG_PHSYNC;
2356                 else
2357                         flags |= DRM_MODE_FLAG_NHSYNC;
2358
2359                 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
2360                         flags |= DRM_MODE_FLAG_PVSYNC;
2361                 else
2362                         flags |= DRM_MODE_FLAG_NVSYNC;
2363         } else {
2364                 if (tmp & DP_SYNC_HS_HIGH)
2365                         flags |= DRM_MODE_FLAG_PHSYNC;
2366                 else
2367                         flags |= DRM_MODE_FLAG_NHSYNC;
2368
2369                 if (tmp & DP_SYNC_VS_HIGH)
2370                         flags |= DRM_MODE_FLAG_PVSYNC;
2371                 else
2372                         flags |= DRM_MODE_FLAG_NVSYNC;
2373         }
2374
2375         pipe_config->base.adjusted_mode.flags |= flags;
2376
2377         if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
2378             !IS_CHERRYVIEW(dev) && tmp & DP_COLOR_RANGE_16_235)
2379                 pipe_config->limited_color_range = true;
2380
2381         pipe_config->has_dp_encoder = true;
2382
2383         pipe_config->lane_count =
2384                 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
2385
2386         intel_dp_get_m_n(crtc, pipe_config);
2387
2388         if (port == PORT_A) {
2389                 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
2390                         pipe_config->port_clock = 162000;
2391                 else
2392                         pipe_config->port_clock = 270000;
2393         }
2394
2395         pipe_config->base.adjusted_mode.crtc_clock =
2396                 intel_dotclock_calculate(pipe_config->port_clock,
2397                                          &pipe_config->dp_m_n);
2398
2399         if (is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
2400             pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
2401                 /*
2402                  * This is a big fat ugly hack.
2403                  *
2404                  * Some machines in UEFI boot mode provide us a VBT that has 18
2405                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2406                  * unknown we fail to light up. Yet the same BIOS boots up with
2407                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2408                  * max, not what it tells us to use.
2409                  *
2410                  * Note: This will still be broken if the eDP panel is not lit
2411                  * up by the BIOS, and thus we can't get the mode at module
2412                  * load.
2413                  */
2414                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2415                               pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
2416                 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
2417         }
2418 }
2419
2420 static void intel_disable_dp(struct intel_encoder *encoder)
2421 {
2422         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2423         struct drm_device *dev = encoder->base.dev;
2424         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2425
2426         if (crtc->config->has_audio)
2427                 intel_audio_codec_disable(encoder);
2428
2429         if (HAS_PSR(dev) && !HAS_DDI(dev))
2430                 intel_psr_disable(intel_dp);
2431
2432         /* Make sure the panel is off before trying to change the mode. But also
2433          * ensure that we have vdd while we switch off the panel. */
2434         intel_edp_panel_vdd_on(intel_dp);
2435         intel_edp_backlight_off(intel_dp);
2436         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2437         intel_edp_panel_off(intel_dp);
2438
2439         /* disable the port before the pipe on g4x */
2440         if (INTEL_INFO(dev)->gen < 5)
2441                 intel_dp_link_down(intel_dp);
2442 }
2443
2444 static void ilk_post_disable_dp(struct intel_encoder *encoder)
2445 {
2446         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2447         enum port port = dp_to_dig_port(intel_dp)->port;
2448
2449         intel_dp_link_down(intel_dp);
2450
2451         /* Only ilk+ has port A */
2452         if (port == PORT_A)
2453                 ironlake_edp_pll_off(intel_dp);
2454 }
2455
2456 static void vlv_post_disable_dp(struct intel_encoder *encoder)
2457 {
2458         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2459
2460         intel_dp_link_down(intel_dp);
2461 }
2462
2463 static void chv_data_lane_soft_reset(struct intel_encoder *encoder,
2464                                      bool reset)
2465 {
2466         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2467         enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
2468         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2469         enum pipe pipe = crtc->pipe;
2470         uint32_t val;
2471
2472         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2473         if (reset)
2474                 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2475         else
2476                 val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
2477         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2478
2479         if (crtc->config->lane_count > 2) {
2480                 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
2481                 if (reset)
2482                         val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2483                 else
2484                         val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
2485                 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
2486         }
2487
2488         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
2489         val |= CHV_PCS_REQ_SOFTRESET_EN;
2490         if (reset)
2491                 val &= ~DPIO_PCS_CLK_SOFT_RESET;
2492         else
2493                 val |= DPIO_PCS_CLK_SOFT_RESET;
2494         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2495
2496         if (crtc->config->lane_count > 2) {
2497                 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2498                 val |= CHV_PCS_REQ_SOFTRESET_EN;
2499                 if (reset)
2500                         val &= ~DPIO_PCS_CLK_SOFT_RESET;
2501                 else
2502                         val |= DPIO_PCS_CLK_SOFT_RESET;
2503                 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2504         }
2505 }
2506
2507 static void chv_post_disable_dp(struct intel_encoder *encoder)
2508 {
2509         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2510         struct drm_device *dev = encoder->base.dev;
2511         struct drm_i915_private *dev_priv = dev->dev_private;
2512
2513         intel_dp_link_down(intel_dp);
2514
2515         mutex_lock(&dev_priv->sb_lock);
2516
2517         /* Assert data lane reset */
2518         chv_data_lane_soft_reset(encoder, true);
2519
2520         mutex_unlock(&dev_priv->sb_lock);
2521 }
2522
2523 static void
2524 _intel_dp_set_link_train(struct intel_dp *intel_dp,
2525                          uint32_t *DP,
2526                          uint8_t dp_train_pat)
2527 {
2528         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2529         struct drm_device *dev = intel_dig_port->base.base.dev;
2530         struct drm_i915_private *dev_priv = dev->dev_private;
2531         enum port port = intel_dig_port->port;
2532
2533         if (HAS_DDI(dev)) {
2534                 uint32_t temp = I915_READ(DP_TP_CTL(port));
2535
2536                 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2537                         temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2538                 else
2539                         temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2540
2541                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2542                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2543                 case DP_TRAINING_PATTERN_DISABLE:
2544                         temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2545
2546                         break;
2547                 case DP_TRAINING_PATTERN_1:
2548                         temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2549                         break;
2550                 case DP_TRAINING_PATTERN_2:
2551                         temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2552                         break;
2553                 case DP_TRAINING_PATTERN_3:
2554                         temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2555                         break;
2556                 }
2557                 I915_WRITE(DP_TP_CTL(port), temp);
2558
2559         } else if ((IS_GEN7(dev) && port == PORT_A) ||
2560                    (HAS_PCH_CPT(dev) && port != PORT_A)) {
2561                 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2562
2563                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2564                 case DP_TRAINING_PATTERN_DISABLE:
2565                         *DP |= DP_LINK_TRAIN_OFF_CPT;
2566                         break;
2567                 case DP_TRAINING_PATTERN_1:
2568                         *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2569                         break;
2570                 case DP_TRAINING_PATTERN_2:
2571                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2572                         break;
2573                 case DP_TRAINING_PATTERN_3:
2574                         DRM_ERROR("DP training pattern 3 not supported\n");
2575                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2576                         break;
2577                 }
2578
2579         } else {
2580                 if (IS_CHERRYVIEW(dev))
2581                         *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2582                 else
2583                         *DP &= ~DP_LINK_TRAIN_MASK;
2584
2585                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2586                 case DP_TRAINING_PATTERN_DISABLE:
2587                         *DP |= DP_LINK_TRAIN_OFF;
2588                         break;
2589                 case DP_TRAINING_PATTERN_1:
2590                         *DP |= DP_LINK_TRAIN_PAT_1;
2591                         break;
2592                 case DP_TRAINING_PATTERN_2:
2593                         *DP |= DP_LINK_TRAIN_PAT_2;
2594                         break;
2595                 case DP_TRAINING_PATTERN_3:
2596                         if (IS_CHERRYVIEW(dev)) {
2597                                 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2598                         } else {
2599                                 DRM_ERROR("DP training pattern 3 not supported\n");
2600                                 *DP |= DP_LINK_TRAIN_PAT_2;
2601                         }
2602                         break;
2603                 }
2604         }
2605 }
2606
2607 static void intel_dp_enable_port(struct intel_dp *intel_dp)
2608 {
2609         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2610         struct drm_i915_private *dev_priv = dev->dev_private;
2611         struct intel_crtc *crtc =
2612                 to_intel_crtc(dp_to_dig_port(intel_dp)->base.base.crtc);
2613
2614         /* enable with pattern 1 (as per spec) */
2615         _intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2616                                  DP_TRAINING_PATTERN_1);
2617
2618         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2619         POSTING_READ(intel_dp->output_reg);
2620
2621         /*
2622          * Magic for VLV/CHV. We _must_ first set up the register
2623          * without actually enabling the port, and then do another
2624          * write to enable the port. Otherwise link training will
2625          * fail when the power sequencer is freshly used for this port.
2626          */
2627         intel_dp->DP |= DP_PORT_EN;
2628         if (crtc->config->has_audio)
2629                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
2630
2631         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2632         POSTING_READ(intel_dp->output_reg);
2633 }
2634
2635 static void intel_enable_dp(struct intel_encoder *encoder)
2636 {
2637         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2638         struct drm_device *dev = encoder->base.dev;
2639         struct drm_i915_private *dev_priv = dev->dev_private;
2640         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2641         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
2642         enum pipe pipe = crtc->pipe;
2643
2644         if (WARN_ON(dp_reg & DP_PORT_EN))
2645                 return;
2646
2647         pps_lock(intel_dp);
2648
2649         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
2650                 vlv_init_panel_power_sequencer(intel_dp);
2651
2652         intel_dp_enable_port(intel_dp);
2653
2654         edp_panel_vdd_on(intel_dp);
2655         edp_panel_on(intel_dp);
2656         edp_panel_vdd_off(intel_dp, true);
2657
2658         pps_unlock(intel_dp);
2659
2660         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
2661                 unsigned int lane_mask = 0x0;
2662
2663                 if (IS_CHERRYVIEW(dev))
2664                         lane_mask = intel_dp_unused_lane_mask(crtc->config->lane_count);
2665
2666                 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
2667                                     lane_mask);
2668         }
2669
2670         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2671         intel_dp_start_link_train(intel_dp);
2672         intel_dp_stop_link_train(intel_dp);
2673
2674         if (crtc->config->has_audio) {
2675                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
2676                                  pipe_name(pipe));
2677                 intel_audio_codec_enable(encoder);
2678         }
2679 }
2680
2681 static void g4x_enable_dp(struct intel_encoder *encoder)
2682 {
2683         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2684
2685         intel_enable_dp(encoder);
2686         intel_edp_backlight_on(intel_dp);
2687 }
2688
2689 static void vlv_enable_dp(struct intel_encoder *encoder)
2690 {
2691         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2692
2693         intel_edp_backlight_on(intel_dp);
2694         intel_psr_enable(intel_dp);
2695 }
2696
2697 static void g4x_pre_enable_dp(struct intel_encoder *encoder)
2698 {
2699         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2700         enum port port = dp_to_dig_port(intel_dp)->port;
2701
2702         intel_dp_prepare(encoder);
2703
2704         /* Only ilk+ has port A */
2705         if (port == PORT_A)
2706                 ironlake_edp_pll_on(intel_dp);
2707 }
2708
2709 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
2710 {
2711         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2712         struct drm_i915_private *dev_priv = intel_dig_port->base.base.dev->dev_private;
2713         enum pipe pipe = intel_dp->pps_pipe;
2714         i915_reg_t pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
2715
2716         edp_panel_vdd_off_sync(intel_dp);
2717
2718         /*
2719          * VLV seems to get confused when multiple power seqeuencers
2720          * have the same port selected (even if only one has power/vdd
2721          * enabled). The failure manifests as vlv_wait_port_ready() failing
2722          * CHV on the other hand doesn't seem to mind having the same port
2723          * selected in multiple power seqeuencers, but let's clear the
2724          * port select always when logically disconnecting a power sequencer
2725          * from a port.
2726          */
2727         DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2728                       pipe_name(pipe), port_name(intel_dig_port->port));
2729         I915_WRITE(pp_on_reg, 0);
2730         POSTING_READ(pp_on_reg);
2731
2732         intel_dp->pps_pipe = INVALID_PIPE;
2733 }
2734
2735 static void vlv_steal_power_sequencer(struct drm_device *dev,
2736                                       enum pipe pipe)
2737 {
2738         struct drm_i915_private *dev_priv = dev->dev_private;
2739         struct intel_encoder *encoder;
2740
2741         lockdep_assert_held(&dev_priv->pps_mutex);
2742
2743         if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
2744                 return;
2745
2746         for_each_intel_encoder(dev, encoder) {
2747                 struct intel_dp *intel_dp;
2748                 enum port port;
2749
2750                 if (encoder->type != INTEL_OUTPUT_EDP)
2751                         continue;
2752
2753                 intel_dp = enc_to_intel_dp(&encoder->base);
2754                 port = dp_to_dig_port(intel_dp)->port;
2755
2756                 if (intel_dp->pps_pipe != pipe)
2757                         continue;
2758
2759                 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
2760                               pipe_name(pipe), port_name(port));
2761
2762                 WARN(encoder->base.crtc,
2763                      "stealing pipe %c power sequencer from active eDP port %c\n",
2764                      pipe_name(pipe), port_name(port));
2765
2766                 /* make sure vdd is off before we steal it */
2767                 vlv_detach_power_sequencer(intel_dp);
2768         }
2769 }
2770
2771 static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
2772 {
2773         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2774         struct intel_encoder *encoder = &intel_dig_port->base;
2775         struct drm_device *dev = encoder->base.dev;
2776         struct drm_i915_private *dev_priv = dev->dev_private;
2777         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2778
2779         lockdep_assert_held(&dev_priv->pps_mutex);
2780
2781         if (!is_edp(intel_dp))
2782                 return;
2783
2784         if (intel_dp->pps_pipe == crtc->pipe)
2785                 return;
2786
2787         /*
2788          * If another power sequencer was being used on this
2789          * port previously make sure to turn off vdd there while
2790          * we still have control of it.
2791          */
2792         if (intel_dp->pps_pipe != INVALID_PIPE)
2793                 vlv_detach_power_sequencer(intel_dp);
2794
2795         /*
2796          * We may be stealing the power
2797          * sequencer from another port.
2798          */
2799         vlv_steal_power_sequencer(dev, crtc->pipe);
2800
2801         /* now it's all ours */
2802         intel_dp->pps_pipe = crtc->pipe;
2803
2804         DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2805                       pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
2806
2807         /* init power sequencer on this pipe and port */
2808         intel_dp_init_panel_power_sequencer(dev, intel_dp);
2809         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
2810 }
2811
2812 static void vlv_pre_enable_dp(struct intel_encoder *encoder)
2813 {
2814         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2815         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2816         struct drm_device *dev = encoder->base.dev;
2817         struct drm_i915_private *dev_priv = dev->dev_private;
2818         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
2819         enum dpio_channel port = vlv_dport_to_channel(dport);
2820         int pipe = intel_crtc->pipe;
2821         u32 val;
2822
2823         mutex_lock(&dev_priv->sb_lock);
2824
2825         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
2826         val = 0;
2827         if (pipe)
2828                 val |= (1<<21);
2829         else
2830                 val &= ~(1<<21);
2831         val |= 0x001000c4;
2832         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
2833         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
2834         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
2835
2836         mutex_unlock(&dev_priv->sb_lock);
2837
2838         intel_enable_dp(encoder);
2839 }
2840
2841 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
2842 {
2843         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2844         struct drm_device *dev = encoder->base.dev;
2845         struct drm_i915_private *dev_priv = dev->dev_private;
2846         struct intel_crtc *intel_crtc =
2847                 to_intel_crtc(encoder->base.crtc);
2848         enum dpio_channel port = vlv_dport_to_channel(dport);
2849         int pipe = intel_crtc->pipe;
2850
2851         intel_dp_prepare(encoder);
2852
2853         /* Program Tx lane resets to default */
2854         mutex_lock(&dev_priv->sb_lock);
2855         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
2856                          DPIO_PCS_TX_LANE2_RESET |
2857                          DPIO_PCS_TX_LANE1_RESET);
2858         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
2859                          DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2860                          DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2861                          (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2862                                  DPIO_PCS_CLK_SOFT_RESET);
2863
2864         /* Fix up inter-pair skew failure */
2865         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2866         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2867         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
2868         mutex_unlock(&dev_priv->sb_lock);
2869 }
2870
2871 static void chv_pre_enable_dp(struct intel_encoder *encoder)
2872 {
2873         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2874         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2875         struct drm_device *dev = encoder->base.dev;
2876         struct drm_i915_private *dev_priv = dev->dev_private;
2877         struct intel_crtc *intel_crtc =
2878                 to_intel_crtc(encoder->base.crtc);
2879         enum dpio_channel ch = vlv_dport_to_channel(dport);
2880         int pipe = intel_crtc->pipe;
2881         int data, i, stagger;
2882         u32 val;
2883
2884         mutex_lock(&dev_priv->sb_lock);
2885
2886         /* allow hardware to manage TX FIFO reset source */
2887         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
2888         val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
2889         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
2890
2891         if (intel_crtc->config->lane_count > 2) {
2892                 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
2893                 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
2894                 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
2895         }
2896
2897         /* Program Tx lane latency optimal setting*/
2898         for (i = 0; i < intel_crtc->config->lane_count; i++) {
2899                 /* Set the upar bit */
2900                 if (intel_crtc->config->lane_count == 1)
2901                         data = 0x0;
2902                 else
2903                         data = (i == 1) ? 0x0 : 0x1;
2904                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
2905                                 data << DPIO_UPAR_SHIFT);
2906         }
2907
2908         /* Data lane stagger programming */
2909         if (intel_crtc->config->port_clock > 270000)
2910                 stagger = 0x18;
2911         else if (intel_crtc->config->port_clock > 135000)
2912                 stagger = 0xd;
2913         else if (intel_crtc->config->port_clock > 67500)
2914                 stagger = 0x7;
2915         else if (intel_crtc->config->port_clock > 33750)
2916                 stagger = 0x4;
2917         else
2918                 stagger = 0x2;
2919
2920         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
2921         val |= DPIO_TX2_STAGGER_MASK(0x1f);
2922         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
2923
2924         if (intel_crtc->config->lane_count > 2) {
2925                 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
2926                 val |= DPIO_TX2_STAGGER_MASK(0x1f);
2927                 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
2928         }
2929
2930         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch),
2931                        DPIO_LANESTAGGER_STRAP(stagger) |
2932                        DPIO_LANESTAGGER_STRAP_OVRD |
2933                        DPIO_TX1_STAGGER_MASK(0x1f) |
2934                        DPIO_TX1_STAGGER_MULT(6) |
2935                        DPIO_TX2_STAGGER_MULT(0));
2936
2937         if (intel_crtc->config->lane_count > 2) {
2938                 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch),
2939                                DPIO_LANESTAGGER_STRAP(stagger) |
2940                                DPIO_LANESTAGGER_STRAP_OVRD |
2941                                DPIO_TX1_STAGGER_MASK(0x1f) |
2942                                DPIO_TX1_STAGGER_MULT(7) |
2943                                DPIO_TX2_STAGGER_MULT(5));
2944         }
2945
2946         /* Deassert data lane reset */
2947         chv_data_lane_soft_reset(encoder, false);
2948
2949         mutex_unlock(&dev_priv->sb_lock);
2950
2951         intel_enable_dp(encoder);
2952
2953         /* Second common lane will stay alive on its own now */
2954         if (dport->release_cl2_override) {
2955                 chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false);
2956                 dport->release_cl2_override = false;
2957         }
2958 }
2959
2960 static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2961 {
2962         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2963         struct drm_device *dev = encoder->base.dev;
2964         struct drm_i915_private *dev_priv = dev->dev_private;
2965         struct intel_crtc *intel_crtc =
2966                 to_intel_crtc(encoder->base.crtc);
2967         enum dpio_channel ch = vlv_dport_to_channel(dport);
2968         enum pipe pipe = intel_crtc->pipe;
2969         unsigned int lane_mask =
2970                 intel_dp_unused_lane_mask(intel_crtc->config->lane_count);
2971         u32 val;
2972
2973         intel_dp_prepare(encoder);
2974
2975         /*
2976          * Must trick the second common lane into life.
2977          * Otherwise we can't even access the PLL.
2978          */
2979         if (ch == DPIO_CH0 && pipe == PIPE_B)
2980                 dport->release_cl2_override =
2981                         !chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true);
2982
2983         chv_phy_powergate_lanes(encoder, true, lane_mask);
2984
2985         mutex_lock(&dev_priv->sb_lock);
2986
2987         /* Assert data lane reset */
2988         chv_data_lane_soft_reset(encoder, true);
2989
2990         /* program left/right clock distribution */
2991         if (pipe != PIPE_B) {
2992                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
2993                 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
2994                 if (ch == DPIO_CH0)
2995                         val |= CHV_BUFLEFTENA1_FORCE;
2996                 if (ch == DPIO_CH1)
2997                         val |= CHV_BUFRIGHTENA1_FORCE;
2998                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
2999         } else {
3000                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
3001                 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
3002                 if (ch == DPIO_CH0)
3003                         val |= CHV_BUFLEFTENA2_FORCE;
3004                 if (ch == DPIO_CH1)
3005                         val |= CHV_BUFRIGHTENA2_FORCE;
3006                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
3007         }
3008
3009         /* program clock channel usage */
3010         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
3011         val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
3012         if (pipe != PIPE_B)
3013                 val &= ~CHV_PCS_USEDCLKCHANNEL;
3014         else
3015                 val |= CHV_PCS_USEDCLKCHANNEL;
3016         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
3017
3018         if (intel_crtc->config->lane_count > 2) {
3019                 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
3020                 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
3021                 if (pipe != PIPE_B)
3022                         val &= ~CHV_PCS_USEDCLKCHANNEL;
3023                 else
3024                         val |= CHV_PCS_USEDCLKCHANNEL;
3025                 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
3026         }
3027
3028         /*
3029          * This a a bit weird since generally CL
3030          * matches the pipe, but here we need to
3031          * pick the CL based on the port.
3032          */
3033         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
3034         if (pipe != PIPE_B)
3035                 val &= ~CHV_CMN_USEDCLKCHANNEL;
3036         else
3037                 val |= CHV_CMN_USEDCLKCHANNEL;
3038         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
3039
3040         mutex_unlock(&dev_priv->sb_lock);
3041 }
3042
3043 static void chv_dp_post_pll_disable(struct intel_encoder *encoder)
3044 {
3045         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3046         enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe;
3047         u32 val;
3048
3049         mutex_lock(&dev_priv->sb_lock);
3050
3051         /* disable left/right clock distribution */
3052         if (pipe != PIPE_B) {
3053                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
3054                 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
3055                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
3056         } else {
3057                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
3058                 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
3059                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
3060         }
3061
3062         mutex_unlock(&dev_priv->sb_lock);
3063
3064         /*
3065          * Leave the power down bit cleared for at least one
3066          * lane so that chv_powergate_phy_ch() will power
3067          * on something when the channel is otherwise unused.
3068          * When the port is off and the override is removed
3069          * the lanes power down anyway, so otherwise it doesn't
3070          * really matter what the state of power down bits is
3071          * after this.
3072          */
3073         chv_phy_powergate_lanes(encoder, false, 0x0);
3074 }
3075
3076 /*
3077  * Fetch AUX CH registers 0x202 - 0x207 which contain
3078  * link status information
3079  */
3080 bool
3081 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
3082 {
3083         return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status,
3084                                 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
3085 }
3086
3087 /* These are source-specific values. */
3088 uint8_t
3089 intel_dp_voltage_max(struct intel_dp *intel_dp)
3090 {
3091         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3092         struct drm_i915_private *dev_priv = dev->dev_private;
3093         enum port port = dp_to_dig_port(intel_dp)->port;
3094
3095         if (IS_BROXTON(dev))
3096                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3097         else if (INTEL_INFO(dev)->gen >= 9) {
3098                 if (dev_priv->vbt.edp.low_vswing && port == PORT_A)
3099                         return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3100                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3101         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
3102                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3103         else if (IS_GEN7(dev) && port == PORT_A)
3104                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3105         else if (HAS_PCH_CPT(dev) && port != PORT_A)
3106                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3107         else
3108                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3109 }
3110
3111 uint8_t
3112 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
3113 {
3114         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3115         enum port port = dp_to_dig_port(intel_dp)->port;
3116
3117         if (INTEL_INFO(dev)->gen >= 9) {
3118                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3119                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3120                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
3121                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3122                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3123                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3124                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3125                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3126                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3127                 default:
3128                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3129                 }
3130         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
3131                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3132                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3133                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
3134                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3135                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3136                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3137                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3138                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3139                 default:
3140                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3141                 }
3142         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
3143                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3144                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3145                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
3146                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3147                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3148                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3149                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3150                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3151                 default:
3152                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3153                 }
3154         } else if (IS_GEN7(dev) && port == PORT_A) {
3155                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3156                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3157                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3158                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3159                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3160                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3161                 default:
3162                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3163                 }
3164         } else {
3165                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3166                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3167                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3168                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3169                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3170                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3171                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3172                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3173                 default:
3174                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3175                 }
3176         }
3177 }
3178
3179 static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
3180 {
3181         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3182         struct drm_i915_private *dev_priv = dev->dev_private;
3183         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
3184         struct intel_crtc *intel_crtc =
3185                 to_intel_crtc(dport->base.base.crtc);
3186         unsigned long demph_reg_value, preemph_reg_value,
3187                 uniqtranscale_reg_value;
3188         uint8_t train_set = intel_dp->train_set[0];
3189         enum dpio_channel port = vlv_dport_to_channel(dport);
3190         int pipe = intel_crtc->pipe;
3191
3192         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3193         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3194                 preemph_reg_value = 0x0004000;
3195                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3196                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3197                         demph_reg_value = 0x2B405555;
3198                         uniqtranscale_reg_value = 0x552AB83A;
3199                         break;
3200                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3201                         demph_reg_value = 0x2B404040;
3202                         uniqtranscale_reg_value = 0x5548B83A;
3203                         break;
3204                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3205                         demph_reg_value = 0x2B245555;
3206                         uniqtranscale_reg_value = 0x5560B83A;
3207                         break;
3208                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3209                         demph_reg_value = 0x2B405555;
3210                         uniqtranscale_reg_value = 0x5598DA3A;
3211                         break;
3212                 default:
3213                         return 0;
3214                 }
3215                 break;
3216         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3217                 preemph_reg_value = 0x0002000;
3218                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3219                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3220                         demph_reg_value = 0x2B404040;
3221                         uniqtranscale_reg_value = 0x5552B83A;
3222                         break;
3223                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3224                         demph_reg_value = 0x2B404848;
3225                         uniqtranscale_reg_value = 0x5580B83A;
3226                         break;
3227                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3228                         demph_reg_value = 0x2B404040;
3229                         uniqtranscale_reg_value = 0x55ADDA3A;
3230                         break;
3231                 default:
3232                         return 0;
3233                 }
3234                 break;
3235         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3236                 preemph_reg_value = 0x0000000;
3237                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3238                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3239                         demph_reg_value = 0x2B305555;
3240                         uniqtranscale_reg_value = 0x5570B83A;
3241                         break;
3242                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3243                         demph_reg_value = 0x2B2B4040;
3244                         uniqtranscale_reg_value = 0x55ADDA3A;
3245                         break;
3246                 default:
3247                         return 0;
3248                 }
3249                 break;
3250         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3251                 preemph_reg_value = 0x0006000;
3252                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3253                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3254                         demph_reg_value = 0x1B405555;
3255                         uniqtranscale_reg_value = 0x55ADDA3A;
3256                         break;
3257                 default:
3258                         return 0;
3259                 }
3260                 break;
3261         default:
3262                 return 0;
3263         }
3264
3265         mutex_lock(&dev_priv->sb_lock);
3266         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
3267         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
3268         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
3269                          uniqtranscale_reg_value);
3270         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
3271         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
3272         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
3273         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
3274         mutex_unlock(&dev_priv->sb_lock);
3275
3276         return 0;
3277 }
3278
3279 static bool chv_need_uniq_trans_scale(uint8_t train_set)
3280 {
3281         return (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) == DP_TRAIN_PRE_EMPH_LEVEL_0 &&
3282                 (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) == DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3283 }
3284
3285 static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
3286 {
3287         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3288         struct drm_i915_private *dev_priv = dev->dev_private;
3289         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
3290         struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
3291         u32 deemph_reg_value, margin_reg_value, val;
3292         uint8_t train_set = intel_dp->train_set[0];
3293         enum dpio_channel ch = vlv_dport_to_channel(dport);
3294         enum pipe pipe = intel_crtc->pipe;
3295         int i;
3296
3297         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3298         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3299                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3300                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3301                         deemph_reg_value = 128;
3302                         margin_reg_value = 52;
3303                         break;
3304                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3305                         deemph_reg_value = 128;
3306                         margin_reg_value = 77;
3307                         break;
3308                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3309                         deemph_reg_value = 128;
3310                         margin_reg_value = 102;
3311                         break;
3312                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3313                         deemph_reg_value = 128;
3314                         margin_reg_value = 154;
3315                         /* FIXME extra to set for 1200 */
3316                         break;
3317                 default:
3318                         return 0;
3319                 }
3320                 break;
3321         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3322                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3323                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3324                         deemph_reg_value = 85;
3325                         margin_reg_value = 78;
3326                         break;
3327                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3328                         deemph_reg_value = 85;
3329                         margin_reg_value = 116;
3330                         break;
3331                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3332                         deemph_reg_value = 85;
3333                         margin_reg_value = 154;
3334                         break;
3335                 default:
3336                         return 0;
3337                 }
3338                 break;
3339         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3340                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3341                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3342                         deemph_reg_value = 64;
3343                         margin_reg_value = 104;
3344                         break;
3345                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3346                         deemph_reg_value = 64;
3347                         margin_reg_value = 154;
3348                         break;
3349                 default:
3350                         return 0;
3351                 }
3352                 break;
3353         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3354                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3355                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3356                         deemph_reg_value = 43;
3357                         margin_reg_value = 154;
3358                         break;
3359                 default:
3360                         return 0;
3361                 }
3362                 break;
3363         default:
3364                 return 0;
3365         }
3366
3367         mutex_lock(&dev_priv->sb_lock);
3368
3369         /* Clear calc init */
3370         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3371         val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
3372         val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
3373         val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
3374         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3375
3376         if (intel_crtc->config->lane_count > 2) {
3377                 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3378                 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
3379                 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
3380                 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
3381                 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
3382         }
3383
3384         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
3385         val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
3386         val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
3387         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
3388
3389         if (intel_crtc->config->lane_count > 2) {
3390                 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
3391                 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
3392                 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
3393                 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
3394         }
3395
3396         /* Program swing deemph */
3397         for (i = 0; i < intel_crtc->config->lane_count; i++) {
3398                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
3399                 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
3400                 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
3401                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
3402         }
3403
3404         /* Program swing margin */
3405         for (i = 0; i < intel_crtc->config->lane_count; i++) {
3406                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
3407
3408                 val &= ~DPIO_SWING_MARGIN000_MASK;
3409                 val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
3410
3411                 /*
3412                  * Supposedly this value shouldn't matter when unique transition
3413                  * scale is disabled, but in fact it does matter. Let's just
3414                  * always program the same value and hope it's OK.
3415                  */
3416                 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3417                 val |= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT;
3418
3419                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3420         }
3421
3422         /*
3423          * The document said it needs to set bit 27 for ch0 and bit 26
3424          * for ch1. Might be a typo in the doc.
3425          * For now, for this unique transition scale selection, set bit
3426          * 27 for ch0 and ch1.
3427          */
3428         for (i = 0; i < intel_crtc->config->lane_count; i++) {
3429                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3430                 if (chv_need_uniq_trans_scale(train_set))
3431                         val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
3432                 else
3433                         val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
3434                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3435         }
3436
3437         /* Start swing calculation */
3438         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3439         val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3440         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3441
3442         if (intel_crtc->config->lane_count > 2) {
3443                 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3444                 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3445                 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
3446         }
3447
3448         mutex_unlock(&dev_priv->sb_lock);
3449
3450         return 0;
3451 }
3452
3453 static uint32_t
3454 gen4_signal_levels(uint8_t train_set)
3455 {
3456         uint32_t        signal_levels = 0;
3457
3458         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3459         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3460         default:
3461                 signal_levels |= DP_VOLTAGE_0_4;
3462                 break;
3463         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3464                 signal_levels |= DP_VOLTAGE_0_6;
3465                 break;
3466         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3467                 signal_levels |= DP_VOLTAGE_0_8;
3468                 break;
3469         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3470                 signal_levels |= DP_VOLTAGE_1_2;
3471                 break;
3472         }
3473         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3474         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3475         default:
3476                 signal_levels |= DP_PRE_EMPHASIS_0;
3477                 break;
3478         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3479                 signal_levels |= DP_PRE_EMPHASIS_3_5;
3480                 break;
3481         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3482                 signal_levels |= DP_PRE_EMPHASIS_6;
3483                 break;
3484         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3485                 signal_levels |= DP_PRE_EMPHASIS_9_5;
3486                 break;
3487         }
3488         return signal_levels;
3489 }
3490
3491 /* Gen6's DP voltage swing and pre-emphasis control */
3492 static uint32_t
3493 gen6_edp_signal_levels(uint8_t train_set)
3494 {
3495         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3496                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3497         switch (signal_levels) {
3498         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3499         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3500                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3501         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3502                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
3503         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3504         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3505                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
3506         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3507         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3508                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
3509         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3510         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3511                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
3512         default:
3513                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3514                               "0x%x\n", signal_levels);
3515                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3516         }
3517 }
3518
3519 /* Gen7's DP voltage swing and pre-emphasis control */
3520 static uint32_t
3521 gen7_edp_signal_levels(uint8_t train_set)
3522 {
3523         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3524                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3525         switch (signal_levels) {
3526         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3527                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
3528         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3529                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
3530         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3531                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3532
3533         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3534                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
3535         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3536                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3537
3538         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3539                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
3540         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3541                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3542
3543         default:
3544                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3545                               "0x%x\n", signal_levels);
3546                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3547         }
3548 }
3549
3550 void
3551 intel_dp_set_signal_levels(struct intel_dp *intel_dp)
3552 {
3553         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3554         enum port port = intel_dig_port->port;
3555         struct drm_device *dev = intel_dig_port->base.base.dev;
3556         struct drm_i915_private *dev_priv = to_i915(dev);
3557         uint32_t signal_levels, mask = 0;
3558         uint8_t train_set = intel_dp->train_set[0];
3559
3560         if (HAS_DDI(dev)) {
3561                 signal_levels = ddi_signal_levels(intel_dp);
3562
3563                 if (IS_BROXTON(dev))
3564                         signal_levels = 0;
3565                 else
3566                         mask = DDI_BUF_EMP_MASK;
3567         } else if (IS_CHERRYVIEW(dev)) {
3568                 signal_levels = chv_signal_levels(intel_dp);
3569         } else if (IS_VALLEYVIEW(dev)) {
3570                 signal_levels = vlv_signal_levels(intel_dp);
3571         } else if (IS_GEN7(dev) && port == PORT_A) {
3572                 signal_levels = gen7_edp_signal_levels(train_set);
3573                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
3574         } else if (IS_GEN6(dev) && port == PORT_A) {
3575                 signal_levels = gen6_edp_signal_levels(train_set);
3576                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3577         } else {
3578                 signal_levels = gen4_signal_levels(train_set);
3579                 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3580         }
3581
3582         if (mask)
3583                 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3584
3585         DRM_DEBUG_KMS("Using vswing level %d\n",
3586                 train_set & DP_TRAIN_VOLTAGE_SWING_MASK);
3587         DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3588                 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
3589                         DP_TRAIN_PRE_EMPHASIS_SHIFT);
3590
3591         intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels;
3592
3593         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3594         POSTING_READ(intel_dp->output_reg);
3595 }
3596
3597 void
3598 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
3599                                        uint8_t dp_train_pat)
3600 {
3601         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3602         struct drm_i915_private *dev_priv =
3603                 to_i915(intel_dig_port->base.base.dev);
3604
3605         _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat);
3606
3607         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3608         POSTING_READ(intel_dp->output_reg);
3609 }
3610
3611 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3612 {
3613         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3614         struct drm_device *dev = intel_dig_port->base.base.dev;
3615         struct drm_i915_private *dev_priv = dev->dev_private;
3616         enum port port = intel_dig_port->port;
3617         uint32_t val;
3618
3619         if (!HAS_DDI(dev))
3620                 return;
3621
3622         val = I915_READ(DP_TP_CTL(port));
3623         val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3624         val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3625         I915_WRITE(DP_TP_CTL(port), val);
3626
3627         /*
3628          * On PORT_A we can have only eDP in SST mode. There the only reason
3629          * we need to set idle transmission mode is to work around a HW issue
3630          * where we enable the pipe while not in idle link-training mode.
3631          * In this case there is requirement to wait for a minimum number of
3632          * idle patterns to be sent.
3633          */
3634         if (port == PORT_A)
3635                 return;
3636
3637         if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
3638                      1))
3639                 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3640 }
3641
3642 static void
3643 intel_dp_link_down(struct intel_dp *intel_dp)
3644 {
3645         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3646         struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
3647         enum port port = intel_dig_port->port;
3648         struct drm_device *dev = intel_dig_port->base.base.dev;
3649         struct drm_i915_private *dev_priv = dev->dev_private;
3650         uint32_t DP = intel_dp->DP;
3651
3652         if (WARN_ON(HAS_DDI(dev)))
3653                 return;
3654
3655         if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
3656                 return;
3657
3658         DRM_DEBUG_KMS("\n");
3659
3660         if ((IS_GEN7(dev) && port == PORT_A) ||
3661             (HAS_PCH_CPT(dev) && port != PORT_A)) {
3662                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
3663                 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
3664         } else {
3665                 if (IS_CHERRYVIEW(dev))
3666                         DP &= ~DP_LINK_TRAIN_MASK_CHV;
3667                 else
3668                         DP &= ~DP_LINK_TRAIN_MASK;
3669                 DP |= DP_LINK_TRAIN_PAT_IDLE;
3670         }
3671         I915_WRITE(intel_dp->output_reg, DP);
3672         POSTING_READ(intel_dp->output_reg);
3673
3674         DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
3675         I915_WRITE(intel_dp->output_reg, DP);
3676         POSTING_READ(intel_dp->output_reg);
3677
3678         /*
3679          * HW workaround for IBX, we need to move the port
3680          * to transcoder A after disabling it to allow the
3681          * matching HDMI port to be enabled on transcoder A.
3682          */
3683         if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B && port != PORT_A) {
3684                 /*
3685                  * We get CPU/PCH FIFO underruns on the other pipe when
3686                  * doing the workaround. Sweep them under the rug.
3687                  */
3688                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3689                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3690
3691                 /* always enable with pattern 1 (as per spec) */
3692                 DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK);
3693                 DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1;
3694                 I915_WRITE(intel_dp->output_reg, DP);
3695                 POSTING_READ(intel_dp->output_reg);
3696
3697                 DP &= ~DP_PORT_EN;
3698                 I915_WRITE(intel_dp->output_reg, DP);
3699                 POSTING_READ(intel_dp->output_reg);
3700
3701                 intel_wait_for_vblank_if_active(dev_priv->dev, PIPE_A);
3702                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3703                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3704         }
3705
3706         msleep(intel_dp->panel_power_down_delay);
3707
3708         intel_dp->DP = DP;
3709 }
3710
3711 static bool
3712 intel_dp_get_dpcd(struct intel_dp *intel_dp)
3713 {
3714         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3715         struct drm_device *dev = dig_port->base.base.dev;
3716         struct drm_i915_private *dev_priv = dev->dev_private;
3717         uint8_t rev;
3718
3719         if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd,
3720                              sizeof(intel_dp->dpcd)) < 0)
3721                 return false; /* aux transfer failed */
3722
3723         DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
3724
3725         if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3726                 return false; /* DPCD not present */
3727
3728         if (drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT,
3729                              &intel_dp->sink_count, 1) < 0)
3730                 return false;
3731
3732         /*
3733          * Sink count can change between short pulse hpd hence
3734          * a member variable in intel_dp will track any changes
3735          * between short pulse interrupts.
3736          */
3737         intel_dp->sink_count = DP_GET_SINK_COUNT(intel_dp->sink_count);
3738
3739         /*
3740          * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
3741          * a dongle is present but no display. Unless we require to know
3742          * if a dongle is present or not, we don't need to update
3743          * downstream port information. So, an early return here saves
3744          * time from performing other operations which are not required.
3745          */
3746         if (!is_edp(intel_dp) && !intel_dp->sink_count)
3747                 return false;
3748
3749         /* Check if the panel supports PSR */
3750         memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
3751         if (is_edp(intel_dp)) {
3752                 drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT,
3753                                  intel_dp->psr_dpcd,
3754                                  sizeof(intel_dp->psr_dpcd));
3755                 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3756                         dev_priv->psr.sink_support = true;
3757                         DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3758                 }
3759
3760                 if (INTEL_INFO(dev)->gen >= 9 &&
3761                         (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) {
3762                         uint8_t frame_sync_cap;
3763
3764                         dev_priv->psr.sink_support = true;
3765                         drm_dp_dpcd_read(&intel_dp->aux,
3766                                          DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP,
3767                                          &frame_sync_cap, 1);
3768                         dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false;
3769                         /* PSR2 needs frame sync as well */
3770                         dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync;
3771                         DRM_DEBUG_KMS("PSR2 %s on sink",
3772                                 dev_priv->psr.psr2_support ? "supported" : "not supported");
3773                 }
3774         }
3775
3776         DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n",
3777                       yesno(intel_dp_source_supports_hbr2(intel_dp)),
3778                       yesno(drm_dp_tps3_supported(intel_dp->dpcd)));
3779
3780         /* Intermediate frequency support */
3781         if (is_edp(intel_dp) &&
3782             (intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
3783             (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV, &rev, 1) == 1) &&
3784             (rev >= 0x03)) { /* eDp v1.4 or higher */
3785                 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
3786                 int i;
3787
3788                 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
3789                                 sink_rates, sizeof(sink_rates));
3790
3791                 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
3792                         int val = le16_to_cpu(sink_rates[i]);
3793
3794                         if (val == 0)
3795                                 break;
3796
3797                         /* Value read is in kHz while drm clock is saved in deca-kHz */
3798                         intel_dp->sink_rates[i] = (val * 200) / 10;
3799                 }
3800                 intel_dp->num_sink_rates = i;
3801         }
3802
3803         intel_dp_print_rates(intel_dp);
3804
3805         if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3806               DP_DWN_STRM_PORT_PRESENT))
3807                 return true; /* native DP sink */
3808
3809         if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3810                 return true; /* no per-port downstream info */
3811
3812         if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3813                              intel_dp->downstream_ports,
3814                              DP_MAX_DOWNSTREAM_PORTS) < 0)
3815                 return false; /* downstream port status fetch failed */
3816
3817         return true;
3818 }
3819
3820 static void
3821 intel_dp_probe_oui(struct intel_dp *intel_dp)
3822 {
3823         u8 buf[3];
3824
3825         if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3826                 return;
3827
3828         if (drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
3829                 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3830                               buf[0], buf[1], buf[2]);
3831
3832         if (drm_dp_dpcd_read(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
3833                 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3834                               buf[0], buf[1], buf[2]);
3835 }
3836
3837 static bool
3838 intel_dp_probe_mst(struct intel_dp *intel_dp)
3839 {
3840         u8 buf[1];
3841
3842         if (!i915.enable_dp_mst)
3843                 return false;
3844
3845         if (!intel_dp->can_mst)
3846                 return false;
3847
3848         if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3849                 return false;
3850
3851         if (drm_dp_dpcd_read(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
3852                 if (buf[0] & DP_MST_CAP) {
3853                         DRM_DEBUG_KMS("Sink is MST capable\n");
3854                         intel_dp->is_mst = true;
3855                 } else {
3856                         DRM_DEBUG_KMS("Sink is not MST capable\n");
3857                         intel_dp->is_mst = false;
3858                 }
3859         }
3860
3861         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3862         return intel_dp->is_mst;
3863 }
3864
3865 static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp)
3866 {
3867         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3868         struct drm_device *dev = dig_port->base.base.dev;
3869         struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3870         u8 buf;
3871         int ret = 0;
3872         int count = 0;
3873         int attempts = 10;
3874
3875         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) {
3876                 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3877                 ret = -EIO;
3878                 goto out;
3879         }
3880
3881         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3882                                buf & ~DP_TEST_SINK_START) < 0) {
3883                 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3884                 ret = -EIO;
3885                 goto out;
3886         }
3887
3888         do {
3889                 intel_wait_for_vblank(dev, intel_crtc->pipe);
3890
3891                 if (drm_dp_dpcd_readb(&intel_dp->aux,
3892                                       DP_TEST_SINK_MISC, &buf) < 0) {
3893                         ret = -EIO;
3894                         goto out;
3895                 }
3896                 count = buf & DP_TEST_COUNT_MASK;
3897         } while (--attempts && count);
3898
3899         if (attempts == 0) {
3900                 DRM_DEBUG_KMS("TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped\n");
3901                 ret = -ETIMEDOUT;
3902         }
3903
3904  out:
3905         hsw_enable_ips(intel_crtc);
3906         return ret;
3907 }
3908
3909 static int intel_dp_sink_crc_start(struct intel_dp *intel_dp)
3910 {
3911         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3912         struct drm_device *dev = dig_port->base.base.dev;
3913         struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3914         u8 buf;
3915         int ret;
3916
3917         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
3918                 return -EIO;
3919
3920         if (!(buf & DP_TEST_CRC_SUPPORTED))
3921                 return -ENOTTY;
3922
3923         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
3924                 return -EIO;
3925
3926         if (buf & DP_TEST_SINK_START) {
3927                 ret = intel_dp_sink_crc_stop(intel_dp);
3928                 if (ret)
3929                         return ret;
3930         }
3931
3932         hsw_disable_ips(intel_crtc);
3933
3934         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3935                                buf | DP_TEST_SINK_START) < 0) {
3936                 hsw_enable_ips(intel_crtc);
3937                 return -EIO;
3938         }
3939
3940         intel_wait_for_vblank(dev, intel_crtc->pipe);
3941         return 0;
3942 }
3943
3944 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3945 {
3946         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3947         struct drm_device *dev = dig_port->base.base.dev;
3948         struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3949         u8 buf;
3950         int count, ret;
3951         int attempts = 6;
3952
3953         ret = intel_dp_sink_crc_start(intel_dp);
3954         if (ret)
3955                 return ret;
3956
3957         do {
3958                 intel_wait_for_vblank(dev, intel_crtc->pipe);
3959
3960                 if (drm_dp_dpcd_readb(&intel_dp->aux,
3961                                       DP_TEST_SINK_MISC, &buf) < 0) {
3962                         ret = -EIO;
3963                         goto stop;
3964                 }
3965                 count = buf & DP_TEST_COUNT_MASK;
3966
3967         } while (--attempts && count == 0);
3968
3969         if (attempts == 0) {
3970                 DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n");
3971                 ret = -ETIMEDOUT;
3972                 goto stop;
3973         }
3974
3975         if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) {
3976                 ret = -EIO;
3977                 goto stop;
3978         }
3979
3980 stop:
3981         intel_dp_sink_crc_stop(intel_dp);
3982         return ret;
3983 }
3984
3985 static bool
3986 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3987 {
3988         return drm_dp_dpcd_read(&intel_dp->aux,
3989                                        DP_DEVICE_SERVICE_IRQ_VECTOR,
3990                                        sink_irq_vector, 1) == 1;
3991 }
3992
3993 static bool
3994 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3995 {
3996         int ret;
3997
3998         ret = drm_dp_dpcd_read(&intel_dp->aux,
3999                                              DP_SINK_COUNT_ESI,
4000                                              sink_irq_vector, 14);
4001         if (ret != 14)
4002                 return false;
4003
4004         return true;
4005 }
4006
4007 static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
4008 {
4009         uint8_t test_result = DP_TEST_ACK;
4010         return test_result;
4011 }
4012
4013 static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
4014 {
4015         uint8_t test_result = DP_TEST_NAK;
4016         return test_result;
4017 }
4018
4019 static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
4020 {
4021         uint8_t test_result = DP_TEST_NAK;
4022         struct intel_connector *intel_connector = intel_dp->attached_connector;
4023         struct drm_connector *connector = &intel_connector->base;
4024
4025         if (intel_connector->detect_edid == NULL ||
4026             connector->edid_corrupt ||
4027             intel_dp->aux.i2c_defer_count > 6) {
4028                 /* Check EDID read for NACKs, DEFERs and corruption
4029                  * (DP CTS 1.2 Core r1.1)
4030                  *    4.2.2.4 : Failed EDID read, I2C_NAK
4031                  *    4.2.2.5 : Failed EDID read, I2C_DEFER
4032                  *    4.2.2.6 : EDID corruption detected
4033                  * Use failsafe mode for all cases
4034                  */
4035                 if (intel_dp->aux.i2c_nack_count > 0 ||
4036                         intel_dp->aux.i2c_defer_count > 0)
4037                         DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
4038                                       intel_dp->aux.i2c_nack_count,
4039                                       intel_dp->aux.i2c_defer_count);
4040                 intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_FAILSAFE;
4041         } else {
4042                 struct edid *block = intel_connector->detect_edid;
4043
4044                 /* We have to write the checksum
4045                  * of the last block read
4046                  */
4047                 block += intel_connector->detect_edid->extensions;
4048
4049                 if (!drm_dp_dpcd_write(&intel_dp->aux,
4050                                         DP_TEST_EDID_CHECKSUM,
4051                                         &block->checksum,
4052                                         1))
4053                         DRM_DEBUG_KMS("Failed to write EDID checksum\n");
4054
4055                 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
4056                 intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_STANDARD;
4057         }
4058
4059         /* Set test active flag here so userspace doesn't interrupt things */
4060         intel_dp->compliance_test_active = 1;
4061
4062         return test_result;
4063 }
4064
4065 static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
4066 {
4067         uint8_t test_result = DP_TEST_NAK;
4068         return test_result;
4069 }
4070
4071 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
4072 {
4073         uint8_t response = DP_TEST_NAK;
4074         uint8_t rxdata = 0;
4075         int status = 0;
4076
4077         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_REQUEST, &rxdata, 1);
4078         if (status <= 0) {
4079                 DRM_DEBUG_KMS("Could not read test request from sink\n");
4080                 goto update_status;
4081         }
4082
4083         switch (rxdata) {
4084         case DP_TEST_LINK_TRAINING:
4085                 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
4086                 intel_dp->compliance_test_type = DP_TEST_LINK_TRAINING;
4087                 response = intel_dp_autotest_link_training(intel_dp);
4088                 break;
4089         case DP_TEST_LINK_VIDEO_PATTERN:
4090                 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
4091                 intel_dp->compliance_test_type = DP_TEST_LINK_VIDEO_PATTERN;
4092                 response = intel_dp_autotest_video_pattern(intel_dp);
4093                 break;
4094         case DP_TEST_LINK_EDID_READ:
4095                 DRM_DEBUG_KMS("EDID test requested\n");
4096                 intel_dp->compliance_test_type = DP_TEST_LINK_EDID_READ;
4097                 response = intel_dp_autotest_edid(intel_dp);
4098                 break;
4099         case DP_TEST_LINK_PHY_TEST_PATTERN:
4100                 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
4101                 intel_dp->compliance_test_type = DP_TEST_LINK_PHY_TEST_PATTERN;
4102                 response = intel_dp_autotest_phy_pattern(intel_dp);
4103                 break;
4104         default:
4105                 DRM_DEBUG_KMS("Invalid test request '%02x'\n", rxdata);
4106                 break;
4107         }
4108
4109 update_status:
4110         status = drm_dp_dpcd_write(&intel_dp->aux,
4111                                    DP_TEST_RESPONSE,
4112                                    &response, 1);
4113         if (status <= 0)
4114                 DRM_DEBUG_KMS("Could not write test response to sink\n");
4115 }
4116
4117 static int
4118 intel_dp_check_mst_status(struct intel_dp *intel_dp)
4119 {
4120         bool bret;
4121
4122         if (intel_dp->is_mst) {
4123                 u8 esi[16] = { 0 };
4124                 int ret = 0;
4125                 int retry;
4126                 bool handled;
4127                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4128 go_again:
4129                 if (bret == true) {
4130
4131                         /* check link status - esi[10] = 0x200c */
4132                         if (intel_dp->active_mst_links &&
4133                             !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
4134                                 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
4135                                 intel_dp_start_link_train(intel_dp);
4136                                 intel_dp_stop_link_train(intel_dp);
4137                         }
4138
4139                         DRM_DEBUG_KMS("got esi %3ph\n", esi);
4140                         ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
4141
4142                         if (handled) {
4143                                 for (retry = 0; retry < 3; retry++) {
4144                                         int wret;
4145                                         wret = drm_dp_dpcd_write(&intel_dp->aux,
4146                                                                  DP_SINK_COUNT_ESI+1,
4147                                                                  &esi[1], 3);
4148                                         if (wret == 3) {
4149                                                 break;
4150                                         }
4151                                 }
4152
4153                                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4154                                 if (bret == true) {
4155                                         DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
4156                                         goto go_again;
4157                                 }
4158                         } else
4159                                 ret = 0;
4160
4161                         return ret;
4162                 } else {
4163                         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4164                         DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4165                         intel_dp->is_mst = false;
4166                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4167                         /* send a hotplug event */
4168                         drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
4169                 }
4170         }
4171         return -EINVAL;
4172 }
4173
4174 static void
4175 intel_dp_check_link_status(struct intel_dp *intel_dp)
4176 {
4177         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4178         struct drm_device *dev = intel_dp_to_dev(intel_dp);
4179         u8 link_status[DP_LINK_STATUS_SIZE];
4180
4181         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
4182
4183         if (!intel_dp_get_link_status(intel_dp, link_status)) {
4184                 DRM_ERROR("Failed to get link status\n");
4185                 return;
4186         }
4187
4188         if (!intel_encoder->base.crtc)
4189                 return;
4190
4191         if (!to_intel_crtc(intel_encoder->base.crtc)->active)
4192                 return;
4193
4194         /* if link training is requested we should perform it always */
4195         if ((intel_dp->compliance_test_type == DP_TEST_LINK_TRAINING) ||
4196             (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count))) {
4197                 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
4198                               intel_encoder->base.name);
4199                 intel_dp_start_link_train(intel_dp);
4200                 intel_dp_stop_link_train(intel_dp);
4201         }
4202 }
4203
4204 /*
4205  * According to DP spec
4206  * 5.1.2:
4207  *  1. Read DPCD
4208  *  2. Configure link according to Receiver Capabilities
4209  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
4210  *  4. Check link status on receipt of hot-plug interrupt
4211  *
4212  * intel_dp_short_pulse -  handles short pulse interrupts
4213  * when full detection is not required.
4214  * Returns %true if short pulse is handled and full detection
4215  * is NOT required and %false otherwise.
4216  */
4217 static bool
4218 intel_dp_short_pulse(struct intel_dp *intel_dp)
4219 {
4220         struct drm_device *dev = intel_dp_to_dev(intel_dp);
4221         u8 sink_irq_vector;
4222         u8 old_sink_count = intel_dp->sink_count;
4223         bool ret;
4224
4225         /*
4226          * Clearing compliance test variables to allow capturing
4227          * of values for next automated test request.
4228          */
4229         intel_dp->compliance_test_active = 0;
4230         intel_dp->compliance_test_type = 0;
4231         intel_dp->compliance_test_data = 0;
4232
4233         /*
4234          * Now read the DPCD to see if it's actually running
4235          * If the current value of sink count doesn't match with
4236          * the value that was stored earlier or dpcd read failed
4237          * we need to do full detection
4238          */
4239         ret = intel_dp_get_dpcd(intel_dp);
4240
4241         if ((old_sink_count != intel_dp->sink_count) || !ret) {
4242                 /* No need to proceed if we are going to do full detect */
4243                 return false;
4244         }
4245
4246         /* Try to read the source of the interrupt */
4247         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4248             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
4249                 /* Clear interrupt source */
4250                 drm_dp_dpcd_writeb(&intel_dp->aux,
4251                                    DP_DEVICE_SERVICE_IRQ_VECTOR,
4252                                    sink_irq_vector);
4253
4254                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4255                         DRM_DEBUG_DRIVER("Test request in short pulse not handled\n");
4256                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4257                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4258         }
4259
4260         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4261         intel_dp_check_link_status(intel_dp);
4262         drm_modeset_unlock(&dev->mode_config.connection_mutex);
4263
4264         return true;
4265 }
4266
4267 /* XXX this is probably wrong for multiple downstream ports */
4268 static enum drm_connector_status
4269 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
4270 {
4271         uint8_t *dpcd = intel_dp->dpcd;
4272         uint8_t type;
4273
4274         if (!intel_dp_get_dpcd(intel_dp))
4275                 return connector_status_disconnected;
4276
4277         if (is_edp(intel_dp))
4278                 return connector_status_connected;
4279
4280         /* if there's no downstream port, we're done */
4281         if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
4282                 return connector_status_connected;
4283
4284         /* If we're HPD-aware, SINK_COUNT changes dynamically */
4285         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4286             intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
4287
4288                 return intel_dp->sink_count ?
4289                 connector_status_connected : connector_status_disconnected;
4290         }
4291
4292         /* If no HPD, poke DDC gently */
4293         if (drm_probe_ddc(&intel_dp->aux.ddc))
4294                 return connector_status_connected;
4295
4296         /* Well we tried, say unknown for unreliable port types */
4297         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4298                 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4299                 if (type == DP_DS_PORT_TYPE_VGA ||
4300                     type == DP_DS_PORT_TYPE_NON_EDID)
4301                         return connector_status_unknown;
4302         } else {
4303                 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4304                         DP_DWN_STRM_PORT_TYPE_MASK;
4305                 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4306                     type == DP_DWN_STRM_PORT_TYPE_OTHER)
4307                         return connector_status_unknown;
4308         }
4309
4310         /* Anything else is out of spec, warn and ignore */
4311         DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4312         return connector_status_disconnected;
4313 }
4314
4315 static enum drm_connector_status
4316 edp_detect(struct intel_dp *intel_dp)
4317 {
4318         struct drm_device *dev = intel_dp_to_dev(intel_dp);
4319         enum drm_connector_status status;
4320
4321         status = intel_panel_detect(dev);
4322         if (status == connector_status_unknown)
4323                 status = connector_status_connected;
4324
4325         return status;
4326 }
4327
4328 static bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
4329                                        struct intel_digital_port *port)
4330 {
4331         u32 bit;
4332
4333         switch (port->port) {
4334         case PORT_A:
4335                 return true;
4336         case PORT_B:
4337                 bit = SDE_PORTB_HOTPLUG;
4338                 break;
4339         case PORT_C:
4340                 bit = SDE_PORTC_HOTPLUG;
4341                 break;
4342         case PORT_D:
4343                 bit = SDE_PORTD_HOTPLUG;
4344                 break;
4345         default:
4346                 MISSING_CASE(port->port);
4347                 return false;
4348         }
4349
4350         return I915_READ(SDEISR) & bit;
4351 }
4352
4353 static bool cpt_digital_port_connected(struct drm_i915_private *dev_priv,
4354                                        struct intel_digital_port *port)
4355 {
4356         u32 bit;
4357
4358         switch (port->port) {
4359         case PORT_A:
4360                 return true;
4361         case PORT_B:
4362                 bit = SDE_PORTB_HOTPLUG_CPT;
4363                 break;
4364         case PORT_C:
4365                 bit = SDE_PORTC_HOTPLUG_CPT;
4366                 break;
4367         case PORT_D:
4368                 bit = SDE_PORTD_HOTPLUG_CPT;
4369                 break;
4370         case PORT_E:
4371                 bit = SDE_PORTE_HOTPLUG_SPT;
4372                 break;
4373         default:
4374                 MISSING_CASE(port->port);
4375                 return false;
4376         }
4377
4378         return I915_READ(SDEISR) & bit;
4379 }
4380
4381 static bool g4x_digital_port_connected(struct drm_i915_private *dev_priv,
4382                                        struct intel_digital_port *port)
4383 {
4384         u32 bit;
4385
4386         switch (port->port) {
4387         case PORT_B:
4388                 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4389                 break;
4390         case PORT_C:
4391                 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4392                 break;
4393         case PORT_D:
4394                 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4395                 break;
4396         default:
4397                 MISSING_CASE(port->port);
4398                 return false;
4399         }
4400
4401         return I915_READ(PORT_HOTPLUG_STAT) & bit;
4402 }
4403
4404 static bool gm45_digital_port_connected(struct drm_i915_private *dev_priv,
4405                                         struct intel_digital_port *port)
4406 {
4407         u32 bit;
4408
4409         switch (port->port) {
4410         case PORT_B:
4411                 bit = PORTB_HOTPLUG_LIVE_STATUS_GM45;
4412                 break;
4413         case PORT_C:
4414                 bit = PORTC_HOTPLUG_LIVE_STATUS_GM45;
4415                 break;
4416         case PORT_D:
4417                 bit = PORTD_HOTPLUG_LIVE_STATUS_GM45;
4418                 break;
4419         default:
4420                 MISSING_CASE(port->port);
4421                 return false;
4422         }
4423
4424         return I915_READ(PORT_HOTPLUG_STAT) & bit;
4425 }
4426
4427 static bool bxt_digital_port_connected(struct drm_i915_private *dev_priv,
4428                                        struct intel_digital_port *intel_dig_port)
4429 {
4430         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4431         enum port port;
4432         u32 bit;
4433
4434         intel_hpd_pin_to_port(intel_encoder->hpd_pin, &port);
4435         switch (port) {
4436         case PORT_A:
4437                 bit = BXT_DE_PORT_HP_DDIA;
4438                 break;
4439         case PORT_B:
4440                 bit = BXT_DE_PORT_HP_DDIB;
4441                 break;
4442         case PORT_C:
4443                 bit = BXT_DE_PORT_HP_DDIC;
4444                 break;
4445         default:
4446                 MISSING_CASE(port);
4447                 return false;
4448         }
4449
4450         return I915_READ(GEN8_DE_PORT_ISR) & bit;
4451 }
4452
4453 /*
4454  * intel_digital_port_connected - is the specified port connected?
4455  * @dev_priv: i915 private structure
4456  * @port: the port to test
4457  *
4458  * Return %true if @port is connected, %false otherwise.
4459  */
4460 bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
4461                                          struct intel_digital_port *port)
4462 {
4463         if (HAS_PCH_IBX(dev_priv))
4464                 return ibx_digital_port_connected(dev_priv, port);
4465         else if (HAS_PCH_SPLIT(dev_priv))
4466                 return cpt_digital_port_connected(dev_priv, port);
4467         else if (IS_BROXTON(dev_priv))
4468                 return bxt_digital_port_connected(dev_priv, port);
4469         else if (IS_GM45(dev_priv))
4470                 return gm45_digital_port_connected(dev_priv, port);
4471         else
4472                 return g4x_digital_port_connected(dev_priv, port);
4473 }
4474
4475 static struct edid *
4476 intel_dp_get_edid(struct intel_dp *intel_dp)
4477 {
4478         struct intel_connector *intel_connector = intel_dp->attached_connector;
4479
4480         /* use cached edid if we have one */
4481         if (intel_connector->edid) {
4482                 /* invalid edid */
4483                 if (IS_ERR(intel_connector->edid))
4484                         return NULL;
4485
4486                 return drm_edid_duplicate(intel_connector->edid);
4487         } else
4488                 return drm_get_edid(&intel_connector->base,
4489                                     &intel_dp->aux.ddc);
4490 }
4491
4492 static void
4493 intel_dp_set_edid(struct intel_dp *intel_dp)
4494 {
4495         struct intel_connector *intel_connector = intel_dp->attached_connector;
4496         struct edid *edid;
4497
4498         intel_dp_unset_edid(intel_dp);
4499         edid = intel_dp_get_edid(intel_dp);
4500         intel_connector->detect_edid = edid;
4501
4502         if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
4503                 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
4504         else
4505                 intel_dp->has_audio = drm_detect_monitor_audio(edid);
4506 }
4507
4508 static void
4509 intel_dp_unset_edid(struct intel_dp *intel_dp)
4510 {
4511         struct intel_connector *intel_connector = intel_dp->attached_connector;
4512
4513         kfree(intel_connector->detect_edid);
4514         intel_connector->detect_edid = NULL;
4515
4516         intel_dp->has_audio = false;
4517 }
4518
4519 static void
4520 intel_dp_long_pulse(struct intel_connector *intel_connector)
4521 {
4522         struct drm_connector *connector = &intel_connector->base;
4523         struct intel_dp *intel_dp = intel_attached_dp(connector);
4524         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4525         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4526         struct drm_device *dev = connector->dev;
4527         enum drm_connector_status status;
4528         enum intel_display_power_domain power_domain;
4529         bool ret;
4530         u8 sink_irq_vector;
4531
4532         power_domain = intel_display_port_aux_power_domain(intel_encoder);
4533         intel_display_power_get(to_i915(dev), power_domain);
4534
4535         /* Can't disconnect eDP, but you can close the lid... */
4536         if (is_edp(intel_dp))
4537                 status = edp_detect(intel_dp);
4538         else if (intel_digital_port_connected(to_i915(dev),
4539                                               dp_to_dig_port(intel_dp)))
4540                 status = intel_dp_detect_dpcd(intel_dp);
4541         else
4542                 status = connector_status_disconnected;
4543
4544         if (status != connector_status_connected) {
4545                 intel_dp->compliance_test_active = 0;
4546                 intel_dp->compliance_test_type = 0;
4547                 intel_dp->compliance_test_data = 0;
4548
4549                 if (intel_dp->is_mst) {
4550                         DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4551                                       intel_dp->is_mst,
4552                                       intel_dp->mst_mgr.mst_state);
4553                         intel_dp->is_mst = false;
4554                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4555                                                         intel_dp->is_mst);
4556                 }
4557
4558                 goto out;
4559         }
4560
4561         if (intel_encoder->type != INTEL_OUTPUT_EDP)
4562                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4563
4564         intel_dp_probe_oui(intel_dp);
4565
4566         ret = intel_dp_probe_mst(intel_dp);
4567         if (ret) {
4568                 /*
4569                  * If we are in MST mode then this connector
4570                  * won't appear connected or have anything
4571                  * with EDID on it
4572                  */
4573                 status = connector_status_disconnected;
4574                 goto out;
4575         } else if (connector->status == connector_status_connected) {
4576                 /*
4577                  * If display was connected already and is still connected
4578                  * check links status, there has been known issues of
4579                  * link loss triggerring long pulse!!!!
4580                  */
4581                 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4582                 intel_dp_check_link_status(intel_dp);
4583                 drm_modeset_unlock(&dev->mode_config.connection_mutex);
4584                 goto out;
4585         }
4586
4587         /*
4588          * Clearing NACK and defer counts to get their exact values
4589          * while reading EDID which are required by Compliance tests
4590          * 4.2.2.4 and 4.2.2.5
4591          */
4592         intel_dp->aux.i2c_nack_count = 0;
4593         intel_dp->aux.i2c_defer_count = 0;
4594
4595         intel_dp_set_edid(intel_dp);
4596
4597         status = connector_status_connected;
4598         intel_dp->detect_done = true;
4599
4600         /* Try to read the source of the interrupt */
4601         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4602             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
4603                 /* Clear interrupt source */
4604                 drm_dp_dpcd_writeb(&intel_dp->aux,
4605                                    DP_DEVICE_SERVICE_IRQ_VECTOR,
4606                                    sink_irq_vector);
4607
4608                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4609                         intel_dp_handle_test_request(intel_dp);
4610                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4611                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4612         }
4613
4614 out:
4615         if ((status != connector_status_connected) &&
4616             (intel_dp->is_mst == false))
4617                 intel_dp_unset_edid(intel_dp);
4618
4619         intel_display_power_put(to_i915(dev), power_domain);
4620         return;
4621 }
4622
4623 static enum drm_connector_status
4624 intel_dp_detect(struct drm_connector *connector, bool force)
4625 {
4626         struct intel_dp *intel_dp = intel_attached_dp(connector);
4627         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4628         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4629         struct intel_connector *intel_connector = to_intel_connector(connector);
4630
4631         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4632                       connector->base.id, connector->name);
4633
4634         if (intel_dp->is_mst) {
4635                 /* MST devices are disconnected from a monitor POV */
4636                 intel_dp_unset_edid(intel_dp);
4637                 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4638                         intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4639                 return connector_status_disconnected;
4640         }
4641
4642         /* If full detect is not performed yet, do a full detect */
4643         if (!intel_dp->detect_done)
4644                 intel_dp_long_pulse(intel_dp->attached_connector);
4645
4646         intel_dp->detect_done = false;
4647
4648         if (intel_connector->detect_edid)
4649                 return connector_status_connected;
4650         else
4651                 return connector_status_disconnected;
4652 }
4653
4654 static void
4655 intel_dp_force(struct drm_connector *connector)
4656 {
4657         struct intel_dp *intel_dp = intel_attached_dp(connector);
4658         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4659         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
4660         enum intel_display_power_domain power_domain;
4661
4662         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4663                       connector->base.id, connector->name);
4664         intel_dp_unset_edid(intel_dp);
4665
4666         if (connector->status != connector_status_connected)
4667                 return;
4668
4669         power_domain = intel_display_port_aux_power_domain(intel_encoder);
4670         intel_display_power_get(dev_priv, power_domain);
4671
4672         intel_dp_set_edid(intel_dp);
4673
4674         intel_display_power_put(dev_priv, power_domain);
4675
4676         if (intel_encoder->type != INTEL_OUTPUT_EDP)
4677                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4678 }
4679
4680 static int intel_dp_get_modes(struct drm_connector *connector)
4681 {
4682         struct intel_connector *intel_connector = to_intel_connector(connector);
4683         struct edid *edid;
4684
4685         edid = intel_connector->detect_edid;
4686         if (edid) {
4687                 int ret = intel_connector_update_modes(connector, edid);
4688                 if (ret)
4689                         return ret;
4690         }
4691
4692         /* if eDP has no EDID, fall back to fixed mode */
4693         if (is_edp(intel_attached_dp(connector)) &&
4694             intel_connector->panel.fixed_mode) {
4695                 struct drm_display_mode *mode;
4696
4697                 mode = drm_mode_duplicate(connector->dev,
4698                                           intel_connector->panel.fixed_mode);
4699                 if (mode) {
4700                         drm_mode_probed_add(connector, mode);
4701                         return 1;
4702                 }
4703         }
4704
4705         return 0;
4706 }
4707
4708 static bool
4709 intel_dp_detect_audio(struct drm_connector *connector)
4710 {
4711         bool has_audio = false;
4712         struct edid *edid;
4713
4714         edid = to_intel_connector(connector)->detect_edid;
4715         if (edid)
4716                 has_audio = drm_detect_monitor_audio(edid);
4717
4718         return has_audio;
4719 }
4720
4721 static int
4722 intel_dp_set_property(struct drm_connector *connector,
4723                       struct drm_property *property,
4724                       uint64_t val)
4725 {
4726         struct drm_i915_private *dev_priv = connector->dev->dev_private;
4727         struct intel_connector *intel_connector = to_intel_connector(connector);
4728         struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
4729         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4730         int ret;
4731
4732         ret = drm_object_property_set_value(&connector->base, property, val);
4733         if (ret)
4734                 return ret;
4735
4736         if (property == dev_priv->force_audio_property) {
4737                 int i = val;
4738                 bool has_audio;
4739
4740                 if (i == intel_dp->force_audio)
4741                         return 0;
4742
4743                 intel_dp->force_audio = i;
4744
4745                 if (i == HDMI_AUDIO_AUTO)
4746                         has_audio = intel_dp_detect_audio(connector);
4747                 else
4748                         has_audio = (i == HDMI_AUDIO_ON);
4749
4750                 if (has_audio == intel_dp->has_audio)
4751                         return 0;
4752
4753                 intel_dp->has_audio = has_audio;
4754                 goto done;
4755         }
4756
4757         if (property == dev_priv->broadcast_rgb_property) {
4758                 bool old_auto = intel_dp->color_range_auto;
4759                 bool old_range = intel_dp->limited_color_range;
4760
4761                 switch (val) {
4762                 case INTEL_BROADCAST_RGB_AUTO:
4763                         intel_dp->color_range_auto = true;
4764                         break;
4765                 case INTEL_BROADCAST_RGB_FULL:
4766                         intel_dp->color_range_auto = false;
4767                         intel_dp->limited_color_range = false;
4768                         break;
4769                 case INTEL_BROADCAST_RGB_LIMITED:
4770                         intel_dp->color_range_auto = false;
4771                         intel_dp->limited_color_range = true;
4772                         break;
4773                 default:
4774                         return -EINVAL;
4775                 }
4776
4777                 if (old_auto == intel_dp->color_range_auto &&
4778                     old_range == intel_dp->limited_color_range)
4779                         return 0;
4780
4781                 goto done;
4782         }
4783
4784         if (is_edp(intel_dp) &&
4785             property == connector->dev->mode_config.scaling_mode_property) {
4786                 if (val == DRM_MODE_SCALE_NONE) {
4787                         DRM_DEBUG_KMS("no scaling not supported\n");
4788                         return -EINVAL;
4789                 }
4790                 if (HAS_GMCH_DISPLAY(dev_priv) &&
4791                     val == DRM_MODE_SCALE_CENTER) {
4792                         DRM_DEBUG_KMS("centering not supported\n");
4793                         return -EINVAL;
4794                 }
4795
4796                 if (intel_connector->panel.fitting_mode == val) {
4797                         /* the eDP scaling property is not changed */
4798                         return 0;
4799                 }
4800                 intel_connector->panel.fitting_mode = val;
4801
4802                 goto done;
4803         }
4804
4805         return -EINVAL;
4806
4807 done:
4808         if (intel_encoder->base.crtc)
4809                 intel_crtc_restore_mode(intel_encoder->base.crtc);
4810
4811         return 0;
4812 }
4813
4814 static void
4815 intel_dp_connector_destroy(struct drm_connector *connector)
4816 {
4817         struct intel_connector *intel_connector = to_intel_connector(connector);
4818
4819         kfree(intel_connector->detect_edid);
4820
4821         if (!IS_ERR_OR_NULL(intel_connector->edid))
4822                 kfree(intel_connector->edid);
4823
4824         /* Can't call is_edp() since the encoder may have been destroyed
4825          * already. */
4826         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4827                 intel_panel_fini(&intel_connector->panel);
4828
4829         drm_connector_cleanup(connector);
4830         kfree(connector);
4831 }
4832
4833 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
4834 {
4835         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4836         struct intel_dp *intel_dp = &intel_dig_port->dp;
4837
4838         intel_dp_mst_encoder_cleanup(intel_dig_port);
4839         if (is_edp(intel_dp)) {
4840                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4841                 /*
4842                  * vdd might still be enabled do to the delayed vdd off.
4843                  * Make sure vdd is actually turned off here.
4844                  */
4845                 pps_lock(intel_dp);
4846                 edp_panel_vdd_off_sync(intel_dp);
4847                 pps_unlock(intel_dp);
4848
4849                 if (intel_dp->edp_notifier.notifier_call) {
4850                         unregister_reboot_notifier(&intel_dp->edp_notifier);
4851                         intel_dp->edp_notifier.notifier_call = NULL;
4852                 }
4853         }
4854         drm_encoder_cleanup(encoder);
4855         kfree(intel_dig_port);
4856 }
4857
4858 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4859 {
4860         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4861
4862         if (!is_edp(intel_dp))
4863                 return;
4864
4865         /*
4866          * vdd might still be enabled do to the delayed vdd off.
4867          * Make sure vdd is actually turned off here.
4868          */
4869         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4870         pps_lock(intel_dp);
4871         edp_panel_vdd_off_sync(intel_dp);
4872         pps_unlock(intel_dp);
4873 }
4874
4875 static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
4876 {
4877         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4878         struct drm_device *dev = intel_dig_port->base.base.dev;
4879         struct drm_i915_private *dev_priv = dev->dev_private;
4880         enum intel_display_power_domain power_domain;
4881
4882         lockdep_assert_held(&dev_priv->pps_mutex);
4883
4884         if (!edp_have_panel_vdd(intel_dp))
4885                 return;
4886
4887         /*
4888          * The VDD bit needs a power domain reference, so if the bit is
4889          * already enabled when we boot or resume, grab this reference and
4890          * schedule a vdd off, so we don't hold on to the reference
4891          * indefinitely.
4892          */
4893         DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4894         power_domain = intel_display_port_aux_power_domain(&intel_dig_port->base);
4895         intel_display_power_get(dev_priv, power_domain);
4896
4897         edp_panel_vdd_schedule_off(intel_dp);
4898 }
4899
4900 void intel_dp_encoder_reset(struct drm_encoder *encoder)
4901 {
4902         struct intel_dp *intel_dp;
4903
4904         if (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP)
4905                 return;
4906
4907         intel_dp = enc_to_intel_dp(encoder);
4908
4909         pps_lock(intel_dp);
4910
4911         /*
4912          * Read out the current power sequencer assignment,
4913          * in case the BIOS did something with it.
4914          */
4915         if (IS_VALLEYVIEW(encoder->dev) || IS_CHERRYVIEW(encoder->dev))
4916                 vlv_initial_power_sequencer_setup(intel_dp);
4917
4918         intel_edp_panel_vdd_sanitize(intel_dp);
4919
4920         pps_unlock(intel_dp);
4921 }
4922
4923 static const struct drm_connector_funcs intel_dp_connector_funcs = {
4924         .dpms = drm_atomic_helper_connector_dpms,
4925         .detect = intel_dp_detect,
4926         .force = intel_dp_force,
4927         .fill_modes = drm_helper_probe_single_connector_modes,
4928         .set_property = intel_dp_set_property,
4929         .atomic_get_property = intel_connector_atomic_get_property,
4930         .destroy = intel_dp_connector_destroy,
4931         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
4932         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
4933 };
4934
4935 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4936         .get_modes = intel_dp_get_modes,
4937         .mode_valid = intel_dp_mode_valid,
4938         .best_encoder = intel_best_encoder,
4939 };
4940
4941 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
4942         .reset = intel_dp_encoder_reset,
4943         .destroy = intel_dp_encoder_destroy,
4944 };
4945
4946 enum irqreturn
4947 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4948 {
4949         struct intel_dp *intel_dp = &intel_dig_port->dp;
4950         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4951         struct drm_device *dev = intel_dig_port->base.base.dev;
4952         struct drm_i915_private *dev_priv = dev->dev_private;
4953         enum intel_display_power_domain power_domain;
4954         enum irqreturn ret = IRQ_NONE;
4955
4956         if (intel_dig_port->base.type != INTEL_OUTPUT_EDP &&
4957             intel_dig_port->base.type != INTEL_OUTPUT_HDMI)
4958                 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
4959
4960         if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
4961                 /*
4962                  * vdd off can generate a long pulse on eDP which
4963                  * would require vdd on to handle it, and thus we
4964                  * would end up in an endless cycle of
4965                  * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
4966                  */
4967                 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
4968                               port_name(intel_dig_port->port));
4969                 return IRQ_HANDLED;
4970         }
4971
4972         DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4973                       port_name(intel_dig_port->port),
4974                       long_hpd ? "long" : "short");
4975
4976         power_domain = intel_display_port_aux_power_domain(intel_encoder);
4977         intel_display_power_get(dev_priv, power_domain);
4978
4979         if (long_hpd) {
4980                 /* indicate that we need to restart link training */
4981                 intel_dp->train_set_valid = false;
4982
4983                 intel_dp_long_pulse(intel_dp->attached_connector);
4984                 if (intel_dp->is_mst)
4985                         ret = IRQ_HANDLED;
4986                 goto put_power;
4987
4988         } else {
4989                 if (intel_dp->is_mst) {
4990                         if (intel_dp_check_mst_status(intel_dp) == -EINVAL) {
4991                                 /*
4992                                  * If we were in MST mode, and device is not
4993                                  * there, get out of MST mode
4994                                  */
4995                                 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4996                                               intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4997                                 intel_dp->is_mst = false;
4998                                 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4999                                                                 intel_dp->is_mst);
5000                                 goto put_power;
5001                         }
5002                 }
5003
5004                 if (!intel_dp->is_mst) {
5005                         if (!intel_dp_short_pulse(intel_dp)) {
5006                                 intel_dp_long_pulse(intel_dp->attached_connector);
5007                                 goto put_power;
5008                         }
5009                 }
5010         }
5011
5012         ret = IRQ_HANDLED;
5013
5014 put_power:
5015         intel_display_power_put(dev_priv, power_domain);
5016
5017         return ret;
5018 }
5019
5020 /* check the VBT to see whether the eDP is on another port */
5021 bool intel_dp_is_edp(struct drm_device *dev, enum port port)
5022 {
5023         struct drm_i915_private *dev_priv = dev->dev_private;
5024
5025         /*
5026          * eDP not supported on g4x. so bail out early just
5027          * for a bit extra safety in case the VBT is bonkers.
5028          */
5029         if (INTEL_INFO(dev)->gen < 5)
5030                 return false;
5031
5032         if (port == PORT_A)
5033                 return true;
5034
5035         return intel_bios_is_port_edp(dev_priv, port);
5036 }
5037
5038 void
5039 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
5040 {
5041         struct intel_connector *intel_connector = to_intel_connector(connector);
5042
5043         intel_attach_force_audio_property(connector);
5044         intel_attach_broadcast_rgb_property(connector);
5045         intel_dp->color_range_auto = true;
5046
5047         if (is_edp(intel_dp)) {
5048                 drm_mode_create_scaling_mode_property(connector->dev);
5049                 drm_object_attach_property(
5050                         &connector->base,
5051                         connector->dev->mode_config.scaling_mode_property,
5052                         DRM_MODE_SCALE_ASPECT);
5053                 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
5054         }
5055 }
5056
5057 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
5058 {
5059         intel_dp->panel_power_off_time = ktime_get_boottime();
5060         intel_dp->last_power_on = jiffies;
5061         intel_dp->last_backlight_off = jiffies;
5062 }
5063
5064 static void
5065 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
5066                                     struct intel_dp *intel_dp)
5067 {
5068         struct drm_i915_private *dev_priv = dev->dev_private;
5069         struct edp_power_seq cur, vbt, spec,
5070                 *final = &intel_dp->pps_delays;
5071         u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0;
5072         i915_reg_t pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
5073
5074         lockdep_assert_held(&dev_priv->pps_mutex);
5075
5076         /* already initialized? */
5077         if (final->t11_t12 != 0)
5078                 return;
5079
5080         if (IS_BROXTON(dev)) {
5081                 /*
5082                  * TODO: BXT has 2 sets of PPS registers.
5083                  * Correct Register for Broxton need to be identified
5084                  * using VBT. hardcoding for now
5085                  */
5086                 pp_ctrl_reg = BXT_PP_CONTROL(0);
5087                 pp_on_reg = BXT_PP_ON_DELAYS(0);
5088                 pp_off_reg = BXT_PP_OFF_DELAYS(0);
5089         } else if (HAS_PCH_SPLIT(dev)) {
5090                 pp_ctrl_reg = PCH_PP_CONTROL;
5091                 pp_on_reg = PCH_PP_ON_DELAYS;
5092                 pp_off_reg = PCH_PP_OFF_DELAYS;
5093                 pp_div_reg = PCH_PP_DIVISOR;
5094         } else {
5095                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
5096
5097                 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
5098                 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
5099                 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
5100                 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
5101         }
5102
5103         /* Workaround: Need to write PP_CONTROL with the unlock key as
5104          * the very first thing. */
5105         pp_ctl = ironlake_get_pp_control(intel_dp);
5106
5107         pp_on = I915_READ(pp_on_reg);
5108         pp_off = I915_READ(pp_off_reg);
5109         if (!IS_BROXTON(dev)) {
5110                 I915_WRITE(pp_ctrl_reg, pp_ctl);
5111                 pp_div = I915_READ(pp_div_reg);
5112         }
5113
5114         /* Pull timing values out of registers */
5115         cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
5116                 PANEL_POWER_UP_DELAY_SHIFT;
5117
5118         cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
5119                 PANEL_LIGHT_ON_DELAY_SHIFT;
5120
5121         cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
5122                 PANEL_LIGHT_OFF_DELAY_SHIFT;
5123
5124         cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
5125                 PANEL_POWER_DOWN_DELAY_SHIFT;
5126
5127         if (IS_BROXTON(dev)) {
5128                 u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
5129                         BXT_POWER_CYCLE_DELAY_SHIFT;
5130                 if (tmp > 0)
5131                         cur.t11_t12 = (tmp - 1) * 1000;
5132                 else
5133                         cur.t11_t12 = 0;
5134         } else {
5135                 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
5136                        PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
5137         }
5138
5139         DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5140                       cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
5141
5142         vbt = dev_priv->vbt.edp.pps;
5143
5144         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
5145          * our hw here, which are all in 100usec. */
5146         spec.t1_t3 = 210 * 10;
5147         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
5148         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
5149         spec.t10 = 500 * 10;
5150         /* This one is special and actually in units of 100ms, but zero
5151          * based in the hw (so we need to add 100 ms). But the sw vbt
5152          * table multiplies it with 1000 to make it in units of 100usec,
5153          * too. */
5154         spec.t11_t12 = (510 + 100) * 10;
5155
5156         DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5157                       vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
5158
5159         /* Use the max of the register settings and vbt. If both are
5160          * unset, fall back to the spec limits. */
5161 #define assign_final(field)     final->field = (max(cur.field, vbt.field) == 0 ? \
5162                                        spec.field : \
5163                                        max(cur.field, vbt.field))
5164         assign_final(t1_t3);
5165         assign_final(t8);
5166         assign_final(t9);
5167         assign_final(t10);
5168         assign_final(t11_t12);
5169 #undef assign_final
5170
5171 #define get_delay(field)        (DIV_ROUND_UP(final->field, 10))
5172         intel_dp->panel_power_up_delay = get_delay(t1_t3);
5173         intel_dp->backlight_on_delay = get_delay(t8);
5174         intel_dp->backlight_off_delay = get_delay(t9);
5175         intel_dp->panel_power_down_delay = get_delay(t10);
5176         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
5177 #undef get_delay
5178
5179         DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
5180                       intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
5181                       intel_dp->panel_power_cycle_delay);
5182
5183         DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
5184                       intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
5185 }
5186
5187 static void
5188 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
5189                                               struct intel_dp *intel_dp)
5190 {
5191         struct drm_i915_private *dev_priv = dev->dev_private;
5192         u32 pp_on, pp_off, pp_div, port_sel = 0;
5193         int div = dev_priv->rawclk_freq / 1000;
5194         i915_reg_t pp_on_reg, pp_off_reg, pp_div_reg, pp_ctrl_reg;
5195         enum port port = dp_to_dig_port(intel_dp)->port;
5196         const struct edp_power_seq *seq = &intel_dp->pps_delays;
5197
5198         lockdep_assert_held(&dev_priv->pps_mutex);
5199
5200         if (IS_BROXTON(dev)) {
5201                 /*
5202                  * TODO: BXT has 2 sets of PPS registers.
5203                  * Correct Register for Broxton need to be identified
5204                  * using VBT. hardcoding for now
5205                  */
5206                 pp_ctrl_reg = BXT_PP_CONTROL(0);
5207                 pp_on_reg = BXT_PP_ON_DELAYS(0);
5208                 pp_off_reg = BXT_PP_OFF_DELAYS(0);
5209
5210         } else if (HAS_PCH_SPLIT(dev)) {
5211                 pp_on_reg = PCH_PP_ON_DELAYS;
5212                 pp_off_reg = PCH_PP_OFF_DELAYS;
5213                 pp_div_reg = PCH_PP_DIVISOR;
5214         } else {
5215                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
5216
5217                 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
5218                 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
5219                 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
5220         }
5221
5222         /*
5223          * And finally store the new values in the power sequencer. The
5224          * backlight delays are set to 1 because we do manual waits on them. For
5225          * T8, even BSpec recommends doing it. For T9, if we don't do this,
5226          * we'll end up waiting for the backlight off delay twice: once when we
5227          * do the manual sleep, and once when we disable the panel and wait for
5228          * the PP_STATUS bit to become zero.
5229          */
5230         pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
5231                 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
5232         pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
5233                  (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
5234         /* Compute the divisor for the pp clock, simply match the Bspec
5235          * formula. */
5236         if (IS_BROXTON(dev)) {
5237                 pp_div = I915_READ(pp_ctrl_reg);
5238                 pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
5239                 pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000)
5240                                 << BXT_POWER_CYCLE_DELAY_SHIFT);
5241         } else {
5242                 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
5243                 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
5244                                 << PANEL_POWER_CYCLE_DELAY_SHIFT);
5245         }
5246
5247         /* Haswell doesn't have any port selection bits for the panel
5248          * power sequencer any more. */
5249         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
5250                 port_sel = PANEL_PORT_SELECT_VLV(port);
5251         } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5252                 if (port == PORT_A)
5253                         port_sel = PANEL_PORT_SELECT_DPA;
5254                 else
5255                         port_sel = PANEL_PORT_SELECT_DPD;
5256         }
5257
5258         pp_on |= port_sel;
5259
5260         I915_WRITE(pp_on_reg, pp_on);
5261         I915_WRITE(pp_off_reg, pp_off);
5262         if (IS_BROXTON(dev))
5263                 I915_WRITE(pp_ctrl_reg, pp_div);
5264         else
5265                 I915_WRITE(pp_div_reg, pp_div);
5266
5267         DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
5268                       I915_READ(pp_on_reg),
5269                       I915_READ(pp_off_reg),
5270                       IS_BROXTON(dev) ?
5271                       (I915_READ(pp_ctrl_reg) & BXT_POWER_CYCLE_DELAY_MASK) :
5272                       I915_READ(pp_div_reg));
5273 }
5274
5275 /**
5276  * intel_dp_set_drrs_state - program registers for RR switch to take effect
5277  * @dev: DRM device
5278  * @refresh_rate: RR to be programmed
5279  *
5280  * This function gets called when refresh rate (RR) has to be changed from
5281  * one frequency to another. Switches can be between high and low RR
5282  * supported by the panel or to any other RR based on media playback (in
5283  * this case, RR value needs to be passed from user space).
5284  *
5285  * The caller of this function needs to take a lock on dev_priv->drrs.
5286  */
5287 static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
5288 {
5289         struct drm_i915_private *dev_priv = dev->dev_private;
5290         struct intel_encoder *encoder;
5291         struct intel_digital_port *dig_port = NULL;
5292         struct intel_dp *intel_dp = dev_priv->drrs.dp;
5293         struct intel_crtc_state *config = NULL;
5294         struct intel_crtc *intel_crtc = NULL;
5295         enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
5296
5297         if (refresh_rate <= 0) {
5298                 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
5299                 return;
5300         }
5301
5302         if (intel_dp == NULL) {
5303                 DRM_DEBUG_KMS("DRRS not supported.\n");
5304                 return;
5305         }
5306
5307         /*
5308          * FIXME: This needs proper synchronization with psr state for some
5309          * platforms that cannot have PSR and DRRS enabled at the same time.
5310          */
5311
5312         dig_port = dp_to_dig_port(intel_dp);
5313         encoder = &dig_port->base;
5314         intel_crtc = to_intel_crtc(encoder->base.crtc);
5315
5316         if (!intel_crtc) {
5317                 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5318                 return;
5319         }
5320
5321         config = intel_crtc->config;
5322
5323         if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
5324                 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5325                 return;
5326         }
5327
5328         if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
5329                         refresh_rate)
5330                 index = DRRS_LOW_RR;
5331
5332         if (index == dev_priv->drrs.refresh_rate_type) {
5333                 DRM_DEBUG_KMS(
5334                         "DRRS requested for previously set RR...ignoring\n");
5335                 return;
5336         }
5337
5338         if (!intel_crtc->active) {
5339                 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5340                 return;
5341         }
5342
5343         if (INTEL_INFO(dev)->gen >= 8 && !IS_CHERRYVIEW(dev)) {
5344                 switch (index) {
5345                 case DRRS_HIGH_RR:
5346                         intel_dp_set_m_n(intel_crtc, M1_N1);
5347                         break;
5348                 case DRRS_LOW_RR:
5349                         intel_dp_set_m_n(intel_crtc, M2_N2);
5350                         break;
5351                 case DRRS_MAX_RR:
5352                 default:
5353                         DRM_ERROR("Unsupported refreshrate type\n");
5354                 }
5355         } else if (INTEL_INFO(dev)->gen > 6) {
5356                 i915_reg_t reg = PIPECONF(intel_crtc->config->cpu_transcoder);
5357                 u32 val;
5358
5359                 val = I915_READ(reg);
5360                 if (index > DRRS_HIGH_RR) {
5361                         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
5362                                 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5363                         else
5364                                 val |= PIPECONF_EDP_RR_MODE_SWITCH;
5365                 } else {
5366                         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
5367                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5368                         else
5369                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
5370                 }
5371                 I915_WRITE(reg, val);
5372         }
5373
5374         dev_priv->drrs.refresh_rate_type = index;
5375
5376         DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
5377 }
5378
5379 /**
5380  * intel_edp_drrs_enable - init drrs struct if supported
5381  * @intel_dp: DP struct
5382  *
5383  * Initializes frontbuffer_bits and drrs.dp
5384  */
5385 void intel_edp_drrs_enable(struct intel_dp *intel_dp)
5386 {
5387         struct drm_device *dev = intel_dp_to_dev(intel_dp);
5388         struct drm_i915_private *dev_priv = dev->dev_private;
5389         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5390         struct drm_crtc *crtc = dig_port->base.base.crtc;
5391         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5392
5393         if (!intel_crtc->config->has_drrs) {
5394                 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
5395                 return;
5396         }
5397
5398         mutex_lock(&dev_priv->drrs.mutex);
5399         if (WARN_ON(dev_priv->drrs.dp)) {
5400                 DRM_ERROR("DRRS already enabled\n");
5401                 goto unlock;
5402         }
5403
5404         dev_priv->drrs.busy_frontbuffer_bits = 0;
5405
5406         dev_priv->drrs.dp = intel_dp;
5407
5408 unlock:
5409         mutex_unlock(&dev_priv->drrs.mutex);
5410 }
5411
5412 /**
5413  * intel_edp_drrs_disable - Disable DRRS
5414  * @intel_dp: DP struct
5415  *
5416  */
5417 void intel_edp_drrs_disable(struct intel_dp *intel_dp)
5418 {
5419         struct drm_device *dev = intel_dp_to_dev(intel_dp);
5420         struct drm_i915_private *dev_priv = dev->dev_private;
5421         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5422         struct drm_crtc *crtc = dig_port->base.base.crtc;
5423         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5424
5425         if (!intel_crtc->config->has_drrs)
5426                 return;
5427
5428         mutex_lock(&dev_priv->drrs.mutex);
5429         if (!dev_priv->drrs.dp) {
5430                 mutex_unlock(&dev_priv->drrs.mutex);
5431                 return;
5432         }
5433
5434         if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5435                 intel_dp_set_drrs_state(dev_priv->dev,
5436                         intel_dp->attached_connector->panel.
5437                         fixed_mode->vrefresh);
5438
5439         dev_priv->drrs.dp = NULL;
5440         mutex_unlock(&dev_priv->drrs.mutex);
5441
5442         cancel_delayed_work_sync(&dev_priv->drrs.work);
5443 }
5444
5445 static void intel_edp_drrs_downclock_work(struct work_struct *work)
5446 {
5447         struct drm_i915_private *dev_priv =
5448                 container_of(work, typeof(*dev_priv), drrs.work.work);
5449         struct intel_dp *intel_dp;
5450
5451         mutex_lock(&dev_priv->drrs.mutex);
5452
5453         intel_dp = dev_priv->drrs.dp;
5454
5455         if (!intel_dp)
5456                 goto unlock;
5457
5458         /*
5459          * The delayed work can race with an invalidate hence we need to
5460          * recheck.
5461          */
5462
5463         if (dev_priv->drrs.busy_frontbuffer_bits)
5464                 goto unlock;
5465
5466         if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR)
5467                 intel_dp_set_drrs_state(dev_priv->dev,
5468                         intel_dp->attached_connector->panel.
5469                         downclock_mode->vrefresh);
5470
5471 unlock:
5472         mutex_unlock(&dev_priv->drrs.mutex);
5473 }
5474
5475 /**
5476  * intel_edp_drrs_invalidate - Disable Idleness DRRS
5477  * @dev: DRM device
5478  * @frontbuffer_bits: frontbuffer plane tracking bits
5479  *
5480  * This function gets called everytime rendering on the given planes start.
5481  * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
5482  *
5483  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5484  */
5485 void intel_edp_drrs_invalidate(struct drm_device *dev,
5486                 unsigned frontbuffer_bits)
5487 {
5488         struct drm_i915_private *dev_priv = dev->dev_private;
5489         struct drm_crtc *crtc;
5490         enum pipe pipe;
5491
5492         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5493                 return;
5494
5495         cancel_delayed_work(&dev_priv->drrs.work);
5496
5497         mutex_lock(&dev_priv->drrs.mutex);
5498         if (!dev_priv->drrs.dp) {
5499                 mutex_unlock(&dev_priv->drrs.mutex);
5500                 return;
5501         }
5502
5503         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5504         pipe = to_intel_crtc(crtc)->pipe;
5505
5506         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5507         dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
5508
5509         /* invalidate means busy screen hence upclock */
5510         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5511                 intel_dp_set_drrs_state(dev_priv->dev,
5512                                 dev_priv->drrs.dp->attached_connector->panel.
5513                                 fixed_mode->vrefresh);
5514
5515         mutex_unlock(&dev_priv->drrs.mutex);
5516 }
5517
5518 /**
5519  * intel_edp_drrs_flush - Restart Idleness DRRS
5520  * @dev: DRM device
5521  * @frontbuffer_bits: frontbuffer plane tracking bits
5522  *
5523  * This function gets called every time rendering on the given planes has
5524  * completed or flip on a crtc is completed. So DRRS should be upclocked
5525  * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
5526  * if no other planes are dirty.
5527  *
5528  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5529  */
5530 void intel_edp_drrs_flush(struct drm_device *dev,
5531                 unsigned frontbuffer_bits)
5532 {
5533         struct drm_i915_private *dev_priv = dev->dev_private;
5534         struct drm_crtc *crtc;
5535         enum pipe pipe;
5536
5537         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5538                 return;
5539
5540         cancel_delayed_work(&dev_priv->drrs.work);
5541
5542         mutex_lock(&dev_priv->drrs.mutex);
5543         if (!dev_priv->drrs.dp) {
5544                 mutex_unlock(&dev_priv->drrs.mutex);
5545                 return;
5546         }
5547
5548         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5549         pipe = to_intel_crtc(crtc)->pipe;
5550
5551         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5552         dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
5553
5554         /* flush means busy screen hence upclock */
5555         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5556                 intel_dp_set_drrs_state(dev_priv->dev,
5557                                 dev_priv->drrs.dp->attached_connector->panel.
5558                                 fixed_mode->vrefresh);
5559
5560         /*
5561          * flush also means no more activity hence schedule downclock, if all
5562          * other fbs are quiescent too
5563          */
5564         if (!dev_priv->drrs.busy_frontbuffer_bits)
5565                 schedule_delayed_work(&dev_priv->drrs.work,
5566                                 msecs_to_jiffies(1000));
5567         mutex_unlock(&dev_priv->drrs.mutex);
5568 }
5569
5570 /**
5571  * DOC: Display Refresh Rate Switching (DRRS)
5572  *
5573  * Display Refresh Rate Switching (DRRS) is a power conservation feature
5574  * which enables swtching between low and high refresh rates,
5575  * dynamically, based on the usage scenario. This feature is applicable
5576  * for internal panels.
5577  *
5578  * Indication that the panel supports DRRS is given by the panel EDID, which
5579  * would list multiple refresh rates for one resolution.
5580  *
5581  * DRRS is of 2 types - static and seamless.
5582  * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5583  * (may appear as a blink on screen) and is used in dock-undock scenario.
5584  * Seamless DRRS involves changing RR without any visual effect to the user
5585  * and can be used during normal system usage. This is done by programming
5586  * certain registers.
5587  *
5588  * Support for static/seamless DRRS may be indicated in the VBT based on
5589  * inputs from the panel spec.
5590  *
5591  * DRRS saves power by switching to low RR based on usage scenarios.
5592  *
5593  * eDP DRRS:-
5594  *        The implementation is based on frontbuffer tracking implementation.
5595  * When there is a disturbance on the screen triggered by user activity or a
5596  * periodic system activity, DRRS is disabled (RR is changed to high RR).
5597  * When there is no movement on screen, after a timeout of 1 second, a switch
5598  * to low RR is made.
5599  *        For integration with frontbuffer tracking code,
5600  * intel_edp_drrs_invalidate() and intel_edp_drrs_flush() are called.
5601  *
5602  * DRRS can be further extended to support other internal panels and also
5603  * the scenario of video playback wherein RR is set based on the rate
5604  * requested by userspace.
5605  */
5606
5607 /**
5608  * intel_dp_drrs_init - Init basic DRRS work and mutex.
5609  * @intel_connector: eDP connector
5610  * @fixed_mode: preferred mode of panel
5611  *
5612  * This function is  called only once at driver load to initialize basic
5613  * DRRS stuff.
5614  *
5615  * Returns:
5616  * Downclock mode if panel supports it, else return NULL.
5617  * DRRS support is determined by the presence of downclock mode (apart
5618  * from VBT setting).
5619  */
5620 static struct drm_display_mode *
5621 intel_dp_drrs_init(struct intel_connector *intel_connector,
5622                 struct drm_display_mode *fixed_mode)
5623 {
5624         struct drm_connector *connector = &intel_connector->base;
5625         struct drm_device *dev = connector->dev;
5626         struct drm_i915_private *dev_priv = dev->dev_private;
5627         struct drm_display_mode *downclock_mode = NULL;
5628
5629         INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
5630         mutex_init(&dev_priv->drrs.mutex);
5631
5632         if (INTEL_INFO(dev)->gen <= 6) {
5633                 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5634                 return NULL;
5635         }
5636
5637         if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
5638                 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
5639                 return NULL;
5640         }
5641
5642         downclock_mode = intel_find_panel_downclock
5643                                         (dev, fixed_mode, connector);
5644
5645         if (!downclock_mode) {
5646                 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
5647                 return NULL;
5648         }
5649
5650         dev_priv->drrs.type = dev_priv->vbt.drrs_type;
5651
5652         dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
5653         DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
5654         return downclock_mode;
5655 }
5656
5657 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
5658                                      struct intel_connector *intel_connector)
5659 {
5660         struct drm_connector *connector = &intel_connector->base;
5661         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5662         struct intel_encoder *intel_encoder = &intel_dig_port->base;
5663         struct drm_device *dev = intel_encoder->base.dev;
5664         struct drm_i915_private *dev_priv = dev->dev_private;
5665         struct drm_display_mode *fixed_mode = NULL;
5666         struct drm_display_mode *downclock_mode = NULL;
5667         bool has_dpcd;
5668         struct drm_display_mode *scan;
5669         struct edid *edid;
5670         enum pipe pipe = INVALID_PIPE;
5671
5672         if (!is_edp(intel_dp))
5673                 return true;
5674
5675         pps_lock(intel_dp);
5676         intel_edp_panel_vdd_sanitize(intel_dp);
5677         pps_unlock(intel_dp);
5678
5679         /* Cache DPCD and EDID for edp. */
5680         has_dpcd = intel_dp_get_dpcd(intel_dp);
5681
5682         if (has_dpcd) {
5683                 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
5684                         dev_priv->no_aux_handshake =
5685                                 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
5686                                 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
5687         } else {
5688                 /* if this fails, presume the device is a ghost */
5689                 DRM_INFO("failed to retrieve link info, disabling eDP\n");
5690                 return false;
5691         }
5692
5693         /* We now know it's not a ghost, init power sequence regs. */
5694         pps_lock(intel_dp);
5695         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
5696         pps_unlock(intel_dp);
5697
5698         mutex_lock(&dev->mode_config.mutex);
5699         edid = drm_get_edid(connector, &intel_dp->aux.ddc);
5700         if (edid) {
5701                 if (drm_add_edid_modes(connector, edid)) {
5702                         drm_mode_connector_update_edid_property(connector,
5703                                                                 edid);
5704                         drm_edid_to_eld(connector, edid);
5705                 } else {
5706                         kfree(edid);
5707                         edid = ERR_PTR(-EINVAL);
5708                 }
5709         } else {
5710                 edid = ERR_PTR(-ENOENT);
5711         }
5712         intel_connector->edid = edid;
5713
5714         /* prefer fixed mode from EDID if available */
5715         list_for_each_entry(scan, &connector->probed_modes, head) {
5716                 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
5717                         fixed_mode = drm_mode_duplicate(dev, scan);
5718                         downclock_mode = intel_dp_drrs_init(
5719                                                 intel_connector, fixed_mode);
5720                         break;
5721                 }
5722         }
5723
5724         /* fallback to VBT if available for eDP */
5725         if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
5726                 fixed_mode = drm_mode_duplicate(dev,
5727                                         dev_priv->vbt.lfp_lvds_vbt_mode);
5728                 if (fixed_mode) {
5729                         fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
5730                         connector->display_info.width_mm = fixed_mode->width_mm;
5731                         connector->display_info.height_mm = fixed_mode->height_mm;
5732                 }
5733         }
5734         mutex_unlock(&dev->mode_config.mutex);
5735
5736         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
5737                 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
5738                 register_reboot_notifier(&intel_dp->edp_notifier);
5739
5740                 /*
5741                  * Figure out the current pipe for the initial backlight setup.
5742                  * If the current pipe isn't valid, try the PPS pipe, and if that
5743                  * fails just assume pipe A.
5744                  */
5745                 if (IS_CHERRYVIEW(dev))
5746                         pipe = DP_PORT_TO_PIPE_CHV(intel_dp->DP);
5747                 else
5748                         pipe = PORT_TO_PIPE(intel_dp->DP);
5749
5750                 if (pipe != PIPE_A && pipe != PIPE_B)
5751                         pipe = intel_dp->pps_pipe;
5752
5753                 if (pipe != PIPE_A && pipe != PIPE_B)
5754                         pipe = PIPE_A;
5755
5756                 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
5757                               pipe_name(pipe));
5758         }
5759
5760         intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
5761         intel_connector->panel.backlight.power = intel_edp_backlight_power;
5762         intel_panel_setup_backlight(connector, pipe);
5763
5764         return true;
5765 }
5766
5767 bool
5768 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
5769                         struct intel_connector *intel_connector)
5770 {
5771         struct drm_connector *connector = &intel_connector->base;
5772         struct intel_dp *intel_dp = &intel_dig_port->dp;
5773         struct intel_encoder *intel_encoder = &intel_dig_port->base;
5774         struct drm_device *dev = intel_encoder->base.dev;
5775         struct drm_i915_private *dev_priv = dev->dev_private;
5776         enum port port = intel_dig_port->port;
5777         int type, ret;
5778
5779         if (WARN(intel_dig_port->max_lanes < 1,
5780                  "Not enough lanes (%d) for DP on port %c\n",
5781                  intel_dig_port->max_lanes, port_name(port)))
5782                 return false;
5783
5784         intel_dp->pps_pipe = INVALID_PIPE;
5785
5786         /* intel_dp vfuncs */
5787         if (INTEL_INFO(dev)->gen >= 9)
5788                 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
5789         else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
5790                 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
5791         else if (HAS_PCH_SPLIT(dev))
5792                 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
5793         else
5794                 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
5795
5796         if (INTEL_INFO(dev)->gen >= 9)
5797                 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
5798         else
5799                 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
5800
5801         if (HAS_DDI(dev))
5802                 intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain;
5803
5804         /* Preserve the current hw state. */
5805         intel_dp->DP = I915_READ(intel_dp->output_reg);
5806         intel_dp->attached_connector = intel_connector;
5807
5808         if (intel_dp_is_edp(dev, port))
5809                 type = DRM_MODE_CONNECTOR_eDP;
5810         else
5811                 type = DRM_MODE_CONNECTOR_DisplayPort;
5812
5813         /*
5814          * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5815          * for DP the encoder type can be set by the caller to
5816          * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5817          */
5818         if (type == DRM_MODE_CONNECTOR_eDP)
5819                 intel_encoder->type = INTEL_OUTPUT_EDP;
5820
5821         /* eDP only on port B and/or C on vlv/chv */
5822         if (WARN_ON((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
5823                     is_edp(intel_dp) && port != PORT_B && port != PORT_C))
5824                 return false;
5825
5826         DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5827                         type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5828                         port_name(port));
5829
5830         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
5831         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5832
5833         connector->interlace_allowed = true;
5834         connector->doublescan_allowed = 0;
5835
5836         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
5837                           edp_panel_vdd_work);
5838
5839         intel_connector_attach_encoder(intel_connector, intel_encoder);
5840         drm_connector_register(connector);
5841
5842         if (HAS_DDI(dev))
5843                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5844         else
5845                 intel_connector->get_hw_state = intel_connector_get_hw_state;
5846         intel_connector->unregister = intel_dp_connector_unregister;
5847
5848         /* Set up the hotplug pin. */
5849         switch (port) {
5850         case PORT_A:
5851                 intel_encoder->hpd_pin = HPD_PORT_A;
5852                 break;
5853         case PORT_B:
5854                 intel_encoder->hpd_pin = HPD_PORT_B;
5855                 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
5856                         intel_encoder->hpd_pin = HPD_PORT_A;
5857                 break;
5858         case PORT_C:
5859                 intel_encoder->hpd_pin = HPD_PORT_C;
5860                 break;
5861         case PORT_D:
5862                 intel_encoder->hpd_pin = HPD_PORT_D;
5863                 break;
5864         case PORT_E:
5865                 intel_encoder->hpd_pin = HPD_PORT_E;
5866                 break;
5867         default:
5868                 BUG();
5869         }
5870
5871         if (is_edp(intel_dp)) {
5872                 pps_lock(intel_dp);
5873                 intel_dp_init_panel_power_timestamps(intel_dp);
5874                 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
5875                         vlv_initial_power_sequencer_setup(intel_dp);
5876                 else
5877                         intel_dp_init_panel_power_sequencer(dev, intel_dp);
5878                 pps_unlock(intel_dp);
5879         }
5880
5881         ret = intel_dp_aux_init(intel_dp, intel_connector);
5882         if (ret)
5883                 goto fail;
5884
5885         /* init MST on ports that can support it */
5886         if (HAS_DP_MST(dev) &&
5887             (port == PORT_B || port == PORT_C || port == PORT_D))
5888                 intel_dp_mst_encoder_init(intel_dig_port,
5889                                           intel_connector->base.base.id);
5890
5891         if (!intel_edp_init_connector(intel_dp, intel_connector)) {
5892                 intel_dp_aux_fini(intel_dp);
5893                 intel_dp_mst_encoder_cleanup(intel_dig_port);
5894                 goto fail;
5895         }
5896
5897         intel_dp_add_properties(intel_dp, connector);
5898
5899         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5900          * 0xd.  Failure to do so will result in spurious interrupts being
5901          * generated on the port when a cable is not attached.
5902          */
5903         if (IS_G4X(dev) && !IS_GM45(dev)) {
5904                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
5905                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
5906         }
5907
5908         i915_debugfs_connector_add(connector);
5909
5910         return true;
5911
5912 fail:
5913         if (is_edp(intel_dp)) {
5914                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5915                 /*
5916                  * vdd might still be enabled do to the delayed vdd off.
5917                  * Make sure vdd is actually turned off here.
5918                  */
5919                 pps_lock(intel_dp);
5920                 edp_panel_vdd_off_sync(intel_dp);
5921                 pps_unlock(intel_dp);
5922         }
5923         drm_connector_unregister(connector);
5924         drm_connector_cleanup(connector);
5925
5926         return false;
5927 }
5928
5929 bool intel_dp_init(struct drm_device *dev,
5930                    i915_reg_t output_reg,
5931                    enum port port)
5932 {
5933         struct drm_i915_private *dev_priv = dev->dev_private;
5934         struct intel_digital_port *intel_dig_port;
5935         struct intel_encoder *intel_encoder;
5936         struct drm_encoder *encoder;
5937         struct intel_connector *intel_connector;
5938
5939         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
5940         if (!intel_dig_port)
5941                 return false;
5942
5943         intel_connector = intel_connector_alloc();
5944         if (!intel_connector)
5945                 goto err_connector_alloc;
5946
5947         intel_encoder = &intel_dig_port->base;
5948         encoder = &intel_encoder->base;
5949
5950         if (drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
5951                              DRM_MODE_ENCODER_TMDS, NULL))
5952                 goto err_encoder_init;
5953
5954         intel_encoder->compute_config = intel_dp_compute_config;
5955         intel_encoder->disable = intel_disable_dp;
5956         intel_encoder->get_hw_state = intel_dp_get_hw_state;
5957         intel_encoder->get_config = intel_dp_get_config;
5958         intel_encoder->suspend = intel_dp_encoder_suspend;
5959         if (IS_CHERRYVIEW(dev)) {
5960                 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
5961                 intel_encoder->pre_enable = chv_pre_enable_dp;
5962                 intel_encoder->enable = vlv_enable_dp;
5963                 intel_encoder->post_disable = chv_post_disable_dp;
5964                 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
5965         } else if (IS_VALLEYVIEW(dev)) {
5966                 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
5967                 intel_encoder->pre_enable = vlv_pre_enable_dp;
5968                 intel_encoder->enable = vlv_enable_dp;
5969                 intel_encoder->post_disable = vlv_post_disable_dp;
5970         } else {
5971                 intel_encoder->pre_enable = g4x_pre_enable_dp;
5972                 intel_encoder->enable = g4x_enable_dp;
5973                 if (INTEL_INFO(dev)->gen >= 5)
5974                         intel_encoder->post_disable = ilk_post_disable_dp;
5975         }
5976
5977         intel_dig_port->port = port;
5978         intel_dig_port->dp.output_reg = output_reg;
5979         intel_dig_port->max_lanes = 4;
5980
5981         intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
5982         if (IS_CHERRYVIEW(dev)) {
5983                 if (port == PORT_D)
5984                         intel_encoder->crtc_mask = 1 << 2;
5985                 else
5986                         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
5987         } else {
5988                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
5989         }
5990         intel_encoder->cloneable = 0;
5991
5992         intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
5993         dev_priv->hotplug.irq_port[port] = intel_dig_port;
5994
5995         if (!intel_dp_init_connector(intel_dig_port, intel_connector))
5996                 goto err_init_connector;
5997
5998         return true;
5999
6000 err_init_connector:
6001         drm_encoder_cleanup(encoder);
6002 err_encoder_init:
6003         kfree(intel_connector);
6004 err_connector_alloc:
6005         kfree(intel_dig_port);
6006         return false;
6007 }
6008
6009 void intel_dp_mst_suspend(struct drm_device *dev)
6010 {
6011         struct drm_i915_private *dev_priv = dev->dev_private;
6012         int i;
6013
6014         /* disable MST */
6015         for (i = 0; i < I915_MAX_PORTS; i++) {
6016                 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
6017                 if (!intel_dig_port)
6018                         continue;
6019
6020                 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
6021                         if (!intel_dig_port->dp.can_mst)
6022                                 continue;
6023                         if (intel_dig_port->dp.is_mst)
6024                                 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
6025                 }
6026         }
6027 }
6028
6029 void intel_dp_mst_resume(struct drm_device *dev)
6030 {
6031         struct drm_i915_private *dev_priv = dev->dev_private;
6032         int i;
6033
6034         for (i = 0; i < I915_MAX_PORTS; i++) {
6035                 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
6036                 if (!intel_dig_port)
6037                         continue;
6038                 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
6039                         int ret;
6040
6041                         if (!intel_dig_port->dp.can_mst)
6042                                 continue;
6043
6044                         ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
6045                         if (ret != 0) {
6046                                 intel_dp_check_mst_status(&intel_dig_port->dp);
6047                         }
6048                 }
6049         }
6050 }