2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
31 #include <linux/notifier.h>
32 #include <linux/reboot.h>
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/drm_crtc.h>
36 #include <drm/drm_crtc_helper.h>
37 #include <drm/drm_edid.h>
38 #include "intel_drv.h"
39 #include <drm/i915_drm.h>
42 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
44 /* Compliance test status bits */
45 #define INTEL_DP_RESOLUTION_SHIFT_MASK 0
46 #define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
47 #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
48 #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
55 static const struct dp_link_dpll gen4_dpll[] = {
57 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
59 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
62 static const struct dp_link_dpll pch_dpll[] = {
64 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
66 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
69 static const struct dp_link_dpll vlv_dpll[] = {
71 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
73 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
77 * CHV supports eDP 1.4 that have more link rates.
78 * Below only provides the fixed rate but exclude variable rate.
80 static const struct dp_link_dpll chv_dpll[] = {
82 * CHV requires to program fractional division for m2.
83 * m2 is stored in fixed point format using formula below
84 * (m2_int << 22) | m2_fraction
86 { 162000, /* m2_int = 32, m2_fraction = 1677722 */
87 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
88 { 270000, /* m2_int = 27, m2_fraction = 0 */
89 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
90 { 540000, /* m2_int = 27, m2_fraction = 0 */
91 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
94 static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
95 324000, 432000, 540000 };
96 static const int skl_rates[] = { 162000, 216000, 270000,
97 324000, 432000, 540000 };
98 static const int default_rates[] = { 162000, 270000, 540000 };
101 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
102 * @intel_dp: DP struct
104 * If a CPU or PCH DP output is attached to an eDP panel, this function
105 * will return true, and false otherwise.
107 static bool is_edp(struct intel_dp *intel_dp)
109 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
111 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
114 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
116 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
118 return intel_dig_port->base.base.dev;
121 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
123 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
126 static void intel_dp_link_down(struct intel_dp *intel_dp);
127 static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
128 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
129 static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp);
130 static void vlv_steal_power_sequencer(struct drm_device *dev,
132 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
135 intel_dp_max_link_bw(struct intel_dp *intel_dp)
137 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
139 switch (max_link_bw) {
140 case DP_LINK_BW_1_62:
145 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
147 max_link_bw = DP_LINK_BW_1_62;
153 static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
155 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
156 u8 source_max, sink_max;
158 source_max = intel_dig_port->max_lanes;
159 sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
161 return min(source_max, sink_max);
165 * The units on the numbers in the next two are... bizarre. Examples will
166 * make it clearer; this one parallels an example in the eDP spec.
168 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
170 * 270000 * 1 * 8 / 10 == 216000
172 * The actual data capacity of that configuration is 2.16Gbit/s, so the
173 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
174 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
175 * 119000. At 18bpp that's 2142000 kilobits per second.
177 * Thus the strange-looking division by 10 in intel_dp_link_required, to
178 * get the result in decakilobits instead of kilobits.
182 intel_dp_link_required(int pixel_clock, int bpp)
184 return (pixel_clock * bpp + 9) / 10;
188 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
190 return (max_link_clock * max_lanes * 8) / 10;
193 static enum drm_mode_status
194 intel_dp_mode_valid(struct drm_connector *connector,
195 struct drm_display_mode *mode)
197 struct intel_dp *intel_dp = intel_attached_dp(connector);
198 struct intel_connector *intel_connector = to_intel_connector(connector);
199 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
200 int target_clock = mode->clock;
201 int max_rate, mode_rate, max_lanes, max_link_clock;
202 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
204 if (is_edp(intel_dp) && fixed_mode) {
205 if (mode->hdisplay > fixed_mode->hdisplay)
208 if (mode->vdisplay > fixed_mode->vdisplay)
211 target_clock = fixed_mode->clock;
214 max_link_clock = intel_dp_max_link_rate(intel_dp);
215 max_lanes = intel_dp_max_lane_count(intel_dp);
217 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
218 mode_rate = intel_dp_link_required(target_clock, 18);
220 if (mode_rate > max_rate || target_clock > max_dotclk)
221 return MODE_CLOCK_HIGH;
223 if (mode->clock < 10000)
224 return MODE_CLOCK_LOW;
226 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
227 return MODE_H_ILLEGAL;
232 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
239 for (i = 0; i < src_bytes; i++)
240 v |= ((uint32_t) src[i]) << ((3-i) * 8);
244 static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
249 for (i = 0; i < dst_bytes; i++)
250 dst[i] = src >> ((3-i) * 8);
254 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
255 struct intel_dp *intel_dp);
257 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
258 struct intel_dp *intel_dp);
260 intel_dp_pps_init(struct drm_device *dev, struct intel_dp *intel_dp);
262 static void pps_lock(struct intel_dp *intel_dp)
264 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
265 struct intel_encoder *encoder = &intel_dig_port->base;
266 struct drm_device *dev = encoder->base.dev;
267 struct drm_i915_private *dev_priv = to_i915(dev);
268 enum intel_display_power_domain power_domain;
271 * See vlv_power_sequencer_reset() why we need
272 * a power domain reference here.
274 power_domain = intel_display_port_aux_power_domain(encoder);
275 intel_display_power_get(dev_priv, power_domain);
277 mutex_lock(&dev_priv->pps_mutex);
280 static void pps_unlock(struct intel_dp *intel_dp)
282 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
283 struct intel_encoder *encoder = &intel_dig_port->base;
284 struct drm_device *dev = encoder->base.dev;
285 struct drm_i915_private *dev_priv = to_i915(dev);
286 enum intel_display_power_domain power_domain;
288 mutex_unlock(&dev_priv->pps_mutex);
290 power_domain = intel_display_port_aux_power_domain(encoder);
291 intel_display_power_put(dev_priv, power_domain);
295 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
297 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
298 struct drm_device *dev = intel_dig_port->base.base.dev;
299 struct drm_i915_private *dev_priv = to_i915(dev);
300 enum pipe pipe = intel_dp->pps_pipe;
301 bool pll_enabled, release_cl_override = false;
302 enum dpio_phy phy = DPIO_PHY(pipe);
303 enum dpio_channel ch = vlv_pipe_to_channel(pipe);
306 if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
307 "skipping pipe %c power seqeuncer kick due to port %c being active\n",
308 pipe_name(pipe), port_name(intel_dig_port->port)))
311 DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
312 pipe_name(pipe), port_name(intel_dig_port->port));
314 /* Preserve the BIOS-computed detected bit. This is
315 * supposed to be read-only.
317 DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
318 DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
319 DP |= DP_PORT_WIDTH(1);
320 DP |= DP_LINK_TRAIN_PAT_1;
322 if (IS_CHERRYVIEW(dev))
323 DP |= DP_PIPE_SELECT_CHV(pipe);
324 else if (pipe == PIPE_B)
325 DP |= DP_PIPEB_SELECT;
327 pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
330 * The DPLL for the pipe must be enabled for this to work.
331 * So enable temporarily it if it's not already enabled.
334 release_cl_override = IS_CHERRYVIEW(dev) &&
335 !chv_phy_powergate_ch(dev_priv, phy, ch, true);
337 if (vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev) ?
338 &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
339 DRM_ERROR("Failed to force on pll for pipe %c!\n",
346 * Similar magic as in intel_dp_enable_port().
347 * We _must_ do this port enable + disable trick
348 * to make this power seqeuencer lock onto the port.
349 * Otherwise even VDD force bit won't work.
351 I915_WRITE(intel_dp->output_reg, DP);
352 POSTING_READ(intel_dp->output_reg);
354 I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
355 POSTING_READ(intel_dp->output_reg);
357 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
358 POSTING_READ(intel_dp->output_reg);
361 vlv_force_pll_off(dev, pipe);
363 if (release_cl_override)
364 chv_phy_powergate_ch(dev_priv, phy, ch, false);
369 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
371 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
372 struct drm_device *dev = intel_dig_port->base.base.dev;
373 struct drm_i915_private *dev_priv = to_i915(dev);
374 struct intel_encoder *encoder;
375 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
378 lockdep_assert_held(&dev_priv->pps_mutex);
380 /* We should never land here with regular DP ports */
381 WARN_ON(!is_edp(intel_dp));
383 if (intel_dp->pps_pipe != INVALID_PIPE)
384 return intel_dp->pps_pipe;
387 * We don't have power sequencer currently.
388 * Pick one that's not used by other ports.
390 for_each_intel_encoder(dev, encoder) {
391 struct intel_dp *tmp;
393 if (encoder->type != INTEL_OUTPUT_EDP)
396 tmp = enc_to_intel_dp(&encoder->base);
398 if (tmp->pps_pipe != INVALID_PIPE)
399 pipes &= ~(1 << tmp->pps_pipe);
403 * Didn't find one. This should not happen since there
404 * are two power sequencers and up to two eDP ports.
406 if (WARN_ON(pipes == 0))
409 pipe = ffs(pipes) - 1;
411 vlv_steal_power_sequencer(dev, pipe);
412 intel_dp->pps_pipe = pipe;
414 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
415 pipe_name(intel_dp->pps_pipe),
416 port_name(intel_dig_port->port));
418 /* init power sequencer on this pipe and port */
419 intel_dp_init_panel_power_sequencer(dev, intel_dp);
420 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
423 * Even vdd force doesn't work until we've made
424 * the power sequencer lock in on the port.
426 vlv_power_sequencer_kick(intel_dp);
428 return intel_dp->pps_pipe;
432 bxt_power_sequencer_idx(struct intel_dp *intel_dp)
434 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
435 struct drm_device *dev = intel_dig_port->base.base.dev;
436 struct drm_i915_private *dev_priv = to_i915(dev);
438 lockdep_assert_held(&dev_priv->pps_mutex);
440 /* We should never land here with regular DP ports */
441 WARN_ON(!is_edp(intel_dp));
444 * TODO: BXT has 2 PPS instances. The correct port->PPS instance
445 * mapping needs to be retrieved from VBT, for now just hard-code to
446 * use instance #0 always.
448 if (!intel_dp->pps_reset)
451 intel_dp->pps_reset = false;
454 * Only the HW needs to be reprogrammed, the SW state is fixed and
455 * has been setup during connector init.
457 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
462 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
465 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
468 return I915_READ(PP_STATUS(pipe)) & PP_ON;
471 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
474 return I915_READ(PP_CONTROL(pipe)) & EDP_FORCE_VDD;
477 static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
484 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
486 vlv_pipe_check pipe_check)
490 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
491 u32 port_sel = I915_READ(PP_ON_DELAYS(pipe)) &
492 PANEL_PORT_SELECT_MASK;
494 if (port_sel != PANEL_PORT_SELECT_VLV(port))
497 if (!pipe_check(dev_priv, pipe))
507 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
509 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
510 struct drm_device *dev = intel_dig_port->base.base.dev;
511 struct drm_i915_private *dev_priv = to_i915(dev);
512 enum port port = intel_dig_port->port;
514 lockdep_assert_held(&dev_priv->pps_mutex);
516 /* try to find a pipe with this port selected */
517 /* first pick one where the panel is on */
518 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
520 /* didn't find one? pick one where vdd is on */
521 if (intel_dp->pps_pipe == INVALID_PIPE)
522 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
523 vlv_pipe_has_vdd_on);
524 /* didn't find one? pick one with just the correct port */
525 if (intel_dp->pps_pipe == INVALID_PIPE)
526 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
529 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
530 if (intel_dp->pps_pipe == INVALID_PIPE) {
531 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
536 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
537 port_name(port), pipe_name(intel_dp->pps_pipe));
539 intel_dp_init_panel_power_sequencer(dev, intel_dp);
540 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
543 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
545 struct drm_device *dev = &dev_priv->drm;
546 struct intel_encoder *encoder;
548 if (WARN_ON(!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
553 * We can't grab pps_mutex here due to deadlock with power_domain
554 * mutex when power_domain functions are called while holding pps_mutex.
555 * That also means that in order to use pps_pipe the code needs to
556 * hold both a power domain reference and pps_mutex, and the power domain
557 * reference get/put must be done while _not_ holding pps_mutex.
558 * pps_{lock,unlock}() do these steps in the correct order, so one
559 * should use them always.
562 for_each_intel_encoder(dev, encoder) {
563 struct intel_dp *intel_dp;
565 if (encoder->type != INTEL_OUTPUT_EDP)
568 intel_dp = enc_to_intel_dp(&encoder->base);
570 intel_dp->pps_reset = true;
572 intel_dp->pps_pipe = INVALID_PIPE;
576 struct pps_registers {
584 static void intel_pps_get_registers(struct drm_i915_private *dev_priv,
585 struct intel_dp *intel_dp,
586 struct pps_registers *regs)
590 memset(regs, 0, sizeof(*regs));
592 if (IS_BROXTON(dev_priv))
593 pps_idx = bxt_power_sequencer_idx(intel_dp);
594 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
595 pps_idx = vlv_power_sequencer_pipe(intel_dp);
597 regs->pp_ctrl = PP_CONTROL(pps_idx);
598 regs->pp_stat = PP_STATUS(pps_idx);
599 regs->pp_on = PP_ON_DELAYS(pps_idx);
600 regs->pp_off = PP_OFF_DELAYS(pps_idx);
601 if (!IS_BROXTON(dev_priv))
602 regs->pp_div = PP_DIVISOR(pps_idx);
606 _pp_ctrl_reg(struct intel_dp *intel_dp)
608 struct pps_registers regs;
610 intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp)), intel_dp,
617 _pp_stat_reg(struct intel_dp *intel_dp)
619 struct pps_registers regs;
621 intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp)), intel_dp,
627 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
628 This function only applicable when panel PM state is not to be tracked */
629 static int edp_notify_handler(struct notifier_block *this, unsigned long code,
632 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
634 struct drm_device *dev = intel_dp_to_dev(intel_dp);
635 struct drm_i915_private *dev_priv = to_i915(dev);
637 if (!is_edp(intel_dp) || code != SYS_RESTART)
642 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
643 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
644 i915_reg_t pp_ctrl_reg, pp_div_reg;
647 pp_ctrl_reg = PP_CONTROL(pipe);
648 pp_div_reg = PP_DIVISOR(pipe);
649 pp_div = I915_READ(pp_div_reg);
650 pp_div &= PP_REFERENCE_DIVIDER_MASK;
652 /* 0x1F write to PP_DIV_REG sets max cycle delay */
653 I915_WRITE(pp_div_reg, pp_div | 0x1F);
654 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
655 msleep(intel_dp->panel_power_cycle_delay);
658 pps_unlock(intel_dp);
663 static bool edp_have_panel_power(struct intel_dp *intel_dp)
665 struct drm_device *dev = intel_dp_to_dev(intel_dp);
666 struct drm_i915_private *dev_priv = to_i915(dev);
668 lockdep_assert_held(&dev_priv->pps_mutex);
670 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
671 intel_dp->pps_pipe == INVALID_PIPE)
674 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
677 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
679 struct drm_device *dev = intel_dp_to_dev(intel_dp);
680 struct drm_i915_private *dev_priv = to_i915(dev);
682 lockdep_assert_held(&dev_priv->pps_mutex);
684 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
685 intel_dp->pps_pipe == INVALID_PIPE)
688 return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
692 intel_dp_check_edp(struct intel_dp *intel_dp)
694 struct drm_device *dev = intel_dp_to_dev(intel_dp);
695 struct drm_i915_private *dev_priv = to_i915(dev);
697 if (!is_edp(intel_dp))
700 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
701 WARN(1, "eDP powered off while attempting aux channel communication.\n");
702 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
703 I915_READ(_pp_stat_reg(intel_dp)),
704 I915_READ(_pp_ctrl_reg(intel_dp)));
709 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
711 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
712 struct drm_device *dev = intel_dig_port->base.base.dev;
713 struct drm_i915_private *dev_priv = to_i915(dev);
714 i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
718 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
720 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
721 msecs_to_jiffies_timeout(10));
723 done = wait_for(C, 10) == 0;
725 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
732 static uint32_t g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
734 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
735 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
741 * The clock divider is based off the hrawclk, and would like to run at
742 * 2MHz. So, take the hrawclk value and divide by 2000 and use that
744 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
747 static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
749 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
750 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
756 * The clock divider is based off the cdclk or PCH rawclk, and would
757 * like to run at 2MHz. So, take the cdclk or PCH rawclk value and
758 * divide by 2000 and use that
760 if (intel_dig_port->port == PORT_A)
761 return DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 2000);
763 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
766 static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
768 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
769 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
771 if (intel_dig_port->port != PORT_A && HAS_PCH_LPT_H(dev_priv)) {
772 /* Workaround for non-ULT HSW */
780 return ilk_get_aux_clock_divider(intel_dp, index);
783 static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
786 * SKL doesn't need us to program the AUX clock divider (Hardware will
787 * derive the clock from CDCLK automatically). We still implement the
788 * get_aux_clock_divider vfunc to plug-in into the existing code.
790 return index ? 0 : 1;
793 static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
796 uint32_t aux_clock_divider)
798 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
799 struct drm_device *dev = intel_dig_port->base.base.dev;
800 uint32_t precharge, timeout;
807 if (IS_BROADWELL(dev) && intel_dig_port->port == PORT_A)
808 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
810 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
812 return DP_AUX_CH_CTL_SEND_BUSY |
814 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
815 DP_AUX_CH_CTL_TIME_OUT_ERROR |
817 DP_AUX_CH_CTL_RECEIVE_ERROR |
818 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
819 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
820 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
823 static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
828 return DP_AUX_CH_CTL_SEND_BUSY |
830 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
831 DP_AUX_CH_CTL_TIME_OUT_ERROR |
832 DP_AUX_CH_CTL_TIME_OUT_1600us |
833 DP_AUX_CH_CTL_RECEIVE_ERROR |
834 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
835 DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
836 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
840 intel_dp_aux_ch(struct intel_dp *intel_dp,
841 const uint8_t *send, int send_bytes,
842 uint8_t *recv, int recv_size)
844 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
845 struct drm_device *dev = intel_dig_port->base.base.dev;
846 struct drm_i915_private *dev_priv = to_i915(dev);
847 i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
848 uint32_t aux_clock_divider;
849 int i, ret, recv_bytes;
852 bool has_aux_irq = HAS_AUX_IRQ(dev);
858 * We will be called with VDD already enabled for dpcd/edid/oui reads.
859 * In such cases we want to leave VDD enabled and it's up to upper layers
860 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
863 vdd = edp_panel_vdd_on(intel_dp);
865 /* dp aux is extremely sensitive to irq latency, hence request the
866 * lowest possible wakeup latency and so prevent the cpu from going into
869 pm_qos_update_request(&dev_priv->pm_qos, 0);
871 intel_dp_check_edp(intel_dp);
873 /* Try to wait for any previous AUX channel activity */
874 for (try = 0; try < 3; try++) {
875 status = I915_READ_NOTRACE(ch_ctl);
876 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
882 static u32 last_status = -1;
883 const u32 status = I915_READ(ch_ctl);
885 if (status != last_status) {
886 WARN(1, "dp_aux_ch not started status 0x%08x\n",
888 last_status = status;
895 /* Only 5 data registers! */
896 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
901 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
902 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
907 /* Must try at least 3 times according to DP spec */
908 for (try = 0; try < 5; try++) {
909 /* Load the send data into the aux channel data registers */
910 for (i = 0; i < send_bytes; i += 4)
911 I915_WRITE(intel_dp->aux_ch_data_reg[i >> 2],
912 intel_dp_pack_aux(send + i,
915 /* Send the command and wait for it to complete */
916 I915_WRITE(ch_ctl, send_ctl);
918 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
920 /* Clear done status and any errors */
924 DP_AUX_CH_CTL_TIME_OUT_ERROR |
925 DP_AUX_CH_CTL_RECEIVE_ERROR);
927 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
930 /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
931 * 400us delay required for errors and timeouts
932 * Timeout errors from the HW already meet this
933 * requirement so skip to next iteration
935 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
936 usleep_range(400, 500);
939 if (status & DP_AUX_CH_CTL_DONE)
944 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
945 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
951 /* Check for timeout or receive error.
952 * Timeouts occur when the sink is not connected
954 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
955 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
960 /* Timeouts occur when the device isn't connected, so they're
961 * "normal" -- don't fill the kernel log with these */
962 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
963 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
968 /* Unload any bytes sent back from the other side */
969 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
970 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
973 * By BSpec: "Message sizes of 0 or >20 are not allowed."
974 * We have no idea of what happened so we return -EBUSY so
975 * drm layer takes care for the necessary retries.
977 if (recv_bytes == 0 || recv_bytes > 20) {
978 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
981 * FIXME: This patch was created on top of a series that
982 * organize the retries at drm level. There EBUSY should
983 * also take care for 1ms wait before retrying.
984 * That aux retries re-org is still needed and after that is
985 * merged we remove this sleep from here.
987 usleep_range(1000, 1500);
992 if (recv_bytes > recv_size)
993 recv_bytes = recv_size;
995 for (i = 0; i < recv_bytes; i += 4)
996 intel_dp_unpack_aux(I915_READ(intel_dp->aux_ch_data_reg[i >> 2]),
997 recv + i, recv_bytes - i);
1001 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
1004 edp_panel_vdd_off(intel_dp, false);
1006 pps_unlock(intel_dp);
1011 #define BARE_ADDRESS_SIZE 3
1012 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
1014 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
1016 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
1017 uint8_t txbuf[20], rxbuf[20];
1018 size_t txsize, rxsize;
1021 txbuf[0] = (msg->request << 4) |
1022 ((msg->address >> 16) & 0xf);
1023 txbuf[1] = (msg->address >> 8) & 0xff;
1024 txbuf[2] = msg->address & 0xff;
1025 txbuf[3] = msg->size - 1;
1027 switch (msg->request & ~DP_AUX_I2C_MOT) {
1028 case DP_AUX_NATIVE_WRITE:
1029 case DP_AUX_I2C_WRITE:
1030 case DP_AUX_I2C_WRITE_STATUS_UPDATE:
1031 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
1032 rxsize = 2; /* 0 or 1 data bytes */
1034 if (WARN_ON(txsize > 20))
1037 WARN_ON(!msg->buffer != !msg->size);
1040 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
1042 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
1044 msg->reply = rxbuf[0] >> 4;
1047 /* Number of bytes written in a short write. */
1048 ret = clamp_t(int, rxbuf[1], 0, msg->size);
1050 /* Return payload size. */
1056 case DP_AUX_NATIVE_READ:
1057 case DP_AUX_I2C_READ:
1058 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
1059 rxsize = msg->size + 1;
1061 if (WARN_ON(rxsize > 20))
1064 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
1066 msg->reply = rxbuf[0] >> 4;
1068 * Assume happy day, and copy the data. The caller is
1069 * expected to check msg->reply before touching it.
1071 * Return payload size.
1074 memcpy(msg->buffer, rxbuf + 1, ret);
1086 static i915_reg_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv,
1093 return DP_AUX_CH_CTL(port);
1096 return DP_AUX_CH_CTL(PORT_B);
1100 static i915_reg_t g4x_aux_data_reg(struct drm_i915_private *dev_priv,
1101 enum port port, int index)
1107 return DP_AUX_CH_DATA(port, index);
1110 return DP_AUX_CH_DATA(PORT_B, index);
1114 static i915_reg_t ilk_aux_ctl_reg(struct drm_i915_private *dev_priv,
1119 return DP_AUX_CH_CTL(port);
1123 return PCH_DP_AUX_CH_CTL(port);
1126 return DP_AUX_CH_CTL(PORT_A);
1130 static i915_reg_t ilk_aux_data_reg(struct drm_i915_private *dev_priv,
1131 enum port port, int index)
1135 return DP_AUX_CH_DATA(port, index);
1139 return PCH_DP_AUX_CH_DATA(port, index);
1142 return DP_AUX_CH_DATA(PORT_A, index);
1147 * On SKL we don't have Aux for port E so we rely
1148 * on VBT to set a proper alternate aux channel.
1150 static enum port skl_porte_aux_port(struct drm_i915_private *dev_priv)
1152 const struct ddi_vbt_port_info *info =
1153 &dev_priv->vbt.ddi_port_info[PORT_E];
1155 switch (info->alternate_aux_channel) {
1165 MISSING_CASE(info->alternate_aux_channel);
1170 static i915_reg_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv,
1174 port = skl_porte_aux_port(dev_priv);
1181 return DP_AUX_CH_CTL(port);
1184 return DP_AUX_CH_CTL(PORT_A);
1188 static i915_reg_t skl_aux_data_reg(struct drm_i915_private *dev_priv,
1189 enum port port, int index)
1192 port = skl_porte_aux_port(dev_priv);
1199 return DP_AUX_CH_DATA(port, index);
1202 return DP_AUX_CH_DATA(PORT_A, index);
1206 static i915_reg_t intel_aux_ctl_reg(struct drm_i915_private *dev_priv,
1209 if (INTEL_INFO(dev_priv)->gen >= 9)
1210 return skl_aux_ctl_reg(dev_priv, port);
1211 else if (HAS_PCH_SPLIT(dev_priv))
1212 return ilk_aux_ctl_reg(dev_priv, port);
1214 return g4x_aux_ctl_reg(dev_priv, port);
1217 static i915_reg_t intel_aux_data_reg(struct drm_i915_private *dev_priv,
1218 enum port port, int index)
1220 if (INTEL_INFO(dev_priv)->gen >= 9)
1221 return skl_aux_data_reg(dev_priv, port, index);
1222 else if (HAS_PCH_SPLIT(dev_priv))
1223 return ilk_aux_data_reg(dev_priv, port, index);
1225 return g4x_aux_data_reg(dev_priv, port, index);
1228 static void intel_aux_reg_init(struct intel_dp *intel_dp)
1230 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1231 enum port port = dp_to_dig_port(intel_dp)->port;
1234 intel_dp->aux_ch_ctl_reg = intel_aux_ctl_reg(dev_priv, port);
1235 for (i = 0; i < ARRAY_SIZE(intel_dp->aux_ch_data_reg); i++)
1236 intel_dp->aux_ch_data_reg[i] = intel_aux_data_reg(dev_priv, port, i);
1240 intel_dp_aux_fini(struct intel_dp *intel_dp)
1242 kfree(intel_dp->aux.name);
1246 intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
1248 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1249 enum port port = intel_dig_port->port;
1251 intel_aux_reg_init(intel_dp);
1252 drm_dp_aux_init(&intel_dp->aux);
1254 /* Failure to allocate our preferred name is not critical */
1255 intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c", port_name(port));
1256 intel_dp->aux.transfer = intel_dp_aux_transfer;
1260 intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
1262 if (intel_dp->num_sink_rates) {
1263 *sink_rates = intel_dp->sink_rates;
1264 return intel_dp->num_sink_rates;
1267 *sink_rates = default_rates;
1269 return (intel_dp_max_link_bw(intel_dp) >> 3) + 1;
1272 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
1274 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1275 struct drm_device *dev = dig_port->base.base.dev;
1277 /* WaDisableHBR2:skl */
1278 if (IS_SKL_REVID(dev, 0, SKL_REVID_B0))
1281 if ((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) || IS_BROADWELL(dev) ||
1282 (INTEL_INFO(dev)->gen >= 9))
1289 intel_dp_source_rates(struct intel_dp *intel_dp, const int **source_rates)
1291 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1292 struct drm_device *dev = dig_port->base.base.dev;
1295 if (IS_BROXTON(dev)) {
1296 *source_rates = bxt_rates;
1297 size = ARRAY_SIZE(bxt_rates);
1298 } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
1299 *source_rates = skl_rates;
1300 size = ARRAY_SIZE(skl_rates);
1302 *source_rates = default_rates;
1303 size = ARRAY_SIZE(default_rates);
1306 /* This depends on the fact that 5.4 is last value in the array */
1307 if (!intel_dp_source_supports_hbr2(intel_dp))
1314 intel_dp_set_clock(struct intel_encoder *encoder,
1315 struct intel_crtc_state *pipe_config)
1317 struct drm_device *dev = encoder->base.dev;
1318 const struct dp_link_dpll *divisor = NULL;
1322 divisor = gen4_dpll;
1323 count = ARRAY_SIZE(gen4_dpll);
1324 } else if (HAS_PCH_SPLIT(dev)) {
1326 count = ARRAY_SIZE(pch_dpll);
1327 } else if (IS_CHERRYVIEW(dev)) {
1329 count = ARRAY_SIZE(chv_dpll);
1330 } else if (IS_VALLEYVIEW(dev)) {
1332 count = ARRAY_SIZE(vlv_dpll);
1335 if (divisor && count) {
1336 for (i = 0; i < count; i++) {
1337 if (pipe_config->port_clock == divisor[i].clock) {
1338 pipe_config->dpll = divisor[i].dpll;
1339 pipe_config->clock_set = true;
1346 static int intersect_rates(const int *source_rates, int source_len,
1347 const int *sink_rates, int sink_len,
1350 int i = 0, j = 0, k = 0;
1352 while (i < source_len && j < sink_len) {
1353 if (source_rates[i] == sink_rates[j]) {
1354 if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
1356 common_rates[k] = source_rates[i];
1360 } else if (source_rates[i] < sink_rates[j]) {
1369 static int intel_dp_common_rates(struct intel_dp *intel_dp,
1372 const int *source_rates, *sink_rates;
1373 int source_len, sink_len;
1375 sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
1376 source_len = intel_dp_source_rates(intel_dp, &source_rates);
1378 return intersect_rates(source_rates, source_len,
1379 sink_rates, sink_len,
1383 static void snprintf_int_array(char *str, size_t len,
1384 const int *array, int nelem)
1390 for (i = 0; i < nelem; i++) {
1391 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1399 static void intel_dp_print_rates(struct intel_dp *intel_dp)
1401 const int *source_rates, *sink_rates;
1402 int source_len, sink_len, common_len;
1403 int common_rates[DP_MAX_SUPPORTED_RATES];
1404 char str[128]; /* FIXME: too big for stack? */
1406 if ((drm_debug & DRM_UT_KMS) == 0)
1409 source_len = intel_dp_source_rates(intel_dp, &source_rates);
1410 snprintf_int_array(str, sizeof(str), source_rates, source_len);
1411 DRM_DEBUG_KMS("source rates: %s\n", str);
1413 sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
1414 snprintf_int_array(str, sizeof(str), sink_rates, sink_len);
1415 DRM_DEBUG_KMS("sink rates: %s\n", str);
1417 common_len = intel_dp_common_rates(intel_dp, common_rates);
1418 snprintf_int_array(str, sizeof(str), common_rates, common_len);
1419 DRM_DEBUG_KMS("common rates: %s\n", str);
1422 static int rate_to_index(int find, const int *rates)
1426 for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i)
1427 if (find == rates[i])
1434 intel_dp_max_link_rate(struct intel_dp *intel_dp)
1436 int rates[DP_MAX_SUPPORTED_RATES] = {};
1439 len = intel_dp_common_rates(intel_dp, rates);
1440 if (WARN_ON(len <= 0))
1443 return rates[len - 1];
1446 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1448 return rate_to_index(rate, intel_dp->sink_rates);
1451 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1452 uint8_t *link_bw, uint8_t *rate_select)
1454 if (intel_dp->num_sink_rates) {
1457 intel_dp_rate_select(intel_dp, port_clock);
1459 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1465 intel_dp_compute_config(struct intel_encoder *encoder,
1466 struct intel_crtc_state *pipe_config,
1467 struct drm_connector_state *conn_state)
1469 struct drm_device *dev = encoder->base.dev;
1470 struct drm_i915_private *dev_priv = to_i915(dev);
1471 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1472 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1473 enum port port = dp_to_dig_port(intel_dp)->port;
1474 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
1475 struct intel_connector *intel_connector = intel_dp->attached_connector;
1476 int lane_count, clock;
1477 int min_lane_count = 1;
1478 int max_lane_count = intel_dp_max_lane_count(intel_dp);
1479 /* Conveniently, the link BW constants become indices with a shift...*/
1483 int link_avail, link_clock;
1484 int common_rates[DP_MAX_SUPPORTED_RATES] = {};
1486 uint8_t link_bw, rate_select;
1488 common_len = intel_dp_common_rates(intel_dp, common_rates);
1490 /* No common link rates between source and sink */
1491 WARN_ON(common_len <= 0);
1493 max_clock = common_len - 1;
1495 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
1496 pipe_config->has_pch_encoder = true;
1498 pipe_config->has_drrs = false;
1499 pipe_config->has_audio = intel_dp->has_audio && port != PORT_A;
1501 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1502 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1505 if (INTEL_INFO(dev)->gen >= 9) {
1507 ret = skl_update_scaler_crtc(pipe_config);
1512 if (HAS_GMCH_DISPLAY(dev))
1513 intel_gmch_panel_fitting(intel_crtc, pipe_config,
1514 intel_connector->panel.fitting_mode);
1516 intel_pch_panel_fitting(intel_crtc, pipe_config,
1517 intel_connector->panel.fitting_mode);
1520 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
1523 DRM_DEBUG_KMS("DP link computation with max lane count %i "
1524 "max bw %d pixel clock %iKHz\n",
1525 max_lane_count, common_rates[max_clock],
1526 adjusted_mode->crtc_clock);
1528 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1529 * bpc in between. */
1530 bpp = pipe_config->pipe_bpp;
1531 if (is_edp(intel_dp)) {
1533 /* Get bpp from vbt only for panels that dont have bpp in edid */
1534 if (intel_connector->base.display_info.bpc == 0 &&
1535 (dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp)) {
1536 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1537 dev_priv->vbt.edp.bpp);
1538 bpp = dev_priv->vbt.edp.bpp;
1542 * Use the maximum clock and number of lanes the eDP panel
1543 * advertizes being capable of. The panels are generally
1544 * designed to support only a single clock and lane
1545 * configuration, and typically these values correspond to the
1546 * native resolution of the panel.
1548 min_lane_count = max_lane_count;
1549 min_clock = max_clock;
1552 for (; bpp >= 6*3; bpp -= 2*3) {
1553 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1556 for (clock = min_clock; clock <= max_clock; clock++) {
1557 for (lane_count = min_lane_count;
1558 lane_count <= max_lane_count;
1561 link_clock = common_rates[clock];
1562 link_avail = intel_dp_max_data_rate(link_clock,
1565 if (mode_rate <= link_avail) {
1575 if (intel_dp->color_range_auto) {
1578 * CEA-861-E - 5.1 Default Encoding Parameters
1579 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1581 pipe_config->limited_color_range =
1582 bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1;
1584 pipe_config->limited_color_range =
1585 intel_dp->limited_color_range;
1588 pipe_config->lane_count = lane_count;
1590 pipe_config->pipe_bpp = bpp;
1591 pipe_config->port_clock = common_rates[clock];
1593 intel_dp_compute_rate(intel_dp, pipe_config->port_clock,
1594 &link_bw, &rate_select);
1596 DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n",
1597 link_bw, rate_select, pipe_config->lane_count,
1598 pipe_config->port_clock, bpp);
1599 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1600 mode_rate, link_avail);
1602 intel_link_compute_m_n(bpp, lane_count,
1603 adjusted_mode->crtc_clock,
1604 pipe_config->port_clock,
1605 &pipe_config->dp_m_n);
1607 if (intel_connector->panel.downclock_mode != NULL &&
1608 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
1609 pipe_config->has_drrs = true;
1610 intel_link_compute_m_n(bpp, lane_count,
1611 intel_connector->panel.downclock_mode->clock,
1612 pipe_config->port_clock,
1613 &pipe_config->dp_m2_n2);
1617 * DPLL0 VCO may need to be adjusted to get the correct
1618 * clock for eDP. This will affect cdclk as well.
1620 if (is_edp(intel_dp) &&
1621 (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))) {
1624 switch (pipe_config->port_clock / 2) {
1634 to_intel_atomic_state(pipe_config->base.state)->cdclk_pll_vco = vco;
1638 intel_dp_set_clock(encoder, pipe_config);
1643 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1644 const struct intel_crtc_state *pipe_config)
1646 intel_dp->link_rate = pipe_config->port_clock;
1647 intel_dp->lane_count = pipe_config->lane_count;
1648 intel_dp->link_mst = intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST);
1651 static void intel_dp_prepare(struct intel_encoder *encoder,
1652 struct intel_crtc_state *pipe_config)
1654 struct drm_device *dev = encoder->base.dev;
1655 struct drm_i915_private *dev_priv = to_i915(dev);
1656 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1657 enum port port = dp_to_dig_port(intel_dp)->port;
1658 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1659 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1661 intel_dp_set_link_params(intel_dp, pipe_config);
1664 * There are four kinds of DP registers:
1671 * IBX PCH and CPU are the same for almost everything,
1672 * except that the CPU DP PLL is configured in this
1675 * CPT PCH is quite different, having many bits moved
1676 * to the TRANS_DP_CTL register instead. That
1677 * configuration happens (oddly) in ironlake_pch_enable
1680 /* Preserve the BIOS-computed detected bit. This is
1681 * supposed to be read-only.
1683 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
1685 /* Handle DP bits in common between all three register formats */
1686 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
1687 intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count);
1689 /* Split out the IBX/CPU vs CPT settings */
1691 if (IS_GEN7(dev) && port == PORT_A) {
1692 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1693 intel_dp->DP |= DP_SYNC_HS_HIGH;
1694 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1695 intel_dp->DP |= DP_SYNC_VS_HIGH;
1696 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1698 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1699 intel_dp->DP |= DP_ENHANCED_FRAMING;
1701 intel_dp->DP |= crtc->pipe << 29;
1702 } else if (HAS_PCH_CPT(dev) && port != PORT_A) {
1705 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1707 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1708 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1709 trans_dp |= TRANS_DP_ENH_FRAMING;
1711 trans_dp &= ~TRANS_DP_ENH_FRAMING;
1712 I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
1714 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
1715 !IS_CHERRYVIEW(dev) && pipe_config->limited_color_range)
1716 intel_dp->DP |= DP_COLOR_RANGE_16_235;
1718 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1719 intel_dp->DP |= DP_SYNC_HS_HIGH;
1720 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1721 intel_dp->DP |= DP_SYNC_VS_HIGH;
1722 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1724 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1725 intel_dp->DP |= DP_ENHANCED_FRAMING;
1727 if (IS_CHERRYVIEW(dev))
1728 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1729 else if (crtc->pipe == PIPE_B)
1730 intel_dp->DP |= DP_PIPEB_SELECT;
1734 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1735 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
1737 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1738 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
1740 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1741 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1743 static void intel_pps_verify_state(struct drm_i915_private *dev_priv,
1744 struct intel_dp *intel_dp);
1746 static void wait_panel_status(struct intel_dp *intel_dp,
1750 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1751 struct drm_i915_private *dev_priv = to_i915(dev);
1752 i915_reg_t pp_stat_reg, pp_ctrl_reg;
1754 lockdep_assert_held(&dev_priv->pps_mutex);
1756 intel_pps_verify_state(dev_priv, intel_dp);
1758 pp_stat_reg = _pp_stat_reg(intel_dp);
1759 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1761 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1763 I915_READ(pp_stat_reg),
1764 I915_READ(pp_ctrl_reg));
1766 if (intel_wait_for_register(dev_priv,
1767 pp_stat_reg, mask, value,
1769 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1770 I915_READ(pp_stat_reg),
1771 I915_READ(pp_ctrl_reg));
1773 DRM_DEBUG_KMS("Wait complete\n");
1776 static void wait_panel_on(struct intel_dp *intel_dp)
1778 DRM_DEBUG_KMS("Wait for panel power on\n");
1779 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1782 static void wait_panel_off(struct intel_dp *intel_dp)
1784 DRM_DEBUG_KMS("Wait for panel power off time\n");
1785 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1788 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
1790 ktime_t panel_power_on_time;
1791 s64 panel_power_off_duration;
1793 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1795 /* take the difference of currrent time and panel power off time
1796 * and then make panel wait for t11_t12 if needed. */
1797 panel_power_on_time = ktime_get_boottime();
1798 panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
1800 /* When we disable the VDD override bit last we have to do the manual
1802 if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
1803 wait_remaining_ms_from_jiffies(jiffies,
1804 intel_dp->panel_power_cycle_delay - panel_power_off_duration);
1806 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1809 static void wait_backlight_on(struct intel_dp *intel_dp)
1811 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1812 intel_dp->backlight_on_delay);
1815 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
1817 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1818 intel_dp->backlight_off_delay);
1821 /* Read the current pp_control value, unlocking the register if it
1825 static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
1827 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1828 struct drm_i915_private *dev_priv = to_i915(dev);
1831 lockdep_assert_held(&dev_priv->pps_mutex);
1833 control = I915_READ(_pp_ctrl_reg(intel_dp));
1834 if (WARN_ON(!HAS_DDI(dev_priv) &&
1835 (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) {
1836 control &= ~PANEL_UNLOCK_MASK;
1837 control |= PANEL_UNLOCK_REGS;
1843 * Must be paired with edp_panel_vdd_off().
1844 * Must hold pps_mutex around the whole on/off sequence.
1845 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1847 static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
1849 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1850 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1851 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1852 struct drm_i915_private *dev_priv = to_i915(dev);
1853 enum intel_display_power_domain power_domain;
1855 i915_reg_t pp_stat_reg, pp_ctrl_reg;
1856 bool need_to_disable = !intel_dp->want_panel_vdd;
1858 lockdep_assert_held(&dev_priv->pps_mutex);
1860 if (!is_edp(intel_dp))
1863 cancel_delayed_work(&intel_dp->panel_vdd_work);
1864 intel_dp->want_panel_vdd = true;
1866 if (edp_have_panel_vdd(intel_dp))
1867 return need_to_disable;
1869 power_domain = intel_display_port_aux_power_domain(intel_encoder);
1870 intel_display_power_get(dev_priv, power_domain);
1872 DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
1873 port_name(intel_dig_port->port));
1875 if (!edp_have_panel_power(intel_dp))
1876 wait_panel_power_cycle(intel_dp);
1878 pp = ironlake_get_pp_control(intel_dp);
1879 pp |= EDP_FORCE_VDD;
1881 pp_stat_reg = _pp_stat_reg(intel_dp);
1882 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1884 I915_WRITE(pp_ctrl_reg, pp);
1885 POSTING_READ(pp_ctrl_reg);
1886 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1887 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1889 * If the panel wasn't on, delay before accessing aux channel
1891 if (!edp_have_panel_power(intel_dp)) {
1892 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
1893 port_name(intel_dig_port->port));
1894 msleep(intel_dp->panel_power_up_delay);
1897 return need_to_disable;
1901 * Must be paired with intel_edp_panel_vdd_off() or
1902 * intel_edp_panel_off().
1903 * Nested calls to these functions are not allowed since
1904 * we drop the lock. Caller must use some higher level
1905 * locking to prevent nested calls from other threads.
1907 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
1911 if (!is_edp(intel_dp))
1915 vdd = edp_panel_vdd_on(intel_dp);
1916 pps_unlock(intel_dp);
1918 I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
1919 port_name(dp_to_dig_port(intel_dp)->port));
1922 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
1924 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1925 struct drm_i915_private *dev_priv = to_i915(dev);
1926 struct intel_digital_port *intel_dig_port =
1927 dp_to_dig_port(intel_dp);
1928 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1929 enum intel_display_power_domain power_domain;
1931 i915_reg_t pp_stat_reg, pp_ctrl_reg;
1933 lockdep_assert_held(&dev_priv->pps_mutex);
1935 WARN_ON(intel_dp->want_panel_vdd);
1937 if (!edp_have_panel_vdd(intel_dp))
1940 DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
1941 port_name(intel_dig_port->port));
1943 pp = ironlake_get_pp_control(intel_dp);
1944 pp &= ~EDP_FORCE_VDD;
1946 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1947 pp_stat_reg = _pp_stat_reg(intel_dp);
1949 I915_WRITE(pp_ctrl_reg, pp);
1950 POSTING_READ(pp_ctrl_reg);
1952 /* Make sure sequencer is idle before allowing subsequent activity */
1953 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1954 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1956 if ((pp & PANEL_POWER_ON) == 0)
1957 intel_dp->panel_power_off_time = ktime_get_boottime();
1959 power_domain = intel_display_port_aux_power_domain(intel_encoder);
1960 intel_display_power_put(dev_priv, power_domain);
1963 static void edp_panel_vdd_work(struct work_struct *__work)
1965 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1966 struct intel_dp, panel_vdd_work);
1969 if (!intel_dp->want_panel_vdd)
1970 edp_panel_vdd_off_sync(intel_dp);
1971 pps_unlock(intel_dp);
1974 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
1976 unsigned long delay;
1979 * Queue the timer to fire a long time from now (relative to the power
1980 * down delay) to keep the panel power up across a sequence of
1983 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
1984 schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
1988 * Must be paired with edp_panel_vdd_on().
1989 * Must hold pps_mutex around the whole on/off sequence.
1990 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1992 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1994 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1996 lockdep_assert_held(&dev_priv->pps_mutex);
1998 if (!is_edp(intel_dp))
2001 I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
2002 port_name(dp_to_dig_port(intel_dp)->port));
2004 intel_dp->want_panel_vdd = false;
2007 edp_panel_vdd_off_sync(intel_dp);
2009 edp_panel_vdd_schedule_off(intel_dp);
2012 static void edp_panel_on(struct intel_dp *intel_dp)
2014 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2015 struct drm_i915_private *dev_priv = to_i915(dev);
2017 i915_reg_t pp_ctrl_reg;
2019 lockdep_assert_held(&dev_priv->pps_mutex);
2021 if (!is_edp(intel_dp))
2024 DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
2025 port_name(dp_to_dig_port(intel_dp)->port));
2027 if (WARN(edp_have_panel_power(intel_dp),
2028 "eDP port %c panel power already on\n",
2029 port_name(dp_to_dig_port(intel_dp)->port)))
2032 wait_panel_power_cycle(intel_dp);
2034 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2035 pp = ironlake_get_pp_control(intel_dp);
2037 /* ILK workaround: disable reset around power sequence */
2038 pp &= ~PANEL_POWER_RESET;
2039 I915_WRITE(pp_ctrl_reg, pp);
2040 POSTING_READ(pp_ctrl_reg);
2043 pp |= PANEL_POWER_ON;
2045 pp |= PANEL_POWER_RESET;
2047 I915_WRITE(pp_ctrl_reg, pp);
2048 POSTING_READ(pp_ctrl_reg);
2050 wait_panel_on(intel_dp);
2051 intel_dp->last_power_on = jiffies;
2054 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
2055 I915_WRITE(pp_ctrl_reg, pp);
2056 POSTING_READ(pp_ctrl_reg);
2060 void intel_edp_panel_on(struct intel_dp *intel_dp)
2062 if (!is_edp(intel_dp))
2066 edp_panel_on(intel_dp);
2067 pps_unlock(intel_dp);
2071 static void edp_panel_off(struct intel_dp *intel_dp)
2073 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2074 struct intel_encoder *intel_encoder = &intel_dig_port->base;
2075 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2076 struct drm_i915_private *dev_priv = to_i915(dev);
2077 enum intel_display_power_domain power_domain;
2079 i915_reg_t pp_ctrl_reg;
2081 lockdep_assert_held(&dev_priv->pps_mutex);
2083 if (!is_edp(intel_dp))
2086 DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2087 port_name(dp_to_dig_port(intel_dp)->port));
2089 WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
2090 port_name(dp_to_dig_port(intel_dp)->port));
2092 pp = ironlake_get_pp_control(intel_dp);
2093 /* We need to switch off panel power _and_ force vdd, for otherwise some
2094 * panels get very unhappy and cease to work. */
2095 pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
2098 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2100 intel_dp->want_panel_vdd = false;
2102 I915_WRITE(pp_ctrl_reg, pp);
2103 POSTING_READ(pp_ctrl_reg);
2105 intel_dp->panel_power_off_time = ktime_get_boottime();
2106 wait_panel_off(intel_dp);
2108 /* We got a reference when we enabled the VDD. */
2109 power_domain = intel_display_port_aux_power_domain(intel_encoder);
2110 intel_display_power_put(dev_priv, power_domain);
2113 void intel_edp_panel_off(struct intel_dp *intel_dp)
2115 if (!is_edp(intel_dp))
2119 edp_panel_off(intel_dp);
2120 pps_unlock(intel_dp);
2123 /* Enable backlight in the panel power control. */
2124 static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
2126 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2127 struct drm_device *dev = intel_dig_port->base.base.dev;
2128 struct drm_i915_private *dev_priv = to_i915(dev);
2130 i915_reg_t pp_ctrl_reg;
2133 * If we enable the backlight right away following a panel power
2134 * on, we may see slight flicker as the panel syncs with the eDP
2135 * link. So delay a bit to make sure the image is solid before
2136 * allowing it to appear.
2138 wait_backlight_on(intel_dp);
2142 pp = ironlake_get_pp_control(intel_dp);
2143 pp |= EDP_BLC_ENABLE;
2145 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2147 I915_WRITE(pp_ctrl_reg, pp);
2148 POSTING_READ(pp_ctrl_reg);
2150 pps_unlock(intel_dp);
2153 /* Enable backlight PWM and backlight PP control. */
2154 void intel_edp_backlight_on(struct intel_dp *intel_dp)
2156 if (!is_edp(intel_dp))
2159 DRM_DEBUG_KMS("\n");
2161 intel_panel_enable_backlight(intel_dp->attached_connector);
2162 _intel_edp_backlight_on(intel_dp);
2165 /* Disable backlight in the panel power control. */
2166 static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
2168 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2169 struct drm_i915_private *dev_priv = to_i915(dev);
2171 i915_reg_t pp_ctrl_reg;
2173 if (!is_edp(intel_dp))
2178 pp = ironlake_get_pp_control(intel_dp);
2179 pp &= ~EDP_BLC_ENABLE;
2181 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2183 I915_WRITE(pp_ctrl_reg, pp);
2184 POSTING_READ(pp_ctrl_reg);
2186 pps_unlock(intel_dp);
2188 intel_dp->last_backlight_off = jiffies;
2189 edp_wait_backlight_off(intel_dp);
2192 /* Disable backlight PP control and backlight PWM. */
2193 void intel_edp_backlight_off(struct intel_dp *intel_dp)
2195 if (!is_edp(intel_dp))
2198 DRM_DEBUG_KMS("\n");
2200 _intel_edp_backlight_off(intel_dp);
2201 intel_panel_disable_backlight(intel_dp->attached_connector);
2205 * Hook for controlling the panel power control backlight through the bl_power
2206 * sysfs attribute. Take care to handle multiple calls.
2208 static void intel_edp_backlight_power(struct intel_connector *connector,
2211 struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
2215 is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
2216 pps_unlock(intel_dp);
2218 if (is_enabled == enable)
2221 DRM_DEBUG_KMS("panel power control backlight %s\n",
2222 enable ? "enable" : "disable");
2225 _intel_edp_backlight_on(intel_dp);
2227 _intel_edp_backlight_off(intel_dp);
2230 static void assert_dp_port(struct intel_dp *intel_dp, bool state)
2232 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2233 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2234 bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN;
2236 I915_STATE_WARN(cur_state != state,
2237 "DP port %c state assertion failure (expected %s, current %s)\n",
2238 port_name(dig_port->port),
2239 onoff(state), onoff(cur_state));
2241 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
2243 static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
2245 bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE;
2247 I915_STATE_WARN(cur_state != state,
2248 "eDP PLL state assertion failure (expected %s, current %s)\n",
2249 onoff(state), onoff(cur_state));
2251 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2252 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2254 static void ironlake_edp_pll_on(struct intel_dp *intel_dp,
2255 struct intel_crtc_state *pipe_config)
2257 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2258 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2260 assert_pipe_disabled(dev_priv, crtc->pipe);
2261 assert_dp_port_disabled(intel_dp);
2262 assert_edp_pll_disabled(dev_priv);
2264 DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
2265 pipe_config->port_clock);
2267 intel_dp->DP &= ~DP_PLL_FREQ_MASK;
2269 if (pipe_config->port_clock == 162000)
2270 intel_dp->DP |= DP_PLL_FREQ_162MHZ;
2272 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
2274 I915_WRITE(DP_A, intel_dp->DP);
2279 * [DevILK] Work around required when enabling DP PLL
2280 * while a pipe is enabled going to FDI:
2281 * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
2282 * 2. Program DP PLL enable
2284 if (IS_GEN5(dev_priv))
2285 intel_wait_for_vblank_if_active(&dev_priv->drm, !crtc->pipe);
2287 intel_dp->DP |= DP_PLL_ENABLE;
2289 I915_WRITE(DP_A, intel_dp->DP);
2294 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
2296 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2297 struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
2298 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2300 assert_pipe_disabled(dev_priv, crtc->pipe);
2301 assert_dp_port_disabled(intel_dp);
2302 assert_edp_pll_enabled(dev_priv);
2304 DRM_DEBUG_KMS("disabling eDP PLL\n");
2306 intel_dp->DP &= ~DP_PLL_ENABLE;
2308 I915_WRITE(DP_A, intel_dp->DP);
2313 /* If the sink supports it, try to set the power state appropriately */
2314 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
2318 /* Should have a valid DPCD by this point */
2319 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2322 if (mode != DRM_MODE_DPMS_ON) {
2323 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2327 * When turning on, we need to retry for 1ms to give the sink
2330 for (i = 0; i < 3; i++) {
2331 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2340 DRM_DEBUG_KMS("failed to %s sink power state\n",
2341 mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
2344 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
2347 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2348 enum port port = dp_to_dig_port(intel_dp)->port;
2349 struct drm_device *dev = encoder->base.dev;
2350 struct drm_i915_private *dev_priv = to_i915(dev);
2351 enum intel_display_power_domain power_domain;
2355 power_domain = intel_display_port_power_domain(encoder);
2356 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
2361 tmp = I915_READ(intel_dp->output_reg);
2363 if (!(tmp & DP_PORT_EN))
2366 if (IS_GEN7(dev) && port == PORT_A) {
2367 *pipe = PORT_TO_PIPE_CPT(tmp);
2368 } else if (HAS_PCH_CPT(dev) && port != PORT_A) {
2371 for_each_pipe(dev_priv, p) {
2372 u32 trans_dp = I915_READ(TRANS_DP_CTL(p));
2373 if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) {
2381 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
2382 i915_mmio_reg_offset(intel_dp->output_reg));
2383 } else if (IS_CHERRYVIEW(dev)) {
2384 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
2386 *pipe = PORT_TO_PIPE(tmp);
2392 intel_display_power_put(dev_priv, power_domain);
2397 static void intel_dp_get_config(struct intel_encoder *encoder,
2398 struct intel_crtc_state *pipe_config)
2400 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2402 struct drm_device *dev = encoder->base.dev;
2403 struct drm_i915_private *dev_priv = to_i915(dev);
2404 enum port port = dp_to_dig_port(intel_dp)->port;
2405 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2407 tmp = I915_READ(intel_dp->output_reg);
2409 pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
2411 if (HAS_PCH_CPT(dev) && port != PORT_A) {
2412 u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2414 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
2415 flags |= DRM_MODE_FLAG_PHSYNC;
2417 flags |= DRM_MODE_FLAG_NHSYNC;
2419 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
2420 flags |= DRM_MODE_FLAG_PVSYNC;
2422 flags |= DRM_MODE_FLAG_NVSYNC;
2424 if (tmp & DP_SYNC_HS_HIGH)
2425 flags |= DRM_MODE_FLAG_PHSYNC;
2427 flags |= DRM_MODE_FLAG_NHSYNC;
2429 if (tmp & DP_SYNC_VS_HIGH)
2430 flags |= DRM_MODE_FLAG_PVSYNC;
2432 flags |= DRM_MODE_FLAG_NVSYNC;
2435 pipe_config->base.adjusted_mode.flags |= flags;
2437 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
2438 !IS_CHERRYVIEW(dev) && tmp & DP_COLOR_RANGE_16_235)
2439 pipe_config->limited_color_range = true;
2441 pipe_config->lane_count =
2442 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
2444 intel_dp_get_m_n(crtc, pipe_config);
2446 if (port == PORT_A) {
2447 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
2448 pipe_config->port_clock = 162000;
2450 pipe_config->port_clock = 270000;
2453 pipe_config->base.adjusted_mode.crtc_clock =
2454 intel_dotclock_calculate(pipe_config->port_clock,
2455 &pipe_config->dp_m_n);
2457 if (is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
2458 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
2460 * This is a big fat ugly hack.
2462 * Some machines in UEFI boot mode provide us a VBT that has 18
2463 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2464 * unknown we fail to light up. Yet the same BIOS boots up with
2465 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2466 * max, not what it tells us to use.
2468 * Note: This will still be broken if the eDP panel is not lit
2469 * up by the BIOS, and thus we can't get the mode at module
2472 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2473 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
2474 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
2478 static void intel_disable_dp(struct intel_encoder *encoder,
2479 struct intel_crtc_state *old_crtc_state,
2480 struct drm_connector_state *old_conn_state)
2482 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2483 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2485 if (old_crtc_state->has_audio)
2486 intel_audio_codec_disable(encoder);
2488 if (HAS_PSR(dev_priv) && !HAS_DDI(dev_priv))
2489 intel_psr_disable(intel_dp);
2491 /* Make sure the panel is off before trying to change the mode. But also
2492 * ensure that we have vdd while we switch off the panel. */
2493 intel_edp_panel_vdd_on(intel_dp);
2494 intel_edp_backlight_off(intel_dp);
2495 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2496 intel_edp_panel_off(intel_dp);
2498 /* disable the port before the pipe on g4x */
2499 if (INTEL_GEN(dev_priv) < 5)
2500 intel_dp_link_down(intel_dp);
2503 static void ilk_post_disable_dp(struct intel_encoder *encoder,
2504 struct intel_crtc_state *old_crtc_state,
2505 struct drm_connector_state *old_conn_state)
2507 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2508 enum port port = dp_to_dig_port(intel_dp)->port;
2510 intel_dp_link_down(intel_dp);
2512 /* Only ilk+ has port A */
2514 ironlake_edp_pll_off(intel_dp);
2517 static void vlv_post_disable_dp(struct intel_encoder *encoder,
2518 struct intel_crtc_state *old_crtc_state,
2519 struct drm_connector_state *old_conn_state)
2521 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2523 intel_dp_link_down(intel_dp);
2526 static void chv_post_disable_dp(struct intel_encoder *encoder,
2527 struct intel_crtc_state *old_crtc_state,
2528 struct drm_connector_state *old_conn_state)
2530 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2531 struct drm_device *dev = encoder->base.dev;
2532 struct drm_i915_private *dev_priv = to_i915(dev);
2534 intel_dp_link_down(intel_dp);
2536 mutex_lock(&dev_priv->sb_lock);
2538 /* Assert data lane reset */
2539 chv_data_lane_soft_reset(encoder, true);
2541 mutex_unlock(&dev_priv->sb_lock);
2545 _intel_dp_set_link_train(struct intel_dp *intel_dp,
2547 uint8_t dp_train_pat)
2549 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2550 struct drm_device *dev = intel_dig_port->base.base.dev;
2551 struct drm_i915_private *dev_priv = to_i915(dev);
2552 enum port port = intel_dig_port->port;
2554 if (dp_train_pat & DP_TRAINING_PATTERN_MASK)
2555 DRM_DEBUG_KMS("Using DP training pattern TPS%d\n",
2556 dp_train_pat & DP_TRAINING_PATTERN_MASK);
2559 uint32_t temp = I915_READ(DP_TP_CTL(port));
2561 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2562 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2564 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2566 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2567 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2568 case DP_TRAINING_PATTERN_DISABLE:
2569 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2572 case DP_TRAINING_PATTERN_1:
2573 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2575 case DP_TRAINING_PATTERN_2:
2576 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2578 case DP_TRAINING_PATTERN_3:
2579 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2582 I915_WRITE(DP_TP_CTL(port), temp);
2584 } else if ((IS_GEN7(dev) && port == PORT_A) ||
2585 (HAS_PCH_CPT(dev) && port != PORT_A)) {
2586 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2588 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2589 case DP_TRAINING_PATTERN_DISABLE:
2590 *DP |= DP_LINK_TRAIN_OFF_CPT;
2592 case DP_TRAINING_PATTERN_1:
2593 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2595 case DP_TRAINING_PATTERN_2:
2596 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2598 case DP_TRAINING_PATTERN_3:
2599 DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
2600 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2605 if (IS_CHERRYVIEW(dev))
2606 *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2608 *DP &= ~DP_LINK_TRAIN_MASK;
2610 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2611 case DP_TRAINING_PATTERN_DISABLE:
2612 *DP |= DP_LINK_TRAIN_OFF;
2614 case DP_TRAINING_PATTERN_1:
2615 *DP |= DP_LINK_TRAIN_PAT_1;
2617 case DP_TRAINING_PATTERN_2:
2618 *DP |= DP_LINK_TRAIN_PAT_2;
2620 case DP_TRAINING_PATTERN_3:
2621 if (IS_CHERRYVIEW(dev)) {
2622 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2624 DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
2625 *DP |= DP_LINK_TRAIN_PAT_2;
2632 static void intel_dp_enable_port(struct intel_dp *intel_dp,
2633 struct intel_crtc_state *old_crtc_state)
2635 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2636 struct drm_i915_private *dev_priv = to_i915(dev);
2638 /* enable with pattern 1 (as per spec) */
2640 intel_dp_program_link_training_pattern(intel_dp, DP_TRAINING_PATTERN_1);
2643 * Magic for VLV/CHV. We _must_ first set up the register
2644 * without actually enabling the port, and then do another
2645 * write to enable the port. Otherwise link training will
2646 * fail when the power sequencer is freshly used for this port.
2648 intel_dp->DP |= DP_PORT_EN;
2649 if (old_crtc_state->has_audio)
2650 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
2652 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2653 POSTING_READ(intel_dp->output_reg);
2656 static void intel_enable_dp(struct intel_encoder *encoder,
2657 struct intel_crtc_state *pipe_config)
2659 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2660 struct drm_device *dev = encoder->base.dev;
2661 struct drm_i915_private *dev_priv = to_i915(dev);
2662 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2663 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
2664 enum pipe pipe = crtc->pipe;
2666 if (WARN_ON(dp_reg & DP_PORT_EN))
2671 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
2672 vlv_init_panel_power_sequencer(intel_dp);
2674 intel_dp_enable_port(intel_dp, pipe_config);
2676 edp_panel_vdd_on(intel_dp);
2677 edp_panel_on(intel_dp);
2678 edp_panel_vdd_off(intel_dp, true);
2680 pps_unlock(intel_dp);
2682 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
2683 unsigned int lane_mask = 0x0;
2685 if (IS_CHERRYVIEW(dev))
2686 lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count);
2688 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
2692 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2693 intel_dp_start_link_train(intel_dp);
2694 intel_dp_stop_link_train(intel_dp);
2696 if (pipe_config->has_audio) {
2697 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
2699 intel_audio_codec_enable(encoder);
2703 static void g4x_enable_dp(struct intel_encoder *encoder,
2704 struct intel_crtc_state *pipe_config,
2705 struct drm_connector_state *conn_state)
2707 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2709 intel_enable_dp(encoder, pipe_config);
2710 intel_edp_backlight_on(intel_dp);
2713 static void vlv_enable_dp(struct intel_encoder *encoder,
2714 struct intel_crtc_state *pipe_config,
2715 struct drm_connector_state *conn_state)
2717 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2719 intel_edp_backlight_on(intel_dp);
2720 intel_psr_enable(intel_dp);
2723 static void g4x_pre_enable_dp(struct intel_encoder *encoder,
2724 struct intel_crtc_state *pipe_config,
2725 struct drm_connector_state *conn_state)
2727 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2728 enum port port = dp_to_dig_port(intel_dp)->port;
2730 intel_dp_prepare(encoder, pipe_config);
2732 /* Only ilk+ has port A */
2734 ironlake_edp_pll_on(intel_dp, pipe_config);
2737 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
2739 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2740 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
2741 enum pipe pipe = intel_dp->pps_pipe;
2742 i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe);
2744 edp_panel_vdd_off_sync(intel_dp);
2747 * VLV seems to get confused when multiple power seqeuencers
2748 * have the same port selected (even if only one has power/vdd
2749 * enabled). The failure manifests as vlv_wait_port_ready() failing
2750 * CHV on the other hand doesn't seem to mind having the same port
2751 * selected in multiple power seqeuencers, but let's clear the
2752 * port select always when logically disconnecting a power sequencer
2755 DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2756 pipe_name(pipe), port_name(intel_dig_port->port));
2757 I915_WRITE(pp_on_reg, 0);
2758 POSTING_READ(pp_on_reg);
2760 intel_dp->pps_pipe = INVALID_PIPE;
2763 static void vlv_steal_power_sequencer(struct drm_device *dev,
2766 struct drm_i915_private *dev_priv = to_i915(dev);
2767 struct intel_encoder *encoder;
2769 lockdep_assert_held(&dev_priv->pps_mutex);
2771 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
2774 for_each_intel_encoder(dev, encoder) {
2775 struct intel_dp *intel_dp;
2778 if (encoder->type != INTEL_OUTPUT_EDP)
2781 intel_dp = enc_to_intel_dp(&encoder->base);
2782 port = dp_to_dig_port(intel_dp)->port;
2784 if (intel_dp->pps_pipe != pipe)
2787 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
2788 pipe_name(pipe), port_name(port));
2790 WARN(encoder->base.crtc,
2791 "stealing pipe %c power sequencer from active eDP port %c\n",
2792 pipe_name(pipe), port_name(port));
2794 /* make sure vdd is off before we steal it */
2795 vlv_detach_power_sequencer(intel_dp);
2799 static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
2801 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2802 struct intel_encoder *encoder = &intel_dig_port->base;
2803 struct drm_device *dev = encoder->base.dev;
2804 struct drm_i915_private *dev_priv = to_i915(dev);
2805 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2807 lockdep_assert_held(&dev_priv->pps_mutex);
2809 if (!is_edp(intel_dp))
2812 if (intel_dp->pps_pipe == crtc->pipe)
2816 * If another power sequencer was being used on this
2817 * port previously make sure to turn off vdd there while
2818 * we still have control of it.
2820 if (intel_dp->pps_pipe != INVALID_PIPE)
2821 vlv_detach_power_sequencer(intel_dp);
2824 * We may be stealing the power
2825 * sequencer from another port.
2827 vlv_steal_power_sequencer(dev, crtc->pipe);
2829 /* now it's all ours */
2830 intel_dp->pps_pipe = crtc->pipe;
2832 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2833 pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
2835 /* init power sequencer on this pipe and port */
2836 intel_dp_init_panel_power_sequencer(dev, intel_dp);
2837 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
2840 static void vlv_pre_enable_dp(struct intel_encoder *encoder,
2841 struct intel_crtc_state *pipe_config,
2842 struct drm_connector_state *conn_state)
2844 vlv_phy_pre_encoder_enable(encoder);
2846 intel_enable_dp(encoder, pipe_config);
2849 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder,
2850 struct intel_crtc_state *pipe_config,
2851 struct drm_connector_state *conn_state)
2853 intel_dp_prepare(encoder, pipe_config);
2855 vlv_phy_pre_pll_enable(encoder);
2858 static void chv_pre_enable_dp(struct intel_encoder *encoder,
2859 struct intel_crtc_state *pipe_config,
2860 struct drm_connector_state *conn_state)
2862 chv_phy_pre_encoder_enable(encoder);
2864 intel_enable_dp(encoder, pipe_config);
2866 /* Second common lane will stay alive on its own now */
2867 chv_phy_release_cl2_override(encoder);
2870 static void chv_dp_pre_pll_enable(struct intel_encoder *encoder,
2871 struct intel_crtc_state *pipe_config,
2872 struct drm_connector_state *conn_state)
2874 intel_dp_prepare(encoder, pipe_config);
2876 chv_phy_pre_pll_enable(encoder);
2879 static void chv_dp_post_pll_disable(struct intel_encoder *encoder,
2880 struct intel_crtc_state *pipe_config,
2881 struct drm_connector_state *conn_state)
2883 chv_phy_post_pll_disable(encoder);
2887 * Fetch AUX CH registers 0x202 - 0x207 which contain
2888 * link status information
2891 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
2893 return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status,
2894 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
2897 /* These are source-specific values. */
2899 intel_dp_voltage_max(struct intel_dp *intel_dp)
2901 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2902 struct drm_i915_private *dev_priv = to_i915(dev);
2903 enum port port = dp_to_dig_port(intel_dp)->port;
2905 if (IS_BROXTON(dev))
2906 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
2907 else if (INTEL_INFO(dev)->gen >= 9) {
2908 if (dev_priv->vbt.edp.low_vswing && port == PORT_A)
2909 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
2910 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
2911 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
2912 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
2913 else if (IS_GEN7(dev) && port == PORT_A)
2914 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
2915 else if (HAS_PCH_CPT(dev) && port != PORT_A)
2916 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
2918 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
2922 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2924 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2925 enum port port = dp_to_dig_port(intel_dp)->port;
2927 if (INTEL_INFO(dev)->gen >= 9) {
2928 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2929 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2930 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2931 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2932 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2933 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2934 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2935 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2936 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2938 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2940 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2941 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2942 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2943 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2944 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2945 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2946 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2947 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2948 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2950 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2952 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
2953 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2954 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2955 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2956 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2957 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2958 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2959 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2960 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2962 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2964 } else if (IS_GEN7(dev) && port == PORT_A) {
2965 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2966 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2967 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2968 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2969 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2970 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2972 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2975 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2976 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2977 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2978 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2979 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2980 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2981 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2982 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2984 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2989 static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
2991 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
2992 unsigned long demph_reg_value, preemph_reg_value,
2993 uniqtranscale_reg_value;
2994 uint8_t train_set = intel_dp->train_set[0];
2996 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2997 case DP_TRAIN_PRE_EMPH_LEVEL_0:
2998 preemph_reg_value = 0x0004000;
2999 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3000 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3001 demph_reg_value = 0x2B405555;
3002 uniqtranscale_reg_value = 0x552AB83A;
3004 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3005 demph_reg_value = 0x2B404040;
3006 uniqtranscale_reg_value = 0x5548B83A;
3008 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3009 demph_reg_value = 0x2B245555;
3010 uniqtranscale_reg_value = 0x5560B83A;
3012 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3013 demph_reg_value = 0x2B405555;
3014 uniqtranscale_reg_value = 0x5598DA3A;
3020 case DP_TRAIN_PRE_EMPH_LEVEL_1:
3021 preemph_reg_value = 0x0002000;
3022 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3023 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3024 demph_reg_value = 0x2B404040;
3025 uniqtranscale_reg_value = 0x5552B83A;
3027 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3028 demph_reg_value = 0x2B404848;
3029 uniqtranscale_reg_value = 0x5580B83A;
3031 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3032 demph_reg_value = 0x2B404040;
3033 uniqtranscale_reg_value = 0x55ADDA3A;
3039 case DP_TRAIN_PRE_EMPH_LEVEL_2:
3040 preemph_reg_value = 0x0000000;
3041 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3042 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3043 demph_reg_value = 0x2B305555;
3044 uniqtranscale_reg_value = 0x5570B83A;
3046 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3047 demph_reg_value = 0x2B2B4040;
3048 uniqtranscale_reg_value = 0x55ADDA3A;
3054 case DP_TRAIN_PRE_EMPH_LEVEL_3:
3055 preemph_reg_value = 0x0006000;
3056 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3057 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3058 demph_reg_value = 0x1B405555;
3059 uniqtranscale_reg_value = 0x55ADDA3A;
3069 vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value,
3070 uniqtranscale_reg_value, 0);
3075 static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
3077 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3078 u32 deemph_reg_value, margin_reg_value;
3079 bool uniq_trans_scale = false;
3080 uint8_t train_set = intel_dp->train_set[0];
3082 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3083 case DP_TRAIN_PRE_EMPH_LEVEL_0:
3084 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3085 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3086 deemph_reg_value = 128;
3087 margin_reg_value = 52;
3089 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3090 deemph_reg_value = 128;
3091 margin_reg_value = 77;
3093 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3094 deemph_reg_value = 128;
3095 margin_reg_value = 102;
3097 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3098 deemph_reg_value = 128;
3099 margin_reg_value = 154;
3100 uniq_trans_scale = true;
3106 case DP_TRAIN_PRE_EMPH_LEVEL_1:
3107 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3108 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3109 deemph_reg_value = 85;
3110 margin_reg_value = 78;
3112 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3113 deemph_reg_value = 85;
3114 margin_reg_value = 116;
3116 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3117 deemph_reg_value = 85;
3118 margin_reg_value = 154;
3124 case DP_TRAIN_PRE_EMPH_LEVEL_2:
3125 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3126 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3127 deemph_reg_value = 64;
3128 margin_reg_value = 104;
3130 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3131 deemph_reg_value = 64;
3132 margin_reg_value = 154;
3138 case DP_TRAIN_PRE_EMPH_LEVEL_3:
3139 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3140 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3141 deemph_reg_value = 43;
3142 margin_reg_value = 154;
3152 chv_set_phy_signal_level(encoder, deemph_reg_value,
3153 margin_reg_value, uniq_trans_scale);
3159 gen4_signal_levels(uint8_t train_set)
3161 uint32_t signal_levels = 0;
3163 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3164 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3166 signal_levels |= DP_VOLTAGE_0_4;
3168 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3169 signal_levels |= DP_VOLTAGE_0_6;
3171 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3172 signal_levels |= DP_VOLTAGE_0_8;
3174 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3175 signal_levels |= DP_VOLTAGE_1_2;
3178 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3179 case DP_TRAIN_PRE_EMPH_LEVEL_0:
3181 signal_levels |= DP_PRE_EMPHASIS_0;
3183 case DP_TRAIN_PRE_EMPH_LEVEL_1:
3184 signal_levels |= DP_PRE_EMPHASIS_3_5;
3186 case DP_TRAIN_PRE_EMPH_LEVEL_2:
3187 signal_levels |= DP_PRE_EMPHASIS_6;
3189 case DP_TRAIN_PRE_EMPH_LEVEL_3:
3190 signal_levels |= DP_PRE_EMPHASIS_9_5;
3193 return signal_levels;
3196 /* Gen6's DP voltage swing and pre-emphasis control */
3198 gen6_edp_signal_levels(uint8_t train_set)
3200 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3201 DP_TRAIN_PRE_EMPHASIS_MASK);
3202 switch (signal_levels) {
3203 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3204 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3205 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3206 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3207 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
3208 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3209 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3210 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
3211 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3212 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3213 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
3214 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3215 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3216 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
3218 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3219 "0x%x\n", signal_levels);
3220 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3224 /* Gen7's DP voltage swing and pre-emphasis control */
3226 gen7_edp_signal_levels(uint8_t train_set)
3228 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3229 DP_TRAIN_PRE_EMPHASIS_MASK);
3230 switch (signal_levels) {
3231 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3232 return EDP_LINK_TRAIN_400MV_0DB_IVB;
3233 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3234 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
3235 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3236 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3238 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3239 return EDP_LINK_TRAIN_600MV_0DB_IVB;
3240 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3241 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3243 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3244 return EDP_LINK_TRAIN_800MV_0DB_IVB;
3245 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3246 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3249 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3250 "0x%x\n", signal_levels);
3251 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3256 intel_dp_set_signal_levels(struct intel_dp *intel_dp)
3258 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3259 enum port port = intel_dig_port->port;
3260 struct drm_device *dev = intel_dig_port->base.base.dev;
3261 struct drm_i915_private *dev_priv = to_i915(dev);
3262 uint32_t signal_levels, mask = 0;
3263 uint8_t train_set = intel_dp->train_set[0];
3266 signal_levels = ddi_signal_levels(intel_dp);
3268 if (IS_BROXTON(dev))
3271 mask = DDI_BUF_EMP_MASK;
3272 } else if (IS_CHERRYVIEW(dev)) {
3273 signal_levels = chv_signal_levels(intel_dp);
3274 } else if (IS_VALLEYVIEW(dev)) {
3275 signal_levels = vlv_signal_levels(intel_dp);
3276 } else if (IS_GEN7(dev) && port == PORT_A) {
3277 signal_levels = gen7_edp_signal_levels(train_set);
3278 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
3279 } else if (IS_GEN6(dev) && port == PORT_A) {
3280 signal_levels = gen6_edp_signal_levels(train_set);
3281 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3283 signal_levels = gen4_signal_levels(train_set);
3284 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3288 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3290 DRM_DEBUG_KMS("Using vswing level %d\n",
3291 train_set & DP_TRAIN_VOLTAGE_SWING_MASK);
3292 DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3293 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
3294 DP_TRAIN_PRE_EMPHASIS_SHIFT);
3296 intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels;
3298 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3299 POSTING_READ(intel_dp->output_reg);
3303 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
3304 uint8_t dp_train_pat)
3306 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3307 struct drm_i915_private *dev_priv =
3308 to_i915(intel_dig_port->base.base.dev);
3310 _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat);
3312 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3313 POSTING_READ(intel_dp->output_reg);
3316 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3318 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3319 struct drm_device *dev = intel_dig_port->base.base.dev;
3320 struct drm_i915_private *dev_priv = to_i915(dev);
3321 enum port port = intel_dig_port->port;
3327 val = I915_READ(DP_TP_CTL(port));
3328 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3329 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3330 I915_WRITE(DP_TP_CTL(port), val);
3333 * On PORT_A we can have only eDP in SST mode. There the only reason
3334 * we need to set idle transmission mode is to work around a HW issue
3335 * where we enable the pipe while not in idle link-training mode.
3336 * In this case there is requirement to wait for a minimum number of
3337 * idle patterns to be sent.
3342 if (intel_wait_for_register(dev_priv,DP_TP_STATUS(port),
3343 DP_TP_STATUS_IDLE_DONE,
3344 DP_TP_STATUS_IDLE_DONE,
3346 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3350 intel_dp_link_down(struct intel_dp *intel_dp)
3352 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3353 struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
3354 enum port port = intel_dig_port->port;
3355 struct drm_device *dev = intel_dig_port->base.base.dev;
3356 struct drm_i915_private *dev_priv = to_i915(dev);
3357 uint32_t DP = intel_dp->DP;
3359 if (WARN_ON(HAS_DDI(dev)))
3362 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
3365 DRM_DEBUG_KMS("\n");
3367 if ((IS_GEN7(dev) && port == PORT_A) ||
3368 (HAS_PCH_CPT(dev) && port != PORT_A)) {
3369 DP &= ~DP_LINK_TRAIN_MASK_CPT;
3370 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
3372 if (IS_CHERRYVIEW(dev))
3373 DP &= ~DP_LINK_TRAIN_MASK_CHV;
3375 DP &= ~DP_LINK_TRAIN_MASK;
3376 DP |= DP_LINK_TRAIN_PAT_IDLE;
3378 I915_WRITE(intel_dp->output_reg, DP);
3379 POSTING_READ(intel_dp->output_reg);
3381 DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
3382 I915_WRITE(intel_dp->output_reg, DP);
3383 POSTING_READ(intel_dp->output_reg);
3386 * HW workaround for IBX, we need to move the port
3387 * to transcoder A after disabling it to allow the
3388 * matching HDMI port to be enabled on transcoder A.
3390 if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B && port != PORT_A) {
3392 * We get CPU/PCH FIFO underruns on the other pipe when
3393 * doing the workaround. Sweep them under the rug.
3395 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3396 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3398 /* always enable with pattern 1 (as per spec) */
3399 DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK);
3400 DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1;
3401 I915_WRITE(intel_dp->output_reg, DP);
3402 POSTING_READ(intel_dp->output_reg);
3405 I915_WRITE(intel_dp->output_reg, DP);
3406 POSTING_READ(intel_dp->output_reg);
3408 intel_wait_for_vblank_if_active(&dev_priv->drm, PIPE_A);
3409 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3410 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3413 msleep(intel_dp->panel_power_down_delay);
3419 intel_dp_read_dpcd(struct intel_dp *intel_dp)
3421 if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd,
3422 sizeof(intel_dp->dpcd)) < 0)
3423 return false; /* aux transfer failed */
3425 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
3427 return intel_dp->dpcd[DP_DPCD_REV] != 0;
3431 intel_edp_init_dpcd(struct intel_dp *intel_dp)
3433 struct drm_i915_private *dev_priv =
3434 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
3436 /* this function is meant to be called only once */
3437 WARN_ON(intel_dp->dpcd[DP_DPCD_REV] != 0);
3439 if (!intel_dp_read_dpcd(intel_dp))
3442 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3443 dev_priv->no_aux_handshake = intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3444 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3446 /* Check if the panel supports PSR */
3447 drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT,
3449 sizeof(intel_dp->psr_dpcd));
3450 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3451 dev_priv->psr.sink_support = true;
3452 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3455 if (INTEL_GEN(dev_priv) >= 9 &&
3456 (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) {
3457 uint8_t frame_sync_cap;
3459 dev_priv->psr.sink_support = true;
3460 drm_dp_dpcd_read(&intel_dp->aux,
3461 DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP,
3462 &frame_sync_cap, 1);
3463 dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false;
3464 /* PSR2 needs frame sync as well */
3465 dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync;
3466 DRM_DEBUG_KMS("PSR2 %s on sink",
3467 dev_priv->psr.psr2_support ? "supported" : "not supported");
3470 /* Read the eDP Display control capabilities registers */
3471 if ((intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
3472 drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
3473 intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd) ==
3474 sizeof(intel_dp->edp_dpcd)))
3475 DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int) sizeof(intel_dp->edp_dpcd),
3476 intel_dp->edp_dpcd);
3478 /* Intermediate frequency support */
3479 if (intel_dp->edp_dpcd[0] >= 0x03) { /* eDp v1.4 or higher */
3480 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
3483 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
3484 sink_rates, sizeof(sink_rates));
3486 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
3487 int val = le16_to_cpu(sink_rates[i]);
3492 /* Value read is in kHz while drm clock is saved in deca-kHz */
3493 intel_dp->sink_rates[i] = (val * 200) / 10;
3495 intel_dp->num_sink_rates = i;
3503 intel_dp_get_dpcd(struct intel_dp *intel_dp)
3505 if (!intel_dp_read_dpcd(intel_dp))
3508 if (drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT,
3509 &intel_dp->sink_count, 1) < 0)
3513 * Sink count can change between short pulse hpd hence
3514 * a member variable in intel_dp will track any changes
3515 * between short pulse interrupts.
3517 intel_dp->sink_count = DP_GET_SINK_COUNT(intel_dp->sink_count);
3520 * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
3521 * a dongle is present but no display. Unless we require to know
3522 * if a dongle is present or not, we don't need to update
3523 * downstream port information. So, an early return here saves
3524 * time from performing other operations which are not required.
3526 if (!is_edp(intel_dp) && !intel_dp->sink_count)
3529 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3530 DP_DWN_STRM_PORT_PRESENT))
3531 return true; /* native DP sink */
3533 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3534 return true; /* no per-port downstream info */
3536 if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3537 intel_dp->downstream_ports,
3538 DP_MAX_DOWNSTREAM_PORTS) < 0)
3539 return false; /* downstream port status fetch failed */
3545 intel_dp_probe_oui(struct intel_dp *intel_dp)
3549 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3552 if (drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
3553 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3554 buf[0], buf[1], buf[2]);
3556 if (drm_dp_dpcd_read(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
3557 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3558 buf[0], buf[1], buf[2]);
3562 intel_dp_can_mst(struct intel_dp *intel_dp)
3566 if (!i915.enable_dp_mst)
3569 if (!intel_dp->can_mst)
3572 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3575 if (drm_dp_dpcd_read(&intel_dp->aux, DP_MSTM_CAP, buf, 1) != 1)
3578 return buf[0] & DP_MST_CAP;
3582 intel_dp_configure_mst(struct intel_dp *intel_dp)
3584 if (!i915.enable_dp_mst)
3587 if (!intel_dp->can_mst)
3590 intel_dp->is_mst = intel_dp_can_mst(intel_dp);
3592 if (intel_dp->is_mst)
3593 DRM_DEBUG_KMS("Sink is MST capable\n");
3595 DRM_DEBUG_KMS("Sink is not MST capable\n");
3597 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
3601 static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp)
3603 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3604 struct drm_device *dev = dig_port->base.base.dev;
3605 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3611 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) {
3612 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3617 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3618 buf & ~DP_TEST_SINK_START) < 0) {
3619 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3625 intel_wait_for_vblank(dev, intel_crtc->pipe);
3627 if (drm_dp_dpcd_readb(&intel_dp->aux,
3628 DP_TEST_SINK_MISC, &buf) < 0) {
3632 count = buf & DP_TEST_COUNT_MASK;
3633 } while (--attempts && count);
3635 if (attempts == 0) {
3636 DRM_DEBUG_KMS("TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped\n");
3641 hsw_enable_ips(intel_crtc);
3645 static int intel_dp_sink_crc_start(struct intel_dp *intel_dp)
3647 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3648 struct drm_device *dev = dig_port->base.base.dev;
3649 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3653 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
3656 if (!(buf & DP_TEST_CRC_SUPPORTED))
3659 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
3662 if (buf & DP_TEST_SINK_START) {
3663 ret = intel_dp_sink_crc_stop(intel_dp);
3668 hsw_disable_ips(intel_crtc);
3670 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3671 buf | DP_TEST_SINK_START) < 0) {
3672 hsw_enable_ips(intel_crtc);
3676 intel_wait_for_vblank(dev, intel_crtc->pipe);
3680 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3682 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3683 struct drm_device *dev = dig_port->base.base.dev;
3684 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3689 ret = intel_dp_sink_crc_start(intel_dp);
3694 intel_wait_for_vblank(dev, intel_crtc->pipe);
3696 if (drm_dp_dpcd_readb(&intel_dp->aux,
3697 DP_TEST_SINK_MISC, &buf) < 0) {
3701 count = buf & DP_TEST_COUNT_MASK;
3703 } while (--attempts && count == 0);
3705 if (attempts == 0) {
3706 DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n");
3711 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) {
3717 intel_dp_sink_crc_stop(intel_dp);
3722 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3724 return drm_dp_dpcd_read(&intel_dp->aux,
3725 DP_DEVICE_SERVICE_IRQ_VECTOR,
3726 sink_irq_vector, 1) == 1;
3730 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3734 ret = drm_dp_dpcd_read(&intel_dp->aux,
3736 sink_irq_vector, 14);
3743 static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
3745 uint8_t test_result = DP_TEST_ACK;
3749 static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
3751 uint8_t test_result = DP_TEST_NAK;
3755 static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
3757 uint8_t test_result = DP_TEST_NAK;
3758 struct intel_connector *intel_connector = intel_dp->attached_connector;
3759 struct drm_connector *connector = &intel_connector->base;
3761 if (intel_connector->detect_edid == NULL ||
3762 connector->edid_corrupt ||
3763 intel_dp->aux.i2c_defer_count > 6) {
3764 /* Check EDID read for NACKs, DEFERs and corruption
3765 * (DP CTS 1.2 Core r1.1)
3766 * 4.2.2.4 : Failed EDID read, I2C_NAK
3767 * 4.2.2.5 : Failed EDID read, I2C_DEFER
3768 * 4.2.2.6 : EDID corruption detected
3769 * Use failsafe mode for all cases
3771 if (intel_dp->aux.i2c_nack_count > 0 ||
3772 intel_dp->aux.i2c_defer_count > 0)
3773 DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
3774 intel_dp->aux.i2c_nack_count,
3775 intel_dp->aux.i2c_defer_count);
3776 intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_FAILSAFE;
3778 struct edid *block = intel_connector->detect_edid;
3780 /* We have to write the checksum
3781 * of the last block read
3783 block += intel_connector->detect_edid->extensions;
3785 if (!drm_dp_dpcd_write(&intel_dp->aux,
3786 DP_TEST_EDID_CHECKSUM,
3789 DRM_DEBUG_KMS("Failed to write EDID checksum\n");
3791 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
3792 intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_STANDARD;
3795 /* Set test active flag here so userspace doesn't interrupt things */
3796 intel_dp->compliance_test_active = 1;
3801 static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
3803 uint8_t test_result = DP_TEST_NAK;
3807 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
3809 uint8_t response = DP_TEST_NAK;
3813 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_REQUEST, &rxdata, 1);
3815 DRM_DEBUG_KMS("Could not read test request from sink\n");
3820 case DP_TEST_LINK_TRAINING:
3821 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
3822 intel_dp->compliance_test_type = DP_TEST_LINK_TRAINING;
3823 response = intel_dp_autotest_link_training(intel_dp);
3825 case DP_TEST_LINK_VIDEO_PATTERN:
3826 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
3827 intel_dp->compliance_test_type = DP_TEST_LINK_VIDEO_PATTERN;
3828 response = intel_dp_autotest_video_pattern(intel_dp);
3830 case DP_TEST_LINK_EDID_READ:
3831 DRM_DEBUG_KMS("EDID test requested\n");
3832 intel_dp->compliance_test_type = DP_TEST_LINK_EDID_READ;
3833 response = intel_dp_autotest_edid(intel_dp);
3835 case DP_TEST_LINK_PHY_TEST_PATTERN:
3836 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
3837 intel_dp->compliance_test_type = DP_TEST_LINK_PHY_TEST_PATTERN;
3838 response = intel_dp_autotest_phy_pattern(intel_dp);
3841 DRM_DEBUG_KMS("Invalid test request '%02x'\n", rxdata);
3846 status = drm_dp_dpcd_write(&intel_dp->aux,
3850 DRM_DEBUG_KMS("Could not write test response to sink\n");
3854 intel_dp_check_mst_status(struct intel_dp *intel_dp)
3858 if (intel_dp->is_mst) {
3863 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3867 /* check link status - esi[10] = 0x200c */
3868 if (intel_dp->active_mst_links &&
3869 !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
3870 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
3871 intel_dp_start_link_train(intel_dp);
3872 intel_dp_stop_link_train(intel_dp);
3875 DRM_DEBUG_KMS("got esi %3ph\n", esi);
3876 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
3879 for (retry = 0; retry < 3; retry++) {
3881 wret = drm_dp_dpcd_write(&intel_dp->aux,
3882 DP_SINK_COUNT_ESI+1,
3889 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3891 DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
3899 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3900 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
3901 intel_dp->is_mst = false;
3902 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3903 /* send a hotplug event */
3904 drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
3911 intel_dp_check_link_status(struct intel_dp *intel_dp)
3913 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
3914 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3915 u8 link_status[DP_LINK_STATUS_SIZE];
3917 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
3919 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3920 DRM_ERROR("Failed to get link status\n");
3924 if (!intel_encoder->base.crtc)
3927 if (!to_intel_crtc(intel_encoder->base.crtc)->active)
3930 /* if link training is requested we should perform it always */
3931 if ((intel_dp->compliance_test_type == DP_TEST_LINK_TRAINING) ||
3932 (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count))) {
3933 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
3934 intel_encoder->base.name);
3935 intel_dp_start_link_train(intel_dp);
3936 intel_dp_stop_link_train(intel_dp);
3941 * According to DP spec
3944 * 2. Configure link according to Receiver Capabilities
3945 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
3946 * 4. Check link status on receipt of hot-plug interrupt
3948 * intel_dp_short_pulse - handles short pulse interrupts
3949 * when full detection is not required.
3950 * Returns %true if short pulse is handled and full detection
3951 * is NOT required and %false otherwise.
3954 intel_dp_short_pulse(struct intel_dp *intel_dp)
3956 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3957 u8 sink_irq_vector = 0;
3958 u8 old_sink_count = intel_dp->sink_count;
3962 * Clearing compliance test variables to allow capturing
3963 * of values for next automated test request.
3965 intel_dp->compliance_test_active = 0;
3966 intel_dp->compliance_test_type = 0;
3967 intel_dp->compliance_test_data = 0;
3970 * Now read the DPCD to see if it's actually running
3971 * If the current value of sink count doesn't match with
3972 * the value that was stored earlier or dpcd read failed
3973 * we need to do full detection
3975 ret = intel_dp_get_dpcd(intel_dp);
3977 if ((old_sink_count != intel_dp->sink_count) || !ret) {
3978 /* No need to proceed if we are going to do full detect */
3982 /* Try to read the source of the interrupt */
3983 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3984 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) &&
3985 sink_irq_vector != 0) {
3986 /* Clear interrupt source */
3987 drm_dp_dpcd_writeb(&intel_dp->aux,
3988 DP_DEVICE_SERVICE_IRQ_VECTOR,
3991 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
3992 DRM_DEBUG_DRIVER("Test request in short pulse not handled\n");
3993 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
3994 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3997 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
3998 intel_dp_check_link_status(intel_dp);
3999 drm_modeset_unlock(&dev->mode_config.connection_mutex);
4004 /* XXX this is probably wrong for multiple downstream ports */
4005 static enum drm_connector_status
4006 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
4008 uint8_t *dpcd = intel_dp->dpcd;
4011 if (!intel_dp_get_dpcd(intel_dp))
4012 return connector_status_disconnected;
4014 if (is_edp(intel_dp))
4015 return connector_status_connected;
4017 /* if there's no downstream port, we're done */
4018 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
4019 return connector_status_connected;
4021 /* If we're HPD-aware, SINK_COUNT changes dynamically */
4022 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4023 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
4025 return intel_dp->sink_count ?
4026 connector_status_connected : connector_status_disconnected;
4029 if (intel_dp_can_mst(intel_dp))
4030 return connector_status_connected;
4032 /* If no HPD, poke DDC gently */
4033 if (drm_probe_ddc(&intel_dp->aux.ddc))
4034 return connector_status_connected;
4036 /* Well we tried, say unknown for unreliable port types */
4037 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4038 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4039 if (type == DP_DS_PORT_TYPE_VGA ||
4040 type == DP_DS_PORT_TYPE_NON_EDID)
4041 return connector_status_unknown;
4043 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4044 DP_DWN_STRM_PORT_TYPE_MASK;
4045 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4046 type == DP_DWN_STRM_PORT_TYPE_OTHER)
4047 return connector_status_unknown;
4050 /* Anything else is out of spec, warn and ignore */
4051 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4052 return connector_status_disconnected;
4055 static enum drm_connector_status
4056 edp_detect(struct intel_dp *intel_dp)
4058 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4059 enum drm_connector_status status;
4061 status = intel_panel_detect(dev);
4062 if (status == connector_status_unknown)
4063 status = connector_status_connected;
4068 static bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
4069 struct intel_digital_port *port)
4073 switch (port->port) {
4077 bit = SDE_PORTB_HOTPLUG;
4080 bit = SDE_PORTC_HOTPLUG;
4083 bit = SDE_PORTD_HOTPLUG;
4086 MISSING_CASE(port->port);
4090 return I915_READ(SDEISR) & bit;
4093 static bool cpt_digital_port_connected(struct drm_i915_private *dev_priv,
4094 struct intel_digital_port *port)
4098 switch (port->port) {
4102 bit = SDE_PORTB_HOTPLUG_CPT;
4105 bit = SDE_PORTC_HOTPLUG_CPT;
4108 bit = SDE_PORTD_HOTPLUG_CPT;
4111 bit = SDE_PORTE_HOTPLUG_SPT;
4114 MISSING_CASE(port->port);
4118 return I915_READ(SDEISR) & bit;
4121 static bool g4x_digital_port_connected(struct drm_i915_private *dev_priv,
4122 struct intel_digital_port *port)
4126 switch (port->port) {
4128 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4131 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4134 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4137 MISSING_CASE(port->port);
4141 return I915_READ(PORT_HOTPLUG_STAT) & bit;
4144 static bool gm45_digital_port_connected(struct drm_i915_private *dev_priv,
4145 struct intel_digital_port *port)
4149 switch (port->port) {
4151 bit = PORTB_HOTPLUG_LIVE_STATUS_GM45;
4154 bit = PORTC_HOTPLUG_LIVE_STATUS_GM45;
4157 bit = PORTD_HOTPLUG_LIVE_STATUS_GM45;
4160 MISSING_CASE(port->port);
4164 return I915_READ(PORT_HOTPLUG_STAT) & bit;
4167 static bool bxt_digital_port_connected(struct drm_i915_private *dev_priv,
4168 struct intel_digital_port *intel_dig_port)
4170 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4174 intel_hpd_pin_to_port(intel_encoder->hpd_pin, &port);
4177 bit = BXT_DE_PORT_HP_DDIA;
4180 bit = BXT_DE_PORT_HP_DDIB;
4183 bit = BXT_DE_PORT_HP_DDIC;
4190 return I915_READ(GEN8_DE_PORT_ISR) & bit;
4194 * intel_digital_port_connected - is the specified port connected?
4195 * @dev_priv: i915 private structure
4196 * @port: the port to test
4198 * Return %true if @port is connected, %false otherwise.
4200 bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
4201 struct intel_digital_port *port)
4203 if (HAS_PCH_IBX(dev_priv))
4204 return ibx_digital_port_connected(dev_priv, port);
4205 else if (HAS_PCH_SPLIT(dev_priv))
4206 return cpt_digital_port_connected(dev_priv, port);
4207 else if (IS_BROXTON(dev_priv))
4208 return bxt_digital_port_connected(dev_priv, port);
4209 else if (IS_GM45(dev_priv))
4210 return gm45_digital_port_connected(dev_priv, port);
4212 return g4x_digital_port_connected(dev_priv, port);
4215 static struct edid *
4216 intel_dp_get_edid(struct intel_dp *intel_dp)
4218 struct intel_connector *intel_connector = intel_dp->attached_connector;
4220 /* use cached edid if we have one */
4221 if (intel_connector->edid) {
4223 if (IS_ERR(intel_connector->edid))
4226 return drm_edid_duplicate(intel_connector->edid);
4228 return drm_get_edid(&intel_connector->base,
4229 &intel_dp->aux.ddc);
4233 intel_dp_set_edid(struct intel_dp *intel_dp)
4235 struct intel_connector *intel_connector = intel_dp->attached_connector;
4238 intel_dp_unset_edid(intel_dp);
4239 edid = intel_dp_get_edid(intel_dp);
4240 intel_connector->detect_edid = edid;
4242 if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
4243 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
4245 intel_dp->has_audio = drm_detect_monitor_audio(edid);
4249 intel_dp_unset_edid(struct intel_dp *intel_dp)
4251 struct intel_connector *intel_connector = intel_dp->attached_connector;
4253 kfree(intel_connector->detect_edid);
4254 intel_connector->detect_edid = NULL;
4256 intel_dp->has_audio = false;
4260 intel_dp_long_pulse(struct intel_connector *intel_connector)
4262 struct drm_connector *connector = &intel_connector->base;
4263 struct intel_dp *intel_dp = intel_attached_dp(connector);
4264 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4265 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4266 struct drm_device *dev = connector->dev;
4267 enum drm_connector_status status;
4268 enum intel_display_power_domain power_domain;
4269 u8 sink_irq_vector = 0;
4271 power_domain = intel_display_port_aux_power_domain(intel_encoder);
4272 intel_display_power_get(to_i915(dev), power_domain);
4274 /* Can't disconnect eDP, but you can close the lid... */
4275 if (is_edp(intel_dp))
4276 status = edp_detect(intel_dp);
4277 else if (intel_digital_port_connected(to_i915(dev),
4278 dp_to_dig_port(intel_dp)))
4279 status = intel_dp_detect_dpcd(intel_dp);
4281 status = connector_status_disconnected;
4283 if (status != connector_status_connected) {
4284 intel_dp->compliance_test_active = 0;
4285 intel_dp->compliance_test_type = 0;
4286 intel_dp->compliance_test_data = 0;
4288 if (intel_dp->is_mst) {
4289 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4291 intel_dp->mst_mgr.mst_state);
4292 intel_dp->is_mst = false;
4293 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4300 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4301 intel_encoder->type = INTEL_OUTPUT_DP;
4303 DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n",
4304 yesno(intel_dp_source_supports_hbr2(intel_dp)),
4305 yesno(drm_dp_tps3_supported(intel_dp->dpcd)));
4307 intel_dp_print_rates(intel_dp);
4309 intel_dp_probe_oui(intel_dp);
4311 intel_dp_configure_mst(intel_dp);
4313 if (intel_dp->is_mst) {
4315 * If we are in MST mode then this connector
4316 * won't appear connected or have anything
4319 status = connector_status_disconnected;
4321 } else if (connector->status == connector_status_connected) {
4323 * If display was connected already and is still connected
4324 * check links status, there has been known issues of
4325 * link loss triggerring long pulse!!!!
4327 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4328 intel_dp_check_link_status(intel_dp);
4329 drm_modeset_unlock(&dev->mode_config.connection_mutex);
4334 * Clearing NACK and defer counts to get their exact values
4335 * while reading EDID which are required by Compliance tests
4336 * 4.2.2.4 and 4.2.2.5
4338 intel_dp->aux.i2c_nack_count = 0;
4339 intel_dp->aux.i2c_defer_count = 0;
4341 intel_dp_set_edid(intel_dp);
4343 status = connector_status_connected;
4344 intel_dp->detect_done = true;
4346 /* Try to read the source of the interrupt */
4347 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4348 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) &&
4349 sink_irq_vector != 0) {
4350 /* Clear interrupt source */
4351 drm_dp_dpcd_writeb(&intel_dp->aux,
4352 DP_DEVICE_SERVICE_IRQ_VECTOR,
4355 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4356 intel_dp_handle_test_request(intel_dp);
4357 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4358 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4362 if ((status != connector_status_connected) &&
4363 (intel_dp->is_mst == false))
4364 intel_dp_unset_edid(intel_dp);
4366 intel_display_power_put(to_i915(dev), power_domain);
4370 static enum drm_connector_status
4371 intel_dp_detect(struct drm_connector *connector, bool force)
4373 struct intel_dp *intel_dp = intel_attached_dp(connector);
4374 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4375 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4376 struct intel_connector *intel_connector = to_intel_connector(connector);
4378 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4379 connector->base.id, connector->name);
4381 if (intel_dp->is_mst) {
4382 /* MST devices are disconnected from a monitor POV */
4383 intel_dp_unset_edid(intel_dp);
4384 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4385 intel_encoder->type = INTEL_OUTPUT_DP;
4386 return connector_status_disconnected;
4389 /* If full detect is not performed yet, do a full detect */
4390 if (!intel_dp->detect_done)
4391 intel_dp_long_pulse(intel_dp->attached_connector);
4393 intel_dp->detect_done = false;
4395 if (is_edp(intel_dp) || intel_connector->detect_edid)
4396 return connector_status_connected;
4398 return connector_status_disconnected;
4402 intel_dp_force(struct drm_connector *connector)
4404 struct intel_dp *intel_dp = intel_attached_dp(connector);
4405 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4406 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
4407 enum intel_display_power_domain power_domain;
4409 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4410 connector->base.id, connector->name);
4411 intel_dp_unset_edid(intel_dp);
4413 if (connector->status != connector_status_connected)
4416 power_domain = intel_display_port_aux_power_domain(intel_encoder);
4417 intel_display_power_get(dev_priv, power_domain);
4419 intel_dp_set_edid(intel_dp);
4421 intel_display_power_put(dev_priv, power_domain);
4423 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4424 intel_encoder->type = INTEL_OUTPUT_DP;
4427 static int intel_dp_get_modes(struct drm_connector *connector)
4429 struct intel_connector *intel_connector = to_intel_connector(connector);
4432 edid = intel_connector->detect_edid;
4434 int ret = intel_connector_update_modes(connector, edid);
4439 /* if eDP has no EDID, fall back to fixed mode */
4440 if (is_edp(intel_attached_dp(connector)) &&
4441 intel_connector->panel.fixed_mode) {
4442 struct drm_display_mode *mode;
4444 mode = drm_mode_duplicate(connector->dev,
4445 intel_connector->panel.fixed_mode);
4447 drm_mode_probed_add(connector, mode);
4456 intel_dp_detect_audio(struct drm_connector *connector)
4458 bool has_audio = false;
4461 edid = to_intel_connector(connector)->detect_edid;
4463 has_audio = drm_detect_monitor_audio(edid);
4469 intel_dp_set_property(struct drm_connector *connector,
4470 struct drm_property *property,
4473 struct drm_i915_private *dev_priv = to_i915(connector->dev);
4474 struct intel_connector *intel_connector = to_intel_connector(connector);
4475 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
4476 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4479 ret = drm_object_property_set_value(&connector->base, property, val);
4483 if (property == dev_priv->force_audio_property) {
4487 if (i == intel_dp->force_audio)
4490 intel_dp->force_audio = i;
4492 if (i == HDMI_AUDIO_AUTO)
4493 has_audio = intel_dp_detect_audio(connector);
4495 has_audio = (i == HDMI_AUDIO_ON);
4497 if (has_audio == intel_dp->has_audio)
4500 intel_dp->has_audio = has_audio;
4504 if (property == dev_priv->broadcast_rgb_property) {
4505 bool old_auto = intel_dp->color_range_auto;
4506 bool old_range = intel_dp->limited_color_range;
4509 case INTEL_BROADCAST_RGB_AUTO:
4510 intel_dp->color_range_auto = true;
4512 case INTEL_BROADCAST_RGB_FULL:
4513 intel_dp->color_range_auto = false;
4514 intel_dp->limited_color_range = false;
4516 case INTEL_BROADCAST_RGB_LIMITED:
4517 intel_dp->color_range_auto = false;
4518 intel_dp->limited_color_range = true;
4524 if (old_auto == intel_dp->color_range_auto &&
4525 old_range == intel_dp->limited_color_range)
4531 if (is_edp(intel_dp) &&
4532 property == connector->dev->mode_config.scaling_mode_property) {
4533 if (val == DRM_MODE_SCALE_NONE) {
4534 DRM_DEBUG_KMS("no scaling not supported\n");
4537 if (HAS_GMCH_DISPLAY(dev_priv) &&
4538 val == DRM_MODE_SCALE_CENTER) {
4539 DRM_DEBUG_KMS("centering not supported\n");
4543 if (intel_connector->panel.fitting_mode == val) {
4544 /* the eDP scaling property is not changed */
4547 intel_connector->panel.fitting_mode = val;
4555 if (intel_encoder->base.crtc)
4556 intel_crtc_restore_mode(intel_encoder->base.crtc);
4562 intel_dp_connector_register(struct drm_connector *connector)
4564 struct intel_dp *intel_dp = intel_attached_dp(connector);
4567 ret = intel_connector_register(connector);
4571 i915_debugfs_connector_add(connector);
4573 DRM_DEBUG_KMS("registering %s bus for %s\n",
4574 intel_dp->aux.name, connector->kdev->kobj.name);
4576 intel_dp->aux.dev = connector->kdev;
4577 return drm_dp_aux_register(&intel_dp->aux);
4581 intel_dp_connector_unregister(struct drm_connector *connector)
4583 drm_dp_aux_unregister(&intel_attached_dp(connector)->aux);
4584 intel_connector_unregister(connector);
4588 intel_dp_connector_destroy(struct drm_connector *connector)
4590 struct intel_connector *intel_connector = to_intel_connector(connector);
4592 kfree(intel_connector->detect_edid);
4594 if (!IS_ERR_OR_NULL(intel_connector->edid))
4595 kfree(intel_connector->edid);
4597 /* Can't call is_edp() since the encoder may have been destroyed
4599 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4600 intel_panel_fini(&intel_connector->panel);
4602 drm_connector_cleanup(connector);
4606 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
4608 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4609 struct intel_dp *intel_dp = &intel_dig_port->dp;
4611 intel_dp_mst_encoder_cleanup(intel_dig_port);
4612 if (is_edp(intel_dp)) {
4613 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4615 * vdd might still be enabled do to the delayed vdd off.
4616 * Make sure vdd is actually turned off here.
4619 edp_panel_vdd_off_sync(intel_dp);
4620 pps_unlock(intel_dp);
4622 if (intel_dp->edp_notifier.notifier_call) {
4623 unregister_reboot_notifier(&intel_dp->edp_notifier);
4624 intel_dp->edp_notifier.notifier_call = NULL;
4628 intel_dp_aux_fini(intel_dp);
4630 drm_encoder_cleanup(encoder);
4631 kfree(intel_dig_port);
4634 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4636 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4638 if (!is_edp(intel_dp))
4642 * vdd might still be enabled do to the delayed vdd off.
4643 * Make sure vdd is actually turned off here.
4645 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4647 edp_panel_vdd_off_sync(intel_dp);
4648 pps_unlock(intel_dp);
4651 static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
4653 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4654 struct drm_device *dev = intel_dig_port->base.base.dev;
4655 struct drm_i915_private *dev_priv = to_i915(dev);
4656 enum intel_display_power_domain power_domain;
4658 lockdep_assert_held(&dev_priv->pps_mutex);
4660 if (!edp_have_panel_vdd(intel_dp))
4664 * The VDD bit needs a power domain reference, so if the bit is
4665 * already enabled when we boot or resume, grab this reference and
4666 * schedule a vdd off, so we don't hold on to the reference
4669 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4670 power_domain = intel_display_port_aux_power_domain(&intel_dig_port->base);
4671 intel_display_power_get(dev_priv, power_domain);
4673 edp_panel_vdd_schedule_off(intel_dp);
4676 void intel_dp_encoder_reset(struct drm_encoder *encoder)
4678 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
4679 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4681 if (!HAS_DDI(dev_priv))
4682 intel_dp->DP = I915_READ(intel_dp->output_reg);
4684 if (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP)
4689 /* Reinit the power sequencer, in case BIOS did something with it. */
4690 intel_dp_pps_init(encoder->dev, intel_dp);
4691 intel_edp_panel_vdd_sanitize(intel_dp);
4693 pps_unlock(intel_dp);
4696 static const struct drm_connector_funcs intel_dp_connector_funcs = {
4697 .dpms = drm_atomic_helper_connector_dpms,
4698 .detect = intel_dp_detect,
4699 .force = intel_dp_force,
4700 .fill_modes = drm_helper_probe_single_connector_modes,
4701 .set_property = intel_dp_set_property,
4702 .atomic_get_property = intel_connector_atomic_get_property,
4703 .late_register = intel_dp_connector_register,
4704 .early_unregister = intel_dp_connector_unregister,
4705 .destroy = intel_dp_connector_destroy,
4706 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
4707 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
4710 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4711 .get_modes = intel_dp_get_modes,
4712 .mode_valid = intel_dp_mode_valid,
4715 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
4716 .reset = intel_dp_encoder_reset,
4717 .destroy = intel_dp_encoder_destroy,
4721 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4723 struct intel_dp *intel_dp = &intel_dig_port->dp;
4724 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4725 struct drm_device *dev = intel_dig_port->base.base.dev;
4726 struct drm_i915_private *dev_priv = to_i915(dev);
4727 enum intel_display_power_domain power_domain;
4728 enum irqreturn ret = IRQ_NONE;
4730 if (intel_dig_port->base.type != INTEL_OUTPUT_EDP &&
4731 intel_dig_port->base.type != INTEL_OUTPUT_HDMI)
4732 intel_dig_port->base.type = INTEL_OUTPUT_DP;
4734 if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
4736 * vdd off can generate a long pulse on eDP which
4737 * would require vdd on to handle it, and thus we
4738 * would end up in an endless cycle of
4739 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
4741 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
4742 port_name(intel_dig_port->port));
4746 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4747 port_name(intel_dig_port->port),
4748 long_hpd ? "long" : "short");
4750 power_domain = intel_display_port_aux_power_domain(intel_encoder);
4751 intel_display_power_get(dev_priv, power_domain);
4754 intel_dp_long_pulse(intel_dp->attached_connector);
4755 if (intel_dp->is_mst)
4760 if (intel_dp->is_mst) {
4761 if (intel_dp_check_mst_status(intel_dp) == -EINVAL) {
4763 * If we were in MST mode, and device is not
4764 * there, get out of MST mode
4766 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4767 intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4768 intel_dp->is_mst = false;
4769 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4775 if (!intel_dp->is_mst) {
4776 if (!intel_dp_short_pulse(intel_dp)) {
4777 intel_dp_long_pulse(intel_dp->attached_connector);
4786 intel_display_power_put(dev_priv, power_domain);
4791 /* check the VBT to see whether the eDP is on another port */
4792 bool intel_dp_is_edp(struct drm_device *dev, enum port port)
4794 struct drm_i915_private *dev_priv = to_i915(dev);
4797 * eDP not supported on g4x. so bail out early just
4798 * for a bit extra safety in case the VBT is bonkers.
4800 if (INTEL_INFO(dev)->gen < 5)
4806 return intel_bios_is_port_edp(dev_priv, port);
4810 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
4812 struct intel_connector *intel_connector = to_intel_connector(connector);
4814 intel_attach_force_audio_property(connector);
4815 intel_attach_broadcast_rgb_property(connector);
4816 intel_dp->color_range_auto = true;
4818 if (is_edp(intel_dp)) {
4819 drm_mode_create_scaling_mode_property(connector->dev);
4820 drm_object_attach_property(
4822 connector->dev->mode_config.scaling_mode_property,
4823 DRM_MODE_SCALE_ASPECT);
4824 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
4828 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
4830 intel_dp->panel_power_off_time = ktime_get_boottime();
4831 intel_dp->last_power_on = jiffies;
4832 intel_dp->last_backlight_off = jiffies;
4836 intel_pps_readout_hw_state(struct drm_i915_private *dev_priv,
4837 struct intel_dp *intel_dp, struct edp_power_seq *seq)
4839 u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0;
4840 struct pps_registers regs;
4842 intel_pps_get_registers(dev_priv, intel_dp, ®s);
4844 /* Workaround: Need to write PP_CONTROL with the unlock key as
4845 * the very first thing. */
4846 pp_ctl = ironlake_get_pp_control(intel_dp);
4848 pp_on = I915_READ(regs.pp_on);
4849 pp_off = I915_READ(regs.pp_off);
4850 if (!IS_BROXTON(dev_priv)) {
4851 I915_WRITE(regs.pp_ctrl, pp_ctl);
4852 pp_div = I915_READ(regs.pp_div);
4855 /* Pull timing values out of registers */
4856 seq->t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
4857 PANEL_POWER_UP_DELAY_SHIFT;
4859 seq->t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
4860 PANEL_LIGHT_ON_DELAY_SHIFT;
4862 seq->t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
4863 PANEL_LIGHT_OFF_DELAY_SHIFT;
4865 seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
4866 PANEL_POWER_DOWN_DELAY_SHIFT;
4868 if (IS_BROXTON(dev_priv)) {
4869 u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
4870 BXT_POWER_CYCLE_DELAY_SHIFT;
4872 seq->t11_t12 = (tmp - 1) * 1000;
4876 seq->t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
4877 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
4882 intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq)
4884 DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4886 seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12);
4890 intel_pps_verify_state(struct drm_i915_private *dev_priv,
4891 struct intel_dp *intel_dp)
4893 struct edp_power_seq hw;
4894 struct edp_power_seq *sw = &intel_dp->pps_delays;
4896 intel_pps_readout_hw_state(dev_priv, intel_dp, &hw);
4898 if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 ||
4899 hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) {
4900 DRM_ERROR("PPS state mismatch\n");
4901 intel_pps_dump_state("sw", sw);
4902 intel_pps_dump_state("hw", &hw);
4907 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
4908 struct intel_dp *intel_dp)
4910 struct drm_i915_private *dev_priv = to_i915(dev);
4911 struct edp_power_seq cur, vbt, spec,
4912 *final = &intel_dp->pps_delays;
4914 lockdep_assert_held(&dev_priv->pps_mutex);
4916 /* already initialized? */
4917 if (final->t11_t12 != 0)
4920 intel_pps_readout_hw_state(dev_priv, intel_dp, &cur);
4922 intel_pps_dump_state("cur", &cur);
4924 vbt = dev_priv->vbt.edp.pps;
4926 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
4927 * our hw here, which are all in 100usec. */
4928 spec.t1_t3 = 210 * 10;
4929 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
4930 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
4931 spec.t10 = 500 * 10;
4932 /* This one is special and actually in units of 100ms, but zero
4933 * based in the hw (so we need to add 100 ms). But the sw vbt
4934 * table multiplies it with 1000 to make it in units of 100usec,
4936 spec.t11_t12 = (510 + 100) * 10;
4938 intel_pps_dump_state("vbt", &vbt);
4940 /* Use the max of the register settings and vbt. If both are
4941 * unset, fall back to the spec limits. */
4942 #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
4944 max(cur.field, vbt.field))
4945 assign_final(t1_t3);
4949 assign_final(t11_t12);
4952 #define get_delay(field) (DIV_ROUND_UP(final->field, 10))
4953 intel_dp->panel_power_up_delay = get_delay(t1_t3);
4954 intel_dp->backlight_on_delay = get_delay(t8);
4955 intel_dp->backlight_off_delay = get_delay(t9);
4956 intel_dp->panel_power_down_delay = get_delay(t10);
4957 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
4960 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4961 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
4962 intel_dp->panel_power_cycle_delay);
4964 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4965 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
4968 * We override the HW backlight delays to 1 because we do manual waits
4969 * on them. For T8, even BSpec recommends doing it. For T9, if we
4970 * don't do this, we'll end up waiting for the backlight off delay
4971 * twice: once when we do the manual sleep, and once when we disable
4972 * the panel and wait for the PP_STATUS bit to become zero.
4979 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
4980 struct intel_dp *intel_dp)
4982 struct drm_i915_private *dev_priv = to_i915(dev);
4983 u32 pp_on, pp_off, pp_div, port_sel = 0;
4984 int div = dev_priv->rawclk_freq / 1000;
4985 struct pps_registers regs;
4986 enum port port = dp_to_dig_port(intel_dp)->port;
4987 const struct edp_power_seq *seq = &intel_dp->pps_delays;
4989 lockdep_assert_held(&dev_priv->pps_mutex);
4991 intel_pps_get_registers(dev_priv, intel_dp, ®s);
4993 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
4994 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
4995 pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
4996 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
4997 /* Compute the divisor for the pp clock, simply match the Bspec
4999 if (IS_BROXTON(dev)) {
5000 pp_div = I915_READ(regs.pp_ctrl);
5001 pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
5002 pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000)
5003 << BXT_POWER_CYCLE_DELAY_SHIFT);
5005 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
5006 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
5007 << PANEL_POWER_CYCLE_DELAY_SHIFT);
5010 /* Haswell doesn't have any port selection bits for the panel
5011 * power sequencer any more. */
5012 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
5013 port_sel = PANEL_PORT_SELECT_VLV(port);
5014 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5016 port_sel = PANEL_PORT_SELECT_DPA;
5018 port_sel = PANEL_PORT_SELECT_DPD;
5023 I915_WRITE(regs.pp_on, pp_on);
5024 I915_WRITE(regs.pp_off, pp_off);
5025 if (IS_BROXTON(dev))
5026 I915_WRITE(regs.pp_ctrl, pp_div);
5028 I915_WRITE(regs.pp_div, pp_div);
5030 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
5031 I915_READ(regs.pp_on),
5032 I915_READ(regs.pp_off),
5034 (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) :
5035 I915_READ(regs.pp_div));
5038 static void intel_dp_pps_init(struct drm_device *dev,
5039 struct intel_dp *intel_dp)
5041 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
5042 vlv_initial_power_sequencer_setup(intel_dp);
5044 intel_dp_init_panel_power_sequencer(dev, intel_dp);
5045 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
5050 * intel_dp_set_drrs_state - program registers for RR switch to take effect
5052 * @crtc_state: a pointer to the active intel_crtc_state
5053 * @refresh_rate: RR to be programmed
5055 * This function gets called when refresh rate (RR) has to be changed from
5056 * one frequency to another. Switches can be between high and low RR
5057 * supported by the panel or to any other RR based on media playback (in
5058 * this case, RR value needs to be passed from user space).
5060 * The caller of this function needs to take a lock on dev_priv->drrs.
5062 static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
5063 struct intel_crtc_state *crtc_state,
5066 struct intel_encoder *encoder;
5067 struct intel_digital_port *dig_port = NULL;
5068 struct intel_dp *intel_dp = dev_priv->drrs.dp;
5069 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
5070 enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
5072 if (refresh_rate <= 0) {
5073 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
5077 if (intel_dp == NULL) {
5078 DRM_DEBUG_KMS("DRRS not supported.\n");
5083 * FIXME: This needs proper synchronization with psr state for some
5084 * platforms that cannot have PSR and DRRS enabled at the same time.
5087 dig_port = dp_to_dig_port(intel_dp);
5088 encoder = &dig_port->base;
5089 intel_crtc = to_intel_crtc(encoder->base.crtc);
5092 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5096 if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
5097 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5101 if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
5103 index = DRRS_LOW_RR;
5105 if (index == dev_priv->drrs.refresh_rate_type) {
5107 "DRRS requested for previously set RR...ignoring\n");
5111 if (!crtc_state->base.active) {
5112 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5116 if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
5119 intel_dp_set_m_n(intel_crtc, M1_N1);
5122 intel_dp_set_m_n(intel_crtc, M2_N2);
5126 DRM_ERROR("Unsupported refreshrate type\n");
5128 } else if (INTEL_GEN(dev_priv) > 6) {
5129 i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);
5132 val = I915_READ(reg);
5133 if (index > DRRS_HIGH_RR) {
5134 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5135 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5137 val |= PIPECONF_EDP_RR_MODE_SWITCH;
5139 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5140 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5142 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
5144 I915_WRITE(reg, val);
5147 dev_priv->drrs.refresh_rate_type = index;
5149 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
5153 * intel_edp_drrs_enable - init drrs struct if supported
5154 * @intel_dp: DP struct
5156 * Initializes frontbuffer_bits and drrs.dp
5158 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
5159 struct intel_crtc_state *crtc_state)
5161 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5162 struct drm_i915_private *dev_priv = to_i915(dev);
5164 if (!crtc_state->has_drrs) {
5165 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
5169 mutex_lock(&dev_priv->drrs.mutex);
5170 if (WARN_ON(dev_priv->drrs.dp)) {
5171 DRM_ERROR("DRRS already enabled\n");
5175 dev_priv->drrs.busy_frontbuffer_bits = 0;
5177 dev_priv->drrs.dp = intel_dp;
5180 mutex_unlock(&dev_priv->drrs.mutex);
5184 * intel_edp_drrs_disable - Disable DRRS
5185 * @intel_dp: DP struct
5188 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
5189 struct intel_crtc_state *old_crtc_state)
5191 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5192 struct drm_i915_private *dev_priv = to_i915(dev);
5194 if (!old_crtc_state->has_drrs)
5197 mutex_lock(&dev_priv->drrs.mutex);
5198 if (!dev_priv->drrs.dp) {
5199 mutex_unlock(&dev_priv->drrs.mutex);
5203 if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5204 intel_dp_set_drrs_state(dev_priv, old_crtc_state,
5205 intel_dp->attached_connector->panel.fixed_mode->vrefresh);
5207 dev_priv->drrs.dp = NULL;
5208 mutex_unlock(&dev_priv->drrs.mutex);
5210 cancel_delayed_work_sync(&dev_priv->drrs.work);
5213 static void intel_edp_drrs_downclock_work(struct work_struct *work)
5215 struct drm_i915_private *dev_priv =
5216 container_of(work, typeof(*dev_priv), drrs.work.work);
5217 struct intel_dp *intel_dp;
5219 mutex_lock(&dev_priv->drrs.mutex);
5221 intel_dp = dev_priv->drrs.dp;
5227 * The delayed work can race with an invalidate hence we need to
5231 if (dev_priv->drrs.busy_frontbuffer_bits)
5234 if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) {
5235 struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
5237 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5238 intel_dp->attached_connector->panel.downclock_mode->vrefresh);
5242 mutex_unlock(&dev_priv->drrs.mutex);
5246 * intel_edp_drrs_invalidate - Disable Idleness DRRS
5247 * @dev_priv: i915 device
5248 * @frontbuffer_bits: frontbuffer plane tracking bits
5250 * This function gets called everytime rendering on the given planes start.
5251 * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
5253 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5255 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
5256 unsigned int frontbuffer_bits)
5258 struct drm_crtc *crtc;
5261 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5264 cancel_delayed_work(&dev_priv->drrs.work);
5266 mutex_lock(&dev_priv->drrs.mutex);
5267 if (!dev_priv->drrs.dp) {
5268 mutex_unlock(&dev_priv->drrs.mutex);
5272 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5273 pipe = to_intel_crtc(crtc)->pipe;
5275 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5276 dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
5278 /* invalidate means busy screen hence upclock */
5279 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5280 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5281 dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
5283 mutex_unlock(&dev_priv->drrs.mutex);
5287 * intel_edp_drrs_flush - Restart Idleness DRRS
5288 * @dev_priv: i915 device
5289 * @frontbuffer_bits: frontbuffer plane tracking bits
5291 * This function gets called every time rendering on the given planes has
5292 * completed or flip on a crtc is completed. So DRRS should be upclocked
5293 * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
5294 * if no other planes are dirty.
5296 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5298 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
5299 unsigned int frontbuffer_bits)
5301 struct drm_crtc *crtc;
5304 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5307 cancel_delayed_work(&dev_priv->drrs.work);
5309 mutex_lock(&dev_priv->drrs.mutex);
5310 if (!dev_priv->drrs.dp) {
5311 mutex_unlock(&dev_priv->drrs.mutex);
5315 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5316 pipe = to_intel_crtc(crtc)->pipe;
5318 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5319 dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
5321 /* flush means busy screen hence upclock */
5322 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5323 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5324 dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
5327 * flush also means no more activity hence schedule downclock, if all
5328 * other fbs are quiescent too
5330 if (!dev_priv->drrs.busy_frontbuffer_bits)
5331 schedule_delayed_work(&dev_priv->drrs.work,
5332 msecs_to_jiffies(1000));
5333 mutex_unlock(&dev_priv->drrs.mutex);
5337 * DOC: Display Refresh Rate Switching (DRRS)
5339 * Display Refresh Rate Switching (DRRS) is a power conservation feature
5340 * which enables swtching between low and high refresh rates,
5341 * dynamically, based on the usage scenario. This feature is applicable
5342 * for internal panels.
5344 * Indication that the panel supports DRRS is given by the panel EDID, which
5345 * would list multiple refresh rates for one resolution.
5347 * DRRS is of 2 types - static and seamless.
5348 * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5349 * (may appear as a blink on screen) and is used in dock-undock scenario.
5350 * Seamless DRRS involves changing RR without any visual effect to the user
5351 * and can be used during normal system usage. This is done by programming
5352 * certain registers.
5354 * Support for static/seamless DRRS may be indicated in the VBT based on
5355 * inputs from the panel spec.
5357 * DRRS saves power by switching to low RR based on usage scenarios.
5359 * The implementation is based on frontbuffer tracking implementation. When
5360 * there is a disturbance on the screen triggered by user activity or a periodic
5361 * system activity, DRRS is disabled (RR is changed to high RR). When there is
5362 * no movement on screen, after a timeout of 1 second, a switch to low RR is
5365 * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
5366 * and intel_edp_drrs_flush() are called.
5368 * DRRS can be further extended to support other internal panels and also
5369 * the scenario of video playback wherein RR is set based on the rate
5370 * requested by userspace.
5374 * intel_dp_drrs_init - Init basic DRRS work and mutex.
5375 * @intel_connector: eDP connector
5376 * @fixed_mode: preferred mode of panel
5378 * This function is called only once at driver load to initialize basic
5382 * Downclock mode if panel supports it, else return NULL.
5383 * DRRS support is determined by the presence of downclock mode (apart
5384 * from VBT setting).
5386 static struct drm_display_mode *
5387 intel_dp_drrs_init(struct intel_connector *intel_connector,
5388 struct drm_display_mode *fixed_mode)
5390 struct drm_connector *connector = &intel_connector->base;
5391 struct drm_device *dev = connector->dev;
5392 struct drm_i915_private *dev_priv = to_i915(dev);
5393 struct drm_display_mode *downclock_mode = NULL;
5395 INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
5396 mutex_init(&dev_priv->drrs.mutex);
5398 if (INTEL_INFO(dev)->gen <= 6) {
5399 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5403 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
5404 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
5408 downclock_mode = intel_find_panel_downclock
5409 (dev, fixed_mode, connector);
5411 if (!downclock_mode) {
5412 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
5416 dev_priv->drrs.type = dev_priv->vbt.drrs_type;
5418 dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
5419 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
5420 return downclock_mode;
5423 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
5424 struct intel_connector *intel_connector)
5426 struct drm_connector *connector = &intel_connector->base;
5427 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5428 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5429 struct drm_device *dev = intel_encoder->base.dev;
5430 struct drm_i915_private *dev_priv = to_i915(dev);
5431 struct drm_display_mode *fixed_mode = NULL;
5432 struct drm_display_mode *downclock_mode = NULL;
5434 struct drm_display_mode *scan;
5436 enum pipe pipe = INVALID_PIPE;
5438 if (!is_edp(intel_dp))
5442 * On IBX/CPT we may get here with LVDS already registered. Since the
5443 * driver uses the only internal power sequencer available for both
5444 * eDP and LVDS bail out early in this case to prevent interfering
5445 * with an already powered-on LVDS power sequencer.
5447 if (intel_get_lvds_encoder(dev)) {
5448 WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
5449 DRM_INFO("LVDS was detected, not registering eDP\n");
5456 intel_dp_init_panel_power_timestamps(intel_dp);
5457 intel_dp_pps_init(dev, intel_dp);
5458 intel_edp_panel_vdd_sanitize(intel_dp);
5460 pps_unlock(intel_dp);
5462 /* Cache DPCD and EDID for edp. */
5463 has_dpcd = intel_edp_init_dpcd(intel_dp);
5466 /* if this fails, presume the device is a ghost */
5467 DRM_INFO("failed to retrieve link info, disabling eDP\n");
5471 mutex_lock(&dev->mode_config.mutex);
5472 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
5474 if (drm_add_edid_modes(connector, edid)) {
5475 drm_mode_connector_update_edid_property(connector,
5477 drm_edid_to_eld(connector, edid);
5480 edid = ERR_PTR(-EINVAL);
5483 edid = ERR_PTR(-ENOENT);
5485 intel_connector->edid = edid;
5487 /* prefer fixed mode from EDID if available */
5488 list_for_each_entry(scan, &connector->probed_modes, head) {
5489 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
5490 fixed_mode = drm_mode_duplicate(dev, scan);
5491 downclock_mode = intel_dp_drrs_init(
5492 intel_connector, fixed_mode);
5497 /* fallback to VBT if available for eDP */
5498 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
5499 fixed_mode = drm_mode_duplicate(dev,
5500 dev_priv->vbt.lfp_lvds_vbt_mode);
5502 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
5503 connector->display_info.width_mm = fixed_mode->width_mm;
5504 connector->display_info.height_mm = fixed_mode->height_mm;
5507 mutex_unlock(&dev->mode_config.mutex);
5509 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
5510 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
5511 register_reboot_notifier(&intel_dp->edp_notifier);
5514 * Figure out the current pipe for the initial backlight setup.
5515 * If the current pipe isn't valid, try the PPS pipe, and if that
5516 * fails just assume pipe A.
5518 if (IS_CHERRYVIEW(dev))
5519 pipe = DP_PORT_TO_PIPE_CHV(intel_dp->DP);
5521 pipe = PORT_TO_PIPE(intel_dp->DP);
5523 if (pipe != PIPE_A && pipe != PIPE_B)
5524 pipe = intel_dp->pps_pipe;
5526 if (pipe != PIPE_A && pipe != PIPE_B)
5529 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
5533 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
5534 intel_connector->panel.backlight.power = intel_edp_backlight_power;
5535 intel_panel_setup_backlight(connector, pipe);
5540 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5542 * vdd might still be enabled do to the delayed vdd off.
5543 * Make sure vdd is actually turned off here.
5546 edp_panel_vdd_off_sync(intel_dp);
5547 pps_unlock(intel_dp);
5553 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
5554 struct intel_connector *intel_connector)
5556 struct drm_connector *connector = &intel_connector->base;
5557 struct intel_dp *intel_dp = &intel_dig_port->dp;
5558 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5559 struct drm_device *dev = intel_encoder->base.dev;
5560 struct drm_i915_private *dev_priv = to_i915(dev);
5561 enum port port = intel_dig_port->port;
5564 if (WARN(intel_dig_port->max_lanes < 1,
5565 "Not enough lanes (%d) for DP on port %c\n",
5566 intel_dig_port->max_lanes, port_name(port)))
5569 intel_dp->pps_pipe = INVALID_PIPE;
5571 /* intel_dp vfuncs */
5572 if (INTEL_INFO(dev)->gen >= 9)
5573 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
5574 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
5575 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
5576 else if (HAS_PCH_SPLIT(dev))
5577 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
5579 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
5581 if (INTEL_INFO(dev)->gen >= 9)
5582 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
5584 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
5587 intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain;
5589 /* Preserve the current hw state. */
5590 intel_dp->DP = I915_READ(intel_dp->output_reg);
5591 intel_dp->attached_connector = intel_connector;
5593 if (intel_dp_is_edp(dev, port))
5594 type = DRM_MODE_CONNECTOR_eDP;
5596 type = DRM_MODE_CONNECTOR_DisplayPort;
5599 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5600 * for DP the encoder type can be set by the caller to
5601 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5603 if (type == DRM_MODE_CONNECTOR_eDP)
5604 intel_encoder->type = INTEL_OUTPUT_EDP;
5606 /* eDP only on port B and/or C on vlv/chv */
5607 if (WARN_ON((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
5608 is_edp(intel_dp) && port != PORT_B && port != PORT_C))
5611 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5612 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5615 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
5616 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5618 connector->interlace_allowed = true;
5619 connector->doublescan_allowed = 0;
5621 intel_dp_aux_init(intel_dp, intel_connector);
5623 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
5624 edp_panel_vdd_work);
5626 intel_connector_attach_encoder(intel_connector, intel_encoder);
5629 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5631 intel_connector->get_hw_state = intel_connector_get_hw_state;
5633 /* Set up the hotplug pin. */
5636 intel_encoder->hpd_pin = HPD_PORT_A;
5639 intel_encoder->hpd_pin = HPD_PORT_B;
5640 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
5641 intel_encoder->hpd_pin = HPD_PORT_A;
5644 intel_encoder->hpd_pin = HPD_PORT_C;
5647 intel_encoder->hpd_pin = HPD_PORT_D;
5650 intel_encoder->hpd_pin = HPD_PORT_E;
5656 /* init MST on ports that can support it */
5657 if (HAS_DP_MST(dev) && !is_edp(intel_dp) &&
5658 (port == PORT_B || port == PORT_C || port == PORT_D))
5659 intel_dp_mst_encoder_init(intel_dig_port,
5660 intel_connector->base.base.id);
5662 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
5663 intel_dp_aux_fini(intel_dp);
5664 intel_dp_mst_encoder_cleanup(intel_dig_port);
5668 intel_dp_add_properties(intel_dp, connector);
5670 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5671 * 0xd. Failure to do so will result in spurious interrupts being
5672 * generated on the port when a cable is not attached.
5674 if (IS_G4X(dev) && !IS_GM45(dev)) {
5675 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
5676 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
5682 drm_connector_cleanup(connector);
5687 bool intel_dp_init(struct drm_device *dev,
5688 i915_reg_t output_reg,
5691 struct drm_i915_private *dev_priv = to_i915(dev);
5692 struct intel_digital_port *intel_dig_port;
5693 struct intel_encoder *intel_encoder;
5694 struct drm_encoder *encoder;
5695 struct intel_connector *intel_connector;
5697 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
5698 if (!intel_dig_port)
5701 intel_connector = intel_connector_alloc();
5702 if (!intel_connector)
5703 goto err_connector_alloc;
5705 intel_encoder = &intel_dig_port->base;
5706 encoder = &intel_encoder->base;
5708 if (drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
5709 DRM_MODE_ENCODER_TMDS, "DP %c", port_name(port)))
5710 goto err_encoder_init;
5712 intel_encoder->compute_config = intel_dp_compute_config;
5713 intel_encoder->disable = intel_disable_dp;
5714 intel_encoder->get_hw_state = intel_dp_get_hw_state;
5715 intel_encoder->get_config = intel_dp_get_config;
5716 intel_encoder->suspend = intel_dp_encoder_suspend;
5717 if (IS_CHERRYVIEW(dev)) {
5718 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
5719 intel_encoder->pre_enable = chv_pre_enable_dp;
5720 intel_encoder->enable = vlv_enable_dp;
5721 intel_encoder->post_disable = chv_post_disable_dp;
5722 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
5723 } else if (IS_VALLEYVIEW(dev)) {
5724 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
5725 intel_encoder->pre_enable = vlv_pre_enable_dp;
5726 intel_encoder->enable = vlv_enable_dp;
5727 intel_encoder->post_disable = vlv_post_disable_dp;
5729 intel_encoder->pre_enable = g4x_pre_enable_dp;
5730 intel_encoder->enable = g4x_enable_dp;
5731 if (INTEL_INFO(dev)->gen >= 5)
5732 intel_encoder->post_disable = ilk_post_disable_dp;
5735 intel_dig_port->port = port;
5736 intel_dig_port->dp.output_reg = output_reg;
5737 intel_dig_port->max_lanes = 4;
5739 intel_encoder->type = INTEL_OUTPUT_DP;
5740 if (IS_CHERRYVIEW(dev)) {
5742 intel_encoder->crtc_mask = 1 << 2;
5744 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
5746 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
5748 intel_encoder->cloneable = 0;
5750 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
5751 dev_priv->hotplug.irq_port[port] = intel_dig_port;
5753 if (!intel_dp_init_connector(intel_dig_port, intel_connector))
5754 goto err_init_connector;
5759 drm_encoder_cleanup(encoder);
5761 kfree(intel_connector);
5762 err_connector_alloc:
5763 kfree(intel_dig_port);
5767 void intel_dp_mst_suspend(struct drm_device *dev)
5769 struct drm_i915_private *dev_priv = to_i915(dev);
5773 for (i = 0; i < I915_MAX_PORTS; i++) {
5774 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
5776 if (!intel_dig_port || !intel_dig_port->dp.can_mst)
5779 if (intel_dig_port->dp.is_mst)
5780 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
5784 void intel_dp_mst_resume(struct drm_device *dev)
5786 struct drm_i915_private *dev_priv = to_i915(dev);
5789 for (i = 0; i < I915_MAX_PORTS; i++) {
5790 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
5793 if (!intel_dig_port || !intel_dig_port->dp.can_mst)
5796 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
5798 intel_dp_check_mst_status(&intel_dig_port->dp);