2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #ifndef __INTEL_DRV_H__
26 #define __INTEL_DRV_H__
28 #include <linux/async.h>
29 #include <linux/i2c.h>
30 #include <linux/hdmi.h>
31 #include <drm/i915_drm.h>
33 #include <drm/drm_crtc.h>
34 #include <drm/drm_crtc_helper.h>
35 #include <drm/drm_fb_helper.h>
36 #include <drm/drm_dp_mst_helper.h>
37 #include <drm/drm_rect.h>
38 #include <drm/drm_atomic.h>
41 * _wait_for - magic (register) wait macro
43 * Does the right thing for modeset paths when run under kdgb or similar atomic
44 * contexts. Note that it's important that we check the condition again after
45 * having timed out, since the timeout could be due to preemption or similar and
46 * we've never had a chance to check the condition before the timeout.
48 * TODO: When modesetting has fully transitioned to atomic, the below
49 * drm_can_sleep() can be removed and in_atomic()/!in_atomic() asserts
52 #define _wait_for(COND, US, W) ({ \
53 unsigned long timeout__ = jiffies + usecs_to_jiffies(US) + 1; \
56 if (time_after(jiffies, timeout__)) { \
61 if ((W) && drm_can_sleep()) { \
62 usleep_range((W), (W)*2); \
70 #define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 1000)
71 #define wait_for_us(COND, US) _wait_for((COND), (US), 1)
73 /* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */
74 #if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT)
75 # define _WAIT_FOR_ATOMIC_CHECK WARN_ON_ONCE(!in_atomic())
77 # define _WAIT_FOR_ATOMIC_CHECK do { } while (0)
80 #define _wait_for_atomic(COND, US) ({ \
81 unsigned long end__; \
83 _WAIT_FOR_ATOMIC_CHECK; \
84 BUILD_BUG_ON((US) > 50000); \
85 end__ = (local_clock() >> 10) + (US) + 1; \
87 if (time_after((unsigned long)(local_clock() >> 10), end__)) { \
88 /* Unlike the regular wait_for(), this atomic variant \
89 * cannot be preempted (and we'll just ignore the issue\
90 * of irq interruptions) and so we know that no time \
91 * has passed since the last check of COND and can \
92 * immediately report the timeout. \
102 #define wait_for_atomic(COND, MS) _wait_for_atomic((COND), (MS) * 1000)
103 #define wait_for_atomic_us(COND, US) _wait_for_atomic((COND), (US))
105 #define KHz(x) (1000 * (x))
106 #define MHz(x) KHz(1000 * (x))
109 * Display related stuff
112 /* store information about an Ixxx DVO */
113 /* The i830->i865 use multiple DVOs with multiple i2cs */
114 /* the i915, i945 have a single sDVO i2c bus - which is different */
115 #define MAX_OUTPUTS 6
116 /* maximum connectors per crtcs in the mode set */
118 /* Maximum cursor sizes */
119 #define GEN2_CURSOR_WIDTH 64
120 #define GEN2_CURSOR_HEIGHT 64
121 #define MAX_CURSOR_WIDTH 256
122 #define MAX_CURSOR_HEIGHT 256
124 #define INTEL_I2C_BUS_DVO 1
125 #define INTEL_I2C_BUS_SDVO 2
127 /* these are outputs from the chip - integrated only
128 external chips are via DVO or SDVO output */
129 enum intel_output_type {
130 INTEL_OUTPUT_UNUSED = 0,
131 INTEL_OUTPUT_ANALOG = 1,
132 INTEL_OUTPUT_DVO = 2,
133 INTEL_OUTPUT_SDVO = 3,
134 INTEL_OUTPUT_LVDS = 4,
135 INTEL_OUTPUT_TVOUT = 5,
136 INTEL_OUTPUT_HDMI = 6,
137 INTEL_OUTPUT_DISPLAYPORT = 7,
138 INTEL_OUTPUT_EDP = 8,
139 INTEL_OUTPUT_DSI = 9,
140 INTEL_OUTPUT_UNKNOWN = 10,
141 INTEL_OUTPUT_DP_MST = 11,
144 #define INTEL_DVO_CHIP_NONE 0
145 #define INTEL_DVO_CHIP_LVDS 1
146 #define INTEL_DVO_CHIP_TMDS 2
147 #define INTEL_DVO_CHIP_TVOUT 4
149 #define INTEL_DSI_VIDEO_MODE 0
150 #define INTEL_DSI_COMMAND_MODE 1
152 struct intel_framebuffer {
153 struct drm_framebuffer base;
154 struct drm_i915_gem_object *obj;
155 struct intel_rotation_info rot_info;
159 struct drm_fb_helper helper;
160 struct intel_framebuffer *fb;
164 struct intel_encoder {
165 struct drm_encoder base;
167 enum intel_output_type type;
168 unsigned int cloneable;
169 void (*hot_plug)(struct intel_encoder *);
170 bool (*compute_config)(struct intel_encoder *,
171 struct intel_crtc_state *);
172 void (*pre_pll_enable)(struct intel_encoder *);
173 void (*pre_enable)(struct intel_encoder *);
174 void (*enable)(struct intel_encoder *);
175 void (*mode_set)(struct intel_encoder *intel_encoder);
176 void (*disable)(struct intel_encoder *);
177 void (*post_disable)(struct intel_encoder *);
178 void (*post_pll_disable)(struct intel_encoder *);
179 /* Read out the current hw state of this connector, returning true if
180 * the encoder is active. If the encoder is enabled it also set the pipe
181 * it is connected to in the pipe parameter. */
182 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
183 /* Reconstructs the equivalent mode flags for the current hardware
184 * state. This must be called _after_ display->get_pipe_config has
185 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
186 * be set correctly before calling this function. */
187 void (*get_config)(struct intel_encoder *,
188 struct intel_crtc_state *pipe_config);
190 * Called during system suspend after all pending requests for the
191 * encoder are flushed (for example for DP AUX transactions) and
192 * device interrupts are disabled.
194 void (*suspend)(struct intel_encoder *);
196 enum hpd_pin hpd_pin;
200 struct drm_display_mode *fixed_mode;
201 struct drm_display_mode *downclock_mode;
211 bool combination_mode; /* gen 2/4 only */
215 bool util_pin_active_low; /* bxt+ */
216 u8 controller; /* bxt+ only */
217 struct pwm_device *pwm;
219 struct backlight_device *device;
221 /* Connector and platform specific backlight functions */
222 int (*setup)(struct intel_connector *connector, enum pipe pipe);
223 uint32_t (*get)(struct intel_connector *connector);
224 void (*set)(struct intel_connector *connector, uint32_t level);
225 void (*disable)(struct intel_connector *connector);
226 void (*enable)(struct intel_connector *connector);
227 uint32_t (*hz_to_pwm)(struct intel_connector *connector,
229 void (*power)(struct intel_connector *, bool enable);
233 struct intel_connector {
234 struct drm_connector base;
236 * The fixed encoder this connector is connected to.
238 struct intel_encoder *encoder;
240 /* Reads out the current hw, returning true if the connector is enabled
241 * and active (i.e. dpms ON state). */
242 bool (*get_hw_state)(struct intel_connector *);
245 * Removes all interfaces through which the connector is accessible
246 * - like sysfs, debugfs entries -, so that no new operations can be
247 * started on the connector. Also makes sure all currently pending
248 * operations finish before returing.
250 void (*unregister)(struct intel_connector *);
252 /* Panel info for eDP and LVDS */
253 struct intel_panel panel;
255 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
257 struct edid *detect_edid;
259 /* since POLL and HPD connectors may use the same HPD line keep the native
260 state of connector->polled in case hotplug storm detection changes it */
263 void *port; /* store this opaque as its illegal to dereference it */
265 struct intel_dp *mst_port;
268 typedef struct dpll {
280 struct intel_atomic_state {
281 struct drm_atomic_state base;
286 * Calculated device cdclk, can be different from cdclk
287 * only when all crtc's are DPMS off.
289 unsigned int dev_cdclk;
291 bool dpll_set, modeset;
293 unsigned int active_crtcs;
294 unsigned int min_pixclk[I915_MAX_PIPES];
296 struct intel_shared_dpll_config shared_dpll[I915_NUM_PLLS];
297 struct intel_wm_config wm_config;
300 * Current watermarks can't be trusted during hardware readout, so
301 * don't bother calculating intermediate watermarks.
303 bool skip_intermediate_wm;
306 struct intel_plane_state {
307 struct drm_plane_state base;
310 struct drm_rect clip;
315 * = -1 : not using a scaler
316 * >= 0 : using a scalers
318 * plane requiring a scaler:
319 * - During check_plane, its bit is set in
320 * crtc_state->scaler_state.scaler_users by calling helper function
321 * update_scaler_plane.
322 * - scaler_id indicates the scaler it got assigned.
324 * plane doesn't require a scaler:
325 * - this can happen when scaling is no more required or plane simply
327 * - During check_plane, corresponding bit is reset in
328 * crtc_state->scaler_state.scaler_users by calling helper function
329 * update_scaler_plane.
333 struct drm_intel_sprite_colorkey ckey;
335 /* async flip related structures */
336 struct drm_i915_gem_request *wait_req;
339 struct intel_initial_plane_config {
340 struct intel_framebuffer *fb;
346 #define SKL_MIN_SRC_W 8
347 #define SKL_MAX_SRC_W 4096
348 #define SKL_MIN_SRC_H 8
349 #define SKL_MAX_SRC_H 4096
350 #define SKL_MIN_DST_W 8
351 #define SKL_MAX_DST_W 4096
352 #define SKL_MIN_DST_H 8
353 #define SKL_MAX_DST_H 4096
355 struct intel_scaler {
360 struct intel_crtc_scaler_state {
361 #define SKL_NUM_SCALERS 2
362 struct intel_scaler scalers[SKL_NUM_SCALERS];
365 * scaler_users: keeps track of users requesting scalers on this crtc.
367 * If a bit is set, a user is using a scaler.
368 * Here user can be a plane or crtc as defined below:
369 * bits 0-30 - plane (bit position is index from drm_plane_index)
372 * Instead of creating a new index to cover planes and crtc, using
373 * existing drm_plane_index for planes which is well less than 31
374 * planes and bit 31 for crtc. This should be fine to cover all
377 * intel_atomic_setup_scalers will setup available scalers to users
378 * requesting scalers. It will gracefully fail if request exceeds
381 #define SKL_CRTC_INDEX 31
382 unsigned scaler_users;
384 /* scaler used by crtc for panel fitting purpose */
388 /* drm_mode->private_flags */
389 #define I915_MODE_FLAG_INHERITED 1
391 struct intel_pipe_wm {
392 struct intel_wm_level wm[5];
396 bool sprites_enabled;
401 struct skl_wm_level wm[8];
402 struct skl_wm_level trans_wm;
406 struct intel_crtc_state {
407 struct drm_crtc_state base;
410 * quirks - bitfield with hw state readout quirks
412 * For various reasons the hw state readout code might not be able to
413 * completely faithfully read out the current state. These cases are
414 * tracked with quirk flags so that fastboot and state checker can act
417 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
418 unsigned long quirks;
420 bool update_pipe; /* can a fast modeset be performed? */
422 bool wm_changed; /* watermarks are updated */
423 bool fb_changed; /* fb on any of the planes is changed */
425 /* Pipe source size (ie. panel fitter input size)
426 * All planes will be positioned inside this space,
427 * and get clipped at the edges. */
428 int pipe_src_w, pipe_src_h;
430 /* Whether to set up the PCH/FDI. Note that we never allow sharing
431 * between pch encoders and cpu encoders. */
432 bool has_pch_encoder;
434 /* Are we sending infoframes on the attached port */
437 /* CPU Transcoder for the pipe. Currently this can only differ from the
438 * pipe on Haswell (where we have a special eDP transcoder). */
439 enum transcoder cpu_transcoder;
442 * Use reduced/limited/broadcast rbg range, compressing from the full
443 * range fed into the crtcs.
445 bool limited_color_range;
447 /* DP has a bunch of special case unfortunately, so mark the pipe
451 /* DSI has special cases */
452 bool has_dsi_encoder;
454 /* Whether we should send NULL infoframes. Required for audio. */
457 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
458 * has_dp_encoder is set. */
462 * Enable dithering, used when the selected pipe bpp doesn't match the
467 /* Controls for the clock computation, to override various stages. */
470 /* SDVO TV has a bunch of special case. To make multifunction encoders
471 * work correctly, we need to track this at runtime.*/
475 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
476 * required. This is set in the 2nd loop of calling encoder's
477 * ->compute_config if the first pick doesn't work out.
481 /* Settings for the intel dpll used on pretty much everything but
485 /* Selected dpll when shared or DPLL_ID_PRIVATE. */
486 enum intel_dpll_id shared_dpll;
489 * - PORT_CLK_SEL for DDI ports on HSW/BDW.
490 * - enum skl_dpll on SKL
492 uint32_t ddi_pll_sel;
494 /* Actual register state of the dpll, for shared dpll cross-checking. */
495 struct intel_dpll_hw_state dpll_hw_state;
498 struct intel_link_m_n dp_m_n;
500 /* m2_n2 for eDP downclock */
501 struct intel_link_m_n dp_m2_n2;
505 * Frequence the dpll for the port should run at. Differs from the
506 * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
507 * already multiplied by pixel_multiplier.
511 /* Used by SDVO (and if we ever fix it, HDMI). */
512 unsigned pixel_multiplier;
516 /* Panel fitter controls for gen2-gen4 + VLV */
520 u32 lvds_border_bits;
523 /* Panel fitter placement and size for Ironlake+ */
531 /* FDI configuration, only valid if has_pch_encoder is set. */
533 struct intel_link_m_n fdi_m_n;
541 bool dp_encoder_is_mst;
544 struct intel_crtc_scaler_state scaler_state;
546 /* w/a for waiting 2 vblanks during crtc enable */
547 enum pipe hsw_workaround_pipe;
549 /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
554 * Optimal watermarks, programmed post-vblank when this state
558 struct intel_pipe_wm ilk;
559 struct skl_pipe_wm skl;
563 * Intermediate watermarks; these can be programmed immediately
564 * since they satisfy both the current configuration we're
565 * switching away from and the new configuration we're switching
568 struct intel_pipe_wm intermediate;
571 * Platforms with two-step watermark programming will need to
572 * update watermark programming post-vblank to switch from the
573 * safe intermediate watermarks to the optimal final
576 bool need_postvbl_update;
580 struct vlv_wm_state {
581 struct vlv_pipe_wm wm[3];
582 struct vlv_sr_wm sr[3];
583 uint8_t num_active_planes;
589 struct intel_mmio_flip {
590 struct work_struct work;
591 struct drm_i915_private *i915;
592 struct drm_i915_gem_request *req;
593 struct intel_crtc *crtc;
594 unsigned int rotation;
598 * Tracking of operations that need to be performed at the beginning/end of an
599 * atomic commit, outside the atomic section where interrupts are disabled.
600 * These are generally operations that grab mutexes or might otherwise sleep
601 * and thus can't be run with interrupts disabled.
603 struct intel_crtc_atomic_commit {
604 /* Sleepable operations to perform before commit */
606 /* Sleepable operations to perform after commit */
608 bool post_enable_primary;
610 /* Sleepable operations to perform before and after commit */
615 struct drm_crtc base;
618 u8 lut_r[256], lut_g[256], lut_b[256];
620 * Whether the crtc and the connected output pipeline is active. Implies
621 * that crtc->enabled is set, i.e. the current mode configuration has
622 * some outputs connected to this crtc.
625 unsigned long enabled_power_domains;
627 struct intel_overlay *overlay;
628 struct intel_unpin_work *unpin_work;
630 atomic_t unpin_work_count;
632 /* Display surface base address adjustement for pageflips. Note that on
633 * gen4+ this only adjusts up to a tile, offsets within a tile are
634 * handled in the hw itself (with the TILEOFF register). */
639 uint32_t cursor_addr;
640 uint32_t cursor_cntl;
641 uint32_t cursor_size;
642 uint32_t cursor_base;
644 struct intel_crtc_state *config;
646 /* reset counter value when the last flip was submitted */
647 unsigned int reset_counter;
649 /* Access to these should be protected by dev_priv->irq_lock. */
650 bool cpu_fifo_underrun_disabled;
651 bool pch_fifo_underrun_disabled;
653 /* per-pipe watermark state */
655 /* watermarks currently being used */
657 struct intel_pipe_wm ilk;
658 struct skl_pipe_wm skl;
661 /* allow CxSR on this pipe */
668 unsigned start_vbl_count;
669 ktime_t start_vbl_time;
670 int min_vbl, max_vbl;
674 struct intel_crtc_atomic_commit atomic;
676 /* scalers available on this crtc */
679 struct vlv_wm_state wm_state;
682 struct intel_plane_wm_parameters {
683 uint32_t horiz_pixels;
684 uint32_t vert_pixels;
686 * For packed pixel formats:
687 * bytes_per_pixel - holds bytes per pixel
688 * For planar pixel formats:
689 * bytes_per_pixel - holds bytes per pixel for uv-plane
690 * y_bytes_per_pixel - holds bytes per pixel for y-plane
692 uint8_t bytes_per_pixel;
693 uint8_t y_bytes_per_pixel;
697 unsigned int rotation;
702 struct drm_plane base;
707 uint32_t frontbuffer_bit;
709 /* Since we need to change the watermarks before/after
710 * enabling/disabling the planes, we need to store the parameters here
711 * as the other pieces of the struct may not reflect the values we want
712 * for the watermark calculations. Currently only Haswell uses this.
714 struct intel_plane_wm_parameters wm;
717 * NOTE: Do not place new plane state fields here (e.g., when adding
718 * new plane properties). New runtime state should now be placed in
719 * the intel_plane_state structure and accessed via plane_state.
722 void (*update_plane)(struct drm_plane *plane,
723 const struct intel_crtc_state *crtc_state,
724 const struct intel_plane_state *plane_state);
725 void (*disable_plane)(struct drm_plane *plane,
726 struct drm_crtc *crtc);
727 int (*check_plane)(struct drm_plane *plane,
728 struct intel_crtc_state *crtc_state,
729 struct intel_plane_state *state);
732 struct intel_watermark_params {
733 unsigned long fifo_size;
734 unsigned long max_wm;
735 unsigned long default_wm;
736 unsigned long guard_size;
737 unsigned long cacheline_size;
740 struct cxsr_latency {
743 unsigned long fsb_freq;
744 unsigned long mem_freq;
745 unsigned long display_sr;
746 unsigned long display_hpll_disable;
747 unsigned long cursor_sr;
748 unsigned long cursor_hpll_disable;
751 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
752 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
753 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
754 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
755 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
756 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
757 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
758 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
759 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
764 bool limited_color_range;
765 bool color_range_auto;
768 enum hdmi_force_audio force_audio;
769 bool rgb_quant_range_selectable;
770 enum hdmi_picture_aspect aspect_ratio;
771 struct intel_connector *attached_connector;
772 void (*write_infoframe)(struct drm_encoder *encoder,
773 enum hdmi_infoframe_type type,
774 const void *frame, ssize_t len);
775 void (*set_infoframes)(struct drm_encoder *encoder,
777 const struct drm_display_mode *adjusted_mode);
778 bool (*infoframe_enabled)(struct drm_encoder *encoder,
779 const struct intel_crtc_state *pipe_config);
782 struct intel_dp_mst_encoder;
783 #define DP_MAX_DOWNSTREAM_PORTS 0x10
787 * When platform provides two set of M_N registers for dp, we can
788 * program them and switch between them incase of DRRS.
789 * But When only one such register is provided, we have to program the
790 * required divider value on that registers itself based on the DRRS state.
792 * M1_N1 : Program dp_m_n on M1_N1 registers
793 * dp_m2_n2 on M2_N2 registers (If supported)
795 * M2_N2 : Program dp_m2_n2 on M1_N1 registers
796 * M2_N2 registers are not supported
800 /* Sets the m1_n1 and m2_n2 */
806 i915_reg_t output_reg;
807 i915_reg_t aux_ch_ctl_reg;
808 i915_reg_t aux_ch_data_reg[5];
813 enum hdmi_force_audio force_audio;
814 bool limited_color_range;
815 bool color_range_auto;
816 uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
817 uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
818 uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
819 /* sink rates as reported by DP_SUPPORTED_LINK_RATES */
820 uint8_t num_sink_rates;
821 int sink_rates[DP_MAX_SUPPORTED_RATES];
822 struct drm_dp_aux aux;
823 uint8_t train_set[4];
824 int panel_power_up_delay;
825 int panel_power_down_delay;
826 int panel_power_cycle_delay;
827 int backlight_on_delay;
828 int backlight_off_delay;
829 struct delayed_work panel_vdd_work;
831 unsigned long last_power_on;
832 unsigned long last_backlight_off;
833 ktime_t panel_power_off_time;
835 struct notifier_block edp_notifier;
838 * Pipe whose power sequencer is currently locked into
839 * this port. Only relevant on VLV/CHV.
842 struct edp_power_seq pps_delays;
844 bool can_mst; /* this port supports mst */
846 int active_mst_links;
847 /* connector directly attached - won't be use for modeset in mst world */
848 struct intel_connector *attached_connector;
850 /* mst connector list */
851 struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
852 struct drm_dp_mst_topology_mgr mst_mgr;
854 uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
856 * This function returns the value we have to program the AUX_CTL
857 * register with to kick off an AUX transaction.
859 uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
862 uint32_t aux_clock_divider);
864 /* This is called before a link training is starterd */
865 void (*prepare_link_retrain)(struct intel_dp *intel_dp);
867 bool train_set_valid;
869 /* Displayport compliance testing */
870 unsigned long compliance_test_type;
871 unsigned long compliance_test_data;
872 bool compliance_test_active;
875 struct intel_digital_port {
876 struct intel_encoder base;
880 struct intel_hdmi hdmi;
881 enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
882 bool release_cl2_override;
884 /* for communication with audio component; protected by av_mutex */
885 const struct drm_connector *audio_connector;
888 struct intel_dp_mst_encoder {
889 struct intel_encoder base;
891 struct intel_digital_port *primary;
892 void *port; /* store this opaque as its illegal to dereference it */
895 static inline enum dpio_channel
896 vlv_dport_to_channel(struct intel_digital_port *dport)
898 switch (dport->port) {
909 static inline enum dpio_phy
910 vlv_dport_to_phy(struct intel_digital_port *dport)
912 switch (dport->port) {
923 static inline enum dpio_channel
924 vlv_pipe_to_channel(enum pipe pipe)
937 static inline struct drm_crtc *
938 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
940 struct drm_i915_private *dev_priv = dev->dev_private;
941 return dev_priv->pipe_to_crtc_mapping[pipe];
944 static inline struct drm_crtc *
945 intel_get_crtc_for_plane(struct drm_device *dev, int plane)
947 struct drm_i915_private *dev_priv = dev->dev_private;
948 return dev_priv->plane_to_crtc_mapping[plane];
951 struct intel_unpin_work {
952 struct work_struct work;
953 struct drm_crtc *crtc;
954 struct drm_framebuffer *old_fb;
955 struct drm_i915_gem_object *pending_flip_obj;
956 struct drm_pending_vblank_event *event;
958 #define INTEL_FLIP_INACTIVE 0
959 #define INTEL_FLIP_PENDING 1
960 #define INTEL_FLIP_COMPLETE 2
963 struct drm_i915_gem_request *flip_queued_req;
964 u32 flip_queued_vblank;
965 u32 flip_ready_vblank;
966 bool enable_stall_check;
969 struct intel_load_detect_pipe {
970 struct drm_atomic_state *restore_state;
973 static inline struct intel_encoder *
974 intel_attached_encoder(struct drm_connector *connector)
976 return to_intel_connector(connector)->encoder;
979 static inline struct intel_digital_port *
980 enc_to_dig_port(struct drm_encoder *encoder)
982 return container_of(encoder, struct intel_digital_port, base.base);
985 static inline struct intel_dp_mst_encoder *
986 enc_to_mst(struct drm_encoder *encoder)
988 return container_of(encoder, struct intel_dp_mst_encoder, base.base);
991 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
993 return &enc_to_dig_port(encoder)->dp;
996 static inline struct intel_digital_port *
997 dp_to_dig_port(struct intel_dp *intel_dp)
999 return container_of(intel_dp, struct intel_digital_port, dp);
1002 static inline struct intel_digital_port *
1003 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
1005 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
1009 * Returns the number of planes for this pipe, ie the number of sprites + 1
1010 * (primary plane). This doesn't count the cursor plane then.
1012 static inline unsigned int intel_num_planes(struct intel_crtc *crtc)
1014 return INTEL_INFO(crtc->base.dev)->num_sprites[crtc->pipe] + 1;
1017 /* intel_fifo_underrun.c */
1018 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1019 enum pipe pipe, bool enable);
1020 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1021 enum transcoder pch_transcoder,
1023 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1025 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1026 enum transcoder pch_transcoder);
1027 void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv);
1028 void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv);
1031 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1032 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1033 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1034 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1035 void gen6_reset_rps_interrupts(struct drm_device *dev);
1036 void gen6_enable_rps_interrupts(struct drm_device *dev);
1037 void gen6_disable_rps_interrupts(struct drm_device *dev);
1038 u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask);
1039 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
1040 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
1041 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
1044 * We only use drm_irq_uninstall() at unload and VT switch, so
1045 * this is the only thing we need to check.
1047 return dev_priv->pm.irqs_enabled;
1050 int intel_get_crtc_scanline(struct intel_crtc *crtc);
1051 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
1052 unsigned int pipe_mask);
1053 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
1054 unsigned int pipe_mask);
1057 void intel_crt_init(struct drm_device *dev);
1061 void intel_ddi_clk_select(struct intel_encoder *encoder,
1062 const struct intel_crtc_state *pipe_config);
1063 void intel_prepare_ddi_buffer(struct intel_encoder *encoder);
1064 void hsw_fdi_link_train(struct drm_crtc *crtc);
1065 void intel_ddi_init(struct drm_device *dev, enum port port);
1066 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
1067 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
1068 void intel_ddi_pll_init(struct drm_device *dev);
1069 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
1070 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1071 enum transcoder cpu_transcoder);
1072 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
1073 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
1074 bool intel_ddi_pll_select(struct intel_crtc *crtc,
1075 struct intel_crtc_state *crtc_state);
1076 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
1077 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp);
1078 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
1079 void intel_ddi_fdi_disable(struct drm_crtc *crtc);
1080 bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
1081 struct intel_crtc *intel_crtc);
1082 void intel_ddi_get_config(struct intel_encoder *encoder,
1083 struct intel_crtc_state *pipe_config);
1084 struct intel_encoder *
1085 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state);
1087 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
1088 void intel_ddi_clock_get(struct intel_encoder *encoder,
1089 struct intel_crtc_state *pipe_config);
1090 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
1091 uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
1093 /* intel_frontbuffer.c */
1094 void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
1095 enum fb_op_origin origin);
1096 void intel_frontbuffer_flip_prepare(struct drm_device *dev,
1097 unsigned frontbuffer_bits);
1098 void intel_frontbuffer_flip_complete(struct drm_device *dev,
1099 unsigned frontbuffer_bits);
1100 void intel_frontbuffer_flip(struct drm_device *dev,
1101 unsigned frontbuffer_bits);
1102 unsigned int intel_fb_align_height(struct drm_device *dev,
1103 unsigned int height,
1104 uint32_t pixel_format,
1105 uint64_t fb_format_modifier);
1106 void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire,
1107 enum fb_op_origin origin);
1108 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
1109 uint64_t fb_modifier, uint32_t pixel_format);
1112 void intel_init_audio(struct drm_device *dev);
1113 void intel_audio_codec_enable(struct intel_encoder *encoder);
1114 void intel_audio_codec_disable(struct intel_encoder *encoder);
1115 void i915_audio_component_init(struct drm_i915_private *dev_priv);
1116 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
1118 /* intel_display.c */
1119 extern const struct drm_plane_funcs intel_plane_funcs;
1120 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
1121 bool intel_has_pending_fb_unpin(struct drm_device *dev);
1122 void intel_mark_busy(struct drm_device *dev);
1123 void intel_mark_idle(struct drm_device *dev);
1124 void intel_crtc_restore_mode(struct drm_crtc *crtc);
1125 int intel_display_suspend(struct drm_device *dev);
1126 void intel_encoder_destroy(struct drm_encoder *encoder);
1127 int intel_connector_init(struct intel_connector *);
1128 struct intel_connector *intel_connector_alloc(void);
1129 bool intel_connector_get_hw_state(struct intel_connector *connector);
1130 void intel_connector_attach_encoder(struct intel_connector *connector,
1131 struct intel_encoder *encoder);
1132 struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
1133 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
1134 struct drm_crtc *crtc);
1135 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
1136 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
1137 struct drm_file *file_priv);
1138 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1140 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type);
1142 intel_wait_for_vblank(struct drm_device *dev, int pipe)
1144 drm_wait_one_vblank(dev, pipe);
1147 intel_wait_for_vblank_if_active(struct drm_device *dev, int pipe)
1149 const struct intel_crtc *crtc =
1150 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
1153 intel_wait_for_vblank(dev, pipe);
1155 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1156 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1157 struct intel_digital_port *dport,
1158 unsigned int expected_mask);
1159 bool intel_get_load_detect_pipe(struct drm_connector *connector,
1160 struct drm_display_mode *mode,
1161 struct intel_load_detect_pipe *old,
1162 struct drm_modeset_acquire_ctx *ctx);
1163 void intel_release_load_detect_pipe(struct drm_connector *connector,
1164 struct intel_load_detect_pipe *old,
1165 struct drm_modeset_acquire_ctx *ctx);
1166 int intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
1167 unsigned int rotation);
1168 struct drm_framebuffer *
1169 __intel_framebuffer_create(struct drm_device *dev,
1170 struct drm_mode_fb_cmd2 *mode_cmd,
1171 struct drm_i915_gem_object *obj);
1172 void intel_prepare_page_flip(struct drm_device *dev, int plane);
1173 void intel_finish_page_flip(struct drm_device *dev, int pipe);
1174 void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
1175 void intel_check_page_flip(struct drm_device *dev, int pipe);
1176 int intel_prepare_plane_fb(struct drm_plane *plane,
1177 const struct drm_plane_state *new_state);
1178 void intel_cleanup_plane_fb(struct drm_plane *plane,
1179 const struct drm_plane_state *old_state);
1180 int intel_plane_atomic_get_property(struct drm_plane *plane,
1181 const struct drm_plane_state *state,
1182 struct drm_property *property,
1184 int intel_plane_atomic_set_property(struct drm_plane *plane,
1185 struct drm_plane_state *state,
1186 struct drm_property *property,
1188 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
1189 struct drm_plane_state *plane_state);
1191 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
1192 uint64_t fb_modifier, unsigned int cpp);
1195 intel_rotation_90_or_270(unsigned int rotation)
1197 return rotation & (BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270));
1200 void intel_create_rotation_property(struct drm_device *dev,
1201 struct intel_plane *plane);
1203 /* shared dpll functions */
1204 struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
1205 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1206 struct intel_shared_dpll *pll,
1208 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
1209 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
1210 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
1211 struct intel_crtc_state *state);
1213 int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
1214 const struct dpll *dpll);
1215 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe);
1216 int lpt_get_iclkip(struct drm_i915_private *dev_priv);
1218 /* modesetting asserts */
1219 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1221 void assert_pll(struct drm_i915_private *dev_priv,
1222 enum pipe pipe, bool state);
1223 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1224 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1225 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1226 enum pipe pipe, bool state);
1227 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1228 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1229 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1230 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1231 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1232 u32 intel_compute_tile_offset(int *x, int *y,
1233 const struct drm_framebuffer *fb, int plane,
1235 unsigned int rotation);
1236 void intel_prepare_reset(struct drm_device *dev);
1237 void intel_finish_reset(struct drm_device *dev);
1238 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1239 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1240 void broxton_init_cdclk(struct drm_device *dev);
1241 void broxton_uninit_cdclk(struct drm_device *dev);
1242 void broxton_ddi_phy_init(struct drm_device *dev);
1243 void broxton_ddi_phy_uninit(struct drm_device *dev);
1244 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1245 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1246 void skl_init_cdclk(struct drm_i915_private *dev_priv);
1247 int skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
1248 void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1249 void skl_enable_dc6(struct drm_i915_private *dev_priv);
1250 void skl_disable_dc6(struct drm_i915_private *dev_priv);
1251 void intel_dp_get_m_n(struct intel_crtc *crtc,
1252 struct intel_crtc_state *pipe_config);
1253 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
1254 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1255 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1256 intel_clock_t *best_clock);
1257 int chv_calc_dpll_params(int refclk, intel_clock_t *pll_clock);
1259 bool intel_crtc_active(struct drm_crtc *crtc);
1260 void hsw_enable_ips(struct intel_crtc *crtc);
1261 void hsw_disable_ips(struct intel_crtc *crtc);
1262 enum intel_display_power_domain
1263 intel_display_port_power_domain(struct intel_encoder *intel_encoder);
1264 enum intel_display_power_domain
1265 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder);
1266 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1267 struct intel_crtc_state *pipe_config);
1269 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1270 int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
1272 u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
1273 struct drm_i915_gem_object *obj,
1274 unsigned int plane);
1276 u32 skl_plane_ctl_format(uint32_t pixel_format);
1277 u32 skl_plane_ctl_tiling(uint64_t fb_modifier);
1278 u32 skl_plane_ctl_rotation(unsigned int rotation);
1281 void intel_csr_ucode_init(struct drm_i915_private *);
1282 void intel_csr_load_program(struct drm_i915_private *);
1283 void intel_csr_ucode_fini(struct drm_i915_private *);
1286 void intel_dp_init(struct drm_device *dev, i915_reg_t output_reg, enum port port);
1287 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1288 struct intel_connector *intel_connector);
1289 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1290 const struct intel_crtc_state *pipe_config);
1291 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1292 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1293 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1294 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1295 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
1296 bool intel_dp_compute_config(struct intel_encoder *encoder,
1297 struct intel_crtc_state *pipe_config);
1298 bool intel_dp_is_edp(struct drm_device *dev, enum port port);
1299 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1301 void intel_edp_backlight_on(struct intel_dp *intel_dp);
1302 void intel_edp_backlight_off(struct intel_dp *intel_dp);
1303 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1304 void intel_edp_panel_on(struct intel_dp *intel_dp);
1305 void intel_edp_panel_off(struct intel_dp *intel_dp);
1306 void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
1307 void intel_dp_mst_suspend(struct drm_device *dev);
1308 void intel_dp_mst_resume(struct drm_device *dev);
1309 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1310 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1311 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1312 void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv);
1313 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1314 void intel_plane_destroy(struct drm_plane *plane);
1315 void intel_edp_drrs_enable(struct intel_dp *intel_dp);
1316 void intel_edp_drrs_disable(struct intel_dp *intel_dp);
1317 void intel_edp_drrs_invalidate(struct drm_device *dev,
1318 unsigned frontbuffer_bits);
1319 void intel_edp_drrs_flush(struct drm_device *dev, unsigned frontbuffer_bits);
1320 bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
1321 struct intel_digital_port *port);
1322 void hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config);
1325 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
1326 uint8_t dp_train_pat);
1328 intel_dp_set_signal_levels(struct intel_dp *intel_dp);
1329 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
1331 intel_dp_voltage_max(struct intel_dp *intel_dp);
1333 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing);
1334 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1335 uint8_t *link_bw, uint8_t *rate_select);
1336 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
1338 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]);
1340 /* intel_dp_mst.c */
1341 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1342 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1344 void intel_dsi_init(struct drm_device *dev);
1348 void intel_dvo_init(struct drm_device *dev);
1351 /* legacy fbdev emulation in intel_fbdev.c */
1352 #ifdef CONFIG_DRM_FBDEV_EMULATION
1353 extern int intel_fbdev_init(struct drm_device *dev);
1354 extern void intel_fbdev_initial_config_async(struct drm_device *dev);
1355 extern void intel_fbdev_fini(struct drm_device *dev);
1356 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1357 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1358 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1360 static inline int intel_fbdev_init(struct drm_device *dev)
1365 static inline void intel_fbdev_initial_config_async(struct drm_device *dev)
1369 static inline void intel_fbdev_fini(struct drm_device *dev)
1373 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1377 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1383 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1384 struct drm_atomic_state *state);
1385 bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
1386 void intel_fbc_pre_update(struct intel_crtc *crtc);
1387 void intel_fbc_post_update(struct intel_crtc *crtc);
1388 void intel_fbc_init(struct drm_i915_private *dev_priv);
1389 void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv);
1390 void intel_fbc_enable(struct intel_crtc *crtc);
1391 void intel_fbc_disable(struct intel_crtc *crtc);
1392 void intel_fbc_global_disable(struct drm_i915_private *dev_priv);
1393 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1394 unsigned int frontbuffer_bits,
1395 enum fb_op_origin origin);
1396 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1397 unsigned int frontbuffer_bits, enum fb_op_origin origin);
1398 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
1401 void intel_hdmi_init(struct drm_device *dev, i915_reg_t hdmi_reg, enum port port);
1402 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1403 struct intel_connector *intel_connector);
1404 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1405 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1406 struct intel_crtc_state *pipe_config);
1410 void intel_lvds_init(struct drm_device *dev);
1411 bool intel_is_dual_link_lvds(struct drm_device *dev);
1415 int intel_connector_update_modes(struct drm_connector *connector,
1417 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1418 void intel_attach_force_audio_property(struct drm_connector *connector);
1419 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1420 void intel_attach_aspect_ratio_property(struct drm_connector *connector);
1423 /* intel_overlay.c */
1424 void intel_setup_overlay(struct drm_device *dev);
1425 void intel_cleanup_overlay(struct drm_device *dev);
1426 int intel_overlay_switch_off(struct intel_overlay *overlay);
1427 int intel_overlay_put_image(struct drm_device *dev, void *data,
1428 struct drm_file *file_priv);
1429 int intel_overlay_attrs(struct drm_device *dev, void *data,
1430 struct drm_file *file_priv);
1431 void intel_overlay_reset(struct drm_i915_private *dev_priv);
1435 int intel_panel_init(struct intel_panel *panel,
1436 struct drm_display_mode *fixed_mode,
1437 struct drm_display_mode *downclock_mode);
1438 void intel_panel_fini(struct intel_panel *panel);
1439 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1440 struct drm_display_mode *adjusted_mode);
1441 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1442 struct intel_crtc_state *pipe_config,
1444 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1445 struct intel_crtc_state *pipe_config,
1447 void intel_panel_set_backlight_acpi(struct intel_connector *connector,
1448 u32 level, u32 max);
1449 int intel_panel_setup_backlight(struct drm_connector *connector, enum pipe pipe);
1450 void intel_panel_enable_backlight(struct intel_connector *connector);
1451 void intel_panel_disable_backlight(struct intel_connector *connector);
1452 void intel_panel_destroy_backlight(struct drm_connector *connector);
1453 enum drm_connector_status intel_panel_detect(struct drm_device *dev);
1454 extern struct drm_display_mode *intel_find_panel_downclock(
1455 struct drm_device *dev,
1456 struct drm_display_mode *fixed_mode,
1457 struct drm_connector *connector);
1458 void intel_backlight_register(struct drm_device *dev);
1459 void intel_backlight_unregister(struct drm_device *dev);
1463 void intel_psr_enable(struct intel_dp *intel_dp);
1464 void intel_psr_disable(struct intel_dp *intel_dp);
1465 void intel_psr_invalidate(struct drm_device *dev,
1466 unsigned frontbuffer_bits);
1467 void intel_psr_flush(struct drm_device *dev,
1468 unsigned frontbuffer_bits,
1469 enum fb_op_origin origin);
1470 void intel_psr_init(struct drm_device *dev);
1471 void intel_psr_single_frame_update(struct drm_device *dev,
1472 unsigned frontbuffer_bits);
1474 /* intel_runtime_pm.c */
1475 int intel_power_domains_init(struct drm_i915_private *);
1476 void intel_power_domains_fini(struct drm_i915_private *);
1477 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
1478 void intel_power_domains_suspend(struct drm_i915_private *dev_priv);
1479 void skl_pw1_misc_io_init(struct drm_i915_private *dev_priv);
1480 void skl_pw1_misc_io_fini(struct drm_i915_private *dev_priv);
1481 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1483 intel_display_power_domain_str(enum intel_display_power_domain domain);
1485 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1486 enum intel_display_power_domain domain);
1487 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1488 enum intel_display_power_domain domain);
1489 void intel_display_power_get(struct drm_i915_private *dev_priv,
1490 enum intel_display_power_domain domain);
1491 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
1492 enum intel_display_power_domain domain);
1493 void intel_display_power_put(struct drm_i915_private *dev_priv,
1494 enum intel_display_power_domain domain);
1497 assert_rpm_device_not_suspended(struct drm_i915_private *dev_priv)
1499 WARN_ONCE(dev_priv->pm.suspended,
1500 "Device suspended during HW access\n");
1504 assert_rpm_wakelock_held(struct drm_i915_private *dev_priv)
1506 assert_rpm_device_not_suspended(dev_priv);
1507 /* FIXME: Needs to be converted back to WARN_ONCE, but currently causes
1508 * too much noise. */
1509 if (!atomic_read(&dev_priv->pm.wakeref_count))
1510 DRM_DEBUG_DRIVER("RPM wakelock ref not held during HW access");
1514 assert_rpm_atomic_begin(struct drm_i915_private *dev_priv)
1516 int seq = atomic_read(&dev_priv->pm.atomic_seq);
1518 assert_rpm_wakelock_held(dev_priv);
1524 assert_rpm_atomic_end(struct drm_i915_private *dev_priv, int begin_seq)
1526 WARN_ONCE(atomic_read(&dev_priv->pm.atomic_seq) != begin_seq,
1527 "HW access outside of RPM atomic section\n");
1531 * disable_rpm_wakeref_asserts - disable the RPM assert checks
1532 * @dev_priv: i915 device instance
1534 * This function disable asserts that check if we hold an RPM wakelock
1535 * reference, while keeping the device-not-suspended checks still enabled.
1536 * It's meant to be used only in special circumstances where our rule about
1537 * the wakelock refcount wrt. the device power state doesn't hold. According
1538 * to this rule at any point where we access the HW or want to keep the HW in
1539 * an active state we must hold an RPM wakelock reference acquired via one of
1540 * the intel_runtime_pm_get() helpers. Currently there are a few special spots
1541 * where this rule doesn't hold: the IRQ and suspend/resume handlers, the
1542 * forcewake release timer, and the GPU RPS and hangcheck works. All other
1543 * users should avoid using this function.
1545 * Any calls to this function must have a symmetric call to
1546 * enable_rpm_wakeref_asserts().
1549 disable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1551 atomic_inc(&dev_priv->pm.wakeref_count);
1555 * enable_rpm_wakeref_asserts - re-enable the RPM assert checks
1556 * @dev_priv: i915 device instance
1558 * This function re-enables the RPM assert checks after disabling them with
1559 * disable_rpm_wakeref_asserts. It's meant to be used only in special
1560 * circumstances otherwise its use should be avoided.
1562 * Any calls to this function must have a symmetric call to
1563 * disable_rpm_wakeref_asserts().
1566 enable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1568 atomic_dec(&dev_priv->pm.wakeref_count);
1571 /* TODO: convert users of these to rely instead on proper RPM refcounting */
1572 #define DISABLE_RPM_WAKEREF_ASSERTS(dev_priv) \
1573 disable_rpm_wakeref_asserts(dev_priv)
1575 #define ENABLE_RPM_WAKEREF_ASSERTS(dev_priv) \
1576 enable_rpm_wakeref_asserts(dev_priv)
1578 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1579 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv);
1580 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1581 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1583 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
1585 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1586 bool override, unsigned int mask);
1587 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1588 enum dpio_channel ch, bool override);
1592 void intel_init_clock_gating(struct drm_device *dev);
1593 void intel_suspend_hw(struct drm_device *dev);
1594 int ilk_wm_max_level(const struct drm_device *dev);
1595 void intel_update_watermarks(struct drm_crtc *crtc);
1596 void intel_init_pm(struct drm_device *dev);
1597 void intel_pm_setup(struct drm_device *dev);
1598 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1599 void intel_gpu_ips_teardown(void);
1600 void intel_init_gt_powersave(struct drm_device *dev);
1601 void intel_cleanup_gt_powersave(struct drm_device *dev);
1602 void intel_enable_gt_powersave(struct drm_device *dev);
1603 void intel_disable_gt_powersave(struct drm_device *dev);
1604 void intel_suspend_gt_powersave(struct drm_device *dev);
1605 void intel_reset_gt_powersave(struct drm_device *dev);
1606 void gen6_update_ring_freq(struct drm_device *dev);
1607 void gen6_rps_busy(struct drm_i915_private *dev_priv);
1608 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
1609 void gen6_rps_idle(struct drm_i915_private *dev_priv);
1610 void gen6_rps_boost(struct drm_i915_private *dev_priv,
1611 struct intel_rps_client *rps,
1612 unsigned long submitted);
1613 void intel_queue_rps_boost_for_request(struct drm_device *dev,
1614 struct drm_i915_gem_request *req);
1615 void vlv_wm_get_hw_state(struct drm_device *dev);
1616 void ilk_wm_get_hw_state(struct drm_device *dev);
1617 void skl_wm_get_hw_state(struct drm_device *dev);
1618 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
1619 struct skl_ddb_allocation *ddb /* out */);
1620 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config);
1621 bool ilk_disable_lp_wm(struct drm_device *dev);
1622 int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6);
1625 bool intel_sdvo_init(struct drm_device *dev,
1626 i915_reg_t reg, enum port port);
1629 /* intel_sprite.c */
1630 int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
1631 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1632 struct drm_file *file_priv);
1633 void intel_pipe_update_start(struct intel_crtc *crtc);
1634 void intel_pipe_update_end(struct intel_crtc *crtc);
1637 void intel_tv_init(struct drm_device *dev);
1639 /* intel_atomic.c */
1640 int intel_connector_atomic_get_property(struct drm_connector *connector,
1641 const struct drm_connector_state *state,
1642 struct drm_property *property,
1644 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
1645 void intel_crtc_destroy_state(struct drm_crtc *crtc,
1646 struct drm_crtc_state *state);
1647 struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
1648 void intel_atomic_state_clear(struct drm_atomic_state *);
1649 struct intel_shared_dpll_config *
1650 intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s);
1652 static inline struct intel_crtc_state *
1653 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
1654 struct intel_crtc *crtc)
1656 struct drm_crtc_state *crtc_state;
1657 crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
1658 if (IS_ERR(crtc_state))
1659 return ERR_CAST(crtc_state);
1661 return to_intel_crtc_state(crtc_state);
1664 static inline struct intel_plane_state *
1665 intel_atomic_get_existing_plane_state(struct drm_atomic_state *state,
1666 struct intel_plane *plane)
1668 struct drm_plane_state *plane_state;
1670 plane_state = drm_atomic_get_existing_plane_state(state, &plane->base);
1672 return to_intel_plane_state(plane_state);
1675 int intel_atomic_setup_scalers(struct drm_device *dev,
1676 struct intel_crtc *intel_crtc,
1677 struct intel_crtc_state *crtc_state);
1679 /* intel_atomic_plane.c */
1680 struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
1681 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
1682 void intel_plane_destroy_state(struct drm_plane *plane,
1683 struct drm_plane_state *state);
1684 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
1686 #endif /* __INTEL_DRV_H__ */