2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #ifndef __INTEL_DRV_H__
26 #define __INTEL_DRV_H__
28 #include <linux/async.h>
29 #include <linux/i2c.h>
30 #include <linux/hdmi.h>
31 #include <drm/i915_drm.h>
33 #include <drm/drm_crtc.h>
34 #include <drm/drm_crtc_helper.h>
35 #include <drm/drm_fb_helper.h>
36 #include <drm/drm_dp_dual_mode_helper.h>
37 #include <drm/drm_dp_mst_helper.h>
38 #include <drm/drm_rect.h>
39 #include <drm/drm_atomic.h>
42 * _wait_for - magic (register) wait macro
44 * Does the right thing for modeset paths when run under kdgb or similar atomic
45 * contexts. Note that it's important that we check the condition again after
46 * having timed out, since the timeout could be due to preemption or similar and
47 * we've never had a chance to check the condition before the timeout.
49 * TODO: When modesetting has fully transitioned to atomic, the below
50 * drm_can_sleep() can be removed and in_atomic()/!in_atomic() asserts
53 #define _wait_for(COND, US, W) ({ \
54 unsigned long timeout__ = jiffies + usecs_to_jiffies(US) + 1; \
57 if (time_after(jiffies, timeout__)) { \
62 if ((W) && drm_can_sleep()) { \
63 usleep_range((W), (W)*2); \
71 #define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 1000)
72 #define wait_for_us(COND, US) _wait_for((COND), (US), 1)
74 /* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */
75 #if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT)
76 # define _WAIT_FOR_ATOMIC_CHECK WARN_ON_ONCE(!in_atomic())
78 # define _WAIT_FOR_ATOMIC_CHECK do { } while (0)
81 #define _wait_for_atomic(COND, US) ({ \
82 unsigned long end__; \
84 _WAIT_FOR_ATOMIC_CHECK; \
85 BUILD_BUG_ON((US) > 50000); \
86 end__ = (local_clock() >> 10) + (US) + 1; \
88 if (time_after((unsigned long)(local_clock() >> 10), end__)) { \
89 /* Unlike the regular wait_for(), this atomic variant \
90 * cannot be preempted (and we'll just ignore the issue\
91 * of irq interruptions) and so we know that no time \
92 * has passed since the last check of COND and can \
93 * immediately report the timeout. \
103 #define wait_for_atomic(COND, MS) _wait_for_atomic((COND), (MS) * 1000)
104 #define wait_for_atomic_us(COND, US) _wait_for_atomic((COND), (US))
106 #define KHz(x) (1000 * (x))
107 #define MHz(x) KHz(1000 * (x))
110 * Display related stuff
113 /* store information about an Ixxx DVO */
114 /* The i830->i865 use multiple DVOs with multiple i2cs */
115 /* the i915, i945 have a single sDVO i2c bus - which is different */
116 #define MAX_OUTPUTS 6
117 /* maximum connectors per crtcs in the mode set */
119 /* Maximum cursor sizes */
120 #define GEN2_CURSOR_WIDTH 64
121 #define GEN2_CURSOR_HEIGHT 64
122 #define MAX_CURSOR_WIDTH 256
123 #define MAX_CURSOR_HEIGHT 256
125 #define INTEL_I2C_BUS_DVO 1
126 #define INTEL_I2C_BUS_SDVO 2
128 /* these are outputs from the chip - integrated only
129 external chips are via DVO or SDVO output */
130 enum intel_output_type {
131 INTEL_OUTPUT_UNUSED = 0,
132 INTEL_OUTPUT_ANALOG = 1,
133 INTEL_OUTPUT_DVO = 2,
134 INTEL_OUTPUT_SDVO = 3,
135 INTEL_OUTPUT_LVDS = 4,
136 INTEL_OUTPUT_TVOUT = 5,
137 INTEL_OUTPUT_HDMI = 6,
138 INTEL_OUTPUT_DISPLAYPORT = 7,
139 INTEL_OUTPUT_EDP = 8,
140 INTEL_OUTPUT_DSI = 9,
141 INTEL_OUTPUT_UNKNOWN = 10,
142 INTEL_OUTPUT_DP_MST = 11,
145 #define INTEL_DVO_CHIP_NONE 0
146 #define INTEL_DVO_CHIP_LVDS 1
147 #define INTEL_DVO_CHIP_TMDS 2
148 #define INTEL_DVO_CHIP_TVOUT 4
150 #define INTEL_DSI_VIDEO_MODE 0
151 #define INTEL_DSI_COMMAND_MODE 1
153 struct intel_framebuffer {
154 struct drm_framebuffer base;
155 struct drm_i915_gem_object *obj;
156 struct intel_rotation_info rot_info;
160 struct drm_fb_helper helper;
161 struct intel_framebuffer *fb;
165 struct intel_encoder {
166 struct drm_encoder base;
168 enum intel_output_type type;
169 unsigned int cloneable;
170 void (*hot_plug)(struct intel_encoder *);
171 bool (*compute_config)(struct intel_encoder *,
172 struct intel_crtc_state *);
173 void (*pre_pll_enable)(struct intel_encoder *);
174 void (*pre_enable)(struct intel_encoder *);
175 void (*enable)(struct intel_encoder *);
176 void (*mode_set)(struct intel_encoder *intel_encoder);
177 void (*disable)(struct intel_encoder *);
178 void (*post_disable)(struct intel_encoder *);
179 void (*post_pll_disable)(struct intel_encoder *);
180 /* Read out the current hw state of this connector, returning true if
181 * the encoder is active. If the encoder is enabled it also set the pipe
182 * it is connected to in the pipe parameter. */
183 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
184 /* Reconstructs the equivalent mode flags for the current hardware
185 * state. This must be called _after_ display->get_pipe_config has
186 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
187 * be set correctly before calling this function. */
188 void (*get_config)(struct intel_encoder *,
189 struct intel_crtc_state *pipe_config);
191 * Called during system suspend after all pending requests for the
192 * encoder are flushed (for example for DP AUX transactions) and
193 * device interrupts are disabled.
195 void (*suspend)(struct intel_encoder *);
197 enum hpd_pin hpd_pin;
201 struct drm_display_mode *fixed_mode;
202 struct drm_display_mode *downclock_mode;
212 bool combination_mode; /* gen 2/4 only */
216 bool util_pin_active_low; /* bxt+ */
217 u8 controller; /* bxt+ only */
218 struct pwm_device *pwm;
220 struct backlight_device *device;
222 /* Connector and platform specific backlight functions */
223 int (*setup)(struct intel_connector *connector, enum pipe pipe);
224 uint32_t (*get)(struct intel_connector *connector);
225 void (*set)(struct intel_connector *connector, uint32_t level);
226 void (*disable)(struct intel_connector *connector);
227 void (*enable)(struct intel_connector *connector);
228 uint32_t (*hz_to_pwm)(struct intel_connector *connector,
230 void (*power)(struct intel_connector *, bool enable);
234 struct intel_connector {
235 struct drm_connector base;
237 * The fixed encoder this connector is connected to.
239 struct intel_encoder *encoder;
241 /* Reads out the current hw, returning true if the connector is enabled
242 * and active (i.e. dpms ON state). */
243 bool (*get_hw_state)(struct intel_connector *);
246 * Removes all interfaces through which the connector is accessible
247 * - like sysfs, debugfs entries -, so that no new operations can be
248 * started on the connector. Also makes sure all currently pending
249 * operations finish before returing.
251 void (*unregister)(struct intel_connector *);
253 /* Panel info for eDP and LVDS */
254 struct intel_panel panel;
256 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
258 struct edid *detect_edid;
260 /* since POLL and HPD connectors may use the same HPD line keep the native
261 state of connector->polled in case hotplug storm detection changes it */
264 void *port; /* store this opaque as its illegal to dereference it */
266 struct intel_dp *mst_port;
281 struct intel_atomic_state {
282 struct drm_atomic_state base;
287 * Calculated device cdclk, can be different from cdclk
288 * only when all crtc's are DPMS off.
290 unsigned int dev_cdclk;
292 bool dpll_set, modeset;
295 * Does this transaction change the pipes that are active? This mask
296 * tracks which CRTC's have changed their active state at the end of
297 * the transaction (not counting the temporary disable during modesets).
298 * This mask should only be non-zero when intel_state->modeset is true,
299 * but the converse is not necessarily true; simply changing a mode may
300 * not flip the final active status of any CRTC's
302 unsigned int active_pipe_changes;
304 unsigned int active_crtcs;
305 unsigned int min_pixclk[I915_MAX_PIPES];
307 struct intel_shared_dpll_config shared_dpll[I915_NUM_PLLS];
308 struct intel_wm_config wm_config;
311 * Current watermarks can't be trusted during hardware readout, so
312 * don't bother calculating intermediate watermarks.
314 bool skip_intermediate_wm;
317 struct skl_wm_values wm_results;
320 struct intel_plane_state {
321 struct drm_plane_state base;
324 struct drm_rect clip;
329 * = -1 : not using a scaler
330 * >= 0 : using a scalers
332 * plane requiring a scaler:
333 * - During check_plane, its bit is set in
334 * crtc_state->scaler_state.scaler_users by calling helper function
335 * update_scaler_plane.
336 * - scaler_id indicates the scaler it got assigned.
338 * plane doesn't require a scaler:
339 * - this can happen when scaling is no more required or plane simply
341 * - During check_plane, corresponding bit is reset in
342 * crtc_state->scaler_state.scaler_users by calling helper function
343 * update_scaler_plane.
347 struct drm_intel_sprite_colorkey ckey;
349 /* async flip related structures */
350 struct drm_i915_gem_request *wait_req;
353 struct intel_initial_plane_config {
354 struct intel_framebuffer *fb;
360 #define SKL_MIN_SRC_W 8
361 #define SKL_MAX_SRC_W 4096
362 #define SKL_MIN_SRC_H 8
363 #define SKL_MAX_SRC_H 4096
364 #define SKL_MIN_DST_W 8
365 #define SKL_MAX_DST_W 4096
366 #define SKL_MIN_DST_H 8
367 #define SKL_MAX_DST_H 4096
369 struct intel_scaler {
374 struct intel_crtc_scaler_state {
375 #define SKL_NUM_SCALERS 2
376 struct intel_scaler scalers[SKL_NUM_SCALERS];
379 * scaler_users: keeps track of users requesting scalers on this crtc.
381 * If a bit is set, a user is using a scaler.
382 * Here user can be a plane or crtc as defined below:
383 * bits 0-30 - plane (bit position is index from drm_plane_index)
386 * Instead of creating a new index to cover planes and crtc, using
387 * existing drm_plane_index for planes which is well less than 31
388 * planes and bit 31 for crtc. This should be fine to cover all
391 * intel_atomic_setup_scalers will setup available scalers to users
392 * requesting scalers. It will gracefully fail if request exceeds
395 #define SKL_CRTC_INDEX 31
396 unsigned scaler_users;
398 /* scaler used by crtc for panel fitting purpose */
402 /* drm_mode->private_flags */
403 #define I915_MODE_FLAG_INHERITED 1
405 struct intel_pipe_wm {
406 struct intel_wm_level wm[5];
407 struct intel_wm_level raw_wm[5];
411 bool sprites_enabled;
416 struct skl_wm_level wm[8];
417 struct skl_wm_level trans_wm;
421 struct intel_crtc_wm_state {
425 * Intermediate watermarks; these can be
426 * programmed immediately since they satisfy
427 * both the current configuration we're
428 * switching away from and the new
429 * configuration we're switching to.
431 struct intel_pipe_wm intermediate;
434 * Optimal watermarks, programmed post-vblank
435 * when this state is committed.
437 struct intel_pipe_wm optimal;
441 /* gen9+ only needs 1-step wm programming */
442 struct skl_pipe_wm optimal;
444 /* cached plane data rate */
445 unsigned plane_data_rate[I915_MAX_PLANES];
446 unsigned plane_y_data_rate[I915_MAX_PLANES];
448 /* minimum block allocation */
449 uint16_t minimum_blocks[I915_MAX_PLANES];
450 uint16_t minimum_y_blocks[I915_MAX_PLANES];
455 * Platforms with two-step watermark programming will need to
456 * update watermark programming post-vblank to switch from the
457 * safe intermediate watermarks to the optimal final
460 bool need_postvbl_update;
463 struct intel_crtc_state {
464 struct drm_crtc_state base;
467 * quirks - bitfield with hw state readout quirks
469 * For various reasons the hw state readout code might not be able to
470 * completely faithfully read out the current state. These cases are
471 * tracked with quirk flags so that fastboot and state checker can act
474 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
475 unsigned long quirks;
477 unsigned fb_bits; /* framebuffers to flip */
478 bool update_pipe; /* can a fast modeset be performed? */
480 bool update_wm_pre, update_wm_post; /* watermarks are updated */
481 bool fb_changed; /* fb on any of the planes is changed */
483 /* Pipe source size (ie. panel fitter input size)
484 * All planes will be positioned inside this space,
485 * and get clipped at the edges. */
486 int pipe_src_w, pipe_src_h;
488 /* Whether to set up the PCH/FDI. Note that we never allow sharing
489 * between pch encoders and cpu encoders. */
490 bool has_pch_encoder;
492 /* Are we sending infoframes on the attached port */
495 /* CPU Transcoder for the pipe. Currently this can only differ from the
496 * pipe on Haswell and later (where we have a special eDP transcoder)
497 * and Broxton (where we have special DSI transcoders). */
498 enum transcoder cpu_transcoder;
501 * Use reduced/limited/broadcast rbg range, compressing from the full
502 * range fed into the crtcs.
504 bool limited_color_range;
506 /* DP has a bunch of special case unfortunately, so mark the pipe
510 /* DSI has special cases */
511 bool has_dsi_encoder;
513 /* Whether we should send NULL infoframes. Required for audio. */
516 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
517 * has_dp_encoder is set. */
521 * Enable dithering, used when the selected pipe bpp doesn't match the
526 /* Controls for the clock computation, to override various stages. */
529 /* SDVO TV has a bunch of special case. To make multifunction encoders
530 * work correctly, we need to track this at runtime.*/
534 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
535 * required. This is set in the 2nd loop of calling encoder's
536 * ->compute_config if the first pick doesn't work out.
540 /* Settings for the intel dpll used on pretty much everything but
544 /* Selected dpll when shared or NULL. */
545 struct intel_shared_dpll *shared_dpll;
548 * - PORT_CLK_SEL for DDI ports on HSW/BDW.
549 * - enum skl_dpll on SKL
551 uint32_t ddi_pll_sel;
553 /* Actual register state of the dpll, for shared dpll cross-checking. */
554 struct intel_dpll_hw_state dpll_hw_state;
556 /* DSI PLL registers */
562 struct intel_link_m_n dp_m_n;
564 /* m2_n2 for eDP downclock */
565 struct intel_link_m_n dp_m2_n2;
569 * Frequence the dpll for the port should run at. Differs from the
570 * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
571 * already multiplied by pixel_multiplier.
575 /* Used by SDVO (and if we ever fix it, HDMI). */
576 unsigned pixel_multiplier;
580 /* Panel fitter controls for gen2-gen4 + VLV */
584 u32 lvds_border_bits;
587 /* Panel fitter placement and size for Ironlake+ */
595 /* FDI configuration, only valid if has_pch_encoder is set. */
597 struct intel_link_m_n fdi_m_n;
605 bool dp_encoder_is_mst;
608 struct intel_crtc_scaler_state scaler_state;
610 /* w/a for waiting 2 vblanks during crtc enable */
611 enum pipe hsw_workaround_pipe;
613 /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
616 struct intel_crtc_wm_state wm;
618 /* Gamma mode programmed on the pipe */
622 struct vlv_wm_state {
623 struct vlv_pipe_wm wm[3];
624 struct vlv_sr_wm sr[3];
625 uint8_t num_active_planes;
631 struct intel_mmio_flip {
632 struct work_struct work;
633 struct drm_i915_private *i915;
634 struct drm_i915_gem_request *req;
635 struct intel_crtc *crtc;
636 unsigned int rotation;
640 struct drm_crtc base;
643 u8 lut_r[256], lut_g[256], lut_b[256];
645 * Whether the crtc and the connected output pipeline is active. Implies
646 * that crtc->enabled is set, i.e. the current mode configuration has
647 * some outputs connected to this crtc.
650 unsigned long enabled_power_domains;
652 struct intel_overlay *overlay;
653 struct intel_unpin_work *unpin_work;
655 atomic_t unpin_work_count;
657 /* Display surface base address adjustement for pageflips. Note that on
658 * gen4+ this only adjusts up to a tile, offsets within a tile are
659 * handled in the hw itself (with the TILEOFF register). */
664 uint32_t cursor_addr;
665 uint32_t cursor_cntl;
666 uint32_t cursor_size;
667 uint32_t cursor_base;
669 struct intel_crtc_state *config;
671 /* reset counter value when the last flip was submitted */
672 unsigned int reset_counter;
674 /* Access to these should be protected by dev_priv->irq_lock. */
675 bool cpu_fifo_underrun_disabled;
676 bool pch_fifo_underrun_disabled;
678 /* per-pipe watermark state */
680 /* watermarks currently being used */
682 struct intel_pipe_wm ilk;
683 struct skl_pipe_wm skl;
686 /* allow CxSR on this pipe */
693 unsigned start_vbl_count;
694 ktime_t start_vbl_time;
695 int min_vbl, max_vbl;
699 /* scalers available on this crtc */
702 struct vlv_wm_state wm_state;
705 struct intel_plane_wm_parameters {
706 uint32_t horiz_pixels;
707 uint32_t vert_pixels;
709 * For packed pixel formats:
710 * bytes_per_pixel - holds bytes per pixel
711 * For planar pixel formats:
712 * bytes_per_pixel - holds bytes per pixel for uv-plane
713 * y_bytes_per_pixel - holds bytes per pixel for y-plane
715 uint8_t bytes_per_pixel;
716 uint8_t y_bytes_per_pixel;
720 unsigned int rotation;
725 struct drm_plane base;
730 uint32_t frontbuffer_bit;
732 /* Since we need to change the watermarks before/after
733 * enabling/disabling the planes, we need to store the parameters here
734 * as the other pieces of the struct may not reflect the values we want
735 * for the watermark calculations. Currently only Haswell uses this.
737 struct intel_plane_wm_parameters wm;
740 * NOTE: Do not place new plane state fields here (e.g., when adding
741 * new plane properties). New runtime state should now be placed in
742 * the intel_plane_state structure and accessed via plane_state.
745 void (*update_plane)(struct drm_plane *plane,
746 const struct intel_crtc_state *crtc_state,
747 const struct intel_plane_state *plane_state);
748 void (*disable_plane)(struct drm_plane *plane,
749 struct drm_crtc *crtc);
750 int (*check_plane)(struct drm_plane *plane,
751 struct intel_crtc_state *crtc_state,
752 struct intel_plane_state *state);
755 struct intel_watermark_params {
756 unsigned long fifo_size;
757 unsigned long max_wm;
758 unsigned long default_wm;
759 unsigned long guard_size;
760 unsigned long cacheline_size;
763 struct cxsr_latency {
766 unsigned long fsb_freq;
767 unsigned long mem_freq;
768 unsigned long display_sr;
769 unsigned long display_hpll_disable;
770 unsigned long cursor_sr;
771 unsigned long cursor_hpll_disable;
774 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
775 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
776 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
777 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
778 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
779 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
780 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
781 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
782 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
788 enum drm_dp_dual_mode_type type;
791 bool limited_color_range;
792 bool color_range_auto;
795 enum hdmi_force_audio force_audio;
796 bool rgb_quant_range_selectable;
797 enum hdmi_picture_aspect aspect_ratio;
798 struct intel_connector *attached_connector;
799 void (*write_infoframe)(struct drm_encoder *encoder,
800 enum hdmi_infoframe_type type,
801 const void *frame, ssize_t len);
802 void (*set_infoframes)(struct drm_encoder *encoder,
804 const struct drm_display_mode *adjusted_mode);
805 bool (*infoframe_enabled)(struct drm_encoder *encoder,
806 const struct intel_crtc_state *pipe_config);
809 struct intel_dp_mst_encoder;
810 #define DP_MAX_DOWNSTREAM_PORTS 0x10
814 * When platform provides two set of M_N registers for dp, we can
815 * program them and switch between them incase of DRRS.
816 * But When only one such register is provided, we have to program the
817 * required divider value on that registers itself based on the DRRS state.
819 * M1_N1 : Program dp_m_n on M1_N1 registers
820 * dp_m2_n2 on M2_N2 registers (If supported)
822 * M2_N2 : Program dp_m2_n2 on M1_N1 registers
823 * M2_N2 registers are not supported
827 /* Sets the m1_n1 and m2_n2 */
833 i915_reg_t output_reg;
834 i915_reg_t aux_ch_ctl_reg;
835 i915_reg_t aux_ch_data_reg[5];
842 enum hdmi_force_audio force_audio;
843 bool limited_color_range;
844 bool color_range_auto;
845 uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
846 uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
847 uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
848 uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
849 /* sink rates as reported by DP_SUPPORTED_LINK_RATES */
850 uint8_t num_sink_rates;
851 int sink_rates[DP_MAX_SUPPORTED_RATES];
852 struct drm_dp_aux aux;
853 uint8_t train_set[4];
854 int panel_power_up_delay;
855 int panel_power_down_delay;
856 int panel_power_cycle_delay;
857 int backlight_on_delay;
858 int backlight_off_delay;
859 struct delayed_work panel_vdd_work;
861 unsigned long last_power_on;
862 unsigned long last_backlight_off;
863 ktime_t panel_power_off_time;
865 struct notifier_block edp_notifier;
868 * Pipe whose power sequencer is currently locked into
869 * this port. Only relevant on VLV/CHV.
872 struct edp_power_seq pps_delays;
874 bool can_mst; /* this port supports mst */
876 int active_mst_links;
877 /* connector directly attached - won't be use for modeset in mst world */
878 struct intel_connector *attached_connector;
880 /* mst connector list */
881 struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
882 struct drm_dp_mst_topology_mgr mst_mgr;
884 uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
886 * This function returns the value we have to program the AUX_CTL
887 * register with to kick off an AUX transaction.
889 uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
892 uint32_t aux_clock_divider);
894 /* This is called before a link training is starterd */
895 void (*prepare_link_retrain)(struct intel_dp *intel_dp);
897 bool train_set_valid;
899 /* Displayport compliance testing */
900 unsigned long compliance_test_type;
901 unsigned long compliance_test_data;
902 bool compliance_test_active;
905 struct intel_digital_port {
906 struct intel_encoder base;
910 struct intel_hdmi hdmi;
911 enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
912 bool release_cl2_override;
914 /* for communication with audio component; protected by av_mutex */
915 const struct drm_connector *audio_connector;
918 struct intel_dp_mst_encoder {
919 struct intel_encoder base;
921 struct intel_digital_port *primary;
922 void *port; /* store this opaque as its illegal to dereference it */
925 static inline enum dpio_channel
926 vlv_dport_to_channel(struct intel_digital_port *dport)
928 switch (dport->port) {
939 static inline enum dpio_phy
940 vlv_dport_to_phy(struct intel_digital_port *dport)
942 switch (dport->port) {
953 static inline enum dpio_channel
954 vlv_pipe_to_channel(enum pipe pipe)
967 static inline struct drm_crtc *
968 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
970 struct drm_i915_private *dev_priv = dev->dev_private;
971 return dev_priv->pipe_to_crtc_mapping[pipe];
974 static inline struct drm_crtc *
975 intel_get_crtc_for_plane(struct drm_device *dev, int plane)
977 struct drm_i915_private *dev_priv = dev->dev_private;
978 return dev_priv->plane_to_crtc_mapping[plane];
981 struct intel_unpin_work {
982 struct work_struct work;
983 struct drm_crtc *crtc;
984 struct drm_framebuffer *old_fb;
985 struct drm_i915_gem_object *pending_flip_obj;
986 struct drm_pending_vblank_event *event;
988 #define INTEL_FLIP_INACTIVE 0
989 #define INTEL_FLIP_PENDING 1
990 #define INTEL_FLIP_COMPLETE 2
993 struct drm_i915_gem_request *flip_queued_req;
994 u32 flip_queued_vblank;
995 u32 flip_ready_vblank;
996 bool enable_stall_check;
999 struct intel_load_detect_pipe {
1000 struct drm_atomic_state *restore_state;
1003 static inline struct intel_encoder *
1004 intel_attached_encoder(struct drm_connector *connector)
1006 return to_intel_connector(connector)->encoder;
1009 static inline struct intel_digital_port *
1010 enc_to_dig_port(struct drm_encoder *encoder)
1012 return container_of(encoder, struct intel_digital_port, base.base);
1015 static inline struct intel_dp_mst_encoder *
1016 enc_to_mst(struct drm_encoder *encoder)
1018 return container_of(encoder, struct intel_dp_mst_encoder, base.base);
1021 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
1023 return &enc_to_dig_port(encoder)->dp;
1026 static inline struct intel_digital_port *
1027 dp_to_dig_port(struct intel_dp *intel_dp)
1029 return container_of(intel_dp, struct intel_digital_port, dp);
1032 static inline struct intel_digital_port *
1033 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
1035 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
1039 * Returns the number of planes for this pipe, ie the number of sprites + 1
1040 * (primary plane). This doesn't count the cursor plane then.
1042 static inline unsigned int intel_num_planes(struct intel_crtc *crtc)
1044 return INTEL_INFO(crtc->base.dev)->num_sprites[crtc->pipe] + 1;
1047 /* intel_fifo_underrun.c */
1048 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1049 enum pipe pipe, bool enable);
1050 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1051 enum transcoder pch_transcoder,
1053 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1055 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1056 enum transcoder pch_transcoder);
1057 void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv);
1058 void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv);
1061 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1062 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1063 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1064 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1065 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1066 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
1067 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
1068 u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask);
1069 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
1070 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
1071 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
1074 * We only use drm_irq_uninstall() at unload and VT switch, so
1075 * this is the only thing we need to check.
1077 return dev_priv->pm.irqs_enabled;
1080 int intel_get_crtc_scanline(struct intel_crtc *crtc);
1081 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
1082 unsigned int pipe_mask);
1083 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
1084 unsigned int pipe_mask);
1087 void intel_crt_init(struct drm_device *dev);
1091 void intel_ddi_clk_select(struct intel_encoder *encoder,
1092 const struct intel_crtc_state *pipe_config);
1093 void intel_prepare_ddi_buffer(struct intel_encoder *encoder);
1094 void hsw_fdi_link_train(struct drm_crtc *crtc);
1095 void intel_ddi_init(struct drm_device *dev, enum port port);
1096 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
1097 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
1098 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
1099 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1100 enum transcoder cpu_transcoder);
1101 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
1102 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
1103 bool intel_ddi_pll_select(struct intel_crtc *crtc,
1104 struct intel_crtc_state *crtc_state);
1105 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
1106 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp);
1107 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
1108 void intel_ddi_fdi_disable(struct drm_crtc *crtc);
1109 void intel_ddi_get_config(struct intel_encoder *encoder,
1110 struct intel_crtc_state *pipe_config);
1111 struct intel_encoder *
1112 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state);
1114 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
1115 void intel_ddi_clock_get(struct intel_encoder *encoder,
1116 struct intel_crtc_state *pipe_config);
1117 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
1118 uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
1120 /* intel_frontbuffer.c */
1121 void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
1122 enum fb_op_origin origin);
1123 void intel_frontbuffer_flip_prepare(struct drm_device *dev,
1124 unsigned frontbuffer_bits);
1125 void intel_frontbuffer_flip_complete(struct drm_device *dev,
1126 unsigned frontbuffer_bits);
1127 void intel_frontbuffer_flip(struct drm_device *dev,
1128 unsigned frontbuffer_bits);
1129 unsigned int intel_fb_align_height(struct drm_device *dev,
1130 unsigned int height,
1131 uint32_t pixel_format,
1132 uint64_t fb_format_modifier);
1133 void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire,
1134 enum fb_op_origin origin);
1135 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
1136 uint64_t fb_modifier, uint32_t pixel_format);
1139 void intel_init_audio_hooks(struct drm_i915_private *dev_priv);
1140 void intel_audio_codec_enable(struct intel_encoder *encoder);
1141 void intel_audio_codec_disable(struct intel_encoder *encoder);
1142 void i915_audio_component_init(struct drm_i915_private *dev_priv);
1143 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
1145 /* intel_display.c */
1146 void intel_update_rawclk(struct drm_i915_private *dev_priv);
1147 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
1148 const char *name, u32 reg, int ref_freq);
1149 extern const struct drm_plane_funcs intel_plane_funcs;
1150 void intel_init_display_hooks(struct drm_i915_private *dev_priv);
1151 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
1152 bool intel_has_pending_fb_unpin(struct drm_device *dev);
1153 void intel_mark_busy(struct drm_i915_private *dev_priv);
1154 void intel_mark_idle(struct drm_i915_private *dev_priv);
1155 void intel_crtc_restore_mode(struct drm_crtc *crtc);
1156 int intel_display_suspend(struct drm_device *dev);
1157 void intel_encoder_destroy(struct drm_encoder *encoder);
1158 int intel_connector_init(struct intel_connector *);
1159 struct intel_connector *intel_connector_alloc(void);
1160 bool intel_connector_get_hw_state(struct intel_connector *connector);
1161 void intel_connector_attach_encoder(struct intel_connector *connector,
1162 struct intel_encoder *encoder);
1163 struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
1164 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
1165 struct drm_crtc *crtc);
1166 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
1167 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
1168 struct drm_file *file_priv);
1169 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1171 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type);
1173 intel_wait_for_vblank(struct drm_device *dev, int pipe)
1175 drm_wait_one_vblank(dev, pipe);
1178 intel_wait_for_vblank_if_active(struct drm_device *dev, int pipe)
1180 const struct intel_crtc *crtc =
1181 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
1184 intel_wait_for_vblank(dev, pipe);
1186 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1187 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1188 struct intel_digital_port *dport,
1189 unsigned int expected_mask);
1190 bool intel_get_load_detect_pipe(struct drm_connector *connector,
1191 struct drm_display_mode *mode,
1192 struct intel_load_detect_pipe *old,
1193 struct drm_modeset_acquire_ctx *ctx);
1194 void intel_release_load_detect_pipe(struct drm_connector *connector,
1195 struct intel_load_detect_pipe *old,
1196 struct drm_modeset_acquire_ctx *ctx);
1197 int intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
1198 unsigned int rotation);
1199 void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation);
1200 struct drm_framebuffer *
1201 __intel_framebuffer_create(struct drm_device *dev,
1202 struct drm_mode_fb_cmd2 *mode_cmd,
1203 struct drm_i915_gem_object *obj);
1204 void intel_prepare_page_flip(struct drm_i915_private *dev_priv, int plane);
1205 void intel_finish_page_flip(struct drm_i915_private *dev_priv, int pipe);
1206 void intel_finish_page_flip_plane(struct drm_i915_private *dev_priv, int plane);
1207 void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe);
1208 int intel_prepare_plane_fb(struct drm_plane *plane,
1209 const struct drm_plane_state *new_state);
1210 void intel_cleanup_plane_fb(struct drm_plane *plane,
1211 const struct drm_plane_state *old_state);
1212 int intel_plane_atomic_get_property(struct drm_plane *plane,
1213 const struct drm_plane_state *state,
1214 struct drm_property *property,
1216 int intel_plane_atomic_set_property(struct drm_plane *plane,
1217 struct drm_plane_state *state,
1218 struct drm_property *property,
1220 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
1221 struct drm_plane_state *plane_state);
1223 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
1224 uint64_t fb_modifier, unsigned int cpp);
1227 intel_rotation_90_or_270(unsigned int rotation)
1229 return rotation & (BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270));
1232 void intel_create_rotation_property(struct drm_device *dev,
1233 struct intel_plane *plane);
1235 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1238 int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
1239 const struct dpll *dpll);
1240 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe);
1241 int lpt_get_iclkip(struct drm_i915_private *dev_priv);
1243 /* modesetting asserts */
1244 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1246 void assert_pll(struct drm_i915_private *dev_priv,
1247 enum pipe pipe, bool state);
1248 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1249 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1250 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state);
1251 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1252 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1253 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1254 enum pipe pipe, bool state);
1255 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1256 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1257 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1258 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1259 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1260 u32 intel_compute_tile_offset(int *x, int *y,
1261 const struct drm_framebuffer *fb, int plane,
1263 unsigned int rotation);
1264 void intel_prepare_reset(struct drm_i915_private *dev_priv);
1265 void intel_finish_reset(struct drm_i915_private *dev_priv);
1266 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1267 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1268 void broxton_init_cdclk(struct drm_i915_private *dev_priv);
1269 void broxton_uninit_cdclk(struct drm_i915_private *dev_priv);
1270 bool broxton_cdclk_verify_state(struct drm_i915_private *dev_priv);
1271 void broxton_ddi_phy_init(struct drm_i915_private *dev_priv);
1272 void broxton_ddi_phy_uninit(struct drm_i915_private *dev_priv);
1273 void broxton_ddi_phy_verify_state(struct drm_i915_private *dev_priv);
1274 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv);
1275 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1276 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1277 void gen9_enable_dc5(struct drm_i915_private *dev_priv);
1278 void skl_init_cdclk(struct drm_i915_private *dev_priv);
1279 int skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
1280 void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1281 void skl_enable_dc6(struct drm_i915_private *dev_priv);
1282 void skl_disable_dc6(struct drm_i915_private *dev_priv);
1283 void intel_dp_get_m_n(struct intel_crtc *crtc,
1284 struct intel_crtc_state *pipe_config);
1285 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
1286 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1287 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1288 struct dpll *best_clock);
1289 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
1291 bool intel_crtc_active(struct drm_crtc *crtc);
1292 void hsw_enable_ips(struct intel_crtc *crtc);
1293 void hsw_disable_ips(struct intel_crtc *crtc);
1294 enum intel_display_power_domain
1295 intel_display_port_power_domain(struct intel_encoder *intel_encoder);
1296 enum intel_display_power_domain
1297 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder);
1298 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1299 struct intel_crtc_state *pipe_config);
1301 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1302 int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
1304 u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
1305 struct drm_i915_gem_object *obj,
1306 unsigned int plane);
1308 u32 skl_plane_ctl_format(uint32_t pixel_format);
1309 u32 skl_plane_ctl_tiling(uint64_t fb_modifier);
1310 u32 skl_plane_ctl_rotation(unsigned int rotation);
1313 void intel_csr_ucode_init(struct drm_i915_private *);
1314 void intel_csr_load_program(struct drm_i915_private *);
1315 void intel_csr_ucode_fini(struct drm_i915_private *);
1316 void intel_csr_ucode_suspend(struct drm_i915_private *);
1317 void intel_csr_ucode_resume(struct drm_i915_private *);
1320 void intel_dp_init(struct drm_device *dev, i915_reg_t output_reg, enum port port);
1321 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1322 struct intel_connector *intel_connector);
1323 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1324 const struct intel_crtc_state *pipe_config);
1325 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1326 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1327 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1328 void intel_dp_encoder_reset(struct drm_encoder *encoder);
1329 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
1330 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1331 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
1332 bool intel_dp_compute_config(struct intel_encoder *encoder,
1333 struct intel_crtc_state *pipe_config);
1334 bool intel_dp_is_edp(struct drm_device *dev, enum port port);
1335 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1337 void intel_edp_backlight_on(struct intel_dp *intel_dp);
1338 void intel_edp_backlight_off(struct intel_dp *intel_dp);
1339 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1340 void intel_edp_panel_on(struct intel_dp *intel_dp);
1341 void intel_edp_panel_off(struct intel_dp *intel_dp);
1342 void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
1343 void intel_dp_mst_suspend(struct drm_device *dev);
1344 void intel_dp_mst_resume(struct drm_device *dev);
1345 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1346 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1347 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1348 void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv);
1349 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1350 void intel_plane_destroy(struct drm_plane *plane);
1351 void intel_edp_drrs_enable(struct intel_dp *intel_dp);
1352 void intel_edp_drrs_disable(struct intel_dp *intel_dp);
1353 void intel_edp_drrs_invalidate(struct drm_device *dev,
1354 unsigned frontbuffer_bits);
1355 void intel_edp_drrs_flush(struct drm_device *dev, unsigned frontbuffer_bits);
1356 bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
1357 struct intel_digital_port *port);
1360 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
1361 uint8_t dp_train_pat);
1363 intel_dp_set_signal_levels(struct intel_dp *intel_dp);
1364 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
1366 intel_dp_voltage_max(struct intel_dp *intel_dp);
1368 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing);
1369 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1370 uint8_t *link_bw, uint8_t *rate_select);
1371 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
1373 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]);
1375 static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
1377 return ~((1 << lane_count) - 1) & 0xf;
1380 /* intel_dp_aux_backlight.c */
1381 int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector);
1383 /* intel_dp_mst.c */
1384 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1385 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1387 void intel_dsi_init(struct drm_device *dev);
1391 void intel_dvo_init(struct drm_device *dev);
1394 /* legacy fbdev emulation in intel_fbdev.c */
1395 #ifdef CONFIG_DRM_FBDEV_EMULATION
1396 extern int intel_fbdev_init(struct drm_device *dev);
1397 extern void intel_fbdev_initial_config_async(struct drm_device *dev);
1398 extern void intel_fbdev_fini(struct drm_device *dev);
1399 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1400 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1401 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1403 static inline int intel_fbdev_init(struct drm_device *dev)
1408 static inline void intel_fbdev_initial_config_async(struct drm_device *dev)
1412 static inline void intel_fbdev_fini(struct drm_device *dev)
1416 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1420 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1426 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1427 struct drm_atomic_state *state);
1428 bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
1429 void intel_fbc_pre_update(struct intel_crtc *crtc);
1430 void intel_fbc_post_update(struct intel_crtc *crtc);
1431 void intel_fbc_init(struct drm_i915_private *dev_priv);
1432 void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv);
1433 void intel_fbc_enable(struct intel_crtc *crtc);
1434 void intel_fbc_disable(struct intel_crtc *crtc);
1435 void intel_fbc_global_disable(struct drm_i915_private *dev_priv);
1436 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1437 unsigned int frontbuffer_bits,
1438 enum fb_op_origin origin);
1439 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1440 unsigned int frontbuffer_bits, enum fb_op_origin origin);
1441 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
1444 void intel_hdmi_init(struct drm_device *dev, i915_reg_t hdmi_reg, enum port port);
1445 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1446 struct intel_connector *intel_connector);
1447 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1448 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1449 struct intel_crtc_state *pipe_config);
1450 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable);
1454 void intel_lvds_init(struct drm_device *dev);
1455 bool intel_is_dual_link_lvds(struct drm_device *dev);
1459 int intel_connector_update_modes(struct drm_connector *connector,
1461 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1462 void intel_attach_force_audio_property(struct drm_connector *connector);
1463 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1464 void intel_attach_aspect_ratio_property(struct drm_connector *connector);
1467 /* intel_overlay.c */
1468 void intel_setup_overlay(struct drm_i915_private *dev_priv);
1469 void intel_cleanup_overlay(struct drm_i915_private *dev_priv);
1470 int intel_overlay_switch_off(struct intel_overlay *overlay);
1471 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
1472 struct drm_file *file_priv);
1473 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
1474 struct drm_file *file_priv);
1475 void intel_overlay_reset(struct drm_i915_private *dev_priv);
1479 int intel_panel_init(struct intel_panel *panel,
1480 struct drm_display_mode *fixed_mode,
1481 struct drm_display_mode *downclock_mode);
1482 void intel_panel_fini(struct intel_panel *panel);
1483 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1484 struct drm_display_mode *adjusted_mode);
1485 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1486 struct intel_crtc_state *pipe_config,
1488 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1489 struct intel_crtc_state *pipe_config,
1491 void intel_panel_set_backlight_acpi(struct intel_connector *connector,
1492 u32 level, u32 max);
1493 int intel_panel_setup_backlight(struct drm_connector *connector, enum pipe pipe);
1494 void intel_panel_enable_backlight(struct intel_connector *connector);
1495 void intel_panel_disable_backlight(struct intel_connector *connector);
1496 void intel_panel_destroy_backlight(struct drm_connector *connector);
1497 enum drm_connector_status intel_panel_detect(struct drm_device *dev);
1498 extern struct drm_display_mode *intel_find_panel_downclock(
1499 struct drm_device *dev,
1500 struct drm_display_mode *fixed_mode,
1501 struct drm_connector *connector);
1502 void intel_backlight_register(struct drm_device *dev);
1503 void intel_backlight_unregister(struct drm_device *dev);
1507 void intel_psr_enable(struct intel_dp *intel_dp);
1508 void intel_psr_disable(struct intel_dp *intel_dp);
1509 void intel_psr_invalidate(struct drm_device *dev,
1510 unsigned frontbuffer_bits);
1511 void intel_psr_flush(struct drm_device *dev,
1512 unsigned frontbuffer_bits,
1513 enum fb_op_origin origin);
1514 void intel_psr_init(struct drm_device *dev);
1515 void intel_psr_single_frame_update(struct drm_device *dev,
1516 unsigned frontbuffer_bits);
1518 /* intel_runtime_pm.c */
1519 int intel_power_domains_init(struct drm_i915_private *);
1520 void intel_power_domains_fini(struct drm_i915_private *);
1521 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
1522 void intel_power_domains_suspend(struct drm_i915_private *dev_priv);
1523 void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
1524 void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
1525 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1527 intel_display_power_domain_str(enum intel_display_power_domain domain);
1529 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1530 enum intel_display_power_domain domain);
1531 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1532 enum intel_display_power_domain domain);
1533 void intel_display_power_get(struct drm_i915_private *dev_priv,
1534 enum intel_display_power_domain domain);
1535 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
1536 enum intel_display_power_domain domain);
1537 void intel_display_power_put(struct drm_i915_private *dev_priv,
1538 enum intel_display_power_domain domain);
1541 assert_rpm_device_not_suspended(struct drm_i915_private *dev_priv)
1543 WARN_ONCE(dev_priv->pm.suspended,
1544 "Device suspended during HW access\n");
1548 assert_rpm_wakelock_held(struct drm_i915_private *dev_priv)
1550 assert_rpm_device_not_suspended(dev_priv);
1551 /* FIXME: Needs to be converted back to WARN_ONCE, but currently causes
1552 * too much noise. */
1553 if (!atomic_read(&dev_priv->pm.wakeref_count))
1554 DRM_DEBUG_DRIVER("RPM wakelock ref not held during HW access");
1558 assert_rpm_atomic_begin(struct drm_i915_private *dev_priv)
1560 int seq = atomic_read(&dev_priv->pm.atomic_seq);
1562 assert_rpm_wakelock_held(dev_priv);
1568 assert_rpm_atomic_end(struct drm_i915_private *dev_priv, int begin_seq)
1570 WARN_ONCE(atomic_read(&dev_priv->pm.atomic_seq) != begin_seq,
1571 "HW access outside of RPM atomic section\n");
1575 * disable_rpm_wakeref_asserts - disable the RPM assert checks
1576 * @dev_priv: i915 device instance
1578 * This function disable asserts that check if we hold an RPM wakelock
1579 * reference, while keeping the device-not-suspended checks still enabled.
1580 * It's meant to be used only in special circumstances where our rule about
1581 * the wakelock refcount wrt. the device power state doesn't hold. According
1582 * to this rule at any point where we access the HW or want to keep the HW in
1583 * an active state we must hold an RPM wakelock reference acquired via one of
1584 * the intel_runtime_pm_get() helpers. Currently there are a few special spots
1585 * where this rule doesn't hold: the IRQ and suspend/resume handlers, the
1586 * forcewake release timer, and the GPU RPS and hangcheck works. All other
1587 * users should avoid using this function.
1589 * Any calls to this function must have a symmetric call to
1590 * enable_rpm_wakeref_asserts().
1593 disable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1595 atomic_inc(&dev_priv->pm.wakeref_count);
1599 * enable_rpm_wakeref_asserts - re-enable the RPM assert checks
1600 * @dev_priv: i915 device instance
1602 * This function re-enables the RPM assert checks after disabling them with
1603 * disable_rpm_wakeref_asserts. It's meant to be used only in special
1604 * circumstances otherwise its use should be avoided.
1606 * Any calls to this function must have a symmetric call to
1607 * disable_rpm_wakeref_asserts().
1610 enable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1612 atomic_dec(&dev_priv->pm.wakeref_count);
1615 /* TODO: convert users of these to rely instead on proper RPM refcounting */
1616 #define DISABLE_RPM_WAKEREF_ASSERTS(dev_priv) \
1617 disable_rpm_wakeref_asserts(dev_priv)
1619 #define ENABLE_RPM_WAKEREF_ASSERTS(dev_priv) \
1620 enable_rpm_wakeref_asserts(dev_priv)
1622 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1623 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv);
1624 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1625 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1627 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
1629 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1630 bool override, unsigned int mask);
1631 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1632 enum dpio_channel ch, bool override);
1636 void intel_init_clock_gating(struct drm_device *dev);
1637 void intel_suspend_hw(struct drm_device *dev);
1638 int ilk_wm_max_level(const struct drm_device *dev);
1639 void intel_update_watermarks(struct drm_crtc *crtc);
1640 void intel_init_pm(struct drm_device *dev);
1641 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
1642 void intel_pm_setup(struct drm_device *dev);
1643 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1644 void intel_gpu_ips_teardown(void);
1645 void intel_init_gt_powersave(struct drm_i915_private *dev_priv);
1646 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv);
1647 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv);
1648 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv);
1649 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv);
1650 void intel_reset_gt_powersave(struct drm_i915_private *dev_priv);
1651 void gen6_update_ring_freq(struct drm_i915_private *dev_priv);
1652 void gen6_rps_busy(struct drm_i915_private *dev_priv);
1653 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
1654 void gen6_rps_idle(struct drm_i915_private *dev_priv);
1655 void gen6_rps_boost(struct drm_i915_private *dev_priv,
1656 struct intel_rps_client *rps,
1657 unsigned long submitted);
1658 void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req);
1659 void vlv_wm_get_hw_state(struct drm_device *dev);
1660 void ilk_wm_get_hw_state(struct drm_device *dev);
1661 void skl_wm_get_hw_state(struct drm_device *dev);
1662 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
1663 struct skl_ddb_allocation *ddb /* out */);
1664 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config);
1665 bool ilk_disable_lp_wm(struct drm_device *dev);
1666 int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6);
1667 static inline int intel_enable_rc6(void)
1669 return i915.enable_rc6;
1673 bool intel_sdvo_init(struct drm_device *dev,
1674 i915_reg_t reg, enum port port);
1677 /* intel_sprite.c */
1678 int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
1679 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1680 struct drm_file *file_priv);
1681 void intel_pipe_update_start(struct intel_crtc *crtc);
1682 void intel_pipe_update_end(struct intel_crtc *crtc);
1685 void intel_tv_init(struct drm_device *dev);
1687 /* intel_atomic.c */
1688 int intel_connector_atomic_get_property(struct drm_connector *connector,
1689 const struct drm_connector_state *state,
1690 struct drm_property *property,
1692 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
1693 void intel_crtc_destroy_state(struct drm_crtc *crtc,
1694 struct drm_crtc_state *state);
1695 struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
1696 void intel_atomic_state_clear(struct drm_atomic_state *);
1697 struct intel_shared_dpll_config *
1698 intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s);
1700 static inline struct intel_crtc_state *
1701 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
1702 struct intel_crtc *crtc)
1704 struct drm_crtc_state *crtc_state;
1705 crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
1706 if (IS_ERR(crtc_state))
1707 return ERR_CAST(crtc_state);
1709 return to_intel_crtc_state(crtc_state);
1712 static inline struct intel_plane_state *
1713 intel_atomic_get_existing_plane_state(struct drm_atomic_state *state,
1714 struct intel_plane *plane)
1716 struct drm_plane_state *plane_state;
1718 plane_state = drm_atomic_get_existing_plane_state(state, &plane->base);
1720 return to_intel_plane_state(plane_state);
1723 int intel_atomic_setup_scalers(struct drm_device *dev,
1724 struct intel_crtc *intel_crtc,
1725 struct intel_crtc_state *crtc_state);
1727 /* intel_atomic_plane.c */
1728 struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
1729 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
1730 void intel_plane_destroy_state(struct drm_plane *plane,
1731 struct drm_plane_state *state);
1732 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
1735 void intel_color_init(struct drm_crtc *crtc);
1736 int intel_color_check(struct drm_crtc *crtc, struct drm_crtc_state *state);
1737 void intel_color_set_csc(struct drm_crtc_state *crtc_state);
1738 void intel_color_load_luts(struct drm_crtc_state *crtc_state);
1740 #endif /* __INTEL_DRV_H__ */