drivers/gpu/drm/i915/intel_drv.h

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright (c) 2007-2008 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23  * IN THE SOFTWARE.
  24  */
  25 #ifndef __INTEL_DRV_H__
  26 #define __INTEL_DRV_H__
  27
  28 #include <linux/async.h>
  29 #include <linux/i2c.h>
  30 #include <linux/hdmi.h>
  31 #include <drm/i915_drm.h>
  32 #include "i915_drv.h"
  33 #include <drm/drm_crtc.h>
  34 #include <drm/drm_crtc_helper.h>
  35 #include <drm/drm_fb_helper.h>
  36 #include <drm/drm_dp_dual_mode_helper.h>
  37 #include <drm/drm_dp_mst_helper.h>
  38 #include <drm/drm_rect.h>
  39 #include <drm/drm_atomic.h>
  40
  41 /**
  42  * _wait_for - magic (register) wait macro
  43  *
  44  * Does the right thing for modeset paths when run under kdgb or similar atomic
  45  * contexts. Note that it's important that we check the condition again after
  46  * having timed out, since the timeout could be due to preemption or similar and
  47  * we've never had a chance to check the condition before the timeout.
  48  *
  49  * TODO: When modesetting has fully transitioned to atomic, the below
  50  * drm_can_sleep() can be removed and in_atomic()/!in_atomic() asserts
  51  * added.
  52  */
  53 #define _wait_for(COND, US, W) ({ \
  54         unsigned long timeout__ = jiffies + usecs_to_jiffies(US) + 1;   \
  55         int ret__ = 0;                                                  \
  56         while (!(COND)) {                                               \
  57                 if (time_after(jiffies, timeout__)) {                   \
  58                         if (!(COND))                                    \
  59                                 ret__ = -ETIMEDOUT;                     \
  60                         break;                                          \
  61                 }                                                       \
  62                 if ((W) && drm_can_sleep()) {                           \
  63                         usleep_range((W), (W)*2);                       \
  64                 } else {                                                \
  65                         cpu_relax();                                    \
  66                 }                                                       \
  67         }                                                               \
  68         ret__;                                                          \
  69 })
  70
  71 #define wait_for(COND, MS)              _wait_for((COND), (MS) * 1000, 1000)
  72
  73 /* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */
  74 #if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT)
  75 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) WARN_ON_ONCE((ATOMIC) && !in_atomic())
  76 #else
  77 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) do { } while (0)
  78 #endif
  79
  80 #define _wait_for_atomic(COND, US, ATOMIC) \
  81 ({ \
  82         int cpu, ret, timeout = (US) * 1000; \
  83         u64 base; \
  84         _WAIT_FOR_ATOMIC_CHECK(ATOMIC); \
  85         BUILD_BUG_ON((US) > 50000); \
  86         if (!(ATOMIC)) { \
  87                 preempt_disable(); \
  88                 cpu = smp_processor_id(); \
  89         } \
  90         base = local_clock(); \
  91         for (;;) { \
  92                 u64 now = local_clock(); \
  93                 if (!(ATOMIC)) \
  94                         preempt_enable(); \
  95                 if (COND) { \
  96                         ret = 0; \
  97                         break; \
  98                 } \
  99                 if (now - base >= timeout) { \
 100                         ret = -ETIMEDOUT; \
 101                         break; \
 102                 } \
 103                 cpu_relax(); \
 104                 if (!(ATOMIC)) { \
 105                         preempt_disable(); \
 106                         if (unlikely(cpu != smp_processor_id())) { \
 107                                 timeout -= now - base; \
 108                                 cpu = smp_processor_id(); \
 109                                 base = local_clock(); \
 110                         } \
 111                 } \
 112         } \
 113         ret; \
 114 })
 115
 116 #define wait_for_us(COND, US) \
 117 ({ \
 118         int ret__; \
 119         BUILD_BUG_ON(!__builtin_constant_p(US)); \
 120         if ((US) > 10) \
 121                 ret__ = _wait_for((COND), (US), 10); \
 122         else \
 123                 ret__ = _wait_for_atomic((COND), (US), 0); \
 124         ret__; \
 125 })
 126
 127 #define wait_for_atomic(COND, MS)       _wait_for_atomic((COND), (MS) * 1000, 1)
 128 #define wait_for_atomic_us(COND, US)    _wait_for_atomic((COND), (US), 1)
 129
 130 #define KHz(x) (1000 * (x))
 131 #define MHz(x) KHz(1000 * (x))
 132
 133 /*
 134  * Display related stuff
 135  */
 136
 137 /* store information about an Ixxx DVO */
 138 /* The i830->i865 use multiple DVOs with multiple i2cs */
 139 /* the i915, i945 have a single sDVO i2c bus - which is different */
 140 #define MAX_OUTPUTS 6
 141 /* maximum connectors per crtcs in the mode set */
 142
 143 /* Maximum cursor sizes */
 144 #define GEN2_CURSOR_WIDTH 64
 145 #define GEN2_CURSOR_HEIGHT 64
 146 #define MAX_CURSOR_WIDTH 256
 147 #define MAX_CURSOR_HEIGHT 256
 148
 149 #define INTEL_I2C_BUS_DVO 1
 150 #define INTEL_I2C_BUS_SDVO 2
 151
 152 /* these are outputs from the chip - integrated only
 153    external chips are via DVO or SDVO output */
 154 enum intel_output_type {
 155         INTEL_OUTPUT_UNUSED = 0,
 156         INTEL_OUTPUT_ANALOG = 1,
 157         INTEL_OUTPUT_DVO = 2,
 158         INTEL_OUTPUT_SDVO = 3,
 159         INTEL_OUTPUT_LVDS = 4,
 160         INTEL_OUTPUT_TVOUT = 5,
 161         INTEL_OUTPUT_HDMI = 6,
 162         INTEL_OUTPUT_DP = 7,
 163         INTEL_OUTPUT_EDP = 8,
 164         INTEL_OUTPUT_DSI = 9,
 165         INTEL_OUTPUT_UNKNOWN = 10,
 166         INTEL_OUTPUT_DP_MST = 11,
 167 };
 168
 169 #define INTEL_DVO_CHIP_NONE 0
 170 #define INTEL_DVO_CHIP_LVDS 1
 171 #define INTEL_DVO_CHIP_TMDS 2
 172 #define INTEL_DVO_CHIP_TVOUT 4
 173
 174 #define INTEL_DSI_VIDEO_MODE    0
 175 #define INTEL_DSI_COMMAND_MODE  1
 176
 177 struct intel_framebuffer {
 178         struct drm_framebuffer base;
 179         struct drm_i915_gem_object *obj;
 180         struct intel_rotation_info rot_info;
 181 };
 182
 183 struct intel_fbdev {
 184         struct drm_fb_helper helper;
 185         struct intel_framebuffer *fb;
 186         async_cookie_t cookie;
 187         int preferred_bpp;
 188 };
 189
 190 struct intel_encoder {
 191         struct drm_encoder base;
 192
 193         enum intel_output_type type;
 194         unsigned int cloneable;
 195         void (*hot_plug)(struct intel_encoder *);
 196         bool (*compute_config)(struct intel_encoder *,
 197                                struct intel_crtc_state *);
 198         void (*pre_pll_enable)(struct intel_encoder *);
 199         void (*pre_enable)(struct intel_encoder *);
 200         void (*enable)(struct intel_encoder *);
 201         void (*mode_set)(struct intel_encoder *intel_encoder);
 202         void (*disable)(struct intel_encoder *);
 203         void (*post_disable)(struct intel_encoder *);
 204         void (*post_pll_disable)(struct intel_encoder *);
 205         /* Read out the current hw state of this connector, returning true if
 206          * the encoder is active. If the encoder is enabled it also set the pipe
 207          * it is connected to in the pipe parameter. */
 208         bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
 209         /* Reconstructs the equivalent mode flags for the current hardware
 210          * state. This must be called _after_ display->get_pipe_config has
 211          * pre-filled the pipe config. Note that intel_encoder->base.crtc must
 212          * be set correctly before calling this function. */
 213         void (*get_config)(struct intel_encoder *,
 214                            struct intel_crtc_state *pipe_config);
 215         /*
 216          * Called during system suspend after all pending requests for the
 217          * encoder are flushed (for example for DP AUX transactions) and
 218          * device interrupts are disabled.
 219          */
 220         void (*suspend)(struct intel_encoder *);
 221         int crtc_mask;
 222         enum hpd_pin hpd_pin;
 223 };
 224
 225 struct intel_panel {
 226         struct drm_display_mode *fixed_mode;
 227         struct drm_display_mode *downclock_mode;
 228         int fitting_mode;
 229
 230         /* backlight */
 231         struct {
 232                 bool present;
 233                 u32 level;
 234                 u32 min;
 235                 u32 max;
 236                 bool enabled;
 237                 bool combination_mode;  /* gen 2/4 only */
 238                 bool active_low_pwm;
 239
 240                 /* PWM chip */
 241                 bool util_pin_active_low;       /* bxt+ */
 242                 u8 controller;          /* bxt+ only */
 243                 struct pwm_device *pwm;
 244
 245                 struct backlight_device *device;
 246
 247                 /* Connector and platform specific backlight functions */
 248                 int (*setup)(struct intel_connector *connector, enum pipe pipe);
 249                 uint32_t (*get)(struct intel_connector *connector);
 250                 void (*set)(struct intel_connector *connector, uint32_t level);
 251                 void (*disable)(struct intel_connector *connector);
 252                 void (*enable)(struct intel_connector *connector);
 253                 uint32_t (*hz_to_pwm)(struct intel_connector *connector,
 254                                       uint32_t hz);
 255                 void (*power)(struct intel_connector *, bool enable);
 256         } backlight;
 257 };
 258
 259 struct intel_connector {
 260         struct drm_connector base;
 261         /*
 262          * The fixed encoder this connector is connected to.
 263          */
 264         struct intel_encoder *encoder;
 265
 266         /* Reads out the current hw, returning true if the connector is enabled
 267          * and active (i.e. dpms ON state). */
 268         bool (*get_hw_state)(struct intel_connector *);
 269
 270         /* Panel info for eDP and LVDS */
 271         struct intel_panel panel;
 272
 273         /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
 274         struct edid *edid;
 275         struct edid *detect_edid;
 276
 277         /* since POLL and HPD connectors may use the same HPD line keep the native
 278            state of connector->polled in case hotplug storm detection changes it */
 279         u8 polled;
 280
 281         void *port; /* store this opaque as its illegal to dereference it */
 282
 283         struct intel_dp *mst_port;
 284 };
 285
 286 struct dpll {
 287         /* given values */
 288         int n;
 289         int m1, m2;
 290         int p1, p2;
 291         /* derived values */
 292         int     dot;
 293         int     vco;
 294         int     m;
 295         int     p;
 296 };
 297
 298 struct intel_atomic_state {
 299         struct drm_atomic_state base;
 300
 301         unsigned int cdclk;
 302
 303         /*
 304          * Calculated device cdclk, can be different from cdclk
 305          * only when all crtc's are DPMS off.
 306          */
 307         unsigned int dev_cdclk;
 308
 309         bool dpll_set, modeset;
 310
 311         /*
 312          * Does this transaction change the pipes that are active?  This mask
 313          * tracks which CRTC's have changed their active state at the end of
 314          * the transaction (not counting the temporary disable during modesets).
 315          * This mask should only be non-zero when intel_state->modeset is true,
 316          * but the converse is not necessarily true; simply changing a mode may
 317          * not flip the final active status of any CRTC's
 318          */
 319         unsigned int active_pipe_changes;
 320
 321         unsigned int active_crtcs;
 322         unsigned int min_pixclk[I915_MAX_PIPES];
 323
 324         /* SKL/KBL Only */
 325         unsigned int cdclk_pll_vco;
 326
 327         struct intel_shared_dpll_config shared_dpll[I915_NUM_PLLS];
 328
 329         /*
 330          * Current watermarks can't be trusted during hardware readout, so
 331          * don't bother calculating intermediate watermarks.
 332          */
 333         bool skip_intermediate_wm;
 334
 335         /* Gen9+ only */
 336         struct skl_wm_values wm_results;
 337 };
 338
 339 struct intel_plane_state {
 340         struct drm_plane_state base;
 341         struct drm_rect clip;
 342
 343         /*
 344          * scaler_id
 345          *    = -1 : not using a scaler
 346          *    >=  0 : using a scalers
 347          *
 348          * plane requiring a scaler:
 349          *   - During check_plane, its bit is set in
 350          *     crtc_state->scaler_state.scaler_users by calling helper function
 351          *     update_scaler_plane.
 352          *   - scaler_id indicates the scaler it got assigned.
 353          *
 354          * plane doesn't require a scaler:
 355          *   - this can happen when scaling is no more required or plane simply
 356          *     got disabled.
 357          *   - During check_plane, corresponding bit is reset in
 358          *     crtc_state->scaler_state.scaler_users by calling helper function
 359          *     update_scaler_plane.
 360          */
 361         int scaler_id;
 362
 363         struct drm_intel_sprite_colorkey ckey;
 364
 365         /* async flip related structures */
 366         struct drm_i915_gem_request *wait_req;
 367 };
 368
 369 struct intel_initial_plane_config {
 370         struct intel_framebuffer *fb;
 371         unsigned int tiling;
 372         int size;
 373         u32 base;
 374 };
 375
 376 #define SKL_MIN_SRC_W 8
 377 #define SKL_MAX_SRC_W 4096
 378 #define SKL_MIN_SRC_H 8
 379 #define SKL_MAX_SRC_H 4096
 380 #define SKL_MIN_DST_W 8
 381 #define SKL_MAX_DST_W 4096
 382 #define SKL_MIN_DST_H 8
 383 #define SKL_MAX_DST_H 4096
 384
 385 struct intel_scaler {
 386         int in_use;
 387         uint32_t mode;
 388 };
 389
 390 struct intel_crtc_scaler_state {
 391 #define SKL_NUM_SCALERS 2
 392         struct intel_scaler scalers[SKL_NUM_SCALERS];
 393
 394         /*
 395          * scaler_users: keeps track of users requesting scalers on this crtc.
 396          *
 397          *     If a bit is set, a user is using a scaler.
 398          *     Here user can be a plane or crtc as defined below:
 399          *       bits 0-30 - plane (bit position is index from drm_plane_index)
 400          *       bit 31    - crtc
 401          *
 402          * Instead of creating a new index to cover planes and crtc, using
 403          * existing drm_plane_index for planes which is well less than 31
 404          * planes and bit 31 for crtc. This should be fine to cover all
 405          * our platforms.
 406          *
 407          * intel_atomic_setup_scalers will setup available scalers to users
 408          * requesting scalers. It will gracefully fail if request exceeds
 409          * avilability.
 410          */
 411 #define SKL_CRTC_INDEX 31
 412         unsigned scaler_users;
 413
 414         /* scaler used by crtc for panel fitting purpose */
 415         int scaler_id;
 416 };
 417
 418 /* drm_mode->private_flags */
 419 #define I915_MODE_FLAG_INHERITED 1
 420
 421 struct intel_pipe_wm {
 422         struct intel_wm_level wm[5];
 423         struct intel_wm_level raw_wm[5];
 424         uint32_t linetime;
 425         bool fbc_wm_enabled;
 426         bool pipe_enabled;
 427         bool sprites_enabled;
 428         bool sprites_scaled;
 429 };
 430
 431 struct skl_pipe_wm {
 432         struct skl_wm_level wm[8];
 433         struct skl_wm_level trans_wm;
 434         uint32_t linetime;
 435 };
 436
 437 struct intel_crtc_wm_state {
 438         union {
 439                 struct {
 440                         /*
 441                          * Intermediate watermarks; these can be
 442                          * programmed immediately since they satisfy
 443                          * both the current configuration we're
 444                          * switching away from and the new
 445                          * configuration we're switching to.
 446                          */
 447                         struct intel_pipe_wm intermediate;
 448
 449                         /*
 450                          * Optimal watermarks, programmed post-vblank
 451                          * when this state is committed.
 452                          */
 453                         struct intel_pipe_wm optimal;
 454                 } ilk;
 455
 456                 struct {
 457                         /* gen9+ only needs 1-step wm programming */
 458                         struct skl_pipe_wm optimal;
 459
 460                         /* cached plane data rate */
 461                         unsigned plane_data_rate[I915_MAX_PLANES];
 462                         unsigned plane_y_data_rate[I915_MAX_PLANES];
 463
 464                         /* minimum block allocation */
 465                         uint16_t minimum_blocks[I915_MAX_PLANES];
 466                         uint16_t minimum_y_blocks[I915_MAX_PLANES];
 467                 } skl;
 468         };
 469
 470         /*
 471          * Platforms with two-step watermark programming will need to
 472          * update watermark programming post-vblank to switch from the
 473          * safe intermediate watermarks to the optimal final
 474          * watermarks.
 475          */
 476         bool need_postvbl_update;
 477 };
 478
 479 struct intel_crtc_state {
 480         struct drm_crtc_state base;
 481
 482         /**
 483          * quirks - bitfield with hw state readout quirks
 484          *
 485          * For various reasons the hw state readout code might not be able to
 486          * completely faithfully read out the current state. These cases are
 487          * tracked with quirk flags so that fastboot and state checker can act
 488          * accordingly.
 489          */
 490 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS       (1<<0) /* unreliable sync mode.flags */
 491         unsigned long quirks;
 492
 493         unsigned fb_bits; /* framebuffers to flip */
 494         bool update_pipe; /* can a fast modeset be performed? */
 495         bool disable_cxsr;
 496         bool update_wm_pre, update_wm_post; /* watermarks are updated */
 497         bool fb_changed; /* fb on any of the planes is changed */
 498
 499         /* Pipe source size (ie. panel fitter input size)
 500          * All planes will be positioned inside this space,
 501          * and get clipped at the edges. */
 502         int pipe_src_w, pipe_src_h;
 503
 504         /* Whether to set up the PCH/FDI. Note that we never allow sharing
 505          * between pch encoders and cpu encoders. */
 506         bool has_pch_encoder;
 507
 508         /* Are we sending infoframes on the attached port */
 509         bool has_infoframe;
 510
 511         /* CPU Transcoder for the pipe. Currently this can only differ from the
 512          * pipe on Haswell and later (where we have a special eDP transcoder)
 513          * and Broxton (where we have special DSI transcoders). */
 514         enum transcoder cpu_transcoder;
 515
 516         /*
 517          * Use reduced/limited/broadcast rbg range, compressing from the full
 518          * range fed into the crtcs.
 519          */
 520         bool limited_color_range;
 521
 522         /* Bitmask of encoder types (enum intel_output_type)
 523          * driven by the pipe.
 524          */
 525         unsigned int output_types;
 526
 527         /* Whether we should send NULL infoframes. Required for audio. */
 528         bool has_hdmi_sink;
 529
 530         /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
 531          * has_dp_encoder is set. */
 532         bool has_audio;
 533
 534         /*
 535          * Enable dithering, used when the selected pipe bpp doesn't match the
 536          * plane bpp.
 537          */
 538         bool dither;
 539
 540         /* Controls for the clock computation, to override various stages. */
 541         bool clock_set;
 542
 543         /* SDVO TV has a bunch of special case. To make multifunction encoders
 544          * work correctly, we need to track this at runtime.*/
 545         bool sdvo_tv_clock;
 546
 547         /*
 548          * crtc bandwidth limit, don't increase pipe bpp or clock if not really
 549          * required. This is set in the 2nd loop of calling encoder's
 550          * ->compute_config if the first pick doesn't work out.
 551          */
 552         bool bw_constrained;
 553
 554         /* Settings for the intel dpll used on pretty much everything but
 555          * haswell. */
 556         struct dpll dpll;
 557
 558         /* Selected dpll when shared or NULL. */
 559         struct intel_shared_dpll *shared_dpll;
 560
 561         /*
 562          * - PORT_CLK_SEL for DDI ports on HSW/BDW.
 563          * - enum skl_dpll on SKL
 564          */
 565         uint32_t ddi_pll_sel;
 566
 567         /* Actual register state of the dpll, for shared dpll cross-checking. */
 568         struct intel_dpll_hw_state dpll_hw_state;
 569
 570         /* DSI PLL registers */
 571         struct {
 572                 u32 ctrl, div;
 573         } dsi_pll;
 574
 575         int pipe_bpp;
 576         struct intel_link_m_n dp_m_n;
 577
 578         /* m2_n2 for eDP downclock */
 579         struct intel_link_m_n dp_m2_n2;
 580         bool has_drrs;
 581
 582         /*
 583          * Frequence the dpll for the port should run at. Differs from the
 584          * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
 585          * already multiplied by pixel_multiplier.
 586          */
 587         int port_clock;
 588
 589         /* Used by SDVO (and if we ever fix it, HDMI). */
 590         unsigned pixel_multiplier;
 591
 592         uint8_t lane_count;
 593
 594         /*
 595          * Used by platforms having DP/HDMI PHY with programmable lane
 596          * latency optimization.
 597          */
 598         uint8_t lane_lat_optim_mask;
 599
 600         /* Panel fitter controls for gen2-gen4 + VLV */
 601         struct {
 602                 u32 control;
 603                 u32 pgm_ratios;
 604                 u32 lvds_border_bits;
 605         } gmch_pfit;
 606
 607         /* Panel fitter placement and size for Ironlake+ */
 608         struct {
 609                 u32 pos;
 610                 u32 size;
 611                 bool enabled;
 612                 bool force_thru;
 613         } pch_pfit;
 614
 615         /* FDI configuration, only valid if has_pch_encoder is set. */
 616         int fdi_lanes;
 617         struct intel_link_m_n fdi_m_n;
 618
 619         bool ips_enabled;
 620
 621         bool enable_fbc;
 622
 623         bool double_wide;
 624
 625         bool dp_encoder_is_mst;
 626         int pbn;
 627
 628         struct intel_crtc_scaler_state scaler_state;
 629
 630         /* w/a for waiting 2 vblanks during crtc enable */
 631         enum pipe hsw_workaround_pipe;
 632
 633         /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
 634         bool disable_lp_wm;
 635
 636         struct intel_crtc_wm_state wm;
 637
 638         /* Gamma mode programmed on the pipe */
 639         uint32_t gamma_mode;
 640 };
 641
 642 struct vlv_wm_state {
 643         struct vlv_pipe_wm wm[3];
 644         struct vlv_sr_wm sr[3];
 645         uint8_t num_active_planes;
 646         uint8_t num_levels;
 647         uint8_t level;
 648         bool cxsr;
 649 };
 650
 651 struct intel_crtc {
 652         struct drm_crtc base;
 653         enum pipe pipe;
 654         enum plane plane;
 655         u8 lut_r[256], lut_g[256], lut_b[256];
 656         /*
 657          * Whether the crtc and the connected output pipeline is active. Implies
 658          * that crtc->enabled is set, i.e. the current mode configuration has
 659          * some outputs connected to this crtc.
 660          */
 661         bool active;
 662         unsigned long enabled_power_domains;
 663         bool lowfreq_avail;
 664         struct intel_overlay *overlay;
 665         struct intel_flip_work *flip_work;
 666
 667         atomic_t unpin_work_count;
 668
 669         /* Display surface base address adjustement for pageflips. Note that on
 670          * gen4+ this only adjusts up to a tile, offsets within a tile are
 671          * handled in the hw itself (with the TILEOFF register). */
 672         u32 dspaddr_offset;
 673         int adjusted_x;
 674         int adjusted_y;
 675
 676         uint32_t cursor_addr;
 677         uint32_t cursor_cntl;
 678         uint32_t cursor_size;
 679         uint32_t cursor_base;
 680
 681         struct intel_crtc_state *config;
 682
 683         /* reset counter value when the last flip was submitted */
 684         unsigned int reset_counter;
 685
 686         /* Access to these should be protected by dev_priv->irq_lock. */
 687         bool cpu_fifo_underrun_disabled;
 688         bool pch_fifo_underrun_disabled;
 689
 690         /* per-pipe watermark state */
 691         struct {
 692                 /* watermarks currently being used  */
 693                 union {
 694                         struct intel_pipe_wm ilk;
 695                         struct skl_pipe_wm skl;
 696                 } active;
 697
 698                 /* allow CxSR on this pipe */
 699                 bool cxsr_allowed;
 700         } wm;
 701
 702         int scanline_offset;
 703
 704         struct {
 705                 unsigned start_vbl_count;
 706                 ktime_t start_vbl_time;
 707                 int min_vbl, max_vbl;
 708                 int scanline_start;
 709         } debug;
 710
 711         /* scalers available on this crtc */
 712         int num_scalers;
 713
 714         struct vlv_wm_state wm_state;
 715 };
 716
 717 struct intel_plane_wm_parameters {
 718         uint32_t horiz_pixels;
 719         uint32_t vert_pixels;
 720         /*
 721          *   For packed pixel formats:
 722          *     bytes_per_pixel - holds bytes per pixel
 723          *   For planar pixel formats:
 724          *     bytes_per_pixel - holds bytes per pixel for uv-plane
 725          *     y_bytes_per_pixel - holds bytes per pixel for y-plane
 726          */
 727         uint8_t bytes_per_pixel;
 728         uint8_t y_bytes_per_pixel;
 729         bool enabled;
 730         bool scaled;
 731         u64 tiling;
 732         unsigned int rotation;
 733         uint16_t fifo_size;
 734 };
 735
 736 struct intel_plane {
 737         struct drm_plane base;
 738         int plane;
 739         enum pipe pipe;
 740         bool can_scale;
 741         int max_downscale;
 742         uint32_t frontbuffer_bit;
 743
 744         /* Since we need to change the watermarks before/after
 745          * enabling/disabling the planes, we need to store the parameters here
 746          * as the other pieces of the struct may not reflect the values we want
 747          * for the watermark calculations. Currently only Haswell uses this.
 748          */
 749         struct intel_plane_wm_parameters wm;
 750
 751         /*
 752          * NOTE: Do not place new plane state fields here (e.g., when adding
 753          * new plane properties).  New runtime state should now be placed in
 754          * the intel_plane_state structure and accessed via plane_state.
 755          */
 756
 757         void (*update_plane)(struct drm_plane *plane,
 758                              const struct intel_crtc_state *crtc_state,
 759                              const struct intel_plane_state *plane_state);
 760         void (*disable_plane)(struct drm_plane *plane,
 761                               struct drm_crtc *crtc);
 762         int (*check_plane)(struct drm_plane *plane,
 763                            struct intel_crtc_state *crtc_state,
 764                            struct intel_plane_state *state);
 765 };
 766
 767 struct intel_watermark_params {
 768         unsigned long fifo_size;
 769         unsigned long max_wm;
 770         unsigned long default_wm;
 771         unsigned long guard_size;
 772         unsigned long cacheline_size;
 773 };
 774
 775 struct cxsr_latency {
 776         int is_desktop;
 777         int is_ddr3;
 778         unsigned long fsb_freq;
 779         unsigned long mem_freq;
 780         unsigned long display_sr;
 781         unsigned long display_hpll_disable;
 782         unsigned long cursor_sr;
 783         unsigned long cursor_hpll_disable;
 784 };
 785
 786 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
 787 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
 788 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
 789 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
 790 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
 791 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
 792 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
 793 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
 794 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
 795
 796 struct intel_hdmi {
 797         i915_reg_t hdmi_reg;
 798         int ddc_bus;
 799         struct {
 800                 enum drm_dp_dual_mode_type type;
 801                 int max_tmds_clock;
 802         } dp_dual_mode;
 803         bool limited_color_range;
 804         bool color_range_auto;
 805         bool has_hdmi_sink;
 806         bool has_audio;
 807         enum hdmi_force_audio force_audio;
 808         bool rgb_quant_range_selectable;
 809         enum hdmi_picture_aspect aspect_ratio;
 810         struct intel_connector *attached_connector;
 811         void (*write_infoframe)(struct drm_encoder *encoder,
 812                                 enum hdmi_infoframe_type type,
 813                                 const void *frame, ssize_t len);
 814         void (*set_infoframes)(struct drm_encoder *encoder,
 815                                bool enable,
 816                                const struct drm_display_mode *adjusted_mode);
 817         bool (*infoframe_enabled)(struct drm_encoder *encoder,
 818                                   const struct intel_crtc_state *pipe_config);
 819 };
 820
 821 struct intel_dp_mst_encoder;
 822 #define DP_MAX_DOWNSTREAM_PORTS         0x10
 823
 824 /*
 825  * enum link_m_n_set:
 826  *      When platform provides two set of M_N registers for dp, we can
 827  *      program them and switch between them incase of DRRS.
 828  *      But When only one such register is provided, we have to program the
 829  *      required divider value on that registers itself based on the DRRS state.
 830  *
 831  * M1_N1        : Program dp_m_n on M1_N1 registers
 832  *                        dp_m2_n2 on M2_N2 registers (If supported)
 833  *
 834  * M2_N2        : Program dp_m2_n2 on M1_N1 registers
 835  *                        M2_N2 registers are not supported
 836  */
 837
 838 enum link_m_n_set {
 839         /* Sets the m1_n1 and m2_n2 */
 840         M1_N1 = 0,
 841         M2_N2
 842 };
 843
 844 struct intel_dp {
 845         i915_reg_t output_reg;
 846         i915_reg_t aux_ch_ctl_reg;
 847         i915_reg_t aux_ch_data_reg[5];
 848         uint32_t DP;
 849         int link_rate;
 850         uint8_t lane_count;
 851         uint8_t sink_count;
 852         bool has_audio;
 853         bool detect_done;
 854         enum hdmi_force_audio force_audio;
 855         bool limited_color_range;
 856         bool color_range_auto;
 857         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
 858         uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
 859         uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
 860         uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
 861         /* sink rates as reported by DP_SUPPORTED_LINK_RATES */
 862         uint8_t num_sink_rates;
 863         int sink_rates[DP_MAX_SUPPORTED_RATES];
 864         struct drm_dp_aux aux;
 865         uint8_t train_set[4];
 866         int panel_power_up_delay;
 867         int panel_power_down_delay;
 868         int panel_power_cycle_delay;
 869         int backlight_on_delay;
 870         int backlight_off_delay;
 871         struct delayed_work panel_vdd_work;
 872         bool want_panel_vdd;
 873         unsigned long last_power_on;
 874         unsigned long last_backlight_off;
 875         ktime_t panel_power_off_time;
 876
 877         struct notifier_block edp_notifier;
 878
 879         /*
 880          * Pipe whose power sequencer is currently locked into
 881          * this port. Only relevant on VLV/CHV.
 882          */
 883         enum pipe pps_pipe;
 884         /*
 885          * Set if the sequencer may be reset due to a power transition,
 886          * requiring a reinitialization. Only relevant on BXT.
 887          */
 888         bool pps_reset;
 889         struct edp_power_seq pps_delays;
 890
 891         bool can_mst; /* this port supports mst */
 892         bool is_mst;
 893         int active_mst_links;
 894         /* connector directly attached - won't be use for modeset in mst world */
 895         struct intel_connector *attached_connector;
 896
 897         /* mst connector list */
 898         struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
 899         struct drm_dp_mst_topology_mgr mst_mgr;
 900
 901         uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
 902         /*
 903          * This function returns the value we have to program the AUX_CTL
 904          * register with to kick off an AUX transaction.
 905          */
 906         uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
 907                                      bool has_aux_irq,
 908                                      int send_bytes,
 909                                      uint32_t aux_clock_divider);
 910
 911         /* This is called before a link training is starterd */
 912         void (*prepare_link_retrain)(struct intel_dp *intel_dp);
 913
 914         /* Displayport compliance testing */
 915         unsigned long compliance_test_type;
 916         unsigned long compliance_test_data;
 917         bool compliance_test_active;
 918 };
 919
 920 struct intel_digital_port {
 921         struct intel_encoder base;
 922         enum port port;
 923         u32 saved_port_bits;
 924         struct intel_dp dp;
 925         struct intel_hdmi hdmi;
 926         enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
 927         bool release_cl2_override;
 928         uint8_t max_lanes;
 929         /* for communication with audio component; protected by av_mutex */
 930         const struct drm_connector *audio_connector;
 931 };
 932
 933 struct intel_dp_mst_encoder {
 934         struct intel_encoder base;
 935         enum pipe pipe;
 936         struct intel_digital_port *primary;
 937         struct intel_connector *connector;
 938 };
 939
 940 static inline enum dpio_channel
 941 vlv_dport_to_channel(struct intel_digital_port *dport)
 942 {
 943         switch (dport->port) {
 944         case PORT_B:
 945         case PORT_D:
 946                 return DPIO_CH0;
 947         case PORT_C:
 948                 return DPIO_CH1;
 949         default:
 950                 BUG();
 951         }
 952 }
 953
 954 static inline enum dpio_phy
 955 vlv_dport_to_phy(struct intel_digital_port *dport)
 956 {
 957         switch (dport->port) {
 958         case PORT_B:
 959         case PORT_C:
 960                 return DPIO_PHY0;
 961         case PORT_D:
 962                 return DPIO_PHY1;
 963         default:
 964                 BUG();
 965         }
 966 }
 967
 968 static inline enum dpio_channel
 969 vlv_pipe_to_channel(enum pipe pipe)
 970 {
 971         switch (pipe) {
 972         case PIPE_A:
 973         case PIPE_C:
 974                 return DPIO_CH0;
 975         case PIPE_B:
 976                 return DPIO_CH1;
 977         default:
 978                 BUG();
 979         }
 980 }
 981
 982 static inline struct drm_crtc *
 983 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
 984 {
 985         struct drm_i915_private *dev_priv = to_i915(dev);
 986         return dev_priv->pipe_to_crtc_mapping[pipe];
 987 }
 988
 989 static inline struct drm_crtc *
 990 intel_get_crtc_for_plane(struct drm_device *dev, int plane)
 991 {
 992         struct drm_i915_private *dev_priv = to_i915(dev);
 993         return dev_priv->plane_to_crtc_mapping[plane];
 994 }
 995
 996 struct intel_flip_work {
 997         struct work_struct unpin_work;
 998         struct work_struct mmio_work;
 999
1000         struct drm_crtc *crtc;
1001         struct drm_framebuffer *old_fb;
1002         struct drm_i915_gem_object *pending_flip_obj;
1003         struct drm_pending_vblank_event *event;
1004         atomic_t pending;
1005         u32 flip_count;
1006         u32 gtt_offset;
1007         struct drm_i915_gem_request *flip_queued_req;
1008         u32 flip_queued_vblank;
1009         u32 flip_ready_vblank;
1010         unsigned int rotation;
1011 };
1012
1013 struct intel_load_detect_pipe {
1014         struct drm_atomic_state *restore_state;
1015 };
1016
1017 static inline struct intel_encoder *
1018 intel_attached_encoder(struct drm_connector *connector)
1019 {
1020         return to_intel_connector(connector)->encoder;
1021 }
1022
1023 static inline struct intel_digital_port *
1024 enc_to_dig_port(struct drm_encoder *encoder)
1025 {
1026         return container_of(encoder, struct intel_digital_port, base.base);
1027 }
1028
1029 static inline struct intel_dp_mst_encoder *
1030 enc_to_mst(struct drm_encoder *encoder)
1031 {
1032         return container_of(encoder, struct intel_dp_mst_encoder, base.base);
1033 }
1034
1035 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
1036 {
1037         return &enc_to_dig_port(encoder)->dp;
1038 }
1039
1040 static inline struct intel_digital_port *
1041 dp_to_dig_port(struct intel_dp *intel_dp)
1042 {
1043         return container_of(intel_dp, struct intel_digital_port, dp);
1044 }
1045
1046 static inline struct intel_digital_port *
1047 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
1048 {
1049         return container_of(intel_hdmi, struct intel_digital_port, hdmi);
1050 }
1051
1052 /*
1053  * Returns the number of planes for this pipe, ie the number of sprites + 1
1054  * (primary plane). This doesn't count the cursor plane then.
1055  */
1056 static inline unsigned int intel_num_planes(struct intel_crtc *crtc)
1057 {
1058         return INTEL_INFO(crtc->base.dev)->num_sprites[crtc->pipe] + 1;
1059 }
1060
1061 /* intel_fifo_underrun.c */
1062 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1063                                            enum pipe pipe, bool enable);
1064 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1065                                            enum transcoder pch_transcoder,
1066                                            bool enable);
1067 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1068                                          enum pipe pipe);
1069 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1070                                          enum transcoder pch_transcoder);
1071 void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv);
1072 void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv);
1073
1074 /* i915_irq.c */
1075 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1076 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1077 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1078 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1079 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1080 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
1081 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
1082 u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask);
1083 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
1084 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
1085 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
1086 {
1087         /*
1088          * We only use drm_irq_uninstall() at unload and VT switch, so
1089          * this is the only thing we need to check.
1090          */
1091         return dev_priv->pm.irqs_enabled;
1092 }
1093
1094 int intel_get_crtc_scanline(struct intel_crtc *crtc);
1095 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
1096                                      unsigned int pipe_mask);
1097 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
1098                                      unsigned int pipe_mask);
1099
1100 /* intel_crt.c */
1101 void intel_crt_init(struct drm_device *dev);
1102 void intel_crt_reset(struct drm_encoder *encoder);
1103
1104 /* intel_ddi.c */
1105 void intel_ddi_clk_select(struct intel_encoder *encoder,
1106                           const struct intel_crtc_state *pipe_config);
1107 void intel_prepare_ddi_buffer(struct intel_encoder *encoder);
1108 void hsw_fdi_link_train(struct drm_crtc *crtc);
1109 void intel_ddi_init(struct drm_device *dev, enum port port);
1110 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
1111 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
1112 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
1113 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1114                                        enum transcoder cpu_transcoder);
1115 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
1116 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
1117 bool intel_ddi_pll_select(struct intel_crtc *crtc,
1118                           struct intel_crtc_state *crtc_state);
1119 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
1120 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp);
1121 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
1122 void intel_ddi_fdi_disable(struct drm_crtc *crtc);
1123 void intel_ddi_get_config(struct intel_encoder *encoder,
1124                           struct intel_crtc_state *pipe_config);
1125 struct intel_encoder *
1126 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state);
1127
1128 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
1129 void intel_ddi_clock_get(struct intel_encoder *encoder,
1130                          struct intel_crtc_state *pipe_config);
1131 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
1132 uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
1133
1134 /* intel_frontbuffer.c */
1135 void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
1136                              enum fb_op_origin origin);
1137 void intel_frontbuffer_flip_prepare(struct drm_device *dev,
1138                                     unsigned frontbuffer_bits);
1139 void intel_frontbuffer_flip_complete(struct drm_device *dev,
1140                                      unsigned frontbuffer_bits);
1141 void intel_frontbuffer_flip(struct drm_device *dev,
1142                             unsigned frontbuffer_bits);
1143 unsigned int intel_fb_align_height(struct drm_device *dev,
1144                                    unsigned int height,
1145                                    uint32_t pixel_format,
1146                                    uint64_t fb_format_modifier);
1147 void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire,
1148                         enum fb_op_origin origin);
1149 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
1150                               uint64_t fb_modifier, uint32_t pixel_format);
1151
1152 /* intel_audio.c */
1153 void intel_init_audio_hooks(struct drm_i915_private *dev_priv);
1154 void intel_audio_codec_enable(struct intel_encoder *encoder);
1155 void intel_audio_codec_disable(struct intel_encoder *encoder);
1156 void i915_audio_component_init(struct drm_i915_private *dev_priv);
1157 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
1158
1159 /* intel_display.c */
1160 void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, int vco);
1161 void intel_update_rawclk(struct drm_i915_private *dev_priv);
1162 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
1163                       const char *name, u32 reg, int ref_freq);
1164 extern const struct drm_plane_funcs intel_plane_funcs;
1165 void intel_init_display_hooks(struct drm_i915_private *dev_priv);
1166 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
1167 bool intel_has_pending_fb_unpin(struct drm_device *dev);
1168 void intel_mark_busy(struct drm_i915_private *dev_priv);
1169 void intel_mark_idle(struct drm_i915_private *dev_priv);
1170 void intel_crtc_restore_mode(struct drm_crtc *crtc);
1171 int intel_display_suspend(struct drm_device *dev);
1172 void intel_encoder_destroy(struct drm_encoder *encoder);
1173 int intel_connector_init(struct intel_connector *);
1174 struct intel_connector *intel_connector_alloc(void);
1175 bool intel_connector_get_hw_state(struct intel_connector *connector);
1176 void intel_connector_attach_encoder(struct intel_connector *connector,
1177                                     struct intel_encoder *encoder);
1178 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
1179                                              struct drm_crtc *crtc);
1180 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
1181 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
1182                                 struct drm_file *file_priv);
1183 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1184                                              enum pipe pipe);
1185 static inline bool
1186 intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
1187                     enum intel_output_type type)
1188 {
1189         return crtc_state->output_types & (1 << type);
1190 }
1191 static inline bool
1192 intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
1193 {
1194         return crtc_state->output_types &
1195                 ((1 << INTEL_OUTPUT_DP) |
1196                  (1 << INTEL_OUTPUT_DP_MST) |
1197                  (1 << INTEL_OUTPUT_EDP));
1198 }
1199 static inline void
1200 intel_wait_for_vblank(struct drm_device *dev, int pipe)
1201 {
1202         drm_wait_one_vblank(dev, pipe);
1203 }
1204 static inline void
1205 intel_wait_for_vblank_if_active(struct drm_device *dev, int pipe)
1206 {
1207         const struct intel_crtc *crtc =
1208                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
1209
1210         if (crtc->active)
1211                 intel_wait_for_vblank(dev, pipe);
1212 }
1213
1214 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
1215
1216 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1217 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1218                          struct intel_digital_port *dport,
1219                          unsigned int expected_mask);
1220 bool intel_get_load_detect_pipe(struct drm_connector *connector,
1221                                 struct drm_display_mode *mode,
1222                                 struct intel_load_detect_pipe *old,
1223                                 struct drm_modeset_acquire_ctx *ctx);
1224 void intel_release_load_detect_pipe(struct drm_connector *connector,
1225                                     struct intel_load_detect_pipe *old,
1226                                     struct drm_modeset_acquire_ctx *ctx);
1227 int intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
1228                                unsigned int rotation);
1229 void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation);
1230 struct drm_framebuffer *
1231 __intel_framebuffer_create(struct drm_device *dev,
1232                            struct drm_mode_fb_cmd2 *mode_cmd,
1233                            struct drm_i915_gem_object *obj);
1234 void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe);
1235 void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe);
1236 void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe);
1237 int intel_prepare_plane_fb(struct drm_plane *plane,
1238                            const struct drm_plane_state *new_state);
1239 void intel_cleanup_plane_fb(struct drm_plane *plane,
1240                             const struct drm_plane_state *old_state);
1241 int intel_plane_atomic_get_property(struct drm_plane *plane,
1242                                     const struct drm_plane_state *state,
1243                                     struct drm_property *property,
1244                                     uint64_t *val);
1245 int intel_plane_atomic_set_property(struct drm_plane *plane,
1246                                     struct drm_plane_state *state,
1247                                     struct drm_property *property,
1248                                     uint64_t val);
1249 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
1250                                     struct drm_plane_state *plane_state);
1251
1252 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
1253                                uint64_t fb_modifier, unsigned int cpp);
1254
1255 static inline bool
1256 intel_rotation_90_or_270(unsigned int rotation)
1257 {
1258         return rotation & (DRM_ROTATE_90 | DRM_ROTATE_270);
1259 }
1260
1261 void intel_create_rotation_property(struct drm_device *dev,
1262                                         struct intel_plane *plane);
1263
1264 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1265                                     enum pipe pipe);
1266
1267 int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
1268                      const struct dpll *dpll);
1269 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe);
1270 int lpt_get_iclkip(struct drm_i915_private *dev_priv);
1271
1272 /* modesetting asserts */
1273 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1274                            enum pipe pipe);
1275 void assert_pll(struct drm_i915_private *dev_priv,
1276                 enum pipe pipe, bool state);
1277 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1278 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1279 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state);
1280 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1281 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1282 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1283                        enum pipe pipe, bool state);
1284 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1285 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1286 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1287 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1288 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1289 u32 intel_compute_tile_offset(int *x, int *y,
1290                               const struct drm_framebuffer *fb, int plane,
1291                               unsigned int pitch,
1292                               unsigned int rotation);
1293 void intel_prepare_reset(struct drm_i915_private *dev_priv);
1294 void intel_finish_reset(struct drm_i915_private *dev_priv);
1295 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1296 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1297 void bxt_init_cdclk(struct drm_i915_private *dev_priv);
1298 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
1299 void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy);
1300 void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy);
1301 bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
1302                             enum dpio_phy phy);
1303 bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
1304                               enum dpio_phy phy);
1305 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv);
1306 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1307 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1308 void gen9_enable_dc5(struct drm_i915_private *dev_priv);
1309 void skl_init_cdclk(struct drm_i915_private *dev_priv);
1310 void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1311 unsigned int skl_cdclk_get_vco(unsigned int freq);
1312 void skl_enable_dc6(struct drm_i915_private *dev_priv);
1313 void skl_disable_dc6(struct drm_i915_private *dev_priv);
1314 void intel_dp_get_m_n(struct intel_crtc *crtc,
1315                       struct intel_crtc_state *pipe_config);
1316 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
1317 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1318 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1319                         struct dpll *best_clock);
1320 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
1321
1322 bool intel_crtc_active(struct drm_crtc *crtc);
1323 void hsw_enable_ips(struct intel_crtc *crtc);
1324 void hsw_disable_ips(struct intel_crtc *crtc);
1325 enum intel_display_power_domain
1326 intel_display_port_power_domain(struct intel_encoder *intel_encoder);
1327 enum intel_display_power_domain
1328 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder);
1329 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1330                                  struct intel_crtc_state *pipe_config);
1331
1332 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1333 int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
1334
1335 u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
1336                            struct drm_i915_gem_object *obj,
1337                            unsigned int plane);
1338
1339 u32 skl_plane_ctl_format(uint32_t pixel_format);
1340 u32 skl_plane_ctl_tiling(uint64_t fb_modifier);
1341 u32 skl_plane_ctl_rotation(unsigned int rotation);
1342
1343 /* intel_csr.c */
1344 void intel_csr_ucode_init(struct drm_i915_private *);
1345 void intel_csr_load_program(struct drm_i915_private *);
1346 void intel_csr_ucode_fini(struct drm_i915_private *);
1347 void intel_csr_ucode_suspend(struct drm_i915_private *);
1348 void intel_csr_ucode_resume(struct drm_i915_private *);
1349
1350 /* intel_dp.c */
1351 bool intel_dp_init(struct drm_device *dev, i915_reg_t output_reg, enum port port);
1352 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1353                              struct intel_connector *intel_connector);
1354 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1355                               const struct intel_crtc_state *pipe_config);
1356 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1357 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1358 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1359 void intel_dp_encoder_reset(struct drm_encoder *encoder);
1360 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
1361 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1362 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
1363 bool intel_dp_compute_config(struct intel_encoder *encoder,
1364                              struct intel_crtc_state *pipe_config);
1365 bool intel_dp_is_edp(struct drm_device *dev, enum port port);
1366 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1367                                   bool long_hpd);
1368 void intel_edp_backlight_on(struct intel_dp *intel_dp);
1369 void intel_edp_backlight_off(struct intel_dp *intel_dp);
1370 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1371 void intel_edp_panel_on(struct intel_dp *intel_dp);
1372 void intel_edp_panel_off(struct intel_dp *intel_dp);
1373 void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
1374 void intel_dp_mst_suspend(struct drm_device *dev);
1375 void intel_dp_mst_resume(struct drm_device *dev);
1376 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1377 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1378 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1379 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv);
1380 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1381 void intel_plane_destroy(struct drm_plane *plane);
1382 void intel_edp_drrs_enable(struct intel_dp *intel_dp);
1383 void intel_edp_drrs_disable(struct intel_dp *intel_dp);
1384 void intel_edp_drrs_invalidate(struct drm_device *dev,
1385                 unsigned frontbuffer_bits);
1386 void intel_edp_drrs_flush(struct drm_device *dev, unsigned frontbuffer_bits);
1387 bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
1388                                          struct intel_digital_port *port);
1389
1390 void
1391 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
1392                                        uint8_t dp_train_pat);
1393 void
1394 intel_dp_set_signal_levels(struct intel_dp *intel_dp);
1395 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
1396 uint8_t
1397 intel_dp_voltage_max(struct intel_dp *intel_dp);
1398 uint8_t
1399 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing);
1400 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1401                            uint8_t *link_bw, uint8_t *rate_select);
1402 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
1403 bool
1404 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]);
1405
1406 static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
1407 {
1408         return ~((1 << lane_count) - 1) & 0xf;
1409 }
1410
1411 /* intel_dp_aux_backlight.c */
1412 int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector);
1413
1414 /* intel_dp_mst.c */
1415 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1416 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1417 /* intel_dsi.c */
1418 void intel_dsi_init(struct drm_device *dev);
1419
1420 /* intel_dsi_dcs_backlight.c */
1421 int intel_dsi_dcs_init_backlight_funcs(struct intel_connector *intel_connector);
1422
1423 /* intel_dvo.c */
1424 void intel_dvo_init(struct drm_device *dev);
1425 /* intel_hotplug.c */
1426 void intel_hpd_poll_init(struct drm_i915_private *dev_priv);
1427
1428
1429 /* legacy fbdev emulation in intel_fbdev.c */
1430 #ifdef CONFIG_DRM_FBDEV_EMULATION
1431 extern int intel_fbdev_init(struct drm_device *dev);
1432 extern void intel_fbdev_initial_config_async(struct drm_device *dev);
1433 extern void intel_fbdev_fini(struct drm_device *dev);
1434 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1435 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1436 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1437 #else
1438 static inline int intel_fbdev_init(struct drm_device *dev)
1439 {
1440         return 0;
1441 }
1442
1443 static inline void intel_fbdev_initial_config_async(struct drm_device *dev)
1444 {
1445 }
1446
1447 static inline void intel_fbdev_fini(struct drm_device *dev)
1448 {
1449 }
1450
1451 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1452 {
1453 }
1454
1455 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1456 {
1457 }
1458 #endif
1459
1460 /* intel_fbc.c */
1461 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1462                            struct drm_atomic_state *state);
1463 bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
1464 void intel_fbc_pre_update(struct intel_crtc *crtc,
1465                           struct intel_crtc_state *crtc_state,
1466                           struct intel_plane_state *plane_state);
1467 void intel_fbc_post_update(struct intel_crtc *crtc);
1468 void intel_fbc_init(struct drm_i915_private *dev_priv);
1469 void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv);
1470 void intel_fbc_enable(struct intel_crtc *crtc,
1471                       struct intel_crtc_state *crtc_state,
1472                       struct intel_plane_state *plane_state);
1473 void intel_fbc_disable(struct intel_crtc *crtc);
1474 void intel_fbc_global_disable(struct drm_i915_private *dev_priv);
1475 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1476                           unsigned int frontbuffer_bits,
1477                           enum fb_op_origin origin);
1478 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1479                      unsigned int frontbuffer_bits, enum fb_op_origin origin);
1480 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
1481
1482 /* intel_hdmi.c */
1483 void intel_hdmi_init(struct drm_device *dev, i915_reg_t hdmi_reg, enum port port);
1484 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1485                                struct intel_connector *intel_connector);
1486 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1487 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1488                                struct intel_crtc_state *pipe_config);
1489 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable);
1490
1491
1492 /* intel_lvds.c */
1493 void intel_lvds_init(struct drm_device *dev);
1494 struct intel_encoder *intel_get_lvds_encoder(struct drm_device *dev);
1495 bool intel_is_dual_link_lvds(struct drm_device *dev);
1496
1497
1498 /* intel_modes.c */
1499 int intel_connector_update_modes(struct drm_connector *connector,
1500                                  struct edid *edid);
1501 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1502 void intel_attach_force_audio_property(struct drm_connector *connector);
1503 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1504 void intel_attach_aspect_ratio_property(struct drm_connector *connector);
1505
1506
1507 /* intel_overlay.c */
1508 void intel_setup_overlay(struct drm_i915_private *dev_priv);
1509 void intel_cleanup_overlay(struct drm_i915_private *dev_priv);
1510 int intel_overlay_switch_off(struct intel_overlay *overlay);
1511 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
1512                                   struct drm_file *file_priv);
1513 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
1514                               struct drm_file *file_priv);
1515 void intel_overlay_reset(struct drm_i915_private *dev_priv);
1516
1517
1518 /* intel_panel.c */
1519 int intel_panel_init(struct intel_panel *panel,
1520                      struct drm_display_mode *fixed_mode,
1521                      struct drm_display_mode *downclock_mode);
1522 void intel_panel_fini(struct intel_panel *panel);
1523 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1524                             struct drm_display_mode *adjusted_mode);
1525 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1526                              struct intel_crtc_state *pipe_config,
1527                              int fitting_mode);
1528 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1529                               struct intel_crtc_state *pipe_config,
1530                               int fitting_mode);
1531 void intel_panel_set_backlight_acpi(struct intel_connector *connector,
1532                                     u32 level, u32 max);
1533 int intel_panel_setup_backlight(struct drm_connector *connector,
1534                                 enum pipe pipe);
1535 void intel_panel_enable_backlight(struct intel_connector *connector);
1536 void intel_panel_disable_backlight(struct intel_connector *connector);
1537 void intel_panel_destroy_backlight(struct drm_connector *connector);
1538 enum drm_connector_status intel_panel_detect(struct drm_device *dev);
1539 extern struct drm_display_mode *intel_find_panel_downclock(
1540                                 struct drm_device *dev,
1541                                 struct drm_display_mode *fixed_mode,
1542                                 struct drm_connector *connector);
1543
1544 #if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
1545 int intel_backlight_device_register(struct intel_connector *connector);
1546 void intel_backlight_device_unregister(struct intel_connector *connector);
1547 #else /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1548 static int intel_backlight_device_register(struct intel_connector *connector)
1549 {
1550         return 0;
1551 }
1552 static inline void intel_backlight_device_unregister(struct intel_connector *connector)
1553 {
1554 }
1555 #endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1556
1557
1558 /* intel_psr.c */
1559 void intel_psr_enable(struct intel_dp *intel_dp);
1560 void intel_psr_disable(struct intel_dp *intel_dp);
1561 void intel_psr_invalidate(struct drm_device *dev,
1562                           unsigned frontbuffer_bits);
1563 void intel_psr_flush(struct drm_device *dev,
1564                      unsigned frontbuffer_bits,
1565                      enum fb_op_origin origin);
1566 void intel_psr_init(struct drm_device *dev);
1567 void intel_psr_single_frame_update(struct drm_device *dev,
1568                                    unsigned frontbuffer_bits);
1569
1570 /* intel_runtime_pm.c */
1571 int intel_power_domains_init(struct drm_i915_private *);
1572 void intel_power_domains_fini(struct drm_i915_private *);
1573 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
1574 void intel_power_domains_suspend(struct drm_i915_private *dev_priv);
1575 void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
1576 void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
1577 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1578 const char *
1579 intel_display_power_domain_str(enum intel_display_power_domain domain);
1580
1581 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1582                                     enum intel_display_power_domain domain);
1583 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1584                                       enum intel_display_power_domain domain);
1585 void intel_display_power_get(struct drm_i915_private *dev_priv,
1586                              enum intel_display_power_domain domain);
1587 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
1588                                         enum intel_display_power_domain domain);
1589 void intel_display_power_put(struct drm_i915_private *dev_priv,
1590                              enum intel_display_power_domain domain);
1591
1592 static inline void
1593 assert_rpm_device_not_suspended(struct drm_i915_private *dev_priv)
1594 {
1595         WARN_ONCE(dev_priv->pm.suspended,
1596                   "Device suspended during HW access\n");
1597 }
1598
1599 static inline void
1600 assert_rpm_wakelock_held(struct drm_i915_private *dev_priv)
1601 {
1602         assert_rpm_device_not_suspended(dev_priv);
1603         /* FIXME: Needs to be converted back to WARN_ONCE, but currently causes
1604          * too much noise. */
1605         if (!atomic_read(&dev_priv->pm.wakeref_count))
1606                 DRM_DEBUG_DRIVER("RPM wakelock ref not held during HW access");
1607 }
1608
1609 static inline int
1610 assert_rpm_atomic_begin(struct drm_i915_private *dev_priv)
1611 {
1612         int seq = atomic_read(&dev_priv->pm.atomic_seq);
1613
1614         assert_rpm_wakelock_held(dev_priv);
1615
1616         return seq;
1617 }
1618
1619 static inline void
1620 assert_rpm_atomic_end(struct drm_i915_private *dev_priv, int begin_seq)
1621 {
1622         WARN_ONCE(atomic_read(&dev_priv->pm.atomic_seq) != begin_seq,
1623                   "HW access outside of RPM atomic section\n");
1624 }
1625
1626 /**
1627  * disable_rpm_wakeref_asserts - disable the RPM assert checks
1628  * @dev_priv: i915 device instance
1629  *
1630  * This function disable asserts that check if we hold an RPM wakelock
1631  * reference, while keeping the device-not-suspended checks still enabled.
1632  * It's meant to be used only in special circumstances where our rule about
1633  * the wakelock refcount wrt. the device power state doesn't hold. According
1634  * to this rule at any point where we access the HW or want to keep the HW in
1635  * an active state we must hold an RPM wakelock reference acquired via one of
1636  * the intel_runtime_pm_get() helpers. Currently there are a few special spots
1637  * where this rule doesn't hold: the IRQ and suspend/resume handlers, the
1638  * forcewake release timer, and the GPU RPS and hangcheck works. All other
1639  * users should avoid using this function.
1640  *
1641  * Any calls to this function must have a symmetric call to
1642  * enable_rpm_wakeref_asserts().
1643  */
1644 static inline void
1645 disable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1646 {
1647         atomic_inc(&dev_priv->pm.wakeref_count);
1648 }
1649
1650 /**
1651  * enable_rpm_wakeref_asserts - re-enable the RPM assert checks
1652  * @dev_priv: i915 device instance
1653  *
1654  * This function re-enables the RPM assert checks after disabling them with
1655  * disable_rpm_wakeref_asserts. It's meant to be used only in special
1656  * circumstances otherwise its use should be avoided.
1657  *
1658  * Any calls to this function must have a symmetric call to
1659  * disable_rpm_wakeref_asserts().
1660  */
1661 static inline void
1662 enable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1663 {
1664         atomic_dec(&dev_priv->pm.wakeref_count);
1665 }
1666
1667 /* TODO: convert users of these to rely instead on proper RPM refcounting */
1668 #define DISABLE_RPM_WAKEREF_ASSERTS(dev_priv)   \
1669         disable_rpm_wakeref_asserts(dev_priv)
1670
1671 #define ENABLE_RPM_WAKEREF_ASSERTS(dev_priv)    \
1672         enable_rpm_wakeref_asserts(dev_priv)
1673
1674 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1675 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv);
1676 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1677 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1678
1679 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
1680
1681 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1682                              bool override, unsigned int mask);
1683 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1684                           enum dpio_channel ch, bool override);
1685
1686
1687 /* intel_pm.c */
1688 void intel_init_clock_gating(struct drm_device *dev);
1689 void intel_suspend_hw(struct drm_device *dev);
1690 int ilk_wm_max_level(const struct drm_device *dev);
1691 void intel_update_watermarks(struct drm_crtc *crtc);
1692 void intel_init_pm(struct drm_device *dev);
1693 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
1694 void intel_pm_setup(struct drm_device *dev);
1695 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1696 void intel_gpu_ips_teardown(void);
1697 void intel_init_gt_powersave(struct drm_i915_private *dev_priv);
1698 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv);
1699 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv);
1700 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv);
1701 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv);
1702 void intel_reset_gt_powersave(struct drm_i915_private *dev_priv);
1703 void gen6_update_ring_freq(struct drm_i915_private *dev_priv);
1704 void gen6_rps_busy(struct drm_i915_private *dev_priv);
1705 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
1706 void gen6_rps_idle(struct drm_i915_private *dev_priv);
1707 void gen6_rps_boost(struct drm_i915_private *dev_priv,
1708                     struct intel_rps_client *rps,
1709                     unsigned long submitted);
1710 void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req);
1711 void vlv_wm_get_hw_state(struct drm_device *dev);
1712 void ilk_wm_get_hw_state(struct drm_device *dev);
1713 void skl_wm_get_hw_state(struct drm_device *dev);
1714 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
1715                           struct skl_ddb_allocation *ddb /* out */);
1716 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config);
1717 bool ilk_disable_lp_wm(struct drm_device *dev);
1718 int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6);
1719 static inline int intel_enable_rc6(void)
1720 {
1721         return i915.enable_rc6;
1722 }
1723
1724 /* intel_sdvo.c */
1725 bool intel_sdvo_init(struct drm_device *dev,
1726                      i915_reg_t reg, enum port port);
1727
1728
1729 /* intel_sprite.c */
1730 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
1731                              int usecs);
1732 int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
1733 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1734                               struct drm_file *file_priv);
1735 void intel_pipe_update_start(struct intel_crtc *crtc);
1736 void intel_pipe_update_end(struct intel_crtc *crtc, struct intel_flip_work *work);
1737
1738 /* intel_tv.c */
1739 void intel_tv_init(struct drm_device *dev);
1740
1741 /* intel_atomic.c */
1742 int intel_connector_atomic_get_property(struct drm_connector *connector,
1743                                         const struct drm_connector_state *state,
1744                                         struct drm_property *property,
1745                                         uint64_t *val);
1746 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
1747 void intel_crtc_destroy_state(struct drm_crtc *crtc,
1748                                struct drm_crtc_state *state);
1749 struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
1750 void intel_atomic_state_clear(struct drm_atomic_state *);
1751 struct intel_shared_dpll_config *
1752 intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s);
1753
1754 static inline struct intel_crtc_state *
1755 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
1756                             struct intel_crtc *crtc)
1757 {
1758         struct drm_crtc_state *crtc_state;
1759         crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
1760         if (IS_ERR(crtc_state))
1761                 return ERR_CAST(crtc_state);
1762
1763         return to_intel_crtc_state(crtc_state);
1764 }
1765
1766 static inline struct intel_plane_state *
1767 intel_atomic_get_existing_plane_state(struct drm_atomic_state *state,
1768                                       struct intel_plane *plane)
1769 {
1770         struct drm_plane_state *plane_state;
1771
1772         plane_state = drm_atomic_get_existing_plane_state(state, &plane->base);
1773
1774         return to_intel_plane_state(plane_state);
1775 }
1776
1777 int intel_atomic_setup_scalers(struct drm_device *dev,
1778         struct intel_crtc *intel_crtc,
1779         struct intel_crtc_state *crtc_state);
1780
1781 /* intel_atomic_plane.c */
1782 struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
1783 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
1784 void intel_plane_destroy_state(struct drm_plane *plane,
1785                                struct drm_plane_state *state);
1786 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
1787
1788 /* intel_color.c */
1789 void intel_color_init(struct drm_crtc *crtc);
1790 int intel_color_check(struct drm_crtc *crtc, struct drm_crtc_state *state);
1791 void intel_color_set_csc(struct drm_crtc_state *crtc_state);
1792 void intel_color_load_luts(struct drm_crtc_state *crtc_state);
1793
1794 #endif /* __INTEL_DRV_H__ */