drivers/gpu/drm/i915/intel_dsi.c

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Author: Jani Nikula <jani.nikula@intel.com>
  24  */
  25
  26 #include <drm/drmP.h>
  27 #include <drm/drm_atomic_helper.h>
  28 #include <drm/drm_crtc.h>
  29 #include <drm/drm_edid.h>
  30 #include <drm/i915_drm.h>
  31 #include <drm/drm_panel.h>
  32 #include <drm/drm_mipi_dsi.h>
  33 #include <linux/slab.h>
  34 #include <linux/gpio/consumer.h>
  35 #include "i915_drv.h"
  36 #include "intel_drv.h"
  37 #include "intel_dsi.h"
  38
  39 static const struct {
  40         u16 panel_id;
  41         struct drm_panel * (*init)(struct intel_dsi *intel_dsi, u16 panel_id);
  42 } intel_dsi_drivers[] = {
  43         {
  44                 .panel_id = MIPI_DSI_GENERIC_PANEL_ID,
  45                 .init = vbt_panel_init,
  46         },
  47 };
  48
  49 /* return pixels in terms of txbyteclkhs */
  50 static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count,
  51                        u16 burst_mode_ratio)
  52 {
  53         return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp * burst_mode_ratio,
  54                                          8 * 100), lane_count);
  55 }
  56
  57 /* return pixels equvalent to txbyteclkhs */
  58 static u16 pixels_from_txbyteclkhs(u16 clk_hs, int bpp, int lane_count,
  59                         u16 burst_mode_ratio)
  60 {
  61         return DIV_ROUND_UP((clk_hs * lane_count * 8 * 100),
  62                                                 (bpp * burst_mode_ratio));
  63 }
  64
  65 enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt)
  66 {
  67         /* It just so happens the VBT matches register contents. */
  68         switch (fmt) {
  69         case VID_MODE_FORMAT_RGB888:
  70                 return MIPI_DSI_FMT_RGB888;
  71         case VID_MODE_FORMAT_RGB666:
  72                 return MIPI_DSI_FMT_RGB666;
  73         case VID_MODE_FORMAT_RGB666_PACKED:
  74                 return MIPI_DSI_FMT_RGB666_PACKED;
  75         case VID_MODE_FORMAT_RGB565:
  76                 return MIPI_DSI_FMT_RGB565;
  77         default:
  78                 MISSING_CASE(fmt);
  79                 return MIPI_DSI_FMT_RGB666;
  80         }
  81 }
  82
  83 static void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi, enum port port)
  84 {
  85         struct drm_encoder *encoder = &intel_dsi->base.base;
  86         struct drm_device *dev = encoder->dev;
  87         struct drm_i915_private *dev_priv = dev->dev_private;
  88         u32 mask;
  89
  90         mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY |
  91                 LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY;
  92
  93         if (intel_wait_for_register(dev_priv,
  94                                     MIPI_GEN_FIFO_STAT(port), mask, mask,
  95                                     100))
  96                 DRM_ERROR("DPI FIFOs are not empty\n");
  97 }
  98
  99 static void write_data(struct drm_i915_private *dev_priv,
 100                        i915_reg_t reg,
 101                        const u8 *data, u32 len)
 102 {
 103         u32 i, j;
 104
 105         for (i = 0; i < len; i += 4) {
 106                 u32 val = 0;
 107
 108                 for (j = 0; j < min_t(u32, len - i, 4); j++)
 109                         val |= *data++ << 8 * j;
 110
 111                 I915_WRITE(reg, val);
 112         }
 113 }
 114
 115 static void read_data(struct drm_i915_private *dev_priv,
 116                       i915_reg_t reg,
 117                       u8 *data, u32 len)
 118 {
 119         u32 i, j;
 120
 121         for (i = 0; i < len; i += 4) {
 122                 u32 val = I915_READ(reg);
 123
 124                 for (j = 0; j < min_t(u32, len - i, 4); j++)
 125                         *data++ = val >> 8 * j;
 126         }
 127 }
 128
 129 static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host,
 130                                        const struct mipi_dsi_msg *msg)
 131 {
 132         struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host);
 133         struct drm_device *dev = intel_dsi_host->intel_dsi->base.base.dev;
 134         struct drm_i915_private *dev_priv = dev->dev_private;
 135         enum port port = intel_dsi_host->port;
 136         struct mipi_dsi_packet packet;
 137         ssize_t ret;
 138         const u8 *header, *data;
 139         i915_reg_t data_reg, ctrl_reg;
 140         u32 data_mask, ctrl_mask;
 141
 142         ret = mipi_dsi_create_packet(&packet, msg);
 143         if (ret < 0)
 144                 return ret;
 145
 146         header = packet.header;
 147         data = packet.payload;
 148
 149         if (msg->flags & MIPI_DSI_MSG_USE_LPM) {
 150                 data_reg = MIPI_LP_GEN_DATA(port);
 151                 data_mask = LP_DATA_FIFO_FULL;
 152                 ctrl_reg = MIPI_LP_GEN_CTRL(port);
 153                 ctrl_mask = LP_CTRL_FIFO_FULL;
 154         } else {
 155                 data_reg = MIPI_HS_GEN_DATA(port);
 156                 data_mask = HS_DATA_FIFO_FULL;
 157                 ctrl_reg = MIPI_HS_GEN_CTRL(port);
 158                 ctrl_mask = HS_CTRL_FIFO_FULL;
 159         }
 160
 161         /* note: this is never true for reads */
 162         if (packet.payload_length) {
 163                 if (intel_wait_for_register(dev_priv,
 164                                             MIPI_GEN_FIFO_STAT(port),
 165                                             data_mask, 0,
 166                                             50))
 167                         DRM_ERROR("Timeout waiting for HS/LP DATA FIFO !full\n");
 168
 169                 write_data(dev_priv, data_reg, packet.payload,
 170                            packet.payload_length);
 171         }
 172
 173         if (msg->rx_len) {
 174                 I915_WRITE(MIPI_INTR_STAT(port), GEN_READ_DATA_AVAIL);
 175         }
 176
 177         if (intel_wait_for_register(dev_priv,
 178                                     MIPI_GEN_FIFO_STAT(port),
 179                                     ctrl_mask, 0,
 180                                     50)) {
 181                 DRM_ERROR("Timeout waiting for HS/LP CTRL FIFO !full\n");
 182         }
 183
 184         I915_WRITE(ctrl_reg, header[2] << 16 | header[1] << 8 | header[0]);
 185
 186         /* ->rx_len is set only for reads */
 187         if (msg->rx_len) {
 188                 data_mask = GEN_READ_DATA_AVAIL;
 189                 if (intel_wait_for_register(dev_priv,
 190                                             MIPI_INTR_STAT(port),
 191                                             data_mask, data_mask,
 192                                             50))
 193                         DRM_ERROR("Timeout waiting for read data.\n");
 194
 195                 read_data(dev_priv, data_reg, msg->rx_buf, msg->rx_len);
 196         }
 197
 198         /* XXX: fix for reads and writes */
 199         return 4 + packet.payload_length;
 200 }
 201
 202 static int intel_dsi_host_attach(struct mipi_dsi_host *host,
 203                                  struct mipi_dsi_device *dsi)
 204 {
 205         return 0;
 206 }
 207
 208 static int intel_dsi_host_detach(struct mipi_dsi_host *host,
 209                                  struct mipi_dsi_device *dsi)
 210 {
 211         return 0;
 212 }
 213
 214 static const struct mipi_dsi_host_ops intel_dsi_host_ops = {
 215         .attach = intel_dsi_host_attach,
 216         .detach = intel_dsi_host_detach,
 217         .transfer = intel_dsi_host_transfer,
 218 };
 219
 220 static struct intel_dsi_host *intel_dsi_host_init(struct intel_dsi *intel_dsi,
 221                                                   enum port port)
 222 {
 223         struct intel_dsi_host *host;
 224         struct mipi_dsi_device *device;
 225
 226         host = kzalloc(sizeof(*host), GFP_KERNEL);
 227         if (!host)
 228                 return NULL;
 229
 230         host->base.ops = &intel_dsi_host_ops;
 231         host->intel_dsi = intel_dsi;
 232         host->port = port;
 233
 234         /*
 235          * We should call mipi_dsi_host_register(&host->base) here, but we don't
 236          * have a host->dev, and we don't have OF stuff either. So just use the
 237          * dsi framework as a library and hope for the best. Create the dsi
 238          * devices by ourselves here too. Need to be careful though, because we
 239          * don't initialize any of the driver model devices here.
 240          */
 241         device = kzalloc(sizeof(*device), GFP_KERNEL);
 242         if (!device) {
 243                 kfree(host);
 244                 return NULL;
 245         }
 246
 247         device->host = &host->base;
 248         host->device = device;
 249
 250         return host;
 251 }
 252
 253 /*
 254  * send a video mode command
 255  *
 256  * XXX: commands with data in MIPI_DPI_DATA?
 257  */
 258 static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs,
 259                         enum port port)
 260 {
 261         struct drm_encoder *encoder = &intel_dsi->base.base;
 262         struct drm_device *dev = encoder->dev;
 263         struct drm_i915_private *dev_priv = dev->dev_private;
 264         u32 mask;
 265
 266         /* XXX: pipe, hs */
 267         if (hs)
 268                 cmd &= ~DPI_LP_MODE;
 269         else
 270                 cmd |= DPI_LP_MODE;
 271
 272         /* clear bit */
 273         I915_WRITE(MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT);
 274
 275         /* XXX: old code skips write if control unchanged */
 276         if (cmd == I915_READ(MIPI_DPI_CONTROL(port)))
 277                 DRM_ERROR("Same special packet %02x twice in a row.\n", cmd);
 278
 279         I915_WRITE(MIPI_DPI_CONTROL(port), cmd);
 280
 281         mask = SPL_PKT_SENT_INTERRUPT;
 282         if (intel_wait_for_register(dev_priv,
 283                                     MIPI_INTR_STAT(port), mask, mask,
 284                                     100))
 285                 DRM_ERROR("Video mode command 0x%08x send failed.\n", cmd);
 286
 287         return 0;
 288 }
 289
 290 static void band_gap_reset(struct drm_i915_private *dev_priv)
 291 {
 292         mutex_lock(&dev_priv->sb_lock);
 293
 294         vlv_flisdsi_write(dev_priv, 0x08, 0x0001);
 295         vlv_flisdsi_write(dev_priv, 0x0F, 0x0005);
 296         vlv_flisdsi_write(dev_priv, 0x0F, 0x0025);
 297         udelay(150);
 298         vlv_flisdsi_write(dev_priv, 0x0F, 0x0000);
 299         vlv_flisdsi_write(dev_priv, 0x08, 0x0000);
 300
 301         mutex_unlock(&dev_priv->sb_lock);
 302 }
 303
 304 static inline bool is_vid_mode(struct intel_dsi *intel_dsi)
 305 {
 306         return intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE;
 307 }
 308
 309 static inline bool is_cmd_mode(struct intel_dsi *intel_dsi)
 310 {
 311         return intel_dsi->operation_mode == INTEL_DSI_COMMAND_MODE;
 312 }
 313
 314 static bool intel_dsi_compute_config(struct intel_encoder *encoder,
 315                                      struct intel_crtc_state *pipe_config)
 316 {
 317         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 318         struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
 319                                                    base);
 320         struct intel_connector *intel_connector = intel_dsi->attached_connector;
 321         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
 322         const struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 323         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
 324         int ret;
 325
 326         DRM_DEBUG_KMS("\n");
 327
 328         pipe_config->has_dsi_encoder = true;
 329
 330         if (fixed_mode) {
 331                 intel_fixed_panel_mode(fixed_mode, adjusted_mode);
 332
 333                 if (HAS_GMCH_DISPLAY(dev_priv))
 334                         intel_gmch_panel_fitting(crtc, pipe_config,
 335                                                  intel_connector->panel.fitting_mode);
 336                 else
 337                         intel_pch_panel_fitting(crtc, pipe_config,
 338                                                 intel_connector->panel.fitting_mode);
 339         }
 340
 341         /* DSI uses short packets for sync events, so clear mode flags for DSI */
 342         adjusted_mode->flags = 0;
 343
 344         if (IS_BROXTON(dev_priv)) {
 345                 /* Dual link goes to DSI transcoder A. */
 346                 if (intel_dsi->ports == BIT(PORT_C))
 347                         pipe_config->cpu_transcoder = TRANSCODER_DSI_C;
 348                 else
 349                         pipe_config->cpu_transcoder = TRANSCODER_DSI_A;
 350         }
 351
 352         ret = intel_compute_dsi_pll(encoder, pipe_config);
 353         if (ret)
 354                 return false;
 355
 356         pipe_config->clock_set = true;
 357
 358         return true;
 359 }
 360
 361 static void bxt_dsi_device_ready(struct intel_encoder *encoder)
 362 {
 363         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 364         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 365         enum port port;
 366         u32 val;
 367
 368         DRM_DEBUG_KMS("\n");
 369
 370         /* Exit Low power state in 4 steps*/
 371         for_each_dsi_port(port, intel_dsi->ports) {
 372
 373                 /* 1. Enable MIPI PHY transparent latch */
 374                 val = I915_READ(BXT_MIPI_PORT_CTRL(port));
 375                 I915_WRITE(BXT_MIPI_PORT_CTRL(port), val | LP_OUTPUT_HOLD);
 376                 usleep_range(2000, 2500);
 377
 378                 /* 2. Enter ULPS */
 379                 val = I915_READ(MIPI_DEVICE_READY(port));
 380                 val &= ~ULPS_STATE_MASK;
 381                 val |= (ULPS_STATE_ENTER | DEVICE_READY);
 382                 I915_WRITE(MIPI_DEVICE_READY(port), val);
 383                 usleep_range(2, 3);
 384
 385                 /* 3. Exit ULPS */
 386                 val = I915_READ(MIPI_DEVICE_READY(port));
 387                 val &= ~ULPS_STATE_MASK;
 388                 val |= (ULPS_STATE_EXIT | DEVICE_READY);
 389                 I915_WRITE(MIPI_DEVICE_READY(port), val);
 390                 usleep_range(1000, 1500);
 391
 392                 /* Clear ULPS and set device ready */
 393                 val = I915_READ(MIPI_DEVICE_READY(port));
 394                 val &= ~ULPS_STATE_MASK;
 395                 val |= DEVICE_READY;
 396                 I915_WRITE(MIPI_DEVICE_READY(port), val);
 397         }
 398 }
 399
 400 static void vlv_dsi_device_ready(struct intel_encoder *encoder)
 401 {
 402         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 403         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 404         enum port port;
 405         u32 val;
 406
 407         DRM_DEBUG_KMS("\n");
 408
 409         mutex_lock(&dev_priv->sb_lock);
 410         /* program rcomp for compliance, reduce from 50 ohms to 45 ohms
 411          * needed everytime after power gate */
 412         vlv_flisdsi_write(dev_priv, 0x04, 0x0004);
 413         mutex_unlock(&dev_priv->sb_lock);
 414
 415         /* bandgap reset is needed after everytime we do power gate */
 416         band_gap_reset(dev_priv);
 417
 418         for_each_dsi_port(port, intel_dsi->ports) {
 419
 420                 I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_ENTER);
 421                 usleep_range(2500, 3000);
 422
 423                 /* Enable MIPI PHY transparent latch
 424                  * Common bit for both MIPI Port A & MIPI Port C
 425                  * No similar bit in MIPI Port C reg
 426                  */
 427                 val = I915_READ(MIPI_PORT_CTRL(PORT_A));
 428                 I915_WRITE(MIPI_PORT_CTRL(PORT_A), val | LP_OUTPUT_HOLD);
 429                 usleep_range(1000, 1500);
 430
 431                 I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_EXIT);
 432                 usleep_range(2500, 3000);
 433
 434                 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY);
 435                 usleep_range(2500, 3000);
 436         }
 437 }
 438
 439 static void intel_dsi_device_ready(struct intel_encoder *encoder)
 440 {
 441         struct drm_device *dev = encoder->base.dev;
 442
 443         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 444                 vlv_dsi_device_ready(encoder);
 445         else if (IS_BROXTON(dev))
 446                 bxt_dsi_device_ready(encoder);
 447 }
 448
 449 static void intel_dsi_port_enable(struct intel_encoder *encoder)
 450 {
 451         struct drm_device *dev = encoder->base.dev;
 452         struct drm_i915_private *dev_priv = dev->dev_private;
 453         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 454         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 455         enum port port;
 456
 457         if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
 458                 u32 temp;
 459
 460                 temp = I915_READ(VLV_CHICKEN_3);
 461                 temp &= ~PIXEL_OVERLAP_CNT_MASK |
 462                                         intel_dsi->pixel_overlap <<
 463                                         PIXEL_OVERLAP_CNT_SHIFT;
 464                 I915_WRITE(VLV_CHICKEN_3, temp);
 465         }
 466
 467         for_each_dsi_port(port, intel_dsi->ports) {
 468                 i915_reg_t port_ctrl = IS_BROXTON(dev) ?
 469                         BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
 470                 u32 temp;
 471
 472                 temp = I915_READ(port_ctrl);
 473
 474                 temp &= ~LANE_CONFIGURATION_MASK;
 475                 temp &= ~DUAL_LINK_MODE_MASK;
 476
 477                 if (intel_dsi->ports == (BIT(PORT_A) | BIT(PORT_C))) {
 478                         temp |= (intel_dsi->dual_link - 1)
 479                                                 << DUAL_LINK_MODE_SHIFT;
 480                         temp |= intel_crtc->pipe ?
 481                                         LANE_CONFIGURATION_DUAL_LINK_B :
 482                                         LANE_CONFIGURATION_DUAL_LINK_A;
 483                 }
 484                 /* assert ip_tg_enable signal */
 485                 I915_WRITE(port_ctrl, temp | DPI_ENABLE);
 486                 POSTING_READ(port_ctrl);
 487         }
 488 }
 489
 490 static void intel_dsi_port_disable(struct intel_encoder *encoder)
 491 {
 492         struct drm_device *dev = encoder->base.dev;
 493         struct drm_i915_private *dev_priv = dev->dev_private;
 494         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 495         enum port port;
 496
 497         for_each_dsi_port(port, intel_dsi->ports) {
 498                 i915_reg_t port_ctrl = IS_BROXTON(dev) ?
 499                         BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
 500                 u32 temp;
 501
 502                 /* de-assert ip_tg_enable signal */
 503                 temp = I915_READ(port_ctrl);
 504                 I915_WRITE(port_ctrl, temp & ~DPI_ENABLE);
 505                 POSTING_READ(port_ctrl);
 506         }
 507 }
 508
 509 static void intel_dsi_enable(struct intel_encoder *encoder)
 510 {
 511         struct drm_device *dev = encoder->base.dev;
 512         struct drm_i915_private *dev_priv = dev->dev_private;
 513         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 514         enum port port;
 515
 516         DRM_DEBUG_KMS("\n");
 517
 518         if (is_cmd_mode(intel_dsi)) {
 519                 for_each_dsi_port(port, intel_dsi->ports)
 520                         I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4);
 521         } else {
 522                 msleep(20); /* XXX */
 523                 for_each_dsi_port(port, intel_dsi->ports)
 524                         dpi_send_cmd(intel_dsi, TURN_ON, false, port);
 525                 msleep(100);
 526
 527                 drm_panel_enable(intel_dsi->panel);
 528
 529                 for_each_dsi_port(port, intel_dsi->ports)
 530                         wait_for_dsi_fifo_empty(intel_dsi, port);
 531
 532                 intel_dsi_port_enable(encoder);
 533         }
 534
 535         intel_panel_enable_backlight(intel_dsi->attached_connector);
 536 }
 537
 538 static void intel_dsi_prepare(struct intel_encoder *intel_encoder);
 539
 540 static void intel_dsi_pre_enable(struct intel_encoder *encoder)
 541 {
 542         struct drm_device *dev = encoder->base.dev;
 543         struct drm_i915_private *dev_priv = dev->dev_private;
 544         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 545         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
 546         enum port port;
 547
 548         DRM_DEBUG_KMS("\n");
 549
 550         /*
 551          * The BIOS may leave the PLL in a wonky state where it doesn't
 552          * lock. It needs to be fully powered down to fix it.
 553          */
 554         intel_disable_dsi_pll(encoder);
 555         intel_enable_dsi_pll(encoder, crtc->config);
 556
 557         intel_dsi_prepare(encoder);
 558
 559         /* Panel Enable over CRC PMIC */
 560         if (intel_dsi->gpio_panel)
 561                 gpiod_set_value_cansleep(intel_dsi->gpio_panel, 1);
 562
 563         msleep(intel_dsi->panel_on_delay);
 564
 565         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 566                 u32 val;
 567
 568                 /* Disable DPOunit clock gating, can stall pipe */
 569                 val = I915_READ(DSPCLK_GATE_D);
 570                 val |= DPOUNIT_CLOCK_GATE_DISABLE;
 571                 I915_WRITE(DSPCLK_GATE_D, val);
 572         }
 573
 574         /* put device in ready state */
 575         intel_dsi_device_ready(encoder);
 576
 577         drm_panel_prepare(intel_dsi->panel);
 578
 579         for_each_dsi_port(port, intel_dsi->ports)
 580                 wait_for_dsi_fifo_empty(intel_dsi, port);
 581
 582         /* Enable port in pre-enable phase itself because as per hw team
 583          * recommendation, port should be enabled befor plane & pipe */
 584         intel_dsi_enable(encoder);
 585 }
 586
 587 static void intel_dsi_enable_nop(struct intel_encoder *encoder)
 588 {
 589         DRM_DEBUG_KMS("\n");
 590
 591         /* for DSI port enable has to be done before pipe
 592          * and plane enable, so port enable is done in
 593          * pre_enable phase itself unlike other encoders
 594          */
 595 }
 596
 597 static void intel_dsi_pre_disable(struct intel_encoder *encoder)
 598 {
 599         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 600         enum port port;
 601
 602         DRM_DEBUG_KMS("\n");
 603
 604         intel_panel_disable_backlight(intel_dsi->attached_connector);
 605
 606         if (is_vid_mode(intel_dsi)) {
 607                 /* Send Shutdown command to the panel in LP mode */
 608                 for_each_dsi_port(port, intel_dsi->ports)
 609                         dpi_send_cmd(intel_dsi, SHUTDOWN, false, port);
 610                 msleep(10);
 611         }
 612 }
 613
 614 static void intel_dsi_disable(struct intel_encoder *encoder)
 615 {
 616         struct drm_device *dev = encoder->base.dev;
 617         struct drm_i915_private *dev_priv = dev->dev_private;
 618         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 619         enum port port;
 620         u32 temp;
 621
 622         DRM_DEBUG_KMS("\n");
 623
 624         if (is_vid_mode(intel_dsi)) {
 625                 for_each_dsi_port(port, intel_dsi->ports)
 626                         wait_for_dsi_fifo_empty(intel_dsi, port);
 627
 628                 intel_dsi_port_disable(encoder);
 629                 msleep(2);
 630         }
 631
 632         for_each_dsi_port(port, intel_dsi->ports) {
 633                 /* Panel commands can be sent when clock is in LP11 */
 634                 I915_WRITE(MIPI_DEVICE_READY(port), 0x0);
 635
 636                 intel_dsi_reset_clocks(encoder, port);
 637                 I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
 638
 639                 temp = I915_READ(MIPI_DSI_FUNC_PRG(port));
 640                 temp &= ~VID_MODE_FORMAT_MASK;
 641                 I915_WRITE(MIPI_DSI_FUNC_PRG(port), temp);
 642
 643                 I915_WRITE(MIPI_DEVICE_READY(port), 0x1);
 644         }
 645         /* if disable packets are sent before sending shutdown packet then in
 646          * some next enable sequence send turn on packet error is observed */
 647         drm_panel_disable(intel_dsi->panel);
 648
 649         for_each_dsi_port(port, intel_dsi->ports)
 650                 wait_for_dsi_fifo_empty(intel_dsi, port);
 651 }
 652
 653 static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
 654 {
 655         struct drm_device *dev = encoder->base.dev;
 656         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 657         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 658         enum port port;
 659
 660         DRM_DEBUG_KMS("\n");
 661         for_each_dsi_port(port, intel_dsi->ports) {
 662                 /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */
 663                 i915_reg_t port_ctrl = IS_BROXTON(dev) ?
 664                         BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(PORT_A);
 665                 u32 val;
 666
 667                 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
 668                                                         ULPS_STATE_ENTER);
 669                 usleep_range(2000, 2500);
 670
 671                 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
 672                                                         ULPS_STATE_EXIT);
 673                 usleep_range(2000, 2500);
 674
 675                 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
 676                                                         ULPS_STATE_ENTER);
 677                 usleep_range(2000, 2500);
 678
 679                 /* Wait till Clock lanes are in LP-00 state for MIPI Port A
 680                  * only. MIPI Port C has no similar bit for checking
 681                  */
 682                 if (intel_wait_for_register(dev_priv,
 683                                             port_ctrl, AFE_LATCHOUT, 0,
 684                                             30))
 685                         DRM_ERROR("DSI LP not going Low\n");
 686
 687                 /* Disable MIPI PHY transparent latch */
 688                 val = I915_READ(port_ctrl);
 689                 I915_WRITE(port_ctrl, val & ~LP_OUTPUT_HOLD);
 690                 usleep_range(1000, 1500);
 691
 692                 I915_WRITE(MIPI_DEVICE_READY(port), 0x00);
 693                 usleep_range(2000, 2500);
 694         }
 695
 696         intel_disable_dsi_pll(encoder);
 697 }
 698
 699 static void intel_dsi_post_disable(struct intel_encoder *encoder)
 700 {
 701         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 702         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 703
 704         DRM_DEBUG_KMS("\n");
 705
 706         intel_dsi_disable(encoder);
 707
 708         intel_dsi_clear_device_ready(encoder);
 709
 710         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 711                 u32 val;
 712
 713                 val = I915_READ(DSPCLK_GATE_D);
 714                 val &= ~DPOUNIT_CLOCK_GATE_DISABLE;
 715                 I915_WRITE(DSPCLK_GATE_D, val);
 716         }
 717
 718         drm_panel_unprepare(intel_dsi->panel);
 719
 720         msleep(intel_dsi->panel_off_delay);
 721
 722         /* Panel Disable over CRC PMIC */
 723         if (intel_dsi->gpio_panel)
 724                 gpiod_set_value_cansleep(intel_dsi->gpio_panel, 0);
 725
 726         /*
 727          * FIXME As we do with eDP, just make a note of the time here
 728          * and perform the wait before the next panel power on.
 729          */
 730         msleep(intel_dsi->panel_pwr_cycle_delay);
 731 }
 732
 733 static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
 734                                    enum pipe *pipe)
 735 {
 736         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 737         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 738         struct drm_device *dev = encoder->base.dev;
 739         enum intel_display_power_domain power_domain;
 740         enum port port;
 741         bool active = false;
 742
 743         DRM_DEBUG_KMS("\n");
 744
 745         power_domain = intel_display_port_power_domain(encoder);
 746         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
 747                 return false;
 748
 749         /*
 750          * On Broxton the PLL needs to be enabled with a valid divider
 751          * configuration, otherwise accessing DSI registers will hang the
 752          * machine. See BSpec North Display Engine registers/MIPI[BXT].
 753          */
 754         if (IS_BROXTON(dev_priv) && !intel_dsi_pll_is_enabled(dev_priv))
 755                 goto out_put_power;
 756
 757         /* XXX: this only works for one DSI output */
 758         for_each_dsi_port(port, intel_dsi->ports) {
 759                 i915_reg_t ctrl_reg = IS_BROXTON(dev) ?
 760                         BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
 761                 bool enabled = I915_READ(ctrl_reg) & DPI_ENABLE;
 762
 763                 /*
 764                  * Due to some hardware limitations on VLV/CHV, the DPI enable
 765                  * bit in port C control register does not get set. As a
 766                  * workaround, check pipe B conf instead.
 767                  */
 768                 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && port == PORT_C)
 769                         enabled = I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE;
 770
 771                 /* Try command mode if video mode not enabled */
 772                 if (!enabled) {
 773                         u32 tmp = I915_READ(MIPI_DSI_FUNC_PRG(port));
 774                         enabled = tmp & CMD_MODE_DATA_WIDTH_MASK;
 775                 }
 776
 777                 if (!enabled)
 778                         continue;
 779
 780                 if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY))
 781                         continue;
 782
 783                 if (IS_BROXTON(dev_priv)) {
 784                         u32 tmp = I915_READ(MIPI_CTRL(port));
 785                         tmp &= BXT_PIPE_SELECT_MASK;
 786                         tmp >>= BXT_PIPE_SELECT_SHIFT;
 787
 788                         if (WARN_ON(tmp > PIPE_C))
 789                                 continue;
 790
 791                         *pipe = tmp;
 792                 } else {
 793                         *pipe = port == PORT_A ? PIPE_A : PIPE_B;
 794                 }
 795
 796                 active = true;
 797                 break;
 798         }
 799
 800 out_put_power:
 801         intel_display_power_put(dev_priv, power_domain);
 802
 803         return active;
 804 }
 805
 806 static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder,
 807                                  struct intel_crtc_state *pipe_config)
 808 {
 809         struct drm_device *dev = encoder->base.dev;
 810         struct drm_i915_private *dev_priv = dev->dev_private;
 811         struct drm_display_mode *adjusted_mode =
 812                                         &pipe_config->base.adjusted_mode;
 813         struct drm_display_mode *adjusted_mode_sw;
 814         struct intel_crtc *intel_crtc;
 815         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 816         unsigned int lane_count = intel_dsi->lane_count;
 817         unsigned int bpp, fmt;
 818         enum port port;
 819         u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
 820         u16 hfp_sw, hsync_sw, hbp_sw;
 821         u16 crtc_htotal_sw, crtc_hsync_start_sw, crtc_hsync_end_sw,
 822                                 crtc_hblank_start_sw, crtc_hblank_end_sw;
 823
 824         intel_crtc = to_intel_crtc(encoder->base.crtc);
 825         adjusted_mode_sw = &intel_crtc->config->base.adjusted_mode;
 826
 827         /*
 828          * Atleast one port is active as encoder->get_config called only if
 829          * encoder->get_hw_state() returns true.
 830          */
 831         for_each_dsi_port(port, intel_dsi->ports) {
 832                 if (I915_READ(BXT_MIPI_PORT_CTRL(port)) & DPI_ENABLE)
 833                         break;
 834         }
 835
 836         fmt = I915_READ(MIPI_DSI_FUNC_PRG(port)) & VID_MODE_FORMAT_MASK;
 837         pipe_config->pipe_bpp =
 838                         mipi_dsi_pixel_format_to_bpp(
 839                                 pixel_format_from_register_bits(fmt));
 840         bpp = pipe_config->pipe_bpp;
 841
 842         /* In terms of pixels */
 843         adjusted_mode->crtc_hdisplay =
 844                                 I915_READ(BXT_MIPI_TRANS_HACTIVE(port));
 845         adjusted_mode->crtc_vdisplay =
 846                                 I915_READ(BXT_MIPI_TRANS_VACTIVE(port));
 847         adjusted_mode->crtc_vtotal =
 848                                 I915_READ(BXT_MIPI_TRANS_VTOTAL(port));
 849
 850         hactive = adjusted_mode->crtc_hdisplay;
 851         hfp = I915_READ(MIPI_HFP_COUNT(port));
 852
 853         /*
 854          * Meaningful for video mode non-burst sync pulse mode only,
 855          * can be zero for non-burst sync events and burst modes
 856          */
 857         hsync = I915_READ(MIPI_HSYNC_PADDING_COUNT(port));
 858         hbp = I915_READ(MIPI_HBP_COUNT(port));
 859
 860         /* harizontal values are in terms of high speed byte clock */
 861         hfp = pixels_from_txbyteclkhs(hfp, bpp, lane_count,
 862                                                 intel_dsi->burst_mode_ratio);
 863         hsync = pixels_from_txbyteclkhs(hsync, bpp, lane_count,
 864                                                 intel_dsi->burst_mode_ratio);
 865         hbp = pixels_from_txbyteclkhs(hbp, bpp, lane_count,
 866                                                 intel_dsi->burst_mode_ratio);
 867
 868         if (intel_dsi->dual_link) {
 869                 hfp *= 2;
 870                 hsync *= 2;
 871                 hbp *= 2;
 872         }
 873
 874         /* vertical values are in terms of lines */
 875         vfp = I915_READ(MIPI_VFP_COUNT(port));
 876         vsync = I915_READ(MIPI_VSYNC_PADDING_COUNT(port));
 877         vbp = I915_READ(MIPI_VBP_COUNT(port));
 878
 879         adjusted_mode->crtc_htotal = hactive + hfp + hsync + hbp;
 880         adjusted_mode->crtc_hsync_start = hfp + adjusted_mode->crtc_hdisplay;
 881         adjusted_mode->crtc_hsync_end = hsync + adjusted_mode->crtc_hsync_start;
 882         adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay;
 883         adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal;
 884
 885         adjusted_mode->crtc_vsync_start = vfp + adjusted_mode->crtc_vdisplay;
 886         adjusted_mode->crtc_vsync_end = vsync + adjusted_mode->crtc_vsync_start;
 887         adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay;
 888         adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal;
 889
 890         /*
 891          * In BXT DSI there is no regs programmed with few horizontal timings
 892          * in Pixels but txbyteclkhs.. So retrieval process adds some
 893          * ROUND_UP ERRORS in the process of PIXELS<==>txbyteclkhs.
 894          * Actually here for the given adjusted_mode, we are calculating the
 895          * value programmed to the port and then back to the horizontal timing
 896          * param in pixels. This is the expected value, including roundup errors
 897          * And if that is same as retrieved value from port, then
 898          * (HW state) adjusted_mode's horizontal timings are corrected to
 899          * match with SW state to nullify the errors.
 900          */
 901         /* Calculating the value programmed to the Port register */
 902         hfp_sw = adjusted_mode_sw->crtc_hsync_start -
 903                                         adjusted_mode_sw->crtc_hdisplay;
 904         hsync_sw = adjusted_mode_sw->crtc_hsync_end -
 905                                         adjusted_mode_sw->crtc_hsync_start;
 906         hbp_sw = adjusted_mode_sw->crtc_htotal -
 907                                         adjusted_mode_sw->crtc_hsync_end;
 908
 909         if (intel_dsi->dual_link) {
 910                 hfp_sw /= 2;
 911                 hsync_sw /= 2;
 912                 hbp_sw /= 2;
 913         }
 914
 915         hfp_sw = txbyteclkhs(hfp_sw, bpp, lane_count,
 916                                                 intel_dsi->burst_mode_ratio);
 917         hsync_sw = txbyteclkhs(hsync_sw, bpp, lane_count,
 918                             intel_dsi->burst_mode_ratio);
 919         hbp_sw = txbyteclkhs(hbp_sw, bpp, lane_count,
 920                                                 intel_dsi->burst_mode_ratio);
 921
 922         /* Reverse calculating the adjusted mode parameters from port reg vals*/
 923         hfp_sw = pixels_from_txbyteclkhs(hfp_sw, bpp, lane_count,
 924                                                 intel_dsi->burst_mode_ratio);
 925         hsync_sw = pixels_from_txbyteclkhs(hsync_sw, bpp, lane_count,
 926                                                 intel_dsi->burst_mode_ratio);
 927         hbp_sw = pixels_from_txbyteclkhs(hbp_sw, bpp, lane_count,
 928                                                 intel_dsi->burst_mode_ratio);
 929
 930         if (intel_dsi->dual_link) {
 931                 hfp_sw *= 2;
 932                 hsync_sw *= 2;
 933                 hbp_sw *= 2;
 934         }
 935
 936         crtc_htotal_sw = adjusted_mode_sw->crtc_hdisplay + hfp_sw +
 937                                                         hsync_sw + hbp_sw;
 938         crtc_hsync_start_sw = hfp_sw + adjusted_mode_sw->crtc_hdisplay;
 939         crtc_hsync_end_sw = hsync_sw + crtc_hsync_start_sw;
 940         crtc_hblank_start_sw = adjusted_mode_sw->crtc_hdisplay;
 941         crtc_hblank_end_sw = crtc_htotal_sw;
 942
 943         if (adjusted_mode->crtc_htotal == crtc_htotal_sw)
 944                 adjusted_mode->crtc_htotal = adjusted_mode_sw->crtc_htotal;
 945
 946         if (adjusted_mode->crtc_hsync_start == crtc_hsync_start_sw)
 947                 adjusted_mode->crtc_hsync_start =
 948                                         adjusted_mode_sw->crtc_hsync_start;
 949
 950         if (adjusted_mode->crtc_hsync_end == crtc_hsync_end_sw)
 951                 adjusted_mode->crtc_hsync_end =
 952                                         adjusted_mode_sw->crtc_hsync_end;
 953
 954         if (adjusted_mode->crtc_hblank_start == crtc_hblank_start_sw)
 955                 adjusted_mode->crtc_hblank_start =
 956                                         adjusted_mode_sw->crtc_hblank_start;
 957
 958         if (adjusted_mode->crtc_hblank_end == crtc_hblank_end_sw)
 959                 adjusted_mode->crtc_hblank_end =
 960                                         adjusted_mode_sw->crtc_hblank_end;
 961 }
 962
 963 static void intel_dsi_get_config(struct intel_encoder *encoder,
 964                                  struct intel_crtc_state *pipe_config)
 965 {
 966         struct drm_device *dev = encoder->base.dev;
 967         u32 pclk;
 968         DRM_DEBUG_KMS("\n");
 969
 970         pipe_config->has_dsi_encoder = true;
 971
 972         if (IS_BROXTON(dev))
 973                 bxt_dsi_get_pipe_config(encoder, pipe_config);
 974
 975         pclk = intel_dsi_get_pclk(encoder, pipe_config->pipe_bpp,
 976                                   pipe_config);
 977         if (!pclk)
 978                 return;
 979
 980         pipe_config->base.adjusted_mode.crtc_clock = pclk;
 981         pipe_config->port_clock = pclk;
 982 }
 983
 984 static enum drm_mode_status
 985 intel_dsi_mode_valid(struct drm_connector *connector,
 986                      struct drm_display_mode *mode)
 987 {
 988         struct intel_connector *intel_connector = to_intel_connector(connector);
 989         const struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 990         int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
 991
 992         DRM_DEBUG_KMS("\n");
 993
 994         if (mode->flags & DRM_MODE_FLAG_DBLSCAN) {
 995                 DRM_DEBUG_KMS("MODE_NO_DBLESCAN\n");
 996                 return MODE_NO_DBLESCAN;
 997         }
 998
 999         if (fixed_mode) {
1000                 if (mode->hdisplay > fixed_mode->hdisplay)
1001                         return MODE_PANEL;
1002                 if (mode->vdisplay > fixed_mode->vdisplay)
1003                         return MODE_PANEL;
1004                 if (fixed_mode->clock > max_dotclk)
1005                         return MODE_CLOCK_HIGH;
1006         }
1007
1008         return MODE_OK;
1009 }
1010
1011 /* return txclkesc cycles in terms of divider and duration in us */
1012 static u16 txclkesc(u32 divider, unsigned int us)
1013 {
1014         switch (divider) {
1015         case ESCAPE_CLOCK_DIVIDER_1:
1016         default:
1017                 return 20 * us;
1018         case ESCAPE_CLOCK_DIVIDER_2:
1019                 return 10 * us;
1020         case ESCAPE_CLOCK_DIVIDER_4:
1021                 return 5 * us;
1022         }
1023 }
1024
1025 static void set_dsi_timings(struct drm_encoder *encoder,
1026                             const struct drm_display_mode *adjusted_mode)
1027 {
1028         struct drm_device *dev = encoder->dev;
1029         struct drm_i915_private *dev_priv = dev->dev_private;
1030         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1031         enum port port;
1032         unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
1033         unsigned int lane_count = intel_dsi->lane_count;
1034
1035         u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
1036
1037         hactive = adjusted_mode->crtc_hdisplay;
1038         hfp = adjusted_mode->crtc_hsync_start - adjusted_mode->crtc_hdisplay;
1039         hsync = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
1040         hbp = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_end;
1041
1042         if (intel_dsi->dual_link) {
1043                 hactive /= 2;
1044                 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
1045                         hactive += intel_dsi->pixel_overlap;
1046                 hfp /= 2;
1047                 hsync /= 2;
1048                 hbp /= 2;
1049         }
1050
1051         vfp = adjusted_mode->crtc_vsync_start - adjusted_mode->crtc_vdisplay;
1052         vsync = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
1053         vbp = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_end;
1054
1055         /* horizontal values are in terms of high speed byte clock */
1056         hactive = txbyteclkhs(hactive, bpp, lane_count,
1057                               intel_dsi->burst_mode_ratio);
1058         hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio);
1059         hsync = txbyteclkhs(hsync, bpp, lane_count,
1060                             intel_dsi->burst_mode_ratio);
1061         hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio);
1062
1063         for_each_dsi_port(port, intel_dsi->ports) {
1064                 if (IS_BROXTON(dev)) {
1065                         /*
1066                          * Program hdisplay and vdisplay on MIPI transcoder.
1067                          * This is different from calculated hactive and
1068                          * vactive, as they are calculated per channel basis,
1069                          * whereas these values should be based on resolution.
1070                          */
1071                         I915_WRITE(BXT_MIPI_TRANS_HACTIVE(port),
1072                                    adjusted_mode->crtc_hdisplay);
1073                         I915_WRITE(BXT_MIPI_TRANS_VACTIVE(port),
1074                                    adjusted_mode->crtc_vdisplay);
1075                         I915_WRITE(BXT_MIPI_TRANS_VTOTAL(port),
1076                                    adjusted_mode->crtc_vtotal);
1077                 }
1078
1079                 I915_WRITE(MIPI_HACTIVE_AREA_COUNT(port), hactive);
1080                 I915_WRITE(MIPI_HFP_COUNT(port), hfp);
1081
1082                 /* meaningful for video mode non-burst sync pulse mode only,
1083                  * can be zero for non-burst sync events and burst modes */
1084                 I915_WRITE(MIPI_HSYNC_PADDING_COUNT(port), hsync);
1085                 I915_WRITE(MIPI_HBP_COUNT(port), hbp);
1086
1087                 /* vertical values are in terms of lines */
1088                 I915_WRITE(MIPI_VFP_COUNT(port), vfp);
1089                 I915_WRITE(MIPI_VSYNC_PADDING_COUNT(port), vsync);
1090                 I915_WRITE(MIPI_VBP_COUNT(port), vbp);
1091         }
1092 }
1093
1094 static u32 pixel_format_to_reg(enum mipi_dsi_pixel_format fmt)
1095 {
1096         switch (fmt) {
1097         case MIPI_DSI_FMT_RGB888:
1098                 return VID_MODE_FORMAT_RGB888;
1099         case MIPI_DSI_FMT_RGB666:
1100                 return VID_MODE_FORMAT_RGB666;
1101         case MIPI_DSI_FMT_RGB666_PACKED:
1102                 return VID_MODE_FORMAT_RGB666_PACKED;
1103         case MIPI_DSI_FMT_RGB565:
1104                 return VID_MODE_FORMAT_RGB565;
1105         default:
1106                 MISSING_CASE(fmt);
1107                 return VID_MODE_FORMAT_RGB666;
1108         }
1109 }
1110
1111 static void intel_dsi_prepare(struct intel_encoder *intel_encoder)
1112 {
1113         struct drm_encoder *encoder = &intel_encoder->base;
1114         struct drm_device *dev = encoder->dev;
1115         struct drm_i915_private *dev_priv = dev->dev_private;
1116         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
1117         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1118         const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
1119         enum port port;
1120         unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
1121         u32 val, tmp;
1122         u16 mode_hdisplay;
1123
1124         DRM_DEBUG_KMS("pipe %c\n", pipe_name(intel_crtc->pipe));
1125
1126         mode_hdisplay = adjusted_mode->crtc_hdisplay;
1127
1128         if (intel_dsi->dual_link) {
1129                 mode_hdisplay /= 2;
1130                 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
1131                         mode_hdisplay += intel_dsi->pixel_overlap;
1132         }
1133
1134         for_each_dsi_port(port, intel_dsi->ports) {
1135                 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1136                         /*
1137                          * escape clock divider, 20MHz, shared for A and C.
1138                          * device ready must be off when doing this! txclkesc?
1139                          */
1140                         tmp = I915_READ(MIPI_CTRL(PORT_A));
1141                         tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
1142                         I915_WRITE(MIPI_CTRL(PORT_A), tmp |
1143                                         ESCAPE_CLOCK_DIVIDER_1);
1144
1145                         /* read request priority is per pipe */
1146                         tmp = I915_READ(MIPI_CTRL(port));
1147                         tmp &= ~READ_REQUEST_PRIORITY_MASK;
1148                         I915_WRITE(MIPI_CTRL(port), tmp |
1149                                         READ_REQUEST_PRIORITY_HIGH);
1150                 } else if (IS_BROXTON(dev)) {
1151                         enum pipe pipe = intel_crtc->pipe;
1152
1153                         tmp = I915_READ(MIPI_CTRL(port));
1154                         tmp &= ~BXT_PIPE_SELECT_MASK;
1155
1156                         tmp |= BXT_PIPE_SELECT(pipe);
1157                         I915_WRITE(MIPI_CTRL(port), tmp);
1158                 }
1159
1160                 /* XXX: why here, why like this? handling in irq handler?! */
1161                 I915_WRITE(MIPI_INTR_STAT(port), 0xffffffff);
1162                 I915_WRITE(MIPI_INTR_EN(port), 0xffffffff);
1163
1164                 I915_WRITE(MIPI_DPHY_PARAM(port), intel_dsi->dphy_reg);
1165
1166                 I915_WRITE(MIPI_DPI_RESOLUTION(port),
1167                         adjusted_mode->crtc_vdisplay << VERTICAL_ADDRESS_SHIFT |
1168                         mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT);
1169         }
1170
1171         set_dsi_timings(encoder, adjusted_mode);
1172
1173         val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT;
1174         if (is_cmd_mode(intel_dsi)) {
1175                 val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT;
1176                 val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */
1177         } else {
1178                 val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT;
1179                 val |= pixel_format_to_reg(intel_dsi->pixel_format);
1180         }
1181
1182         tmp = 0;
1183         if (intel_dsi->eotp_pkt == 0)
1184                 tmp |= EOT_DISABLE;
1185         if (intel_dsi->clock_stop)
1186                 tmp |= CLOCKSTOP;
1187
1188         if (IS_BROXTON(dev_priv)) {
1189                 tmp |= BXT_DPHY_DEFEATURE_EN;
1190                 if (!is_cmd_mode(intel_dsi))
1191                         tmp |= BXT_DEFEATURE_DPI_FIFO_CTR;
1192         }
1193
1194         for_each_dsi_port(port, intel_dsi->ports) {
1195                 I915_WRITE(MIPI_DSI_FUNC_PRG(port), val);
1196
1197                 /* timeouts for recovery. one frame IIUC. if counter expires,
1198                  * EOT and stop state. */
1199
1200                 /*
1201                  * In burst mode, value greater than one DPI line Time in byte
1202                  * clock (txbyteclkhs) To timeout this timer 1+ of the above
1203                  * said value is recommended.
1204                  *
1205                  * In non-burst mode, Value greater than one DPI frame time in
1206                  * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
1207                  * said value is recommended.
1208                  *
1209                  * In DBI only mode, value greater than one DBI frame time in
1210                  * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
1211                  * said value is recommended.
1212                  */
1213
1214                 if (is_vid_mode(intel_dsi) &&
1215                         intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
1216                         I915_WRITE(MIPI_HS_TX_TIMEOUT(port),
1217                                 txbyteclkhs(adjusted_mode->crtc_htotal, bpp,
1218                                             intel_dsi->lane_count,
1219                                             intel_dsi->burst_mode_ratio) + 1);
1220                 } else {
1221                         I915_WRITE(MIPI_HS_TX_TIMEOUT(port),
1222                                 txbyteclkhs(adjusted_mode->crtc_vtotal *
1223                                             adjusted_mode->crtc_htotal,
1224                                             bpp, intel_dsi->lane_count,
1225                                             intel_dsi->burst_mode_ratio) + 1);
1226                 }
1227                 I915_WRITE(MIPI_LP_RX_TIMEOUT(port), intel_dsi->lp_rx_timeout);
1228                 I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(port),
1229                                                 intel_dsi->turn_arnd_val);
1230                 I915_WRITE(MIPI_DEVICE_RESET_TIMER(port),
1231                                                 intel_dsi->rst_timer_val);
1232
1233                 /* dphy stuff */
1234
1235                 /* in terms of low power clock */
1236                 I915_WRITE(MIPI_INIT_COUNT(port),
1237                                 txclkesc(intel_dsi->escape_clk_div, 100));
1238
1239                 if (IS_BROXTON(dev) && (!intel_dsi->dual_link)) {
1240                         /*
1241                          * BXT spec says write MIPI_INIT_COUNT for
1242                          * both the ports, even if only one is
1243                          * getting used. So write the other port
1244                          * if not in dual link mode.
1245                          */
1246                         I915_WRITE(MIPI_INIT_COUNT(port ==
1247                                                 PORT_A ? PORT_C : PORT_A),
1248                                         intel_dsi->init_count);
1249                 }
1250
1251                 /* recovery disables */
1252                 I915_WRITE(MIPI_EOT_DISABLE(port), tmp);
1253
1254                 /* in terms of low power clock */
1255                 I915_WRITE(MIPI_INIT_COUNT(port), intel_dsi->init_count);
1256
1257                 /* in terms of txbyteclkhs. actual high to low switch +
1258                  * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK.
1259                  *
1260                  * XXX: write MIPI_STOP_STATE_STALL?
1261                  */
1262                 I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(port),
1263                                                 intel_dsi->hs_to_lp_count);
1264
1265                 /* XXX: low power clock equivalence in terms of byte clock.
1266                  * the number of byte clocks occupied in one low power clock.
1267                  * based on txbyteclkhs and txclkesc.
1268                  * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL
1269                  * ) / 105.???
1270                  */
1271                 I915_WRITE(MIPI_LP_BYTECLK(port), intel_dsi->lp_byte_clk);
1272
1273                 /* the bw essential for transmitting 16 long packets containing
1274                  * 252 bytes meant for dcs write memory command is programmed in
1275                  * this register in terms of byte clocks. based on dsi transfer
1276                  * rate and the number of lanes configured the time taken to
1277                  * transmit 16 long packets in a dsi stream varies. */
1278                 I915_WRITE(MIPI_DBI_BW_CTRL(port), intel_dsi->bw_timer);
1279
1280                 I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(port),
1281                 intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT |
1282                 intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT);
1283
1284                 if (is_vid_mode(intel_dsi))
1285                         /* Some panels might have resolution which is not a
1286                          * multiple of 64 like 1366 x 768. Enable RANDOM
1287                          * resolution support for such panels by default */
1288                         I915_WRITE(MIPI_VIDEO_MODE_FORMAT(port),
1289                                 intel_dsi->video_frmt_cfg_bits |
1290                                 intel_dsi->video_mode_format |
1291                                 IP_TG_CONFIG |
1292                                 RANDOM_DPI_DISPLAY_RESOLUTION);
1293         }
1294 }
1295
1296 static enum drm_connector_status
1297 intel_dsi_detect(struct drm_connector *connector, bool force)
1298 {
1299         return connector_status_connected;
1300 }
1301
1302 static int intel_dsi_get_modes(struct drm_connector *connector)
1303 {
1304         struct intel_connector *intel_connector = to_intel_connector(connector);
1305         struct drm_display_mode *mode;
1306
1307         DRM_DEBUG_KMS("\n");
1308
1309         if (!intel_connector->panel.fixed_mode) {
1310                 DRM_DEBUG_KMS("no fixed mode\n");
1311                 return 0;
1312         }
1313
1314         mode = drm_mode_duplicate(connector->dev,
1315                                   intel_connector->panel.fixed_mode);
1316         if (!mode) {
1317                 DRM_DEBUG_KMS("drm_mode_duplicate failed\n");
1318                 return 0;
1319         }
1320
1321         drm_mode_probed_add(connector, mode);
1322         return 1;
1323 }
1324
1325 static int intel_dsi_set_property(struct drm_connector *connector,
1326                                   struct drm_property *property,
1327                                   uint64_t val)
1328 {
1329         struct drm_device *dev = connector->dev;
1330         struct intel_connector *intel_connector = to_intel_connector(connector);
1331         struct drm_crtc *crtc;
1332         int ret;
1333
1334         ret = drm_object_property_set_value(&connector->base, property, val);
1335         if (ret)
1336                 return ret;
1337
1338         if (property == dev->mode_config.scaling_mode_property) {
1339                 if (val == DRM_MODE_SCALE_NONE) {
1340                         DRM_DEBUG_KMS("no scaling not supported\n");
1341                         return -EINVAL;
1342                 }
1343                 if (HAS_GMCH_DISPLAY(dev) &&
1344                     val == DRM_MODE_SCALE_CENTER) {
1345                         DRM_DEBUG_KMS("centering not supported\n");
1346                         return -EINVAL;
1347                 }
1348
1349                 if (intel_connector->panel.fitting_mode == val)
1350                         return 0;
1351
1352                 intel_connector->panel.fitting_mode = val;
1353         }
1354
1355         crtc = intel_attached_encoder(connector)->base.crtc;
1356         if (crtc && crtc->state->enable) {
1357                 /*
1358                  * If the CRTC is enabled, the display will be changed
1359                  * according to the new panel fitting mode.
1360                  */
1361                 intel_crtc_restore_mode(crtc);
1362         }
1363
1364         return 0;
1365 }
1366
1367 static void intel_dsi_connector_destroy(struct drm_connector *connector)
1368 {
1369         struct intel_connector *intel_connector = to_intel_connector(connector);
1370
1371         DRM_DEBUG_KMS("\n");
1372         intel_panel_fini(&intel_connector->panel);
1373         drm_connector_cleanup(connector);
1374         kfree(connector);
1375 }
1376
1377 static void intel_dsi_encoder_destroy(struct drm_encoder *encoder)
1378 {
1379         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1380
1381         if (intel_dsi->panel) {
1382                 drm_panel_detach(intel_dsi->panel);
1383                 /* XXX: Logically this call belongs in the panel driver. */
1384                 drm_panel_remove(intel_dsi->panel);
1385         }
1386
1387         /* dispose of the gpios */
1388         if (intel_dsi->gpio_panel)
1389                 gpiod_put(intel_dsi->gpio_panel);
1390
1391         intel_encoder_destroy(encoder);
1392 }
1393
1394 static const struct drm_encoder_funcs intel_dsi_funcs = {
1395         .destroy = intel_dsi_encoder_destroy,
1396 };
1397
1398 static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = {
1399         .get_modes = intel_dsi_get_modes,
1400         .mode_valid = intel_dsi_mode_valid,
1401 };
1402
1403 static const struct drm_connector_funcs intel_dsi_connector_funcs = {
1404         .dpms = drm_atomic_helper_connector_dpms,
1405         .detect = intel_dsi_detect,
1406         .late_register = intel_connector_register,
1407         .early_unregister = intel_connector_unregister,
1408         .destroy = intel_dsi_connector_destroy,
1409         .fill_modes = drm_helper_probe_single_connector_modes,
1410         .set_property = intel_dsi_set_property,
1411         .atomic_get_property = intel_connector_atomic_get_property,
1412         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1413         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1414 };
1415
1416 static void intel_dsi_add_properties(struct intel_connector *connector)
1417 {
1418         struct drm_device *dev = connector->base.dev;
1419
1420         if (connector->panel.fixed_mode) {
1421                 drm_mode_create_scaling_mode_property(dev);
1422                 drm_object_attach_property(&connector->base.base,
1423                                            dev->mode_config.scaling_mode_property,
1424                                            DRM_MODE_SCALE_ASPECT);
1425                 connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
1426         }
1427 }
1428
1429 void intel_dsi_init(struct drm_device *dev)
1430 {
1431         struct intel_dsi *intel_dsi;
1432         struct intel_encoder *intel_encoder;
1433         struct drm_encoder *encoder;
1434         struct intel_connector *intel_connector;
1435         struct drm_connector *connector;
1436         struct drm_display_mode *scan, *fixed_mode = NULL;
1437         struct drm_i915_private *dev_priv = dev->dev_private;
1438         enum port port;
1439         unsigned int i;
1440
1441         DRM_DEBUG_KMS("\n");
1442
1443         /* There is no detection method for MIPI so rely on VBT */
1444         if (!intel_bios_is_dsi_present(dev_priv, &port))
1445                 return;
1446
1447         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1448                 dev_priv->mipi_mmio_base = VLV_MIPI_BASE;
1449         } else if (IS_BROXTON(dev)) {
1450                 dev_priv->mipi_mmio_base = BXT_MIPI_BASE;
1451         } else {
1452                 DRM_ERROR("Unsupported Mipi device to reg base");
1453                 return;
1454         }
1455
1456         intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL);
1457         if (!intel_dsi)
1458                 return;
1459
1460         intel_connector = intel_connector_alloc();
1461         if (!intel_connector) {
1462                 kfree(intel_dsi);
1463                 return;
1464         }
1465
1466         intel_encoder = &intel_dsi->base;
1467         encoder = &intel_encoder->base;
1468         intel_dsi->attached_connector = intel_connector;
1469
1470         connector = &intel_connector->base;
1471
1472         drm_encoder_init(dev, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI,
1473                          "DSI %c", port_name(port));
1474
1475         intel_encoder->compute_config = intel_dsi_compute_config;
1476         intel_encoder->pre_enable = intel_dsi_pre_enable;
1477         intel_encoder->enable = intel_dsi_enable_nop;
1478         intel_encoder->disable = intel_dsi_pre_disable;
1479         intel_encoder->post_disable = intel_dsi_post_disable;
1480         intel_encoder->get_hw_state = intel_dsi_get_hw_state;
1481         intel_encoder->get_config = intel_dsi_get_config;
1482
1483         intel_connector->get_hw_state = intel_connector_get_hw_state;
1484
1485         /*
1486          * On BYT/CHV, pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI
1487          * port C. BXT isn't limited like this.
1488          */
1489         if (IS_BROXTON(dev_priv))
1490                 intel_encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C);
1491         else if (port == PORT_A)
1492                 intel_encoder->crtc_mask = BIT(PIPE_A);
1493         else
1494                 intel_encoder->crtc_mask = BIT(PIPE_B);
1495
1496         if (dev_priv->vbt.dsi.config->dual_link) {
1497                 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_C);
1498
1499                 switch (dev_priv->vbt.dsi.config->dl_dcs_backlight_ports) {
1500                 case DL_DCS_PORT_A:
1501                         intel_dsi->dcs_backlight_ports = BIT(PORT_A);
1502                         break;
1503                 case DL_DCS_PORT_C:
1504                         intel_dsi->dcs_backlight_ports = BIT(PORT_C);
1505                         break;
1506                 default:
1507                 case DL_DCS_PORT_A_AND_C:
1508                         intel_dsi->dcs_backlight_ports = BIT(PORT_A) | BIT(PORT_C);
1509                         break;
1510                 }
1511
1512                 switch (dev_priv->vbt.dsi.config->dl_dcs_cabc_ports) {
1513                 case DL_DCS_PORT_A:
1514                         intel_dsi->dcs_cabc_ports = BIT(PORT_A);
1515                         break;
1516                 case DL_DCS_PORT_C:
1517                         intel_dsi->dcs_cabc_ports = BIT(PORT_C);
1518                         break;
1519                 default:
1520                 case DL_DCS_PORT_A_AND_C:
1521                         intel_dsi->dcs_cabc_ports = BIT(PORT_A) | BIT(PORT_C);
1522                         break;
1523                 }
1524         } else {
1525                 intel_dsi->ports = BIT(port);
1526                 intel_dsi->dcs_backlight_ports = BIT(port);
1527                 intel_dsi->dcs_cabc_ports = BIT(port);
1528         }
1529
1530         if (!dev_priv->vbt.dsi.config->cabc_supported)
1531                 intel_dsi->dcs_cabc_ports = 0;
1532
1533         /* Create a DSI host (and a device) for each port. */
1534         for_each_dsi_port(port, intel_dsi->ports) {
1535                 struct intel_dsi_host *host;
1536
1537                 host = intel_dsi_host_init(intel_dsi, port);
1538                 if (!host)
1539                         goto err;
1540
1541                 intel_dsi->dsi_hosts[port] = host;
1542         }
1543
1544         for (i = 0; i < ARRAY_SIZE(intel_dsi_drivers); i++) {
1545                 intel_dsi->panel = intel_dsi_drivers[i].init(intel_dsi,
1546                                                              intel_dsi_drivers[i].panel_id);
1547                 if (intel_dsi->panel)
1548                         break;
1549         }
1550
1551         if (!intel_dsi->panel) {
1552                 DRM_DEBUG_KMS("no device found\n");
1553                 goto err;
1554         }
1555
1556         /*
1557          * In case of BYT with CRC PMIC, we need to use GPIO for
1558          * Panel control.
1559          */
1560         if (dev_priv->vbt.dsi.config->pwm_blc == PPS_BLC_PMIC) {
1561                 intel_dsi->gpio_panel =
1562                         gpiod_get(dev->dev, "panel", GPIOD_OUT_HIGH);
1563
1564                 if (IS_ERR(intel_dsi->gpio_panel)) {
1565                         DRM_ERROR("Failed to own gpio for panel control\n");
1566                         intel_dsi->gpio_panel = NULL;
1567                 }
1568         }
1569
1570         intel_encoder->type = INTEL_OUTPUT_DSI;
1571         intel_encoder->cloneable = 0;
1572         drm_connector_init(dev, connector, &intel_dsi_connector_funcs,
1573                            DRM_MODE_CONNECTOR_DSI);
1574
1575         drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs);
1576
1577         connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/
1578         connector->interlace_allowed = false;
1579         connector->doublescan_allowed = false;
1580
1581         intel_connector_attach_encoder(intel_connector, intel_encoder);
1582
1583         drm_panel_attach(intel_dsi->panel, connector);
1584
1585         mutex_lock(&dev->mode_config.mutex);
1586         drm_panel_get_modes(intel_dsi->panel);
1587         list_for_each_entry(scan, &connector->probed_modes, head) {
1588                 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
1589                         fixed_mode = drm_mode_duplicate(dev, scan);
1590                         break;
1591                 }
1592         }
1593         mutex_unlock(&dev->mode_config.mutex);
1594
1595         if (!fixed_mode) {
1596                 DRM_DEBUG_KMS("no fixed mode\n");
1597                 goto err;
1598         }
1599
1600         connector->display_info.width_mm = fixed_mode->width_mm;
1601         connector->display_info.height_mm = fixed_mode->height_mm;
1602
1603         intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
1604         intel_panel_setup_backlight(connector, INVALID_PIPE);
1605
1606         intel_dsi_add_properties(intel_connector);
1607
1608         return;
1609
1610 err:
1611         drm_encoder_cleanup(&intel_encoder->base);
1612         kfree(intel_dsi);
1613         kfree(intel_connector);
1614 }