drivers/gpu/drm/i915/intel_fbc.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 /**
  25  * DOC: Frame Buffer Compression (FBC)
  26  *
  27  * FBC tries to save memory bandwidth (and so power consumption) by
  28  * compressing the amount of memory used by the display. It is total
  29  * transparent to user space and completely handled in the kernel.
  30  *
  31  * The benefits of FBC are mostly visible with solid backgrounds and
  32  * variation-less patterns. It comes from keeping the memory footprint small
  33  * and having fewer memory pages opened and accessed for refreshing the display.
  34  *
  35  * i915 is responsible to reserve stolen memory for FBC and configure its
  36  * offset on proper registers. The hardware takes care of all
  37  * compress/decompress. However there are many known cases where we have to
  38  * forcibly disable it to allow proper screen updates.
  39  */
  40
  41 #include "intel_drv.h"
  42 #include "i915_drv.h"
  43
  44 static inline bool fbc_supported(struct drm_i915_private *dev_priv)
  45 {
  46         return HAS_FBC(dev_priv);
  47 }
  48
  49 static inline bool fbc_on_pipe_a_only(struct drm_i915_private *dev_priv)
  50 {
  51         return IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8;
  52 }
  53
  54 static inline bool fbc_on_plane_a_only(struct drm_i915_private *dev_priv)
  55 {
  56         return INTEL_INFO(dev_priv)->gen < 4;
  57 }
  58
  59 static inline bool no_fbc_on_multiple_pipes(struct drm_i915_private *dev_priv)
  60 {
  61         return INTEL_INFO(dev_priv)->gen <= 3;
  62 }
  63
  64 /*
  65  * In some platforms where the CRTC's x:0/y:0 coordinates doesn't match the
  66  * frontbuffer's x:0/y:0 coordinates we lie to the hardware about the plane's
  67  * origin so the x and y offsets can actually fit the registers. As a
  68  * consequence, the fence doesn't really start exactly at the display plane
  69  * address we program because it starts at the real start of the buffer, so we
  70  * have to take this into consideration here.
  71  */
  72 static unsigned int get_crtc_fence_y_offset(struct intel_crtc *crtc)
  73 {
  74         return crtc->base.y - crtc->adjusted_y;
  75 }
  76
  77 /*
  78  * For SKL+, the plane source size used by the hardware is based on the value we
  79  * write to the PLANE_SIZE register. For BDW-, the hardware looks at the value
  80  * we wrote to PIPESRC.
  81  */
  82 static void intel_fbc_get_plane_source_size(struct intel_fbc_state_cache *cache,
  83                                             int *width, int *height)
  84 {
  85         int w, h;
  86
  87         if (intel_rotation_90_or_270(cache->plane.rotation)) {
  88                 w = cache->plane.src_h;
  89                 h = cache->plane.src_w;
  90         } else {
  91                 w = cache->plane.src_w;
  92                 h = cache->plane.src_h;
  93         }
  94
  95         if (width)
  96                 *width = w;
  97         if (height)
  98                 *height = h;
  99 }
 100
 101 static int intel_fbc_calculate_cfb_size(struct drm_i915_private *dev_priv,
 102                                         struct intel_fbc_state_cache *cache)
 103 {
 104         int lines;
 105
 106         intel_fbc_get_plane_source_size(cache, NULL, &lines);
 107         if (INTEL_INFO(dev_priv)->gen >= 7)
 108                 lines = min(lines, 2048);
 109
 110         /* Hardware needs the full buffer stride, not just the active area. */
 111         return lines * cache->fb.stride;
 112 }
 113
 114 static void i8xx_fbc_deactivate(struct drm_i915_private *dev_priv)
 115 {
 116         u32 fbc_ctl;
 117
 118         /* Disable compression */
 119         fbc_ctl = I915_READ(FBC_CONTROL);
 120         if ((fbc_ctl & FBC_CTL_EN) == 0)
 121                 return;
 122
 123         fbc_ctl &= ~FBC_CTL_EN;
 124         I915_WRITE(FBC_CONTROL, fbc_ctl);
 125
 126         /* Wait for compressing bit to clear */
 127         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
 128                 DRM_DEBUG_KMS("FBC idle timed out\n");
 129                 return;
 130         }
 131 }
 132
 133 static void i8xx_fbc_activate(struct drm_i915_private *dev_priv)
 134 {
 135         struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
 136         int cfb_pitch;
 137         int i;
 138         u32 fbc_ctl;
 139
 140         /* Note: fbc.threshold == 1 for i8xx */
 141         cfb_pitch = params->cfb_size / FBC_LL_SIZE;
 142         if (params->fb.stride < cfb_pitch)
 143                 cfb_pitch = params->fb.stride;
 144
 145         /* FBC_CTL wants 32B or 64B units */
 146         if (IS_GEN2(dev_priv))
 147                 cfb_pitch = (cfb_pitch / 32) - 1;
 148         else
 149                 cfb_pitch = (cfb_pitch / 64) - 1;
 150
 151         /* Clear old tags */
 152         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
 153                 I915_WRITE(FBC_TAG(i), 0);
 154
 155         if (IS_GEN4(dev_priv)) {
 156                 u32 fbc_ctl2;
 157
 158                 /* Set it up... */
 159                 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
 160                 fbc_ctl2 |= FBC_CTL_PLANE(params->crtc.plane);
 161                 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
 162                 I915_WRITE(FBC_FENCE_OFF, params->crtc.fence_y_offset);
 163         }
 164
 165         /* enable it... */
 166         fbc_ctl = I915_READ(FBC_CONTROL);
 167         fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT;
 168         fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC;
 169         if (IS_I945GM(dev_priv))
 170                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
 171         fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
 172         fbc_ctl |= params->fb.fence_reg;
 173         I915_WRITE(FBC_CONTROL, fbc_ctl);
 174 }
 175
 176 static bool i8xx_fbc_is_active(struct drm_i915_private *dev_priv)
 177 {
 178         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
 179 }
 180
 181 static void g4x_fbc_activate(struct drm_i915_private *dev_priv)
 182 {
 183         struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
 184         u32 dpfc_ctl;
 185
 186         dpfc_ctl = DPFC_CTL_PLANE(params->crtc.plane) | DPFC_SR_EN;
 187         if (drm_format_plane_cpp(params->fb.pixel_format, 0) == 2)
 188                 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 189         else
 190                 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 191         dpfc_ctl |= DPFC_CTL_FENCE_EN | params->fb.fence_reg;
 192
 193         I915_WRITE(DPFC_FENCE_YOFF, params->crtc.fence_y_offset);
 194
 195         /* enable it... */
 196         I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 197 }
 198
 199 static void g4x_fbc_deactivate(struct drm_i915_private *dev_priv)
 200 {
 201         u32 dpfc_ctl;
 202
 203         /* Disable compression */
 204         dpfc_ctl = I915_READ(DPFC_CONTROL);
 205         if (dpfc_ctl & DPFC_CTL_EN) {
 206                 dpfc_ctl &= ~DPFC_CTL_EN;
 207                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
 208         }
 209 }
 210
 211 static bool g4x_fbc_is_active(struct drm_i915_private *dev_priv)
 212 {
 213         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
 214 }
 215
 216 /* This function forces a CFB recompression through the nuke operation. */
 217 static void intel_fbc_recompress(struct drm_i915_private *dev_priv)
 218 {
 219         I915_WRITE(MSG_FBC_REND_STATE, FBC_REND_NUKE);
 220         POSTING_READ(MSG_FBC_REND_STATE);
 221 }
 222
 223 static void ilk_fbc_activate(struct drm_i915_private *dev_priv)
 224 {
 225         struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
 226         u32 dpfc_ctl;
 227         int threshold = dev_priv->fbc.threshold;
 228
 229         dpfc_ctl = DPFC_CTL_PLANE(params->crtc.plane);
 230         if (drm_format_plane_cpp(params->fb.pixel_format, 0) == 2)
 231                 threshold++;
 232
 233         switch (threshold) {
 234         case 4:
 235         case 3:
 236                 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
 237                 break;
 238         case 2:
 239                 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 240                 break;
 241         case 1:
 242                 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 243                 break;
 244         }
 245         dpfc_ctl |= DPFC_CTL_FENCE_EN;
 246         if (IS_GEN5(dev_priv))
 247                 dpfc_ctl |= params->fb.fence_reg;
 248
 249         I915_WRITE(ILK_DPFC_FENCE_YOFF, params->crtc.fence_y_offset);
 250         I915_WRITE(ILK_FBC_RT_BASE, params->fb.ggtt_offset | ILK_FBC_RT_VALID);
 251         /* enable it... */
 252         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 253
 254         if (IS_GEN6(dev_priv)) {
 255                 I915_WRITE(SNB_DPFC_CTL_SA,
 256                            SNB_CPU_FENCE_ENABLE | params->fb.fence_reg);
 257                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, params->crtc.fence_y_offset);
 258         }
 259
 260         intel_fbc_recompress(dev_priv);
 261 }
 262
 263 static void ilk_fbc_deactivate(struct drm_i915_private *dev_priv)
 264 {
 265         u32 dpfc_ctl;
 266
 267         /* Disable compression */
 268         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
 269         if (dpfc_ctl & DPFC_CTL_EN) {
 270                 dpfc_ctl &= ~DPFC_CTL_EN;
 271                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
 272         }
 273 }
 274
 275 static bool ilk_fbc_is_active(struct drm_i915_private *dev_priv)
 276 {
 277         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
 278 }
 279
 280 static void gen7_fbc_activate(struct drm_i915_private *dev_priv)
 281 {
 282         struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
 283         u32 dpfc_ctl;
 284         int threshold = dev_priv->fbc.threshold;
 285
 286         dpfc_ctl = 0;
 287         if (IS_IVYBRIDGE(dev_priv))
 288                 dpfc_ctl |= IVB_DPFC_CTL_PLANE(params->crtc.plane);
 289
 290         if (drm_format_plane_cpp(params->fb.pixel_format, 0) == 2)
 291                 threshold++;
 292
 293         switch (threshold) {
 294         case 4:
 295         case 3:
 296                 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
 297                 break;
 298         case 2:
 299                 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 300                 break;
 301         case 1:
 302                 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 303                 break;
 304         }
 305
 306         dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
 307
 308         if (dev_priv->fbc.false_color)
 309                 dpfc_ctl |= FBC_CTL_FALSE_COLOR;
 310
 311         if (IS_IVYBRIDGE(dev_priv)) {
 312                 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
 313                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
 314                            I915_READ(ILK_DISPLAY_CHICKEN1) |
 315                            ILK_FBCQ_DIS);
 316         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
 317                 /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
 318                 I915_WRITE(CHICKEN_PIPESL_1(params->crtc.pipe),
 319                            I915_READ(CHICKEN_PIPESL_1(params->crtc.pipe)) |
 320                            HSW_FBCQ_DIS);
 321         }
 322
 323         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 324
 325         I915_WRITE(SNB_DPFC_CTL_SA,
 326                    SNB_CPU_FENCE_ENABLE | params->fb.fence_reg);
 327         I915_WRITE(DPFC_CPU_FENCE_OFFSET, params->crtc.fence_y_offset);
 328
 329         intel_fbc_recompress(dev_priv);
 330 }
 331
 332 static bool intel_fbc_hw_is_active(struct drm_i915_private *dev_priv)
 333 {
 334         if (INTEL_INFO(dev_priv)->gen >= 5)
 335                 return ilk_fbc_is_active(dev_priv);
 336         else if (IS_GM45(dev_priv))
 337                 return g4x_fbc_is_active(dev_priv);
 338         else
 339                 return i8xx_fbc_is_active(dev_priv);
 340 }
 341
 342 static void intel_fbc_hw_activate(struct drm_i915_private *dev_priv)
 343 {
 344         struct intel_fbc *fbc = &dev_priv->fbc;
 345
 346         fbc->active = true;
 347
 348         if (INTEL_INFO(dev_priv)->gen >= 7)
 349                 gen7_fbc_activate(dev_priv);
 350         else if (INTEL_INFO(dev_priv)->gen >= 5)
 351                 ilk_fbc_activate(dev_priv);
 352         else if (IS_GM45(dev_priv))
 353                 g4x_fbc_activate(dev_priv);
 354         else
 355                 i8xx_fbc_activate(dev_priv);
 356 }
 357
 358 static void intel_fbc_hw_deactivate(struct drm_i915_private *dev_priv)
 359 {
 360         struct intel_fbc *fbc = &dev_priv->fbc;
 361
 362         fbc->active = false;
 363
 364         if (INTEL_INFO(dev_priv)->gen >= 5)
 365                 ilk_fbc_deactivate(dev_priv);
 366         else if (IS_GM45(dev_priv))
 367                 g4x_fbc_deactivate(dev_priv);
 368         else
 369                 i8xx_fbc_deactivate(dev_priv);
 370 }
 371
 372 /**
 373  * intel_fbc_is_active - Is FBC active?
 374  * @dev_priv: i915 device instance
 375  *
 376  * This function is used to verify the current state of FBC.
 377  *
 378  * FIXME: This should be tracked in the plane config eventually
 379  * instead of queried at runtime for most callers.
 380  */
 381 bool intel_fbc_is_active(struct drm_i915_private *dev_priv)
 382 {
 383         return dev_priv->fbc.active;
 384 }
 385
 386 static void intel_fbc_work_fn(struct work_struct *__work)
 387 {
 388         struct drm_i915_private *dev_priv =
 389                 container_of(__work, struct drm_i915_private, fbc.work.work);
 390         struct intel_fbc *fbc = &dev_priv->fbc;
 391         struct intel_fbc_work *work = &fbc->work;
 392         struct intel_crtc *crtc = fbc->crtc;
 393         struct drm_vblank_crtc *vblank = &dev_priv->dev->vblank[crtc->pipe];
 394
 395         if (drm_crtc_vblank_get(&crtc->base)) {
 396                 DRM_ERROR("vblank not available for FBC on pipe %c\n",
 397                           pipe_name(crtc->pipe));
 398
 399                 mutex_lock(&fbc->lock);
 400                 work->scheduled = false;
 401                 mutex_unlock(&fbc->lock);
 402                 return;
 403         }
 404
 405 retry:
 406         /* Delay the actual enabling to let pageflipping cease and the
 407          * display to settle before starting the compression. Note that
 408          * this delay also serves a second purpose: it allows for a
 409          * vblank to pass after disabling the FBC before we attempt
 410          * to modify the control registers.
 411          *
 412          * WaFbcWaitForVBlankBeforeEnable:ilk,snb
 413          *
 414          * It is also worth mentioning that since work->scheduled_vblank can be
 415          * updated multiple times by the other threads, hitting the timeout is
 416          * not an error condition. We'll just end up hitting the "goto retry"
 417          * case below.
 418          */
 419         wait_event_timeout(vblank->queue,
 420                 drm_crtc_vblank_count(&crtc->base) != work->scheduled_vblank,
 421                 msecs_to_jiffies(50));
 422
 423         mutex_lock(&fbc->lock);
 424
 425         /* Were we cancelled? */
 426         if (!work->scheduled)
 427                 goto out;
 428
 429         /* Were we delayed again while this function was sleeping? */
 430         if (drm_crtc_vblank_count(&crtc->base) == work->scheduled_vblank) {
 431                 mutex_unlock(&fbc->lock);
 432                 goto retry;
 433         }
 434
 435         intel_fbc_hw_activate(dev_priv);
 436
 437         work->scheduled = false;
 438
 439 out:
 440         mutex_unlock(&fbc->lock);
 441         drm_crtc_vblank_put(&crtc->base);
 442 }
 443
 444 static void intel_fbc_schedule_activation(struct intel_crtc *crtc)
 445 {
 446         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 447         struct intel_fbc *fbc = &dev_priv->fbc;
 448         struct intel_fbc_work *work = &fbc->work;
 449
 450         WARN_ON(!mutex_is_locked(&fbc->lock));
 451
 452         if (drm_crtc_vblank_get(&crtc->base)) {
 453                 DRM_ERROR("vblank not available for FBC on pipe %c\n",
 454                           pipe_name(crtc->pipe));
 455                 return;
 456         }
 457
 458         /* It is useless to call intel_fbc_cancel_work() or cancel_work() in
 459          * this function since we're not releasing fbc.lock, so it won't have an
 460          * opportunity to grab it to discover that it was cancelled. So we just
 461          * update the expected jiffy count. */
 462         work->scheduled = true;
 463         work->scheduled_vblank = drm_crtc_vblank_count(&crtc->base);
 464         drm_crtc_vblank_put(&crtc->base);
 465
 466         schedule_work(&work->work);
 467 }
 468
 469 static void intel_fbc_deactivate(struct drm_i915_private *dev_priv)
 470 {
 471         struct intel_fbc *fbc = &dev_priv->fbc;
 472
 473         WARN_ON(!mutex_is_locked(&fbc->lock));
 474
 475         /* Calling cancel_work() here won't help due to the fact that the work
 476          * function grabs fbc->lock. Just set scheduled to false so the work
 477          * function can know it was cancelled. */
 478         fbc->work.scheduled = false;
 479
 480         if (fbc->active)
 481                 intel_fbc_hw_deactivate(dev_priv);
 482 }
 483
 484 static bool multiple_pipes_ok(struct intel_crtc *crtc)
 485 {
 486         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 487         struct drm_plane *primary = crtc->base.primary;
 488         struct intel_fbc *fbc = &dev_priv->fbc;
 489         enum pipe pipe = crtc->pipe;
 490
 491         /* Don't even bother tracking anything we don't need. */
 492         if (!no_fbc_on_multiple_pipes(dev_priv))
 493                 return true;
 494
 495         WARN_ON(!drm_modeset_is_locked(&primary->mutex));
 496
 497         if (to_intel_plane_state(primary->state)->visible)
 498                 fbc->visible_pipes_mask |= (1 << pipe);
 499         else
 500                 fbc->visible_pipes_mask &= ~(1 << pipe);
 501
 502         return (fbc->visible_pipes_mask & ~(1 << pipe)) != 0;
 503 }
 504
 505 static int find_compression_threshold(struct drm_i915_private *dev_priv,
 506                                       struct drm_mm_node *node,
 507                                       int size,
 508                                       int fb_cpp)
 509 {
 510         struct i915_ggtt *ggtt = &dev_priv->ggtt;
 511         int compression_threshold = 1;
 512         int ret;
 513         u64 end;
 514
 515         /* The FBC hardware for BDW/SKL doesn't have access to the stolen
 516          * reserved range size, so it always assumes the maximum (8mb) is used.
 517          * If we enable FBC using a CFB on that memory range we'll get FIFO
 518          * underruns, even if that range is not reserved by the BIOS. */
 519         if (IS_BROADWELL(dev_priv) ||
 520             IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
 521                 end = ggtt->stolen_size - 8 * 1024 * 1024;
 522         else
 523                 end = ggtt->stolen_usable_size;
 524
 525         /* HACK: This code depends on what we will do in *_enable_fbc. If that
 526          * code changes, this code needs to change as well.
 527          *
 528          * The enable_fbc code will attempt to use one of our 2 compression
 529          * thresholds, therefore, in that case, we only have 1 resort.
 530          */
 531
 532         /* Try to over-allocate to reduce reallocations and fragmentation. */
 533         ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size <<= 1,
 534                                                    4096, 0, end);
 535         if (ret == 0)
 536                 return compression_threshold;
 537
 538 again:
 539         /* HW's ability to limit the CFB is 1:4 */
 540         if (compression_threshold > 4 ||
 541             (fb_cpp == 2 && compression_threshold == 2))
 542                 return 0;
 543
 544         ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size >>= 1,
 545                                                    4096, 0, end);
 546         if (ret && INTEL_INFO(dev_priv)->gen <= 4) {
 547                 return 0;
 548         } else if (ret) {
 549                 compression_threshold <<= 1;
 550                 goto again;
 551         } else {
 552                 return compression_threshold;
 553         }
 554 }
 555
 556 static int intel_fbc_alloc_cfb(struct intel_crtc *crtc)
 557 {
 558         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 559         struct intel_fbc *fbc = &dev_priv->fbc;
 560         struct drm_mm_node *uninitialized_var(compressed_llb);
 561         int size, fb_cpp, ret;
 562
 563         WARN_ON(drm_mm_node_allocated(&fbc->compressed_fb));
 564
 565         size = intel_fbc_calculate_cfb_size(dev_priv, &fbc->state_cache);
 566         fb_cpp = drm_format_plane_cpp(fbc->state_cache.fb.pixel_format, 0);
 567
 568         ret = find_compression_threshold(dev_priv, &fbc->compressed_fb,
 569                                          size, fb_cpp);
 570         if (!ret)
 571                 goto err_llb;
 572         else if (ret > 1) {
 573                 DRM_INFO("Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS.\n");
 574
 575         }
 576
 577         fbc->threshold = ret;
 578
 579         if (INTEL_INFO(dev_priv)->gen >= 5)
 580                 I915_WRITE(ILK_DPFC_CB_BASE, fbc->compressed_fb.start);
 581         else if (IS_GM45(dev_priv)) {
 582                 I915_WRITE(DPFC_CB_BASE, fbc->compressed_fb.start);
 583         } else {
 584                 compressed_llb = kzalloc(sizeof(*compressed_llb), GFP_KERNEL);
 585                 if (!compressed_llb)
 586                         goto err_fb;
 587
 588                 ret = i915_gem_stolen_insert_node(dev_priv, compressed_llb,
 589                                                   4096, 4096);
 590                 if (ret)
 591                         goto err_fb;
 592
 593                 fbc->compressed_llb = compressed_llb;
 594
 595                 I915_WRITE(FBC_CFB_BASE,
 596                            dev_priv->mm.stolen_base + fbc->compressed_fb.start);
 597                 I915_WRITE(FBC_LL_BASE,
 598                            dev_priv->mm.stolen_base + compressed_llb->start);
 599         }
 600
 601         DRM_DEBUG_KMS("reserved %llu bytes of contiguous stolen space for FBC, threshold: %d\n",
 602                       fbc->compressed_fb.size, fbc->threshold);
 603
 604         return 0;
 605
 606 err_fb:
 607         kfree(compressed_llb);
 608         i915_gem_stolen_remove_node(dev_priv, &fbc->compressed_fb);
 609 err_llb:
 610         pr_info_once("drm: not enough stolen space for compressed buffer (need %d more bytes), disabling. Hint: you may be able to increase stolen memory size in the BIOS to avoid this.\n", size);
 611         return -ENOSPC;
 612 }
 613
 614 static void __intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv)
 615 {
 616         struct intel_fbc *fbc = &dev_priv->fbc;
 617
 618         if (drm_mm_node_allocated(&fbc->compressed_fb))
 619                 i915_gem_stolen_remove_node(dev_priv, &fbc->compressed_fb);
 620
 621         if (fbc->compressed_llb) {
 622                 i915_gem_stolen_remove_node(dev_priv, fbc->compressed_llb);
 623                 kfree(fbc->compressed_llb);
 624         }
 625 }
 626
 627 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv)
 628 {
 629         struct intel_fbc *fbc = &dev_priv->fbc;
 630
 631         if (!fbc_supported(dev_priv))
 632                 return;
 633
 634         mutex_lock(&fbc->lock);
 635         __intel_fbc_cleanup_cfb(dev_priv);
 636         mutex_unlock(&fbc->lock);
 637 }
 638
 639 static bool stride_is_valid(struct drm_i915_private *dev_priv,
 640                             unsigned int stride)
 641 {
 642         /* These should have been caught earlier. */
 643         WARN_ON(stride < 512);
 644         WARN_ON((stride & (64 - 1)) != 0);
 645
 646         /* Below are the additional FBC restrictions. */
 647
 648         if (IS_GEN2(dev_priv) || IS_GEN3(dev_priv))
 649                 return stride == 4096 || stride == 8192;
 650
 651         if (IS_GEN4(dev_priv) && !IS_G4X(dev_priv) && stride < 2048)
 652                 return false;
 653
 654         if (stride > 16384)
 655                 return false;
 656
 657         return true;
 658 }
 659
 660 static bool pixel_format_is_valid(struct drm_i915_private *dev_priv,
 661                                   uint32_t pixel_format)
 662 {
 663         switch (pixel_format) {
 664         case DRM_FORMAT_XRGB8888:
 665         case DRM_FORMAT_XBGR8888:
 666                 return true;
 667         case DRM_FORMAT_XRGB1555:
 668         case DRM_FORMAT_RGB565:
 669                 /* 16bpp not supported on gen2 */
 670                 if (IS_GEN2(dev_priv))
 671                         return false;
 672                 /* WaFbcOnly1to1Ratio:ctg */
 673                 if (IS_G4X(dev_priv))
 674                         return false;
 675                 return true;
 676         default:
 677                 return false;
 678         }
 679 }
 680
 681 /*
 682  * For some reason, the hardware tracking starts looking at whatever we
 683  * programmed as the display plane base address register. It does not look at
 684  * the X and Y offset registers. That's why we look at the crtc->adjusted{x,y}
 685  * variables instead of just looking at the pipe/plane size.
 686  */
 687 static bool intel_fbc_hw_tracking_covers_screen(struct intel_crtc *crtc)
 688 {
 689         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 690         struct intel_fbc *fbc = &dev_priv->fbc;
 691         unsigned int effective_w, effective_h, max_w, max_h;
 692
 693         if (INTEL_INFO(dev_priv)->gen >= 8 || IS_HASWELL(dev_priv)) {
 694                 max_w = 4096;
 695                 max_h = 4096;
 696         } else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) {
 697                 max_w = 4096;
 698                 max_h = 2048;
 699         } else {
 700                 max_w = 2048;
 701                 max_h = 1536;
 702         }
 703
 704         intel_fbc_get_plane_source_size(&fbc->state_cache, &effective_w,
 705                                         &effective_h);
 706         effective_w += crtc->adjusted_x;
 707         effective_h += crtc->adjusted_y;
 708
 709         return effective_w <= max_w && effective_h <= max_h;
 710 }
 711
 712 static void intel_fbc_update_state_cache(struct intel_crtc *crtc)
 713 {
 714         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 715         struct intel_fbc *fbc = &dev_priv->fbc;
 716         struct intel_fbc_state_cache *cache = &fbc->state_cache;
 717         struct intel_crtc_state *crtc_state =
 718                 to_intel_crtc_state(crtc->base.state);
 719         struct intel_plane_state *plane_state =
 720                 to_intel_plane_state(crtc->base.primary->state);
 721         struct drm_framebuffer *fb = plane_state->base.fb;
 722         struct drm_i915_gem_object *obj;
 723
 724         WARN_ON(!drm_modeset_is_locked(&crtc->base.mutex));
 725         WARN_ON(!drm_modeset_is_locked(&crtc->base.primary->mutex));
 726
 727         cache->crtc.mode_flags = crtc_state->base.adjusted_mode.flags;
 728         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 729                 cache->crtc.hsw_bdw_pixel_rate =
 730                         ilk_pipe_pixel_rate(crtc_state);
 731
 732         cache->plane.rotation = plane_state->base.rotation;
 733         cache->plane.src_w = drm_rect_width(&plane_state->src) >> 16;
 734         cache->plane.src_h = drm_rect_height(&plane_state->src) >> 16;
 735         cache->plane.visible = plane_state->visible;
 736
 737         if (!cache->plane.visible)
 738                 return;
 739
 740         obj = intel_fb_obj(fb);
 741
 742         /* FIXME: We lack the proper locking here, so only run this on the
 743          * platforms that need. */
 744         if (IS_GEN(dev_priv, 5, 6))
 745                 cache->fb.ilk_ggtt_offset = i915_gem_obj_ggtt_offset(obj);
 746         cache->fb.pixel_format = fb->pixel_format;
 747         cache->fb.stride = fb->pitches[0];
 748         cache->fb.fence_reg = obj->fence_reg;
 749         cache->fb.tiling_mode = obj->tiling_mode;
 750 }
 751
 752 static bool intel_fbc_can_activate(struct intel_crtc *crtc)
 753 {
 754         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 755         struct intel_fbc *fbc = &dev_priv->fbc;
 756         struct intel_fbc_state_cache *cache = &fbc->state_cache;
 757
 758         if (!cache->plane.visible) {
 759                 fbc->no_fbc_reason = "primary plane not visible";
 760                 return false;
 761         }
 762
 763         if ((cache->crtc.mode_flags & DRM_MODE_FLAG_INTERLACE) ||
 764             (cache->crtc.mode_flags & DRM_MODE_FLAG_DBLSCAN)) {
 765                 fbc->no_fbc_reason = "incompatible mode";
 766                 return false;
 767         }
 768
 769         if (!intel_fbc_hw_tracking_covers_screen(crtc)) {
 770                 fbc->no_fbc_reason = "mode too large for compression";
 771                 return false;
 772         }
 773
 774         /* The use of a CPU fence is mandatory in order to detect writes
 775          * by the CPU to the scanout and trigger updates to the FBC.
 776          */
 777         if (cache->fb.tiling_mode != I915_TILING_X ||
 778             cache->fb.fence_reg == I915_FENCE_REG_NONE) {
 779                 fbc->no_fbc_reason = "framebuffer not tiled or fenced";
 780                 return false;
 781         }
 782         if (INTEL_INFO(dev_priv)->gen <= 4 && !IS_G4X(dev_priv) &&
 783             cache->plane.rotation != BIT(DRM_ROTATE_0)) {
 784                 fbc->no_fbc_reason = "rotation unsupported";
 785                 return false;
 786         }
 787
 788         if (!stride_is_valid(dev_priv, cache->fb.stride)) {
 789                 fbc->no_fbc_reason = "framebuffer stride not supported";
 790                 return false;
 791         }
 792
 793         if (!pixel_format_is_valid(dev_priv, cache->fb.pixel_format)) {
 794                 fbc->no_fbc_reason = "pixel format is invalid";
 795                 return false;
 796         }
 797
 798         /* WaFbcExceedCdClockThreshold:hsw,bdw */
 799         if ((IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) &&
 800             cache->crtc.hsw_bdw_pixel_rate >= dev_priv->cdclk_freq * 95 / 100) {
 801                 fbc->no_fbc_reason = "pixel rate is too big";
 802                 return false;
 803         }
 804
 805         /* It is possible for the required CFB size change without a
 806          * crtc->disable + crtc->enable since it is possible to change the
 807          * stride without triggering a full modeset. Since we try to
 808          * over-allocate the CFB, there's a chance we may keep FBC enabled even
 809          * if this happens, but if we exceed the current CFB size we'll have to
 810          * disable FBC. Notice that it would be possible to disable FBC, wait
 811          * for a frame, free the stolen node, then try to reenable FBC in case
 812          * we didn't get any invalidate/deactivate calls, but this would require
 813          * a lot of tracking just for a specific case. If we conclude it's an
 814          * important case, we can implement it later. */
 815         if (intel_fbc_calculate_cfb_size(dev_priv, &fbc->state_cache) >
 816             fbc->compressed_fb.size * fbc->threshold) {
 817                 fbc->no_fbc_reason = "CFB requirements changed";
 818                 return false;
 819         }
 820
 821         return true;
 822 }
 823
 824 static bool intel_fbc_can_choose(struct intel_crtc *crtc)
 825 {
 826         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 827         struct intel_fbc *fbc = &dev_priv->fbc;
 828         bool enable_by_default = IS_HASWELL(dev_priv) ||
 829                                  IS_BROADWELL(dev_priv);
 830
 831         if (intel_vgpu_active(dev_priv)) {
 832                 fbc->no_fbc_reason = "VGPU is active";
 833                 return false;
 834         }
 835
 836         if (i915.enable_fbc < 0 && !enable_by_default) {
 837                 fbc->no_fbc_reason = "disabled per chip default";
 838                 return false;
 839         }
 840
 841         if (!i915.enable_fbc) {
 842                 fbc->no_fbc_reason = "disabled per module param";
 843                 return false;
 844         }
 845
 846         if (fbc_on_pipe_a_only(dev_priv) && crtc->pipe != PIPE_A) {
 847                 fbc->no_fbc_reason = "no enabled pipes can have FBC";
 848                 return false;
 849         }
 850
 851         if (fbc_on_plane_a_only(dev_priv) && crtc->plane != PLANE_A) {
 852                 fbc->no_fbc_reason = "no enabled planes can have FBC";
 853                 return false;
 854         }
 855
 856         return true;
 857 }
 858
 859 static void intel_fbc_get_reg_params(struct intel_crtc *crtc,
 860                                      struct intel_fbc_reg_params *params)
 861 {
 862         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 863         struct intel_fbc *fbc = &dev_priv->fbc;
 864         struct intel_fbc_state_cache *cache = &fbc->state_cache;
 865
 866         /* Since all our fields are integer types, use memset here so the
 867          * comparison function can rely on memcmp because the padding will be
 868          * zero. */
 869         memset(params, 0, sizeof(*params));
 870
 871         params->crtc.pipe = crtc->pipe;
 872         params->crtc.plane = crtc->plane;
 873         params->crtc.fence_y_offset = get_crtc_fence_y_offset(crtc);
 874
 875         params->fb.pixel_format = cache->fb.pixel_format;
 876         params->fb.stride = cache->fb.stride;
 877         params->fb.fence_reg = cache->fb.fence_reg;
 878
 879         params->cfb_size = intel_fbc_calculate_cfb_size(dev_priv, cache);
 880
 881         params->fb.ggtt_offset = cache->fb.ilk_ggtt_offset;
 882 }
 883
 884 static bool intel_fbc_reg_params_equal(struct intel_fbc_reg_params *params1,
 885                                        struct intel_fbc_reg_params *params2)
 886 {
 887         /* We can use this since intel_fbc_get_reg_params() does a memset. */
 888         return memcmp(params1, params2, sizeof(*params1)) == 0;
 889 }
 890
 891 void intel_fbc_pre_update(struct intel_crtc *crtc)
 892 {
 893         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 894         struct intel_fbc *fbc = &dev_priv->fbc;
 895
 896         if (!fbc_supported(dev_priv))
 897                 return;
 898
 899         mutex_lock(&fbc->lock);
 900
 901         if (!multiple_pipes_ok(crtc)) {
 902                 fbc->no_fbc_reason = "more than one pipe active";
 903                 goto deactivate;
 904         }
 905
 906         if (!fbc->enabled || fbc->crtc != crtc)
 907                 goto unlock;
 908
 909         intel_fbc_update_state_cache(crtc);
 910
 911 deactivate:
 912         intel_fbc_deactivate(dev_priv);
 913 unlock:
 914         mutex_unlock(&fbc->lock);
 915 }
 916
 917 static void __intel_fbc_post_update(struct intel_crtc *crtc)
 918 {
 919         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 920         struct intel_fbc *fbc = &dev_priv->fbc;
 921         struct intel_fbc_reg_params old_params;
 922
 923         WARN_ON(!mutex_is_locked(&fbc->lock));
 924
 925         if (!fbc->enabled || fbc->crtc != crtc)
 926                 return;
 927
 928         if (!intel_fbc_can_activate(crtc)) {
 929                 WARN_ON(fbc->active);
 930                 return;
 931         }
 932
 933         old_params = fbc->params;
 934         intel_fbc_get_reg_params(crtc, &fbc->params);
 935
 936         /* If the scanout has not changed, don't modify the FBC settings.
 937          * Note that we make the fundamental assumption that the fb->obj
 938          * cannot be unpinned (and have its GTT offset and fence revoked)
 939          * without first being decoupled from the scanout and FBC disabled.
 940          */
 941         if (fbc->active &&
 942             intel_fbc_reg_params_equal(&old_params, &fbc->params))
 943                 return;
 944
 945         intel_fbc_deactivate(dev_priv);
 946         intel_fbc_schedule_activation(crtc);
 947         fbc->no_fbc_reason = "FBC enabled (active or scheduled)";
 948 }
 949
 950 void intel_fbc_post_update(struct intel_crtc *crtc)
 951 {
 952         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 953         struct intel_fbc *fbc = &dev_priv->fbc;
 954
 955         if (!fbc_supported(dev_priv))
 956                 return;
 957
 958         mutex_lock(&fbc->lock);
 959         __intel_fbc_post_update(crtc);
 960         mutex_unlock(&fbc->lock);
 961 }
 962
 963 static unsigned int intel_fbc_get_frontbuffer_bit(struct intel_fbc *fbc)
 964 {
 965         if (fbc->enabled)
 966                 return to_intel_plane(fbc->crtc->base.primary)->frontbuffer_bit;
 967         else
 968                 return fbc->possible_framebuffer_bits;
 969 }
 970
 971 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
 972                           unsigned int frontbuffer_bits,
 973                           enum fb_op_origin origin)
 974 {
 975         struct intel_fbc *fbc = &dev_priv->fbc;
 976
 977         if (!fbc_supported(dev_priv))
 978                 return;
 979
 980         if (origin == ORIGIN_GTT || origin == ORIGIN_FLIP)
 981                 return;
 982
 983         mutex_lock(&fbc->lock);
 984
 985         fbc->busy_bits |= intel_fbc_get_frontbuffer_bit(fbc) & frontbuffer_bits;
 986
 987         if (fbc->enabled && fbc->busy_bits)
 988                 intel_fbc_deactivate(dev_priv);
 989
 990         mutex_unlock(&fbc->lock);
 991 }
 992
 993 void intel_fbc_flush(struct drm_i915_private *dev_priv,
 994                      unsigned int frontbuffer_bits, enum fb_op_origin origin)
 995 {
 996         struct intel_fbc *fbc = &dev_priv->fbc;
 997
 998         if (!fbc_supported(dev_priv))
 999                 return;
1000
1001         if (origin == ORIGIN_GTT || origin == ORIGIN_FLIP)
1002                 return;
1003
1004         mutex_lock(&fbc->lock);
1005
1006         fbc->busy_bits &= ~frontbuffer_bits;
1007
1008         if (!fbc->busy_bits && fbc->enabled &&
1009             (frontbuffer_bits & intel_fbc_get_frontbuffer_bit(fbc))) {
1010                 if (fbc->active)
1011                         intel_fbc_recompress(dev_priv);
1012                 else
1013                         __intel_fbc_post_update(fbc->crtc);
1014         }
1015
1016         mutex_unlock(&fbc->lock);
1017 }
1018
1019 /**
1020  * intel_fbc_choose_crtc - select a CRTC to enable FBC on
1021  * @dev_priv: i915 device instance
1022  * @state: the atomic state structure
1023  *
1024  * This function looks at the proposed state for CRTCs and planes, then chooses
1025  * which pipe is going to have FBC by setting intel_crtc_state->enable_fbc to
1026  * true.
1027  *
1028  * Later, intel_fbc_enable is going to look for state->enable_fbc and then maybe
1029  * enable FBC for the chosen CRTC. If it does, it will set dev_priv->fbc.crtc.
1030  */
1031 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1032                            struct drm_atomic_state *state)
1033 {
1034         struct intel_fbc *fbc = &dev_priv->fbc;
1035         struct drm_crtc *crtc;
1036         struct drm_crtc_state *crtc_state;
1037         struct drm_plane *plane;
1038         struct drm_plane_state *plane_state;
1039         bool fbc_crtc_present = false;
1040         int i, j;
1041
1042         mutex_lock(&fbc->lock);
1043
1044         for_each_crtc_in_state(state, crtc, crtc_state, i) {
1045                 if (fbc->crtc == to_intel_crtc(crtc)) {
1046                         fbc_crtc_present = true;
1047                         break;
1048                 }
1049         }
1050         /* This atomic commit doesn't involve the CRTC currently tied to FBC. */
1051         if (!fbc_crtc_present && fbc->crtc != NULL)
1052                 goto out;
1053
1054         /* Simply choose the first CRTC that is compatible and has a visible
1055          * plane. We could go for fancier schemes such as checking the plane
1056          * size, but this would just affect the few platforms that don't tie FBC
1057          * to pipe or plane A. */
1058         for_each_plane_in_state(state, plane, plane_state, i) {
1059                 struct intel_plane_state *intel_plane_state =
1060                         to_intel_plane_state(plane_state);
1061
1062                 if (!intel_plane_state->visible)
1063                         continue;
1064
1065                 for_each_crtc_in_state(state, crtc, crtc_state, j) {
1066                         struct intel_crtc_state *intel_crtc_state =
1067                                 to_intel_crtc_state(crtc_state);
1068
1069                         if (plane_state->crtc != crtc)
1070                                 continue;
1071
1072                         if (!intel_fbc_can_choose(to_intel_crtc(crtc)))
1073                                 break;
1074
1075                         intel_crtc_state->enable_fbc = true;
1076                         goto out;
1077                 }
1078         }
1079
1080 out:
1081         mutex_unlock(&fbc->lock);
1082 }
1083
1084 /**
1085  * intel_fbc_enable: tries to enable FBC on the CRTC
1086  * @crtc: the CRTC
1087  *
1088  * This function checks if the given CRTC was chosen for FBC, then enables it if
1089  * possible. Notice that it doesn't activate FBC. It is valid to call
1090  * intel_fbc_enable multiple times for the same pipe without an
1091  * intel_fbc_disable in the middle, as long as it is deactivated.
1092  */
1093 void intel_fbc_enable(struct intel_crtc *crtc)
1094 {
1095         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1096         struct intel_fbc *fbc = &dev_priv->fbc;
1097
1098         if (!fbc_supported(dev_priv))
1099                 return;
1100
1101         mutex_lock(&fbc->lock);
1102
1103         if (fbc->enabled) {
1104                 WARN_ON(fbc->crtc == NULL);
1105                 if (fbc->crtc == crtc) {
1106                         WARN_ON(!crtc->config->enable_fbc);
1107                         WARN_ON(fbc->active);
1108                 }
1109                 goto out;
1110         }
1111
1112         if (!crtc->config->enable_fbc)
1113                 goto out;
1114
1115         WARN_ON(fbc->active);
1116         WARN_ON(fbc->crtc != NULL);
1117
1118         intel_fbc_update_state_cache(crtc);
1119         if (intel_fbc_alloc_cfb(crtc)) {
1120                 fbc->no_fbc_reason = "not enough stolen memory";
1121                 goto out;
1122         }
1123
1124         DRM_DEBUG_KMS("Enabling FBC on pipe %c\n", pipe_name(crtc->pipe));
1125         fbc->no_fbc_reason = "FBC enabled but not active yet\n";
1126
1127         fbc->enabled = true;
1128         fbc->crtc = crtc;
1129 out:
1130         mutex_unlock(&fbc->lock);
1131 }
1132
1133 /**
1134  * __intel_fbc_disable - disable FBC
1135  * @dev_priv: i915 device instance
1136  *
1137  * This is the low level function that actually disables FBC. Callers should
1138  * grab the FBC lock.
1139  */
1140 static void __intel_fbc_disable(struct drm_i915_private *dev_priv)
1141 {
1142         struct intel_fbc *fbc = &dev_priv->fbc;
1143         struct intel_crtc *crtc = fbc->crtc;
1144
1145         WARN_ON(!mutex_is_locked(&fbc->lock));
1146         WARN_ON(!fbc->enabled);
1147         WARN_ON(fbc->active);
1148         WARN_ON(crtc->active);
1149
1150         DRM_DEBUG_KMS("Disabling FBC on pipe %c\n", pipe_name(crtc->pipe));
1151
1152         __intel_fbc_cleanup_cfb(dev_priv);
1153
1154         fbc->enabled = false;
1155         fbc->crtc = NULL;
1156 }
1157
1158 /**
1159  * intel_fbc_disable - disable FBC if it's associated with crtc
1160  * @crtc: the CRTC
1161  *
1162  * This function disables FBC if it's associated with the provided CRTC.
1163  */
1164 void intel_fbc_disable(struct intel_crtc *crtc)
1165 {
1166         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1167         struct intel_fbc *fbc = &dev_priv->fbc;
1168
1169         if (!fbc_supported(dev_priv))
1170                 return;
1171
1172         mutex_lock(&fbc->lock);
1173         if (fbc->crtc == crtc) {
1174                 WARN_ON(!fbc->enabled);
1175                 WARN_ON(fbc->active);
1176                 __intel_fbc_disable(dev_priv);
1177         }
1178         mutex_unlock(&fbc->lock);
1179
1180         cancel_work_sync(&fbc->work.work);
1181 }
1182
1183 /**
1184  * intel_fbc_global_disable - globally disable FBC
1185  * @dev_priv: i915 device instance
1186  *
1187  * This function disables FBC regardless of which CRTC is associated with it.
1188  */
1189 void intel_fbc_global_disable(struct drm_i915_private *dev_priv)
1190 {
1191         struct intel_fbc *fbc = &dev_priv->fbc;
1192
1193         if (!fbc_supported(dev_priv))
1194                 return;
1195
1196         mutex_lock(&fbc->lock);
1197         if (fbc->enabled)
1198                 __intel_fbc_disable(dev_priv);
1199         mutex_unlock(&fbc->lock);
1200
1201         cancel_work_sync(&fbc->work.work);
1202 }
1203
1204 /**
1205  * intel_fbc_init_pipe_state - initialize FBC's CRTC visibility tracking
1206  * @dev_priv: i915 device instance
1207  *
1208  * The FBC code needs to track CRTC visibility since the older platforms can't
1209  * have FBC enabled while multiple pipes are used. This function does the
1210  * initial setup at driver load to make sure FBC is matching the real hardware.
1211  */
1212 void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv)
1213 {
1214         struct intel_crtc *crtc;
1215
1216         /* Don't even bother tracking anything if we don't need. */
1217         if (!no_fbc_on_multiple_pipes(dev_priv))
1218                 return;
1219
1220         for_each_intel_crtc(dev_priv->dev, crtc)
1221                 if (intel_crtc_active(&crtc->base) &&
1222                     to_intel_plane_state(crtc->base.primary->state)->visible)
1223                         dev_priv->fbc.visible_pipes_mask |= (1 << crtc->pipe);
1224 }
1225
1226 /**
1227  * intel_fbc_init - Initialize FBC
1228  * @dev_priv: the i915 device
1229  *
1230  * This function might be called during PM init process.
1231  */
1232 void intel_fbc_init(struct drm_i915_private *dev_priv)
1233 {
1234         struct intel_fbc *fbc = &dev_priv->fbc;
1235         enum pipe pipe;
1236
1237         INIT_WORK(&fbc->work.work, intel_fbc_work_fn);
1238         mutex_init(&fbc->lock);
1239         fbc->enabled = false;
1240         fbc->active = false;
1241         fbc->work.scheduled = false;
1242
1243         if (!HAS_FBC(dev_priv)) {
1244                 fbc->no_fbc_reason = "unsupported by this chipset";
1245                 return;
1246         }
1247
1248         for_each_pipe(dev_priv, pipe) {
1249                 fbc->possible_framebuffer_bits |=
1250                                 INTEL_FRONTBUFFER_PRIMARY(pipe);
1251
1252                 if (fbc_on_pipe_a_only(dev_priv))
1253                         break;
1254         }
1255
1256         /* This value was pulled out of someone's hat */
1257         if (INTEL_INFO(dev_priv)->gen <= 4 && !IS_GM45(dev_priv))
1258                 I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT);
1259
1260         /* We still don't have any sort of hardware state readout for FBC, so
1261          * deactivate it in case the BIOS activated it to make sure software
1262          * matches the hardware state. */
1263         if (intel_fbc_hw_is_active(dev_priv))
1264                 intel_fbc_hw_deactivate(dev_priv);
1265 }