drivers/gpu/drm/i915/intel_fbc.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 /**
  25  * DOC: Frame Buffer Compression (FBC)
  26  *
  27  * FBC tries to save memory bandwidth (and so power consumption) by
  28  * compressing the amount of memory used by the display. It is total
  29  * transparent to user space and completely handled in the kernel.
  30  *
  31  * The benefits of FBC are mostly visible with solid backgrounds and
  32  * variation-less patterns. It comes from keeping the memory footprint small
  33  * and having fewer memory pages opened and accessed for refreshing the display.
  34  *
  35  * i915 is responsible to reserve stolen memory for FBC and configure its
  36  * offset on proper registers. The hardware takes care of all
  37  * compress/decompress. However there are many known cases where we have to
  38  * forcibly disable it to allow proper screen updates.
  39  */
  40
  41 #include "intel_drv.h"
  42 #include "i915_drv.h"
  43
  44 static inline bool fbc_supported(struct drm_i915_private *dev_priv)
  45 {
  46         return HAS_FBC(dev_priv);
  47 }
  48
  49 static inline bool fbc_on_pipe_a_only(struct drm_i915_private *dev_priv)
  50 {
  51         return IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8;
  52 }
  53
  54 static inline bool fbc_on_plane_a_only(struct drm_i915_private *dev_priv)
  55 {
  56         return INTEL_INFO(dev_priv)->gen < 4;
  57 }
  58
  59 static inline bool no_fbc_on_multiple_pipes(struct drm_i915_private *dev_priv)
  60 {
  61         return INTEL_INFO(dev_priv)->gen <= 3;
  62 }
  63
  64 /*
  65  * In some platforms where the CRTC's x:0/y:0 coordinates doesn't match the
  66  * frontbuffer's x:0/y:0 coordinates we lie to the hardware about the plane's
  67  * origin so the x and y offsets can actually fit the registers. As a
  68  * consequence, the fence doesn't really start exactly at the display plane
  69  * address we program because it starts at the real start of the buffer, so we
  70  * have to take this into consideration here.
  71  */
  72 static unsigned int get_crtc_fence_y_offset(struct intel_crtc *crtc)
  73 {
  74         return crtc->base.y - crtc->adjusted_y;
  75 }
  76
  77 /*
  78  * For SKL+, the plane source size used by the hardware is based on the value we
  79  * write to the PLANE_SIZE register. For BDW-, the hardware looks at the value
  80  * we wrote to PIPESRC.
  81  */
  82 static void intel_fbc_get_plane_source_size(struct intel_fbc_state_cache *cache,
  83                                             int *width, int *height)
  84 {
  85         int w, h;
  86
  87         if (intel_rotation_90_or_270(cache->plane.rotation)) {
  88                 w = cache->plane.src_h;
  89                 h = cache->plane.src_w;
  90         } else {
  91                 w = cache->plane.src_w;
  92                 h = cache->plane.src_h;
  93         }
  94
  95         if (width)
  96                 *width = w;
  97         if (height)
  98                 *height = h;
  99 }
 100
 101 static int intel_fbc_calculate_cfb_size(struct drm_i915_private *dev_priv,
 102                                         struct intel_fbc_state_cache *cache)
 103 {
 104         int lines;
 105
 106         intel_fbc_get_plane_source_size(cache, NULL, &lines);
 107         if (INTEL_INFO(dev_priv)->gen >= 7)
 108                 lines = min(lines, 2048);
 109
 110         /* Hardware needs the full buffer stride, not just the active area. */
 111         return lines * cache->fb.stride;
 112 }
 113
 114 static void i8xx_fbc_deactivate(struct drm_i915_private *dev_priv)
 115 {
 116         u32 fbc_ctl;
 117
 118         /* Disable compression */
 119         fbc_ctl = I915_READ(FBC_CONTROL);
 120         if ((fbc_ctl & FBC_CTL_EN) == 0)
 121                 return;
 122
 123         fbc_ctl &= ~FBC_CTL_EN;
 124         I915_WRITE(FBC_CONTROL, fbc_ctl);
 125
 126         /* Wait for compressing bit to clear */
 127         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
 128                 DRM_DEBUG_KMS("FBC idle timed out\n");
 129                 return;
 130         }
 131 }
 132
 133 static void i8xx_fbc_activate(struct drm_i915_private *dev_priv)
 134 {
 135         struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
 136         int cfb_pitch;
 137         int i;
 138         u32 fbc_ctl;
 139
 140         /* Note: fbc.threshold == 1 for i8xx */
 141         cfb_pitch = params->cfb_size / FBC_LL_SIZE;
 142         if (params->fb.stride < cfb_pitch)
 143                 cfb_pitch = params->fb.stride;
 144
 145         /* FBC_CTL wants 32B or 64B units */
 146         if (IS_GEN2(dev_priv))
 147                 cfb_pitch = (cfb_pitch / 32) - 1;
 148         else
 149                 cfb_pitch = (cfb_pitch / 64) - 1;
 150
 151         /* Clear old tags */
 152         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
 153                 I915_WRITE(FBC_TAG(i), 0);
 154
 155         if (IS_GEN4(dev_priv)) {
 156                 u32 fbc_ctl2;
 157
 158                 /* Set it up... */
 159                 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
 160                 fbc_ctl2 |= FBC_CTL_PLANE(params->crtc.plane);
 161                 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
 162                 I915_WRITE(FBC_FENCE_OFF, params->crtc.fence_y_offset);
 163         }
 164
 165         /* enable it... */
 166         fbc_ctl = I915_READ(FBC_CONTROL);
 167         fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT;
 168         fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC;
 169         if (IS_I945GM(dev_priv))
 170                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
 171         fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
 172         fbc_ctl |= params->fb.fence_reg;
 173         I915_WRITE(FBC_CONTROL, fbc_ctl);
 174 }
 175
 176 static bool i8xx_fbc_is_active(struct drm_i915_private *dev_priv)
 177 {
 178         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
 179 }
 180
 181 static void g4x_fbc_activate(struct drm_i915_private *dev_priv)
 182 {
 183         struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
 184         u32 dpfc_ctl;
 185
 186         dpfc_ctl = DPFC_CTL_PLANE(params->crtc.plane) | DPFC_SR_EN;
 187         if (drm_format_plane_cpp(params->fb.pixel_format, 0) == 2)
 188                 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 189         else
 190                 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 191         dpfc_ctl |= DPFC_CTL_FENCE_EN | params->fb.fence_reg;
 192
 193         I915_WRITE(DPFC_FENCE_YOFF, params->crtc.fence_y_offset);
 194
 195         /* enable it... */
 196         I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 197 }
 198
 199 static void g4x_fbc_deactivate(struct drm_i915_private *dev_priv)
 200 {
 201         u32 dpfc_ctl;
 202
 203         /* Disable compression */
 204         dpfc_ctl = I915_READ(DPFC_CONTROL);
 205         if (dpfc_ctl & DPFC_CTL_EN) {
 206                 dpfc_ctl &= ~DPFC_CTL_EN;
 207                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
 208         }
 209 }
 210
 211 static bool g4x_fbc_is_active(struct drm_i915_private *dev_priv)
 212 {
 213         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
 214 }
 215
 216 /* This function forces a CFB recompression through the nuke operation. */
 217 static void intel_fbc_recompress(struct drm_i915_private *dev_priv)
 218 {
 219         I915_WRITE(MSG_FBC_REND_STATE, FBC_REND_NUKE);
 220         POSTING_READ(MSG_FBC_REND_STATE);
 221 }
 222
 223 static void ilk_fbc_activate(struct drm_i915_private *dev_priv)
 224 {
 225         struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
 226         u32 dpfc_ctl;
 227         int threshold = dev_priv->fbc.threshold;
 228
 229         dpfc_ctl = DPFC_CTL_PLANE(params->crtc.plane);
 230         if (drm_format_plane_cpp(params->fb.pixel_format, 0) == 2)
 231                 threshold++;
 232
 233         switch (threshold) {
 234         case 4:
 235         case 3:
 236                 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
 237                 break;
 238         case 2:
 239                 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 240                 break;
 241         case 1:
 242                 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 243                 break;
 244         }
 245         dpfc_ctl |= DPFC_CTL_FENCE_EN;
 246         if (IS_GEN5(dev_priv))
 247                 dpfc_ctl |= params->fb.fence_reg;
 248
 249         I915_WRITE(ILK_DPFC_FENCE_YOFF, params->crtc.fence_y_offset);
 250         I915_WRITE(ILK_FBC_RT_BASE, params->fb.ggtt_offset | ILK_FBC_RT_VALID);
 251         /* enable it... */
 252         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 253
 254         if (IS_GEN6(dev_priv)) {
 255                 I915_WRITE(SNB_DPFC_CTL_SA,
 256                            SNB_CPU_FENCE_ENABLE | params->fb.fence_reg);
 257                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, params->crtc.fence_y_offset);
 258         }
 259
 260         intel_fbc_recompress(dev_priv);
 261 }
 262
 263 static void ilk_fbc_deactivate(struct drm_i915_private *dev_priv)
 264 {
 265         u32 dpfc_ctl;
 266
 267         /* Disable compression */
 268         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
 269         if (dpfc_ctl & DPFC_CTL_EN) {
 270                 dpfc_ctl &= ~DPFC_CTL_EN;
 271                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
 272         }
 273 }
 274
 275 static bool ilk_fbc_is_active(struct drm_i915_private *dev_priv)
 276 {
 277         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
 278 }
 279
 280 static void gen7_fbc_activate(struct drm_i915_private *dev_priv)
 281 {
 282         struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
 283         u32 dpfc_ctl;
 284         int threshold = dev_priv->fbc.threshold;
 285
 286         dpfc_ctl = 0;
 287         if (IS_IVYBRIDGE(dev_priv))
 288                 dpfc_ctl |= IVB_DPFC_CTL_PLANE(params->crtc.plane);
 289
 290         if (drm_format_plane_cpp(params->fb.pixel_format, 0) == 2)
 291                 threshold++;
 292
 293         switch (threshold) {
 294         case 4:
 295         case 3:
 296                 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
 297                 break;
 298         case 2:
 299                 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 300                 break;
 301         case 1:
 302                 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 303                 break;
 304         }
 305
 306         dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
 307
 308         if (dev_priv->fbc.false_color)
 309                 dpfc_ctl |= FBC_CTL_FALSE_COLOR;
 310
 311         if (IS_IVYBRIDGE(dev_priv)) {
 312                 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
 313                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
 314                            I915_READ(ILK_DISPLAY_CHICKEN1) |
 315                            ILK_FBCQ_DIS);
 316         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
 317                 /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
 318                 I915_WRITE(CHICKEN_PIPESL_1(params->crtc.pipe),
 319                            I915_READ(CHICKEN_PIPESL_1(params->crtc.pipe)) |
 320                            HSW_FBCQ_DIS);
 321         }
 322
 323         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 324
 325         I915_WRITE(SNB_DPFC_CTL_SA,
 326                    SNB_CPU_FENCE_ENABLE | params->fb.fence_reg);
 327         I915_WRITE(DPFC_CPU_FENCE_OFFSET, params->crtc.fence_y_offset);
 328
 329         intel_fbc_recompress(dev_priv);
 330 }
 331
 332 static bool intel_fbc_hw_is_active(struct drm_i915_private *dev_priv)
 333 {
 334         if (INTEL_INFO(dev_priv)->gen >= 5)
 335                 return ilk_fbc_is_active(dev_priv);
 336         else if (IS_GM45(dev_priv))
 337                 return g4x_fbc_is_active(dev_priv);
 338         else
 339                 return i8xx_fbc_is_active(dev_priv);
 340 }
 341
 342 static void intel_fbc_hw_activate(struct drm_i915_private *dev_priv)
 343 {
 344         struct intel_fbc *fbc = &dev_priv->fbc;
 345
 346         fbc->active = true;
 347
 348         if (INTEL_INFO(dev_priv)->gen >= 7)
 349                 gen7_fbc_activate(dev_priv);
 350         else if (INTEL_INFO(dev_priv)->gen >= 5)
 351                 ilk_fbc_activate(dev_priv);
 352         else if (IS_GM45(dev_priv))
 353                 g4x_fbc_activate(dev_priv);
 354         else
 355                 i8xx_fbc_activate(dev_priv);
 356 }
 357
 358 static void intel_fbc_hw_deactivate(struct drm_i915_private *dev_priv)
 359 {
 360         struct intel_fbc *fbc = &dev_priv->fbc;
 361
 362         fbc->active = false;
 363
 364         if (INTEL_INFO(dev_priv)->gen >= 5)
 365                 ilk_fbc_deactivate(dev_priv);
 366         else if (IS_GM45(dev_priv))
 367                 g4x_fbc_deactivate(dev_priv);
 368         else
 369                 i8xx_fbc_deactivate(dev_priv);
 370 }
 371
 372 /**
 373  * intel_fbc_is_active - Is FBC active?
 374  * @dev_priv: i915 device instance
 375  *
 376  * This function is used to verify the current state of FBC.
 377  *
 378  * FIXME: This should be tracked in the plane config eventually
 379  * instead of queried at runtime for most callers.
 380  */
 381 bool intel_fbc_is_active(struct drm_i915_private *dev_priv)
 382 {
 383         return dev_priv->fbc.active;
 384 }
 385
 386 static void intel_fbc_work_fn(struct work_struct *__work)
 387 {
 388         struct drm_i915_private *dev_priv =
 389                 container_of(__work, struct drm_i915_private, fbc.work.work);
 390         struct intel_fbc *fbc = &dev_priv->fbc;
 391         struct intel_fbc_work *work = &fbc->work;
 392         struct intel_crtc *crtc = fbc->crtc;
 393         struct drm_vblank_crtc *vblank = &dev_priv->dev->vblank[crtc->pipe];
 394
 395         if (drm_crtc_vblank_get(&crtc->base)) {
 396                 DRM_ERROR("vblank not available for FBC on pipe %c\n",
 397                           pipe_name(crtc->pipe));
 398
 399                 mutex_lock(&fbc->lock);
 400                 work->scheduled = false;
 401                 mutex_unlock(&fbc->lock);
 402                 return;
 403         }
 404
 405 retry:
 406         /* Delay the actual enabling to let pageflipping cease and the
 407          * display to settle before starting the compression. Note that
 408          * this delay also serves a second purpose: it allows for a
 409          * vblank to pass after disabling the FBC before we attempt
 410          * to modify the control registers.
 411          *
 412          * WaFbcWaitForVBlankBeforeEnable:ilk,snb
 413          *
 414          * It is also worth mentioning that since work->scheduled_vblank can be
 415          * updated multiple times by the other threads, hitting the timeout is
 416          * not an error condition. We'll just end up hitting the "goto retry"
 417          * case below.
 418          */
 419         wait_event_timeout(vblank->queue,
 420                 drm_crtc_vblank_count(&crtc->base) != work->scheduled_vblank,
 421                 msecs_to_jiffies(50));
 422
 423         mutex_lock(&fbc->lock);
 424
 425         /* Were we cancelled? */
 426         if (!work->scheduled)
 427                 goto out;
 428
 429         /* Were we delayed again while this function was sleeping? */
 430         if (drm_crtc_vblank_count(&crtc->base) == work->scheduled_vblank) {
 431                 mutex_unlock(&fbc->lock);
 432                 goto retry;
 433         }
 434
 435         intel_fbc_hw_activate(dev_priv);
 436
 437         work->scheduled = false;
 438
 439 out:
 440         mutex_unlock(&fbc->lock);
 441         drm_crtc_vblank_put(&crtc->base);
 442 }
 443
 444 static void intel_fbc_schedule_activation(struct intel_crtc *crtc)
 445 {
 446         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 447         struct intel_fbc *fbc = &dev_priv->fbc;
 448         struct intel_fbc_work *work = &fbc->work;
 449
 450         WARN_ON(!mutex_is_locked(&fbc->lock));
 451
 452         if (drm_crtc_vblank_get(&crtc->base)) {
 453                 DRM_ERROR("vblank not available for FBC on pipe %c\n",
 454                           pipe_name(crtc->pipe));
 455                 return;
 456         }
 457
 458         /* It is useless to call intel_fbc_cancel_work() or cancel_work() in
 459          * this function since we're not releasing fbc.lock, so it won't have an
 460          * opportunity to grab it to discover that it was cancelled. So we just
 461          * update the expected jiffy count. */
 462         work->scheduled = true;
 463         work->scheduled_vblank = drm_crtc_vblank_count(&crtc->base);
 464         drm_crtc_vblank_put(&crtc->base);
 465
 466         schedule_work(&work->work);
 467 }
 468
 469 static void intel_fbc_deactivate(struct drm_i915_private *dev_priv)
 470 {
 471         struct intel_fbc *fbc = &dev_priv->fbc;
 472
 473         WARN_ON(!mutex_is_locked(&fbc->lock));
 474
 475         /* Calling cancel_work() here won't help due to the fact that the work
 476          * function grabs fbc->lock. Just set scheduled to false so the work
 477          * function can know it was cancelled. */
 478         fbc->work.scheduled = false;
 479
 480         if (fbc->active)
 481                 intel_fbc_hw_deactivate(dev_priv);
 482 }
 483
 484 static bool multiple_pipes_ok(struct intel_crtc *crtc,
 485                               struct intel_plane_state *plane_state)
 486 {
 487         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 488         struct intel_fbc *fbc = &dev_priv->fbc;
 489         enum pipe pipe = crtc->pipe;
 490
 491         /* Don't even bother tracking anything we don't need. */
 492         if (!no_fbc_on_multiple_pipes(dev_priv))
 493                 return true;
 494
 495         if (plane_state->visible)
 496                 fbc->visible_pipes_mask |= (1 << pipe);
 497         else
 498                 fbc->visible_pipes_mask &= ~(1 << pipe);
 499
 500         return (fbc->visible_pipes_mask & ~(1 << pipe)) != 0;
 501 }
 502
 503 static int find_compression_threshold(struct drm_i915_private *dev_priv,
 504                                       struct drm_mm_node *node,
 505                                       int size,
 506                                       int fb_cpp)
 507 {
 508         struct i915_ggtt *ggtt = &dev_priv->ggtt;
 509         int compression_threshold = 1;
 510         int ret;
 511         u64 end;
 512
 513         /* The FBC hardware for BDW/SKL doesn't have access to the stolen
 514          * reserved range size, so it always assumes the maximum (8mb) is used.
 515          * If we enable FBC using a CFB on that memory range we'll get FIFO
 516          * underruns, even if that range is not reserved by the BIOS. */
 517         if (IS_BROADWELL(dev_priv) ||
 518             IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
 519                 end = ggtt->stolen_size - 8 * 1024 * 1024;
 520         else
 521                 end = ggtt->stolen_usable_size;
 522
 523         /* HACK: This code depends on what we will do in *_enable_fbc. If that
 524          * code changes, this code needs to change as well.
 525          *
 526          * The enable_fbc code will attempt to use one of our 2 compression
 527          * thresholds, therefore, in that case, we only have 1 resort.
 528          */
 529
 530         /* Try to over-allocate to reduce reallocations and fragmentation. */
 531         ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size <<= 1,
 532                                                    4096, 0, end);
 533         if (ret == 0)
 534                 return compression_threshold;
 535
 536 again:
 537         /* HW's ability to limit the CFB is 1:4 */
 538         if (compression_threshold > 4 ||
 539             (fb_cpp == 2 && compression_threshold == 2))
 540                 return 0;
 541
 542         ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size >>= 1,
 543                                                    4096, 0, end);
 544         if (ret && INTEL_INFO(dev_priv)->gen <= 4) {
 545                 return 0;
 546         } else if (ret) {
 547                 compression_threshold <<= 1;
 548                 goto again;
 549         } else {
 550                 return compression_threshold;
 551         }
 552 }
 553
 554 static int intel_fbc_alloc_cfb(struct intel_crtc *crtc)
 555 {
 556         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 557         struct intel_fbc *fbc = &dev_priv->fbc;
 558         struct drm_mm_node *uninitialized_var(compressed_llb);
 559         int size, fb_cpp, ret;
 560
 561         WARN_ON(drm_mm_node_allocated(&fbc->compressed_fb));
 562
 563         size = intel_fbc_calculate_cfb_size(dev_priv, &fbc->state_cache);
 564         fb_cpp = drm_format_plane_cpp(fbc->state_cache.fb.pixel_format, 0);
 565
 566         ret = find_compression_threshold(dev_priv, &fbc->compressed_fb,
 567                                          size, fb_cpp);
 568         if (!ret)
 569                 goto err_llb;
 570         else if (ret > 1) {
 571                 DRM_INFO("Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS.\n");
 572
 573         }
 574
 575         fbc->threshold = ret;
 576
 577         if (INTEL_INFO(dev_priv)->gen >= 5)
 578                 I915_WRITE(ILK_DPFC_CB_BASE, fbc->compressed_fb.start);
 579         else if (IS_GM45(dev_priv)) {
 580                 I915_WRITE(DPFC_CB_BASE, fbc->compressed_fb.start);
 581         } else {
 582                 compressed_llb = kzalloc(sizeof(*compressed_llb), GFP_KERNEL);
 583                 if (!compressed_llb)
 584                         goto err_fb;
 585
 586                 ret = i915_gem_stolen_insert_node(dev_priv, compressed_llb,
 587                                                   4096, 4096);
 588                 if (ret)
 589                         goto err_fb;
 590
 591                 fbc->compressed_llb = compressed_llb;
 592
 593                 I915_WRITE(FBC_CFB_BASE,
 594                            dev_priv->mm.stolen_base + fbc->compressed_fb.start);
 595                 I915_WRITE(FBC_LL_BASE,
 596                            dev_priv->mm.stolen_base + compressed_llb->start);
 597         }
 598
 599         DRM_DEBUG_KMS("reserved %llu bytes of contiguous stolen space for FBC, threshold: %d\n",
 600                       fbc->compressed_fb.size, fbc->threshold);
 601
 602         return 0;
 603
 604 err_fb:
 605         kfree(compressed_llb);
 606         i915_gem_stolen_remove_node(dev_priv, &fbc->compressed_fb);
 607 err_llb:
 608         pr_info_once("drm: not enough stolen space for compressed buffer (need %d more bytes), disabling. Hint: you may be able to increase stolen memory size in the BIOS to avoid this.\n", size);
 609         return -ENOSPC;
 610 }
 611
 612 static void __intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv)
 613 {
 614         struct intel_fbc *fbc = &dev_priv->fbc;
 615
 616         if (drm_mm_node_allocated(&fbc->compressed_fb))
 617                 i915_gem_stolen_remove_node(dev_priv, &fbc->compressed_fb);
 618
 619         if (fbc->compressed_llb) {
 620                 i915_gem_stolen_remove_node(dev_priv, fbc->compressed_llb);
 621                 kfree(fbc->compressed_llb);
 622         }
 623 }
 624
 625 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv)
 626 {
 627         struct intel_fbc *fbc = &dev_priv->fbc;
 628
 629         if (!fbc_supported(dev_priv))
 630                 return;
 631
 632         mutex_lock(&fbc->lock);
 633         __intel_fbc_cleanup_cfb(dev_priv);
 634         mutex_unlock(&fbc->lock);
 635 }
 636
 637 static bool stride_is_valid(struct drm_i915_private *dev_priv,
 638                             unsigned int stride)
 639 {
 640         /* These should have been caught earlier. */
 641         WARN_ON(stride < 512);
 642         WARN_ON((stride & (64 - 1)) != 0);
 643
 644         /* Below are the additional FBC restrictions. */
 645
 646         if (IS_GEN2(dev_priv) || IS_GEN3(dev_priv))
 647                 return stride == 4096 || stride == 8192;
 648
 649         if (IS_GEN4(dev_priv) && !IS_G4X(dev_priv) && stride < 2048)
 650                 return false;
 651
 652         if (stride > 16384)
 653                 return false;
 654
 655         return true;
 656 }
 657
 658 static bool pixel_format_is_valid(struct drm_i915_private *dev_priv,
 659                                   uint32_t pixel_format)
 660 {
 661         switch (pixel_format) {
 662         case DRM_FORMAT_XRGB8888:
 663         case DRM_FORMAT_XBGR8888:
 664                 return true;
 665         case DRM_FORMAT_XRGB1555:
 666         case DRM_FORMAT_RGB565:
 667                 /* 16bpp not supported on gen2 */
 668                 if (IS_GEN2(dev_priv))
 669                         return false;
 670                 /* WaFbcOnly1to1Ratio:ctg */
 671                 if (IS_G4X(dev_priv))
 672                         return false;
 673                 return true;
 674         default:
 675                 return false;
 676         }
 677 }
 678
 679 /*
 680  * For some reason, the hardware tracking starts looking at whatever we
 681  * programmed as the display plane base address register. It does not look at
 682  * the X and Y offset registers. That's why we look at the crtc->adjusted{x,y}
 683  * variables instead of just looking at the pipe/plane size.
 684  */
 685 static bool intel_fbc_hw_tracking_covers_screen(struct intel_crtc *crtc)
 686 {
 687         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 688         struct intel_fbc *fbc = &dev_priv->fbc;
 689         unsigned int effective_w, effective_h, max_w, max_h;
 690
 691         if (INTEL_INFO(dev_priv)->gen >= 8 || IS_HASWELL(dev_priv)) {
 692                 max_w = 4096;
 693                 max_h = 4096;
 694         } else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) {
 695                 max_w = 4096;
 696                 max_h = 2048;
 697         } else {
 698                 max_w = 2048;
 699                 max_h = 1536;
 700         }
 701
 702         intel_fbc_get_plane_source_size(&fbc->state_cache, &effective_w,
 703                                         &effective_h);
 704         effective_w += crtc->adjusted_x;
 705         effective_h += crtc->adjusted_y;
 706
 707         return effective_w <= max_w && effective_h <= max_h;
 708 }
 709
 710 static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
 711                                          struct intel_crtc_state *crtc_state,
 712                                          struct intel_plane_state *plane_state)
 713 {
 714         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 715         struct intel_fbc *fbc = &dev_priv->fbc;
 716         struct intel_fbc_state_cache *cache = &fbc->state_cache;
 717         struct drm_framebuffer *fb = plane_state->base.fb;
 718         struct drm_i915_gem_object *obj;
 719
 720         cache->crtc.mode_flags = crtc_state->base.adjusted_mode.flags;
 721         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 722                 cache->crtc.hsw_bdw_pixel_rate =
 723                         ilk_pipe_pixel_rate(crtc_state);
 724
 725         cache->plane.rotation = plane_state->base.rotation;
 726         cache->plane.src_w = drm_rect_width(&plane_state->src) >> 16;
 727         cache->plane.src_h = drm_rect_height(&plane_state->src) >> 16;
 728         cache->plane.visible = plane_state->visible;
 729
 730         if (!cache->plane.visible)
 731                 return;
 732
 733         obj = intel_fb_obj(fb);
 734
 735         /* FIXME: We lack the proper locking here, so only run this on the
 736          * platforms that need. */
 737         if (IS_GEN(dev_priv, 5, 6))
 738                 cache->fb.ilk_ggtt_offset = i915_gem_obj_ggtt_offset(obj);
 739         cache->fb.pixel_format = fb->pixel_format;
 740         cache->fb.stride = fb->pitches[0];
 741         cache->fb.fence_reg = obj->fence_reg;
 742         cache->fb.tiling_mode = obj->tiling_mode;
 743 }
 744
 745 static bool intel_fbc_can_activate(struct intel_crtc *crtc)
 746 {
 747         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 748         struct intel_fbc *fbc = &dev_priv->fbc;
 749         struct intel_fbc_state_cache *cache = &fbc->state_cache;
 750
 751         if (!cache->plane.visible) {
 752                 fbc->no_fbc_reason = "primary plane not visible";
 753                 return false;
 754         }
 755
 756         if ((cache->crtc.mode_flags & DRM_MODE_FLAG_INTERLACE) ||
 757             (cache->crtc.mode_flags & DRM_MODE_FLAG_DBLSCAN)) {
 758                 fbc->no_fbc_reason = "incompatible mode";
 759                 return false;
 760         }
 761
 762         if (!intel_fbc_hw_tracking_covers_screen(crtc)) {
 763                 fbc->no_fbc_reason = "mode too large for compression";
 764                 return false;
 765         }
 766
 767         /* The use of a CPU fence is mandatory in order to detect writes
 768          * by the CPU to the scanout and trigger updates to the FBC.
 769          */
 770         if (cache->fb.tiling_mode != I915_TILING_X ||
 771             cache->fb.fence_reg == I915_FENCE_REG_NONE) {
 772                 fbc->no_fbc_reason = "framebuffer not tiled or fenced";
 773                 return false;
 774         }
 775         if (INTEL_INFO(dev_priv)->gen <= 4 && !IS_G4X(dev_priv) &&
 776             cache->plane.rotation != BIT(DRM_ROTATE_0)) {
 777                 fbc->no_fbc_reason = "rotation unsupported";
 778                 return false;
 779         }
 780
 781         if (!stride_is_valid(dev_priv, cache->fb.stride)) {
 782                 fbc->no_fbc_reason = "framebuffer stride not supported";
 783                 return false;
 784         }
 785
 786         if (!pixel_format_is_valid(dev_priv, cache->fb.pixel_format)) {
 787                 fbc->no_fbc_reason = "pixel format is invalid";
 788                 return false;
 789         }
 790
 791         /* WaFbcExceedCdClockThreshold:hsw,bdw */
 792         if ((IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) &&
 793             cache->crtc.hsw_bdw_pixel_rate >= dev_priv->cdclk_freq * 95 / 100) {
 794                 fbc->no_fbc_reason = "pixel rate is too big";
 795                 return false;
 796         }
 797
 798         /* It is possible for the required CFB size change without a
 799          * crtc->disable + crtc->enable since it is possible to change the
 800          * stride without triggering a full modeset. Since we try to
 801          * over-allocate the CFB, there's a chance we may keep FBC enabled even
 802          * if this happens, but if we exceed the current CFB size we'll have to
 803          * disable FBC. Notice that it would be possible to disable FBC, wait
 804          * for a frame, free the stolen node, then try to reenable FBC in case
 805          * we didn't get any invalidate/deactivate calls, but this would require
 806          * a lot of tracking just for a specific case. If we conclude it's an
 807          * important case, we can implement it later. */
 808         if (intel_fbc_calculate_cfb_size(dev_priv, &fbc->state_cache) >
 809             fbc->compressed_fb.size * fbc->threshold) {
 810                 fbc->no_fbc_reason = "CFB requirements changed";
 811                 return false;
 812         }
 813
 814         return true;
 815 }
 816
 817 static bool intel_fbc_can_choose(struct intel_crtc *crtc)
 818 {
 819         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 820         struct intel_fbc *fbc = &dev_priv->fbc;
 821
 822         if (intel_vgpu_active(dev_priv)) {
 823                 fbc->no_fbc_reason = "VGPU is active";
 824                 return false;
 825         }
 826
 827         if (!i915.enable_fbc) {
 828                 fbc->no_fbc_reason = "disabled per module param or by default";
 829                 return false;
 830         }
 831
 832         if (fbc_on_pipe_a_only(dev_priv) && crtc->pipe != PIPE_A) {
 833                 fbc->no_fbc_reason = "no enabled pipes can have FBC";
 834                 return false;
 835         }
 836
 837         if (fbc_on_plane_a_only(dev_priv) && crtc->plane != PLANE_A) {
 838                 fbc->no_fbc_reason = "no enabled planes can have FBC";
 839                 return false;
 840         }
 841
 842         return true;
 843 }
 844
 845 static void intel_fbc_get_reg_params(struct intel_crtc *crtc,
 846                                      struct intel_fbc_reg_params *params)
 847 {
 848         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 849         struct intel_fbc *fbc = &dev_priv->fbc;
 850         struct intel_fbc_state_cache *cache = &fbc->state_cache;
 851
 852         /* Since all our fields are integer types, use memset here so the
 853          * comparison function can rely on memcmp because the padding will be
 854          * zero. */
 855         memset(params, 0, sizeof(*params));
 856
 857         params->crtc.pipe = crtc->pipe;
 858         params->crtc.plane = crtc->plane;
 859         params->crtc.fence_y_offset = get_crtc_fence_y_offset(crtc);
 860
 861         params->fb.pixel_format = cache->fb.pixel_format;
 862         params->fb.stride = cache->fb.stride;
 863         params->fb.fence_reg = cache->fb.fence_reg;
 864
 865         params->cfb_size = intel_fbc_calculate_cfb_size(dev_priv, cache);
 866
 867         params->fb.ggtt_offset = cache->fb.ilk_ggtt_offset;
 868 }
 869
 870 static bool intel_fbc_reg_params_equal(struct intel_fbc_reg_params *params1,
 871                                        struct intel_fbc_reg_params *params2)
 872 {
 873         /* We can use this since intel_fbc_get_reg_params() does a memset. */
 874         return memcmp(params1, params2, sizeof(*params1)) == 0;
 875 }
 876
 877 void intel_fbc_pre_update(struct intel_crtc *crtc,
 878                           struct intel_crtc_state *crtc_state,
 879                           struct intel_plane_state *plane_state)
 880 {
 881         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 882         struct intel_fbc *fbc = &dev_priv->fbc;
 883
 884         if (!fbc_supported(dev_priv))
 885                 return;
 886
 887         mutex_lock(&fbc->lock);
 888
 889         if (!multiple_pipes_ok(crtc, plane_state)) {
 890                 fbc->no_fbc_reason = "more than one pipe active";
 891                 goto deactivate;
 892         }
 893
 894         if (!fbc->enabled || fbc->crtc != crtc)
 895                 goto unlock;
 896
 897         intel_fbc_update_state_cache(crtc, crtc_state, plane_state);
 898
 899 deactivate:
 900         intel_fbc_deactivate(dev_priv);
 901 unlock:
 902         mutex_unlock(&fbc->lock);
 903 }
 904
 905 static void __intel_fbc_post_update(struct intel_crtc *crtc)
 906 {
 907         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 908         struct intel_fbc *fbc = &dev_priv->fbc;
 909         struct intel_fbc_reg_params old_params;
 910
 911         WARN_ON(!mutex_is_locked(&fbc->lock));
 912
 913         if (!fbc->enabled || fbc->crtc != crtc)
 914                 return;
 915
 916         if (!intel_fbc_can_activate(crtc)) {
 917                 WARN_ON(fbc->active);
 918                 return;
 919         }
 920
 921         old_params = fbc->params;
 922         intel_fbc_get_reg_params(crtc, &fbc->params);
 923
 924         /* If the scanout has not changed, don't modify the FBC settings.
 925          * Note that we make the fundamental assumption that the fb->obj
 926          * cannot be unpinned (and have its GTT offset and fence revoked)
 927          * without first being decoupled from the scanout and FBC disabled.
 928          */
 929         if (fbc->active &&
 930             intel_fbc_reg_params_equal(&old_params, &fbc->params))
 931                 return;
 932
 933         intel_fbc_deactivate(dev_priv);
 934         intel_fbc_schedule_activation(crtc);
 935         fbc->no_fbc_reason = "FBC enabled (active or scheduled)";
 936 }
 937
 938 void intel_fbc_post_update(struct intel_crtc *crtc)
 939 {
 940         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 941         struct intel_fbc *fbc = &dev_priv->fbc;
 942
 943         if (!fbc_supported(dev_priv))
 944                 return;
 945
 946         mutex_lock(&fbc->lock);
 947         __intel_fbc_post_update(crtc);
 948         mutex_unlock(&fbc->lock);
 949 }
 950
 951 static unsigned int intel_fbc_get_frontbuffer_bit(struct intel_fbc *fbc)
 952 {
 953         if (fbc->enabled)
 954                 return to_intel_plane(fbc->crtc->base.primary)->frontbuffer_bit;
 955         else
 956                 return fbc->possible_framebuffer_bits;
 957 }
 958
 959 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
 960                           unsigned int frontbuffer_bits,
 961                           enum fb_op_origin origin)
 962 {
 963         struct intel_fbc *fbc = &dev_priv->fbc;
 964
 965         if (!fbc_supported(dev_priv))
 966                 return;
 967
 968         if (origin == ORIGIN_GTT || origin == ORIGIN_FLIP)
 969                 return;
 970
 971         mutex_lock(&fbc->lock);
 972
 973         fbc->busy_bits |= intel_fbc_get_frontbuffer_bit(fbc) & frontbuffer_bits;
 974
 975         if (fbc->enabled && fbc->busy_bits)
 976                 intel_fbc_deactivate(dev_priv);
 977
 978         mutex_unlock(&fbc->lock);
 979 }
 980
 981 void intel_fbc_flush(struct drm_i915_private *dev_priv,
 982                      unsigned int frontbuffer_bits, enum fb_op_origin origin)
 983 {
 984         struct intel_fbc *fbc = &dev_priv->fbc;
 985
 986         if (!fbc_supported(dev_priv))
 987                 return;
 988
 989         mutex_lock(&fbc->lock);
 990
 991         fbc->busy_bits &= ~frontbuffer_bits;
 992
 993         if (origin == ORIGIN_GTT || origin == ORIGIN_FLIP)
 994                 goto out;
 995
 996         if (!fbc->busy_bits && fbc->enabled &&
 997             (frontbuffer_bits & intel_fbc_get_frontbuffer_bit(fbc))) {
 998                 if (fbc->active)
 999                         intel_fbc_recompress(dev_priv);
1000                 else
1001                         __intel_fbc_post_update(fbc->crtc);
1002         }
1003
1004 out:
1005         mutex_unlock(&fbc->lock);
1006 }
1007
1008 /**
1009  * intel_fbc_choose_crtc - select a CRTC to enable FBC on
1010  * @dev_priv: i915 device instance
1011  * @state: the atomic state structure
1012  *
1013  * This function looks at the proposed state for CRTCs and planes, then chooses
1014  * which pipe is going to have FBC by setting intel_crtc_state->enable_fbc to
1015  * true.
1016  *
1017  * Later, intel_fbc_enable is going to look for state->enable_fbc and then maybe
1018  * enable FBC for the chosen CRTC. If it does, it will set dev_priv->fbc.crtc.
1019  */
1020 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1021                            struct drm_atomic_state *state)
1022 {
1023         struct intel_fbc *fbc = &dev_priv->fbc;
1024         struct drm_crtc *crtc;
1025         struct drm_crtc_state *crtc_state;
1026         struct drm_plane *plane;
1027         struct drm_plane_state *plane_state;
1028         bool fbc_crtc_present = false;
1029         int i, j;
1030
1031         mutex_lock(&fbc->lock);
1032
1033         for_each_crtc_in_state(state, crtc, crtc_state, i) {
1034                 if (fbc->crtc == to_intel_crtc(crtc)) {
1035                         fbc_crtc_present = true;
1036                         break;
1037                 }
1038         }
1039         /* This atomic commit doesn't involve the CRTC currently tied to FBC. */
1040         if (!fbc_crtc_present && fbc->crtc != NULL)
1041                 goto out;
1042
1043         /* Simply choose the first CRTC that is compatible and has a visible
1044          * plane. We could go for fancier schemes such as checking the plane
1045          * size, but this would just affect the few platforms that don't tie FBC
1046          * to pipe or plane A. */
1047         for_each_plane_in_state(state, plane, plane_state, i) {
1048                 struct intel_plane_state *intel_plane_state =
1049                         to_intel_plane_state(plane_state);
1050
1051                 if (!intel_plane_state->visible)
1052                         continue;
1053
1054                 for_each_crtc_in_state(state, crtc, crtc_state, j) {
1055                         struct intel_crtc_state *intel_crtc_state =
1056                                 to_intel_crtc_state(crtc_state);
1057
1058                         if (plane_state->crtc != crtc)
1059                                 continue;
1060
1061                         if (!intel_fbc_can_choose(to_intel_crtc(crtc)))
1062                                 break;
1063
1064                         intel_crtc_state->enable_fbc = true;
1065                         goto out;
1066                 }
1067         }
1068
1069 out:
1070         mutex_unlock(&fbc->lock);
1071 }
1072
1073 /**
1074  * intel_fbc_enable: tries to enable FBC on the CRTC
1075  * @crtc: the CRTC
1076  *
1077  * This function checks if the given CRTC was chosen for FBC, then enables it if
1078  * possible. Notice that it doesn't activate FBC. It is valid to call
1079  * intel_fbc_enable multiple times for the same pipe without an
1080  * intel_fbc_disable in the middle, as long as it is deactivated.
1081  */
1082 void intel_fbc_enable(struct intel_crtc *crtc,
1083                       struct intel_crtc_state *crtc_state,
1084                       struct intel_plane_state *plane_state)
1085 {
1086         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1087         struct intel_fbc *fbc = &dev_priv->fbc;
1088
1089         if (!fbc_supported(dev_priv))
1090                 return;
1091
1092         mutex_lock(&fbc->lock);
1093
1094         if (fbc->enabled) {
1095                 WARN_ON(fbc->crtc == NULL);
1096                 if (fbc->crtc == crtc) {
1097                         WARN_ON(!crtc_state->enable_fbc);
1098                         WARN_ON(fbc->active);
1099                 }
1100                 goto out;
1101         }
1102
1103         if (!crtc_state->enable_fbc)
1104                 goto out;
1105
1106         WARN_ON(fbc->active);
1107         WARN_ON(fbc->crtc != NULL);
1108
1109         intel_fbc_update_state_cache(crtc, crtc_state, plane_state);
1110         if (intel_fbc_alloc_cfb(crtc)) {
1111                 fbc->no_fbc_reason = "not enough stolen memory";
1112                 goto out;
1113         }
1114
1115         DRM_DEBUG_KMS("Enabling FBC on pipe %c\n", pipe_name(crtc->pipe));
1116         fbc->no_fbc_reason = "FBC enabled but not active yet\n";
1117
1118         fbc->enabled = true;
1119         fbc->crtc = crtc;
1120 out:
1121         mutex_unlock(&fbc->lock);
1122 }
1123
1124 /**
1125  * __intel_fbc_disable - disable FBC
1126  * @dev_priv: i915 device instance
1127  *
1128  * This is the low level function that actually disables FBC. Callers should
1129  * grab the FBC lock.
1130  */
1131 static void __intel_fbc_disable(struct drm_i915_private *dev_priv)
1132 {
1133         struct intel_fbc *fbc = &dev_priv->fbc;
1134         struct intel_crtc *crtc = fbc->crtc;
1135
1136         WARN_ON(!mutex_is_locked(&fbc->lock));
1137         WARN_ON(!fbc->enabled);
1138         WARN_ON(fbc->active);
1139         WARN_ON(crtc->active);
1140
1141         DRM_DEBUG_KMS("Disabling FBC on pipe %c\n", pipe_name(crtc->pipe));
1142
1143         __intel_fbc_cleanup_cfb(dev_priv);
1144
1145         fbc->enabled = false;
1146         fbc->crtc = NULL;
1147 }
1148
1149 /**
1150  * intel_fbc_disable - disable FBC if it's associated with crtc
1151  * @crtc: the CRTC
1152  *
1153  * This function disables FBC if it's associated with the provided CRTC.
1154  */
1155 void intel_fbc_disable(struct intel_crtc *crtc)
1156 {
1157         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1158         struct intel_fbc *fbc = &dev_priv->fbc;
1159
1160         if (!fbc_supported(dev_priv))
1161                 return;
1162
1163         mutex_lock(&fbc->lock);
1164         if (fbc->crtc == crtc) {
1165                 WARN_ON(!fbc->enabled);
1166                 WARN_ON(fbc->active);
1167                 __intel_fbc_disable(dev_priv);
1168         }
1169         mutex_unlock(&fbc->lock);
1170
1171         cancel_work_sync(&fbc->work.work);
1172 }
1173
1174 /**
1175  * intel_fbc_global_disable - globally disable FBC
1176  * @dev_priv: i915 device instance
1177  *
1178  * This function disables FBC regardless of which CRTC is associated with it.
1179  */
1180 void intel_fbc_global_disable(struct drm_i915_private *dev_priv)
1181 {
1182         struct intel_fbc *fbc = &dev_priv->fbc;
1183
1184         if (!fbc_supported(dev_priv))
1185                 return;
1186
1187         mutex_lock(&fbc->lock);
1188         if (fbc->enabled)
1189                 __intel_fbc_disable(dev_priv);
1190         mutex_unlock(&fbc->lock);
1191
1192         cancel_work_sync(&fbc->work.work);
1193 }
1194
1195 /**
1196  * intel_fbc_init_pipe_state - initialize FBC's CRTC visibility tracking
1197  * @dev_priv: i915 device instance
1198  *
1199  * The FBC code needs to track CRTC visibility since the older platforms can't
1200  * have FBC enabled while multiple pipes are used. This function does the
1201  * initial setup at driver load to make sure FBC is matching the real hardware.
1202  */
1203 void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv)
1204 {
1205         struct intel_crtc *crtc;
1206
1207         /* Don't even bother tracking anything if we don't need. */
1208         if (!no_fbc_on_multiple_pipes(dev_priv))
1209                 return;
1210
1211         for_each_intel_crtc(dev_priv->dev, crtc)
1212                 if (intel_crtc_active(&crtc->base) &&
1213                     to_intel_plane_state(crtc->base.primary->state)->visible)
1214                         dev_priv->fbc.visible_pipes_mask |= (1 << crtc->pipe);
1215 }
1216
1217 /*
1218  * The DDX driver changes its behavior depending on the value it reads from
1219  * i915.enable_fbc, so sanitize it by translating the default value into either
1220  * 0 or 1 in order to allow it to know what's going on.
1221  *
1222  * Notice that this is done at driver initialization and we still allow user
1223  * space to change the value during runtime without sanitizing it again. IGT
1224  * relies on being able to change i915.enable_fbc at runtime.
1225  */
1226 static int intel_sanitize_fbc_option(struct drm_i915_private *dev_priv)
1227 {
1228         if (i915.enable_fbc >= 0)
1229                 return !!i915.enable_fbc;
1230
1231         if (IS_BROADWELL(dev_priv))
1232                 return 1;
1233
1234         return 0;
1235 }
1236
1237 /**
1238  * intel_fbc_init - Initialize FBC
1239  * @dev_priv: the i915 device
1240  *
1241  * This function might be called during PM init process.
1242  */
1243 void intel_fbc_init(struct drm_i915_private *dev_priv)
1244 {
1245         struct intel_fbc *fbc = &dev_priv->fbc;
1246         enum pipe pipe;
1247
1248         INIT_WORK(&fbc->work.work, intel_fbc_work_fn);
1249         mutex_init(&fbc->lock);
1250         fbc->enabled = false;
1251         fbc->active = false;
1252         fbc->work.scheduled = false;
1253
1254         i915.enable_fbc = intel_sanitize_fbc_option(dev_priv);
1255         DRM_DEBUG_KMS("Sanitized enable_fbc value: %d\n", i915.enable_fbc);
1256
1257         if (!HAS_FBC(dev_priv)) {
1258                 fbc->no_fbc_reason = "unsupported by this chipset";
1259                 return;
1260         }
1261
1262         for_each_pipe(dev_priv, pipe) {
1263                 fbc->possible_framebuffer_bits |=
1264                                 INTEL_FRONTBUFFER_PRIMARY(pipe);
1265
1266                 if (fbc_on_pipe_a_only(dev_priv))
1267                         break;
1268         }
1269
1270         /* This value was pulled out of someone's hat */
1271         if (INTEL_INFO(dev_priv)->gen <= 4 && !IS_GM45(dev_priv))
1272                 I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT);
1273
1274         /* We still don't have any sort of hardware state readout for FBC, so
1275          * deactivate it in case the BIOS activated it to make sure software
1276          * matches the hardware state. */
1277         if (intel_fbc_hw_is_active(dev_priv))
1278                 intel_fbc_hw_deactivate(dev_priv);
1279 }