drivers/gpu/drm/i915/intel_guc_loader.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Vinit Azad <vinit.azad@intel.com>
  25  *    Ben Widawsky <ben@bwidawsk.net>
  26  *    Dave Gordon <david.s.gordon@intel.com>
  27  *    Alex Dai <yu.dai@intel.com>
  28  */
  29 #include <linux/firmware.h>
  30 #include "i915_drv.h"
  31 #include "intel_guc.h"
  32
  33 /**
  34  * DOC: GuC-specific firmware loader
  35  *
  36  * intel_guc:
  37  * Top level structure of guc. It handles firmware loading and manages client
  38  * pool and doorbells. intel_guc owns a i915_guc_client to replace the legacy
  39  * ExecList submission.
  40  *
  41  * Firmware versioning:
  42  * The firmware build process will generate a version header file with major and
  43  * minor version defined. The versions are built into CSS header of firmware.
  44  * i915 kernel driver set the minimal firmware version required per platform.
  45  * The firmware installation package will install (symbolic link) proper version
  46  * of firmware.
  47  *
  48  * GuC address space:
  49  * GuC does not allow any gfx GGTT address that falls into range [0, WOPCM_TOP),
  50  * which is reserved for Boot ROM, SRAM and WOPCM. Currently this top address is
  51  * 512K. In order to exclude 0-512K address space from GGTT, all gfx objects
  52  * used by GuC is pinned with PIN_OFFSET_BIAS along with size of WOPCM.
  53  *
  54  * Firmware log:
  55  * Firmware log is enabled by setting i915.guc_log_level to non-negative level.
  56  * Log data is printed out via reading debugfs i915_guc_log_dump. Reading from
  57  * i915_guc_load_status will print out firmware loading status and scratch
  58  * registers value.
  59  *
  60  */
  61
  62 #define SKL_FW_MAJOR 6
  63 #define SKL_FW_MINOR 1
  64
  65 #define BXT_FW_MAJOR 8
  66 #define BXT_FW_MINOR 7
  67
  68 #define KBL_FW_MAJOR 9
  69 #define KBL_FW_MINOR 14
  70
  71 #define GUC_FW_PATH(platform, major, minor) \
  72        "i915/" __stringify(platform) "_guc_ver" __stringify(major) "_" __stringify(minor) ".bin"
  73
  74 #define I915_SKL_GUC_UCODE GUC_FW_PATH(skl, SKL_FW_MAJOR, SKL_FW_MINOR)
  75 MODULE_FIRMWARE(I915_SKL_GUC_UCODE);
  76
  77 #define I915_BXT_GUC_UCODE GUC_FW_PATH(bxt, BXT_FW_MAJOR, BXT_FW_MINOR)
  78 MODULE_FIRMWARE(I915_BXT_GUC_UCODE);
  79
  80 #define I915_KBL_GUC_UCODE GUC_FW_PATH(kbl, KBL_FW_MAJOR, KBL_FW_MINOR)
  81 MODULE_FIRMWARE(I915_KBL_GUC_UCODE);
  82
  83 /* User-friendly representation of an enum */
  84 const char *intel_guc_fw_status_repr(enum intel_guc_fw_status status)
  85 {
  86         switch (status) {
  87         case GUC_FIRMWARE_FAIL:
  88                 return "FAIL";
  89         case GUC_FIRMWARE_NONE:
  90                 return "NONE";
  91         case GUC_FIRMWARE_PENDING:
  92                 return "PENDING";
  93         case GUC_FIRMWARE_SUCCESS:
  94                 return "SUCCESS";
  95         default:
  96                 return "UNKNOWN!";
  97         }
  98 };
  99
 100 static void direct_interrupts_to_host(struct drm_i915_private *dev_priv)
 101 {
 102         struct intel_engine_cs *engine;
 103         int irqs;
 104
 105         /* tell all command streamers NOT to forward interrupts or vblank to GuC */
 106         irqs = _MASKED_FIELD(GFX_FORWARD_VBLANK_MASK, GFX_FORWARD_VBLANK_NEVER);
 107         irqs |= _MASKED_BIT_DISABLE(GFX_INTERRUPT_STEERING);
 108         for_each_engine(engine, dev_priv)
 109                 I915_WRITE(RING_MODE_GEN7(engine), irqs);
 110
 111         /* route all GT interrupts to the host */
 112         I915_WRITE(GUC_BCS_RCS_IER, 0);
 113         I915_WRITE(GUC_VCS2_VCS1_IER, 0);
 114         I915_WRITE(GUC_WD_VECS_IER, 0);
 115 }
 116
 117 static void direct_interrupts_to_guc(struct drm_i915_private *dev_priv)
 118 {
 119         struct intel_engine_cs *engine;
 120         int irqs;
 121         u32 tmp;
 122
 123         /* tell all command streamers to forward interrupts (but not vblank) to GuC */
 124         irqs = _MASKED_BIT_ENABLE(GFX_INTERRUPT_STEERING);
 125         for_each_engine(engine, dev_priv)
 126                 I915_WRITE(RING_MODE_GEN7(engine), irqs);
 127
 128         /* route USER_INTERRUPT to Host, all others are sent to GuC. */
 129         irqs = GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
 130                GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
 131         /* These three registers have the same bit definitions */
 132         I915_WRITE(GUC_BCS_RCS_IER, ~irqs);
 133         I915_WRITE(GUC_VCS2_VCS1_IER, ~irqs);
 134         I915_WRITE(GUC_WD_VECS_IER, ~irqs);
 135
 136         /*
 137          * If GuC has routed PM interrupts to itself, don't keep it.
 138          * and keep other interrupts those are unmasked by GuC.
 139         */
 140         tmp = I915_READ(GEN6_PMINTRMSK);
 141         if (tmp & GEN8_PMINTR_REDIRECT_TO_NON_DISP) {
 142                 dev_priv->rps.pm_intr_keep |= ~(tmp & ~GEN8_PMINTR_REDIRECT_TO_NON_DISP);
 143                 dev_priv->rps.pm_intr_keep &= ~GEN8_PMINTR_REDIRECT_TO_NON_DISP;
 144         }
 145 }
 146
 147 static u32 get_gttype(struct drm_i915_private *dev_priv)
 148 {
 149         /* XXX: GT type based on PCI device ID? field seems unused by fw */
 150         return 0;
 151 }
 152
 153 static u32 get_core_family(struct drm_i915_private *dev_priv)
 154 {
 155         switch (INTEL_INFO(dev_priv)->gen) {
 156         case 9:
 157                 return GFXCORE_FAMILY_GEN9;
 158
 159         default:
 160                 DRM_ERROR("GUC: unsupported core family\n");
 161                 return GFXCORE_FAMILY_UNKNOWN;
 162         }
 163 }
 164
 165 static void set_guc_init_params(struct drm_i915_private *dev_priv)
 166 {
 167         struct intel_guc *guc = &dev_priv->guc;
 168         u32 params[GUC_CTL_MAX_DWORDS];
 169         int i;
 170
 171         memset(&params, 0, sizeof(params));
 172
 173         params[GUC_CTL_DEVICE_INFO] |=
 174                 (get_gttype(dev_priv) << GUC_CTL_GTTYPE_SHIFT) |
 175                 (get_core_family(dev_priv) << GUC_CTL_COREFAMILY_SHIFT);
 176
 177         /*
 178          * GuC ARAT increment is 10 ns. GuC default scheduler quantum is one
 179          * second. This ARAR is calculated by:
 180          * Scheduler-Quantum-in-ns / ARAT-increment-in-ns = 1000000000 / 10
 181          */
 182         params[GUC_CTL_ARAT_HIGH] = 0;
 183         params[GUC_CTL_ARAT_LOW] = 100000000;
 184
 185         params[GUC_CTL_WA] |= GUC_CTL_WA_UK_BY_DRIVER;
 186
 187         params[GUC_CTL_FEATURE] |= GUC_CTL_DISABLE_SCHEDULER |
 188                         GUC_CTL_VCS2_ENABLED;
 189
 190         if (i915.guc_log_level >= 0) {
 191                 params[GUC_CTL_LOG_PARAMS] = guc->log_flags;
 192                 params[GUC_CTL_DEBUG] =
 193                         i915.guc_log_level << GUC_LOG_VERBOSITY_SHIFT;
 194         }
 195
 196         if (guc->ads_vma) {
 197                 u32 ads = i915_ggtt_offset(guc->ads_vma) >> PAGE_SHIFT;
 198                 params[GUC_CTL_DEBUG] |= ads << GUC_ADS_ADDR_SHIFT;
 199                 params[GUC_CTL_DEBUG] |= GUC_ADS_ENABLED;
 200         }
 201
 202         /* If GuC submission is enabled, set up additional parameters here */
 203         if (i915.enable_guc_submission) {
 204                 u32 pgs = i915_ggtt_offset(dev_priv->guc.ctx_pool_vma);
 205                 u32 ctx_in_16 = GUC_MAX_GPU_CONTEXTS / 16;
 206
 207                 pgs >>= PAGE_SHIFT;
 208                 params[GUC_CTL_CTXINFO] = (pgs << GUC_CTL_BASE_ADDR_SHIFT) |
 209                         (ctx_in_16 << GUC_CTL_CTXNUM_IN16_SHIFT);
 210
 211                 params[GUC_CTL_FEATURE] |= GUC_CTL_KERNEL_SUBMISSIONS;
 212
 213                 /* Unmask this bit to enable the GuC's internal scheduler */
 214                 params[GUC_CTL_FEATURE] &= ~GUC_CTL_DISABLE_SCHEDULER;
 215         }
 216
 217         I915_WRITE(SOFT_SCRATCH(0), 0);
 218
 219         for (i = 0; i < GUC_CTL_MAX_DWORDS; i++)
 220                 I915_WRITE(SOFT_SCRATCH(1 + i), params[i]);
 221 }
 222
 223 /*
 224  * Read the GuC status register (GUC_STATUS) and store it in the
 225  * specified location; then return a boolean indicating whether
 226  * the value matches either of two values representing completion
 227  * of the GuC boot process.
 228  *
 229  * This is used for polling the GuC status in a wait_for()
 230  * loop below.
 231  */
 232 static inline bool guc_ucode_response(struct drm_i915_private *dev_priv,
 233                                       u32 *status)
 234 {
 235         u32 val = I915_READ(GUC_STATUS);
 236         u32 uk_val = val & GS_UKERNEL_MASK;
 237         *status = val;
 238         return (uk_val == GS_UKERNEL_READY ||
 239                 ((val & GS_MIA_CORE_STATE) && uk_val == GS_UKERNEL_LAPIC_DONE));
 240 }
 241
 242 /*
 243  * Transfer the firmware image to RAM for execution by the microcontroller.
 244  *
 245  * Architecturally, the DMA engine is bidirectional, and can potentially even
 246  * transfer between GTT locations. This functionality is left out of the API
 247  * for now as there is no need for it.
 248  *
 249  * Note that GuC needs the CSS header plus uKernel code to be copied by the
 250  * DMA engine in one operation, whereas the RSA signature is loaded via MMIO.
 251  */
 252 static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv,
 253                               struct i915_vma *vma)
 254 {
 255         struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
 256         unsigned long offset;
 257         struct sg_table *sg = vma->pages;
 258         u32 status, rsa[UOS_RSA_SCRATCH_MAX_COUNT];
 259         int i, ret = 0;
 260
 261         /* where RSA signature starts */
 262         offset = guc_fw->rsa_offset;
 263
 264         /* Copy RSA signature from the fw image to HW for verification */
 265         sg_pcopy_to_buffer(sg->sgl, sg->nents, rsa, sizeof(rsa), offset);
 266         for (i = 0; i < UOS_RSA_SCRATCH_MAX_COUNT; i++)
 267                 I915_WRITE(UOS_RSA_SCRATCH(i), rsa[i]);
 268
 269         /* The header plus uCode will be copied to WOPCM via DMA, excluding any
 270          * other components */
 271         I915_WRITE(DMA_COPY_SIZE, guc_fw->header_size + guc_fw->ucode_size);
 272
 273         /* Set the source address for the new blob */
 274         offset = i915_ggtt_offset(vma) + guc_fw->header_offset;
 275         I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset));
 276         I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF);
 277
 278         /*
 279          * Set the DMA destination. Current uCode expects the code to be
 280          * loaded at 8k; locations below this are used for the stack.
 281          */
 282         I915_WRITE(DMA_ADDR_1_LOW, 0x2000);
 283         I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
 284
 285         /* Finally start the DMA */
 286         I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE | START_DMA));
 287
 288         /*
 289          * Wait for the DMA to complete & the GuC to start up.
 290          * NB: Docs recommend not using the interrupt for completion.
 291          * Measurements indicate this should take no more than 20ms, so a
 292          * timeout here indicates that the GuC has failed and is unusable.
 293          * (Higher levels of the driver will attempt to fall back to
 294          * execlist mode if this happens.)
 295          */
 296         ret = wait_for(guc_ucode_response(dev_priv, &status), 100);
 297
 298         DRM_DEBUG_DRIVER("DMA status 0x%x, GuC status 0x%x\n",
 299                         I915_READ(DMA_CTRL), status);
 300
 301         if ((status & GS_BOOTROM_MASK) == GS_BOOTROM_RSA_FAILED) {
 302                 DRM_ERROR("GuC firmware signature verification failed\n");
 303                 ret = -ENOEXEC;
 304         }
 305
 306         DRM_DEBUG_DRIVER("returning %d\n", ret);
 307
 308         return ret;
 309 }
 310
 311 static u32 guc_wopcm_size(struct drm_i915_private *dev_priv)
 312 {
 313         u32 wopcm_size = GUC_WOPCM_TOP;
 314
 315         /* On BXT, the top of WOPCM is reserved for RC6 context */
 316         if (IS_BROXTON(dev_priv))
 317                 wopcm_size -= BXT_GUC_WOPCM_RC6_RESERVED;
 318
 319         return wopcm_size;
 320 }
 321
 322 /*
 323  * Load the GuC firmware blob into the MinuteIA.
 324  */
 325 static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
 326 {
 327         struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
 328         struct drm_device *dev = &dev_priv->drm;
 329         struct i915_vma *vma;
 330         int ret;
 331
 332         ret = i915_gem_object_set_to_gtt_domain(guc_fw->guc_fw_obj, false);
 333         if (ret) {
 334                 DRM_DEBUG_DRIVER("set-domain failed %d\n", ret);
 335                 return ret;
 336         }
 337
 338         vma = i915_gem_object_ggtt_pin(guc_fw->guc_fw_obj, NULL, 0, 0, 0);
 339         if (IS_ERR(vma)) {
 340                 DRM_DEBUG_DRIVER("pin failed %d\n", (int)PTR_ERR(vma));
 341                 return PTR_ERR(vma);
 342         }
 343
 344         /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
 345         I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
 346
 347         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
 348
 349         /* init WOPCM */
 350         I915_WRITE(GUC_WOPCM_SIZE, guc_wopcm_size(dev_priv));
 351         I915_WRITE(DMA_GUC_WOPCM_OFFSET, GUC_WOPCM_OFFSET_VALUE);
 352
 353         /* Enable MIA caching. GuC clock gating is disabled. */
 354         I915_WRITE(GUC_SHIM_CONTROL, GUC_SHIM_CONTROL_VALUE);
 355
 356         /* WaDisableMinuteIaClockGating:skl,bxt */
 357         if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
 358             IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
 359                 I915_WRITE(GUC_SHIM_CONTROL, (I915_READ(GUC_SHIM_CONTROL) &
 360                                               ~GUC_ENABLE_MIA_CLOCK_GATING));
 361         }
 362
 363         /* WaC6DisallowByGfxPause*/
 364         if (IS_SKL_REVID(dev, 0, SKL_REVID_C0) ||
 365             IS_BXT_REVID(dev, 0, BXT_REVID_B0))
 366                 I915_WRITE(GEN6_GFXPAUSE, 0x30FFF);
 367
 368         if (IS_BROXTON(dev))
 369                 I915_WRITE(GEN9LP_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
 370         else
 371                 I915_WRITE(GEN9_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
 372
 373         if (IS_GEN9(dev)) {
 374                 /* DOP Clock Gating Enable for GuC clocks */
 375                 I915_WRITE(GEN7_MISCCPCTL, (GEN8_DOP_CLOCK_GATE_GUC_ENABLE |
 376                                             I915_READ(GEN7_MISCCPCTL)));
 377
 378                 /* allows for 5us before GT can go to RC6 */
 379                 I915_WRITE(GUC_ARAT_C6DIS, 0x1FF);
 380         }
 381
 382         set_guc_init_params(dev_priv);
 383
 384         ret = guc_ucode_xfer_dma(dev_priv, vma);
 385
 386         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
 387
 388         /*
 389          * We keep the object pages for reuse during resume. But we can unpin it
 390          * now that DMA has completed, so it doesn't continue to take up space.
 391          */
 392         i915_vma_unpin(vma);
 393
 394         return ret;
 395 }
 396
 397 static int i915_reset_guc(struct drm_i915_private *dev_priv)
 398 {
 399         int ret;
 400         u32 guc_status;
 401
 402         ret = intel_guc_reset(dev_priv);
 403         if (ret) {
 404                 DRM_ERROR("GuC reset failed, ret = %d\n", ret);
 405                 return ret;
 406         }
 407
 408         guc_status = I915_READ(GUC_STATUS);
 409         WARN(!(guc_status & GS_MIA_IN_RESET),
 410              "GuC status: 0x%x, MIA core expected to be in reset\n", guc_status);
 411
 412         return ret;
 413 }
 414
 415 /**
 416  * intel_guc_setup() - finish preparing the GuC for activity
 417  * @dev:        drm device
 418  *
 419  * Called from gem_init_hw() during driver loading and also after a GPU reset.
 420  *
 421  * The main action required here it to load the GuC uCode into the device.
 422  * The firmware image should have already been fetched into memory by the
 423  * earlier call to intel_guc_init(), so here we need only check that worked,
 424  * and then transfer the image to the h/w.
 425  *
 426  * Return:      non-zero code on error
 427  */
 428 int intel_guc_setup(struct drm_device *dev)
 429 {
 430         struct drm_i915_private *dev_priv = to_i915(dev);
 431         struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
 432         const char *fw_path = guc_fw->guc_fw_path;
 433         int retries, ret, err;
 434
 435         DRM_DEBUG_DRIVER("GuC fw status: path %s, fetch %s, load %s\n",
 436                 fw_path,
 437                 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
 438                 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
 439
 440         /* Loading forbidden, or no firmware to load? */
 441         if (!i915.enable_guc_loading) {
 442                 err = 0;
 443                 goto fail;
 444         } else if (fw_path == NULL) {
 445                 /* Device is known to have no uCode (e.g. no GuC) */
 446                 err = -ENXIO;
 447                 goto fail;
 448         } else if (*fw_path == '\0') {
 449                 /* Device has a GuC but we don't know what f/w to load? */
 450                 DRM_INFO("No GuC firmware known for this platform\n");
 451                 err = -ENODEV;
 452                 goto fail;
 453         }
 454
 455         /* Fetch failed, or already fetched but failed to load? */
 456         if (guc_fw->guc_fw_fetch_status != GUC_FIRMWARE_SUCCESS) {
 457                 err = -EIO;
 458                 goto fail;
 459         } else if (guc_fw->guc_fw_load_status == GUC_FIRMWARE_FAIL) {
 460                 err = -ENOEXEC;
 461                 goto fail;
 462         }
 463
 464         direct_interrupts_to_host(dev_priv);
 465
 466         guc_fw->guc_fw_load_status = GUC_FIRMWARE_PENDING;
 467
 468         DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
 469                 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
 470                 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
 471
 472         err = i915_guc_submission_init(dev_priv);
 473         if (err)
 474                 goto fail;
 475
 476         /*
 477          * WaEnableuKernelHeaderValidFix:skl,bxt
 478          * For BXT, this is only upto B0 but below WA is required for later
 479          * steppings also so this is extended as well.
 480          */
 481         /* WaEnableGuCBootHashCheckNotSet:skl,bxt */
 482         for (retries = 3; ; ) {
 483                 /*
 484                  * Always reset the GuC just before (re)loading, so
 485                  * that the state and timing are fairly predictable
 486                  */
 487                 err = i915_reset_guc(dev_priv);
 488                 if (err) {
 489                         DRM_ERROR("GuC reset failed: %d\n", err);
 490                         goto fail;
 491                 }
 492
 493                 err = guc_ucode_xfer(dev_priv);
 494                 if (!err)
 495                         break;
 496
 497                 if (--retries == 0)
 498                         goto fail;
 499
 500                 DRM_INFO("GuC fw load failed: %d; will reset and "
 501                          "retry %d more time(s)\n", err, retries);
 502         }
 503
 504         guc_fw->guc_fw_load_status = GUC_FIRMWARE_SUCCESS;
 505
 506         DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
 507                 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
 508                 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
 509
 510         if (i915.enable_guc_submission) {
 511                 err = i915_guc_submission_enable(dev_priv);
 512                 if (err)
 513                         goto fail;
 514                 direct_interrupts_to_guc(dev_priv);
 515         }
 516
 517         return 0;
 518
 519 fail:
 520         if (guc_fw->guc_fw_load_status == GUC_FIRMWARE_PENDING)
 521                 guc_fw->guc_fw_load_status = GUC_FIRMWARE_FAIL;
 522
 523         direct_interrupts_to_host(dev_priv);
 524         i915_guc_submission_disable(dev_priv);
 525         i915_guc_submission_fini(dev_priv);
 526
 527         /*
 528          * We've failed to load the firmware :(
 529          *
 530          * Decide whether to disable GuC submission and fall back to
 531          * execlist mode, and whether to hide the error by returning
 532          * zero or to return -EIO, which the caller will treat as a
 533          * nonfatal error (i.e. it doesn't prevent driver load, but
 534          * marks the GPU as wedged until reset).
 535          */
 536         if (i915.enable_guc_loading > 1) {
 537                 ret = -EIO;
 538         } else if (i915.enable_guc_submission > 1) {
 539                 ret = -EIO;
 540         } else {
 541                 ret = 0;
 542         }
 543
 544         if (err == 0 && !HAS_GUC_UCODE(dev))
 545                 ;       /* Don't mention the GuC! */
 546         else if (err == 0)
 547                 DRM_INFO("GuC firmware load skipped\n");
 548         else if (ret != -EIO)
 549                 DRM_INFO("GuC firmware load failed: %d\n", err);
 550         else
 551                 DRM_ERROR("GuC firmware load failed: %d\n", err);
 552
 553         if (i915.enable_guc_submission) {
 554                 if (fw_path == NULL)
 555                         DRM_INFO("GuC submission without firmware not supported\n");
 556                 if (ret == 0)
 557                         DRM_INFO("Falling back from GuC submission to execlist mode\n");
 558                 else
 559                         DRM_ERROR("GuC init failed: %d\n", ret);
 560         }
 561         i915.enable_guc_submission = 0;
 562
 563         return ret;
 564 }
 565
 566 static void guc_fw_fetch(struct drm_device *dev, struct intel_guc_fw *guc_fw)
 567 {
 568         struct drm_i915_gem_object *obj;
 569         const struct firmware *fw;
 570         struct guc_css_header *css;
 571         size_t size;
 572         int err;
 573
 574         DRM_DEBUG_DRIVER("before requesting firmware: GuC fw fetch status %s\n",
 575                 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
 576
 577         err = request_firmware(&fw, guc_fw->guc_fw_path, &dev->pdev->dev);
 578         if (err)
 579                 goto fail;
 580         if (!fw)
 581                 goto fail;
 582
 583         DRM_DEBUG_DRIVER("fetch GuC fw from %s succeeded, fw %p\n",
 584                 guc_fw->guc_fw_path, fw);
 585
 586         /* Check the size of the blob before examining buffer contents */
 587         if (fw->size < sizeof(struct guc_css_header)) {
 588                 DRM_ERROR("Firmware header is missing\n");
 589                 goto fail;
 590         }
 591
 592         css = (struct guc_css_header *)fw->data;
 593
 594         /* Firmware bits always start from header */
 595         guc_fw->header_offset = 0;
 596         guc_fw->header_size = (css->header_size_dw - css->modulus_size_dw -
 597                 css->key_size_dw - css->exponent_size_dw) * sizeof(u32);
 598
 599         if (guc_fw->header_size != sizeof(struct guc_css_header)) {
 600                 DRM_ERROR("CSS header definition mismatch\n");
 601                 goto fail;
 602         }
 603
 604         /* then, uCode */
 605         guc_fw->ucode_offset = guc_fw->header_offset + guc_fw->header_size;
 606         guc_fw->ucode_size = (css->size_dw - css->header_size_dw) * sizeof(u32);
 607
 608         /* now RSA */
 609         if (css->key_size_dw != UOS_RSA_SCRATCH_MAX_COUNT) {
 610                 DRM_ERROR("RSA key size is bad\n");
 611                 goto fail;
 612         }
 613         guc_fw->rsa_offset = guc_fw->ucode_offset + guc_fw->ucode_size;
 614         guc_fw->rsa_size = css->key_size_dw * sizeof(u32);
 615
 616         /* At least, it should have header, uCode and RSA. Size of all three. */
 617         size = guc_fw->header_size + guc_fw->ucode_size + guc_fw->rsa_size;
 618         if (fw->size < size) {
 619                 DRM_ERROR("Missing firmware components\n");
 620                 goto fail;
 621         }
 622
 623         /* Header and uCode will be loaded to WOPCM. Size of the two. */
 624         size = guc_fw->header_size + guc_fw->ucode_size;
 625         if (size > guc_wopcm_size(to_i915(dev))) {
 626                 DRM_ERROR("Firmware is too large to fit in WOPCM\n");
 627                 goto fail;
 628         }
 629
 630         /*
 631          * The GuC firmware image has the version number embedded at a well-known
 632          * offset within the firmware blob; note that major / minor version are
 633          * TWO bytes each (i.e. u16), although all pointers and offsets are defined
 634          * in terms of bytes (u8).
 635          */
 636         guc_fw->guc_fw_major_found = css->guc_sw_version >> 16;
 637         guc_fw->guc_fw_minor_found = css->guc_sw_version & 0xFFFF;
 638
 639         if (guc_fw->guc_fw_major_found != guc_fw->guc_fw_major_wanted ||
 640             guc_fw->guc_fw_minor_found < guc_fw->guc_fw_minor_wanted) {
 641                 DRM_ERROR("GuC firmware version %d.%d, required %d.%d\n",
 642                         guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found,
 643                         guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
 644                 err = -ENOEXEC;
 645                 goto fail;
 646         }
 647
 648         DRM_DEBUG_DRIVER("firmware version %d.%d OK (minimum %d.%d)\n",
 649                         guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found,
 650                         guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
 651
 652         mutex_lock(&dev->struct_mutex);
 653         obj = i915_gem_object_create_from_data(dev, fw->data, fw->size);
 654         mutex_unlock(&dev->struct_mutex);
 655         if (IS_ERR_OR_NULL(obj)) {
 656                 err = obj ? PTR_ERR(obj) : -ENOMEM;
 657                 goto fail;
 658         }
 659
 660         guc_fw->guc_fw_obj = obj;
 661         guc_fw->guc_fw_size = fw->size;
 662
 663         DRM_DEBUG_DRIVER("GuC fw fetch status SUCCESS, obj %p\n",
 664                         guc_fw->guc_fw_obj);
 665
 666         release_firmware(fw);
 667         guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_SUCCESS;
 668         return;
 669
 670 fail:
 671         DRM_DEBUG_DRIVER("GuC fw fetch status FAIL; err %d, fw %p, obj %p\n",
 672                 err, fw, guc_fw->guc_fw_obj);
 673         DRM_ERROR("Failed to fetch GuC firmware from %s (error %d)\n",
 674                   guc_fw->guc_fw_path, err);
 675
 676         mutex_lock(&dev->struct_mutex);
 677         obj = guc_fw->guc_fw_obj;
 678         if (obj)
 679                 i915_gem_object_put(obj);
 680         guc_fw->guc_fw_obj = NULL;
 681         mutex_unlock(&dev->struct_mutex);
 682
 683         release_firmware(fw);           /* OK even if fw is NULL */
 684         guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_FAIL;
 685 }
 686
 687 /**
 688  * intel_guc_init() - define parameters and fetch firmware
 689  * @dev:        drm device
 690  *
 691  * Called early during driver load, but after GEM is initialised.
 692  *
 693  * The firmware will be transferred to the GuC's memory later,
 694  * when intel_guc_setup() is called.
 695  */
 696 void intel_guc_init(struct drm_device *dev)
 697 {
 698         struct drm_i915_private *dev_priv = to_i915(dev);
 699         struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
 700         const char *fw_path;
 701
 702         /* A negative value means "use platform default" */
 703         if (i915.enable_guc_loading < 0)
 704                 i915.enable_guc_loading = HAS_GUC_UCODE(dev);
 705         if (i915.enable_guc_submission < 0)
 706                 i915.enable_guc_submission = HAS_GUC_SCHED(dev);
 707
 708         if (!HAS_GUC_UCODE(dev)) {
 709                 fw_path = NULL;
 710         } else if (IS_SKYLAKE(dev)) {
 711                 fw_path = I915_SKL_GUC_UCODE;
 712                 guc_fw->guc_fw_major_wanted = SKL_FW_MAJOR;
 713                 guc_fw->guc_fw_minor_wanted = SKL_FW_MINOR;
 714         } else if (IS_BROXTON(dev)) {
 715                 fw_path = I915_BXT_GUC_UCODE;
 716                 guc_fw->guc_fw_major_wanted = BXT_FW_MAJOR;
 717                 guc_fw->guc_fw_minor_wanted = BXT_FW_MINOR;
 718         } else if (IS_KABYLAKE(dev)) {
 719                 fw_path = I915_KBL_GUC_UCODE;
 720                 guc_fw->guc_fw_major_wanted = KBL_FW_MAJOR;
 721                 guc_fw->guc_fw_minor_wanted = KBL_FW_MINOR;
 722         } else {
 723                 fw_path = "";   /* unknown device */
 724         }
 725
 726         guc_fw->guc_dev = dev;
 727         guc_fw->guc_fw_path = fw_path;
 728         guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_NONE;
 729         guc_fw->guc_fw_load_status = GUC_FIRMWARE_NONE;
 730
 731         /* Early (and silent) return if GuC loading is disabled */
 732         if (!i915.enable_guc_loading)
 733                 return;
 734         if (fw_path == NULL)
 735                 return;
 736         if (*fw_path == '\0')
 737                 return;
 738
 739         guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_PENDING;
 740         DRM_DEBUG_DRIVER("GuC firmware pending, path %s\n", fw_path);
 741         guc_fw_fetch(dev, guc_fw);
 742         /* status must now be FAIL or SUCCESS */
 743 }
 744
 745 /**
 746  * intel_guc_fini() - clean up all allocated resources
 747  * @dev:        drm device
 748  */
 749 void intel_guc_fini(struct drm_device *dev)
 750 {
 751         struct drm_i915_private *dev_priv = to_i915(dev);
 752         struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
 753
 754         mutex_lock(&dev->struct_mutex);
 755         direct_interrupts_to_host(dev_priv);
 756         i915_guc_submission_disable(dev_priv);
 757         i915_guc_submission_fini(dev_priv);
 758
 759         if (guc_fw->guc_fw_obj)
 760                 i915_gem_object_put(guc_fw->guc_fw_obj);
 761         guc_fw->guc_fw_obj = NULL;
 762         mutex_unlock(&dev->struct_mutex);
 763
 764         guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_NONE;
 765 }