drivers/gpu/drm/i915/intel_pm.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <linux/cpufreq.h>
  29 #include "i915_drv.h"
  30 #include "intel_drv.h"
  31 #include "../../../platform/x86/intel_ips.h"
  32 #include <linux/module.h>
  33
  34 /**
  35  * DOC: RC6
  36  *
  37  * RC6 is a special power stage which allows the GPU to enter an very
  38  * low-voltage mode when idle, using down to 0V while at this stage.  This
  39  * stage is entered automatically when the GPU is idle when RC6 support is
  40  * enabled, and as soon as new workload arises GPU wakes up automatically as well.
  41  *
  42  * There are different RC6 modes available in Intel GPU, which differentiate
  43  * among each other with the latency required to enter and leave RC6 and
  44  * voltage consumed by the GPU in different states.
  45  *
  46  * The combination of the following flags define which states GPU is allowed
  47  * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
  48  * RC6pp is deepest RC6. Their support by hardware varies according to the
  49  * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
  50  * which brings the most power savings; deeper states save more power, but
  51  * require higher latency to switch to and wake up.
  52  */
  53 #define INTEL_RC6_ENABLE                        (1<<0)
  54 #define INTEL_RC6p_ENABLE                       (1<<1)
  55 #define INTEL_RC6pp_ENABLE                      (1<<2)
  56
  57 static void bxt_init_clock_gating(struct drm_device *dev)
  58 {
  59         struct drm_i915_private *dev_priv = dev->dev_private;
  60
  61         /* WaDisableSDEUnitClockGating:bxt */
  62         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
  63                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
  64
  65         /*
  66          * FIXME:
  67          * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
  68          */
  69         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
  70                    GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
  71
  72         /*
  73          * Wa: Backlight PWM may stop in the asserted state, causing backlight
  74          * to stay fully on.
  75          */
  76         if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
  77                 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
  78                            PWM1_GATING_DIS | PWM2_GATING_DIS);
  79 }
  80
  81 static void i915_pineview_get_mem_freq(struct drm_device *dev)
  82 {
  83         struct drm_i915_private *dev_priv = dev->dev_private;
  84         u32 tmp;
  85
  86         tmp = I915_READ(CLKCFG);
  87
  88         switch (tmp & CLKCFG_FSB_MASK) {
  89         case CLKCFG_FSB_533:
  90                 dev_priv->fsb_freq = 533; /* 133*4 */
  91                 break;
  92         case CLKCFG_FSB_800:
  93                 dev_priv->fsb_freq = 800; /* 200*4 */
  94                 break;
  95         case CLKCFG_FSB_667:
  96                 dev_priv->fsb_freq =  667; /* 167*4 */
  97                 break;
  98         case CLKCFG_FSB_400:
  99                 dev_priv->fsb_freq = 400; /* 100*4 */
 100                 break;
 101         }
 102
 103         switch (tmp & CLKCFG_MEM_MASK) {
 104         case CLKCFG_MEM_533:
 105                 dev_priv->mem_freq = 533;
 106                 break;
 107         case CLKCFG_MEM_667:
 108                 dev_priv->mem_freq = 667;
 109                 break;
 110         case CLKCFG_MEM_800:
 111                 dev_priv->mem_freq = 800;
 112                 break;
 113         }
 114
 115         /* detect pineview DDR3 setting */
 116         tmp = I915_READ(CSHRDDR3CTL);
 117         dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
 118 }
 119
 120 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
 121 {
 122         struct drm_i915_private *dev_priv = dev->dev_private;
 123         u16 ddrpll, csipll;
 124
 125         ddrpll = I915_READ16(DDRMPLL1);
 126         csipll = I915_READ16(CSIPLL0);
 127
 128         switch (ddrpll & 0xff) {
 129         case 0xc:
 130                 dev_priv->mem_freq = 800;
 131                 break;
 132         case 0x10:
 133                 dev_priv->mem_freq = 1066;
 134                 break;
 135         case 0x14:
 136                 dev_priv->mem_freq = 1333;
 137                 break;
 138         case 0x18:
 139                 dev_priv->mem_freq = 1600;
 140                 break;
 141         default:
 142                 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
 143                                  ddrpll & 0xff);
 144                 dev_priv->mem_freq = 0;
 145                 break;
 146         }
 147
 148         dev_priv->ips.r_t = dev_priv->mem_freq;
 149
 150         switch (csipll & 0x3ff) {
 151         case 0x00c:
 152                 dev_priv->fsb_freq = 3200;
 153                 break;
 154         case 0x00e:
 155                 dev_priv->fsb_freq = 3733;
 156                 break;
 157         case 0x010:
 158                 dev_priv->fsb_freq = 4266;
 159                 break;
 160         case 0x012:
 161                 dev_priv->fsb_freq = 4800;
 162                 break;
 163         case 0x014:
 164                 dev_priv->fsb_freq = 5333;
 165                 break;
 166         case 0x016:
 167                 dev_priv->fsb_freq = 5866;
 168                 break;
 169         case 0x018:
 170                 dev_priv->fsb_freq = 6400;
 171                 break;
 172         default:
 173                 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
 174                                  csipll & 0x3ff);
 175                 dev_priv->fsb_freq = 0;
 176                 break;
 177         }
 178
 179         if (dev_priv->fsb_freq == 3200) {
 180                 dev_priv->ips.c_m = 0;
 181         } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
 182                 dev_priv->ips.c_m = 1;
 183         } else {
 184                 dev_priv->ips.c_m = 2;
 185         }
 186 }
 187
 188 static const struct cxsr_latency cxsr_latency_table[] = {
 189         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
 190         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
 191         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
 192         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
 193         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
 194
 195         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
 196         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
 197         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
 198         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
 199         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
 200
 201         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
 202         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
 203         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
 204         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
 205         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
 206
 207         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
 208         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
 209         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
 210         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
 211         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
 212
 213         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
 214         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
 215         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
 216         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
 217         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
 218
 219         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
 220         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
 221         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
 222         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
 223         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
 224 };
 225
 226 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
 227                                                          int is_ddr3,
 228                                                          int fsb,
 229                                                          int mem)
 230 {
 231         const struct cxsr_latency *latency;
 232         int i;
 233
 234         if (fsb == 0 || mem == 0)
 235                 return NULL;
 236
 237         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
 238                 latency = &cxsr_latency_table[i];
 239                 if (is_desktop == latency->is_desktop &&
 240                     is_ddr3 == latency->is_ddr3 &&
 241                     fsb == latency->fsb_freq && mem == latency->mem_freq)
 242                         return latency;
 243         }
 244
 245         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 246
 247         return NULL;
 248 }
 249
 250 static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
 251 {
 252         u32 val;
 253
 254         mutex_lock(&dev_priv->rps.hw_lock);
 255
 256         val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
 257         if (enable)
 258                 val &= ~FORCE_DDR_HIGH_FREQ;
 259         else
 260                 val |= FORCE_DDR_HIGH_FREQ;
 261         val &= ~FORCE_DDR_LOW_FREQ;
 262         val |= FORCE_DDR_FREQ_REQ_ACK;
 263         vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
 264
 265         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
 266                       FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
 267                 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
 268
 269         mutex_unlock(&dev_priv->rps.hw_lock);
 270 }
 271
 272 static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
 273 {
 274         u32 val;
 275
 276         mutex_lock(&dev_priv->rps.hw_lock);
 277
 278         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
 279         if (enable)
 280                 val |= DSP_MAXFIFO_PM5_ENABLE;
 281         else
 282                 val &= ~DSP_MAXFIFO_PM5_ENABLE;
 283         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
 284
 285         mutex_unlock(&dev_priv->rps.hw_lock);
 286 }
 287
 288 #define FW_WM(value, plane) \
 289         (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
 290
 291 void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
 292 {
 293         struct drm_device *dev = dev_priv->dev;
 294         u32 val;
 295
 296         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 297                 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
 298                 POSTING_READ(FW_BLC_SELF_VLV);
 299                 dev_priv->wm.vlv.cxsr = enable;
 300         } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
 301                 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
 302                 POSTING_READ(FW_BLC_SELF);
 303         } else if (IS_PINEVIEW(dev)) {
 304                 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
 305                 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
 306                 I915_WRITE(DSPFW3, val);
 307                 POSTING_READ(DSPFW3);
 308         } else if (IS_I945G(dev) || IS_I945GM(dev)) {
 309                 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
 310                                _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
 311                 I915_WRITE(FW_BLC_SELF, val);
 312                 POSTING_READ(FW_BLC_SELF);
 313         } else if (IS_I915GM(dev)) {
 314                 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
 315                                _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
 316                 I915_WRITE(INSTPM, val);
 317                 POSTING_READ(INSTPM);
 318         } else {
 319                 return;
 320         }
 321
 322         DRM_DEBUG_KMS("memory self-refresh is %s\n",
 323                       enable ? "enabled" : "disabled");
 324 }
 325
 326
 327 /*
 328  * Latency for FIFO fetches is dependent on several factors:
 329  *   - memory configuration (speed, channels)
 330  *   - chipset
 331  *   - current MCH state
 332  * It can be fairly high in some situations, so here we assume a fairly
 333  * pessimal value.  It's a tradeoff between extra memory fetches (if we
 334  * set this value too high, the FIFO will fetch frequently to stay full)
 335  * and power consumption (set it too low to save power and we might see
 336  * FIFO underruns and display "flicker").
 337  *
 338  * A value of 5us seems to be a good balance; safe for very low end
 339  * platforms but not overly aggressive on lower latency configs.
 340  */
 341 static const int pessimal_latency_ns = 5000;
 342
 343 #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
 344         ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
 345
 346 static int vlv_get_fifo_size(struct drm_device *dev,
 347                               enum pipe pipe, int plane)
 348 {
 349         struct drm_i915_private *dev_priv = dev->dev_private;
 350         int sprite0_start, sprite1_start, size;
 351
 352         switch (pipe) {
 353                 uint32_t dsparb, dsparb2, dsparb3;
 354         case PIPE_A:
 355                 dsparb = I915_READ(DSPARB);
 356                 dsparb2 = I915_READ(DSPARB2);
 357                 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
 358                 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
 359                 break;
 360         case PIPE_B:
 361                 dsparb = I915_READ(DSPARB);
 362                 dsparb2 = I915_READ(DSPARB2);
 363                 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
 364                 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
 365                 break;
 366         case PIPE_C:
 367                 dsparb2 = I915_READ(DSPARB2);
 368                 dsparb3 = I915_READ(DSPARB3);
 369                 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
 370                 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
 371                 break;
 372         default:
 373                 return 0;
 374         }
 375
 376         switch (plane) {
 377         case 0:
 378                 size = sprite0_start;
 379                 break;
 380         case 1:
 381                 size = sprite1_start - sprite0_start;
 382                 break;
 383         case 2:
 384                 size = 512 - 1 - sprite1_start;
 385                 break;
 386         default:
 387                 return 0;
 388         }
 389
 390         DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
 391                       pipe_name(pipe), plane == 0 ? "primary" : "sprite",
 392                       plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
 393                       size);
 394
 395         return size;
 396 }
 397
 398 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
 399 {
 400         struct drm_i915_private *dev_priv = dev->dev_private;
 401         uint32_t dsparb = I915_READ(DSPARB);
 402         int size;
 403
 404         size = dsparb & 0x7f;
 405         if (plane)
 406                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
 407
 408         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 409                       plane ? "B" : "A", size);
 410
 411         return size;
 412 }
 413
 414 static int i830_get_fifo_size(struct drm_device *dev, int plane)
 415 {
 416         struct drm_i915_private *dev_priv = dev->dev_private;
 417         uint32_t dsparb = I915_READ(DSPARB);
 418         int size;
 419
 420         size = dsparb & 0x1ff;
 421         if (plane)
 422                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
 423         size >>= 1; /* Convert to cachelines */
 424
 425         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 426                       plane ? "B" : "A", size);
 427
 428         return size;
 429 }
 430
 431 static int i845_get_fifo_size(struct drm_device *dev, int plane)
 432 {
 433         struct drm_i915_private *dev_priv = dev->dev_private;
 434         uint32_t dsparb = I915_READ(DSPARB);
 435         int size;
 436
 437         size = dsparb & 0x7f;
 438         size >>= 2; /* Convert to cachelines */
 439
 440         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 441                       plane ? "B" : "A",
 442                       size);
 443
 444         return size;
 445 }
 446
 447 /* Pineview has different values for various configs */
 448 static const struct intel_watermark_params pineview_display_wm = {
 449         .fifo_size = PINEVIEW_DISPLAY_FIFO,
 450         .max_wm = PINEVIEW_MAX_WM,
 451         .default_wm = PINEVIEW_DFT_WM,
 452         .guard_size = PINEVIEW_GUARD_WM,
 453         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 454 };
 455 static const struct intel_watermark_params pineview_display_hplloff_wm = {
 456         .fifo_size = PINEVIEW_DISPLAY_FIFO,
 457         .max_wm = PINEVIEW_MAX_WM,
 458         .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
 459         .guard_size = PINEVIEW_GUARD_WM,
 460         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 461 };
 462 static const struct intel_watermark_params pineview_cursor_wm = {
 463         .fifo_size = PINEVIEW_CURSOR_FIFO,
 464         .max_wm = PINEVIEW_CURSOR_MAX_WM,
 465         .default_wm = PINEVIEW_CURSOR_DFT_WM,
 466         .guard_size = PINEVIEW_CURSOR_GUARD_WM,
 467         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 468 };
 469 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
 470         .fifo_size = PINEVIEW_CURSOR_FIFO,
 471         .max_wm = PINEVIEW_CURSOR_MAX_WM,
 472         .default_wm = PINEVIEW_CURSOR_DFT_WM,
 473         .guard_size = PINEVIEW_CURSOR_GUARD_WM,
 474         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 475 };
 476 static const struct intel_watermark_params g4x_wm_info = {
 477         .fifo_size = G4X_FIFO_SIZE,
 478         .max_wm = G4X_MAX_WM,
 479         .default_wm = G4X_MAX_WM,
 480         .guard_size = 2,
 481         .cacheline_size = G4X_FIFO_LINE_SIZE,
 482 };
 483 static const struct intel_watermark_params g4x_cursor_wm_info = {
 484         .fifo_size = I965_CURSOR_FIFO,
 485         .max_wm = I965_CURSOR_MAX_WM,
 486         .default_wm = I965_CURSOR_DFT_WM,
 487         .guard_size = 2,
 488         .cacheline_size = G4X_FIFO_LINE_SIZE,
 489 };
 490 static const struct intel_watermark_params i965_cursor_wm_info = {
 491         .fifo_size = I965_CURSOR_FIFO,
 492         .max_wm = I965_CURSOR_MAX_WM,
 493         .default_wm = I965_CURSOR_DFT_WM,
 494         .guard_size = 2,
 495         .cacheline_size = I915_FIFO_LINE_SIZE,
 496 };
 497 static const struct intel_watermark_params i945_wm_info = {
 498         .fifo_size = I945_FIFO_SIZE,
 499         .max_wm = I915_MAX_WM,
 500         .default_wm = 1,
 501         .guard_size = 2,
 502         .cacheline_size = I915_FIFO_LINE_SIZE,
 503 };
 504 static const struct intel_watermark_params i915_wm_info = {
 505         .fifo_size = I915_FIFO_SIZE,
 506         .max_wm = I915_MAX_WM,
 507         .default_wm = 1,
 508         .guard_size = 2,
 509         .cacheline_size = I915_FIFO_LINE_SIZE,
 510 };
 511 static const struct intel_watermark_params i830_a_wm_info = {
 512         .fifo_size = I855GM_FIFO_SIZE,
 513         .max_wm = I915_MAX_WM,
 514         .default_wm = 1,
 515         .guard_size = 2,
 516         .cacheline_size = I830_FIFO_LINE_SIZE,
 517 };
 518 static const struct intel_watermark_params i830_bc_wm_info = {
 519         .fifo_size = I855GM_FIFO_SIZE,
 520         .max_wm = I915_MAX_WM/2,
 521         .default_wm = 1,
 522         .guard_size = 2,
 523         .cacheline_size = I830_FIFO_LINE_SIZE,
 524 };
 525 static const struct intel_watermark_params i845_wm_info = {
 526         .fifo_size = I830_FIFO_SIZE,
 527         .max_wm = I915_MAX_WM,
 528         .default_wm = 1,
 529         .guard_size = 2,
 530         .cacheline_size = I830_FIFO_LINE_SIZE,
 531 };
 532
 533 /**
 534  * intel_calculate_wm - calculate watermark level
 535  * @clock_in_khz: pixel clock
 536  * @wm: chip FIFO params
 537  * @cpp: bytes per pixel
 538  * @latency_ns: memory latency for the platform
 539  *
 540  * Calculate the watermark level (the level at which the display plane will
 541  * start fetching from memory again).  Each chip has a different display
 542  * FIFO size and allocation, so the caller needs to figure that out and pass
 543  * in the correct intel_watermark_params structure.
 544  *
 545  * As the pixel clock runs, the FIFO will be drained at a rate that depends
 546  * on the pixel size.  When it reaches the watermark level, it'll start
 547  * fetching FIFO line sized based chunks from memory until the FIFO fills
 548  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
 549  * will occur, and a display engine hang could result.
 550  */
 551 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
 552                                         const struct intel_watermark_params *wm,
 553                                         int fifo_size, int cpp,
 554                                         unsigned long latency_ns)
 555 {
 556         long entries_required, wm_size;
 557
 558         /*
 559          * Note: we need to make sure we don't overflow for various clock &
 560          * latency values.
 561          * clocks go from a few thousand to several hundred thousand.
 562          * latency is usually a few thousand
 563          */
 564         entries_required = ((clock_in_khz / 1000) * cpp * latency_ns) /
 565                 1000;
 566         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
 567
 568         DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
 569
 570         wm_size = fifo_size - (entries_required + wm->guard_size);
 571
 572         DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
 573
 574         /* Don't promote wm_size to unsigned... */
 575         if (wm_size > (long)wm->max_wm)
 576                 wm_size = wm->max_wm;
 577         if (wm_size <= 0)
 578                 wm_size = wm->default_wm;
 579
 580         /*
 581          * Bspec seems to indicate that the value shouldn't be lower than
 582          * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
 583          * Lets go for 8 which is the burst size since certain platforms
 584          * already use a hardcoded 8 (which is what the spec says should be
 585          * done).
 586          */
 587         if (wm_size <= 8)
 588                 wm_size = 8;
 589
 590         return wm_size;
 591 }
 592
 593 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
 594 {
 595         struct drm_crtc *crtc, *enabled = NULL;
 596
 597         for_each_crtc(dev, crtc) {
 598                 if (intel_crtc_active(crtc)) {
 599                         if (enabled)
 600                                 return NULL;
 601                         enabled = crtc;
 602                 }
 603         }
 604
 605         return enabled;
 606 }
 607
 608 static void pineview_update_wm(struct drm_crtc *unused_crtc)
 609 {
 610         struct drm_device *dev = unused_crtc->dev;
 611         struct drm_i915_private *dev_priv = dev->dev_private;
 612         struct drm_crtc *crtc;
 613         const struct cxsr_latency *latency;
 614         u32 reg;
 615         unsigned long wm;
 616
 617         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
 618                                          dev_priv->fsb_freq, dev_priv->mem_freq);
 619         if (!latency) {
 620                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 621                 intel_set_memory_cxsr(dev_priv, false);
 622                 return;
 623         }
 624
 625         crtc = single_enabled_crtc(dev);
 626         if (crtc) {
 627                 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
 628                 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
 629                 int clock = adjusted_mode->crtc_clock;
 630
 631                 /* Display SR */
 632                 wm = intel_calculate_wm(clock, &pineview_display_wm,
 633                                         pineview_display_wm.fifo_size,
 634                                         cpp, latency->display_sr);
 635                 reg = I915_READ(DSPFW1);
 636                 reg &= ~DSPFW_SR_MASK;
 637                 reg |= FW_WM(wm, SR);
 638                 I915_WRITE(DSPFW1, reg);
 639                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
 640
 641                 /* cursor SR */
 642                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
 643                                         pineview_display_wm.fifo_size,
 644                                         cpp, latency->cursor_sr);
 645                 reg = I915_READ(DSPFW3);
 646                 reg &= ~DSPFW_CURSOR_SR_MASK;
 647                 reg |= FW_WM(wm, CURSOR_SR);
 648                 I915_WRITE(DSPFW3, reg);
 649
 650                 /* Display HPLL off SR */
 651                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
 652                                         pineview_display_hplloff_wm.fifo_size,
 653                                         cpp, latency->display_hpll_disable);
 654                 reg = I915_READ(DSPFW3);
 655                 reg &= ~DSPFW_HPLL_SR_MASK;
 656                 reg |= FW_WM(wm, HPLL_SR);
 657                 I915_WRITE(DSPFW3, reg);
 658
 659                 /* cursor HPLL off SR */
 660                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
 661                                         pineview_display_hplloff_wm.fifo_size,
 662                                         cpp, latency->cursor_hpll_disable);
 663                 reg = I915_READ(DSPFW3);
 664                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
 665                 reg |= FW_WM(wm, HPLL_CURSOR);
 666                 I915_WRITE(DSPFW3, reg);
 667                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
 668
 669                 intel_set_memory_cxsr(dev_priv, true);
 670         } else {
 671                 intel_set_memory_cxsr(dev_priv, false);
 672         }
 673 }
 674
 675 static bool g4x_compute_wm0(struct drm_device *dev,
 676                             int plane,
 677                             const struct intel_watermark_params *display,
 678                             int display_latency_ns,
 679                             const struct intel_watermark_params *cursor,
 680                             int cursor_latency_ns,
 681                             int *plane_wm,
 682                             int *cursor_wm)
 683 {
 684         struct drm_crtc *crtc;
 685         const struct drm_display_mode *adjusted_mode;
 686         int htotal, hdisplay, clock, cpp;
 687         int line_time_us, line_count;
 688         int entries, tlb_miss;
 689
 690         crtc = intel_get_crtc_for_plane(dev, plane);
 691         if (!intel_crtc_active(crtc)) {
 692                 *cursor_wm = cursor->guard_size;
 693                 *plane_wm = display->guard_size;
 694                 return false;
 695         }
 696
 697         adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
 698         clock = adjusted_mode->crtc_clock;
 699         htotal = adjusted_mode->crtc_htotal;
 700         hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
 701         cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
 702
 703         /* Use the small buffer method to calculate plane watermark */
 704         entries = ((clock * cpp / 1000) * display_latency_ns) / 1000;
 705         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
 706         if (tlb_miss > 0)
 707                 entries += tlb_miss;
 708         entries = DIV_ROUND_UP(entries, display->cacheline_size);
 709         *plane_wm = entries + display->guard_size;
 710         if (*plane_wm > (int)display->max_wm)
 711                 *plane_wm = display->max_wm;
 712
 713         /* Use the large buffer method to calculate cursor watermark */
 714         line_time_us = max(htotal * 1000 / clock, 1);
 715         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
 716         entries = line_count * crtc->cursor->state->crtc_w * cpp;
 717         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
 718         if (tlb_miss > 0)
 719                 entries += tlb_miss;
 720         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
 721         *cursor_wm = entries + cursor->guard_size;
 722         if (*cursor_wm > (int)cursor->max_wm)
 723                 *cursor_wm = (int)cursor->max_wm;
 724
 725         return true;
 726 }
 727
 728 /*
 729  * Check the wm result.
 730  *
 731  * If any calculated watermark values is larger than the maximum value that
 732  * can be programmed into the associated watermark register, that watermark
 733  * must be disabled.
 734  */
 735 static bool g4x_check_srwm(struct drm_device *dev,
 736                            int display_wm, int cursor_wm,
 737                            const struct intel_watermark_params *display,
 738                            const struct intel_watermark_params *cursor)
 739 {
 740         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
 741                       display_wm, cursor_wm);
 742
 743         if (display_wm > display->max_wm) {
 744                 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
 745                               display_wm, display->max_wm);
 746                 return false;
 747         }
 748
 749         if (cursor_wm > cursor->max_wm) {
 750                 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
 751                               cursor_wm, cursor->max_wm);
 752                 return false;
 753         }
 754
 755         if (!(display_wm || cursor_wm)) {
 756                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
 757                 return false;
 758         }
 759
 760         return true;
 761 }
 762
 763 static bool g4x_compute_srwm(struct drm_device *dev,
 764                              int plane,
 765                              int latency_ns,
 766                              const struct intel_watermark_params *display,
 767                              const struct intel_watermark_params *cursor,
 768                              int *display_wm, int *cursor_wm)
 769 {
 770         struct drm_crtc *crtc;
 771         const struct drm_display_mode *adjusted_mode;
 772         int hdisplay, htotal, cpp, clock;
 773         unsigned long line_time_us;
 774         int line_count, line_size;
 775         int small, large;
 776         int entries;
 777
 778         if (!latency_ns) {
 779                 *display_wm = *cursor_wm = 0;
 780                 return false;
 781         }
 782
 783         crtc = intel_get_crtc_for_plane(dev, plane);
 784         adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
 785         clock = adjusted_mode->crtc_clock;
 786         htotal = adjusted_mode->crtc_htotal;
 787         hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
 788         cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
 789
 790         line_time_us = max(htotal * 1000 / clock, 1);
 791         line_count = (latency_ns / line_time_us + 1000) / 1000;
 792         line_size = hdisplay * cpp;
 793
 794         /* Use the minimum of the small and large buffer method for primary */
 795         small = ((clock * cpp / 1000) * latency_ns) / 1000;
 796         large = line_count * line_size;
 797
 798         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
 799         *display_wm = entries + display->guard_size;
 800
 801         /* calculate the self-refresh watermark for display cursor */
 802         entries = line_count * cpp * crtc->cursor->state->crtc_w;
 803         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
 804         *cursor_wm = entries + cursor->guard_size;
 805
 806         return g4x_check_srwm(dev,
 807                               *display_wm, *cursor_wm,
 808                               display, cursor);
 809 }
 810
 811 #define FW_WM_VLV(value, plane) \
 812         (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
 813
 814 static void vlv_write_wm_values(struct intel_crtc *crtc,
 815                                 const struct vlv_wm_values *wm)
 816 {
 817         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 818         enum pipe pipe = crtc->pipe;
 819
 820         I915_WRITE(VLV_DDL(pipe),
 821                    (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
 822                    (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
 823                    (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
 824                    (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
 825
 826         I915_WRITE(DSPFW1,
 827                    FW_WM(wm->sr.plane, SR) |
 828                    FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
 829                    FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
 830                    FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
 831         I915_WRITE(DSPFW2,
 832                    FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
 833                    FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
 834                    FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
 835         I915_WRITE(DSPFW3,
 836                    FW_WM(wm->sr.cursor, CURSOR_SR));
 837
 838         if (IS_CHERRYVIEW(dev_priv)) {
 839                 I915_WRITE(DSPFW7_CHV,
 840                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
 841                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
 842                 I915_WRITE(DSPFW8_CHV,
 843                            FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
 844                            FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
 845                 I915_WRITE(DSPFW9_CHV,
 846                            FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
 847                            FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
 848                 I915_WRITE(DSPHOWM,
 849                            FW_WM(wm->sr.plane >> 9, SR_HI) |
 850                            FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
 851                            FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
 852                            FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
 853                            FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
 854                            FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
 855                            FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
 856                            FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
 857                            FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
 858                            FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
 859         } else {
 860                 I915_WRITE(DSPFW7,
 861                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
 862                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
 863                 I915_WRITE(DSPHOWM,
 864                            FW_WM(wm->sr.plane >> 9, SR_HI) |
 865                            FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
 866                            FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
 867                            FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
 868                            FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
 869                            FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
 870                            FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
 871         }
 872
 873         /* zero (unused) WM1 watermarks */
 874         I915_WRITE(DSPFW4, 0);
 875         I915_WRITE(DSPFW5, 0);
 876         I915_WRITE(DSPFW6, 0);
 877         I915_WRITE(DSPHOWM1, 0);
 878
 879         POSTING_READ(DSPFW1);
 880 }
 881
 882 #undef FW_WM_VLV
 883
 884 enum vlv_wm_level {
 885         VLV_WM_LEVEL_PM2,
 886         VLV_WM_LEVEL_PM5,
 887         VLV_WM_LEVEL_DDR_DVFS,
 888 };
 889
 890 /* latency must be in 0.1us units. */
 891 static unsigned int vlv_wm_method2(unsigned int pixel_rate,
 892                                    unsigned int pipe_htotal,
 893                                    unsigned int horiz_pixels,
 894                                    unsigned int cpp,
 895                                    unsigned int latency)
 896 {
 897         unsigned int ret;
 898
 899         ret = (latency * pixel_rate) / (pipe_htotal * 10000);
 900         ret = (ret + 1) * horiz_pixels * cpp;
 901         ret = DIV_ROUND_UP(ret, 64);
 902
 903         return ret;
 904 }
 905
 906 static void vlv_setup_wm_latency(struct drm_device *dev)
 907 {
 908         struct drm_i915_private *dev_priv = dev->dev_private;
 909
 910         /* all latencies in usec */
 911         dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
 912
 913         dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
 914
 915         if (IS_CHERRYVIEW(dev_priv)) {
 916                 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
 917                 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
 918
 919                 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
 920         }
 921 }
 922
 923 static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
 924                                      struct intel_crtc *crtc,
 925                                      const struct intel_plane_state *state,
 926                                      int level)
 927 {
 928         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 929         int clock, htotal, cpp, width, wm;
 930
 931         if (dev_priv->wm.pri_latency[level] == 0)
 932                 return USHRT_MAX;
 933
 934         if (!state->visible)
 935                 return 0;
 936
 937         cpp = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
 938         clock = crtc->config->base.adjusted_mode.crtc_clock;
 939         htotal = crtc->config->base.adjusted_mode.crtc_htotal;
 940         width = crtc->config->pipe_src_w;
 941         if (WARN_ON(htotal == 0))
 942                 htotal = 1;
 943
 944         if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
 945                 /*
 946                  * FIXME the formula gives values that are
 947                  * too big for the cursor FIFO, and hence we
 948                  * would never be able to use cursors. For
 949                  * now just hardcode the watermark.
 950                  */
 951                 wm = 63;
 952         } else {
 953                 wm = vlv_wm_method2(clock, htotal, width, cpp,
 954                                     dev_priv->wm.pri_latency[level] * 10);
 955         }
 956
 957         return min_t(int, wm, USHRT_MAX);
 958 }
 959
 960 static void vlv_compute_fifo(struct intel_crtc *crtc)
 961 {
 962         struct drm_device *dev = crtc->base.dev;
 963         struct vlv_wm_state *wm_state = &crtc->wm_state;
 964         struct intel_plane *plane;
 965         unsigned int total_rate = 0;
 966         const int fifo_size = 512 - 1;
 967         int fifo_extra, fifo_left = fifo_size;
 968
 969         for_each_intel_plane_on_crtc(dev, crtc, plane) {
 970                 struct intel_plane_state *state =
 971                         to_intel_plane_state(plane->base.state);
 972
 973                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
 974                         continue;
 975
 976                 if (state->visible) {
 977                         wm_state->num_active_planes++;
 978                         total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0);
 979                 }
 980         }
 981
 982         for_each_intel_plane_on_crtc(dev, crtc, plane) {
 983                 struct intel_plane_state *state =
 984                         to_intel_plane_state(plane->base.state);
 985                 unsigned int rate;
 986
 987                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
 988                         plane->wm.fifo_size = 63;
 989                         continue;
 990                 }
 991
 992                 if (!state->visible) {
 993                         plane->wm.fifo_size = 0;
 994                         continue;
 995                 }
 996
 997                 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
 998                 plane->wm.fifo_size = fifo_size * rate / total_rate;
 999                 fifo_left -= plane->wm.fifo_size;
1000         }
1001
1002         fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1003
1004         /* spread the remainder evenly */
1005         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1006                 int plane_extra;
1007
1008                 if (fifo_left == 0)
1009                         break;
1010
1011                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1012                         continue;
1013
1014                 /* give it all to the first plane if none are active */
1015                 if (plane->wm.fifo_size == 0 &&
1016                     wm_state->num_active_planes)
1017                         continue;
1018
1019                 plane_extra = min(fifo_extra, fifo_left);
1020                 plane->wm.fifo_size += plane_extra;
1021                 fifo_left -= plane_extra;
1022         }
1023
1024         WARN_ON(fifo_left != 0);
1025 }
1026
1027 static void vlv_invert_wms(struct intel_crtc *crtc)
1028 {
1029         struct vlv_wm_state *wm_state = &crtc->wm_state;
1030         int level;
1031
1032         for (level = 0; level < wm_state->num_levels; level++) {
1033                 struct drm_device *dev = crtc->base.dev;
1034                 const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1035                 struct intel_plane *plane;
1036
1037                 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
1038                 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor;
1039
1040                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1041                         switch (plane->base.type) {
1042                                 int sprite;
1043                         case DRM_PLANE_TYPE_CURSOR:
1044                                 wm_state->wm[level].cursor = plane->wm.fifo_size -
1045                                         wm_state->wm[level].cursor;
1046                                 break;
1047                         case DRM_PLANE_TYPE_PRIMARY:
1048                                 wm_state->wm[level].primary = plane->wm.fifo_size -
1049                                         wm_state->wm[level].primary;
1050                                 break;
1051                         case DRM_PLANE_TYPE_OVERLAY:
1052                                 sprite = plane->plane;
1053                                 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size -
1054                                         wm_state->wm[level].sprite[sprite];
1055                                 break;
1056                         }
1057                 }
1058         }
1059 }
1060
1061 static void vlv_compute_wm(struct intel_crtc *crtc)
1062 {
1063         struct drm_device *dev = crtc->base.dev;
1064         struct vlv_wm_state *wm_state = &crtc->wm_state;
1065         struct intel_plane *plane;
1066         int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1067         int level;
1068
1069         memset(wm_state, 0, sizeof(*wm_state));
1070
1071         wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
1072         wm_state->num_levels = to_i915(dev)->wm.max_level + 1;
1073
1074         wm_state->num_active_planes = 0;
1075
1076         vlv_compute_fifo(crtc);
1077
1078         if (wm_state->num_active_planes != 1)
1079                 wm_state->cxsr = false;
1080
1081         if (wm_state->cxsr) {
1082                 for (level = 0; level < wm_state->num_levels; level++) {
1083                         wm_state->sr[level].plane = sr_fifo_size;
1084                         wm_state->sr[level].cursor = 63;
1085                 }
1086         }
1087
1088         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1089                 struct intel_plane_state *state =
1090                         to_intel_plane_state(plane->base.state);
1091
1092                 if (!state->visible)
1093                         continue;
1094
1095                 /* normal watermarks */
1096                 for (level = 0; level < wm_state->num_levels; level++) {
1097                         int wm = vlv_compute_wm_level(plane, crtc, state, level);
1098                         int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511;
1099
1100                         /* hack */
1101                         if (WARN_ON(level == 0 && wm > max_wm))
1102                                 wm = max_wm;
1103
1104                         if (wm > plane->wm.fifo_size)
1105                                 break;
1106
1107                         switch (plane->base.type) {
1108                                 int sprite;
1109                         case DRM_PLANE_TYPE_CURSOR:
1110                                 wm_state->wm[level].cursor = wm;
1111                                 break;
1112                         case DRM_PLANE_TYPE_PRIMARY:
1113                                 wm_state->wm[level].primary = wm;
1114                                 break;
1115                         case DRM_PLANE_TYPE_OVERLAY:
1116                                 sprite = plane->plane;
1117                                 wm_state->wm[level].sprite[sprite] = wm;
1118                                 break;
1119                         }
1120                 }
1121
1122                 wm_state->num_levels = level;
1123
1124                 if (!wm_state->cxsr)
1125                         continue;
1126
1127                 /* maxfifo watermarks */
1128                 switch (plane->base.type) {
1129                         int sprite, level;
1130                 case DRM_PLANE_TYPE_CURSOR:
1131                         for (level = 0; level < wm_state->num_levels; level++)
1132                                 wm_state->sr[level].cursor =
1133                                         wm_state->wm[level].cursor;
1134                         break;
1135                 case DRM_PLANE_TYPE_PRIMARY:
1136                         for (level = 0; level < wm_state->num_levels; level++)
1137                                 wm_state->sr[level].plane =
1138                                         min(wm_state->sr[level].plane,
1139                                             wm_state->wm[level].primary);
1140                         break;
1141                 case DRM_PLANE_TYPE_OVERLAY:
1142                         sprite = plane->plane;
1143                         for (level = 0; level < wm_state->num_levels; level++)
1144                                 wm_state->sr[level].plane =
1145                                         min(wm_state->sr[level].plane,
1146                                             wm_state->wm[level].sprite[sprite]);
1147                         break;
1148                 }
1149         }
1150
1151         /* clear any (partially) filled invalid levels */
1152         for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) {
1153                 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1154                 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1155         }
1156
1157         vlv_invert_wms(crtc);
1158 }
1159
1160 #define VLV_FIFO(plane, value) \
1161         (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1162
1163 static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1164 {
1165         struct drm_device *dev = crtc->base.dev;
1166         struct drm_i915_private *dev_priv = to_i915(dev);
1167         struct intel_plane *plane;
1168         int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1169
1170         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1171                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1172                         WARN_ON(plane->wm.fifo_size != 63);
1173                         continue;
1174                 }
1175
1176                 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
1177                         sprite0_start = plane->wm.fifo_size;
1178                 else if (plane->plane == 0)
1179                         sprite1_start = sprite0_start + plane->wm.fifo_size;
1180                 else
1181                         fifo_size = sprite1_start + plane->wm.fifo_size;
1182         }
1183
1184         WARN_ON(fifo_size != 512 - 1);
1185
1186         DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1187                       pipe_name(crtc->pipe), sprite0_start,
1188                       sprite1_start, fifo_size);
1189
1190         switch (crtc->pipe) {
1191                 uint32_t dsparb, dsparb2, dsparb3;
1192         case PIPE_A:
1193                 dsparb = I915_READ(DSPARB);
1194                 dsparb2 = I915_READ(DSPARB2);
1195
1196                 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1197                             VLV_FIFO(SPRITEB, 0xff));
1198                 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1199                            VLV_FIFO(SPRITEB, sprite1_start));
1200
1201                 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1202                              VLV_FIFO(SPRITEB_HI, 0x1));
1203                 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1204                            VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1205
1206                 I915_WRITE(DSPARB, dsparb);
1207                 I915_WRITE(DSPARB2, dsparb2);
1208                 break;
1209         case PIPE_B:
1210                 dsparb = I915_READ(DSPARB);
1211                 dsparb2 = I915_READ(DSPARB2);
1212
1213                 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1214                             VLV_FIFO(SPRITED, 0xff));
1215                 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1216                            VLV_FIFO(SPRITED, sprite1_start));
1217
1218                 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1219                              VLV_FIFO(SPRITED_HI, 0xff));
1220                 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1221                            VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1222
1223                 I915_WRITE(DSPARB, dsparb);
1224                 I915_WRITE(DSPARB2, dsparb2);
1225                 break;
1226         case PIPE_C:
1227                 dsparb3 = I915_READ(DSPARB3);
1228                 dsparb2 = I915_READ(DSPARB2);
1229
1230                 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1231                              VLV_FIFO(SPRITEF, 0xff));
1232                 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1233                             VLV_FIFO(SPRITEF, sprite1_start));
1234
1235                 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1236                              VLV_FIFO(SPRITEF_HI, 0xff));
1237                 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1238                            VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1239
1240                 I915_WRITE(DSPARB3, dsparb3);
1241                 I915_WRITE(DSPARB2, dsparb2);
1242                 break;
1243         default:
1244                 break;
1245         }
1246 }
1247
1248 #undef VLV_FIFO
1249
1250 static void vlv_merge_wm(struct drm_device *dev,
1251                          struct vlv_wm_values *wm)
1252 {
1253         struct intel_crtc *crtc;
1254         int num_active_crtcs = 0;
1255
1256         wm->level = to_i915(dev)->wm.max_level;
1257         wm->cxsr = true;
1258
1259         for_each_intel_crtc(dev, crtc) {
1260                 const struct vlv_wm_state *wm_state = &crtc->wm_state;
1261
1262                 if (!crtc->active)
1263                         continue;
1264
1265                 if (!wm_state->cxsr)
1266                         wm->cxsr = false;
1267
1268                 num_active_crtcs++;
1269                 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1270         }
1271
1272         if (num_active_crtcs != 1)
1273                 wm->cxsr = false;
1274
1275         if (num_active_crtcs > 1)
1276                 wm->level = VLV_WM_LEVEL_PM2;
1277
1278         for_each_intel_crtc(dev, crtc) {
1279                 struct vlv_wm_state *wm_state = &crtc->wm_state;
1280                 enum pipe pipe = crtc->pipe;
1281
1282                 if (!crtc->active)
1283                         continue;
1284
1285                 wm->pipe[pipe] = wm_state->wm[wm->level];
1286                 if (wm->cxsr)
1287                         wm->sr = wm_state->sr[wm->level];
1288
1289                 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2;
1290                 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2;
1291                 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2;
1292                 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2;
1293         }
1294 }
1295
1296 static void vlv_update_wm(struct drm_crtc *crtc)
1297 {
1298         struct drm_device *dev = crtc->dev;
1299         struct drm_i915_private *dev_priv = dev->dev_private;
1300         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1301         enum pipe pipe = intel_crtc->pipe;
1302         struct vlv_wm_values wm = {};
1303
1304         vlv_compute_wm(intel_crtc);
1305         vlv_merge_wm(dev, &wm);
1306
1307         if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
1308                 /* FIXME should be part of crtc atomic commit */
1309                 vlv_pipe_set_fifo_size(intel_crtc);
1310                 return;
1311         }
1312
1313         if (wm.level < VLV_WM_LEVEL_DDR_DVFS &&
1314             dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS)
1315                 chv_set_memory_dvfs(dev_priv, false);
1316
1317         if (wm.level < VLV_WM_LEVEL_PM5 &&
1318             dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5)
1319                 chv_set_memory_pm5(dev_priv, false);
1320
1321         if (!wm.cxsr && dev_priv->wm.vlv.cxsr)
1322                 intel_set_memory_cxsr(dev_priv, false);
1323
1324         /* FIXME should be part of crtc atomic commit */
1325         vlv_pipe_set_fifo_size(intel_crtc);
1326
1327         vlv_write_wm_values(intel_crtc, &wm);
1328
1329         DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1330                       "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1331                       pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1332                       wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1],
1333                       wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr);
1334
1335         if (wm.cxsr && !dev_priv->wm.vlv.cxsr)
1336                 intel_set_memory_cxsr(dev_priv, true);
1337
1338         if (wm.level >= VLV_WM_LEVEL_PM5 &&
1339             dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5)
1340                 chv_set_memory_pm5(dev_priv, true);
1341
1342         if (wm.level >= VLV_WM_LEVEL_DDR_DVFS &&
1343             dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS)
1344                 chv_set_memory_dvfs(dev_priv, true);
1345
1346         dev_priv->wm.vlv = wm;
1347 }
1348
1349 #define single_plane_enabled(mask) is_power_of_2(mask)
1350
1351 static void g4x_update_wm(struct drm_crtc *crtc)
1352 {
1353         struct drm_device *dev = crtc->dev;
1354         static const int sr_latency_ns = 12000;
1355         struct drm_i915_private *dev_priv = dev->dev_private;
1356         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1357         int plane_sr, cursor_sr;
1358         unsigned int enabled = 0;
1359         bool cxsr_enabled;
1360
1361         if (g4x_compute_wm0(dev, PIPE_A,
1362                             &g4x_wm_info, pessimal_latency_ns,
1363                             &g4x_cursor_wm_info, pessimal_latency_ns,
1364                             &planea_wm, &cursora_wm))
1365                 enabled |= 1 << PIPE_A;
1366
1367         if (g4x_compute_wm0(dev, PIPE_B,
1368                             &g4x_wm_info, pessimal_latency_ns,
1369                             &g4x_cursor_wm_info, pessimal_latency_ns,
1370                             &planeb_wm, &cursorb_wm))
1371                 enabled |= 1 << PIPE_B;
1372
1373         if (single_plane_enabled(enabled) &&
1374             g4x_compute_srwm(dev, ffs(enabled) - 1,
1375                              sr_latency_ns,
1376                              &g4x_wm_info,
1377                              &g4x_cursor_wm_info,
1378                              &plane_sr, &cursor_sr)) {
1379                 cxsr_enabled = true;
1380         } else {
1381                 cxsr_enabled = false;
1382                 intel_set_memory_cxsr(dev_priv, false);
1383                 plane_sr = cursor_sr = 0;
1384         }
1385
1386         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1387                       "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1388                       planea_wm, cursora_wm,
1389                       planeb_wm, cursorb_wm,
1390                       plane_sr, cursor_sr);
1391
1392         I915_WRITE(DSPFW1,
1393                    FW_WM(plane_sr, SR) |
1394                    FW_WM(cursorb_wm, CURSORB) |
1395                    FW_WM(planeb_wm, PLANEB) |
1396                    FW_WM(planea_wm, PLANEA));
1397         I915_WRITE(DSPFW2,
1398                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1399                    FW_WM(cursora_wm, CURSORA));
1400         /* HPLL off in SR has some issues on G4x... disable it */
1401         I915_WRITE(DSPFW3,
1402                    (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1403                    FW_WM(cursor_sr, CURSOR_SR));
1404
1405         if (cxsr_enabled)
1406                 intel_set_memory_cxsr(dev_priv, true);
1407 }
1408
1409 static void i965_update_wm(struct drm_crtc *unused_crtc)
1410 {
1411         struct drm_device *dev = unused_crtc->dev;
1412         struct drm_i915_private *dev_priv = dev->dev_private;
1413         struct drm_crtc *crtc;
1414         int srwm = 1;
1415         int cursor_sr = 16;
1416         bool cxsr_enabled;
1417
1418         /* Calc sr entries for one plane configs */
1419         crtc = single_enabled_crtc(dev);
1420         if (crtc) {
1421                 /* self-refresh has much higher latency */
1422                 static const int sr_latency_ns = 12000;
1423                 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1424                 int clock = adjusted_mode->crtc_clock;
1425                 int htotal = adjusted_mode->crtc_htotal;
1426                 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
1427                 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
1428                 unsigned long line_time_us;
1429                 int entries;
1430
1431                 line_time_us = max(htotal * 1000 / clock, 1);
1432
1433                 /* Use ns/us then divide to preserve precision */
1434                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1435                         cpp * hdisplay;
1436                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1437                 srwm = I965_FIFO_SIZE - entries;
1438                 if (srwm < 0)
1439                         srwm = 1;
1440                 srwm &= 0x1ff;
1441                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1442                               entries, srwm);
1443
1444                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1445                         cpp * crtc->cursor->state->crtc_w;
1446                 entries = DIV_ROUND_UP(entries,
1447                                           i965_cursor_wm_info.cacheline_size);
1448                 cursor_sr = i965_cursor_wm_info.fifo_size -
1449                         (entries + i965_cursor_wm_info.guard_size);
1450
1451                 if (cursor_sr > i965_cursor_wm_info.max_wm)
1452                         cursor_sr = i965_cursor_wm_info.max_wm;
1453
1454                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1455                               "cursor %d\n", srwm, cursor_sr);
1456
1457                 cxsr_enabled = true;
1458         } else {
1459                 cxsr_enabled = false;
1460                 /* Turn off self refresh if both pipes are enabled */
1461                 intel_set_memory_cxsr(dev_priv, false);
1462         }
1463
1464         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1465                       srwm);
1466
1467         /* 965 has limitations... */
1468         I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1469                    FW_WM(8, CURSORB) |
1470                    FW_WM(8, PLANEB) |
1471                    FW_WM(8, PLANEA));
1472         I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1473                    FW_WM(8, PLANEC_OLD));
1474         /* update cursor SR watermark */
1475         I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
1476
1477         if (cxsr_enabled)
1478                 intel_set_memory_cxsr(dev_priv, true);
1479 }
1480
1481 #undef FW_WM
1482
1483 static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1484 {
1485         struct drm_device *dev = unused_crtc->dev;
1486         struct drm_i915_private *dev_priv = dev->dev_private;
1487         const struct intel_watermark_params *wm_info;
1488         uint32_t fwater_lo;
1489         uint32_t fwater_hi;
1490         int cwm, srwm = 1;
1491         int fifo_size;
1492         int planea_wm, planeb_wm;
1493         struct drm_crtc *crtc, *enabled = NULL;
1494
1495         if (IS_I945GM(dev))
1496                 wm_info = &i945_wm_info;
1497         else if (!IS_GEN2(dev))
1498                 wm_info = &i915_wm_info;
1499         else
1500                 wm_info = &i830_a_wm_info;
1501
1502         fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1503         crtc = intel_get_crtc_for_plane(dev, 0);
1504         if (intel_crtc_active(crtc)) {
1505                 const struct drm_display_mode *adjusted_mode;
1506                 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
1507                 if (IS_GEN2(dev))
1508                         cpp = 4;
1509
1510                 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1511                 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1512                                                wm_info, fifo_size, cpp,
1513                                                pessimal_latency_ns);
1514                 enabled = crtc;
1515         } else {
1516                 planea_wm = fifo_size - wm_info->guard_size;
1517                 if (planea_wm > (long)wm_info->max_wm)
1518                         planea_wm = wm_info->max_wm;
1519         }
1520
1521         if (IS_GEN2(dev))
1522                 wm_info = &i830_bc_wm_info;
1523
1524         fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1525         crtc = intel_get_crtc_for_plane(dev, 1);
1526         if (intel_crtc_active(crtc)) {
1527                 const struct drm_display_mode *adjusted_mode;
1528                 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
1529                 if (IS_GEN2(dev))
1530                         cpp = 4;
1531
1532                 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1533                 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1534                                                wm_info, fifo_size, cpp,
1535                                                pessimal_latency_ns);
1536                 if (enabled == NULL)
1537                         enabled = crtc;
1538                 else
1539                         enabled = NULL;
1540         } else {
1541                 planeb_wm = fifo_size - wm_info->guard_size;
1542                 if (planeb_wm > (long)wm_info->max_wm)
1543                         planeb_wm = wm_info->max_wm;
1544         }
1545
1546         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1547
1548         if (IS_I915GM(dev) && enabled) {
1549                 struct drm_i915_gem_object *obj;
1550
1551                 obj = intel_fb_obj(enabled->primary->state->fb);
1552
1553                 /* self-refresh seems busted with untiled */
1554                 if (obj->tiling_mode == I915_TILING_NONE)
1555                         enabled = NULL;
1556         }
1557
1558         /*
1559          * Overlay gets an aggressive default since video jitter is bad.
1560          */
1561         cwm = 2;
1562
1563         /* Play safe and disable self-refresh before adjusting watermarks. */
1564         intel_set_memory_cxsr(dev_priv, false);
1565
1566         /* Calc sr entries for one plane configs */
1567         if (HAS_FW_BLC(dev) && enabled) {
1568                 /* self-refresh has much higher latency */
1569                 static const int sr_latency_ns = 6000;
1570                 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(enabled)->config->base.adjusted_mode;
1571                 int clock = adjusted_mode->crtc_clock;
1572                 int htotal = adjusted_mode->crtc_htotal;
1573                 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
1574                 int cpp = drm_format_plane_cpp(enabled->primary->state->fb->pixel_format, 0);
1575                 unsigned long line_time_us;
1576                 int entries;
1577
1578                 line_time_us = max(htotal * 1000 / clock, 1);
1579
1580                 /* Use ns/us then divide to preserve precision */
1581                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1582                         cpp * hdisplay;
1583                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1584                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1585                 srwm = wm_info->fifo_size - entries;
1586                 if (srwm < 0)
1587                         srwm = 1;
1588
1589                 if (IS_I945G(dev) || IS_I945GM(dev))
1590                         I915_WRITE(FW_BLC_SELF,
1591                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1592                 else if (IS_I915GM(dev))
1593                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1594         }
1595
1596         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1597                       planea_wm, planeb_wm, cwm, srwm);
1598
1599         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1600         fwater_hi = (cwm & 0x1f);
1601
1602         /* Set request length to 8 cachelines per fetch */
1603         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1604         fwater_hi = fwater_hi | (1 << 8);
1605
1606         I915_WRITE(FW_BLC, fwater_lo);
1607         I915_WRITE(FW_BLC2, fwater_hi);
1608
1609         if (enabled)
1610                 intel_set_memory_cxsr(dev_priv, true);
1611 }
1612
1613 static void i845_update_wm(struct drm_crtc *unused_crtc)
1614 {
1615         struct drm_device *dev = unused_crtc->dev;
1616         struct drm_i915_private *dev_priv = dev->dev_private;
1617         struct drm_crtc *crtc;
1618         const struct drm_display_mode *adjusted_mode;
1619         uint32_t fwater_lo;
1620         int planea_wm;
1621
1622         crtc = single_enabled_crtc(dev);
1623         if (crtc == NULL)
1624                 return;
1625
1626         adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1627         planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1628                                        &i845_wm_info,
1629                                        dev_priv->display.get_fifo_size(dev, 0),
1630                                        4, pessimal_latency_ns);
1631         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1632         fwater_lo |= (3<<8) | planea_wm;
1633
1634         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1635
1636         I915_WRITE(FW_BLC, fwater_lo);
1637 }
1638
1639 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
1640 {
1641         uint32_t pixel_rate;
1642
1643         pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
1644
1645         /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1646          * adjust the pixel_rate here. */
1647
1648         if (pipe_config->pch_pfit.enabled) {
1649                 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
1650                 uint32_t pfit_size = pipe_config->pch_pfit.size;
1651
1652                 pipe_w = pipe_config->pipe_src_w;
1653                 pipe_h = pipe_config->pipe_src_h;
1654
1655                 pfit_w = (pfit_size >> 16) & 0xFFFF;
1656                 pfit_h = pfit_size & 0xFFFF;
1657                 if (pipe_w < pfit_w)
1658                         pipe_w = pfit_w;
1659                 if (pipe_h < pfit_h)
1660                         pipe_h = pfit_h;
1661
1662                 if (WARN_ON(!pfit_w || !pfit_h))
1663                         return pixel_rate;
1664
1665                 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1666                                      pfit_w * pfit_h);
1667         }
1668
1669         return pixel_rate;
1670 }
1671
1672 /* latency must be in 0.1us units. */
1673 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
1674 {
1675         uint64_t ret;
1676
1677         if (WARN(latency == 0, "Latency value missing\n"))
1678                 return UINT_MAX;
1679
1680         ret = (uint64_t) pixel_rate * cpp * latency;
1681         ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1682
1683         return ret;
1684 }
1685
1686 /* latency must be in 0.1us units. */
1687 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
1688                                uint32_t horiz_pixels, uint8_t cpp,
1689                                uint32_t latency)
1690 {
1691         uint32_t ret;
1692
1693         if (WARN(latency == 0, "Latency value missing\n"))
1694                 return UINT_MAX;
1695         if (WARN_ON(!pipe_htotal))
1696                 return UINT_MAX;
1697
1698         ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1699         ret = (ret + 1) * horiz_pixels * cpp;
1700         ret = DIV_ROUND_UP(ret, 64) + 2;
1701         return ret;
1702 }
1703
1704 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
1705                            uint8_t cpp)
1706 {
1707         /*
1708          * Neither of these should be possible since this function shouldn't be
1709          * called if the CRTC is off or the plane is invisible.  But let's be
1710          * extra paranoid to avoid a potential divide-by-zero if we screw up
1711          * elsewhere in the driver.
1712          */
1713         if (WARN_ON(!cpp))
1714                 return 0;
1715         if (WARN_ON(!horiz_pixels))
1716                 return 0;
1717
1718         return DIV_ROUND_UP(pri_val * 64, horiz_pixels * cpp) + 2;
1719 }
1720
1721 struct ilk_wm_maximums {
1722         uint16_t pri;
1723         uint16_t spr;
1724         uint16_t cur;
1725         uint16_t fbc;
1726 };
1727
1728 /*
1729  * For both WM_PIPE and WM_LP.
1730  * mem_value must be in 0.1us units.
1731  */
1732 static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
1733                                    const struct intel_plane_state *pstate,
1734                                    uint32_t mem_value,
1735                                    bool is_lp)
1736 {
1737         int cpp = pstate->base.fb ?
1738                 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
1739         uint32_t method1, method2;
1740
1741         if (!cstate->base.active || !pstate->visible)
1742                 return 0;
1743
1744         method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
1745
1746         if (!is_lp)
1747                 return method1;
1748
1749         method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1750                                  cstate->base.adjusted_mode.crtc_htotal,
1751                                  drm_rect_width(&pstate->dst),
1752                                  cpp, mem_value);
1753
1754         return min(method1, method2);
1755 }
1756
1757 /*
1758  * For both WM_PIPE and WM_LP.
1759  * mem_value must be in 0.1us units.
1760  */
1761 static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
1762                                    const struct intel_plane_state *pstate,
1763                                    uint32_t mem_value)
1764 {
1765         int cpp = pstate->base.fb ?
1766                 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
1767         uint32_t method1, method2;
1768
1769         if (!cstate->base.active || !pstate->visible)
1770                 return 0;
1771
1772         method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
1773         method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1774                                  cstate->base.adjusted_mode.crtc_htotal,
1775                                  drm_rect_width(&pstate->dst),
1776                                  cpp, mem_value);
1777         return min(method1, method2);
1778 }
1779
1780 /*
1781  * For both WM_PIPE and WM_LP.
1782  * mem_value must be in 0.1us units.
1783  */
1784 static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
1785                                    const struct intel_plane_state *pstate,
1786                                    uint32_t mem_value)
1787 {
1788         /*
1789          * We treat the cursor plane as always-on for the purposes of watermark
1790          * calculation.  Until we have two-stage watermark programming merged,
1791          * this is necessary to avoid flickering.
1792          */
1793         int cpp = 4;
1794         int width = pstate->visible ? pstate->base.crtc_w : 64;
1795
1796         if (!cstate->base.active)
1797                 return 0;
1798
1799         return ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1800                               cstate->base.adjusted_mode.crtc_htotal,
1801                               width, cpp, mem_value);
1802 }
1803
1804 /* Only for WM_LP. */
1805 static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
1806                                    const struct intel_plane_state *pstate,
1807                                    uint32_t pri_val)
1808 {
1809         int cpp = pstate->base.fb ?
1810                 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
1811
1812         if (!cstate->base.active || !pstate->visible)
1813                 return 0;
1814
1815         return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->dst), cpp);
1816 }
1817
1818 static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1819 {
1820         if (INTEL_INFO(dev)->gen >= 8)
1821                 return 3072;
1822         else if (INTEL_INFO(dev)->gen >= 7)
1823                 return 768;
1824         else
1825                 return 512;
1826 }
1827
1828 static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1829                                          int level, bool is_sprite)
1830 {
1831         if (INTEL_INFO(dev)->gen >= 8)
1832                 /* BDW primary/sprite plane watermarks */
1833                 return level == 0 ? 255 : 2047;
1834         else if (INTEL_INFO(dev)->gen >= 7)
1835                 /* IVB/HSW primary/sprite plane watermarks */
1836                 return level == 0 ? 127 : 1023;
1837         else if (!is_sprite)
1838                 /* ILK/SNB primary plane watermarks */
1839                 return level == 0 ? 127 : 511;
1840         else
1841                 /* ILK/SNB sprite plane watermarks */
1842                 return level == 0 ? 63 : 255;
1843 }
1844
1845 static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1846                                           int level)
1847 {
1848         if (INTEL_INFO(dev)->gen >= 7)
1849                 return level == 0 ? 63 : 255;
1850         else
1851                 return level == 0 ? 31 : 63;
1852 }
1853
1854 static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1855 {
1856         if (INTEL_INFO(dev)->gen >= 8)
1857                 return 31;
1858         else
1859                 return 15;
1860 }
1861
1862 /* Calculate the maximum primary/sprite plane watermark */
1863 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1864                                      int level,
1865                                      const struct intel_wm_config *config,
1866                                      enum intel_ddb_partitioning ddb_partitioning,
1867                                      bool is_sprite)
1868 {
1869         unsigned int fifo_size = ilk_display_fifo_size(dev);
1870
1871         /* if sprites aren't enabled, sprites get nothing */
1872         if (is_sprite && !config->sprites_enabled)
1873                 return 0;
1874
1875         /* HSW allows LP1+ watermarks even with multiple pipes */
1876         if (level == 0 || config->num_pipes_active > 1) {
1877                 fifo_size /= INTEL_INFO(dev)->num_pipes;
1878
1879                 /*
1880                  * For some reason the non self refresh
1881                  * FIFO size is only half of the self
1882                  * refresh FIFO size on ILK/SNB.
1883                  */
1884                 if (INTEL_INFO(dev)->gen <= 6)
1885                         fifo_size /= 2;
1886         }
1887
1888         if (config->sprites_enabled) {
1889                 /* level 0 is always calculated with 1:1 split */
1890                 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1891                         if (is_sprite)
1892                                 fifo_size *= 5;
1893                         fifo_size /= 6;
1894                 } else {
1895                         fifo_size /= 2;
1896                 }
1897         }
1898
1899         /* clamp to max that the registers can hold */
1900         return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
1901 }
1902
1903 /* Calculate the maximum cursor plane watermark */
1904 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
1905                                       int level,
1906                                       const struct intel_wm_config *config)
1907 {
1908         /* HSW LP1+ watermarks w/ multiple pipes */
1909         if (level > 0 && config->num_pipes_active > 1)
1910                 return 64;
1911
1912         /* otherwise just report max that registers can hold */
1913         return ilk_cursor_wm_reg_max(dev, level);
1914 }
1915
1916 static void ilk_compute_wm_maximums(const struct drm_device *dev,
1917                                     int level,
1918                                     const struct intel_wm_config *config,
1919                                     enum intel_ddb_partitioning ddb_partitioning,
1920                                     struct ilk_wm_maximums *max)
1921 {
1922         max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1923         max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1924         max->cur = ilk_cursor_wm_max(dev, level, config);
1925         max->fbc = ilk_fbc_wm_reg_max(dev);
1926 }
1927
1928 static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1929                                         int level,
1930                                         struct ilk_wm_maximums *max)
1931 {
1932         max->pri = ilk_plane_wm_reg_max(dev, level, false);
1933         max->spr = ilk_plane_wm_reg_max(dev, level, true);
1934         max->cur = ilk_cursor_wm_reg_max(dev, level);
1935         max->fbc = ilk_fbc_wm_reg_max(dev);
1936 }
1937
1938 static bool ilk_validate_wm_level(int level,
1939                                   const struct ilk_wm_maximums *max,
1940                                   struct intel_wm_level *result)
1941 {
1942         bool ret;
1943
1944         /* already determined to be invalid? */
1945         if (!result->enable)
1946                 return false;
1947
1948         result->enable = result->pri_val <= max->pri &&
1949                          result->spr_val <= max->spr &&
1950                          result->cur_val <= max->cur;
1951
1952         ret = result->enable;
1953
1954         /*
1955          * HACK until we can pre-compute everything,
1956          * and thus fail gracefully if LP0 watermarks
1957          * are exceeded...
1958          */
1959         if (level == 0 && !result->enable) {
1960                 if (result->pri_val > max->pri)
1961                         DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1962                                       level, result->pri_val, max->pri);
1963                 if (result->spr_val > max->spr)
1964                         DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
1965                                       level, result->spr_val, max->spr);
1966                 if (result->cur_val > max->cur)
1967                         DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
1968                                       level, result->cur_val, max->cur);
1969
1970                 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
1971                 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
1972                 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
1973                 result->enable = true;
1974         }
1975
1976         return ret;
1977 }
1978
1979 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
1980                                  const struct intel_crtc *intel_crtc,
1981                                  int level,
1982                                  struct intel_crtc_state *cstate,
1983                                  struct intel_plane_state *pristate,
1984                                  struct intel_plane_state *sprstate,
1985                                  struct intel_plane_state *curstate,
1986                                  struct intel_wm_level *result)
1987 {
1988         uint16_t pri_latency = dev_priv->wm.pri_latency[level];
1989         uint16_t spr_latency = dev_priv->wm.spr_latency[level];
1990         uint16_t cur_latency = dev_priv->wm.cur_latency[level];
1991
1992         /* WM1+ latency values stored in 0.5us units */
1993         if (level > 0) {
1994                 pri_latency *= 5;
1995                 spr_latency *= 5;
1996                 cur_latency *= 5;
1997         }
1998
1999         result->pri_val = ilk_compute_pri_wm(cstate, pristate,
2000                                              pri_latency, level);
2001         result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency);
2002         result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency);
2003         result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val);
2004         result->enable = true;
2005 }
2006
2007 static uint32_t
2008 hsw_compute_linetime_wm(struct drm_device *dev,
2009                         struct intel_crtc_state *cstate)
2010 {
2011         struct drm_i915_private *dev_priv = dev->dev_private;
2012         const struct drm_display_mode *adjusted_mode =
2013                 &cstate->base.adjusted_mode;
2014         u32 linetime, ips_linetime;
2015
2016         if (!cstate->base.active)
2017                 return 0;
2018         if (WARN_ON(adjusted_mode->crtc_clock == 0))
2019                 return 0;
2020         if (WARN_ON(dev_priv->cdclk_freq == 0))
2021                 return 0;
2022
2023         /* The WM are computed with base on how long it takes to fill a single
2024          * row at the given clock rate, multiplied by 8.
2025          * */
2026         linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2027                                      adjusted_mode->crtc_clock);
2028         ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2029                                          dev_priv->cdclk_freq);
2030
2031         return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2032                PIPE_WM_LINETIME_TIME(linetime);
2033 }
2034
2035 static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
2036 {
2037         struct drm_i915_private *dev_priv = dev->dev_private;
2038
2039         if (IS_GEN9(dev)) {
2040                 uint32_t val;
2041                 int ret, i;
2042                 int level, max_level = ilk_wm_max_level(dev);
2043
2044                 /* read the first set of memory latencies[0:3] */
2045                 val = 0; /* data0 to be programmed to 0 for first set */
2046                 mutex_lock(&dev_priv->rps.hw_lock);
2047                 ret = sandybridge_pcode_read(dev_priv,
2048                                              GEN9_PCODE_READ_MEM_LATENCY,
2049                                              &val);
2050                 mutex_unlock(&dev_priv->rps.hw_lock);
2051
2052                 if (ret) {
2053                         DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2054                         return;
2055                 }
2056
2057                 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2058                 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2059                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2060                 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2061                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2062                 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2063                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2064
2065                 /* read the second set of memory latencies[4:7] */
2066                 val = 1; /* data0 to be programmed to 1 for second set */
2067                 mutex_lock(&dev_priv->rps.hw_lock);
2068                 ret = sandybridge_pcode_read(dev_priv,
2069                                              GEN9_PCODE_READ_MEM_LATENCY,
2070                                              &val);
2071                 mutex_unlock(&dev_priv->rps.hw_lock);
2072                 if (ret) {
2073                         DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2074                         return;
2075                 }
2076
2077                 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2078                 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2079                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2080                 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2081                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2082                 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2083                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2084
2085                 /*
2086                  * WaWmMemoryReadLatency:skl
2087                  *
2088                  * punit doesn't take into account the read latency so we need
2089                  * to add 2us to the various latency levels we retrieve from
2090                  * the punit.
2091                  *   - W0 is a bit special in that it's the only level that
2092                  *   can't be disabled if we want to have display working, so
2093                  *   we always add 2us there.
2094                  *   - For levels >=1, punit returns 0us latency when they are
2095                  *   disabled, so we respect that and don't add 2us then
2096                  *
2097                  * Additionally, if a level n (n > 1) has a 0us latency, all
2098                  * levels m (m >= n) need to be disabled. We make sure to
2099                  * sanitize the values out of the punit to satisfy this
2100                  * requirement.
2101                  */
2102                 wm[0] += 2;
2103                 for (level = 1; level <= max_level; level++)
2104                         if (wm[level] != 0)
2105                                 wm[level] += 2;
2106                         else {
2107                                 for (i = level + 1; i <= max_level; i++)
2108                                         wm[i] = 0;
2109
2110                                 break;
2111                         }
2112         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2113                 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2114
2115                 wm[0] = (sskpd >> 56) & 0xFF;
2116                 if (wm[0] == 0)
2117                         wm[0] = sskpd & 0xF;
2118                 wm[1] = (sskpd >> 4) & 0xFF;
2119                 wm[2] = (sskpd >> 12) & 0xFF;
2120                 wm[3] = (sskpd >> 20) & 0x1FF;
2121                 wm[4] = (sskpd >> 32) & 0x1FF;
2122         } else if (INTEL_INFO(dev)->gen >= 6) {
2123                 uint32_t sskpd = I915_READ(MCH_SSKPD);
2124
2125                 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2126                 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2127                 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2128                 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2129         } else if (INTEL_INFO(dev)->gen >= 5) {
2130                 uint32_t mltr = I915_READ(MLTR_ILK);
2131
2132                 /* ILK primary LP0 latency is 700 ns */
2133                 wm[0] = 7;
2134                 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2135                 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2136         }
2137 }
2138
2139 static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2140 {
2141         /* ILK sprite LP0 latency is 1300 ns */
2142         if (INTEL_INFO(dev)->gen == 5)
2143                 wm[0] = 13;
2144 }
2145
2146 static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2147 {
2148         /* ILK cursor LP0 latency is 1300 ns */
2149         if (INTEL_INFO(dev)->gen == 5)
2150                 wm[0] = 13;
2151
2152         /* WaDoubleCursorLP3Latency:ivb */
2153         if (IS_IVYBRIDGE(dev))
2154                 wm[3] *= 2;
2155 }
2156
2157 int ilk_wm_max_level(const struct drm_device *dev)
2158 {
2159         /* how many WM levels are we expecting */
2160         if (INTEL_INFO(dev)->gen >= 9)
2161                 return 7;
2162         else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2163                 return 4;
2164         else if (INTEL_INFO(dev)->gen >= 6)
2165                 return 3;
2166         else
2167                 return 2;
2168 }
2169
2170 static void intel_print_wm_latency(struct drm_device *dev,
2171                                    const char *name,
2172                                    const uint16_t wm[8])
2173 {
2174         int level, max_level = ilk_wm_max_level(dev);
2175
2176         for (level = 0; level <= max_level; level++) {
2177                 unsigned int latency = wm[level];
2178
2179                 if (latency == 0) {
2180                         DRM_ERROR("%s WM%d latency not provided\n",
2181                                   name, level);
2182                         continue;
2183                 }
2184
2185                 /*
2186                  * - latencies are in us on gen9.
2187                  * - before then, WM1+ latency values are in 0.5us units
2188                  */
2189                 if (IS_GEN9(dev))
2190                         latency *= 10;
2191                 else if (level > 0)
2192                         latency *= 5;
2193
2194                 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2195                               name, level, wm[level],
2196                               latency / 10, latency % 10);
2197         }
2198 }
2199
2200 static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2201                                     uint16_t wm[5], uint16_t min)
2202 {
2203         int level, max_level = ilk_wm_max_level(dev_priv->dev);
2204
2205         if (wm[0] >= min)
2206                 return false;
2207
2208         wm[0] = max(wm[0], min);
2209         for (level = 1; level <= max_level; level++)
2210                 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2211
2212         return true;
2213 }
2214
2215 static void snb_wm_latency_quirk(struct drm_device *dev)
2216 {
2217         struct drm_i915_private *dev_priv = dev->dev_private;
2218         bool changed;
2219
2220         /*
2221          * The BIOS provided WM memory latency values are often
2222          * inadequate for high resolution displays. Adjust them.
2223          */
2224         changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2225                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2226                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2227
2228         if (!changed)
2229                 return;
2230
2231         DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2232         intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2233         intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2234         intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2235 }
2236
2237 static void ilk_setup_wm_latency(struct drm_device *dev)
2238 {
2239         struct drm_i915_private *dev_priv = dev->dev_private;
2240
2241         intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2242
2243         memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2244                sizeof(dev_priv->wm.pri_latency));
2245         memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2246                sizeof(dev_priv->wm.pri_latency));
2247
2248         intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2249         intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
2250
2251         intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2252         intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2253         intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2254
2255         if (IS_GEN6(dev))
2256                 snb_wm_latency_quirk(dev);
2257 }
2258
2259 static void skl_setup_wm_latency(struct drm_device *dev)
2260 {
2261         struct drm_i915_private *dev_priv = dev->dev_private;
2262
2263         intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
2264         intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
2265 }
2266
2267 static bool ilk_validate_pipe_wm(struct drm_device *dev,
2268                                  struct intel_pipe_wm *pipe_wm)
2269 {
2270         /* LP0 watermark maximums depend on this pipe alone */
2271         const struct intel_wm_config config = {
2272                 .num_pipes_active = 1,
2273                 .sprites_enabled = pipe_wm->sprites_enabled,
2274                 .sprites_scaled = pipe_wm->sprites_scaled,
2275         };
2276         struct ilk_wm_maximums max;
2277
2278         /* LP0 watermarks always use 1/2 DDB partitioning */
2279         ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2280
2281         /* At least LP0 must be valid */
2282         if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) {
2283                 DRM_DEBUG_KMS("LP0 watermark invalid\n");
2284                 return false;
2285         }
2286
2287         return true;
2288 }
2289
2290 /* Compute new watermarks for the pipe */
2291 static int ilk_compute_pipe_wm(struct intel_crtc *intel_crtc,
2292                                struct drm_atomic_state *state)
2293 {
2294         struct intel_pipe_wm *pipe_wm;
2295         struct drm_device *dev = intel_crtc->base.dev;
2296         const struct drm_i915_private *dev_priv = dev->dev_private;
2297         struct intel_crtc_state *cstate = NULL;
2298         struct intel_plane *intel_plane;
2299         struct drm_plane_state *ps;
2300         struct intel_plane_state *pristate = NULL;
2301         struct intel_plane_state *sprstate = NULL;
2302         struct intel_plane_state *curstate = NULL;
2303         int level, max_level = ilk_wm_max_level(dev), usable_level;
2304         struct ilk_wm_maximums max;
2305
2306         cstate = intel_atomic_get_crtc_state(state, intel_crtc);
2307         if (IS_ERR(cstate))
2308                 return PTR_ERR(cstate);
2309
2310         pipe_wm = &cstate->wm.optimal.ilk;
2311
2312         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2313                 ps = drm_atomic_get_plane_state(state,
2314                                                 &intel_plane->base);
2315                 if (IS_ERR(ps))
2316                         return PTR_ERR(ps);
2317
2318                 if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY)
2319                         pristate = to_intel_plane_state(ps);
2320                 else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY)
2321                         sprstate = to_intel_plane_state(ps);
2322                 else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
2323                         curstate = to_intel_plane_state(ps);
2324         }
2325
2326         pipe_wm->pipe_enabled = cstate->base.active;
2327         pipe_wm->sprites_enabled = sprstate->visible;
2328         pipe_wm->sprites_scaled = sprstate->visible &&
2329                 (drm_rect_width(&sprstate->dst) != drm_rect_width(&sprstate->src) >> 16 ||
2330                 drm_rect_height(&sprstate->dst) != drm_rect_height(&sprstate->src) >> 16);
2331
2332         usable_level = max_level;
2333
2334         /* ILK/SNB: LP2+ watermarks only w/o sprites */
2335         if (INTEL_INFO(dev)->gen <= 6 && sprstate->visible)
2336                 usable_level = 1;
2337
2338         /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2339         if (pipe_wm->sprites_scaled)
2340                 usable_level = 0;
2341
2342         ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
2343                              pristate, sprstate, curstate, &pipe_wm->wm[0]);
2344
2345         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2346                 pipe_wm->linetime = hsw_compute_linetime_wm(dev, cstate);
2347
2348         if (!ilk_validate_pipe_wm(dev, pipe_wm))
2349                 return -EINVAL;
2350
2351         ilk_compute_wm_reg_maximums(dev, 1, &max);
2352
2353         for (level = 1; level <= max_level; level++) {
2354                 struct intel_wm_level *wm = &pipe_wm->wm[level];
2355
2356                 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,
2357                                      pristate, sprstate, curstate, wm);
2358
2359                 /*
2360                  * Disable any watermark level that exceeds the
2361                  * register maximums since such watermarks are
2362                  * always invalid.
2363                  */
2364                 if (level > usable_level) {
2365                         wm->enable = false;
2366                 } else if (!ilk_validate_wm_level(level, &max, wm)) {
2367                         wm->enable = false;
2368                         usable_level = level;
2369                 }
2370         }
2371
2372         return 0;
2373 }
2374
2375 /*
2376  * Build a set of 'intermediate' watermark values that satisfy both the old
2377  * state and the new state.  These can be programmed to the hardware
2378  * immediately.
2379  */
2380 static int ilk_compute_intermediate_wm(struct drm_device *dev,
2381                                        struct intel_crtc *intel_crtc,
2382                                        struct intel_crtc_state *newstate)
2383 {
2384         struct intel_pipe_wm *a = &newstate->wm.intermediate;
2385         struct intel_pipe_wm *b = &intel_crtc->wm.active.ilk;
2386         int level, max_level = ilk_wm_max_level(dev);
2387
2388         /*
2389          * Start with the final, target watermarks, then combine with the
2390          * currently active watermarks to get values that are safe both before
2391          * and after the vblank.
2392          */
2393         *a = newstate->wm.optimal.ilk;
2394         a->pipe_enabled |= b->pipe_enabled;
2395         a->sprites_enabled |= b->sprites_enabled;
2396         a->sprites_scaled |= b->sprites_scaled;
2397
2398         for (level = 0; level <= max_level; level++) {
2399                 struct intel_wm_level *a_wm = &a->wm[level];
2400                 const struct intel_wm_level *b_wm = &b->wm[level];
2401
2402                 a_wm->enable &= b_wm->enable;
2403                 a_wm->pri_val = max(a_wm->pri_val, b_wm->pri_val);
2404                 a_wm->spr_val = max(a_wm->spr_val, b_wm->spr_val);
2405                 a_wm->cur_val = max(a_wm->cur_val, b_wm->cur_val);
2406                 a_wm->fbc_val = max(a_wm->fbc_val, b_wm->fbc_val);
2407         }
2408
2409         /*
2410          * We need to make sure that these merged watermark values are
2411          * actually a valid configuration themselves.  If they're not,
2412          * there's no safe way to transition from the old state to
2413          * the new state, so we need to fail the atomic transaction.
2414          */
2415         if (!ilk_validate_pipe_wm(dev, a))
2416                 return -EINVAL;
2417
2418         /*
2419          * If our intermediate WM are identical to the final WM, then we can
2420          * omit the post-vblank programming; only update if it's different.
2421          */
2422         if (memcmp(a, &newstate->wm.optimal.ilk, sizeof(*a)) == 0)
2423                 newstate->wm.need_postvbl_update = false;
2424
2425         return 0;
2426 }
2427
2428 /*
2429  * Merge the watermarks from all active pipes for a specific level.
2430  */
2431 static void ilk_merge_wm_level(struct drm_device *dev,
2432                                int level,
2433                                struct intel_wm_level *ret_wm)
2434 {
2435         const struct intel_crtc *intel_crtc;
2436
2437         ret_wm->enable = true;
2438
2439         for_each_intel_crtc(dev, intel_crtc) {
2440                 const struct intel_pipe_wm *active = &intel_crtc->wm.active.ilk;
2441                 const struct intel_wm_level *wm = &active->wm[level];
2442
2443                 if (!active->pipe_enabled)
2444                         continue;
2445
2446                 /*
2447                  * The watermark values may have been used in the past,
2448                  * so we must maintain them in the registers for some
2449                  * time even if the level is now disabled.
2450                  */
2451                 if (!wm->enable)
2452                         ret_wm->enable = false;
2453
2454                 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2455                 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2456                 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2457                 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2458         }
2459 }
2460
2461 /*
2462  * Merge all low power watermarks for all active pipes.
2463  */
2464 static void ilk_wm_merge(struct drm_device *dev,
2465                          const struct intel_wm_config *config,
2466                          const struct ilk_wm_maximums *max,
2467                          struct intel_pipe_wm *merged)
2468 {
2469         struct drm_i915_private *dev_priv = dev->dev_private;
2470         int level, max_level = ilk_wm_max_level(dev);
2471         int last_enabled_level = max_level;
2472
2473         /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2474         if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2475             config->num_pipes_active > 1)
2476                 return;
2477
2478         /* ILK: FBC WM must be disabled always */
2479         merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
2480
2481         /* merge each WM1+ level */
2482         for (level = 1; level <= max_level; level++) {
2483                 struct intel_wm_level *wm = &merged->wm[level];
2484
2485                 ilk_merge_wm_level(dev, level, wm);
2486
2487                 if (level > last_enabled_level)
2488                         wm->enable = false;
2489                 else if (!ilk_validate_wm_level(level, max, wm))
2490                         /* make sure all following levels get disabled */
2491                         last_enabled_level = level - 1;
2492
2493                 /*
2494                  * The spec says it is preferred to disable
2495                  * FBC WMs instead of disabling a WM level.
2496                  */
2497                 if (wm->fbc_val > max->fbc) {
2498                         if (wm->enable)
2499                                 merged->fbc_wm_enabled = false;
2500                         wm->fbc_val = 0;
2501                 }
2502         }
2503
2504         /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2505         /*
2506          * FIXME this is racy. FBC might get enabled later.
2507          * What we should check here is whether FBC can be
2508          * enabled sometime later.
2509          */
2510         if (IS_GEN5(dev) && !merged->fbc_wm_enabled &&
2511             intel_fbc_is_active(dev_priv)) {
2512                 for (level = 2; level <= max_level; level++) {
2513                         struct intel_wm_level *wm = &merged->wm[level];
2514
2515                         wm->enable = false;
2516                 }
2517         }
2518 }
2519
2520 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2521 {
2522         /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2523         return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2524 }
2525
2526 /* The value we need to program into the WM_LPx latency field */
2527 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2528 {
2529         struct drm_i915_private *dev_priv = dev->dev_private;
2530
2531         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2532                 return 2 * level;
2533         else
2534                 return dev_priv->wm.pri_latency[level];
2535 }
2536
2537 static void ilk_compute_wm_results(struct drm_device *dev,
2538                                    const struct intel_pipe_wm *merged,
2539                                    enum intel_ddb_partitioning partitioning,
2540                                    struct ilk_wm_values *results)
2541 {
2542         struct intel_crtc *intel_crtc;
2543         int level, wm_lp;
2544
2545         results->enable_fbc_wm = merged->fbc_wm_enabled;
2546         results->partitioning = partitioning;
2547
2548         /* LP1+ register values */
2549         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2550                 const struct intel_wm_level *r;
2551
2552                 level = ilk_wm_lp_to_level(wm_lp, merged);
2553
2554                 r = &merged->wm[level];
2555
2556                 /*
2557                  * Maintain the watermark values even if the level is
2558                  * disabled. Doing otherwise could cause underruns.
2559                  */
2560                 results->wm_lp[wm_lp - 1] =
2561                         (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
2562                         (r->pri_val << WM1_LP_SR_SHIFT) |
2563                         r->cur_val;
2564
2565                 if (r->enable)
2566                         results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2567
2568                 if (INTEL_INFO(dev)->gen >= 8)
2569                         results->wm_lp[wm_lp - 1] |=
2570                                 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2571                 else
2572                         results->wm_lp[wm_lp - 1] |=
2573                                 r->fbc_val << WM1_LP_FBC_SHIFT;
2574
2575                 /*
2576                  * Always set WM1S_LP_EN when spr_val != 0, even if the
2577                  * level is disabled. Doing otherwise could cause underruns.
2578                  */
2579                 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2580                         WARN_ON(wm_lp != 1);
2581                         results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2582                 } else
2583                         results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2584         }
2585
2586         /* LP0 register values */
2587         for_each_intel_crtc(dev, intel_crtc) {
2588                 enum pipe pipe = intel_crtc->pipe;
2589                 const struct intel_wm_level *r =
2590                         &intel_crtc->wm.active.ilk.wm[0];
2591
2592                 if (WARN_ON(!r->enable))
2593                         continue;
2594
2595                 results->wm_linetime[pipe] = intel_crtc->wm.active.ilk.linetime;
2596
2597                 results->wm_pipe[pipe] =
2598                         (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2599                         (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2600                         r->cur_val;
2601         }
2602 }
2603
2604 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2605  * case both are at the same level. Prefer r1 in case they're the same. */
2606 static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
2607                                                   struct intel_pipe_wm *r1,
2608                                                   struct intel_pipe_wm *r2)
2609 {
2610         int level, max_level = ilk_wm_max_level(dev);
2611         int level1 = 0, level2 = 0;
2612
2613         for (level = 1; level <= max_level; level++) {
2614                 if (r1->wm[level].enable)
2615                         level1 = level;
2616                 if (r2->wm[level].enable)
2617                         level2 = level;
2618         }
2619
2620         if (level1 == level2) {
2621                 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2622                         return r2;
2623                 else
2624                         return r1;
2625         } else if (level1 > level2) {
2626                 return r1;
2627         } else {
2628                 return r2;
2629         }
2630 }
2631
2632 /* dirty bits used to track which watermarks need changes */
2633 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2634 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2635 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2636 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2637 #define WM_DIRTY_FBC (1 << 24)
2638 #define WM_DIRTY_DDB (1 << 25)
2639
2640 static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
2641                                          const struct ilk_wm_values *old,
2642                                          const struct ilk_wm_values *new)
2643 {
2644         unsigned int dirty = 0;
2645         enum pipe pipe;
2646         int wm_lp;
2647
2648         for_each_pipe(dev_priv, pipe) {
2649                 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2650                         dirty |= WM_DIRTY_LINETIME(pipe);
2651                         /* Must disable LP1+ watermarks too */
2652                         dirty |= WM_DIRTY_LP_ALL;
2653                 }
2654
2655                 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2656                         dirty |= WM_DIRTY_PIPE(pipe);
2657                         /* Must disable LP1+ watermarks too */
2658                         dirty |= WM_DIRTY_LP_ALL;
2659                 }
2660         }
2661
2662         if (old->enable_fbc_wm != new->enable_fbc_wm) {
2663                 dirty |= WM_DIRTY_FBC;
2664                 /* Must disable LP1+ watermarks too */
2665                 dirty |= WM_DIRTY_LP_ALL;
2666         }
2667
2668         if (old->partitioning != new->partitioning) {
2669                 dirty |= WM_DIRTY_DDB;
2670                 /* Must disable LP1+ watermarks too */
2671                 dirty |= WM_DIRTY_LP_ALL;
2672         }
2673
2674         /* LP1+ watermarks already deemed dirty, no need to continue */
2675         if (dirty & WM_DIRTY_LP_ALL)
2676                 return dirty;
2677
2678         /* Find the lowest numbered LP1+ watermark in need of an update... */
2679         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2680                 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2681                     old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2682                         break;
2683         }
2684
2685         /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2686         for (; wm_lp <= 3; wm_lp++)
2687                 dirty |= WM_DIRTY_LP(wm_lp);
2688
2689         return dirty;
2690 }
2691
2692 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2693                                unsigned int dirty)
2694 {
2695         struct ilk_wm_values *previous = &dev_priv->wm.hw;
2696         bool changed = false;
2697
2698         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2699                 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2700                 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
2701                 changed = true;
2702         }
2703         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2704                 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2705                 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
2706                 changed = true;
2707         }
2708         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2709                 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2710                 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
2711                 changed = true;
2712         }
2713
2714         /*
2715          * Don't touch WM1S_LP_EN here.
2716          * Doing so could cause underruns.
2717          */
2718
2719         return changed;
2720 }
2721
2722 /*
2723  * The spec says we shouldn't write when we don't need, because every write
2724  * causes WMs to be re-evaluated, expending some power.
2725  */
2726 static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2727                                 struct ilk_wm_values *results)
2728 {
2729         struct drm_device *dev = dev_priv->dev;
2730         struct ilk_wm_values *previous = &dev_priv->wm.hw;
2731         unsigned int dirty;
2732         uint32_t val;
2733
2734         dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
2735         if (!dirty)
2736                 return;
2737
2738         _ilk_disable_lp_wm(dev_priv, dirty);
2739
2740         if (dirty & WM_DIRTY_PIPE(PIPE_A))
2741                 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2742         if (dirty & WM_DIRTY_PIPE(PIPE_B))
2743                 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2744         if (dirty & WM_DIRTY_PIPE(PIPE_C))
2745                 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2746
2747         if (dirty & WM_DIRTY_LINETIME(PIPE_A))
2748                 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2749         if (dirty & WM_DIRTY_LINETIME(PIPE_B))
2750                 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2751         if (dirty & WM_DIRTY_LINETIME(PIPE_C))
2752                 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2753
2754         if (dirty & WM_DIRTY_DDB) {
2755                 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2756                         val = I915_READ(WM_MISC);
2757                         if (results->partitioning == INTEL_DDB_PART_1_2)
2758                                 val &= ~WM_MISC_DATA_PARTITION_5_6;
2759                         else
2760                                 val |= WM_MISC_DATA_PARTITION_5_6;
2761                         I915_WRITE(WM_MISC, val);
2762                 } else {
2763                         val = I915_READ(DISP_ARB_CTL2);
2764                         if (results->partitioning == INTEL_DDB_PART_1_2)
2765                                 val &= ~DISP_DATA_PARTITION_5_6;
2766                         else
2767                                 val |= DISP_DATA_PARTITION_5_6;
2768                         I915_WRITE(DISP_ARB_CTL2, val);
2769                 }
2770         }
2771
2772         if (dirty & WM_DIRTY_FBC) {
2773                 val = I915_READ(DISP_ARB_CTL);
2774                 if (results->enable_fbc_wm)
2775                         val &= ~DISP_FBC_WM_DIS;
2776                 else
2777                         val |= DISP_FBC_WM_DIS;
2778                 I915_WRITE(DISP_ARB_CTL, val);
2779         }
2780
2781         if (dirty & WM_DIRTY_LP(1) &&
2782             previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2783                 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2784
2785         if (INTEL_INFO(dev)->gen >= 7) {
2786                 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2787                         I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2788                 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2789                         I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2790         }
2791
2792         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
2793                 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2794         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
2795                 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2796         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
2797                 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2798
2799         dev_priv->wm.hw = *results;
2800 }
2801
2802 bool ilk_disable_lp_wm(struct drm_device *dev)
2803 {
2804         struct drm_i915_private *dev_priv = dev->dev_private;
2805
2806         return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2807 }
2808
2809 /*
2810  * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
2811  * different active planes.
2812  */
2813
2814 #define SKL_DDB_SIZE            896     /* in blocks */
2815 #define BXT_DDB_SIZE            512
2816
2817 /*
2818  * Return the index of a plane in the SKL DDB and wm result arrays.  Primary
2819  * plane is always in slot 0, cursor is always in slot I915_MAX_PLANES-1, and
2820  * other universal planes are in indices 1..n.  Note that this may leave unused
2821  * indices between the top "sprite" plane and the cursor.
2822  */
2823 static int
2824 skl_wm_plane_id(const struct intel_plane *plane)
2825 {
2826         switch (plane->base.type) {
2827         case DRM_PLANE_TYPE_PRIMARY:
2828                 return 0;
2829         case DRM_PLANE_TYPE_CURSOR:
2830                 return PLANE_CURSOR;
2831         case DRM_PLANE_TYPE_OVERLAY:
2832                 return plane->plane + 1;
2833         default:
2834                 MISSING_CASE(plane->base.type);
2835                 return plane->plane;
2836         }
2837 }
2838
2839 static void
2840 skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
2841                                    const struct intel_crtc_state *cstate,
2842                                    const struct intel_wm_config *config,
2843                                    struct skl_ddb_entry *alloc /* out */)
2844 {
2845         struct drm_crtc *for_crtc = cstate->base.crtc;
2846         struct drm_crtc *crtc;
2847         unsigned int pipe_size, ddb_size;
2848         int nth_active_pipe;
2849
2850         if (!cstate->base.active) {
2851                 alloc->start = 0;
2852                 alloc->end = 0;
2853                 return;
2854         }
2855
2856         if (IS_BROXTON(dev))
2857                 ddb_size = BXT_DDB_SIZE;
2858         else
2859                 ddb_size = SKL_DDB_SIZE;
2860
2861         ddb_size -= 4; /* 4 blocks for bypass path allocation */
2862
2863         nth_active_pipe = 0;
2864         for_each_crtc(dev, crtc) {
2865                 if (!to_intel_crtc(crtc)->active)
2866                         continue;
2867
2868                 if (crtc == for_crtc)
2869                         break;
2870
2871                 nth_active_pipe++;
2872         }
2873
2874         pipe_size = ddb_size / config->num_pipes_active;
2875         alloc->start = nth_active_pipe * ddb_size / config->num_pipes_active;
2876         alloc->end = alloc->start + pipe_size;
2877 }
2878
2879 static unsigned int skl_cursor_allocation(const struct intel_wm_config *config)
2880 {
2881         if (config->num_pipes_active == 1)
2882                 return 32;
2883
2884         return 8;
2885 }
2886
2887 static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
2888 {
2889         entry->start = reg & 0x3ff;
2890         entry->end = (reg >> 16) & 0x3ff;
2891         if (entry->end)
2892                 entry->end += 1;
2893 }
2894
2895 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2896                           struct skl_ddb_allocation *ddb /* out */)
2897 {
2898         enum pipe pipe;
2899         int plane;
2900         u32 val;
2901
2902         memset(ddb, 0, sizeof(*ddb));
2903
2904         for_each_pipe(dev_priv, pipe) {
2905                 enum intel_display_power_domain power_domain;
2906
2907                 power_domain = POWER_DOMAIN_PIPE(pipe);
2908                 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
2909                         continue;
2910
2911                 for_each_plane(dev_priv, pipe, plane) {
2912                         val = I915_READ(PLANE_BUF_CFG(pipe, plane));
2913                         skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
2914                                                    val);
2915                 }
2916
2917                 val = I915_READ(CUR_BUF_CFG(pipe));
2918                 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR],
2919                                            val);
2920
2921                 intel_display_power_put(dev_priv, power_domain);
2922         }
2923 }
2924
2925 static unsigned int
2926 skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
2927                              const struct drm_plane_state *pstate,
2928                              int y)
2929 {
2930         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
2931         struct drm_framebuffer *fb = pstate->fb;
2932
2933         /* for planar format */
2934         if (fb->pixel_format == DRM_FORMAT_NV12) {
2935                 if (y)  /* y-plane data rate */
2936                         return intel_crtc->config->pipe_src_w *
2937                                 intel_crtc->config->pipe_src_h *
2938                                 drm_format_plane_cpp(fb->pixel_format, 0);
2939                 else    /* uv-plane data rate */
2940                         return (intel_crtc->config->pipe_src_w/2) *
2941                                 (intel_crtc->config->pipe_src_h/2) *
2942                                 drm_format_plane_cpp(fb->pixel_format, 1);
2943         }
2944
2945         /* for packed formats */
2946         return intel_crtc->config->pipe_src_w *
2947                 intel_crtc->config->pipe_src_h *
2948                 drm_format_plane_cpp(fb->pixel_format, 0);
2949 }
2950
2951 /*
2952  * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
2953  * a 8192x4096@32bpp framebuffer:
2954  *   3 * 4096 * 8192  * 4 < 2^32
2955  */
2956 static unsigned int
2957 skl_get_total_relative_data_rate(const struct intel_crtc_state *cstate)
2958 {
2959         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
2960         struct drm_device *dev = intel_crtc->base.dev;
2961         const struct intel_plane *intel_plane;
2962         unsigned int total_data_rate = 0;
2963
2964         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2965                 const struct drm_plane_state *pstate = intel_plane->base.state;
2966
2967                 if (pstate->fb == NULL)
2968                         continue;
2969
2970                 if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
2971                         continue;
2972
2973                 /* packed/uv */
2974                 total_data_rate += skl_plane_relative_data_rate(cstate,
2975                                                                 pstate,
2976                                                                 0);
2977
2978                 if (pstate->fb->pixel_format == DRM_FORMAT_NV12)
2979                         /* y-plane */
2980                         total_data_rate += skl_plane_relative_data_rate(cstate,
2981                                                                         pstate,
2982                                                                         1);
2983         }
2984
2985         return total_data_rate;
2986 }
2987
2988 static void
2989 skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
2990                       struct skl_ddb_allocation *ddb /* out */)
2991 {
2992         struct drm_crtc *crtc = cstate->base.crtc;
2993         struct drm_device *dev = crtc->dev;
2994         struct drm_i915_private *dev_priv = to_i915(dev);
2995         struct intel_wm_config *config = &dev_priv->wm.config;
2996         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2997         struct intel_plane *intel_plane;
2998         enum pipe pipe = intel_crtc->pipe;
2999         struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
3000         uint16_t alloc_size, start, cursor_blocks;
3001         uint16_t minimum[I915_MAX_PLANES];
3002         uint16_t y_minimum[I915_MAX_PLANES];
3003         unsigned int total_data_rate;
3004
3005         skl_ddb_get_pipe_allocation_limits(dev, cstate, config, alloc);
3006         alloc_size = skl_ddb_entry_size(alloc);
3007         if (alloc_size == 0) {
3008                 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
3009                 memset(&ddb->plane[pipe][PLANE_CURSOR], 0,
3010                        sizeof(ddb->plane[pipe][PLANE_CURSOR]));
3011                 return;
3012         }
3013
3014         cursor_blocks = skl_cursor_allocation(config);
3015         ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - cursor_blocks;
3016         ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
3017
3018         alloc_size -= cursor_blocks;
3019         alloc->end -= cursor_blocks;
3020
3021         /* 1. Allocate the mininum required blocks for each active plane */
3022         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3023                 struct drm_plane *plane = &intel_plane->base;
3024                 struct drm_framebuffer *fb = plane->state->fb;
3025                 int id = skl_wm_plane_id(intel_plane);
3026
3027                 if (fb == NULL)
3028                         continue;
3029                 if (plane->type == DRM_PLANE_TYPE_CURSOR)
3030                         continue;
3031
3032                 minimum[id] = 8;
3033                 alloc_size -= minimum[id];
3034                 y_minimum[id] = (fb->pixel_format == DRM_FORMAT_NV12) ? 8 : 0;
3035                 alloc_size -= y_minimum[id];
3036         }
3037
3038         /*
3039          * 2. Distribute the remaining space in proportion to the amount of
3040          * data each plane needs to fetch from memory.
3041          *
3042          * FIXME: we may not allocate every single block here.
3043          */
3044         total_data_rate = skl_get_total_relative_data_rate(cstate);
3045
3046         start = alloc->start;
3047         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3048                 struct drm_plane *plane = &intel_plane->base;
3049                 struct drm_plane_state *pstate = intel_plane->base.state;
3050                 unsigned int data_rate, y_data_rate;
3051                 uint16_t plane_blocks, y_plane_blocks = 0;
3052                 int id = skl_wm_plane_id(intel_plane);
3053
3054                 if (pstate->fb == NULL)
3055                         continue;
3056                 if (plane->type == DRM_PLANE_TYPE_CURSOR)
3057                         continue;
3058
3059                 data_rate = skl_plane_relative_data_rate(cstate, pstate, 0);
3060
3061                 /*
3062                  * allocation for (packed formats) or (uv-plane part of planar format):
3063                  * promote the expression to 64 bits to avoid overflowing, the
3064                  * result is < available as data_rate / total_data_rate < 1
3065                  */
3066                 plane_blocks = minimum[id];
3067                 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
3068                                         total_data_rate);
3069
3070                 ddb->plane[pipe][id].start = start;
3071                 ddb->plane[pipe][id].end = start + plane_blocks;
3072
3073                 start += plane_blocks;
3074
3075                 /*
3076                  * allocation for y_plane part of planar format:
3077                  */
3078                 if (pstate->fb->pixel_format == DRM_FORMAT_NV12) {
3079                         y_data_rate = skl_plane_relative_data_rate(cstate,
3080                                                                    pstate,
3081                                                                    1);
3082                         y_plane_blocks = y_minimum[id];
3083                         y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
3084                                                 total_data_rate);
3085
3086                         ddb->y_plane[pipe][id].start = start;
3087                         ddb->y_plane[pipe][id].end = start + y_plane_blocks;
3088
3089                         start += y_plane_blocks;
3090                 }
3091
3092         }
3093
3094 }
3095
3096 static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
3097 {
3098         /* TODO: Take into account the scalers once we support them */
3099         return config->base.adjusted_mode.crtc_clock;
3100 }
3101
3102 /*
3103  * The max latency should be 257 (max the punit can code is 255 and we add 2us
3104  * for the read latency) and cpp should always be <= 8, so that
3105  * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3106  * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3107 */
3108 static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
3109 {
3110         uint32_t wm_intermediate_val, ret;
3111
3112         if (latency == 0)
3113                 return UINT_MAX;
3114
3115         wm_intermediate_val = latency * pixel_rate * cpp / 512;
3116         ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
3117
3118         return ret;
3119 }
3120
3121 static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
3122                                uint32_t horiz_pixels, uint8_t cpp,
3123                                uint64_t tiling, uint32_t latency)
3124 {
3125         uint32_t ret;
3126         uint32_t plane_bytes_per_line, plane_blocks_per_line;
3127         uint32_t wm_intermediate_val;
3128
3129         if (latency == 0)
3130                 return UINT_MAX;
3131
3132         plane_bytes_per_line = horiz_pixels * cpp;
3133
3134         if (tiling == I915_FORMAT_MOD_Y_TILED ||
3135             tiling == I915_FORMAT_MOD_Yf_TILED) {
3136                 plane_bytes_per_line *= 4;
3137                 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3138                 plane_blocks_per_line /= 4;
3139         } else {
3140                 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3141         }
3142
3143         wm_intermediate_val = latency * pixel_rate;
3144         ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
3145                                 plane_blocks_per_line;
3146
3147         return ret;
3148 }
3149
3150 static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb,
3151                                        const struct intel_crtc *intel_crtc)
3152 {
3153         struct drm_device *dev = intel_crtc->base.dev;
3154         struct drm_i915_private *dev_priv = dev->dev_private;
3155         const struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
3156
3157         /*
3158          * If ddb allocation of pipes changed, it may require recalculation of
3159          * watermarks
3160          */
3161         if (memcmp(new_ddb->pipe, cur_ddb->pipe, sizeof(new_ddb->pipe)))
3162                 return true;
3163
3164         return false;
3165 }
3166
3167 static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
3168                                  struct intel_crtc_state *cstate,
3169                                  struct intel_plane *intel_plane,
3170                                  uint16_t ddb_allocation,
3171                                  int level,
3172                                  uint16_t *out_blocks, /* out */
3173                                  uint8_t *out_lines /* out */)
3174 {
3175         struct drm_plane *plane = &intel_plane->base;
3176         struct drm_framebuffer *fb = plane->state->fb;
3177         uint32_t latency = dev_priv->wm.skl_latency[level];
3178         uint32_t method1, method2;
3179         uint32_t plane_bytes_per_line, plane_blocks_per_line;
3180         uint32_t res_blocks, res_lines;
3181         uint32_t selected_result;
3182         uint8_t cpp;
3183
3184         if (latency == 0 || !cstate->base.active || !fb)
3185                 return false;
3186
3187         cpp = drm_format_plane_cpp(fb->pixel_format, 0);
3188         method1 = skl_wm_method1(skl_pipe_pixel_rate(cstate),
3189                                  cpp, latency);
3190         method2 = skl_wm_method2(skl_pipe_pixel_rate(cstate),
3191                                  cstate->base.adjusted_mode.crtc_htotal,
3192                                  cstate->pipe_src_w,
3193                                  cpp, fb->modifier[0],
3194                                  latency);
3195
3196         plane_bytes_per_line = cstate->pipe_src_w * cpp;
3197         plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3198
3199         if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3200             fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
3201                 uint32_t min_scanlines = 4;
3202                 uint32_t y_tile_minimum;
3203                 if (intel_rotation_90_or_270(plane->state->rotation)) {
3204                         int cpp = (fb->pixel_format == DRM_FORMAT_NV12) ?
3205                                 drm_format_plane_cpp(fb->pixel_format, 1) :
3206                                 drm_format_plane_cpp(fb->pixel_format, 0);
3207
3208                         switch (cpp) {
3209                         case 1:
3210                                 min_scanlines = 16;
3211                                 break;
3212                         case 2:
3213                                 min_scanlines = 8;
3214                                 break;
3215                         case 8:
3216                                 WARN(1, "Unsupported pixel depth for rotation");
3217                         }
3218                 }
3219                 y_tile_minimum = plane_blocks_per_line * min_scanlines;
3220                 selected_result = max(method2, y_tile_minimum);
3221         } else {
3222                 if ((ddb_allocation / plane_blocks_per_line) >= 1)
3223                         selected_result = min(method1, method2);
3224                 else
3225                         selected_result = method1;
3226         }
3227
3228         res_blocks = selected_result + 1;
3229         res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
3230
3231         if (level >= 1 && level <= 7) {
3232                 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3233                     fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED)
3234                         res_lines += 4;
3235                 else
3236                         res_blocks++;
3237         }
3238
3239         if (res_blocks >= ddb_allocation || res_lines > 31)
3240                 return false;
3241
3242         *out_blocks = res_blocks;
3243         *out_lines = res_lines;
3244
3245         return true;
3246 }
3247
3248 static void skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3249                                  struct skl_ddb_allocation *ddb,
3250                                  struct intel_crtc_state *cstate,
3251                                  int level,
3252                                  struct skl_wm_level *result)
3253 {
3254         struct drm_device *dev = dev_priv->dev;
3255         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
3256         struct intel_plane *intel_plane;
3257         uint16_t ddb_blocks;
3258         enum pipe pipe = intel_crtc->pipe;
3259
3260         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3261                 int i = skl_wm_plane_id(intel_plane);
3262
3263                 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
3264
3265                 result->plane_en[i] = skl_compute_plane_wm(dev_priv,
3266                                                 cstate,
3267                                                 intel_plane,
3268                                                 ddb_blocks,
3269                                                 level,
3270                                                 &result->plane_res_b[i],
3271                                                 &result->plane_res_l[i]);
3272         }
3273 }
3274
3275 static uint32_t
3276 skl_compute_linetime_wm(struct intel_crtc_state *cstate)
3277 {
3278         if (!cstate->base.active)
3279                 return 0;
3280
3281         if (WARN_ON(skl_pipe_pixel_rate(cstate) == 0))
3282                 return 0;
3283
3284         return DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * 1000,
3285                             skl_pipe_pixel_rate(cstate));
3286 }
3287
3288 static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
3289                                       struct skl_wm_level *trans_wm /* out */)
3290 {
3291         struct drm_crtc *crtc = cstate->base.crtc;
3292         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3293         struct intel_plane *intel_plane;
3294
3295         if (!cstate->base.active)
3296                 return;
3297
3298         /* Until we know more, just disable transition WMs */
3299         for_each_intel_plane_on_crtc(crtc->dev, intel_crtc, intel_plane) {
3300                 int i = skl_wm_plane_id(intel_plane);
3301
3302                 trans_wm->plane_en[i] = false;
3303         }
3304 }
3305
3306 static void skl_compute_pipe_wm(struct intel_crtc_state *cstate,
3307                                 struct skl_ddb_allocation *ddb,
3308                                 struct skl_pipe_wm *pipe_wm)
3309 {
3310         struct drm_device *dev = cstate->base.crtc->dev;
3311         const struct drm_i915_private *dev_priv = dev->dev_private;
3312         int level, max_level = ilk_wm_max_level(dev);
3313
3314         for (level = 0; level <= max_level; level++) {
3315                 skl_compute_wm_level(dev_priv, ddb, cstate,
3316                                      level, &pipe_wm->wm[level]);
3317         }
3318         pipe_wm->linetime = skl_compute_linetime_wm(cstate);
3319
3320         skl_compute_transition_wm(cstate, &pipe_wm->trans_wm);
3321 }
3322
3323 static void skl_compute_wm_results(struct drm_device *dev,
3324                                    struct skl_pipe_wm *p_wm,
3325                                    struct skl_wm_values *r,
3326                                    struct intel_crtc *intel_crtc)
3327 {
3328         int level, max_level = ilk_wm_max_level(dev);
3329         enum pipe pipe = intel_crtc->pipe;
3330         uint32_t temp;
3331         int i;
3332
3333         for (level = 0; level <= max_level; level++) {
3334                 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3335                         temp = 0;
3336
3337                         temp |= p_wm->wm[level].plane_res_l[i] <<
3338                                         PLANE_WM_LINES_SHIFT;
3339                         temp |= p_wm->wm[level].plane_res_b[i];
3340                         if (p_wm->wm[level].plane_en[i])
3341                                 temp |= PLANE_WM_EN;
3342
3343                         r->plane[pipe][i][level] = temp;
3344                 }
3345
3346                 temp = 0;
3347
3348                 temp |= p_wm->wm[level].plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3349                 temp |= p_wm->wm[level].plane_res_b[PLANE_CURSOR];
3350
3351                 if (p_wm->wm[level].plane_en[PLANE_CURSOR])
3352                         temp |= PLANE_WM_EN;
3353
3354                 r->plane[pipe][PLANE_CURSOR][level] = temp;
3355
3356         }
3357
3358         /* transition WMs */
3359         for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3360                 temp = 0;
3361                 temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT;
3362                 temp |= p_wm->trans_wm.plane_res_b[i];
3363                 if (p_wm->trans_wm.plane_en[i])
3364                         temp |= PLANE_WM_EN;
3365
3366                 r->plane_trans[pipe][i] = temp;
3367         }
3368
3369         temp = 0;
3370         temp |= p_wm->trans_wm.plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3371         temp |= p_wm->trans_wm.plane_res_b[PLANE_CURSOR];
3372         if (p_wm->trans_wm.plane_en[PLANE_CURSOR])
3373                 temp |= PLANE_WM_EN;
3374
3375         r->plane_trans[pipe][PLANE_CURSOR] = temp;
3376
3377         r->wm_linetime[pipe] = p_wm->linetime;
3378 }
3379
3380 static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
3381                                 i915_reg_t reg,
3382                                 const struct skl_ddb_entry *entry)
3383 {
3384         if (entry->end)
3385                 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3386         else
3387                 I915_WRITE(reg, 0);
3388 }
3389
3390 static void skl_write_wm_values(struct drm_i915_private *dev_priv,
3391                                 const struct skl_wm_values *new)
3392 {
3393         struct drm_device *dev = dev_priv->dev;
3394         struct intel_crtc *crtc;
3395
3396         for_each_intel_crtc(dev, crtc) {
3397                 int i, level, max_level = ilk_wm_max_level(dev);
3398                 enum pipe pipe = crtc->pipe;
3399
3400                 if (!new->dirty[pipe])
3401                         continue;
3402
3403                 I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]);
3404
3405                 for (level = 0; level <= max_level; level++) {
3406                         for (i = 0; i < intel_num_planes(crtc); i++)
3407                                 I915_WRITE(PLANE_WM(pipe, i, level),
3408                                            new->plane[pipe][i][level]);
3409                         I915_WRITE(CUR_WM(pipe, level),
3410                                    new->plane[pipe][PLANE_CURSOR][level]);
3411                 }
3412                 for (i = 0; i < intel_num_planes(crtc); i++)
3413                         I915_WRITE(PLANE_WM_TRANS(pipe, i),
3414                                    new->plane_trans[pipe][i]);
3415                 I915_WRITE(CUR_WM_TRANS(pipe),
3416                            new->plane_trans[pipe][PLANE_CURSOR]);
3417
3418                 for (i = 0; i < intel_num_planes(crtc); i++) {
3419                         skl_ddb_entry_write(dev_priv,
3420                                             PLANE_BUF_CFG(pipe, i),
3421                                             &new->ddb.plane[pipe][i]);
3422                         skl_ddb_entry_write(dev_priv,
3423                                             PLANE_NV12_BUF_CFG(pipe, i),
3424                                             &new->ddb.y_plane[pipe][i]);
3425                 }
3426
3427                 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
3428                                     &new->ddb.plane[pipe][PLANE_CURSOR]);
3429         }
3430 }
3431
3432 /*
3433  * When setting up a new DDB allocation arrangement, we need to correctly
3434  * sequence the times at which the new allocations for the pipes are taken into
3435  * account or we'll have pipes fetching from space previously allocated to
3436  * another pipe.
3437  *
3438  * Roughly the sequence looks like:
3439  *  1. re-allocate the pipe(s) with the allocation being reduced and not
3440  *     overlapping with a previous light-up pipe (another way to put it is:
3441  *     pipes with their new allocation strickly included into their old ones).
3442  *  2. re-allocate the other pipes that get their allocation reduced
3443  *  3. allocate the pipes having their allocation increased
3444  *
3445  * Steps 1. and 2. are here to take care of the following case:
3446  * - Initially DDB looks like this:
3447  *     |   B    |   C    |
3448  * - enable pipe A.
3449  * - pipe B has a reduced DDB allocation that overlaps with the old pipe C
3450  *   allocation
3451  *     |  A  |  B  |  C  |
3452  *
3453  * We need to sequence the re-allocation: C, B, A (and not B, C, A).
3454  */
3455
3456 static void
3457 skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int pass)
3458 {
3459         int plane;
3460
3461         DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass);
3462
3463         for_each_plane(dev_priv, pipe, plane) {
3464                 I915_WRITE(PLANE_SURF(pipe, plane),
3465                            I915_READ(PLANE_SURF(pipe, plane)));
3466         }
3467         I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3468 }
3469
3470 static bool
3471 skl_ddb_allocation_included(const struct skl_ddb_allocation *old,
3472                             const struct skl_ddb_allocation *new,
3473                             enum pipe pipe)
3474 {
3475         uint16_t old_size, new_size;
3476
3477         old_size = skl_ddb_entry_size(&old->pipe[pipe]);
3478         new_size = skl_ddb_entry_size(&new->pipe[pipe]);
3479
3480         return old_size != new_size &&
3481                new->pipe[pipe].start >= old->pipe[pipe].start &&
3482                new->pipe[pipe].end <= old->pipe[pipe].end;
3483 }
3484
3485 static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
3486                                 struct skl_wm_values *new_values)
3487 {
3488         struct drm_device *dev = dev_priv->dev;
3489         struct skl_ddb_allocation *cur_ddb, *new_ddb;
3490         bool reallocated[I915_MAX_PIPES] = {};
3491         struct intel_crtc *crtc;
3492         enum pipe pipe;
3493
3494         new_ddb = &new_values->ddb;
3495         cur_ddb = &dev_priv->wm.skl_hw.ddb;
3496
3497         /*
3498          * First pass: flush the pipes with the new allocation contained into
3499          * the old space.
3500          *
3501          * We'll wait for the vblank on those pipes to ensure we can safely
3502          * re-allocate the freed space without this pipe fetching from it.
3503          */
3504         for_each_intel_crtc(dev, crtc) {
3505                 if (!crtc->active)
3506                         continue;
3507
3508                 pipe = crtc->pipe;
3509
3510                 if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe))
3511                         continue;
3512
3513                 skl_wm_flush_pipe(dev_priv, pipe, 1);
3514                 intel_wait_for_vblank(dev, pipe);
3515
3516                 reallocated[pipe] = true;
3517         }
3518
3519
3520         /*
3521          * Second pass: flush the pipes that are having their allocation
3522          * reduced, but overlapping with a previous allocation.
3523          *
3524          * Here as well we need to wait for the vblank to make sure the freed
3525          * space is not used anymore.
3526          */
3527         for_each_intel_crtc(dev, crtc) {
3528                 if (!crtc->active)
3529                         continue;
3530
3531                 pipe = crtc->pipe;
3532
3533                 if (reallocated[pipe])
3534                         continue;
3535
3536                 if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) <
3537                     skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {
3538                         skl_wm_flush_pipe(dev_priv, pipe, 2);
3539                         intel_wait_for_vblank(dev, pipe);
3540                         reallocated[pipe] = true;
3541                 }
3542         }
3543
3544         /*
3545          * Third pass: flush the pipes that got more space allocated.
3546          *
3547          * We don't need to actively wait for the update here, next vblank
3548          * will just get more DDB space with the correct WM values.
3549          */
3550         for_each_intel_crtc(dev, crtc) {
3551                 if (!crtc->active)
3552                         continue;
3553
3554                 pipe = crtc->pipe;
3555
3556                 /*
3557                  * At this point, only the pipes more space than before are
3558                  * left to re-allocate.
3559                  */
3560                 if (reallocated[pipe])
3561                         continue;
3562
3563                 skl_wm_flush_pipe(dev_priv, pipe, 3);
3564         }
3565 }
3566
3567 static bool skl_update_pipe_wm(struct drm_crtc *crtc,
3568                                struct skl_ddb_allocation *ddb, /* out */
3569                                struct skl_pipe_wm *pipe_wm /* out */)
3570 {
3571         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3572         struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3573
3574         skl_allocate_pipe_ddb(cstate, ddb);
3575         skl_compute_pipe_wm(cstate, ddb, pipe_wm);
3576
3577         if (!memcmp(&intel_crtc->wm.active.skl, pipe_wm, sizeof(*pipe_wm)))
3578                 return false;
3579
3580         intel_crtc->wm.active.skl = *pipe_wm;
3581
3582         return true;
3583 }
3584
3585 static void skl_update_other_pipe_wm(struct drm_device *dev,
3586                                      struct drm_crtc *crtc,
3587                                      struct skl_wm_values *r)
3588 {
3589         struct intel_crtc *intel_crtc;
3590         struct intel_crtc *this_crtc = to_intel_crtc(crtc);
3591
3592         /*
3593          * If the WM update hasn't changed the allocation for this_crtc (the
3594          * crtc we are currently computing the new WM values for), other
3595          * enabled crtcs will keep the same allocation and we don't need to
3596          * recompute anything for them.
3597          */
3598         if (!skl_ddb_allocation_changed(&r->ddb, this_crtc))
3599                 return;
3600
3601         /*
3602          * Otherwise, because of this_crtc being freshly enabled/disabled, the
3603          * other active pipes need new DDB allocation and WM values.
3604          */
3605         for_each_intel_crtc(dev, intel_crtc) {
3606                 struct skl_pipe_wm pipe_wm = {};
3607                 bool wm_changed;
3608
3609                 if (this_crtc->pipe == intel_crtc->pipe)
3610                         continue;
3611
3612                 if (!intel_crtc->active)
3613                         continue;
3614
3615                 wm_changed = skl_update_pipe_wm(&intel_crtc->base,
3616                                                 &r->ddb, &pipe_wm);
3617
3618                 /*
3619                  * If we end up re-computing the other pipe WM values, it's
3620                  * because it was really needed, so we expect the WM values to
3621                  * be different.
3622                  */
3623                 WARN_ON(!wm_changed);
3624
3625                 skl_compute_wm_results(dev, &pipe_wm, r, intel_crtc);
3626                 r->dirty[intel_crtc->pipe] = true;
3627         }
3628 }
3629
3630 static void skl_clear_wm(struct skl_wm_values *watermarks, enum pipe pipe)
3631 {
3632         watermarks->wm_linetime[pipe] = 0;
3633         memset(watermarks->plane[pipe], 0,
3634                sizeof(uint32_t) * 8 * I915_MAX_PLANES);
3635         memset(watermarks->plane_trans[pipe],
3636                0, sizeof(uint32_t) * I915_MAX_PLANES);
3637         watermarks->plane_trans[pipe][PLANE_CURSOR] = 0;
3638
3639         /* Clear ddb entries for pipe */
3640         memset(&watermarks->ddb.pipe[pipe], 0, sizeof(struct skl_ddb_entry));
3641         memset(&watermarks->ddb.plane[pipe], 0,
3642                sizeof(struct skl_ddb_entry) * I915_MAX_PLANES);
3643         memset(&watermarks->ddb.y_plane[pipe], 0,
3644                sizeof(struct skl_ddb_entry) * I915_MAX_PLANES);
3645         memset(&watermarks->ddb.plane[pipe][PLANE_CURSOR], 0,
3646                sizeof(struct skl_ddb_entry));
3647
3648 }
3649
3650 static void skl_update_wm(struct drm_crtc *crtc)
3651 {
3652         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3653         struct drm_device *dev = crtc->dev;
3654         struct drm_i915_private *dev_priv = dev->dev_private;
3655         struct skl_wm_values *results = &dev_priv->wm.skl_results;
3656         struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3657         struct skl_pipe_wm *pipe_wm = &cstate->wm.optimal.skl;
3658
3659
3660         /* Clear all dirty flags */
3661         memset(results->dirty, 0, sizeof(bool) * I915_MAX_PIPES);
3662
3663         skl_clear_wm(results, intel_crtc->pipe);
3664
3665         if (!skl_update_pipe_wm(crtc, &results->ddb, pipe_wm))
3666                 return;
3667
3668         skl_compute_wm_results(dev, pipe_wm, results, intel_crtc);
3669         results->dirty[intel_crtc->pipe] = true;
3670
3671         skl_update_other_pipe_wm(dev, crtc, results);
3672         skl_write_wm_values(dev_priv, results);
3673         skl_flush_wm_values(dev_priv, results);
3674
3675         /* store the new configuration */
3676         dev_priv->wm.skl_hw = *results;
3677 }
3678
3679 static void ilk_compute_wm_config(struct drm_device *dev,
3680                                   struct intel_wm_config *config)
3681 {
3682         struct intel_crtc *crtc;
3683
3684         /* Compute the currently _active_ config */
3685         for_each_intel_crtc(dev, crtc) {
3686                 const struct intel_pipe_wm *wm = &crtc->wm.active.ilk;
3687
3688                 if (!wm->pipe_enabled)
3689                         continue;
3690
3691                 config->sprites_enabled |= wm->sprites_enabled;
3692                 config->sprites_scaled |= wm->sprites_scaled;
3693                 config->num_pipes_active++;
3694         }
3695 }
3696
3697 static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
3698 {
3699         struct drm_device *dev = dev_priv->dev;
3700         struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
3701         struct ilk_wm_maximums max;
3702         struct intel_wm_config config = {};
3703         struct ilk_wm_values results = {};
3704         enum intel_ddb_partitioning partitioning;
3705
3706         ilk_compute_wm_config(dev, &config);
3707
3708         ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
3709         ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
3710
3711         /* 5/6 split only in single pipe config on IVB+ */
3712         if (INTEL_INFO(dev)->gen >= 7 &&
3713             config.num_pipes_active == 1 && config.sprites_enabled) {
3714                 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
3715                 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
3716
3717                 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
3718         } else {
3719                 best_lp_wm = &lp_wm_1_2;
3720         }
3721
3722         partitioning = (best_lp_wm == &lp_wm_1_2) ?
3723                        INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
3724
3725         ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
3726
3727         ilk_write_wm_values(dev_priv, &results);
3728 }
3729
3730 static void ilk_initial_watermarks(struct intel_crtc_state *cstate)
3731 {
3732         struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
3733         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
3734
3735         mutex_lock(&dev_priv->wm.wm_mutex);
3736         intel_crtc->wm.active.ilk = cstate->wm.intermediate;
3737         ilk_program_watermarks(dev_priv);
3738         mutex_unlock(&dev_priv->wm.wm_mutex);
3739 }
3740
3741 static void ilk_optimize_watermarks(struct intel_crtc_state *cstate)
3742 {
3743         struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
3744         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
3745
3746         mutex_lock(&dev_priv->wm.wm_mutex);
3747         if (cstate->wm.need_postvbl_update) {
3748                 intel_crtc->wm.active.ilk = cstate->wm.optimal.ilk;
3749                 ilk_program_watermarks(dev_priv);
3750         }
3751         mutex_unlock(&dev_priv->wm.wm_mutex);
3752 }
3753
3754 static void skl_pipe_wm_active_state(uint32_t val,
3755                                      struct skl_pipe_wm *active,
3756                                      bool is_transwm,
3757                                      bool is_cursor,
3758                                      int i,
3759                                      int level)
3760 {
3761         bool is_enabled = (val & PLANE_WM_EN) != 0;
3762
3763         if (!is_transwm) {
3764                 if (!is_cursor) {
3765                         active->wm[level].plane_en[i] = is_enabled;
3766                         active->wm[level].plane_res_b[i] =
3767                                         val & PLANE_WM_BLOCKS_MASK;
3768                         active->wm[level].plane_res_l[i] =
3769                                         (val >> PLANE_WM_LINES_SHIFT) &
3770                                                 PLANE_WM_LINES_MASK;
3771                 } else {
3772                         active->wm[level].plane_en[PLANE_CURSOR] = is_enabled;
3773                         active->wm[level].plane_res_b[PLANE_CURSOR] =
3774                                         val & PLANE_WM_BLOCKS_MASK;
3775                         active->wm[level].plane_res_l[PLANE_CURSOR] =
3776                                         (val >> PLANE_WM_LINES_SHIFT) &
3777                                                 PLANE_WM_LINES_MASK;
3778                 }
3779         } else {
3780                 if (!is_cursor) {
3781                         active->trans_wm.plane_en[i] = is_enabled;
3782                         active->trans_wm.plane_res_b[i] =
3783                                         val & PLANE_WM_BLOCKS_MASK;
3784                         active->trans_wm.plane_res_l[i] =
3785                                         (val >> PLANE_WM_LINES_SHIFT) &
3786                                                 PLANE_WM_LINES_MASK;
3787                 } else {
3788                         active->trans_wm.plane_en[PLANE_CURSOR] = is_enabled;
3789                         active->trans_wm.plane_res_b[PLANE_CURSOR] =
3790                                         val & PLANE_WM_BLOCKS_MASK;
3791                         active->trans_wm.plane_res_l[PLANE_CURSOR] =
3792                                         (val >> PLANE_WM_LINES_SHIFT) &
3793                                                 PLANE_WM_LINES_MASK;
3794                 }
3795         }
3796 }
3797
3798 static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3799 {
3800         struct drm_device *dev = crtc->dev;
3801         struct drm_i915_private *dev_priv = dev->dev_private;
3802         struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
3803         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3804         struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3805         struct skl_pipe_wm *active = &cstate->wm.optimal.skl;
3806         enum pipe pipe = intel_crtc->pipe;
3807         int level, i, max_level;
3808         uint32_t temp;
3809
3810         max_level = ilk_wm_max_level(dev);
3811
3812         hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3813
3814         for (level = 0; level <= max_level; level++) {
3815                 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3816                         hw->plane[pipe][i][level] =
3817                                         I915_READ(PLANE_WM(pipe, i, level));
3818                 hw->plane[pipe][PLANE_CURSOR][level] = I915_READ(CUR_WM(pipe, level));
3819         }
3820
3821         for (i = 0; i < intel_num_planes(intel_crtc); i++)
3822                 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
3823         hw->plane_trans[pipe][PLANE_CURSOR] = I915_READ(CUR_WM_TRANS(pipe));
3824
3825         if (!intel_crtc->active)
3826                 return;
3827
3828         hw->dirty[pipe] = true;
3829
3830         active->linetime = hw->wm_linetime[pipe];
3831
3832         for (level = 0; level <= max_level; level++) {
3833                 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3834                         temp = hw->plane[pipe][i][level];
3835                         skl_pipe_wm_active_state(temp, active, false,
3836                                                 false, i, level);
3837                 }
3838                 temp = hw->plane[pipe][PLANE_CURSOR][level];
3839                 skl_pipe_wm_active_state(temp, active, false, true, i, level);
3840         }
3841
3842         for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3843                 temp = hw->plane_trans[pipe][i];
3844                 skl_pipe_wm_active_state(temp, active, true, false, i, 0);
3845         }
3846
3847         temp = hw->plane_trans[pipe][PLANE_CURSOR];
3848         skl_pipe_wm_active_state(temp, active, true, true, i, 0);
3849
3850         intel_crtc->wm.active.skl = *active;
3851 }
3852
3853 void skl_wm_get_hw_state(struct drm_device *dev)
3854 {
3855         struct drm_i915_private *dev_priv = dev->dev_private;
3856         struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
3857         struct drm_crtc *crtc;
3858
3859         skl_ddb_get_hw_state(dev_priv, ddb);
3860         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3861                 skl_pipe_wm_get_hw_state(crtc);
3862 }
3863
3864 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3865 {
3866         struct drm_device *dev = crtc->dev;
3867         struct drm_i915_private *dev_priv = dev->dev_private;
3868         struct ilk_wm_values *hw = &dev_priv->wm.hw;
3869         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3870         struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3871         struct intel_pipe_wm *active = &cstate->wm.optimal.ilk;
3872         enum pipe pipe = intel_crtc->pipe;
3873         static const i915_reg_t wm0_pipe_reg[] = {
3874                 [PIPE_A] = WM0_PIPEA_ILK,
3875                 [PIPE_B] = WM0_PIPEB_ILK,
3876                 [PIPE_C] = WM0_PIPEC_IVB,
3877         };
3878
3879         hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
3880         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3881                 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3882
3883         active->pipe_enabled = intel_crtc->active;
3884
3885         if (active->pipe_enabled) {
3886                 u32 tmp = hw->wm_pipe[pipe];
3887
3888                 /*
3889                  * For active pipes LP0 watermark is marked as
3890                  * enabled, and LP1+ watermaks as disabled since
3891                  * we can't really reverse compute them in case
3892                  * multiple pipes are active.
3893                  */
3894                 active->wm[0].enable = true;
3895                 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
3896                 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
3897                 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
3898                 active->linetime = hw->wm_linetime[pipe];
3899         } else {
3900                 int level, max_level = ilk_wm_max_level(dev);
3901
3902                 /*
3903                  * For inactive pipes, all watermark levels
3904                  * should be marked as enabled but zeroed,
3905                  * which is what we'd compute them to.
3906                  */
3907                 for (level = 0; level <= max_level; level++)
3908                         active->wm[level].enable = true;
3909         }
3910
3911         intel_crtc->wm.active.ilk = *active;
3912 }
3913
3914 #define _FW_WM(value, plane) \
3915         (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
3916 #define _FW_WM_VLV(value, plane) \
3917         (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
3918
3919 static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
3920                                struct vlv_wm_values *wm)
3921 {
3922         enum pipe pipe;
3923         uint32_t tmp;
3924
3925         for_each_pipe(dev_priv, pipe) {
3926                 tmp = I915_READ(VLV_DDL(pipe));
3927
3928                 wm->ddl[pipe].primary =
3929                         (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3930                 wm->ddl[pipe].cursor =
3931                         (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3932                 wm->ddl[pipe].sprite[0] =
3933                         (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3934                 wm->ddl[pipe].sprite[1] =
3935                         (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3936         }
3937
3938         tmp = I915_READ(DSPFW1);
3939         wm->sr.plane = _FW_WM(tmp, SR);
3940         wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB);
3941         wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB);
3942         wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA);
3943
3944         tmp = I915_READ(DSPFW2);
3945         wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB);
3946         wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA);
3947         wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA);
3948
3949         tmp = I915_READ(DSPFW3);
3950         wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
3951
3952         if (IS_CHERRYVIEW(dev_priv)) {
3953                 tmp = I915_READ(DSPFW7_CHV);
3954                 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
3955                 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
3956
3957                 tmp = I915_READ(DSPFW8_CHV);
3958                 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF);
3959                 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE);
3960
3961                 tmp = I915_READ(DSPFW9_CHV);
3962                 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC);
3963                 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC);
3964
3965                 tmp = I915_READ(DSPHOWM);
3966                 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
3967                 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
3968                 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
3969                 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8;
3970                 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
3971                 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
3972                 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
3973                 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
3974                 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
3975                 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
3976         } else {
3977                 tmp = I915_READ(DSPFW7);
3978                 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
3979                 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
3980
3981                 tmp = I915_READ(DSPHOWM);
3982                 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
3983                 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
3984                 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
3985                 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
3986                 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
3987                 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
3988                 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
3989         }
3990 }
3991
3992 #undef _FW_WM
3993 #undef _FW_WM_VLV
3994
3995 void vlv_wm_get_hw_state(struct drm_device *dev)
3996 {
3997         struct drm_i915_private *dev_priv = to_i915(dev);
3998         struct vlv_wm_values *wm = &dev_priv->wm.vlv;
3999         struct intel_plane *plane;
4000         enum pipe pipe;
4001         u32 val;
4002
4003         vlv_read_wm_values(dev_priv, wm);
4004
4005         for_each_intel_plane(dev, plane) {
4006                 switch (plane->base.type) {
4007                         int sprite;
4008                 case DRM_PLANE_TYPE_CURSOR:
4009                         plane->wm.fifo_size = 63;
4010                         break;
4011                 case DRM_PLANE_TYPE_PRIMARY:
4012                         plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0);
4013                         break;
4014                 case DRM_PLANE_TYPE_OVERLAY:
4015                         sprite = plane->plane;
4016                         plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1);
4017                         break;
4018                 }
4019         }
4020
4021         wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4022         wm->level = VLV_WM_LEVEL_PM2;
4023
4024         if (IS_CHERRYVIEW(dev_priv)) {
4025                 mutex_lock(&dev_priv->rps.hw_lock);
4026
4027                 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4028                 if (val & DSP_MAXFIFO_PM5_ENABLE)
4029                         wm->level = VLV_WM_LEVEL_PM5;
4030
4031                 /*
4032                  * If DDR DVFS is disabled in the BIOS, Punit
4033                  * will never ack the request. So if that happens
4034                  * assume we don't have to enable/disable DDR DVFS
4035                  * dynamically. To test that just set the REQ_ACK
4036                  * bit to poke the Punit, but don't change the
4037                  * HIGH/LOW bits so that we don't actually change
4038                  * the current state.
4039                  */
4040                 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4041                 val |= FORCE_DDR_FREQ_REQ_ACK;
4042                 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
4043
4044                 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
4045                               FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
4046                         DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
4047                                       "assuming DDR DVFS is disabled\n");
4048                         dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
4049                 } else {
4050                         val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4051                         if ((val & FORCE_DDR_HIGH_FREQ) == 0)
4052                                 wm->level = VLV_WM_LEVEL_DDR_DVFS;
4053                 }
4054
4055                 mutex_unlock(&dev_priv->rps.hw_lock);
4056         }
4057
4058         for_each_pipe(dev_priv, pipe)
4059                 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4060                               pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor,
4061                               wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]);
4062
4063         DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4064                       wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
4065 }
4066
4067 void ilk_wm_get_hw_state(struct drm_device *dev)
4068 {
4069         struct drm_i915_private *dev_priv = dev->dev_private;
4070         struct ilk_wm_values *hw = &dev_priv->wm.hw;
4071         struct drm_crtc *crtc;
4072
4073         for_each_crtc(dev, crtc)
4074                 ilk_pipe_wm_get_hw_state(crtc);
4075
4076         hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
4077         hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
4078         hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
4079
4080         hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
4081         if (INTEL_INFO(dev)->gen >= 7) {
4082                 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
4083                 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
4084         }
4085
4086         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4087                 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
4088                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4089         else if (IS_IVYBRIDGE(dev))
4090                 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
4091                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4092
4093         hw->enable_fbc_wm =
4094                 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
4095 }
4096
4097 /**
4098  * intel_update_watermarks - update FIFO watermark values based on current modes
4099  *
4100  * Calculate watermark values for the various WM regs based on current mode
4101  * and plane configuration.
4102  *
4103  * There are several cases to deal with here:
4104  *   - normal (i.e. non-self-refresh)
4105  *   - self-refresh (SR) mode
4106  *   - lines are large relative to FIFO size (buffer can hold up to 2)
4107  *   - lines are small relative to FIFO size (buffer can hold more than 2
4108  *     lines), so need to account for TLB latency
4109  *
4110  *   The normal calculation is:
4111  *     watermark = dotclock * bytes per pixel * latency
4112  *   where latency is platform & configuration dependent (we assume pessimal
4113  *   values here).
4114  *
4115  *   The SR calculation is:
4116  *     watermark = (trunc(latency/line time)+1) * surface width *
4117  *       bytes per pixel
4118  *   where
4119  *     line time = htotal / dotclock
4120  *     surface width = hdisplay for normal plane and 64 for cursor
4121  *   and latency is assumed to be high, as above.
4122  *
4123  * The final value programmed to the register should always be rounded up,
4124  * and include an extra 2 entries to account for clock crossings.
4125  *
4126  * We don't use the sprite, so we can ignore that.  And on Crestline we have
4127  * to set the non-SR watermarks to 8.
4128  */
4129 void intel_update_watermarks(struct drm_crtc *crtc)
4130 {
4131         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
4132
4133         if (dev_priv->display.update_wm)
4134                 dev_priv->display.update_wm(crtc);
4135 }
4136
4137 /*
4138  * Lock protecting IPS related data structures
4139  */
4140 DEFINE_SPINLOCK(mchdev_lock);
4141
4142 /* Global for IPS driver to get at the current i915 device. Protected by
4143  * mchdev_lock. */
4144 static struct drm_i915_private *i915_mch_dev;
4145
4146 bool ironlake_set_drps(struct drm_device *dev, u8 val)
4147 {
4148         struct drm_i915_private *dev_priv = dev->dev_private;
4149         u16 rgvswctl;
4150
4151         assert_spin_locked(&mchdev_lock);
4152
4153         rgvswctl = I915_READ16(MEMSWCTL);
4154         if (rgvswctl & MEMCTL_CMD_STS) {
4155                 DRM_DEBUG("gpu busy, RCS change rejected\n");
4156                 return false; /* still busy with another command */
4157         }
4158
4159         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4160                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4161         I915_WRITE16(MEMSWCTL, rgvswctl);
4162         POSTING_READ16(MEMSWCTL);
4163
4164         rgvswctl |= MEMCTL_CMD_STS;
4165         I915_WRITE16(MEMSWCTL, rgvswctl);
4166
4167         return true;
4168 }
4169
4170 static void ironlake_enable_drps(struct drm_device *dev)
4171 {
4172         struct drm_i915_private *dev_priv = dev->dev_private;
4173         u32 rgvmodectl;
4174         u8 fmax, fmin, fstart, vstart;
4175
4176         spin_lock_irq(&mchdev_lock);
4177
4178         rgvmodectl = I915_READ(MEMMODECTL);
4179
4180         /* Enable temp reporting */
4181         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4182         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4183
4184         /* 100ms RC evaluation intervals */
4185         I915_WRITE(RCUPEI, 100000);
4186         I915_WRITE(RCDNEI, 100000);
4187
4188         /* Set max/min thresholds to 90ms and 80ms respectively */
4189         I915_WRITE(RCBMAXAVG, 90000);
4190         I915_WRITE(RCBMINAVG, 80000);
4191
4192         I915_WRITE(MEMIHYST, 1);
4193
4194         /* Set up min, max, and cur for interrupt handling */
4195         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4196         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4197         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4198                 MEMMODE_FSTART_SHIFT;
4199
4200         vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
4201                 PXVFREQ_PX_SHIFT;
4202
4203         dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4204         dev_priv->ips.fstart = fstart;
4205
4206         dev_priv->ips.max_delay = fstart;
4207         dev_priv->ips.min_delay = fmin;
4208         dev_priv->ips.cur_delay = fstart;
4209
4210         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4211                          fmax, fmin, fstart);
4212
4213         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4214
4215         /*
4216          * Interrupts will be enabled in ironlake_irq_postinstall
4217          */
4218
4219         I915_WRITE(VIDSTART, vstart);
4220         POSTING_READ(VIDSTART);
4221
4222         rgvmodectl |= MEMMODE_SWMODE_EN;
4223         I915_WRITE(MEMMODECTL, rgvmodectl);
4224
4225         if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
4226                 DRM_ERROR("stuck trying to change perf mode\n");
4227         mdelay(1);
4228
4229         ironlake_set_drps(dev, fstart);
4230
4231         dev_priv->ips.last_count1 = I915_READ(DMIEC) +
4232                 I915_READ(DDREC) + I915_READ(CSIEC);
4233         dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
4234         dev_priv->ips.last_count2 = I915_READ(GFXEC);
4235         dev_priv->ips.last_time2 = ktime_get_raw_ns();
4236
4237         spin_unlock_irq(&mchdev_lock);
4238 }
4239
4240 static void ironlake_disable_drps(struct drm_device *dev)
4241 {
4242         struct drm_i915_private *dev_priv = dev->dev_private;
4243         u16 rgvswctl;
4244
4245         spin_lock_irq(&mchdev_lock);
4246
4247         rgvswctl = I915_READ16(MEMSWCTL);
4248
4249         /* Ack interrupts, disable EFC interrupt */
4250         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4251         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4252         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4253         I915_WRITE(DEIIR, DE_PCU_EVENT);
4254         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4255
4256         /* Go back to the starting frequency */
4257         ironlake_set_drps(dev, dev_priv->ips.fstart);
4258         mdelay(1);
4259         rgvswctl |= MEMCTL_CMD_STS;
4260         I915_WRITE(MEMSWCTL, rgvswctl);
4261         mdelay(1);
4262
4263         spin_unlock_irq(&mchdev_lock);
4264 }
4265
4266 /* There's a funny hw issue where the hw returns all 0 when reading from
4267  * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4268  * ourselves, instead of doing a rmw cycle (which might result in us clearing
4269  * all limits and the gpu stuck at whatever frequency it is at atm).
4270  */
4271 static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
4272 {
4273         u32 limits;
4274
4275         /* Only set the down limit when we've reached the lowest level to avoid
4276          * getting more interrupts, otherwise leave this clear. This prevents a
4277          * race in the hw when coming out of rc6: There's a tiny window where
4278          * the hw runs at the minimal clock before selecting the desired
4279          * frequency, if the down threshold expires in that window we will not
4280          * receive a down interrupt. */
4281         if (IS_GEN9(dev_priv->dev)) {
4282                 limits = (dev_priv->rps.max_freq_softlimit) << 23;
4283                 if (val <= dev_priv->rps.min_freq_softlimit)
4284                         limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4285         } else {
4286                 limits = dev_priv->rps.max_freq_softlimit << 24;
4287                 if (val <= dev_priv->rps.min_freq_softlimit)
4288                         limits |= dev_priv->rps.min_freq_softlimit << 16;
4289         }
4290
4291         return limits;
4292 }
4293
4294 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4295 {
4296         int new_power;
4297         u32 threshold_up = 0, threshold_down = 0; /* in % */
4298         u32 ei_up = 0, ei_down = 0;
4299
4300         new_power = dev_priv->rps.power;
4301         switch (dev_priv->rps.power) {
4302         case LOW_POWER:
4303                 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
4304                         new_power = BETWEEN;
4305                 break;
4306
4307         case BETWEEN:
4308                 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
4309                         new_power = LOW_POWER;
4310                 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
4311                         new_power = HIGH_POWER;
4312                 break;
4313
4314         case HIGH_POWER:
4315                 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
4316                         new_power = BETWEEN;
4317                 break;
4318         }
4319         /* Max/min bins are special */
4320         if (val <= dev_priv->rps.min_freq_softlimit)
4321                 new_power = LOW_POWER;
4322         if (val >= dev_priv->rps.max_freq_softlimit)
4323                 new_power = HIGH_POWER;
4324         if (new_power == dev_priv->rps.power)
4325                 return;
4326
4327         /* Note the units here are not exactly 1us, but 1280ns. */
4328         switch (new_power) {
4329         case LOW_POWER:
4330                 /* Upclock if more than 95% busy over 16ms */
4331                 ei_up = 16000;
4332                 threshold_up = 95;
4333
4334                 /* Downclock if less than 85% busy over 32ms */
4335                 ei_down = 32000;
4336                 threshold_down = 85;
4337                 break;
4338
4339         case BETWEEN:
4340                 /* Upclock if more than 90% busy over 13ms */
4341                 ei_up = 13000;
4342                 threshold_up = 90;
4343
4344                 /* Downclock if less than 75% busy over 32ms */
4345                 ei_down = 32000;
4346                 threshold_down = 75;
4347                 break;
4348
4349         case HIGH_POWER:
4350                 /* Upclock if more than 85% busy over 10ms */
4351                 ei_up = 10000;
4352                 threshold_up = 85;
4353
4354                 /* Downclock if less than 60% busy over 32ms */
4355                 ei_down = 32000;
4356                 threshold_down = 60;
4357                 break;
4358         }
4359
4360         I915_WRITE(GEN6_RP_UP_EI,
4361                 GT_INTERVAL_FROM_US(dev_priv, ei_up));
4362         I915_WRITE(GEN6_RP_UP_THRESHOLD,
4363                 GT_INTERVAL_FROM_US(dev_priv, (ei_up * threshold_up / 100)));
4364
4365         I915_WRITE(GEN6_RP_DOWN_EI,
4366                 GT_INTERVAL_FROM_US(dev_priv, ei_down));
4367         I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
4368                 GT_INTERVAL_FROM_US(dev_priv, (ei_down * threshold_down / 100)));
4369
4370          I915_WRITE(GEN6_RP_CONTROL,
4371                     GEN6_RP_MEDIA_TURBO |
4372                     GEN6_RP_MEDIA_HW_NORMAL_MODE |
4373                     GEN6_RP_MEDIA_IS_GFX |
4374                     GEN6_RP_ENABLE |
4375                     GEN6_RP_UP_BUSY_AVG |
4376                     GEN6_RP_DOWN_IDLE_AVG);
4377
4378         dev_priv->rps.power = new_power;
4379         dev_priv->rps.up_threshold = threshold_up;
4380         dev_priv->rps.down_threshold = threshold_down;
4381         dev_priv->rps.last_adj = 0;
4382 }
4383
4384 static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4385 {
4386         u32 mask = 0;
4387
4388         if (val > dev_priv->rps.min_freq_softlimit)
4389                 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
4390         if (val < dev_priv->rps.max_freq_softlimit)
4391                 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
4392
4393         mask &= dev_priv->pm_rps_events;
4394
4395         return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
4396 }
4397
4398 /* gen6_set_rps is called to update the frequency request, but should also be
4399  * called when the range (min_delay and max_delay) is modified so that we can
4400  * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
4401 static void gen6_set_rps(struct drm_device *dev, u8 val)
4402 {
4403         struct drm_i915_private *dev_priv = dev->dev_private;
4404
4405         /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
4406         if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
4407                 return;
4408
4409         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4410         WARN_ON(val > dev_priv->rps.max_freq);
4411         WARN_ON(val < dev_priv->rps.min_freq);
4412
4413         /* min/max delay may still have been modified so be sure to
4414          * write the limits value.
4415          */
4416         if (val != dev_priv->rps.cur_freq) {
4417                 gen6_set_rps_thresholds(dev_priv, val);
4418
4419                 if (IS_GEN9(dev))
4420                         I915_WRITE(GEN6_RPNSWREQ,
4421                                    GEN9_FREQUENCY(val));
4422                 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4423                         I915_WRITE(GEN6_RPNSWREQ,
4424                                    HSW_FREQUENCY(val));
4425                 else
4426                         I915_WRITE(GEN6_RPNSWREQ,
4427                                    GEN6_FREQUENCY(val) |
4428                                    GEN6_OFFSET(0) |
4429                                    GEN6_AGGRESSIVE_TURBO);
4430         }
4431
4432         /* Make sure we continue to get interrupts
4433          * until we hit the minimum or maximum frequencies.
4434          */
4435         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
4436         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4437
4438         POSTING_READ(GEN6_RPNSWREQ);
4439
4440         dev_priv->rps.cur_freq = val;
4441         trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4442 }
4443
4444 static void valleyview_set_rps(struct drm_device *dev, u8 val)
4445 {
4446         struct drm_i915_private *dev_priv = dev->dev_private;
4447
4448         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4449         WARN_ON(val > dev_priv->rps.max_freq);
4450         WARN_ON(val < dev_priv->rps.min_freq);
4451
4452         if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1),
4453                       "Odd GPU freq value\n"))
4454                 val &= ~1;
4455
4456         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4457
4458         if (val != dev_priv->rps.cur_freq) {
4459                 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
4460                 if (!IS_CHERRYVIEW(dev_priv))
4461                         gen6_set_rps_thresholds(dev_priv, val);
4462         }
4463
4464         dev_priv->rps.cur_freq = val;
4465         trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4466 }
4467
4468 /* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
4469  *
4470  * * If Gfx is Idle, then
4471  * 1. Forcewake Media well.
4472  * 2. Request idle freq.
4473  * 3. Release Forcewake of Media well.
4474 */
4475 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
4476 {
4477         u32 val = dev_priv->rps.idle_freq;
4478
4479         if (dev_priv->rps.cur_freq <= val)
4480                 return;
4481
4482         /* Wake up the media well, as that takes a lot less
4483          * power than the Render well. */
4484         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
4485         valleyview_set_rps(dev_priv->dev, val);
4486         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
4487 }
4488
4489 void gen6_rps_busy(struct drm_i915_private *dev_priv)
4490 {
4491         mutex_lock(&dev_priv->rps.hw_lock);
4492         if (dev_priv->rps.enabled) {
4493                 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
4494                         gen6_rps_reset_ei(dev_priv);
4495                 I915_WRITE(GEN6_PMINTRMSK,
4496                            gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
4497         }
4498         mutex_unlock(&dev_priv->rps.hw_lock);
4499 }
4500
4501 void gen6_rps_idle(struct drm_i915_private *dev_priv)
4502 {
4503         struct drm_device *dev = dev_priv->dev;
4504
4505         mutex_lock(&dev_priv->rps.hw_lock);
4506         if (dev_priv->rps.enabled) {
4507                 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
4508                         vlv_set_rps_idle(dev_priv);
4509                 else
4510                         gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
4511                 dev_priv->rps.last_adj = 0;
4512                 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
4513         }
4514         mutex_unlock(&dev_priv->rps.hw_lock);
4515
4516         spin_lock(&dev_priv->rps.client_lock);
4517         while (!list_empty(&dev_priv->rps.clients))
4518                 list_del_init(dev_priv->rps.clients.next);
4519         spin_unlock(&dev_priv->rps.client_lock);
4520 }
4521
4522 void gen6_rps_boost(struct drm_i915_private *dev_priv,
4523                     struct intel_rps_client *rps,
4524                     unsigned long submitted)
4525 {
4526         /* This is intentionally racy! We peek at the state here, then
4527          * validate inside the RPS worker.
4528          */
4529         if (!(dev_priv->mm.busy &&
4530               dev_priv->rps.enabled &&
4531               dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit))
4532                 return;
4533
4534         /* Force a RPS boost (and don't count it against the client) if
4535          * the GPU is severely congested.
4536          */
4537         if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
4538                 rps = NULL;
4539
4540         spin_lock(&dev_priv->rps.client_lock);
4541         if (rps == NULL || list_empty(&rps->link)) {
4542                 spin_lock_irq(&dev_priv->irq_lock);
4543                 if (dev_priv->rps.interrupts_enabled) {
4544                         dev_priv->rps.client_boost = true;
4545                         queue_work(dev_priv->wq, &dev_priv->rps.work);
4546                 }
4547                 spin_unlock_irq(&dev_priv->irq_lock);
4548
4549                 if (rps != NULL) {
4550                         list_add(&rps->link, &dev_priv->rps.clients);
4551                         rps->boosts++;
4552                 } else
4553                         dev_priv->rps.boosts++;
4554         }
4555         spin_unlock(&dev_priv->rps.client_lock);
4556 }
4557
4558 void intel_set_rps(struct drm_device *dev, u8 val)
4559 {
4560         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
4561                 valleyview_set_rps(dev, val);
4562         else
4563                 gen6_set_rps(dev, val);
4564 }
4565
4566 static void gen9_disable_rps(struct drm_device *dev)
4567 {
4568         struct drm_i915_private *dev_priv = dev->dev_private;
4569
4570         I915_WRITE(GEN6_RC_CONTROL, 0);
4571         I915_WRITE(GEN9_PG_ENABLE, 0);
4572 }
4573
4574 static void gen6_disable_rps(struct drm_device *dev)
4575 {
4576         struct drm_i915_private *dev_priv = dev->dev_private;
4577
4578         I915_WRITE(GEN6_RC_CONTROL, 0);
4579         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
4580 }
4581
4582 static void cherryview_disable_rps(struct drm_device *dev)
4583 {
4584         struct drm_i915_private *dev_priv = dev->dev_private;
4585
4586         I915_WRITE(GEN6_RC_CONTROL, 0);
4587 }
4588
4589 static void valleyview_disable_rps(struct drm_device *dev)
4590 {
4591         struct drm_i915_private *dev_priv = dev->dev_private;
4592
4593         /* we're doing forcewake before Disabling RC6,
4594          * This what the BIOS expects when going into suspend */
4595         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4596
4597         I915_WRITE(GEN6_RC_CONTROL, 0);
4598
4599         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4600 }
4601
4602 static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
4603 {
4604         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
4605                 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
4606                         mode = GEN6_RC_CTL_RC6_ENABLE;
4607                 else
4608                         mode = 0;
4609         }
4610         if (HAS_RC6p(dev))
4611                 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n",
4612                               onoff(mode & GEN6_RC_CTL_RC6_ENABLE),
4613                               onoff(mode & GEN6_RC_CTL_RC6p_ENABLE),
4614                               onoff(mode & GEN6_RC_CTL_RC6pp_ENABLE));
4615
4616         else
4617                 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n",
4618                               onoff(mode & GEN6_RC_CTL_RC6_ENABLE));
4619 }
4620
4621 static bool bxt_check_bios_rc6_setup(const struct drm_device *dev)
4622 {
4623         struct drm_i915_private *dev_priv = dev->dev_private;
4624         bool enable_rc6 = true;
4625         unsigned long rc6_ctx_base;
4626
4627         if (!(I915_READ(RC6_LOCATION) & RC6_CTX_IN_DRAM)) {
4628                 DRM_DEBUG_KMS("RC6 Base location not set properly.\n");
4629                 enable_rc6 = false;
4630         }
4631
4632         /*
4633          * The exact context size is not known for BXT, so assume a page size
4634          * for this check.
4635          */
4636         rc6_ctx_base = I915_READ(RC6_CTX_BASE) & RC6_CTX_BASE_MASK;
4637         if (!((rc6_ctx_base >= dev_priv->gtt.stolen_reserved_base) &&
4638               (rc6_ctx_base + PAGE_SIZE <= dev_priv->gtt.stolen_reserved_base +
4639                                         dev_priv->gtt.stolen_reserved_size))) {
4640                 DRM_DEBUG_KMS("RC6 Base address not as expected.\n");
4641                 enable_rc6 = false;
4642         }
4643
4644         if (!(((I915_READ(PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1) &&
4645               ((I915_READ(PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1) &&
4646               ((I915_READ(PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1) &&
4647               ((I915_READ(PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1))) {
4648                 DRM_DEBUG_KMS("Engine Idle wait time not set properly.\n");
4649                 enable_rc6 = false;
4650         }
4651
4652         if (!(I915_READ(GEN6_RC_CONTROL) & (GEN6_RC_CTL_RC6_ENABLE |
4653                                             GEN6_RC_CTL_HW_ENABLE)) &&
4654             ((I915_READ(GEN6_RC_CONTROL) & GEN6_RC_CTL_HW_ENABLE) ||
4655              !(I915_READ(GEN6_RC_STATE) & RC6_STATE))) {
4656                 DRM_DEBUG_KMS("HW/SW RC6 is not enabled by BIOS.\n");
4657                 enable_rc6 = false;
4658         }
4659
4660         return enable_rc6;
4661 }
4662
4663 int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
4664 {
4665         /* No RC6 before Ironlake and code is gone for ilk. */
4666         if (INTEL_INFO(dev)->gen < 6)
4667                 return 0;
4668
4669         if (!enable_rc6)
4670                 return 0;
4671
4672         if (IS_BROXTON(dev) && !bxt_check_bios_rc6_setup(dev)) {
4673                 DRM_INFO("RC6 disabled by BIOS\n");
4674                 return 0;
4675         }
4676
4677         /* Respect the kernel parameter if it is set */
4678         if (enable_rc6 >= 0) {
4679                 int mask;
4680
4681                 if (HAS_RC6p(dev))
4682                         mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
4683                                INTEL_RC6pp_ENABLE;
4684                 else
4685                         mask = INTEL_RC6_ENABLE;
4686
4687                 if ((enable_rc6 & mask) != enable_rc6)
4688                         DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
4689                                       enable_rc6 & mask, enable_rc6, mask);
4690
4691                 return enable_rc6 & mask;
4692         }
4693
4694         if (IS_IVYBRIDGE(dev))
4695                 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
4696
4697         return INTEL_RC6_ENABLE;
4698 }
4699
4700 int intel_enable_rc6(const struct drm_device *dev)
4701 {
4702         return i915.enable_rc6;
4703 }
4704
4705 static void gen6_init_rps_frequencies(struct drm_device *dev)
4706 {
4707         struct drm_i915_private *dev_priv = dev->dev_private;
4708         uint32_t rp_state_cap;
4709         u32 ddcc_status = 0;
4710         int ret;
4711
4712         /* All of these values are in units of 50MHz */
4713         dev_priv->rps.cur_freq          = 0;
4714         /* static values from HW: RP0 > RP1 > RPn (min_freq) */
4715         if (IS_BROXTON(dev)) {
4716                 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
4717                 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
4718                 dev_priv->rps.rp1_freq = (rp_state_cap >>  8) & 0xff;
4719                 dev_priv->rps.min_freq = (rp_state_cap >>  0) & 0xff;
4720         } else {
4721                 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
4722                 dev_priv->rps.rp0_freq = (rp_state_cap >>  0) & 0xff;
4723                 dev_priv->rps.rp1_freq = (rp_state_cap >>  8) & 0xff;
4724                 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
4725         }
4726
4727         /* hw_max = RP0 until we check for overclocking */
4728         dev_priv->rps.max_freq          = dev_priv->rps.rp0_freq;
4729
4730         dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
4731         if (IS_HASWELL(dev) || IS_BROADWELL(dev) ||
4732             IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
4733                 ret = sandybridge_pcode_read(dev_priv,
4734                                         HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
4735                                         &ddcc_status);
4736                 if (0 == ret)
4737                         dev_priv->rps.efficient_freq =
4738                                 clamp_t(u8,
4739                                         ((ddcc_status >> 8) & 0xff),
4740                                         dev_priv->rps.min_freq,
4741                                         dev_priv->rps.max_freq);
4742         }
4743
4744         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
4745                 /* Store the frequency values in 16.66 MHZ units, which is
4746                    the natural hardware unit for SKL */
4747                 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
4748                 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
4749                 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
4750                 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
4751                 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
4752         }
4753
4754         dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
4755
4756         /* Preserve min/max settings in case of re-init */
4757         if (dev_priv->rps.max_freq_softlimit == 0)
4758                 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4759
4760         if (dev_priv->rps.min_freq_softlimit == 0) {
4761                 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4762                         dev_priv->rps.min_freq_softlimit =
4763                                 max_t(int, dev_priv->rps.efficient_freq,
4764                                       intel_freq_opcode(dev_priv, 450));
4765                 else
4766                         dev_priv->rps.min_freq_softlimit =
4767                                 dev_priv->rps.min_freq;
4768         }
4769 }
4770
4771 /* See the Gen9_GT_PM_Programming_Guide doc for the below */
4772 static void gen9_enable_rps(struct drm_device *dev)
4773 {
4774         struct drm_i915_private *dev_priv = dev->dev_private;
4775
4776         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4777
4778         gen6_init_rps_frequencies(dev);
4779
4780         /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
4781         if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
4782                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4783                 return;
4784         }
4785
4786         /* Program defaults and thresholds for RPS*/
4787         I915_WRITE(GEN6_RC_VIDEO_FREQ,
4788                 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
4789
4790         /* 1 second timeout*/
4791         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
4792                 GT_INTERVAL_FROM_US(dev_priv, 1000000));
4793
4794         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
4795
4796         /* Leaning on the below call to gen6_set_rps to program/setup the
4797          * Up/Down EI & threshold registers, as well as the RP_CONTROL,
4798          * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
4799         dev_priv->rps.power = HIGH_POWER; /* force a reset */
4800         gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
4801
4802         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4803 }
4804
4805 static void gen9_enable_rc6(struct drm_device *dev)
4806 {
4807         struct drm_i915_private *dev_priv = dev->dev_private;
4808         struct intel_engine_cs *ring;
4809         uint32_t rc6_mask = 0;
4810         int unused;
4811
4812         /* 1a: Software RC state - RC0 */
4813         I915_WRITE(GEN6_RC_STATE, 0);
4814
4815         /* 1b: Get forcewake during program sequence. Although the driver
4816          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4817         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4818
4819         /* 2a: Disable RC states. */
4820         I915_WRITE(GEN6_RC_CONTROL, 0);
4821
4822         /* 2b: Program RC6 thresholds.*/
4823
4824         /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
4825         if (IS_SKYLAKE(dev))
4826                 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
4827         else
4828                 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
4829         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4830         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4831         for_each_ring(ring, dev_priv, unused)
4832                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4833
4834         if (HAS_GUC_UCODE(dev))
4835                 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
4836
4837         I915_WRITE(GEN6_RC_SLEEP, 0);
4838
4839         /* 2c: Program Coarse Power Gating Policies. */
4840         I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
4841         I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
4842
4843         /* 3a: Enable RC6 */
4844         if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4845                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
4846         DRM_INFO("RC6 %s\n", onoff(rc6_mask & GEN6_RC_CTL_RC6_ENABLE));
4847         /* WaRsUseTimeoutMode */
4848         if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) ||
4849             IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
4850                 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
4851                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4852                            GEN7_RC_CTL_TO_MODE |
4853                            rc6_mask);
4854         } else {
4855                 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
4856                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4857                            GEN6_RC_CTL_EI_MODE(1) |
4858                            rc6_mask);
4859         }
4860
4861         /*
4862          * 3b: Enable Coarse Power Gating only when RC6 is enabled.
4863          * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
4864          */
4865         if (NEEDS_WaRsDisableCoarsePowerGating(dev))
4866                 I915_WRITE(GEN9_PG_ENABLE, 0);
4867         else
4868                 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
4869                                 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
4870
4871         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4872
4873 }
4874
4875 static void gen8_enable_rps(struct drm_device *dev)
4876 {
4877         struct drm_i915_private *dev_priv = dev->dev_private;
4878         struct intel_engine_cs *ring;
4879         uint32_t rc6_mask = 0;
4880         int unused;
4881
4882         /* 1a: Software RC state - RC0 */
4883         I915_WRITE(GEN6_RC_STATE, 0);
4884
4885         /* 1c & 1d: Get forcewake during program sequence. Although the driver
4886          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4887         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4888
4889         /* 2a: Disable RC states. */
4890         I915_WRITE(GEN6_RC_CONTROL, 0);
4891
4892         /* Initialize rps frequencies */
4893         gen6_init_rps_frequencies(dev);
4894
4895         /* 2b: Program RC6 thresholds.*/
4896         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
4897         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4898         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4899         for_each_ring(ring, dev_priv, unused)
4900                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4901         I915_WRITE(GEN6_RC_SLEEP, 0);
4902         if (IS_BROADWELL(dev))
4903                 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
4904         else
4905                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
4906
4907         /* 3: Enable RC6 */
4908         if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4909                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
4910         intel_print_rc6_info(dev, rc6_mask);
4911         if (IS_BROADWELL(dev))
4912                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4913                                 GEN7_RC_CTL_TO_MODE |
4914                                 rc6_mask);
4915         else
4916                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4917                                 GEN6_RC_CTL_EI_MODE(1) |
4918                                 rc6_mask);
4919
4920         /* 4 Program defaults and thresholds for RPS*/
4921         I915_WRITE(GEN6_RPNSWREQ,
4922                    HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4923         I915_WRITE(GEN6_RC_VIDEO_FREQ,
4924                    HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4925         /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
4926         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
4927
4928         /* Docs recommend 900MHz, and 300 MHz respectively */
4929         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
4930                    dev_priv->rps.max_freq_softlimit << 24 |
4931                    dev_priv->rps.min_freq_softlimit << 16);
4932
4933         I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
4934         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
4935         I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
4936         I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
4937
4938         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4939
4940         /* 5: Enable RPS */
4941         I915_WRITE(GEN6_RP_CONTROL,
4942                    GEN6_RP_MEDIA_TURBO |
4943                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
4944                    GEN6_RP_MEDIA_IS_GFX |
4945                    GEN6_RP_ENABLE |
4946                    GEN6_RP_UP_BUSY_AVG |
4947                    GEN6_RP_DOWN_IDLE_AVG);
4948
4949         /* 6: Ring frequency + overclocking (our driver does this later */
4950
4951         dev_priv->rps.power = HIGH_POWER; /* force a reset */
4952         gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
4953
4954         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4955 }
4956
4957 static void gen6_enable_rps(struct drm_device *dev)
4958 {
4959         struct drm_i915_private *dev_priv = dev->dev_private;
4960         struct intel_engine_cs *ring;
4961         u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
4962         u32 gtfifodbg;
4963         int rc6_mode;
4964         int i, ret;
4965
4966         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4967
4968         /* Here begins a magic sequence of register writes to enable
4969          * auto-downclocking.
4970          *
4971          * Perhaps there might be some value in exposing these to
4972          * userspace...
4973          */
4974         I915_WRITE(GEN6_RC_STATE, 0);
4975
4976         /* Clear the DBG now so we don't confuse earlier errors */
4977         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
4978                 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
4979                 I915_WRITE(GTFIFODBG, gtfifodbg);
4980         }
4981
4982         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4983
4984         /* Initialize rps frequencies */
4985         gen6_init_rps_frequencies(dev);
4986
4987         /* disable the counters and set deterministic thresholds */
4988         I915_WRITE(GEN6_RC_CONTROL, 0);
4989
4990         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
4991         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
4992         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
4993         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
4994         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
4995
4996         for_each_ring(ring, dev_priv, i)
4997                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4998
4999         I915_WRITE(GEN6_RC_SLEEP, 0);
5000         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
5001         if (IS_IVYBRIDGE(dev))
5002                 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
5003         else
5004                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
5005         I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
5006         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
5007
5008         /* Check if we are enabling RC6 */
5009         rc6_mode = intel_enable_rc6(dev_priv->dev);
5010         if (rc6_mode & INTEL_RC6_ENABLE)
5011                 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
5012
5013         /* We don't use those on Haswell */
5014         if (!IS_HASWELL(dev)) {
5015                 if (rc6_mode & INTEL_RC6p_ENABLE)
5016                         rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
5017
5018                 if (rc6_mode & INTEL_RC6pp_ENABLE)
5019                         rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
5020         }
5021
5022         intel_print_rc6_info(dev, rc6_mask);
5023
5024         I915_WRITE(GEN6_RC_CONTROL,
5025                    rc6_mask |
5026                    GEN6_RC_CTL_EI_MODE(1) |
5027                    GEN6_RC_CTL_HW_ENABLE);
5028
5029         /* Power down if completely idle for over 50ms */
5030         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
5031         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5032
5033         ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
5034         if (ret)
5035                 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
5036
5037         ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
5038         if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
5039                 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
5040                                  (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
5041                                  (pcu_mbox & 0xff) * 50);
5042                 dev_priv->rps.max_freq = pcu_mbox & 0xff;
5043         }
5044
5045         dev_priv->rps.power = HIGH_POWER; /* force a reset */
5046         gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
5047
5048         rc6vids = 0;
5049         ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
5050         if (IS_GEN6(dev) && ret) {
5051                 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
5052         } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
5053                 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
5054                           GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
5055                 rc6vids &= 0xffff00;
5056                 rc6vids |= GEN6_ENCODE_RC6_VID(450);
5057                 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
5058                 if (ret)
5059                         DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
5060         }
5061
5062         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5063 }
5064
5065 static void __gen6_update_ring_freq(struct drm_device *dev)
5066 {
5067         struct drm_i915_private *dev_priv = dev->dev_private;
5068         int min_freq = 15;
5069         unsigned int gpu_freq;
5070         unsigned int max_ia_freq, min_ring_freq;
5071         unsigned int max_gpu_freq, min_gpu_freq;
5072         int scaling_factor = 180;
5073         struct cpufreq_policy *policy;
5074
5075         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5076
5077         policy = cpufreq_cpu_get(0);
5078         if (policy) {
5079                 max_ia_freq = policy->cpuinfo.max_freq;
5080                 cpufreq_cpu_put(policy);
5081         } else {
5082                 /*
5083                  * Default to measured freq if none found, PCU will ensure we
5084                  * don't go over
5085                  */
5086                 max_ia_freq = tsc_khz;
5087         }
5088
5089         /* Convert from kHz to MHz */
5090         max_ia_freq /= 1000;
5091
5092         min_ring_freq = I915_READ(DCLK) & 0xf;
5093         /* convert DDR frequency from units of 266.6MHz to bandwidth */
5094         min_ring_freq = mult_frac(min_ring_freq, 8, 3);
5095
5096         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
5097                 /* Convert GT frequency to 50 HZ units */
5098                 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
5099                 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
5100         } else {
5101                 min_gpu_freq = dev_priv->rps.min_freq;
5102                 max_gpu_freq = dev_priv->rps.max_freq;
5103         }
5104
5105         /*
5106          * For each potential GPU frequency, load a ring frequency we'd like
5107          * to use for memory access.  We do this by specifying the IA frequency
5108          * the PCU should use as a reference to determine the ring frequency.
5109          */
5110         for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
5111                 int diff = max_gpu_freq - gpu_freq;
5112                 unsigned int ia_freq = 0, ring_freq = 0;
5113
5114                 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
5115                         /*
5116                          * ring_freq = 2 * GT. ring_freq is in 100MHz units
5117                          * No floor required for ring frequency on SKL.
5118                          */
5119                         ring_freq = gpu_freq;
5120                 } else if (INTEL_INFO(dev)->gen >= 8) {
5121                         /* max(2 * GT, DDR). NB: GT is 50MHz units */
5122                         ring_freq = max(min_ring_freq, gpu_freq);
5123                 } else if (IS_HASWELL(dev)) {
5124                         ring_freq = mult_frac(gpu_freq, 5, 4);
5125                         ring_freq = max(min_ring_freq, ring_freq);
5126                         /* leave ia_freq as the default, chosen by cpufreq */
5127                 } else {
5128                         /* On older processors, there is no separate ring
5129                          * clock domain, so in order to boost the bandwidth
5130                          * of the ring, we need to upclock the CPU (ia_freq).
5131                          *
5132                          * For GPU frequencies less than 750MHz,
5133                          * just use the lowest ring freq.
5134                          */
5135                         if (gpu_freq < min_freq)
5136                                 ia_freq = 800;
5137                         else
5138                                 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
5139                         ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
5140                 }
5141
5142                 sandybridge_pcode_write(dev_priv,
5143                                         GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
5144                                         ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
5145                                         ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
5146                                         gpu_freq);
5147         }
5148 }
5149
5150 void gen6_update_ring_freq(struct drm_device *dev)
5151 {
5152         struct drm_i915_private *dev_priv = dev->dev_private;
5153
5154         if (!HAS_CORE_RING_FREQ(dev))
5155                 return;
5156
5157         mutex_lock(&dev_priv->rps.hw_lock);
5158         __gen6_update_ring_freq(dev);
5159         mutex_unlock(&dev_priv->rps.hw_lock);
5160 }
5161
5162 static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
5163 {
5164         struct drm_device *dev = dev_priv->dev;
5165         u32 val, rp0;
5166
5167         val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5168
5169         switch (INTEL_INFO(dev)->eu_total) {
5170         case 8:
5171                 /* (2 * 4) config */
5172                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5173                 break;
5174         case 12:
5175                 /* (2 * 6) config */
5176                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5177                 break;
5178         case 16:
5179                 /* (2 * 8) config */
5180         default:
5181                 /* Setting (2 * 8) Min RP0 for any other combination */
5182                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5183                 break;
5184         }
5185
5186         rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5187
5188         return rp0;
5189 }
5190
5191 static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5192 {
5193         u32 val, rpe;
5194
5195         val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5196         rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5197
5198         return rpe;
5199 }
5200
5201 static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5202 {
5203         u32 val, rp1;
5204
5205         val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5206         rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5207
5208         return rp1;
5209 }
5210
5211 static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5212 {
5213         u32 val, rp1;
5214
5215         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5216
5217         rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5218
5219         return rp1;
5220 }
5221
5222 static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
5223 {
5224         u32 val, rp0;
5225
5226         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5227
5228         rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5229         /* Clamp to max */
5230         rp0 = min_t(u32, rp0, 0xea);
5231
5232         return rp0;
5233 }
5234
5235 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5236 {
5237         u32 val, rpe;
5238
5239         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
5240         rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
5241         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
5242         rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5243
5244         return rpe;
5245 }
5246
5247 static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
5248 {
5249         u32 val;
5250
5251         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
5252         /*
5253          * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
5254          * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
5255          * a BYT-M B0 the above register contains 0xbf. Moreover when setting
5256          * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
5257          * to make sure it matches what Punit accepts.
5258          */
5259         return max_t(u32, val, 0xc0);
5260 }
5261
5262 /* Check that the pctx buffer wasn't move under us. */
5263 static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5264 {
5265         unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5266
5267         WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5268                              dev_priv->vlv_pctx->stolen->start);
5269 }
5270
5271
5272 /* Check that the pcbr address is not empty. */
5273 static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5274 {
5275         unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5276
5277         WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5278 }
5279
5280 static void cherryview_setup_pctx(struct drm_device *dev)
5281 {
5282         struct drm_i915_private *dev_priv = dev->dev_private;
5283         unsigned long pctx_paddr, paddr;
5284         struct i915_gtt *gtt = &dev_priv->gtt;
5285         u32 pcbr;
5286         int pctx_size = 32*1024;
5287
5288         pcbr = I915_READ(VLV_PCBR);
5289         if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
5290                 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5291                 paddr = (dev_priv->mm.stolen_base +
5292                          (gtt->stolen_size - pctx_size));
5293
5294                 pctx_paddr = (paddr & (~4095));
5295                 I915_WRITE(VLV_PCBR, pctx_paddr);
5296         }
5297
5298         DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5299 }
5300
5301 static void valleyview_setup_pctx(struct drm_device *dev)
5302 {
5303         struct drm_i915_private *dev_priv = dev->dev_private;
5304         struct drm_i915_gem_object *pctx;
5305         unsigned long pctx_paddr;
5306         u32 pcbr;
5307         int pctx_size = 24*1024;
5308
5309         mutex_lock(&dev->struct_mutex);
5310
5311         pcbr = I915_READ(VLV_PCBR);
5312         if (pcbr) {
5313                 /* BIOS set it up already, grab the pre-alloc'd space */
5314                 int pcbr_offset;
5315
5316                 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
5317                 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
5318                                                                       pcbr_offset,
5319                                                                       I915_GTT_OFFSET_NONE,
5320                                                                       pctx_size);
5321                 goto out;
5322         }
5323
5324         DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5325
5326         /*
5327          * From the Gunit register HAS:
5328          * The Gfx driver is expected to program this register and ensure
5329          * proper allocation within Gfx stolen memory.  For example, this
5330          * register should be programmed such than the PCBR range does not
5331          * overlap with other ranges, such as the frame buffer, protected
5332          * memory, or any other relevant ranges.
5333          */
5334         pctx = i915_gem_object_create_stolen(dev, pctx_size);
5335         if (!pctx) {
5336                 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
5337                 goto out;
5338         }
5339
5340         pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5341         I915_WRITE(VLV_PCBR, pctx_paddr);
5342
5343 out:
5344         DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5345         dev_priv->vlv_pctx = pctx;
5346         mutex_unlock(&dev->struct_mutex);
5347 }
5348
5349 static void valleyview_cleanup_pctx(struct drm_device *dev)
5350 {
5351         struct drm_i915_private *dev_priv = dev->dev_private;
5352
5353         if (WARN_ON(!dev_priv->vlv_pctx))
5354                 return;
5355
5356         drm_gem_object_unreference_unlocked(&dev_priv->vlv_pctx->base);
5357         dev_priv->vlv_pctx = NULL;
5358 }
5359
5360 static void valleyview_init_gt_powersave(struct drm_device *dev)
5361 {
5362         struct drm_i915_private *dev_priv = dev->dev_private;
5363         u32 val;
5364
5365         valleyview_setup_pctx(dev);
5366
5367         mutex_lock(&dev_priv->rps.hw_lock);
5368
5369         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5370         switch ((val >> 6) & 3) {
5371         case 0:
5372         case 1:
5373                 dev_priv->mem_freq = 800;
5374                 break;
5375         case 2:
5376                 dev_priv->mem_freq = 1066;
5377                 break;
5378         case 3:
5379                 dev_priv->mem_freq = 1333;
5380                 break;
5381         }
5382         DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5383
5384         dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5385         dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5386         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5387                          intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5388                          dev_priv->rps.max_freq);
5389
5390         dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5391         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5392                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5393                          dev_priv->rps.efficient_freq);
5394
5395         dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5396         DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
5397                          intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5398                          dev_priv->rps.rp1_freq);
5399
5400         dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5401         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5402                          intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5403                          dev_priv->rps.min_freq);
5404
5405         dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5406
5407         /* Preserve min/max settings in case of re-init */
5408         if (dev_priv->rps.max_freq_softlimit == 0)
5409                 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5410
5411         if (dev_priv->rps.min_freq_softlimit == 0)
5412                 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5413
5414         mutex_unlock(&dev_priv->rps.hw_lock);
5415 }
5416
5417 static void cherryview_init_gt_powersave(struct drm_device *dev)
5418 {
5419         struct drm_i915_private *dev_priv = dev->dev_private;
5420         u32 val;
5421
5422         cherryview_setup_pctx(dev);
5423
5424         mutex_lock(&dev_priv->rps.hw_lock);
5425
5426         mutex_lock(&dev_priv->sb_lock);
5427         val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
5428         mutex_unlock(&dev_priv->sb_lock);
5429
5430         switch ((val >> 2) & 0x7) {
5431         case 3:
5432                 dev_priv->mem_freq = 2000;
5433                 break;
5434         default:
5435                 dev_priv->mem_freq = 1600;
5436                 break;
5437         }
5438         DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5439
5440         dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5441         dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5442         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5443                          intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5444                          dev_priv->rps.max_freq);
5445
5446         dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5447         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5448                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5449                          dev_priv->rps.efficient_freq);
5450
5451         dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5452         DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
5453                          intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5454                          dev_priv->rps.rp1_freq);
5455
5456         /* PUnit validated range is only [RPe, RP0] */
5457         dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
5458         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5459                          intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5460                          dev_priv->rps.min_freq);
5461
5462         WARN_ONCE((dev_priv->rps.max_freq |
5463                    dev_priv->rps.efficient_freq |
5464                    dev_priv->rps.rp1_freq |
5465                    dev_priv->rps.min_freq) & 1,
5466                   "Odd GPU freq values\n");
5467
5468         dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5469
5470         /* Preserve min/max settings in case of re-init */
5471         if (dev_priv->rps.max_freq_softlimit == 0)
5472                 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5473
5474         if (dev_priv->rps.min_freq_softlimit == 0)
5475                 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5476
5477         mutex_unlock(&dev_priv->rps.hw_lock);
5478 }
5479
5480 static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
5481 {
5482         valleyview_cleanup_pctx(dev);
5483 }
5484
5485 static void cherryview_enable_rps(struct drm_device *dev)
5486 {
5487         struct drm_i915_private *dev_priv = dev->dev_private;
5488         struct intel_engine_cs *ring;
5489         u32 gtfifodbg, val, rc6_mode = 0, pcbr;
5490         int i;
5491
5492         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5493
5494         gtfifodbg = I915_READ(GTFIFODBG);
5495         if (gtfifodbg) {
5496                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5497                                  gtfifodbg);
5498                 I915_WRITE(GTFIFODBG, gtfifodbg);
5499         }
5500
5501         cherryview_check_pctx(dev_priv);
5502
5503         /* 1a & 1b: Get forcewake during program sequence. Although the driver
5504          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5505         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5506
5507         /*  Disable RC states. */
5508         I915_WRITE(GEN6_RC_CONTROL, 0);
5509
5510         /* 2a: Program RC6 thresholds.*/
5511         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5512         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5513         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5514
5515         for_each_ring(ring, dev_priv, i)
5516                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5517         I915_WRITE(GEN6_RC_SLEEP, 0);
5518
5519         /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
5520         I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
5521
5522         /* allows RC6 residency counter to work */
5523         I915_WRITE(VLV_COUNTER_CONTROL,
5524                    _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
5525                                       VLV_MEDIA_RC6_COUNT_EN |
5526                                       VLV_RENDER_RC6_COUNT_EN));
5527
5528         /* For now we assume BIOS is allocating and populating the PCBR  */
5529         pcbr = I915_READ(VLV_PCBR);
5530
5531         /* 3: Enable RC6 */
5532         if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
5533                                                 (pcbr >> VLV_PCBR_ADDR_SHIFT))
5534                 rc6_mode = GEN7_RC_CTL_TO_MODE;
5535
5536         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5537
5538         /* 4 Program defaults and thresholds for RPS*/
5539         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
5540         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5541         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5542         I915_WRITE(GEN6_RP_UP_EI, 66000);
5543         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5544
5545         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5546
5547         /* 5: Enable RPS */
5548         I915_WRITE(GEN6_RP_CONTROL,
5549                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
5550                    GEN6_RP_MEDIA_IS_GFX |
5551                    GEN6_RP_ENABLE |
5552                    GEN6_RP_UP_BUSY_AVG |
5553                    GEN6_RP_DOWN_IDLE_AVG);
5554
5555         /* Setting Fixed Bias */
5556         val = VLV_OVERRIDE_EN |
5557                   VLV_SOC_TDP_EN |
5558                   CHV_BIAS_CPU_50_SOC_50;
5559         vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5560
5561         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5562
5563         /* RPS code assumes GPLL is used */
5564         WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5565
5566         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
5567         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5568
5569         dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5570         DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
5571                          intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
5572                          dev_priv->rps.cur_freq);
5573
5574         DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5575                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5576                          dev_priv->rps.efficient_freq);
5577
5578         valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
5579
5580         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5581 }
5582
5583 static void valleyview_enable_rps(struct drm_device *dev)
5584 {
5585         struct drm_i915_private *dev_priv = dev->dev_private;
5586         struct intel_engine_cs *ring;
5587         u32 gtfifodbg, val, rc6_mode = 0;
5588         int i;
5589
5590         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5591
5592         valleyview_check_pctx(dev_priv);
5593
5594         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
5595                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5596                                  gtfifodbg);
5597                 I915_WRITE(GTFIFODBG, gtfifodbg);
5598         }
5599
5600         /* If VLV, Forcewake all wells, else re-direct to regular path */
5601         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5602
5603         /*  Disable RC states. */
5604         I915_WRITE(GEN6_RC_CONTROL, 0);
5605
5606         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
5607         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5608         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5609         I915_WRITE(GEN6_RP_UP_EI, 66000);
5610         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5611
5612         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5613
5614         I915_WRITE(GEN6_RP_CONTROL,
5615                    GEN6_RP_MEDIA_TURBO |
5616                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
5617                    GEN6_RP_MEDIA_IS_GFX |
5618                    GEN6_RP_ENABLE |
5619                    GEN6_RP_UP_BUSY_AVG |
5620                    GEN6_RP_DOWN_IDLE_CONT);
5621
5622         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
5623         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5624         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5625
5626         for_each_ring(ring, dev_priv, i)
5627                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5628
5629         I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
5630
5631         /* allows RC6 residency counter to work */
5632         I915_WRITE(VLV_COUNTER_CONTROL,
5633                    _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
5634                                       VLV_RENDER_RC0_COUNT_EN |
5635                                       VLV_MEDIA_RC6_COUNT_EN |
5636                                       VLV_RENDER_RC6_COUNT_EN));
5637
5638         if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
5639                 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
5640
5641         intel_print_rc6_info(dev, rc6_mode);
5642
5643         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5644
5645         /* Setting Fixed Bias */
5646         val = VLV_OVERRIDE_EN |
5647                   VLV_SOC_TDP_EN |
5648                   VLV_BIAS_CPU_125_SOC_875;
5649         vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5650
5651         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5652
5653         /* RPS code assumes GPLL is used */
5654         WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5655
5656         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
5657         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5658
5659         dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5660         DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
5661                          intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
5662                          dev_priv->rps.cur_freq);
5663
5664         DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5665                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5666                          dev_priv->rps.efficient_freq);
5667
5668         valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
5669
5670         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5671 }
5672
5673 static unsigned long intel_pxfreq(u32 vidfreq)
5674 {
5675         unsigned long freq;
5676         int div = (vidfreq & 0x3f0000) >> 16;
5677         int post = (vidfreq & 0x3000) >> 12;
5678         int pre = (vidfreq & 0x7);
5679
5680         if (!pre)
5681                 return 0;
5682
5683         freq = ((div * 133333) / ((1<<post) * pre));
5684
5685         return freq;
5686 }
5687
5688 static const struct cparams {
5689         u16 i;
5690         u16 t;
5691         u16 m;
5692         u16 c;
5693 } cparams[] = {
5694         { 1, 1333, 301, 28664 },
5695         { 1, 1066, 294, 24460 },
5696         { 1, 800, 294, 25192 },
5697         { 0, 1333, 276, 27605 },
5698         { 0, 1066, 276, 27605 },
5699         { 0, 800, 231, 23784 },
5700 };
5701
5702 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
5703 {
5704         u64 total_count, diff, ret;
5705         u32 count1, count2, count3, m = 0, c = 0;
5706         unsigned long now = jiffies_to_msecs(jiffies), diff1;
5707         int i;
5708
5709         assert_spin_locked(&mchdev_lock);
5710
5711         diff1 = now - dev_priv->ips.last_time1;
5712
5713         /* Prevent division-by-zero if we are asking too fast.
5714          * Also, we don't get interesting results if we are polling
5715          * faster than once in 10ms, so just return the saved value
5716          * in such cases.
5717          */
5718         if (diff1 <= 10)
5719                 return dev_priv->ips.chipset_power;
5720
5721         count1 = I915_READ(DMIEC);
5722         count2 = I915_READ(DDREC);
5723         count3 = I915_READ(CSIEC);
5724
5725         total_count = count1 + count2 + count3;
5726
5727         /* FIXME: handle per-counter overflow */
5728         if (total_count < dev_priv->ips.last_count1) {
5729                 diff = ~0UL - dev_priv->ips.last_count1;
5730                 diff += total_count;
5731         } else {
5732                 diff = total_count - dev_priv->ips.last_count1;
5733         }
5734
5735         for (i = 0; i < ARRAY_SIZE(cparams); i++) {
5736                 if (cparams[i].i == dev_priv->ips.c_m &&
5737                     cparams[i].t == dev_priv->ips.r_t) {
5738                         m = cparams[i].m;
5739                         c = cparams[i].c;
5740                         break;
5741                 }
5742         }
5743
5744         diff = div_u64(diff, diff1);
5745         ret = ((m * diff) + c);
5746         ret = div_u64(ret, 10);
5747
5748         dev_priv->ips.last_count1 = total_count;
5749         dev_priv->ips.last_time1 = now;
5750
5751         dev_priv->ips.chipset_power = ret;
5752
5753         return ret;
5754 }
5755
5756 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
5757 {
5758         struct drm_device *dev = dev_priv->dev;
5759         unsigned long val;
5760
5761         if (INTEL_INFO(dev)->gen != 5)
5762                 return 0;
5763
5764         spin_lock_irq(&mchdev_lock);
5765
5766         val = __i915_chipset_val(dev_priv);
5767
5768         spin_unlock_irq(&mchdev_lock);
5769
5770         return val;
5771 }
5772
5773 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
5774 {
5775         unsigned long m, x, b;
5776         u32 tsfs;
5777
5778         tsfs = I915_READ(TSFS);
5779
5780         m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
5781         x = I915_READ8(TR1);
5782
5783         b = tsfs & TSFS_INTR_MASK;
5784
5785         return ((m * x) / 127) - b;
5786 }
5787
5788 static int _pxvid_to_vd(u8 pxvid)
5789 {
5790         if (pxvid == 0)
5791                 return 0;
5792
5793         if (pxvid >= 8 && pxvid < 31)
5794                 pxvid = 31;
5795
5796         return (pxvid + 2) * 125;
5797 }
5798
5799 static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
5800 {
5801         struct drm_device *dev = dev_priv->dev;
5802         const int vd = _pxvid_to_vd(pxvid);
5803         const int vm = vd - 1125;
5804
5805         if (INTEL_INFO(dev)->is_mobile)
5806                 return vm > 0 ? vm : 0;
5807
5808         return vd;
5809 }
5810
5811 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
5812 {
5813         u64 now, diff, diffms;
5814         u32 count;
5815
5816         assert_spin_locked(&mchdev_lock);
5817
5818         now = ktime_get_raw_ns();
5819         diffms = now - dev_priv->ips.last_time2;
5820         do_div(diffms, NSEC_PER_MSEC);
5821
5822         /* Don't divide by 0 */
5823         if (!diffms)
5824                 return;
5825
5826         count = I915_READ(GFXEC);
5827
5828         if (count < dev_priv->ips.last_count2) {
5829                 diff = ~0UL - dev_priv->ips.last_count2;
5830                 diff += count;
5831         } else {
5832                 diff = count - dev_priv->ips.last_count2;
5833         }
5834
5835         dev_priv->ips.last_count2 = count;
5836         dev_priv->ips.last_time2 = now;
5837
5838         /* More magic constants... */
5839         diff = diff * 1181;
5840         diff = div_u64(diff, diffms * 10);
5841         dev_priv->ips.gfx_power = diff;
5842 }
5843
5844 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
5845 {
5846         struct drm_device *dev = dev_priv->dev;
5847
5848         if (INTEL_INFO(dev)->gen != 5)
5849                 return;
5850
5851         spin_lock_irq(&mchdev_lock);
5852
5853         __i915_update_gfx_val(dev_priv);
5854
5855         spin_unlock_irq(&mchdev_lock);
5856 }
5857
5858 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
5859 {
5860         unsigned long t, corr, state1, corr2, state2;
5861         u32 pxvid, ext_v;
5862
5863         assert_spin_locked(&mchdev_lock);
5864
5865         pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
5866         pxvid = (pxvid >> 24) & 0x7f;
5867         ext_v = pvid_to_extvid(dev_priv, pxvid);
5868
5869         state1 = ext_v;
5870
5871         t = i915_mch_val(dev_priv);
5872
5873         /* Revel in the empirically derived constants */
5874
5875         /* Correction factor in 1/100000 units */
5876         if (t > 80)
5877                 corr = ((t * 2349) + 135940);
5878         else if (t >= 50)
5879                 corr = ((t * 964) + 29317);
5880         else /* < 50 */
5881                 corr = ((t * 301) + 1004);
5882
5883         corr = corr * ((150142 * state1) / 10000 - 78642);
5884         corr /= 100000;
5885         corr2 = (corr * dev_priv->ips.corr);
5886
5887         state2 = (corr2 * state1) / 10000;
5888         state2 /= 100; /* convert to mW */
5889
5890         __i915_update_gfx_val(dev_priv);
5891
5892         return dev_priv->ips.gfx_power + state2;
5893 }
5894
5895 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
5896 {
5897         struct drm_device *dev = dev_priv->dev;
5898         unsigned long val;
5899
5900         if (INTEL_INFO(dev)->gen != 5)
5901                 return 0;
5902
5903         spin_lock_irq(&mchdev_lock);
5904
5905         val = __i915_gfx_val(dev_priv);
5906
5907         spin_unlock_irq(&mchdev_lock);
5908
5909         return val;
5910 }
5911
5912 /**
5913  * i915_read_mch_val - return value for IPS use
5914  *
5915  * Calculate and return a value for the IPS driver to use when deciding whether
5916  * we have thermal and power headroom to increase CPU or GPU power budget.
5917  */
5918 unsigned long i915_read_mch_val(void)
5919 {
5920         struct drm_i915_private *dev_priv;
5921         unsigned long chipset_val, graphics_val, ret = 0;
5922
5923         spin_lock_irq(&mchdev_lock);
5924         if (!i915_mch_dev)
5925                 goto out_unlock;
5926         dev_priv = i915_mch_dev;
5927
5928         chipset_val = __i915_chipset_val(dev_priv);
5929         graphics_val = __i915_gfx_val(dev_priv);
5930
5931         ret = chipset_val + graphics_val;
5932
5933 out_unlock:
5934         spin_unlock_irq(&mchdev_lock);
5935
5936         return ret;
5937 }
5938 EXPORT_SYMBOL_GPL(i915_read_mch_val);
5939
5940 /**
5941  * i915_gpu_raise - raise GPU frequency limit
5942  *
5943  * Raise the limit; IPS indicates we have thermal headroom.
5944  */
5945 bool i915_gpu_raise(void)
5946 {
5947         struct drm_i915_private *dev_priv;
5948         bool ret = true;
5949
5950         spin_lock_irq(&mchdev_lock);
5951         if (!i915_mch_dev) {
5952                 ret = false;
5953                 goto out_unlock;
5954         }
5955         dev_priv = i915_mch_dev;
5956
5957         if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
5958                 dev_priv->ips.max_delay--;
5959
5960 out_unlock:
5961         spin_unlock_irq(&mchdev_lock);
5962
5963         return ret;
5964 }
5965 EXPORT_SYMBOL_GPL(i915_gpu_raise);
5966
5967 /**
5968  * i915_gpu_lower - lower GPU frequency limit
5969  *
5970  * IPS indicates we're close to a thermal limit, so throttle back the GPU
5971  * frequency maximum.
5972  */
5973 bool i915_gpu_lower(void)
5974 {
5975         struct drm_i915_private *dev_priv;
5976         bool ret = true;
5977
5978         spin_lock_irq(&mchdev_lock);
5979         if (!i915_mch_dev) {
5980                 ret = false;
5981                 goto out_unlock;
5982         }
5983         dev_priv = i915_mch_dev;
5984
5985         if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
5986                 dev_priv->ips.max_delay++;
5987
5988 out_unlock:
5989         spin_unlock_irq(&mchdev_lock);
5990
5991         return ret;
5992 }
5993 EXPORT_SYMBOL_GPL(i915_gpu_lower);
5994
5995 /**
5996  * i915_gpu_busy - indicate GPU business to IPS
5997  *
5998  * Tell the IPS driver whether or not the GPU is busy.
5999  */
6000 bool i915_gpu_busy(void)
6001 {
6002         struct drm_i915_private *dev_priv;
6003         struct intel_engine_cs *ring;
6004         bool ret = false;
6005         int i;
6006
6007         spin_lock_irq(&mchdev_lock);
6008         if (!i915_mch_dev)
6009                 goto out_unlock;
6010         dev_priv = i915_mch_dev;
6011
6012         for_each_ring(ring, dev_priv, i)
6013                 ret |= !list_empty(&ring->request_list);
6014
6015 out_unlock:
6016         spin_unlock_irq(&mchdev_lock);
6017
6018         return ret;
6019 }
6020 EXPORT_SYMBOL_GPL(i915_gpu_busy);
6021
6022 /**
6023  * i915_gpu_turbo_disable - disable graphics turbo
6024  *
6025  * Disable graphics turbo by resetting the max frequency and setting the
6026  * current frequency to the default.
6027  */
6028 bool i915_gpu_turbo_disable(void)
6029 {
6030         struct drm_i915_private *dev_priv;
6031         bool ret = true;
6032
6033         spin_lock_irq(&mchdev_lock);
6034         if (!i915_mch_dev) {
6035                 ret = false;
6036                 goto out_unlock;
6037         }
6038         dev_priv = i915_mch_dev;
6039
6040         dev_priv->ips.max_delay = dev_priv->ips.fstart;
6041
6042         if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
6043                 ret = false;
6044
6045 out_unlock:
6046         spin_unlock_irq(&mchdev_lock);
6047
6048         return ret;
6049 }
6050 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
6051
6052 /**
6053  * Tells the intel_ips driver that the i915 driver is now loaded, if
6054  * IPS got loaded first.
6055  *
6056  * This awkward dance is so that neither module has to depend on the
6057  * other in order for IPS to do the appropriate communication of
6058  * GPU turbo limits to i915.
6059  */
6060 static void
6061 ips_ping_for_i915_load(void)
6062 {
6063         void (*link)(void);
6064
6065         link = symbol_get(ips_link_to_i915_driver);
6066         if (link) {
6067                 link();
6068                 symbol_put(ips_link_to_i915_driver);
6069         }
6070 }
6071
6072 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
6073 {
6074         /* We only register the i915 ips part with intel-ips once everything is
6075          * set up, to avoid intel-ips sneaking in and reading bogus values. */
6076         spin_lock_irq(&mchdev_lock);
6077         i915_mch_dev = dev_priv;
6078         spin_unlock_irq(&mchdev_lock);
6079
6080         ips_ping_for_i915_load();
6081 }
6082
6083 void intel_gpu_ips_teardown(void)
6084 {
6085         spin_lock_irq(&mchdev_lock);
6086         i915_mch_dev = NULL;
6087         spin_unlock_irq(&mchdev_lock);
6088 }
6089
6090 static void intel_init_emon(struct drm_device *dev)
6091 {
6092         struct drm_i915_private *dev_priv = dev->dev_private;
6093         u32 lcfuse;
6094         u8 pxw[16];
6095         int i;
6096
6097         /* Disable to program */
6098         I915_WRITE(ECR, 0);
6099         POSTING_READ(ECR);
6100
6101         /* Program energy weights for various events */
6102         I915_WRITE(SDEW, 0x15040d00);
6103         I915_WRITE(CSIEW0, 0x007f0000);
6104         I915_WRITE(CSIEW1, 0x1e220004);
6105         I915_WRITE(CSIEW2, 0x04000004);
6106
6107         for (i = 0; i < 5; i++)
6108                 I915_WRITE(PEW(i), 0);
6109         for (i = 0; i < 3; i++)
6110                 I915_WRITE(DEW(i), 0);
6111
6112         /* Program P-state weights to account for frequency power adjustment */
6113         for (i = 0; i < 16; i++) {
6114                 u32 pxvidfreq = I915_READ(PXVFREQ(i));
6115                 unsigned long freq = intel_pxfreq(pxvidfreq);
6116                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6117                         PXVFREQ_PX_SHIFT;
6118                 unsigned long val;
6119
6120                 val = vid * vid;
6121                 val *= (freq / 1000);
6122                 val *= 255;
6123                 val /= (127*127*900);
6124                 if (val > 0xff)
6125                         DRM_ERROR("bad pxval: %ld\n", val);
6126                 pxw[i] = val;
6127         }
6128         /* Render standby states get 0 weight */
6129         pxw[14] = 0;
6130         pxw[15] = 0;
6131
6132         for (i = 0; i < 4; i++) {
6133                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6134                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
6135                 I915_WRITE(PXW(i), val);
6136         }
6137
6138         /* Adjust magic regs to magic values (more experimental results) */
6139         I915_WRITE(OGW0, 0);
6140         I915_WRITE(OGW1, 0);
6141         I915_WRITE(EG0, 0x00007f00);
6142         I915_WRITE(EG1, 0x0000000e);
6143         I915_WRITE(EG2, 0x000e0000);
6144         I915_WRITE(EG3, 0x68000300);
6145         I915_WRITE(EG4, 0x42000000);
6146         I915_WRITE(EG5, 0x00140031);
6147         I915_WRITE(EG6, 0);
6148         I915_WRITE(EG7, 0);
6149
6150         for (i = 0; i < 8; i++)
6151                 I915_WRITE(PXWL(i), 0);
6152
6153         /* Enable PMON + select events */
6154         I915_WRITE(ECR, 0x80000019);
6155
6156         lcfuse = I915_READ(LCFUSE02);
6157
6158         dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
6159 }
6160
6161 void intel_init_gt_powersave(struct drm_device *dev)
6162 {
6163         struct drm_i915_private *dev_priv = dev->dev_private;
6164
6165         /*
6166          * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6167          * requirement.
6168          */
6169         if (!i915.enable_rc6) {
6170                 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6171                 intel_runtime_pm_get(dev_priv);
6172         }
6173
6174         if (IS_CHERRYVIEW(dev))
6175                 cherryview_init_gt_powersave(dev);
6176         else if (IS_VALLEYVIEW(dev))
6177                 valleyview_init_gt_powersave(dev);
6178 }
6179
6180 void intel_cleanup_gt_powersave(struct drm_device *dev)
6181 {
6182         struct drm_i915_private *dev_priv = dev->dev_private;
6183
6184         if (IS_CHERRYVIEW(dev))
6185                 return;
6186         else if (IS_VALLEYVIEW(dev))
6187                 valleyview_cleanup_gt_powersave(dev);
6188
6189         if (!i915.enable_rc6)
6190                 intel_runtime_pm_put(dev_priv);
6191 }
6192
6193 static void gen6_suspend_rps(struct drm_device *dev)
6194 {
6195         struct drm_i915_private *dev_priv = dev->dev_private;
6196
6197         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
6198
6199         gen6_disable_rps_interrupts(dev);
6200 }
6201
6202 /**
6203  * intel_suspend_gt_powersave - suspend PM work and helper threads
6204  * @dev: drm device
6205  *
6206  * We don't want to disable RC6 or other features here, we just want
6207  * to make sure any work we've queued has finished and won't bother
6208  * us while we're suspended.
6209  */
6210 void intel_suspend_gt_powersave(struct drm_device *dev)
6211 {
6212         struct drm_i915_private *dev_priv = dev->dev_private;
6213
6214         if (INTEL_INFO(dev)->gen < 6)
6215                 return;
6216
6217         gen6_suspend_rps(dev);
6218
6219         /* Force GPU to min freq during suspend */
6220         gen6_rps_idle(dev_priv);
6221 }
6222
6223 void intel_disable_gt_powersave(struct drm_device *dev)
6224 {
6225         struct drm_i915_private *dev_priv = dev->dev_private;
6226
6227         if (IS_IRONLAKE_M(dev)) {
6228                 ironlake_disable_drps(dev);
6229         } else if (INTEL_INFO(dev)->gen >= 6) {
6230                 intel_suspend_gt_powersave(dev);
6231
6232                 mutex_lock(&dev_priv->rps.hw_lock);
6233                 if (INTEL_INFO(dev)->gen >= 9)
6234                         gen9_disable_rps(dev);
6235                 else if (IS_CHERRYVIEW(dev))
6236                         cherryview_disable_rps(dev);
6237                 else if (IS_VALLEYVIEW(dev))
6238                         valleyview_disable_rps(dev);
6239                 else
6240                         gen6_disable_rps(dev);
6241
6242                 dev_priv->rps.enabled = false;
6243                 mutex_unlock(&dev_priv->rps.hw_lock);
6244         }
6245 }
6246
6247 static void intel_gen6_powersave_work(struct work_struct *work)
6248 {
6249         struct drm_i915_private *dev_priv =
6250                 container_of(work, struct drm_i915_private,
6251                              rps.delayed_resume_work.work);
6252         struct drm_device *dev = dev_priv->dev;
6253
6254         mutex_lock(&dev_priv->rps.hw_lock);
6255
6256         gen6_reset_rps_interrupts(dev);
6257
6258         if (IS_CHERRYVIEW(dev)) {
6259                 cherryview_enable_rps(dev);
6260         } else if (IS_VALLEYVIEW(dev)) {
6261                 valleyview_enable_rps(dev);
6262         } else if (INTEL_INFO(dev)->gen >= 9) {
6263                 gen9_enable_rc6(dev);
6264                 gen9_enable_rps(dev);
6265                 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
6266                         __gen6_update_ring_freq(dev);
6267         } else if (IS_BROADWELL(dev)) {
6268                 gen8_enable_rps(dev);
6269                 __gen6_update_ring_freq(dev);
6270         } else {
6271                 gen6_enable_rps(dev);
6272                 __gen6_update_ring_freq(dev);
6273         }
6274
6275         WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6276         WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6277
6278         WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6279         WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6280
6281         dev_priv->rps.enabled = true;
6282
6283         gen6_enable_rps_interrupts(dev);
6284
6285         mutex_unlock(&dev_priv->rps.hw_lock);
6286
6287         intel_runtime_pm_put(dev_priv);
6288 }
6289
6290 void intel_enable_gt_powersave(struct drm_device *dev)
6291 {
6292         struct drm_i915_private *dev_priv = dev->dev_private;
6293
6294         /* Powersaving is controlled by the host when inside a VM */
6295         if (intel_vgpu_active(dev))
6296                 return;
6297
6298         if (IS_IRONLAKE_M(dev)) {
6299                 ironlake_enable_drps(dev);
6300                 mutex_lock(&dev->struct_mutex);
6301                 intel_init_emon(dev);
6302                 mutex_unlock(&dev->struct_mutex);
6303         } else if (INTEL_INFO(dev)->gen >= 6) {
6304                 /*
6305                  * PCU communication is slow and this doesn't need to be
6306                  * done at any specific time, so do this out of our fast path
6307                  * to make resume and init faster.
6308                  *
6309                  * We depend on the HW RC6 power context save/restore
6310                  * mechanism when entering D3 through runtime PM suspend. So
6311                  * disable RPM until RPS/RC6 is properly setup. We can only
6312                  * get here via the driver load/system resume/runtime resume
6313                  * paths, so the _noresume version is enough (and in case of
6314                  * runtime resume it's necessary).
6315                  */
6316                 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
6317                                            round_jiffies_up_relative(HZ)))
6318                         intel_runtime_pm_get_noresume(dev_priv);
6319         }
6320 }
6321
6322 void intel_reset_gt_powersave(struct drm_device *dev)
6323 {
6324         struct drm_i915_private *dev_priv = dev->dev_private;
6325
6326         if (INTEL_INFO(dev)->gen < 6)
6327                 return;
6328
6329         gen6_suspend_rps(dev);
6330         dev_priv->rps.enabled = false;
6331 }
6332
6333 static void ibx_init_clock_gating(struct drm_device *dev)
6334 {
6335         struct drm_i915_private *dev_priv = dev->dev_private;
6336
6337         /*
6338          * On Ibex Peak and Cougar Point, we need to disable clock
6339          * gating for the panel power sequencer or it will fail to
6340          * start up when no ports are active.
6341          */
6342         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6343 }
6344
6345 static void g4x_disable_trickle_feed(struct drm_device *dev)
6346 {
6347         struct drm_i915_private *dev_priv = dev->dev_private;
6348         enum pipe pipe;
6349
6350         for_each_pipe(dev_priv, pipe) {
6351                 I915_WRITE(DSPCNTR(pipe),
6352                            I915_READ(DSPCNTR(pipe)) |
6353                            DISPPLANE_TRICKLE_FEED_DISABLE);
6354
6355                 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6356                 POSTING_READ(DSPSURF(pipe));
6357         }
6358 }
6359
6360 static void ilk_init_lp_watermarks(struct drm_device *dev)
6361 {
6362         struct drm_i915_private *dev_priv = dev->dev_private;
6363
6364         I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6365         I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6366         I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6367
6368         /*
6369          * Don't touch WM1S_LP_EN here.
6370          * Doing so could cause underruns.
6371          */
6372 }
6373
6374 static void ironlake_init_clock_gating(struct drm_device *dev)
6375 {
6376         struct drm_i915_private *dev_priv = dev->dev_private;
6377         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6378
6379         /*
6380          * Required for FBC
6381          * WaFbcDisableDpfcClockGating:ilk
6382          */
6383         dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6384                    ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6385                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6386
6387         I915_WRITE(PCH_3DCGDIS0,
6388                    MARIUNIT_CLOCK_GATE_DISABLE |
6389                    SVSMUNIT_CLOCK_GATE_DISABLE);
6390         I915_WRITE(PCH_3DCGDIS1,
6391                    VFMUNIT_CLOCK_GATE_DISABLE);
6392
6393         /*
6394          * According to the spec the following bits should be set in
6395          * order to enable memory self-refresh
6396          * The bit 22/21 of 0x42004
6397          * The bit 5 of 0x42020
6398          * The bit 15 of 0x45000
6399          */
6400         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6401                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
6402                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
6403         dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6404         I915_WRITE(DISP_ARB_CTL,
6405                    (I915_READ(DISP_ARB_CTL) |
6406                     DISP_FBC_WM_DIS));
6407
6408         ilk_init_lp_watermarks(dev);
6409
6410         /*
6411          * Based on the document from hardware guys the following bits
6412          * should be set unconditionally in order to enable FBC.
6413          * The bit 22 of 0x42000
6414          * The bit 22 of 0x42004
6415          * The bit 7,8,9 of 0x42020.
6416          */
6417         if (IS_IRONLAKE_M(dev)) {
6418                 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6419                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6420                            I915_READ(ILK_DISPLAY_CHICKEN1) |
6421                            ILK_FBCQ_DIS);
6422                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6423                            I915_READ(ILK_DISPLAY_CHICKEN2) |
6424                            ILK_DPARB_GATE);
6425         }
6426
6427         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6428
6429         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6430                    I915_READ(ILK_DISPLAY_CHICKEN2) |
6431                    ILK_ELPIN_409_SELECT);
6432         I915_WRITE(_3D_CHICKEN2,
6433                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6434                    _3D_CHICKEN2_WM_READ_PIPELINED);
6435
6436         /* WaDisableRenderCachePipelinedFlush:ilk */
6437         I915_WRITE(CACHE_MODE_0,
6438                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
6439
6440         /* WaDisable_RenderCache_OperationalFlush:ilk */
6441         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6442
6443         g4x_disable_trickle_feed(dev);
6444
6445         ibx_init_clock_gating(dev);
6446 }
6447
6448 static void cpt_init_clock_gating(struct drm_device *dev)
6449 {
6450         struct drm_i915_private *dev_priv = dev->dev_private;
6451         int pipe;
6452         uint32_t val;
6453
6454         /*
6455          * On Ibex Peak and Cougar Point, we need to disable clock
6456          * gating for the panel power sequencer or it will fail to
6457          * start up when no ports are active.
6458          */
6459         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6460                    PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6461                    PCH_CPUNIT_CLOCK_GATE_DISABLE);
6462         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6463                    DPLS_EDP_PPS_FIX_DIS);
6464         /* The below fixes the weird display corruption, a few pixels shifted
6465          * downward, on (only) LVDS of some HP laptops with IVY.
6466          */
6467         for_each_pipe(dev_priv, pipe) {
6468                 val = I915_READ(TRANS_CHICKEN2(pipe));
6469                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6470                 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6471                 if (dev_priv->vbt.fdi_rx_polarity_inverted)
6472                         val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6473                 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
6474                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6475                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
6476                 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6477         }
6478         /* WADP0ClockGatingDisable */
6479         for_each_pipe(dev_priv, pipe) {
6480                 I915_WRITE(TRANS_CHICKEN1(pipe),
6481                            TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6482         }
6483 }
6484
6485 static void gen6_check_mch_setup(struct drm_device *dev)
6486 {
6487         struct drm_i915_private *dev_priv = dev->dev_private;
6488         uint32_t tmp;
6489
6490         tmp = I915_READ(MCH_SSKPD);
6491         if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
6492                 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
6493                               tmp);
6494 }
6495
6496 static void gen6_init_clock_gating(struct drm_device *dev)
6497 {
6498         struct drm_i915_private *dev_priv = dev->dev_private;
6499         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6500
6501         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6502
6503         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6504                    I915_READ(ILK_DISPLAY_CHICKEN2) |
6505                    ILK_ELPIN_409_SELECT);
6506
6507         /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
6508         I915_WRITE(_3D_CHICKEN,
6509                    _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
6510
6511         /* WaDisable_RenderCache_OperationalFlush:snb */
6512         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6513
6514         /*
6515          * BSpec recoomends 8x4 when MSAA is used,
6516          * however in practice 16x4 seems fastest.
6517          *
6518          * Note that PS/WM thread counts depend on the WIZ hashing
6519          * disable bit, which we don't touch here, but it's good
6520          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6521          */
6522         I915_WRITE(GEN6_GT_MODE,
6523                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6524
6525         ilk_init_lp_watermarks(dev);
6526
6527         I915_WRITE(CACHE_MODE_0,
6528                    _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6529
6530         I915_WRITE(GEN6_UCGCTL1,
6531                    I915_READ(GEN6_UCGCTL1) |
6532                    GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
6533                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6534
6535         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
6536          * gating disable must be set.  Failure to set it results in
6537          * flickering pixels due to Z write ordering failures after
6538          * some amount of runtime in the Mesa "fire" demo, and Unigine
6539          * Sanctuary and Tropics, and apparently anything else with
6540          * alpha test or pixel discard.
6541          *
6542          * According to the spec, bit 11 (RCCUNIT) must also be set,
6543          * but we didn't debug actual testcases to find it out.
6544          *
6545          * WaDisableRCCUnitClockGating:snb
6546          * WaDisableRCPBUnitClockGating:snb
6547          */
6548         I915_WRITE(GEN6_UCGCTL2,
6549                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
6550                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
6551
6552         /* WaStripsFansDisableFastClipPerformanceFix:snb */
6553         I915_WRITE(_3D_CHICKEN3,
6554                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6555
6556         /*
6557          * Bspec says:
6558          * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
6559          * 3DSTATE_SF number of SF output attributes is more than 16."
6560          */
6561         I915_WRITE(_3D_CHICKEN3,
6562                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
6563
6564         /*
6565          * According to the spec the following bits should be
6566          * set in order to enable memory self-refresh and fbc:
6567          * The bit21 and bit22 of 0x42000
6568          * The bit21 and bit22 of 0x42004
6569          * The bit5 and bit7 of 0x42020
6570          * The bit14 of 0x70180
6571          * The bit14 of 0x71180
6572          *
6573          * WaFbcAsynchFlipDisableFbcQueue:snb
6574          */
6575         I915_WRITE(ILK_DISPLAY_CHICKEN1,
6576                    I915_READ(ILK_DISPLAY_CHICKEN1) |
6577                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
6578         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6579                    I915_READ(ILK_DISPLAY_CHICKEN2) |
6580                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
6581         I915_WRITE(ILK_DSPCLK_GATE_D,
6582                    I915_READ(ILK_DSPCLK_GATE_D) |
6583                    ILK_DPARBUNIT_CLOCK_GATE_ENABLE  |
6584                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6585
6586         g4x_disable_trickle_feed(dev);
6587
6588         cpt_init_clock_gating(dev);
6589
6590         gen6_check_mch_setup(dev);
6591 }
6592
6593 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
6594 {
6595         uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
6596
6597         /*
6598          * WaVSThreadDispatchOverride:ivb,vlv
6599          *
6600          * This actually overrides the dispatch
6601          * mode for all thread types.
6602          */
6603         reg &= ~GEN7_FF_SCHED_MASK;
6604         reg |= GEN7_FF_TS_SCHED_HW;
6605         reg |= GEN7_FF_VS_SCHED_HW;
6606         reg |= GEN7_FF_DS_SCHED_HW;
6607
6608         I915_WRITE(GEN7_FF_THREAD_MODE, reg);
6609 }
6610
6611 static void lpt_init_clock_gating(struct drm_device *dev)
6612 {
6613         struct drm_i915_private *dev_priv = dev->dev_private;
6614
6615         /*
6616          * TODO: this bit should only be enabled when really needed, then
6617          * disabled when not needed anymore in order to save power.
6618          */
6619         if (HAS_PCH_LPT_LP(dev))
6620                 I915_WRITE(SOUTH_DSPCLK_GATE_D,
6621                            I915_READ(SOUTH_DSPCLK_GATE_D) |
6622                            PCH_LP_PARTITION_LEVEL_DISABLE);
6623
6624         /* WADPOClockGatingDisable:hsw */
6625         I915_WRITE(TRANS_CHICKEN1(PIPE_A),
6626                    I915_READ(TRANS_CHICKEN1(PIPE_A)) |
6627                    TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6628 }
6629
6630 static void lpt_suspend_hw(struct drm_device *dev)
6631 {
6632         struct drm_i915_private *dev_priv = dev->dev_private;
6633
6634         if (HAS_PCH_LPT_LP(dev)) {
6635                 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
6636
6637                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6638                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6639         }
6640 }
6641
6642 static void broadwell_init_clock_gating(struct drm_device *dev)
6643 {
6644         struct drm_i915_private *dev_priv = dev->dev_private;
6645         enum pipe pipe;
6646         uint32_t misccpctl;
6647
6648         ilk_init_lp_watermarks(dev);
6649
6650         /* WaSwitchSolVfFArbitrationPriority:bdw */
6651         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6652
6653         /* WaPsrDPAMaskVBlankInSRD:bdw */
6654         I915_WRITE(CHICKEN_PAR1_1,
6655                    I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
6656
6657         /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
6658         for_each_pipe(dev_priv, pipe) {
6659                 I915_WRITE(CHICKEN_PIPESL_1(pipe),
6660                            I915_READ(CHICKEN_PIPESL_1(pipe)) |
6661                            BDW_DPRS_MASK_VBLANK_SRD);
6662         }
6663
6664         /* WaVSRefCountFullforceMissDisable:bdw */
6665         /* WaDSRefCountFullforceMissDisable:bdw */
6666         I915_WRITE(GEN7_FF_THREAD_MODE,
6667                    I915_READ(GEN7_FF_THREAD_MODE) &
6668                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
6669
6670         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6671                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
6672
6673         /* WaDisableSDEUnitClockGating:bdw */
6674         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6675                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6676
6677         /*
6678          * WaProgramL3SqcReg1Default:bdw
6679          * WaTempDisableDOPClkGating:bdw
6680          */
6681         misccpctl = I915_READ(GEN7_MISCCPCTL);
6682         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
6683         I915_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT);
6684         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
6685
6686         /*
6687          * WaGttCachingOffByDefault:bdw
6688          * GTT cache may not work with big pages, so if those
6689          * are ever enabled GTT cache may need to be disabled.
6690          */
6691         I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
6692
6693         lpt_init_clock_gating(dev);
6694 }
6695
6696 static void haswell_init_clock_gating(struct drm_device *dev)
6697 {
6698         struct drm_i915_private *dev_priv = dev->dev_private;
6699
6700         ilk_init_lp_watermarks(dev);
6701
6702         /* L3 caching of data atomics doesn't work -- disable it. */
6703         I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
6704         I915_WRITE(HSW_ROW_CHICKEN3,
6705                    _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
6706
6707         /* This is required by WaCatErrorRejectionIssue:hsw */
6708         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6709                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6710                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6711
6712         /* WaVSRefCountFullforceMissDisable:hsw */
6713         I915_WRITE(GEN7_FF_THREAD_MODE,
6714                    I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
6715
6716         /* WaDisable_RenderCache_OperationalFlush:hsw */
6717         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6718
6719         /* enable HiZ Raw Stall Optimization */
6720         I915_WRITE(CACHE_MODE_0_GEN7,
6721                    _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6722
6723         /* WaDisable4x2SubspanOptimization:hsw */
6724         I915_WRITE(CACHE_MODE_1,
6725                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6726
6727         /*
6728          * BSpec recommends 8x4 when MSAA is used,
6729          * however in practice 16x4 seems fastest.
6730          *
6731          * Note that PS/WM thread counts depend on the WIZ hashing
6732          * disable bit, which we don't touch here, but it's good
6733          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6734          */
6735         I915_WRITE(GEN7_GT_MODE,
6736                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6737
6738         /* WaSampleCChickenBitEnable:hsw */
6739         I915_WRITE(HALF_SLICE_CHICKEN3,
6740                    _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
6741
6742         /* WaSwitchSolVfFArbitrationPriority:hsw */
6743         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6744
6745         /* WaRsPkgCStateDisplayPMReq:hsw */
6746         I915_WRITE(CHICKEN_PAR1_1,
6747                    I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
6748
6749         lpt_init_clock_gating(dev);
6750 }
6751
6752 static void ivybridge_init_clock_gating(struct drm_device *dev)
6753 {
6754         struct drm_i915_private *dev_priv = dev->dev_private;
6755         uint32_t snpcr;
6756
6757         ilk_init_lp_watermarks(dev);
6758
6759         I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6760
6761         /* WaDisableEarlyCull:ivb */
6762         I915_WRITE(_3D_CHICKEN3,
6763                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6764
6765         /* WaDisableBackToBackFlipFix:ivb */
6766         I915_WRITE(IVB_CHICKEN3,
6767                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6768                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
6769
6770         /* WaDisablePSDDualDispatchEnable:ivb */
6771         if (IS_IVB_GT1(dev))
6772                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6773                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
6774
6775         /* WaDisable_RenderCache_OperationalFlush:ivb */
6776         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6777
6778         /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6779         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
6780                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
6781
6782         /* WaApplyL3ControlAndL3ChickenMode:ivb */
6783         I915_WRITE(GEN7_L3CNTLREG1,
6784                         GEN7_WA_FOR_GEN7_L3_CONTROL);
6785         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
6786                    GEN7_WA_L3_CHICKEN_MODE);
6787         if (IS_IVB_GT1(dev))
6788                 I915_WRITE(GEN7_ROW_CHICKEN2,
6789                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6790         else {
6791                 /* must write both registers */
6792                 I915_WRITE(GEN7_ROW_CHICKEN2,
6793                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6794                 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
6795                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6796         }
6797
6798         /* WaForceL3Serialization:ivb */
6799         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6800                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6801
6802         /*
6803          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
6804          * This implements the WaDisableRCZUnitClockGating:ivb workaround.
6805          */
6806         I915_WRITE(GEN6_UCGCTL2,
6807                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
6808
6809         /* This is required by WaCatErrorRejectionIssue:ivb */
6810         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6811                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6812                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6813
6814         g4x_disable_trickle_feed(dev);
6815
6816         gen7_setup_fixed_func_scheduler(dev_priv);
6817
6818         if (0) { /* causes HiZ corruption on ivb:gt1 */
6819                 /* enable HiZ Raw Stall Optimization */
6820                 I915_WRITE(CACHE_MODE_0_GEN7,
6821                            _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6822         }
6823
6824         /* WaDisable4x2SubspanOptimization:ivb */
6825         I915_WRITE(CACHE_MODE_1,
6826                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6827
6828         /*
6829          * BSpec recommends 8x4 when MSAA is used,
6830          * however in practice 16x4 seems fastest.
6831          *
6832          * Note that PS/WM thread counts depend on the WIZ hashing
6833          * disable bit, which we don't touch here, but it's good
6834          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6835          */
6836         I915_WRITE(GEN7_GT_MODE,
6837                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6838
6839         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
6840         snpcr &= ~GEN6_MBC_SNPCR_MASK;
6841         snpcr |= GEN6_MBC_SNPCR_MED;
6842         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
6843
6844         if (!HAS_PCH_NOP(dev))
6845                 cpt_init_clock_gating(dev);
6846
6847         gen6_check_mch_setup(dev);
6848 }
6849
6850 static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
6851 {
6852         I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6853
6854         /*
6855          * Disable trickle feed and enable pnd deadline calculation
6856          */
6857         I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6858         I915_WRITE(CBR1_VLV, 0);
6859 }
6860
6861 static void valleyview_init_clock_gating(struct drm_device *dev)
6862 {
6863         struct drm_i915_private *dev_priv = dev->dev_private;
6864
6865         vlv_init_display_clock_gating(dev_priv);
6866
6867         /* WaDisableEarlyCull:vlv */
6868         I915_WRITE(_3D_CHICKEN3,
6869                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6870
6871         /* WaDisableBackToBackFlipFix:vlv */
6872         I915_WRITE(IVB_CHICKEN3,
6873                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6874                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
6875
6876         /* WaPsdDispatchEnable:vlv */
6877         /* WaDisablePSDDualDispatchEnable:vlv */
6878         I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6879                    _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
6880                                       GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
6881
6882         /* WaDisable_RenderCache_OperationalFlush:vlv */
6883         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6884
6885         /* WaForceL3Serialization:vlv */
6886         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6887                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6888
6889         /* WaDisableDopClockGating:vlv */
6890         I915_WRITE(GEN7_ROW_CHICKEN2,
6891                    _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6892
6893         /* This is required by WaCatErrorRejectionIssue:vlv */
6894         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6895                    I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6896                    GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6897
6898         gen7_setup_fixed_func_scheduler(dev_priv);
6899
6900         /*
6901          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
6902          * This implements the WaDisableRCZUnitClockGating:vlv workaround.
6903          */
6904         I915_WRITE(GEN6_UCGCTL2,
6905                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
6906
6907         /* WaDisableL3Bank2xClockGate:vlv
6908          * Disabling L3 clock gating- MMIO 940c[25] = 1
6909          * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
6910         I915_WRITE(GEN7_UCGCTL4,
6911                    I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
6912
6913         /*
6914          * BSpec says this must be set, even though
6915          * WaDisable4x2SubspanOptimization isn't listed for VLV.
6916          */
6917         I915_WRITE(CACHE_MODE_1,
6918                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6919
6920         /*
6921          * BSpec recommends 8x4 when MSAA is used,
6922          * however in practice 16x4 seems fastest.
6923          *
6924          * Note that PS/WM thread counts depend on the WIZ hashing
6925          * disable bit, which we don't touch here, but it's good
6926          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6927          */
6928         I915_WRITE(GEN7_GT_MODE,
6929                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6930
6931         /*
6932          * WaIncreaseL3CreditsForVLVB0:vlv
6933          * This is the hardware default actually.
6934          */
6935         I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
6936
6937         /*
6938          * WaDisableVLVClockGating_VBIIssue:vlv
6939          * Disable clock gating on th GCFG unit to prevent a delay
6940          * in the reporting of vblank events.
6941          */
6942         I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6943 }
6944
6945 static void cherryview_init_clock_gating(struct drm_device *dev)
6946 {
6947         struct drm_i915_private *dev_priv = dev->dev_private;
6948
6949         vlv_init_display_clock_gating(dev_priv);
6950
6951         /* WaVSRefCountFullforceMissDisable:chv */
6952         /* WaDSRefCountFullforceMissDisable:chv */
6953         I915_WRITE(GEN7_FF_THREAD_MODE,
6954                    I915_READ(GEN7_FF_THREAD_MODE) &
6955                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
6956
6957         /* WaDisableSemaphoreAndSyncFlipWait:chv */
6958         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6959                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
6960
6961         /* WaDisableCSUnitClockGating:chv */
6962         I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
6963                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6964
6965         /* WaDisableSDEUnitClockGating:chv */
6966         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6967                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6968
6969         /*
6970          * GTT cache may not work with big pages, so if those
6971          * are ever enabled GTT cache may need to be disabled.
6972          */
6973         I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
6974 }
6975
6976 static void g4x_init_clock_gating(struct drm_device *dev)
6977 {
6978         struct drm_i915_private *dev_priv = dev->dev_private;
6979         uint32_t dspclk_gate;
6980
6981         I915_WRITE(RENCLK_GATE_D1, 0);
6982         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
6983                    GS_UNIT_CLOCK_GATE_DISABLE |
6984                    CL_UNIT_CLOCK_GATE_DISABLE);
6985         I915_WRITE(RAMCLK_GATE_D, 0);
6986         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
6987                 OVRUNIT_CLOCK_GATE_DISABLE |
6988                 OVCUNIT_CLOCK_GATE_DISABLE;
6989         if (IS_GM45(dev))
6990                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
6991         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
6992
6993         /* WaDisableRenderCachePipelinedFlush */
6994         I915_WRITE(CACHE_MODE_0,
6995                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
6996
6997         /* WaDisable_RenderCache_OperationalFlush:g4x */
6998         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6999
7000         g4x_disable_trickle_feed(dev);
7001 }
7002
7003 static void crestline_init_clock_gating(struct drm_device *dev)
7004 {
7005         struct drm_i915_private *dev_priv = dev->dev_private;
7006
7007         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7008         I915_WRITE(RENCLK_GATE_D2, 0);
7009         I915_WRITE(DSPCLK_GATE_D, 0);
7010         I915_WRITE(RAMCLK_GATE_D, 0);
7011         I915_WRITE16(DEUC, 0);
7012         I915_WRITE(MI_ARB_STATE,
7013                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7014
7015         /* WaDisable_RenderCache_OperationalFlush:gen4 */
7016         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7017 }
7018
7019 static void broadwater_init_clock_gating(struct drm_device *dev)
7020 {
7021         struct drm_i915_private *dev_priv = dev->dev_private;
7022
7023         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7024                    I965_RCC_CLOCK_GATE_DISABLE |
7025                    I965_RCPB_CLOCK_GATE_DISABLE |
7026                    I965_ISC_CLOCK_GATE_DISABLE |
7027                    I965_FBC_CLOCK_GATE_DISABLE);
7028         I915_WRITE(RENCLK_GATE_D2, 0);
7029         I915_WRITE(MI_ARB_STATE,
7030                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7031
7032         /* WaDisable_RenderCache_OperationalFlush:gen4 */
7033         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7034 }
7035
7036 static void gen3_init_clock_gating(struct drm_device *dev)
7037 {
7038         struct drm_i915_private *dev_priv = dev->dev_private;
7039         u32 dstate = I915_READ(D_STATE);
7040
7041         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7042                 DSTATE_DOT_CLOCK_GATING;
7043         I915_WRITE(D_STATE, dstate);
7044
7045         if (IS_PINEVIEW(dev))
7046                 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
7047
7048         /* IIR "flip pending" means done if this bit is set */
7049         I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
7050
7051         /* interrupts should cause a wake up from C3 */
7052         I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
7053
7054         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
7055         I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
7056
7057         I915_WRITE(MI_ARB_STATE,
7058                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7059 }
7060
7061 static void i85x_init_clock_gating(struct drm_device *dev)
7062 {
7063         struct drm_i915_private *dev_priv = dev->dev_private;
7064
7065         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
7066
7067         /* interrupts should cause a wake up from C3 */
7068         I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
7069                    _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
7070
7071         I915_WRITE(MEM_MODE,
7072                    _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
7073 }
7074
7075 static void i830_init_clock_gating(struct drm_device *dev)
7076 {
7077         struct drm_i915_private *dev_priv = dev->dev_private;
7078
7079         I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
7080
7081         I915_WRITE(MEM_MODE,
7082                    _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
7083                    _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
7084 }
7085
7086 void intel_init_clock_gating(struct drm_device *dev)
7087 {
7088         struct drm_i915_private *dev_priv = dev->dev_private;
7089
7090         if (dev_priv->display.init_clock_gating)
7091                 dev_priv->display.init_clock_gating(dev);
7092 }
7093
7094 void intel_suspend_hw(struct drm_device *dev)
7095 {
7096         if (HAS_PCH_LPT(dev))
7097                 lpt_suspend_hw(dev);
7098 }
7099
7100 /* Set up chip specific power management-related functions */
7101 void intel_init_pm(struct drm_device *dev)
7102 {
7103         struct drm_i915_private *dev_priv = dev->dev_private;
7104
7105         intel_fbc_init(dev_priv);
7106
7107         /* For cxsr */
7108         if (IS_PINEVIEW(dev))
7109                 i915_pineview_get_mem_freq(dev);
7110         else if (IS_GEN5(dev))
7111                 i915_ironlake_get_mem_freq(dev);
7112
7113         /* For FIFO watermark updates */
7114         if (INTEL_INFO(dev)->gen >= 9) {
7115                 skl_setup_wm_latency(dev);
7116
7117                 if (IS_BROXTON(dev))
7118                         dev_priv->display.init_clock_gating =
7119                                 bxt_init_clock_gating;
7120                 dev_priv->display.update_wm = skl_update_wm;
7121         } else if (HAS_PCH_SPLIT(dev)) {
7122                 ilk_setup_wm_latency(dev);
7123
7124                 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
7125                      dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7126                     (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
7127                      dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
7128                         dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
7129                         dev_priv->display.compute_intermediate_wm =
7130                                 ilk_compute_intermediate_wm;
7131                         dev_priv->display.initial_watermarks =
7132                                 ilk_initial_watermarks;
7133                         dev_priv->display.optimize_watermarks =
7134                                 ilk_optimize_watermarks;
7135                 } else {
7136                         DRM_DEBUG_KMS("Failed to read display plane latency. "
7137                                       "Disable CxSR\n");
7138                 }
7139
7140                 if (IS_GEN5(dev))
7141                         dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7142                 else if (IS_GEN6(dev))
7143                         dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7144                 else if (IS_IVYBRIDGE(dev))
7145                         dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7146                 else if (IS_HASWELL(dev))
7147                         dev_priv->display.init_clock_gating = haswell_init_clock_gating;
7148                 else if (INTEL_INFO(dev)->gen == 8)
7149                         dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
7150         } else if (IS_CHERRYVIEW(dev)) {
7151                 vlv_setup_wm_latency(dev);
7152
7153                 dev_priv->display.update_wm = vlv_update_wm;
7154                 dev_priv->display.init_clock_gating =
7155                         cherryview_init_clock_gating;
7156         } else if (IS_VALLEYVIEW(dev)) {
7157                 vlv_setup_wm_latency(dev);
7158
7159                 dev_priv->display.update_wm = vlv_update_wm;
7160                 dev_priv->display.init_clock_gating =
7161                         valleyview_init_clock_gating;
7162         } else if (IS_PINEVIEW(dev)) {
7163                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7164                                             dev_priv->is_ddr3,
7165                                             dev_priv->fsb_freq,
7166                                             dev_priv->mem_freq)) {
7167                         DRM_INFO("failed to find known CxSR latency "
7168                                  "(found ddr%s fsb freq %d, mem freq %d), "
7169                                  "disabling CxSR\n",
7170                                  (dev_priv->is_ddr3 == 1) ? "3" : "2",
7171                                  dev_priv->fsb_freq, dev_priv->mem_freq);
7172                         /* Disable CxSR and never update its watermark again */
7173                         intel_set_memory_cxsr(dev_priv, false);
7174                         dev_priv->display.update_wm = NULL;
7175                 } else
7176                         dev_priv->display.update_wm = pineview_update_wm;
7177                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7178         } else if (IS_G4X(dev)) {
7179                 dev_priv->display.update_wm = g4x_update_wm;
7180                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7181         } else if (IS_GEN4(dev)) {
7182                 dev_priv->display.update_wm = i965_update_wm;
7183                 if (IS_CRESTLINE(dev))
7184                         dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7185                 else if (IS_BROADWATER(dev))
7186                         dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7187         } else if (IS_GEN3(dev)) {
7188                 dev_priv->display.update_wm = i9xx_update_wm;
7189                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7190                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7191         } else if (IS_GEN2(dev)) {
7192                 if (INTEL_INFO(dev)->num_pipes == 1) {
7193                         dev_priv->display.update_wm = i845_update_wm;
7194                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
7195                 } else {
7196                         dev_priv->display.update_wm = i9xx_update_wm;
7197                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
7198                 }
7199
7200                 if (IS_I85X(dev) || IS_I865G(dev))
7201                         dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7202                 else
7203                         dev_priv->display.init_clock_gating = i830_init_clock_gating;
7204         } else {
7205                 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
7206         }
7207 }
7208
7209 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
7210 {
7211         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7212
7213         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7214                 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7215                 return -EAGAIN;
7216         }
7217
7218         I915_WRITE(GEN6_PCODE_DATA, *val);
7219         I915_WRITE(GEN6_PCODE_DATA1, 0);
7220         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7221
7222         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7223                      500)) {
7224                 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7225                 return -ETIMEDOUT;
7226         }
7227
7228         *val = I915_READ(GEN6_PCODE_DATA);
7229         I915_WRITE(GEN6_PCODE_DATA, 0);
7230
7231         return 0;
7232 }
7233
7234 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val)
7235 {
7236         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7237
7238         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7239                 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7240                 return -EAGAIN;
7241         }
7242
7243         I915_WRITE(GEN6_PCODE_DATA, val);
7244         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7245
7246         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7247                      500)) {
7248                 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7249                 return -ETIMEDOUT;
7250         }
7251
7252         I915_WRITE(GEN6_PCODE_DATA, 0);
7253
7254         return 0;
7255 }
7256
7257 static int vlv_gpu_freq_div(unsigned int czclk_freq)
7258 {
7259         switch (czclk_freq) {
7260         case 200:
7261                 return 10;
7262         case 267:
7263                 return 12;
7264         case 320:
7265         case 333:
7266                 return 16;
7267         case 400:
7268                 return 20;
7269         default:
7270                 return -1;
7271         }
7272 }
7273
7274 static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7275 {
7276         int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
7277
7278         div = vlv_gpu_freq_div(czclk_freq);
7279         if (div < 0)
7280                 return div;
7281
7282         return DIV_ROUND_CLOSEST(czclk_freq * (val + 6 - 0xbd), div);
7283 }
7284
7285 static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
7286 {
7287         int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
7288
7289         mul = vlv_gpu_freq_div(czclk_freq);
7290         if (mul < 0)
7291                 return mul;
7292
7293         return DIV_ROUND_CLOSEST(mul * val, czclk_freq) + 0xbd - 6;
7294 }
7295
7296 static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
7297 {
7298         int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
7299
7300         div = vlv_gpu_freq_div(czclk_freq);
7301         if (div < 0)
7302                 return div;
7303         div /= 2;
7304
7305         return DIV_ROUND_CLOSEST(czclk_freq * val, 2 * div) / 2;
7306 }
7307
7308 static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
7309 {
7310         int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
7311
7312         mul = vlv_gpu_freq_div(czclk_freq);
7313         if (mul < 0)
7314                 return mul;
7315         mul /= 2;
7316
7317         /* CHV needs even values */
7318         return DIV_ROUND_CLOSEST(val * 2 * mul, czclk_freq) * 2;
7319 }
7320
7321 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
7322 {
7323         if (IS_GEN9(dev_priv->dev))
7324                 return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
7325                                          GEN9_FREQ_SCALER);
7326         else if (IS_CHERRYVIEW(dev_priv->dev))
7327                 return chv_gpu_freq(dev_priv, val);
7328         else if (IS_VALLEYVIEW(dev_priv->dev))
7329                 return byt_gpu_freq(dev_priv, val);
7330         else
7331                 return val * GT_FREQUENCY_MULTIPLIER;
7332 }
7333
7334 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
7335 {
7336         if (IS_GEN9(dev_priv->dev))
7337                 return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
7338                                          GT_FREQUENCY_MULTIPLIER);
7339         else if (IS_CHERRYVIEW(dev_priv->dev))
7340                 return chv_freq_opcode(dev_priv, val);
7341         else if (IS_VALLEYVIEW(dev_priv->dev))
7342                 return byt_freq_opcode(dev_priv, val);
7343         else
7344                 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
7345 }
7346
7347 struct request_boost {
7348         struct work_struct work;
7349         struct drm_i915_gem_request *req;
7350 };
7351
7352 static void __intel_rps_boost_work(struct work_struct *work)
7353 {
7354         struct request_boost *boost = container_of(work, struct request_boost, work);
7355         struct drm_i915_gem_request *req = boost->req;
7356
7357         if (!i915_gem_request_completed(req, true))
7358                 gen6_rps_boost(to_i915(req->ring->dev), NULL,
7359                                req->emitted_jiffies);
7360
7361         i915_gem_request_unreference__unlocked(req);
7362         kfree(boost);
7363 }
7364
7365 void intel_queue_rps_boost_for_request(struct drm_device *dev,
7366                                        struct drm_i915_gem_request *req)
7367 {
7368         struct request_boost *boost;
7369
7370         if (req == NULL || INTEL_INFO(dev)->gen < 6)
7371                 return;
7372
7373         if (i915_gem_request_completed(req, true))
7374                 return;
7375
7376         boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
7377         if (boost == NULL)
7378                 return;
7379
7380         i915_gem_request_reference(req);
7381         boost->req = req;
7382
7383         INIT_WORK(&boost->work, __intel_rps_boost_work);
7384         queue_work(to_i915(dev)->wq, &boost->work);
7385 }
7386
7387 void intel_pm_setup(struct drm_device *dev)
7388 {
7389         struct drm_i915_private *dev_priv = dev->dev_private;
7390
7391         mutex_init(&dev_priv->rps.hw_lock);
7392         spin_lock_init(&dev_priv->rps.client_lock);
7393
7394         INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
7395                           intel_gen6_powersave_work);
7396         INIT_LIST_HEAD(&dev_priv->rps.clients);
7397         INIT_LIST_HEAD(&dev_priv->rps.semaphores.link);
7398         INIT_LIST_HEAD(&dev_priv->rps.mmioflips.link);
7399
7400         dev_priv->pm.suspended = false;
7401         atomic_set(&dev_priv->pm.wakeref_count, 0);
7402         atomic_set(&dev_priv->pm.atomic_seq, 0);
7403 }