drivers/gpu/drm/i915/intel_pm.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <linux/cpufreq.h>
  29 #include <drm/drm_plane_helper.h>
  30 #include "i915_drv.h"
  31 #include "intel_drv.h"
  32 #include "../../../platform/x86/intel_ips.h"
  33 #include <linux/module.h>
  34
  35 /**
  36  * DOC: RC6
  37  *
  38  * RC6 is a special power stage which allows the GPU to enter an very
  39  * low-voltage mode when idle, using down to 0V while at this stage.  This
  40  * stage is entered automatically when the GPU is idle when RC6 support is
  41  * enabled, and as soon as new workload arises GPU wakes up automatically as well.
  42  *
  43  * There are different RC6 modes available in Intel GPU, which differentiate
  44  * among each other with the latency required to enter and leave RC6 and
  45  * voltage consumed by the GPU in different states.
  46  *
  47  * The combination of the following flags define which states GPU is allowed
  48  * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
  49  * RC6pp is deepest RC6. Their support by hardware varies according to the
  50  * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
  51  * which brings the most power savings; deeper states save more power, but
  52  * require higher latency to switch to and wake up.
  53  */
  54 #define INTEL_RC6_ENABLE                        (1<<0)
  55 #define INTEL_RC6p_ENABLE                       (1<<1)
  56 #define INTEL_RC6pp_ENABLE                      (1<<2)
  57
  58 static void gen9_init_clock_gating(struct drm_device *dev)
  59 {
  60         struct drm_i915_private *dev_priv = dev->dev_private;
  61
  62         /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl */
  63         I915_WRITE(CHICKEN_PAR1_1,
  64                    I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
  65
  66         I915_WRITE(GEN8_CONFIG0,
  67                    I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES);
  68 }
  69
  70 static void bxt_init_clock_gating(struct drm_device *dev)
  71 {
  72         struct drm_i915_private *dev_priv = dev->dev_private;
  73
  74         gen9_init_clock_gating(dev);
  75
  76         /* WaDisableSDEUnitClockGating:bxt */
  77         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
  78                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
  79
  80         /*
  81          * FIXME:
  82          * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
  83          */
  84         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
  85                    GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
  86
  87         /*
  88          * Wa: Backlight PWM may stop in the asserted state, causing backlight
  89          * to stay fully on.
  90          */
  91         if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
  92                 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
  93                            PWM1_GATING_DIS | PWM2_GATING_DIS);
  94 }
  95
  96 static void i915_pineview_get_mem_freq(struct drm_device *dev)
  97 {
  98         struct drm_i915_private *dev_priv = dev->dev_private;
  99         u32 tmp;
 100
 101         tmp = I915_READ(CLKCFG);
 102
 103         switch (tmp & CLKCFG_FSB_MASK) {
 104         case CLKCFG_FSB_533:
 105                 dev_priv->fsb_freq = 533; /* 133*4 */
 106                 break;
 107         case CLKCFG_FSB_800:
 108                 dev_priv->fsb_freq = 800; /* 200*4 */
 109                 break;
 110         case CLKCFG_FSB_667:
 111                 dev_priv->fsb_freq =  667; /* 167*4 */
 112                 break;
 113         case CLKCFG_FSB_400:
 114                 dev_priv->fsb_freq = 400; /* 100*4 */
 115                 break;
 116         }
 117
 118         switch (tmp & CLKCFG_MEM_MASK) {
 119         case CLKCFG_MEM_533:
 120                 dev_priv->mem_freq = 533;
 121                 break;
 122         case CLKCFG_MEM_667:
 123                 dev_priv->mem_freq = 667;
 124                 break;
 125         case CLKCFG_MEM_800:
 126                 dev_priv->mem_freq = 800;
 127                 break;
 128         }
 129
 130         /* detect pineview DDR3 setting */
 131         tmp = I915_READ(CSHRDDR3CTL);
 132         dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
 133 }
 134
 135 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
 136 {
 137         struct drm_i915_private *dev_priv = dev->dev_private;
 138         u16 ddrpll, csipll;
 139
 140         ddrpll = I915_READ16(DDRMPLL1);
 141         csipll = I915_READ16(CSIPLL0);
 142
 143         switch (ddrpll & 0xff) {
 144         case 0xc:
 145                 dev_priv->mem_freq = 800;
 146                 break;
 147         case 0x10:
 148                 dev_priv->mem_freq = 1066;
 149                 break;
 150         case 0x14:
 151                 dev_priv->mem_freq = 1333;
 152                 break;
 153         case 0x18:
 154                 dev_priv->mem_freq = 1600;
 155                 break;
 156         default:
 157                 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
 158                                  ddrpll & 0xff);
 159                 dev_priv->mem_freq = 0;
 160                 break;
 161         }
 162
 163         dev_priv->ips.r_t = dev_priv->mem_freq;
 164
 165         switch (csipll & 0x3ff) {
 166         case 0x00c:
 167                 dev_priv->fsb_freq = 3200;
 168                 break;
 169         case 0x00e:
 170                 dev_priv->fsb_freq = 3733;
 171                 break;
 172         case 0x010:
 173                 dev_priv->fsb_freq = 4266;
 174                 break;
 175         case 0x012:
 176                 dev_priv->fsb_freq = 4800;
 177                 break;
 178         case 0x014:
 179                 dev_priv->fsb_freq = 5333;
 180                 break;
 181         case 0x016:
 182                 dev_priv->fsb_freq = 5866;
 183                 break;
 184         case 0x018:
 185                 dev_priv->fsb_freq = 6400;
 186                 break;
 187         default:
 188                 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
 189                                  csipll & 0x3ff);
 190                 dev_priv->fsb_freq = 0;
 191                 break;
 192         }
 193
 194         if (dev_priv->fsb_freq == 3200) {
 195                 dev_priv->ips.c_m = 0;
 196         } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
 197                 dev_priv->ips.c_m = 1;
 198         } else {
 199                 dev_priv->ips.c_m = 2;
 200         }
 201 }
 202
 203 static const struct cxsr_latency cxsr_latency_table[] = {
 204         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
 205         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
 206         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
 207         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
 208         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
 209
 210         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
 211         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
 212         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
 213         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
 214         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
 215
 216         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
 217         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
 218         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
 219         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
 220         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
 221
 222         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
 223         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
 224         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
 225         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
 226         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
 227
 228         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
 229         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
 230         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
 231         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
 232         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
 233
 234         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
 235         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
 236         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
 237         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
 238         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
 239 };
 240
 241 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
 242                                                          int is_ddr3,
 243                                                          int fsb,
 244                                                          int mem)
 245 {
 246         const struct cxsr_latency *latency;
 247         int i;
 248
 249         if (fsb == 0 || mem == 0)
 250                 return NULL;
 251
 252         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
 253                 latency = &cxsr_latency_table[i];
 254                 if (is_desktop == latency->is_desktop &&
 255                     is_ddr3 == latency->is_ddr3 &&
 256                     fsb == latency->fsb_freq && mem == latency->mem_freq)
 257                         return latency;
 258         }
 259
 260         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 261
 262         return NULL;
 263 }
 264
 265 static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
 266 {
 267         u32 val;
 268
 269         mutex_lock(&dev_priv->rps.hw_lock);
 270
 271         val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
 272         if (enable)
 273                 val &= ~FORCE_DDR_HIGH_FREQ;
 274         else
 275                 val |= FORCE_DDR_HIGH_FREQ;
 276         val &= ~FORCE_DDR_LOW_FREQ;
 277         val |= FORCE_DDR_FREQ_REQ_ACK;
 278         vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
 279
 280         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
 281                       FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
 282                 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
 283
 284         mutex_unlock(&dev_priv->rps.hw_lock);
 285 }
 286
 287 static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
 288 {
 289         u32 val;
 290
 291         mutex_lock(&dev_priv->rps.hw_lock);
 292
 293         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
 294         if (enable)
 295                 val |= DSP_MAXFIFO_PM5_ENABLE;
 296         else
 297                 val &= ~DSP_MAXFIFO_PM5_ENABLE;
 298         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
 299
 300         mutex_unlock(&dev_priv->rps.hw_lock);
 301 }
 302
 303 #define FW_WM(value, plane) \
 304         (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
 305
 306 void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
 307 {
 308         struct drm_device *dev = dev_priv->dev;
 309         u32 val;
 310
 311         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 312                 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
 313                 POSTING_READ(FW_BLC_SELF_VLV);
 314                 dev_priv->wm.vlv.cxsr = enable;
 315         } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
 316                 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
 317                 POSTING_READ(FW_BLC_SELF);
 318         } else if (IS_PINEVIEW(dev)) {
 319                 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
 320                 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
 321                 I915_WRITE(DSPFW3, val);
 322                 POSTING_READ(DSPFW3);
 323         } else if (IS_I945G(dev) || IS_I945GM(dev)) {
 324                 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
 325                                _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
 326                 I915_WRITE(FW_BLC_SELF, val);
 327                 POSTING_READ(FW_BLC_SELF);
 328         } else if (IS_I915GM(dev)) {
 329                 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
 330                                _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
 331                 I915_WRITE(INSTPM, val);
 332                 POSTING_READ(INSTPM);
 333         } else {
 334                 return;
 335         }
 336
 337         DRM_DEBUG_KMS("memory self-refresh is %s\n",
 338                       enable ? "enabled" : "disabled");
 339 }
 340
 341
 342 /*
 343  * Latency for FIFO fetches is dependent on several factors:
 344  *   - memory configuration (speed, channels)
 345  *   - chipset
 346  *   - current MCH state
 347  * It can be fairly high in some situations, so here we assume a fairly
 348  * pessimal value.  It's a tradeoff between extra memory fetches (if we
 349  * set this value too high, the FIFO will fetch frequently to stay full)
 350  * and power consumption (set it too low to save power and we might see
 351  * FIFO underruns and display "flicker").
 352  *
 353  * A value of 5us seems to be a good balance; safe for very low end
 354  * platforms but not overly aggressive on lower latency configs.
 355  */
 356 static const int pessimal_latency_ns = 5000;
 357
 358 #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
 359         ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
 360
 361 static int vlv_get_fifo_size(struct drm_device *dev,
 362                               enum pipe pipe, int plane)
 363 {
 364         struct drm_i915_private *dev_priv = dev->dev_private;
 365         int sprite0_start, sprite1_start, size;
 366
 367         switch (pipe) {
 368                 uint32_t dsparb, dsparb2, dsparb3;
 369         case PIPE_A:
 370                 dsparb = I915_READ(DSPARB);
 371                 dsparb2 = I915_READ(DSPARB2);
 372                 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
 373                 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
 374                 break;
 375         case PIPE_B:
 376                 dsparb = I915_READ(DSPARB);
 377                 dsparb2 = I915_READ(DSPARB2);
 378                 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
 379                 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
 380                 break;
 381         case PIPE_C:
 382                 dsparb2 = I915_READ(DSPARB2);
 383                 dsparb3 = I915_READ(DSPARB3);
 384                 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
 385                 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
 386                 break;
 387         default:
 388                 return 0;
 389         }
 390
 391         switch (plane) {
 392         case 0:
 393                 size = sprite0_start;
 394                 break;
 395         case 1:
 396                 size = sprite1_start - sprite0_start;
 397                 break;
 398         case 2:
 399                 size = 512 - 1 - sprite1_start;
 400                 break;
 401         default:
 402                 return 0;
 403         }
 404
 405         DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
 406                       pipe_name(pipe), plane == 0 ? "primary" : "sprite",
 407                       plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
 408                       size);
 409
 410         return size;
 411 }
 412
 413 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
 414 {
 415         struct drm_i915_private *dev_priv = dev->dev_private;
 416         uint32_t dsparb = I915_READ(DSPARB);
 417         int size;
 418
 419         size = dsparb & 0x7f;
 420         if (plane)
 421                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
 422
 423         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 424                       plane ? "B" : "A", size);
 425
 426         return size;
 427 }
 428
 429 static int i830_get_fifo_size(struct drm_device *dev, int plane)
 430 {
 431         struct drm_i915_private *dev_priv = dev->dev_private;
 432         uint32_t dsparb = I915_READ(DSPARB);
 433         int size;
 434
 435         size = dsparb & 0x1ff;
 436         if (plane)
 437                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
 438         size >>= 1; /* Convert to cachelines */
 439
 440         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 441                       plane ? "B" : "A", size);
 442
 443         return size;
 444 }
 445
 446 static int i845_get_fifo_size(struct drm_device *dev, int plane)
 447 {
 448         struct drm_i915_private *dev_priv = dev->dev_private;
 449         uint32_t dsparb = I915_READ(DSPARB);
 450         int size;
 451
 452         size = dsparb & 0x7f;
 453         size >>= 2; /* Convert to cachelines */
 454
 455         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 456                       plane ? "B" : "A",
 457                       size);
 458
 459         return size;
 460 }
 461
 462 /* Pineview has different values for various configs */
 463 static const struct intel_watermark_params pineview_display_wm = {
 464         .fifo_size = PINEVIEW_DISPLAY_FIFO,
 465         .max_wm = PINEVIEW_MAX_WM,
 466         .default_wm = PINEVIEW_DFT_WM,
 467         .guard_size = PINEVIEW_GUARD_WM,
 468         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 469 };
 470 static const struct intel_watermark_params pineview_display_hplloff_wm = {
 471         .fifo_size = PINEVIEW_DISPLAY_FIFO,
 472         .max_wm = PINEVIEW_MAX_WM,
 473         .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
 474         .guard_size = PINEVIEW_GUARD_WM,
 475         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 476 };
 477 static const struct intel_watermark_params pineview_cursor_wm = {
 478         .fifo_size = PINEVIEW_CURSOR_FIFO,
 479         .max_wm = PINEVIEW_CURSOR_MAX_WM,
 480         .default_wm = PINEVIEW_CURSOR_DFT_WM,
 481         .guard_size = PINEVIEW_CURSOR_GUARD_WM,
 482         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 483 };
 484 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
 485         .fifo_size = PINEVIEW_CURSOR_FIFO,
 486         .max_wm = PINEVIEW_CURSOR_MAX_WM,
 487         .default_wm = PINEVIEW_CURSOR_DFT_WM,
 488         .guard_size = PINEVIEW_CURSOR_GUARD_WM,
 489         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 490 };
 491 static const struct intel_watermark_params g4x_wm_info = {
 492         .fifo_size = G4X_FIFO_SIZE,
 493         .max_wm = G4X_MAX_WM,
 494         .default_wm = G4X_MAX_WM,
 495         .guard_size = 2,
 496         .cacheline_size = G4X_FIFO_LINE_SIZE,
 497 };
 498 static const struct intel_watermark_params g4x_cursor_wm_info = {
 499         .fifo_size = I965_CURSOR_FIFO,
 500         .max_wm = I965_CURSOR_MAX_WM,
 501         .default_wm = I965_CURSOR_DFT_WM,
 502         .guard_size = 2,
 503         .cacheline_size = G4X_FIFO_LINE_SIZE,
 504 };
 505 static const struct intel_watermark_params i965_cursor_wm_info = {
 506         .fifo_size = I965_CURSOR_FIFO,
 507         .max_wm = I965_CURSOR_MAX_WM,
 508         .default_wm = I965_CURSOR_DFT_WM,
 509         .guard_size = 2,
 510         .cacheline_size = I915_FIFO_LINE_SIZE,
 511 };
 512 static const struct intel_watermark_params i945_wm_info = {
 513         .fifo_size = I945_FIFO_SIZE,
 514         .max_wm = I915_MAX_WM,
 515         .default_wm = 1,
 516         .guard_size = 2,
 517         .cacheline_size = I915_FIFO_LINE_SIZE,
 518 };
 519 static const struct intel_watermark_params i915_wm_info = {
 520         .fifo_size = I915_FIFO_SIZE,
 521         .max_wm = I915_MAX_WM,
 522         .default_wm = 1,
 523         .guard_size = 2,
 524         .cacheline_size = I915_FIFO_LINE_SIZE,
 525 };
 526 static const struct intel_watermark_params i830_a_wm_info = {
 527         .fifo_size = I855GM_FIFO_SIZE,
 528         .max_wm = I915_MAX_WM,
 529         .default_wm = 1,
 530         .guard_size = 2,
 531         .cacheline_size = I830_FIFO_LINE_SIZE,
 532 };
 533 static const struct intel_watermark_params i830_bc_wm_info = {
 534         .fifo_size = I855GM_FIFO_SIZE,
 535         .max_wm = I915_MAX_WM/2,
 536         .default_wm = 1,
 537         .guard_size = 2,
 538         .cacheline_size = I830_FIFO_LINE_SIZE,
 539 };
 540 static const struct intel_watermark_params i845_wm_info = {
 541         .fifo_size = I830_FIFO_SIZE,
 542         .max_wm = I915_MAX_WM,
 543         .default_wm = 1,
 544         .guard_size = 2,
 545         .cacheline_size = I830_FIFO_LINE_SIZE,
 546 };
 547
 548 /**
 549  * intel_calculate_wm - calculate watermark level
 550  * @clock_in_khz: pixel clock
 551  * @wm: chip FIFO params
 552  * @cpp: bytes per pixel
 553  * @latency_ns: memory latency for the platform
 554  *
 555  * Calculate the watermark level (the level at which the display plane will
 556  * start fetching from memory again).  Each chip has a different display
 557  * FIFO size and allocation, so the caller needs to figure that out and pass
 558  * in the correct intel_watermark_params structure.
 559  *
 560  * As the pixel clock runs, the FIFO will be drained at a rate that depends
 561  * on the pixel size.  When it reaches the watermark level, it'll start
 562  * fetching FIFO line sized based chunks from memory until the FIFO fills
 563  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
 564  * will occur, and a display engine hang could result.
 565  */
 566 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
 567                                         const struct intel_watermark_params *wm,
 568                                         int fifo_size, int cpp,
 569                                         unsigned long latency_ns)
 570 {
 571         long entries_required, wm_size;
 572
 573         /*
 574          * Note: we need to make sure we don't overflow for various clock &
 575          * latency values.
 576          * clocks go from a few thousand to several hundred thousand.
 577          * latency is usually a few thousand
 578          */
 579         entries_required = ((clock_in_khz / 1000) * cpp * latency_ns) /
 580                 1000;
 581         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
 582
 583         DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
 584
 585         wm_size = fifo_size - (entries_required + wm->guard_size);
 586
 587         DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
 588
 589         /* Don't promote wm_size to unsigned... */
 590         if (wm_size > (long)wm->max_wm)
 591                 wm_size = wm->max_wm;
 592         if (wm_size <= 0)
 593                 wm_size = wm->default_wm;
 594
 595         /*
 596          * Bspec seems to indicate that the value shouldn't be lower than
 597          * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
 598          * Lets go for 8 which is the burst size since certain platforms
 599          * already use a hardcoded 8 (which is what the spec says should be
 600          * done).
 601          */
 602         if (wm_size <= 8)
 603                 wm_size = 8;
 604
 605         return wm_size;
 606 }
 607
 608 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
 609 {
 610         struct drm_crtc *crtc, *enabled = NULL;
 611
 612         for_each_crtc(dev, crtc) {
 613                 if (intel_crtc_active(crtc)) {
 614                         if (enabled)
 615                                 return NULL;
 616                         enabled = crtc;
 617                 }
 618         }
 619
 620         return enabled;
 621 }
 622
 623 static void pineview_update_wm(struct drm_crtc *unused_crtc)
 624 {
 625         struct drm_device *dev = unused_crtc->dev;
 626         struct drm_i915_private *dev_priv = dev->dev_private;
 627         struct drm_crtc *crtc;
 628         const struct cxsr_latency *latency;
 629         u32 reg;
 630         unsigned long wm;
 631
 632         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
 633                                          dev_priv->fsb_freq, dev_priv->mem_freq);
 634         if (!latency) {
 635                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 636                 intel_set_memory_cxsr(dev_priv, false);
 637                 return;
 638         }
 639
 640         crtc = single_enabled_crtc(dev);
 641         if (crtc) {
 642                 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
 643                 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
 644                 int clock = adjusted_mode->crtc_clock;
 645
 646                 /* Display SR */
 647                 wm = intel_calculate_wm(clock, &pineview_display_wm,
 648                                         pineview_display_wm.fifo_size,
 649                                         cpp, latency->display_sr);
 650                 reg = I915_READ(DSPFW1);
 651                 reg &= ~DSPFW_SR_MASK;
 652                 reg |= FW_WM(wm, SR);
 653                 I915_WRITE(DSPFW1, reg);
 654                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
 655
 656                 /* cursor SR */
 657                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
 658                                         pineview_display_wm.fifo_size,
 659                                         cpp, latency->cursor_sr);
 660                 reg = I915_READ(DSPFW3);
 661                 reg &= ~DSPFW_CURSOR_SR_MASK;
 662                 reg |= FW_WM(wm, CURSOR_SR);
 663                 I915_WRITE(DSPFW3, reg);
 664
 665                 /* Display HPLL off SR */
 666                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
 667                                         pineview_display_hplloff_wm.fifo_size,
 668                                         cpp, latency->display_hpll_disable);
 669                 reg = I915_READ(DSPFW3);
 670                 reg &= ~DSPFW_HPLL_SR_MASK;
 671                 reg |= FW_WM(wm, HPLL_SR);
 672                 I915_WRITE(DSPFW3, reg);
 673
 674                 /* cursor HPLL off SR */
 675                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
 676                                         pineview_display_hplloff_wm.fifo_size,
 677                                         cpp, latency->cursor_hpll_disable);
 678                 reg = I915_READ(DSPFW3);
 679                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
 680                 reg |= FW_WM(wm, HPLL_CURSOR);
 681                 I915_WRITE(DSPFW3, reg);
 682                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
 683
 684                 intel_set_memory_cxsr(dev_priv, true);
 685         } else {
 686                 intel_set_memory_cxsr(dev_priv, false);
 687         }
 688 }
 689
 690 static bool g4x_compute_wm0(struct drm_device *dev,
 691                             int plane,
 692                             const struct intel_watermark_params *display,
 693                             int display_latency_ns,
 694                             const struct intel_watermark_params *cursor,
 695                             int cursor_latency_ns,
 696                             int *plane_wm,
 697                             int *cursor_wm)
 698 {
 699         struct drm_crtc *crtc;
 700         const struct drm_display_mode *adjusted_mode;
 701         int htotal, hdisplay, clock, cpp;
 702         int line_time_us, line_count;
 703         int entries, tlb_miss;
 704
 705         crtc = intel_get_crtc_for_plane(dev, plane);
 706         if (!intel_crtc_active(crtc)) {
 707                 *cursor_wm = cursor->guard_size;
 708                 *plane_wm = display->guard_size;
 709                 return false;
 710         }
 711
 712         adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
 713         clock = adjusted_mode->crtc_clock;
 714         htotal = adjusted_mode->crtc_htotal;
 715         hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
 716         cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
 717
 718         /* Use the small buffer method to calculate plane watermark */
 719         entries = ((clock * cpp / 1000) * display_latency_ns) / 1000;
 720         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
 721         if (tlb_miss > 0)
 722                 entries += tlb_miss;
 723         entries = DIV_ROUND_UP(entries, display->cacheline_size);
 724         *plane_wm = entries + display->guard_size;
 725         if (*plane_wm > (int)display->max_wm)
 726                 *plane_wm = display->max_wm;
 727
 728         /* Use the large buffer method to calculate cursor watermark */
 729         line_time_us = max(htotal * 1000 / clock, 1);
 730         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
 731         entries = line_count * crtc->cursor->state->crtc_w * cpp;
 732         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
 733         if (tlb_miss > 0)
 734                 entries += tlb_miss;
 735         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
 736         *cursor_wm = entries + cursor->guard_size;
 737         if (*cursor_wm > (int)cursor->max_wm)
 738                 *cursor_wm = (int)cursor->max_wm;
 739
 740         return true;
 741 }
 742
 743 /*
 744  * Check the wm result.
 745  *
 746  * If any calculated watermark values is larger than the maximum value that
 747  * can be programmed into the associated watermark register, that watermark
 748  * must be disabled.
 749  */
 750 static bool g4x_check_srwm(struct drm_device *dev,
 751                            int display_wm, int cursor_wm,
 752                            const struct intel_watermark_params *display,
 753                            const struct intel_watermark_params *cursor)
 754 {
 755         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
 756                       display_wm, cursor_wm);
 757
 758         if (display_wm > display->max_wm) {
 759                 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
 760                               display_wm, display->max_wm);
 761                 return false;
 762         }
 763
 764         if (cursor_wm > cursor->max_wm) {
 765                 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
 766                               cursor_wm, cursor->max_wm);
 767                 return false;
 768         }
 769
 770         if (!(display_wm || cursor_wm)) {
 771                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
 772                 return false;
 773         }
 774
 775         return true;
 776 }
 777
 778 static bool g4x_compute_srwm(struct drm_device *dev,
 779                              int plane,
 780                              int latency_ns,
 781                              const struct intel_watermark_params *display,
 782                              const struct intel_watermark_params *cursor,
 783                              int *display_wm, int *cursor_wm)
 784 {
 785         struct drm_crtc *crtc;
 786         const struct drm_display_mode *adjusted_mode;
 787         int hdisplay, htotal, cpp, clock;
 788         unsigned long line_time_us;
 789         int line_count, line_size;
 790         int small, large;
 791         int entries;
 792
 793         if (!latency_ns) {
 794                 *display_wm = *cursor_wm = 0;
 795                 return false;
 796         }
 797
 798         crtc = intel_get_crtc_for_plane(dev, plane);
 799         adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
 800         clock = adjusted_mode->crtc_clock;
 801         htotal = adjusted_mode->crtc_htotal;
 802         hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
 803         cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
 804
 805         line_time_us = max(htotal * 1000 / clock, 1);
 806         line_count = (latency_ns / line_time_us + 1000) / 1000;
 807         line_size = hdisplay * cpp;
 808
 809         /* Use the minimum of the small and large buffer method for primary */
 810         small = ((clock * cpp / 1000) * latency_ns) / 1000;
 811         large = line_count * line_size;
 812
 813         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
 814         *display_wm = entries + display->guard_size;
 815
 816         /* calculate the self-refresh watermark for display cursor */
 817         entries = line_count * cpp * crtc->cursor->state->crtc_w;
 818         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
 819         *cursor_wm = entries + cursor->guard_size;
 820
 821         return g4x_check_srwm(dev,
 822                               *display_wm, *cursor_wm,
 823                               display, cursor);
 824 }
 825
 826 #define FW_WM_VLV(value, plane) \
 827         (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
 828
 829 static void vlv_write_wm_values(struct intel_crtc *crtc,
 830                                 const struct vlv_wm_values *wm)
 831 {
 832         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 833         enum pipe pipe = crtc->pipe;
 834
 835         I915_WRITE(VLV_DDL(pipe),
 836                    (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
 837                    (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
 838                    (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
 839                    (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
 840
 841         I915_WRITE(DSPFW1,
 842                    FW_WM(wm->sr.plane, SR) |
 843                    FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
 844                    FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
 845                    FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
 846         I915_WRITE(DSPFW2,
 847                    FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
 848                    FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
 849                    FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
 850         I915_WRITE(DSPFW3,
 851                    FW_WM(wm->sr.cursor, CURSOR_SR));
 852
 853         if (IS_CHERRYVIEW(dev_priv)) {
 854                 I915_WRITE(DSPFW7_CHV,
 855                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
 856                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
 857                 I915_WRITE(DSPFW8_CHV,
 858                            FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
 859                            FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
 860                 I915_WRITE(DSPFW9_CHV,
 861                            FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
 862                            FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
 863                 I915_WRITE(DSPHOWM,
 864                            FW_WM(wm->sr.plane >> 9, SR_HI) |
 865                            FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
 866                            FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
 867                            FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
 868                            FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
 869                            FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
 870                            FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
 871                            FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
 872                            FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
 873                            FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
 874         } else {
 875                 I915_WRITE(DSPFW7,
 876                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
 877                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
 878                 I915_WRITE(DSPHOWM,
 879                            FW_WM(wm->sr.plane >> 9, SR_HI) |
 880                            FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
 881                            FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
 882                            FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
 883                            FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
 884                            FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
 885                            FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
 886         }
 887
 888         /* zero (unused) WM1 watermarks */
 889         I915_WRITE(DSPFW4, 0);
 890         I915_WRITE(DSPFW5, 0);
 891         I915_WRITE(DSPFW6, 0);
 892         I915_WRITE(DSPHOWM1, 0);
 893
 894         POSTING_READ(DSPFW1);
 895 }
 896
 897 #undef FW_WM_VLV
 898
 899 enum vlv_wm_level {
 900         VLV_WM_LEVEL_PM2,
 901         VLV_WM_LEVEL_PM5,
 902         VLV_WM_LEVEL_DDR_DVFS,
 903 };
 904
 905 /* latency must be in 0.1us units. */
 906 static unsigned int vlv_wm_method2(unsigned int pixel_rate,
 907                                    unsigned int pipe_htotal,
 908                                    unsigned int horiz_pixels,
 909                                    unsigned int cpp,
 910                                    unsigned int latency)
 911 {
 912         unsigned int ret;
 913
 914         ret = (latency * pixel_rate) / (pipe_htotal * 10000);
 915         ret = (ret + 1) * horiz_pixels * cpp;
 916         ret = DIV_ROUND_UP(ret, 64);
 917
 918         return ret;
 919 }
 920
 921 static void vlv_setup_wm_latency(struct drm_device *dev)
 922 {
 923         struct drm_i915_private *dev_priv = dev->dev_private;
 924
 925         /* all latencies in usec */
 926         dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
 927
 928         dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
 929
 930         if (IS_CHERRYVIEW(dev_priv)) {
 931                 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
 932                 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
 933
 934                 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
 935         }
 936 }
 937
 938 static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
 939                                      struct intel_crtc *crtc,
 940                                      const struct intel_plane_state *state,
 941                                      int level)
 942 {
 943         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 944         int clock, htotal, cpp, width, wm;
 945
 946         if (dev_priv->wm.pri_latency[level] == 0)
 947                 return USHRT_MAX;
 948
 949         if (!state->visible)
 950                 return 0;
 951
 952         cpp = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
 953         clock = crtc->config->base.adjusted_mode.crtc_clock;
 954         htotal = crtc->config->base.adjusted_mode.crtc_htotal;
 955         width = crtc->config->pipe_src_w;
 956         if (WARN_ON(htotal == 0))
 957                 htotal = 1;
 958
 959         if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
 960                 /*
 961                  * FIXME the formula gives values that are
 962                  * too big for the cursor FIFO, and hence we
 963                  * would never be able to use cursors. For
 964                  * now just hardcode the watermark.
 965                  */
 966                 wm = 63;
 967         } else {
 968                 wm = vlv_wm_method2(clock, htotal, width, cpp,
 969                                     dev_priv->wm.pri_latency[level] * 10);
 970         }
 971
 972         return min_t(int, wm, USHRT_MAX);
 973 }
 974
 975 static void vlv_compute_fifo(struct intel_crtc *crtc)
 976 {
 977         struct drm_device *dev = crtc->base.dev;
 978         struct vlv_wm_state *wm_state = &crtc->wm_state;
 979         struct intel_plane *plane;
 980         unsigned int total_rate = 0;
 981         const int fifo_size = 512 - 1;
 982         int fifo_extra, fifo_left = fifo_size;
 983
 984         for_each_intel_plane_on_crtc(dev, crtc, plane) {
 985                 struct intel_plane_state *state =
 986                         to_intel_plane_state(plane->base.state);
 987
 988                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
 989                         continue;
 990
 991                 if (state->visible) {
 992                         wm_state->num_active_planes++;
 993                         total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0);
 994                 }
 995         }
 996
 997         for_each_intel_plane_on_crtc(dev, crtc, plane) {
 998                 struct intel_plane_state *state =
 999                         to_intel_plane_state(plane->base.state);
1000                 unsigned int rate;
1001
1002                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1003                         plane->wm.fifo_size = 63;
1004                         continue;
1005                 }
1006
1007                 if (!state->visible) {
1008                         plane->wm.fifo_size = 0;
1009                         continue;
1010                 }
1011
1012                 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1013                 plane->wm.fifo_size = fifo_size * rate / total_rate;
1014                 fifo_left -= plane->wm.fifo_size;
1015         }
1016
1017         fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1018
1019         /* spread the remainder evenly */
1020         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1021                 int plane_extra;
1022
1023                 if (fifo_left == 0)
1024                         break;
1025
1026                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1027                         continue;
1028
1029                 /* give it all to the first plane if none are active */
1030                 if (plane->wm.fifo_size == 0 &&
1031                     wm_state->num_active_planes)
1032                         continue;
1033
1034                 plane_extra = min(fifo_extra, fifo_left);
1035                 plane->wm.fifo_size += plane_extra;
1036                 fifo_left -= plane_extra;
1037         }
1038
1039         WARN_ON(fifo_left != 0);
1040 }
1041
1042 static void vlv_invert_wms(struct intel_crtc *crtc)
1043 {
1044         struct vlv_wm_state *wm_state = &crtc->wm_state;
1045         int level;
1046
1047         for (level = 0; level < wm_state->num_levels; level++) {
1048                 struct drm_device *dev = crtc->base.dev;
1049                 const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1050                 struct intel_plane *plane;
1051
1052                 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
1053                 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor;
1054
1055                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1056                         switch (plane->base.type) {
1057                                 int sprite;
1058                         case DRM_PLANE_TYPE_CURSOR:
1059                                 wm_state->wm[level].cursor = plane->wm.fifo_size -
1060                                         wm_state->wm[level].cursor;
1061                                 break;
1062                         case DRM_PLANE_TYPE_PRIMARY:
1063                                 wm_state->wm[level].primary = plane->wm.fifo_size -
1064                                         wm_state->wm[level].primary;
1065                                 break;
1066                         case DRM_PLANE_TYPE_OVERLAY:
1067                                 sprite = plane->plane;
1068                                 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size -
1069                                         wm_state->wm[level].sprite[sprite];
1070                                 break;
1071                         }
1072                 }
1073         }
1074 }
1075
1076 static void vlv_compute_wm(struct intel_crtc *crtc)
1077 {
1078         struct drm_device *dev = crtc->base.dev;
1079         struct vlv_wm_state *wm_state = &crtc->wm_state;
1080         struct intel_plane *plane;
1081         int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1082         int level;
1083
1084         memset(wm_state, 0, sizeof(*wm_state));
1085
1086         wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
1087         wm_state->num_levels = to_i915(dev)->wm.max_level + 1;
1088
1089         wm_state->num_active_planes = 0;
1090
1091         vlv_compute_fifo(crtc);
1092
1093         if (wm_state->num_active_planes != 1)
1094                 wm_state->cxsr = false;
1095
1096         if (wm_state->cxsr) {
1097                 for (level = 0; level < wm_state->num_levels; level++) {
1098                         wm_state->sr[level].plane = sr_fifo_size;
1099                         wm_state->sr[level].cursor = 63;
1100                 }
1101         }
1102
1103         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1104                 struct intel_plane_state *state =
1105                         to_intel_plane_state(plane->base.state);
1106
1107                 if (!state->visible)
1108                         continue;
1109
1110                 /* normal watermarks */
1111                 for (level = 0; level < wm_state->num_levels; level++) {
1112                         int wm = vlv_compute_wm_level(plane, crtc, state, level);
1113                         int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511;
1114
1115                         /* hack */
1116                         if (WARN_ON(level == 0 && wm > max_wm))
1117                                 wm = max_wm;
1118
1119                         if (wm > plane->wm.fifo_size)
1120                                 break;
1121
1122                         switch (plane->base.type) {
1123                                 int sprite;
1124                         case DRM_PLANE_TYPE_CURSOR:
1125                                 wm_state->wm[level].cursor = wm;
1126                                 break;
1127                         case DRM_PLANE_TYPE_PRIMARY:
1128                                 wm_state->wm[level].primary = wm;
1129                                 break;
1130                         case DRM_PLANE_TYPE_OVERLAY:
1131                                 sprite = plane->plane;
1132                                 wm_state->wm[level].sprite[sprite] = wm;
1133                                 break;
1134                         }
1135                 }
1136
1137                 wm_state->num_levels = level;
1138
1139                 if (!wm_state->cxsr)
1140                         continue;
1141
1142                 /* maxfifo watermarks */
1143                 switch (plane->base.type) {
1144                         int sprite, level;
1145                 case DRM_PLANE_TYPE_CURSOR:
1146                         for (level = 0; level < wm_state->num_levels; level++)
1147                                 wm_state->sr[level].cursor =
1148                                         wm_state->wm[level].cursor;
1149                         break;
1150                 case DRM_PLANE_TYPE_PRIMARY:
1151                         for (level = 0; level < wm_state->num_levels; level++)
1152                                 wm_state->sr[level].plane =
1153                                         min(wm_state->sr[level].plane,
1154                                             wm_state->wm[level].primary);
1155                         break;
1156                 case DRM_PLANE_TYPE_OVERLAY:
1157                         sprite = plane->plane;
1158                         for (level = 0; level < wm_state->num_levels; level++)
1159                                 wm_state->sr[level].plane =
1160                                         min(wm_state->sr[level].plane,
1161                                             wm_state->wm[level].sprite[sprite]);
1162                         break;
1163                 }
1164         }
1165
1166         /* clear any (partially) filled invalid levels */
1167         for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) {
1168                 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1169                 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1170         }
1171
1172         vlv_invert_wms(crtc);
1173 }
1174
1175 #define VLV_FIFO(plane, value) \
1176         (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1177
1178 static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1179 {
1180         struct drm_device *dev = crtc->base.dev;
1181         struct drm_i915_private *dev_priv = to_i915(dev);
1182         struct intel_plane *plane;
1183         int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1184
1185         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1186                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1187                         WARN_ON(plane->wm.fifo_size != 63);
1188                         continue;
1189                 }
1190
1191                 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
1192                         sprite0_start = plane->wm.fifo_size;
1193                 else if (plane->plane == 0)
1194                         sprite1_start = sprite0_start + plane->wm.fifo_size;
1195                 else
1196                         fifo_size = sprite1_start + plane->wm.fifo_size;
1197         }
1198
1199         WARN_ON(fifo_size != 512 - 1);
1200
1201         DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1202                       pipe_name(crtc->pipe), sprite0_start,
1203                       sprite1_start, fifo_size);
1204
1205         switch (crtc->pipe) {
1206                 uint32_t dsparb, dsparb2, dsparb3;
1207         case PIPE_A:
1208                 dsparb = I915_READ(DSPARB);
1209                 dsparb2 = I915_READ(DSPARB2);
1210
1211                 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1212                             VLV_FIFO(SPRITEB, 0xff));
1213                 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1214                            VLV_FIFO(SPRITEB, sprite1_start));
1215
1216                 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1217                              VLV_FIFO(SPRITEB_HI, 0x1));
1218                 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1219                            VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1220
1221                 I915_WRITE(DSPARB, dsparb);
1222                 I915_WRITE(DSPARB2, dsparb2);
1223                 break;
1224         case PIPE_B:
1225                 dsparb = I915_READ(DSPARB);
1226                 dsparb2 = I915_READ(DSPARB2);
1227
1228                 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1229                             VLV_FIFO(SPRITED, 0xff));
1230                 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1231                            VLV_FIFO(SPRITED, sprite1_start));
1232
1233                 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1234                              VLV_FIFO(SPRITED_HI, 0xff));
1235                 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1236                            VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1237
1238                 I915_WRITE(DSPARB, dsparb);
1239                 I915_WRITE(DSPARB2, dsparb2);
1240                 break;
1241         case PIPE_C:
1242                 dsparb3 = I915_READ(DSPARB3);
1243                 dsparb2 = I915_READ(DSPARB2);
1244
1245                 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1246                              VLV_FIFO(SPRITEF, 0xff));
1247                 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1248                             VLV_FIFO(SPRITEF, sprite1_start));
1249
1250                 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1251                              VLV_FIFO(SPRITEF_HI, 0xff));
1252                 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1253                            VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1254
1255                 I915_WRITE(DSPARB3, dsparb3);
1256                 I915_WRITE(DSPARB2, dsparb2);
1257                 break;
1258         default:
1259                 break;
1260         }
1261 }
1262
1263 #undef VLV_FIFO
1264
1265 static void vlv_merge_wm(struct drm_device *dev,
1266                          struct vlv_wm_values *wm)
1267 {
1268         struct intel_crtc *crtc;
1269         int num_active_crtcs = 0;
1270
1271         wm->level = to_i915(dev)->wm.max_level;
1272         wm->cxsr = true;
1273
1274         for_each_intel_crtc(dev, crtc) {
1275                 const struct vlv_wm_state *wm_state = &crtc->wm_state;
1276
1277                 if (!crtc->active)
1278                         continue;
1279
1280                 if (!wm_state->cxsr)
1281                         wm->cxsr = false;
1282
1283                 num_active_crtcs++;
1284                 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1285         }
1286
1287         if (num_active_crtcs != 1)
1288                 wm->cxsr = false;
1289
1290         if (num_active_crtcs > 1)
1291                 wm->level = VLV_WM_LEVEL_PM2;
1292
1293         for_each_intel_crtc(dev, crtc) {
1294                 struct vlv_wm_state *wm_state = &crtc->wm_state;
1295                 enum pipe pipe = crtc->pipe;
1296
1297                 if (!crtc->active)
1298                         continue;
1299
1300                 wm->pipe[pipe] = wm_state->wm[wm->level];
1301                 if (wm->cxsr)
1302                         wm->sr = wm_state->sr[wm->level];
1303
1304                 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2;
1305                 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2;
1306                 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2;
1307                 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2;
1308         }
1309 }
1310
1311 static void vlv_update_wm(struct drm_crtc *crtc)
1312 {
1313         struct drm_device *dev = crtc->dev;
1314         struct drm_i915_private *dev_priv = dev->dev_private;
1315         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1316         enum pipe pipe = intel_crtc->pipe;
1317         struct vlv_wm_values wm = {};
1318
1319         vlv_compute_wm(intel_crtc);
1320         vlv_merge_wm(dev, &wm);
1321
1322         if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
1323                 /* FIXME should be part of crtc atomic commit */
1324                 vlv_pipe_set_fifo_size(intel_crtc);
1325                 return;
1326         }
1327
1328         if (wm.level < VLV_WM_LEVEL_DDR_DVFS &&
1329             dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS)
1330                 chv_set_memory_dvfs(dev_priv, false);
1331
1332         if (wm.level < VLV_WM_LEVEL_PM5 &&
1333             dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5)
1334                 chv_set_memory_pm5(dev_priv, false);
1335
1336         if (!wm.cxsr && dev_priv->wm.vlv.cxsr)
1337                 intel_set_memory_cxsr(dev_priv, false);
1338
1339         /* FIXME should be part of crtc atomic commit */
1340         vlv_pipe_set_fifo_size(intel_crtc);
1341
1342         vlv_write_wm_values(intel_crtc, &wm);
1343
1344         DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1345                       "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1346                       pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1347                       wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1],
1348                       wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr);
1349
1350         if (wm.cxsr && !dev_priv->wm.vlv.cxsr)
1351                 intel_set_memory_cxsr(dev_priv, true);
1352
1353         if (wm.level >= VLV_WM_LEVEL_PM5 &&
1354             dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5)
1355                 chv_set_memory_pm5(dev_priv, true);
1356
1357         if (wm.level >= VLV_WM_LEVEL_DDR_DVFS &&
1358             dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS)
1359                 chv_set_memory_dvfs(dev_priv, true);
1360
1361         dev_priv->wm.vlv = wm;
1362 }
1363
1364 #define single_plane_enabled(mask) is_power_of_2(mask)
1365
1366 static void g4x_update_wm(struct drm_crtc *crtc)
1367 {
1368         struct drm_device *dev = crtc->dev;
1369         static const int sr_latency_ns = 12000;
1370         struct drm_i915_private *dev_priv = dev->dev_private;
1371         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1372         int plane_sr, cursor_sr;
1373         unsigned int enabled = 0;
1374         bool cxsr_enabled;
1375
1376         if (g4x_compute_wm0(dev, PIPE_A,
1377                             &g4x_wm_info, pessimal_latency_ns,
1378                             &g4x_cursor_wm_info, pessimal_latency_ns,
1379                             &planea_wm, &cursora_wm))
1380                 enabled |= 1 << PIPE_A;
1381
1382         if (g4x_compute_wm0(dev, PIPE_B,
1383                             &g4x_wm_info, pessimal_latency_ns,
1384                             &g4x_cursor_wm_info, pessimal_latency_ns,
1385                             &planeb_wm, &cursorb_wm))
1386                 enabled |= 1 << PIPE_B;
1387
1388         if (single_plane_enabled(enabled) &&
1389             g4x_compute_srwm(dev, ffs(enabled) - 1,
1390                              sr_latency_ns,
1391                              &g4x_wm_info,
1392                              &g4x_cursor_wm_info,
1393                              &plane_sr, &cursor_sr)) {
1394                 cxsr_enabled = true;
1395         } else {
1396                 cxsr_enabled = false;
1397                 intel_set_memory_cxsr(dev_priv, false);
1398                 plane_sr = cursor_sr = 0;
1399         }
1400
1401         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1402                       "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1403                       planea_wm, cursora_wm,
1404                       planeb_wm, cursorb_wm,
1405                       plane_sr, cursor_sr);
1406
1407         I915_WRITE(DSPFW1,
1408                    FW_WM(plane_sr, SR) |
1409                    FW_WM(cursorb_wm, CURSORB) |
1410                    FW_WM(planeb_wm, PLANEB) |
1411                    FW_WM(planea_wm, PLANEA));
1412         I915_WRITE(DSPFW2,
1413                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1414                    FW_WM(cursora_wm, CURSORA));
1415         /* HPLL off in SR has some issues on G4x... disable it */
1416         I915_WRITE(DSPFW3,
1417                    (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1418                    FW_WM(cursor_sr, CURSOR_SR));
1419
1420         if (cxsr_enabled)
1421                 intel_set_memory_cxsr(dev_priv, true);
1422 }
1423
1424 static void i965_update_wm(struct drm_crtc *unused_crtc)
1425 {
1426         struct drm_device *dev = unused_crtc->dev;
1427         struct drm_i915_private *dev_priv = dev->dev_private;
1428         struct drm_crtc *crtc;
1429         int srwm = 1;
1430         int cursor_sr = 16;
1431         bool cxsr_enabled;
1432
1433         /* Calc sr entries for one plane configs */
1434         crtc = single_enabled_crtc(dev);
1435         if (crtc) {
1436                 /* self-refresh has much higher latency */
1437                 static const int sr_latency_ns = 12000;
1438                 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1439                 int clock = adjusted_mode->crtc_clock;
1440                 int htotal = adjusted_mode->crtc_htotal;
1441                 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
1442                 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
1443                 unsigned long line_time_us;
1444                 int entries;
1445
1446                 line_time_us = max(htotal * 1000 / clock, 1);
1447
1448                 /* Use ns/us then divide to preserve precision */
1449                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1450                         cpp * hdisplay;
1451                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1452                 srwm = I965_FIFO_SIZE - entries;
1453                 if (srwm < 0)
1454                         srwm = 1;
1455                 srwm &= 0x1ff;
1456                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1457                               entries, srwm);
1458
1459                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1460                         cpp * crtc->cursor->state->crtc_w;
1461                 entries = DIV_ROUND_UP(entries,
1462                                           i965_cursor_wm_info.cacheline_size);
1463                 cursor_sr = i965_cursor_wm_info.fifo_size -
1464                         (entries + i965_cursor_wm_info.guard_size);
1465
1466                 if (cursor_sr > i965_cursor_wm_info.max_wm)
1467                         cursor_sr = i965_cursor_wm_info.max_wm;
1468
1469                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1470                               "cursor %d\n", srwm, cursor_sr);
1471
1472                 cxsr_enabled = true;
1473         } else {
1474                 cxsr_enabled = false;
1475                 /* Turn off self refresh if both pipes are enabled */
1476                 intel_set_memory_cxsr(dev_priv, false);
1477         }
1478
1479         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1480                       srwm);
1481
1482         /* 965 has limitations... */
1483         I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1484                    FW_WM(8, CURSORB) |
1485                    FW_WM(8, PLANEB) |
1486                    FW_WM(8, PLANEA));
1487         I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1488                    FW_WM(8, PLANEC_OLD));
1489         /* update cursor SR watermark */
1490         I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
1491
1492         if (cxsr_enabled)
1493                 intel_set_memory_cxsr(dev_priv, true);
1494 }
1495
1496 #undef FW_WM
1497
1498 static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1499 {
1500         struct drm_device *dev = unused_crtc->dev;
1501         struct drm_i915_private *dev_priv = dev->dev_private;
1502         const struct intel_watermark_params *wm_info;
1503         uint32_t fwater_lo;
1504         uint32_t fwater_hi;
1505         int cwm, srwm = 1;
1506         int fifo_size;
1507         int planea_wm, planeb_wm;
1508         struct drm_crtc *crtc, *enabled = NULL;
1509
1510         if (IS_I945GM(dev))
1511                 wm_info = &i945_wm_info;
1512         else if (!IS_GEN2(dev))
1513                 wm_info = &i915_wm_info;
1514         else
1515                 wm_info = &i830_a_wm_info;
1516
1517         fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1518         crtc = intel_get_crtc_for_plane(dev, 0);
1519         if (intel_crtc_active(crtc)) {
1520                 const struct drm_display_mode *adjusted_mode;
1521                 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
1522                 if (IS_GEN2(dev))
1523                         cpp = 4;
1524
1525                 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1526                 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1527                                                wm_info, fifo_size, cpp,
1528                                                pessimal_latency_ns);
1529                 enabled = crtc;
1530         } else {
1531                 planea_wm = fifo_size - wm_info->guard_size;
1532                 if (planea_wm > (long)wm_info->max_wm)
1533                         planea_wm = wm_info->max_wm;
1534         }
1535
1536         if (IS_GEN2(dev))
1537                 wm_info = &i830_bc_wm_info;
1538
1539         fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1540         crtc = intel_get_crtc_for_plane(dev, 1);
1541         if (intel_crtc_active(crtc)) {
1542                 const struct drm_display_mode *adjusted_mode;
1543                 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
1544                 if (IS_GEN2(dev))
1545                         cpp = 4;
1546
1547                 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1548                 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1549                                                wm_info, fifo_size, cpp,
1550                                                pessimal_latency_ns);
1551                 if (enabled == NULL)
1552                         enabled = crtc;
1553                 else
1554                         enabled = NULL;
1555         } else {
1556                 planeb_wm = fifo_size - wm_info->guard_size;
1557                 if (planeb_wm > (long)wm_info->max_wm)
1558                         planeb_wm = wm_info->max_wm;
1559         }
1560
1561         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1562
1563         if (IS_I915GM(dev) && enabled) {
1564                 struct drm_i915_gem_object *obj;
1565
1566                 obj = intel_fb_obj(enabled->primary->state->fb);
1567
1568                 /* self-refresh seems busted with untiled */
1569                 if (obj->tiling_mode == I915_TILING_NONE)
1570                         enabled = NULL;
1571         }
1572
1573         /*
1574          * Overlay gets an aggressive default since video jitter is bad.
1575          */
1576         cwm = 2;
1577
1578         /* Play safe and disable self-refresh before adjusting watermarks. */
1579         intel_set_memory_cxsr(dev_priv, false);
1580
1581         /* Calc sr entries for one plane configs */
1582         if (HAS_FW_BLC(dev) && enabled) {
1583                 /* self-refresh has much higher latency */
1584                 static const int sr_latency_ns = 6000;
1585                 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(enabled)->config->base.adjusted_mode;
1586                 int clock = adjusted_mode->crtc_clock;
1587                 int htotal = adjusted_mode->crtc_htotal;
1588                 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
1589                 int cpp = drm_format_plane_cpp(enabled->primary->state->fb->pixel_format, 0);
1590                 unsigned long line_time_us;
1591                 int entries;
1592
1593                 line_time_us = max(htotal * 1000 / clock, 1);
1594
1595                 /* Use ns/us then divide to preserve precision */
1596                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1597                         cpp * hdisplay;
1598                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1599                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1600                 srwm = wm_info->fifo_size - entries;
1601                 if (srwm < 0)
1602                         srwm = 1;
1603
1604                 if (IS_I945G(dev) || IS_I945GM(dev))
1605                         I915_WRITE(FW_BLC_SELF,
1606                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1607                 else if (IS_I915GM(dev))
1608                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1609         }
1610
1611         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1612                       planea_wm, planeb_wm, cwm, srwm);
1613
1614         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1615         fwater_hi = (cwm & 0x1f);
1616
1617         /* Set request length to 8 cachelines per fetch */
1618         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1619         fwater_hi = fwater_hi | (1 << 8);
1620
1621         I915_WRITE(FW_BLC, fwater_lo);
1622         I915_WRITE(FW_BLC2, fwater_hi);
1623
1624         if (enabled)
1625                 intel_set_memory_cxsr(dev_priv, true);
1626 }
1627
1628 static void i845_update_wm(struct drm_crtc *unused_crtc)
1629 {
1630         struct drm_device *dev = unused_crtc->dev;
1631         struct drm_i915_private *dev_priv = dev->dev_private;
1632         struct drm_crtc *crtc;
1633         const struct drm_display_mode *adjusted_mode;
1634         uint32_t fwater_lo;
1635         int planea_wm;
1636
1637         crtc = single_enabled_crtc(dev);
1638         if (crtc == NULL)
1639                 return;
1640
1641         adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1642         planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1643                                        &i845_wm_info,
1644                                        dev_priv->display.get_fifo_size(dev, 0),
1645                                        4, pessimal_latency_ns);
1646         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1647         fwater_lo |= (3<<8) | planea_wm;
1648
1649         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1650
1651         I915_WRITE(FW_BLC, fwater_lo);
1652 }
1653
1654 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
1655 {
1656         uint32_t pixel_rate;
1657
1658         pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
1659
1660         /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1661          * adjust the pixel_rate here. */
1662
1663         if (pipe_config->pch_pfit.enabled) {
1664                 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
1665                 uint32_t pfit_size = pipe_config->pch_pfit.size;
1666
1667                 pipe_w = pipe_config->pipe_src_w;
1668                 pipe_h = pipe_config->pipe_src_h;
1669
1670                 pfit_w = (pfit_size >> 16) & 0xFFFF;
1671                 pfit_h = pfit_size & 0xFFFF;
1672                 if (pipe_w < pfit_w)
1673                         pipe_w = pfit_w;
1674                 if (pipe_h < pfit_h)
1675                         pipe_h = pfit_h;
1676
1677                 if (WARN_ON(!pfit_w || !pfit_h))
1678                         return pixel_rate;
1679
1680                 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1681                                      pfit_w * pfit_h);
1682         }
1683
1684         return pixel_rate;
1685 }
1686
1687 /* latency must be in 0.1us units. */
1688 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
1689 {
1690         uint64_t ret;
1691
1692         if (WARN(latency == 0, "Latency value missing\n"))
1693                 return UINT_MAX;
1694
1695         ret = (uint64_t) pixel_rate * cpp * latency;
1696         ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1697
1698         return ret;
1699 }
1700
1701 /* latency must be in 0.1us units. */
1702 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
1703                                uint32_t horiz_pixels, uint8_t cpp,
1704                                uint32_t latency)
1705 {
1706         uint32_t ret;
1707
1708         if (WARN(latency == 0, "Latency value missing\n"))
1709                 return UINT_MAX;
1710         if (WARN_ON(!pipe_htotal))
1711                 return UINT_MAX;
1712
1713         ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1714         ret = (ret + 1) * horiz_pixels * cpp;
1715         ret = DIV_ROUND_UP(ret, 64) + 2;
1716         return ret;
1717 }
1718
1719 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
1720                            uint8_t cpp)
1721 {
1722         /*
1723          * Neither of these should be possible since this function shouldn't be
1724          * called if the CRTC is off or the plane is invisible.  But let's be
1725          * extra paranoid to avoid a potential divide-by-zero if we screw up
1726          * elsewhere in the driver.
1727          */
1728         if (WARN_ON(!cpp))
1729                 return 0;
1730         if (WARN_ON(!horiz_pixels))
1731                 return 0;
1732
1733         return DIV_ROUND_UP(pri_val * 64, horiz_pixels * cpp) + 2;
1734 }
1735
1736 struct ilk_wm_maximums {
1737         uint16_t pri;
1738         uint16_t spr;
1739         uint16_t cur;
1740         uint16_t fbc;
1741 };
1742
1743 /*
1744  * For both WM_PIPE and WM_LP.
1745  * mem_value must be in 0.1us units.
1746  */
1747 static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
1748                                    const struct intel_plane_state *pstate,
1749                                    uint32_t mem_value,
1750                                    bool is_lp)
1751 {
1752         int cpp = pstate->base.fb ?
1753                 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
1754         uint32_t method1, method2;
1755
1756         if (!cstate->base.active || !pstate->visible)
1757                 return 0;
1758
1759         method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
1760
1761         if (!is_lp)
1762                 return method1;
1763
1764         method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1765                                  cstate->base.adjusted_mode.crtc_htotal,
1766                                  drm_rect_width(&pstate->dst),
1767                                  cpp, mem_value);
1768
1769         return min(method1, method2);
1770 }
1771
1772 /*
1773  * For both WM_PIPE and WM_LP.
1774  * mem_value must be in 0.1us units.
1775  */
1776 static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
1777                                    const struct intel_plane_state *pstate,
1778                                    uint32_t mem_value)
1779 {
1780         int cpp = pstate->base.fb ?
1781                 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
1782         uint32_t method1, method2;
1783
1784         if (!cstate->base.active || !pstate->visible)
1785                 return 0;
1786
1787         method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
1788         method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1789                                  cstate->base.adjusted_mode.crtc_htotal,
1790                                  drm_rect_width(&pstate->dst),
1791                                  cpp, mem_value);
1792         return min(method1, method2);
1793 }
1794
1795 /*
1796  * For both WM_PIPE and WM_LP.
1797  * mem_value must be in 0.1us units.
1798  */
1799 static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
1800                                    const struct intel_plane_state *pstate,
1801                                    uint32_t mem_value)
1802 {
1803         /*
1804          * We treat the cursor plane as always-on for the purposes of watermark
1805          * calculation.  Until we have two-stage watermark programming merged,
1806          * this is necessary to avoid flickering.
1807          */
1808         int cpp = 4;
1809         int width = pstate->visible ? pstate->base.crtc_w : 64;
1810
1811         if (!cstate->base.active)
1812                 return 0;
1813
1814         return ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1815                               cstate->base.adjusted_mode.crtc_htotal,
1816                               width, cpp, mem_value);
1817 }
1818
1819 /* Only for WM_LP. */
1820 static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
1821                                    const struct intel_plane_state *pstate,
1822                                    uint32_t pri_val)
1823 {
1824         int cpp = pstate->base.fb ?
1825                 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
1826
1827         if (!cstate->base.active || !pstate->visible)
1828                 return 0;
1829
1830         return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->dst), cpp);
1831 }
1832
1833 static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1834 {
1835         if (INTEL_INFO(dev)->gen >= 8)
1836                 return 3072;
1837         else if (INTEL_INFO(dev)->gen >= 7)
1838                 return 768;
1839         else
1840                 return 512;
1841 }
1842
1843 static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1844                                          int level, bool is_sprite)
1845 {
1846         if (INTEL_INFO(dev)->gen >= 8)
1847                 /* BDW primary/sprite plane watermarks */
1848                 return level == 0 ? 255 : 2047;
1849         else if (INTEL_INFO(dev)->gen >= 7)
1850                 /* IVB/HSW primary/sprite plane watermarks */
1851                 return level == 0 ? 127 : 1023;
1852         else if (!is_sprite)
1853                 /* ILK/SNB primary plane watermarks */
1854                 return level == 0 ? 127 : 511;
1855         else
1856                 /* ILK/SNB sprite plane watermarks */
1857                 return level == 0 ? 63 : 255;
1858 }
1859
1860 static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1861                                           int level)
1862 {
1863         if (INTEL_INFO(dev)->gen >= 7)
1864                 return level == 0 ? 63 : 255;
1865         else
1866                 return level == 0 ? 31 : 63;
1867 }
1868
1869 static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1870 {
1871         if (INTEL_INFO(dev)->gen >= 8)
1872                 return 31;
1873         else
1874                 return 15;
1875 }
1876
1877 /* Calculate the maximum primary/sprite plane watermark */
1878 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1879                                      int level,
1880                                      const struct intel_wm_config *config,
1881                                      enum intel_ddb_partitioning ddb_partitioning,
1882                                      bool is_sprite)
1883 {
1884         unsigned int fifo_size = ilk_display_fifo_size(dev);
1885
1886         /* if sprites aren't enabled, sprites get nothing */
1887         if (is_sprite && !config->sprites_enabled)
1888                 return 0;
1889
1890         /* HSW allows LP1+ watermarks even with multiple pipes */
1891         if (level == 0 || config->num_pipes_active > 1) {
1892                 fifo_size /= INTEL_INFO(dev)->num_pipes;
1893
1894                 /*
1895                  * For some reason the non self refresh
1896                  * FIFO size is only half of the self
1897                  * refresh FIFO size on ILK/SNB.
1898                  */
1899                 if (INTEL_INFO(dev)->gen <= 6)
1900                         fifo_size /= 2;
1901         }
1902
1903         if (config->sprites_enabled) {
1904                 /* level 0 is always calculated with 1:1 split */
1905                 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1906                         if (is_sprite)
1907                                 fifo_size *= 5;
1908                         fifo_size /= 6;
1909                 } else {
1910                         fifo_size /= 2;
1911                 }
1912         }
1913
1914         /* clamp to max that the registers can hold */
1915         return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
1916 }
1917
1918 /* Calculate the maximum cursor plane watermark */
1919 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
1920                                       int level,
1921                                       const struct intel_wm_config *config)
1922 {
1923         /* HSW LP1+ watermarks w/ multiple pipes */
1924         if (level > 0 && config->num_pipes_active > 1)
1925                 return 64;
1926
1927         /* otherwise just report max that registers can hold */
1928         return ilk_cursor_wm_reg_max(dev, level);
1929 }
1930
1931 static void ilk_compute_wm_maximums(const struct drm_device *dev,
1932                                     int level,
1933                                     const struct intel_wm_config *config,
1934                                     enum intel_ddb_partitioning ddb_partitioning,
1935                                     struct ilk_wm_maximums *max)
1936 {
1937         max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1938         max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1939         max->cur = ilk_cursor_wm_max(dev, level, config);
1940         max->fbc = ilk_fbc_wm_reg_max(dev);
1941 }
1942
1943 static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1944                                         int level,
1945                                         struct ilk_wm_maximums *max)
1946 {
1947         max->pri = ilk_plane_wm_reg_max(dev, level, false);
1948         max->spr = ilk_plane_wm_reg_max(dev, level, true);
1949         max->cur = ilk_cursor_wm_reg_max(dev, level);
1950         max->fbc = ilk_fbc_wm_reg_max(dev);
1951 }
1952
1953 static bool ilk_validate_wm_level(int level,
1954                                   const struct ilk_wm_maximums *max,
1955                                   struct intel_wm_level *result)
1956 {
1957         bool ret;
1958
1959         /* already determined to be invalid? */
1960         if (!result->enable)
1961                 return false;
1962
1963         result->enable = result->pri_val <= max->pri &&
1964                          result->spr_val <= max->spr &&
1965                          result->cur_val <= max->cur;
1966
1967         ret = result->enable;
1968
1969         /*
1970          * HACK until we can pre-compute everything,
1971          * and thus fail gracefully if LP0 watermarks
1972          * are exceeded...
1973          */
1974         if (level == 0 && !result->enable) {
1975                 if (result->pri_val > max->pri)
1976                         DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1977                                       level, result->pri_val, max->pri);
1978                 if (result->spr_val > max->spr)
1979                         DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
1980                                       level, result->spr_val, max->spr);
1981                 if (result->cur_val > max->cur)
1982                         DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
1983                                       level, result->cur_val, max->cur);
1984
1985                 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
1986                 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
1987                 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
1988                 result->enable = true;
1989         }
1990
1991         return ret;
1992 }
1993
1994 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
1995                                  const struct intel_crtc *intel_crtc,
1996                                  int level,
1997                                  struct intel_crtc_state *cstate,
1998                                  struct intel_plane_state *pristate,
1999                                  struct intel_plane_state *sprstate,
2000                                  struct intel_plane_state *curstate,
2001                                  struct intel_wm_level *result)
2002 {
2003         uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2004         uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2005         uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2006
2007         /* WM1+ latency values stored in 0.5us units */
2008         if (level > 0) {
2009                 pri_latency *= 5;
2010                 spr_latency *= 5;
2011                 cur_latency *= 5;
2012         }
2013
2014         if (pristate) {
2015                 result->pri_val = ilk_compute_pri_wm(cstate, pristate,
2016                                                      pri_latency, level);
2017                 result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val);
2018         }
2019
2020         if (sprstate)
2021                 result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency);
2022
2023         if (curstate)
2024                 result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency);
2025
2026         result->enable = true;
2027 }
2028
2029 static uint32_t
2030 hsw_compute_linetime_wm(const struct intel_crtc_state *cstate)
2031 {
2032         const struct intel_atomic_state *intel_state =
2033                 to_intel_atomic_state(cstate->base.state);
2034         const struct drm_display_mode *adjusted_mode =
2035                 &cstate->base.adjusted_mode;
2036         u32 linetime, ips_linetime;
2037
2038         if (!cstate->base.active)
2039                 return 0;
2040         if (WARN_ON(adjusted_mode->crtc_clock == 0))
2041                 return 0;
2042         if (WARN_ON(intel_state->cdclk == 0))
2043                 return 0;
2044
2045         /* The WM are computed with base on how long it takes to fill a single
2046          * row at the given clock rate, multiplied by 8.
2047          * */
2048         linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2049                                      adjusted_mode->crtc_clock);
2050         ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2051                                          intel_state->cdclk);
2052
2053         return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2054                PIPE_WM_LINETIME_TIME(linetime);
2055 }
2056
2057 static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
2058 {
2059         struct drm_i915_private *dev_priv = dev->dev_private;
2060
2061         if (IS_GEN9(dev)) {
2062                 uint32_t val;
2063                 int ret, i;
2064                 int level, max_level = ilk_wm_max_level(dev);
2065
2066                 /* read the first set of memory latencies[0:3] */
2067                 val = 0; /* data0 to be programmed to 0 for first set */
2068                 mutex_lock(&dev_priv->rps.hw_lock);
2069                 ret = sandybridge_pcode_read(dev_priv,
2070                                              GEN9_PCODE_READ_MEM_LATENCY,
2071                                              &val);
2072                 mutex_unlock(&dev_priv->rps.hw_lock);
2073
2074                 if (ret) {
2075                         DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2076                         return;
2077                 }
2078
2079                 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2080                 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2081                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2082                 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2083                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2084                 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2085                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2086
2087                 /* read the second set of memory latencies[4:7] */
2088                 val = 1; /* data0 to be programmed to 1 for second set */
2089                 mutex_lock(&dev_priv->rps.hw_lock);
2090                 ret = sandybridge_pcode_read(dev_priv,
2091                                              GEN9_PCODE_READ_MEM_LATENCY,
2092                                              &val);
2093                 mutex_unlock(&dev_priv->rps.hw_lock);
2094                 if (ret) {
2095                         DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2096                         return;
2097                 }
2098
2099                 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2100                 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2101                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2102                 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2103                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2104                 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2105                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2106
2107                 /*
2108                  * WaWmMemoryReadLatency:skl
2109                  *
2110                  * punit doesn't take into account the read latency so we need
2111                  * to add 2us to the various latency levels we retrieve from
2112                  * the punit.
2113                  *   - W0 is a bit special in that it's the only level that
2114                  *   can't be disabled if we want to have display working, so
2115                  *   we always add 2us there.
2116                  *   - For levels >=1, punit returns 0us latency when they are
2117                  *   disabled, so we respect that and don't add 2us then
2118                  *
2119                  * Additionally, if a level n (n > 1) has a 0us latency, all
2120                  * levels m (m >= n) need to be disabled. We make sure to
2121                  * sanitize the values out of the punit to satisfy this
2122                  * requirement.
2123                  */
2124                 wm[0] += 2;
2125                 for (level = 1; level <= max_level; level++)
2126                         if (wm[level] != 0)
2127                                 wm[level] += 2;
2128                         else {
2129                                 for (i = level + 1; i <= max_level; i++)
2130                                         wm[i] = 0;
2131
2132                                 break;
2133                         }
2134         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2135                 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2136
2137                 wm[0] = (sskpd >> 56) & 0xFF;
2138                 if (wm[0] == 0)
2139                         wm[0] = sskpd & 0xF;
2140                 wm[1] = (sskpd >> 4) & 0xFF;
2141                 wm[2] = (sskpd >> 12) & 0xFF;
2142                 wm[3] = (sskpd >> 20) & 0x1FF;
2143                 wm[4] = (sskpd >> 32) & 0x1FF;
2144         } else if (INTEL_INFO(dev)->gen >= 6) {
2145                 uint32_t sskpd = I915_READ(MCH_SSKPD);
2146
2147                 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2148                 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2149                 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2150                 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2151         } else if (INTEL_INFO(dev)->gen >= 5) {
2152                 uint32_t mltr = I915_READ(MLTR_ILK);
2153
2154                 /* ILK primary LP0 latency is 700 ns */
2155                 wm[0] = 7;
2156                 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2157                 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2158         }
2159 }
2160
2161 static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2162 {
2163         /* ILK sprite LP0 latency is 1300 ns */
2164         if (IS_GEN5(dev))
2165                 wm[0] = 13;
2166 }
2167
2168 static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2169 {
2170         /* ILK cursor LP0 latency is 1300 ns */
2171         if (IS_GEN5(dev))
2172                 wm[0] = 13;
2173
2174         /* WaDoubleCursorLP3Latency:ivb */
2175         if (IS_IVYBRIDGE(dev))
2176                 wm[3] *= 2;
2177 }
2178
2179 int ilk_wm_max_level(const struct drm_device *dev)
2180 {
2181         /* how many WM levels are we expecting */
2182         if (INTEL_INFO(dev)->gen >= 9)
2183                 return 7;
2184         else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2185                 return 4;
2186         else if (INTEL_INFO(dev)->gen >= 6)
2187                 return 3;
2188         else
2189                 return 2;
2190 }
2191
2192 static void intel_print_wm_latency(struct drm_device *dev,
2193                                    const char *name,
2194                                    const uint16_t wm[8])
2195 {
2196         int level, max_level = ilk_wm_max_level(dev);
2197
2198         for (level = 0; level <= max_level; level++) {
2199                 unsigned int latency = wm[level];
2200
2201                 if (latency == 0) {
2202                         DRM_ERROR("%s WM%d latency not provided\n",
2203                                   name, level);
2204                         continue;
2205                 }
2206
2207                 /*
2208                  * - latencies are in us on gen9.
2209                  * - before then, WM1+ latency values are in 0.5us units
2210                  */
2211                 if (IS_GEN9(dev))
2212                         latency *= 10;
2213                 else if (level > 0)
2214                         latency *= 5;
2215
2216                 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2217                               name, level, wm[level],
2218                               latency / 10, latency % 10);
2219         }
2220 }
2221
2222 static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2223                                     uint16_t wm[5], uint16_t min)
2224 {
2225         int level, max_level = ilk_wm_max_level(dev_priv->dev);
2226
2227         if (wm[0] >= min)
2228                 return false;
2229
2230         wm[0] = max(wm[0], min);
2231         for (level = 1; level <= max_level; level++)
2232                 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2233
2234         return true;
2235 }
2236
2237 static void snb_wm_latency_quirk(struct drm_device *dev)
2238 {
2239         struct drm_i915_private *dev_priv = dev->dev_private;
2240         bool changed;
2241
2242         /*
2243          * The BIOS provided WM memory latency values are often
2244          * inadequate for high resolution displays. Adjust them.
2245          */
2246         changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2247                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2248                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2249
2250         if (!changed)
2251                 return;
2252
2253         DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2254         intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2255         intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2256         intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2257 }
2258
2259 static void ilk_setup_wm_latency(struct drm_device *dev)
2260 {
2261         struct drm_i915_private *dev_priv = dev->dev_private;
2262
2263         intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2264
2265         memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2266                sizeof(dev_priv->wm.pri_latency));
2267         memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2268                sizeof(dev_priv->wm.pri_latency));
2269
2270         intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2271         intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
2272
2273         intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2274         intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2275         intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2276
2277         if (IS_GEN6(dev))
2278                 snb_wm_latency_quirk(dev);
2279 }
2280
2281 static void skl_setup_wm_latency(struct drm_device *dev)
2282 {
2283         struct drm_i915_private *dev_priv = dev->dev_private;
2284
2285         intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
2286         intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
2287 }
2288
2289 static bool ilk_validate_pipe_wm(struct drm_device *dev,
2290                                  struct intel_pipe_wm *pipe_wm)
2291 {
2292         /* LP0 watermark maximums depend on this pipe alone */
2293         const struct intel_wm_config config = {
2294                 .num_pipes_active = 1,
2295                 .sprites_enabled = pipe_wm->sprites_enabled,
2296                 .sprites_scaled = pipe_wm->sprites_scaled,
2297         };
2298         struct ilk_wm_maximums max;
2299
2300         /* LP0 watermarks always use 1/2 DDB partitioning */
2301         ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2302
2303         /* At least LP0 must be valid */
2304         if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) {
2305                 DRM_DEBUG_KMS("LP0 watermark invalid\n");
2306                 return false;
2307         }
2308
2309         return true;
2310 }
2311
2312 /* Compute new watermarks for the pipe */
2313 static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
2314 {
2315         struct drm_atomic_state *state = cstate->base.state;
2316         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
2317         struct intel_pipe_wm *pipe_wm;
2318         struct drm_device *dev = state->dev;
2319         const struct drm_i915_private *dev_priv = dev->dev_private;
2320         struct intel_plane *intel_plane;
2321         struct intel_plane_state *pristate = NULL;
2322         struct intel_plane_state *sprstate = NULL;
2323         struct intel_plane_state *curstate = NULL;
2324         int level, max_level = ilk_wm_max_level(dev), usable_level;
2325         struct ilk_wm_maximums max;
2326
2327         pipe_wm = &cstate->wm.ilk.optimal;
2328
2329         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2330                 struct intel_plane_state *ps;
2331
2332                 ps = intel_atomic_get_existing_plane_state(state,
2333                                                            intel_plane);
2334                 if (!ps)
2335                         continue;
2336
2337                 if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY)
2338                         pristate = ps;
2339                 else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY)
2340                         sprstate = ps;
2341                 else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
2342                         curstate = ps;
2343         }
2344
2345         pipe_wm->pipe_enabled = cstate->base.active;
2346         if (sprstate) {
2347                 pipe_wm->sprites_enabled = sprstate->visible;
2348                 pipe_wm->sprites_scaled = sprstate->visible &&
2349                         (drm_rect_width(&sprstate->dst) != drm_rect_width(&sprstate->src) >> 16 ||
2350                          drm_rect_height(&sprstate->dst) != drm_rect_height(&sprstate->src) >> 16);
2351         }
2352
2353         usable_level = max_level;
2354
2355         /* ILK/SNB: LP2+ watermarks only w/o sprites */
2356         if (INTEL_INFO(dev)->gen <= 6 && pipe_wm->sprites_enabled)
2357                 usable_level = 1;
2358
2359         /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2360         if (pipe_wm->sprites_scaled)
2361                 usable_level = 0;
2362
2363         ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
2364                              pristate, sprstate, curstate, &pipe_wm->raw_wm[0]);
2365
2366         memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm));
2367         pipe_wm->wm[0] = pipe_wm->raw_wm[0];
2368
2369         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2370                 pipe_wm->linetime = hsw_compute_linetime_wm(cstate);
2371
2372         if (!ilk_validate_pipe_wm(dev, pipe_wm))
2373                 return -EINVAL;
2374
2375         ilk_compute_wm_reg_maximums(dev, 1, &max);
2376
2377         for (level = 1; level <= max_level; level++) {
2378                 struct intel_wm_level *wm = &pipe_wm->raw_wm[level];
2379
2380                 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,
2381                                      pristate, sprstate, curstate, wm);
2382
2383                 /*
2384                  * Disable any watermark level that exceeds the
2385                  * register maximums since such watermarks are
2386                  * always invalid.
2387                  */
2388                 if (level > usable_level)
2389                         continue;
2390
2391                 if (ilk_validate_wm_level(level, &max, wm))
2392                         pipe_wm->wm[level] = *wm;
2393                 else
2394                         usable_level = level;
2395         }
2396
2397         return 0;
2398 }
2399
2400 /*
2401  * Build a set of 'intermediate' watermark values that satisfy both the old
2402  * state and the new state.  These can be programmed to the hardware
2403  * immediately.
2404  */
2405 static int ilk_compute_intermediate_wm(struct drm_device *dev,
2406                                        struct intel_crtc *intel_crtc,
2407                                        struct intel_crtc_state *newstate)
2408 {
2409         struct intel_pipe_wm *a = &newstate->wm.ilk.intermediate;
2410         struct intel_pipe_wm *b = &intel_crtc->wm.active.ilk;
2411         int level, max_level = ilk_wm_max_level(dev);
2412
2413         /*
2414          * Start with the final, target watermarks, then combine with the
2415          * currently active watermarks to get values that are safe both before
2416          * and after the vblank.
2417          */
2418         *a = newstate->wm.ilk.optimal;
2419         a->pipe_enabled |= b->pipe_enabled;
2420         a->sprites_enabled |= b->sprites_enabled;
2421         a->sprites_scaled |= b->sprites_scaled;
2422
2423         for (level = 0; level <= max_level; level++) {
2424                 struct intel_wm_level *a_wm = &a->wm[level];
2425                 const struct intel_wm_level *b_wm = &b->wm[level];
2426
2427                 a_wm->enable &= b_wm->enable;
2428                 a_wm->pri_val = max(a_wm->pri_val, b_wm->pri_val);
2429                 a_wm->spr_val = max(a_wm->spr_val, b_wm->spr_val);
2430                 a_wm->cur_val = max(a_wm->cur_val, b_wm->cur_val);
2431                 a_wm->fbc_val = max(a_wm->fbc_val, b_wm->fbc_val);
2432         }
2433
2434         /*
2435          * We need to make sure that these merged watermark values are
2436          * actually a valid configuration themselves.  If they're not,
2437          * there's no safe way to transition from the old state to
2438          * the new state, so we need to fail the atomic transaction.
2439          */
2440         if (!ilk_validate_pipe_wm(dev, a))
2441                 return -EINVAL;
2442
2443         /*
2444          * If our intermediate WM are identical to the final WM, then we can
2445          * omit the post-vblank programming; only update if it's different.
2446          */
2447         if (memcmp(a, &newstate->wm.ilk.optimal, sizeof(*a)) == 0)
2448                 newstate->wm.need_postvbl_update = false;
2449
2450         return 0;
2451 }
2452
2453 /*
2454  * Merge the watermarks from all active pipes for a specific level.
2455  */
2456 static void ilk_merge_wm_level(struct drm_device *dev,
2457                                int level,
2458                                struct intel_wm_level *ret_wm)
2459 {
2460         const struct intel_crtc *intel_crtc;
2461
2462         ret_wm->enable = true;
2463
2464         for_each_intel_crtc(dev, intel_crtc) {
2465                 const struct intel_pipe_wm *active = &intel_crtc->wm.active.ilk;
2466                 const struct intel_wm_level *wm = &active->wm[level];
2467
2468                 if (!active->pipe_enabled)
2469                         continue;
2470
2471                 /*
2472                  * The watermark values may have been used in the past,
2473                  * so we must maintain them in the registers for some
2474                  * time even if the level is now disabled.
2475                  */
2476                 if (!wm->enable)
2477                         ret_wm->enable = false;
2478
2479                 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2480                 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2481                 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2482                 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2483         }
2484 }
2485
2486 /*
2487  * Merge all low power watermarks for all active pipes.
2488  */
2489 static void ilk_wm_merge(struct drm_device *dev,
2490                          const struct intel_wm_config *config,
2491                          const struct ilk_wm_maximums *max,
2492                          struct intel_pipe_wm *merged)
2493 {
2494         struct drm_i915_private *dev_priv = dev->dev_private;
2495         int level, max_level = ilk_wm_max_level(dev);
2496         int last_enabled_level = max_level;
2497
2498         /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2499         if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2500             config->num_pipes_active > 1)
2501                 last_enabled_level = 0;
2502
2503         /* ILK: FBC WM must be disabled always */
2504         merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
2505
2506         /* merge each WM1+ level */
2507         for (level = 1; level <= max_level; level++) {
2508                 struct intel_wm_level *wm = &merged->wm[level];
2509
2510                 ilk_merge_wm_level(dev, level, wm);
2511
2512                 if (level > last_enabled_level)
2513                         wm->enable = false;
2514                 else if (!ilk_validate_wm_level(level, max, wm))
2515                         /* make sure all following levels get disabled */
2516                         last_enabled_level = level - 1;
2517
2518                 /*
2519                  * The spec says it is preferred to disable
2520                  * FBC WMs instead of disabling a WM level.
2521                  */
2522                 if (wm->fbc_val > max->fbc) {
2523                         if (wm->enable)
2524                                 merged->fbc_wm_enabled = false;
2525                         wm->fbc_val = 0;
2526                 }
2527         }
2528
2529         /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2530         /*
2531          * FIXME this is racy. FBC might get enabled later.
2532          * What we should check here is whether FBC can be
2533          * enabled sometime later.
2534          */
2535         if (IS_GEN5(dev) && !merged->fbc_wm_enabled &&
2536             intel_fbc_is_active(dev_priv)) {
2537                 for (level = 2; level <= max_level; level++) {
2538                         struct intel_wm_level *wm = &merged->wm[level];
2539
2540                         wm->enable = false;
2541                 }
2542         }
2543 }
2544
2545 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2546 {
2547         /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2548         return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2549 }
2550
2551 /* The value we need to program into the WM_LPx latency field */
2552 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2553 {
2554         struct drm_i915_private *dev_priv = dev->dev_private;
2555
2556         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2557                 return 2 * level;
2558         else
2559                 return dev_priv->wm.pri_latency[level];
2560 }
2561
2562 static void ilk_compute_wm_results(struct drm_device *dev,
2563                                    const struct intel_pipe_wm *merged,
2564                                    enum intel_ddb_partitioning partitioning,
2565                                    struct ilk_wm_values *results)
2566 {
2567         struct intel_crtc *intel_crtc;
2568         int level, wm_lp;
2569
2570         results->enable_fbc_wm = merged->fbc_wm_enabled;
2571         results->partitioning = partitioning;
2572
2573         /* LP1+ register values */
2574         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2575                 const struct intel_wm_level *r;
2576
2577                 level = ilk_wm_lp_to_level(wm_lp, merged);
2578
2579                 r = &merged->wm[level];
2580
2581                 /*
2582                  * Maintain the watermark values even if the level is
2583                  * disabled. Doing otherwise could cause underruns.
2584                  */
2585                 results->wm_lp[wm_lp - 1] =
2586                         (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
2587                         (r->pri_val << WM1_LP_SR_SHIFT) |
2588                         r->cur_val;
2589
2590                 if (r->enable)
2591                         results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2592
2593                 if (INTEL_INFO(dev)->gen >= 8)
2594                         results->wm_lp[wm_lp - 1] |=
2595                                 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2596                 else
2597                         results->wm_lp[wm_lp - 1] |=
2598                                 r->fbc_val << WM1_LP_FBC_SHIFT;
2599
2600                 /*
2601                  * Always set WM1S_LP_EN when spr_val != 0, even if the
2602                  * level is disabled. Doing otherwise could cause underruns.
2603                  */
2604                 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2605                         WARN_ON(wm_lp != 1);
2606                         results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2607                 } else
2608                         results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2609         }
2610
2611         /* LP0 register values */
2612         for_each_intel_crtc(dev, intel_crtc) {
2613                 enum pipe pipe = intel_crtc->pipe;
2614                 const struct intel_wm_level *r =
2615                         &intel_crtc->wm.active.ilk.wm[0];
2616
2617                 if (WARN_ON(!r->enable))
2618                         continue;
2619
2620                 results->wm_linetime[pipe] = intel_crtc->wm.active.ilk.linetime;
2621
2622                 results->wm_pipe[pipe] =
2623                         (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2624                         (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2625                         r->cur_val;
2626         }
2627 }
2628
2629 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2630  * case both are at the same level. Prefer r1 in case they're the same. */
2631 static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
2632                                                   struct intel_pipe_wm *r1,
2633                                                   struct intel_pipe_wm *r2)
2634 {
2635         int level, max_level = ilk_wm_max_level(dev);
2636         int level1 = 0, level2 = 0;
2637
2638         for (level = 1; level <= max_level; level++) {
2639                 if (r1->wm[level].enable)
2640                         level1 = level;
2641                 if (r2->wm[level].enable)
2642                         level2 = level;
2643         }
2644
2645         if (level1 == level2) {
2646                 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2647                         return r2;
2648                 else
2649                         return r1;
2650         } else if (level1 > level2) {
2651                 return r1;
2652         } else {
2653                 return r2;
2654         }
2655 }
2656
2657 /* dirty bits used to track which watermarks need changes */
2658 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2659 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2660 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2661 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2662 #define WM_DIRTY_FBC (1 << 24)
2663 #define WM_DIRTY_DDB (1 << 25)
2664
2665 static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
2666                                          const struct ilk_wm_values *old,
2667                                          const struct ilk_wm_values *new)
2668 {
2669         unsigned int dirty = 0;
2670         enum pipe pipe;
2671         int wm_lp;
2672
2673         for_each_pipe(dev_priv, pipe) {
2674                 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2675                         dirty |= WM_DIRTY_LINETIME(pipe);
2676                         /* Must disable LP1+ watermarks too */
2677                         dirty |= WM_DIRTY_LP_ALL;
2678                 }
2679
2680                 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2681                         dirty |= WM_DIRTY_PIPE(pipe);
2682                         /* Must disable LP1+ watermarks too */
2683                         dirty |= WM_DIRTY_LP_ALL;
2684                 }
2685         }
2686
2687         if (old->enable_fbc_wm != new->enable_fbc_wm) {
2688                 dirty |= WM_DIRTY_FBC;
2689                 /* Must disable LP1+ watermarks too */
2690                 dirty |= WM_DIRTY_LP_ALL;
2691         }
2692
2693         if (old->partitioning != new->partitioning) {
2694                 dirty |= WM_DIRTY_DDB;
2695                 /* Must disable LP1+ watermarks too */
2696                 dirty |= WM_DIRTY_LP_ALL;
2697         }
2698
2699         /* LP1+ watermarks already deemed dirty, no need to continue */
2700         if (dirty & WM_DIRTY_LP_ALL)
2701                 return dirty;
2702
2703         /* Find the lowest numbered LP1+ watermark in need of an update... */
2704         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2705                 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2706                     old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2707                         break;
2708         }
2709
2710         /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2711         for (; wm_lp <= 3; wm_lp++)
2712                 dirty |= WM_DIRTY_LP(wm_lp);
2713
2714         return dirty;
2715 }
2716
2717 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2718                                unsigned int dirty)
2719 {
2720         struct ilk_wm_values *previous = &dev_priv->wm.hw;
2721         bool changed = false;
2722
2723         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2724                 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2725                 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
2726                 changed = true;
2727         }
2728         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2729                 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2730                 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
2731                 changed = true;
2732         }
2733         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2734                 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2735                 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
2736                 changed = true;
2737         }
2738
2739         /*
2740          * Don't touch WM1S_LP_EN here.
2741          * Doing so could cause underruns.
2742          */
2743
2744         return changed;
2745 }
2746
2747 /*
2748  * The spec says we shouldn't write when we don't need, because every write
2749  * causes WMs to be re-evaluated, expending some power.
2750  */
2751 static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2752                                 struct ilk_wm_values *results)
2753 {
2754         struct drm_device *dev = dev_priv->dev;
2755         struct ilk_wm_values *previous = &dev_priv->wm.hw;
2756         unsigned int dirty;
2757         uint32_t val;
2758
2759         dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
2760         if (!dirty)
2761                 return;
2762
2763         _ilk_disable_lp_wm(dev_priv, dirty);
2764
2765         if (dirty & WM_DIRTY_PIPE(PIPE_A))
2766                 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2767         if (dirty & WM_DIRTY_PIPE(PIPE_B))
2768                 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2769         if (dirty & WM_DIRTY_PIPE(PIPE_C))
2770                 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2771
2772         if (dirty & WM_DIRTY_LINETIME(PIPE_A))
2773                 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2774         if (dirty & WM_DIRTY_LINETIME(PIPE_B))
2775                 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2776         if (dirty & WM_DIRTY_LINETIME(PIPE_C))
2777                 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2778
2779         if (dirty & WM_DIRTY_DDB) {
2780                 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2781                         val = I915_READ(WM_MISC);
2782                         if (results->partitioning == INTEL_DDB_PART_1_2)
2783                                 val &= ~WM_MISC_DATA_PARTITION_5_6;
2784                         else
2785                                 val |= WM_MISC_DATA_PARTITION_5_6;
2786                         I915_WRITE(WM_MISC, val);
2787                 } else {
2788                         val = I915_READ(DISP_ARB_CTL2);
2789                         if (results->partitioning == INTEL_DDB_PART_1_2)
2790                                 val &= ~DISP_DATA_PARTITION_5_6;
2791                         else
2792                                 val |= DISP_DATA_PARTITION_5_6;
2793                         I915_WRITE(DISP_ARB_CTL2, val);
2794                 }
2795         }
2796
2797         if (dirty & WM_DIRTY_FBC) {
2798                 val = I915_READ(DISP_ARB_CTL);
2799                 if (results->enable_fbc_wm)
2800                         val &= ~DISP_FBC_WM_DIS;
2801                 else
2802                         val |= DISP_FBC_WM_DIS;
2803                 I915_WRITE(DISP_ARB_CTL, val);
2804         }
2805
2806         if (dirty & WM_DIRTY_LP(1) &&
2807             previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2808                 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2809
2810         if (INTEL_INFO(dev)->gen >= 7) {
2811                 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2812                         I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2813                 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2814                         I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2815         }
2816
2817         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
2818                 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2819         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
2820                 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2821         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
2822                 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2823
2824         dev_priv->wm.hw = *results;
2825 }
2826
2827 bool ilk_disable_lp_wm(struct drm_device *dev)
2828 {
2829         struct drm_i915_private *dev_priv = dev->dev_private;
2830
2831         return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2832 }
2833
2834 /*
2835  * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
2836  * different active planes.
2837  */
2838
2839 #define SKL_DDB_SIZE            896     /* in blocks */
2840 #define BXT_DDB_SIZE            512
2841
2842 /*
2843  * Return the index of a plane in the SKL DDB and wm result arrays.  Primary
2844  * plane is always in slot 0, cursor is always in slot I915_MAX_PLANES-1, and
2845  * other universal planes are in indices 1..n.  Note that this may leave unused
2846  * indices between the top "sprite" plane and the cursor.
2847  */
2848 static int
2849 skl_wm_plane_id(const struct intel_plane *plane)
2850 {
2851         switch (plane->base.type) {
2852         case DRM_PLANE_TYPE_PRIMARY:
2853                 return 0;
2854         case DRM_PLANE_TYPE_CURSOR:
2855                 return PLANE_CURSOR;
2856         case DRM_PLANE_TYPE_OVERLAY:
2857                 return plane->plane + 1;
2858         default:
2859                 MISSING_CASE(plane->base.type);
2860                 return plane->plane;
2861         }
2862 }
2863
2864 static void
2865 skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
2866                                    const struct intel_crtc_state *cstate,
2867                                    struct skl_ddb_entry *alloc, /* out */
2868                                    int *num_active /* out */)
2869 {
2870         struct drm_atomic_state *state = cstate->base.state;
2871         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
2872         struct drm_i915_private *dev_priv = to_i915(dev);
2873         struct drm_crtc *for_crtc = cstate->base.crtc;
2874         unsigned int pipe_size, ddb_size;
2875         int nth_active_pipe;
2876         int pipe = to_intel_crtc(for_crtc)->pipe;
2877
2878         if (WARN_ON(!state) || !cstate->base.active) {
2879                 alloc->start = 0;
2880                 alloc->end = 0;
2881                 *num_active = hweight32(dev_priv->active_crtcs);
2882                 return;
2883         }
2884
2885         if (intel_state->active_pipe_changes)
2886                 *num_active = hweight32(intel_state->active_crtcs);
2887         else
2888                 *num_active = hweight32(dev_priv->active_crtcs);
2889
2890         if (IS_BROXTON(dev))
2891                 ddb_size = BXT_DDB_SIZE;
2892         else
2893                 ddb_size = SKL_DDB_SIZE;
2894
2895         ddb_size -= 4; /* 4 blocks for bypass path allocation */
2896
2897         /*
2898          * If the state doesn't change the active CRTC's, then there's
2899          * no need to recalculate; the existing pipe allocation limits
2900          * should remain unchanged.  Note that we're safe from racing
2901          * commits since any racing commit that changes the active CRTC
2902          * list would need to grab _all_ crtc locks, including the one
2903          * we currently hold.
2904          */
2905         if (!intel_state->active_pipe_changes) {
2906                 *alloc = dev_priv->wm.skl_hw.ddb.pipe[pipe];
2907                 return;
2908         }
2909
2910         nth_active_pipe = hweight32(intel_state->active_crtcs &
2911                                     (drm_crtc_mask(for_crtc) - 1));
2912         pipe_size = ddb_size / hweight32(intel_state->active_crtcs);
2913         alloc->start = nth_active_pipe * ddb_size / *num_active;
2914         alloc->end = alloc->start + pipe_size;
2915 }
2916
2917 static unsigned int skl_cursor_allocation(int num_active)
2918 {
2919         if (num_active == 1)
2920                 return 32;
2921
2922         return 8;
2923 }
2924
2925 static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
2926 {
2927         entry->start = reg & 0x3ff;
2928         entry->end = (reg >> 16) & 0x3ff;
2929         if (entry->end)
2930                 entry->end += 1;
2931 }
2932
2933 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2934                           struct skl_ddb_allocation *ddb /* out */)
2935 {
2936         enum pipe pipe;
2937         int plane;
2938         u32 val;
2939
2940         memset(ddb, 0, sizeof(*ddb));
2941
2942         for_each_pipe(dev_priv, pipe) {
2943                 enum intel_display_power_domain power_domain;
2944
2945                 power_domain = POWER_DOMAIN_PIPE(pipe);
2946                 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
2947                         continue;
2948
2949                 for_each_plane(dev_priv, pipe, plane) {
2950                         val = I915_READ(PLANE_BUF_CFG(pipe, plane));
2951                         skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
2952                                                    val);
2953                 }
2954
2955                 val = I915_READ(CUR_BUF_CFG(pipe));
2956                 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR],
2957                                            val);
2958
2959                 intel_display_power_put(dev_priv, power_domain);
2960         }
2961 }
2962
2963 /*
2964  * Determines the downscale amount of a plane for the purposes of watermark calculations.
2965  * The bspec defines downscale amount as:
2966  *
2967  * """
2968  * Horizontal down scale amount = maximum[1, Horizontal source size /
2969  *                                           Horizontal destination size]
2970  * Vertical down scale amount = maximum[1, Vertical source size /
2971  *                                         Vertical destination size]
2972  * Total down scale amount = Horizontal down scale amount *
2973  *                           Vertical down scale amount
2974  * """
2975  *
2976  * Return value is provided in 16.16 fixed point form to retain fractional part.
2977  * Caller should take care of dividing & rounding off the value.
2978  */
2979 static uint32_t
2980 skl_plane_downscale_amount(const struct intel_plane_state *pstate)
2981 {
2982         uint32_t downscale_h, downscale_w;
2983         uint32_t src_w, src_h, dst_w, dst_h;
2984
2985         if (WARN_ON(!pstate->visible))
2986                 return DRM_PLANE_HELPER_NO_SCALING;
2987
2988         /* n.b., src is 16.16 fixed point, dst is whole integer */
2989         src_w = drm_rect_width(&pstate->src);
2990         src_h = drm_rect_height(&pstate->src);
2991         dst_w = drm_rect_width(&pstate->dst);
2992         dst_h = drm_rect_height(&pstate->dst);
2993         if (intel_rotation_90_or_270(pstate->base.rotation))
2994                 swap(dst_w, dst_h);
2995
2996         downscale_h = max(src_h / dst_h, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
2997         downscale_w = max(src_w / dst_w, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
2998
2999         /* Provide result in 16.16 fixed point */
3000         return (uint64_t)downscale_w * downscale_h >> 16;
3001 }
3002
3003 static unsigned int
3004 skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
3005                              const struct drm_plane_state *pstate,
3006                              int y)
3007 {
3008         struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
3009         struct drm_framebuffer *fb = pstate->fb;
3010         uint32_t down_scale_amount, data_rate;
3011         uint32_t width = 0, height = 0;
3012         unsigned format = fb ? fb->pixel_format : DRM_FORMAT_XRGB8888;
3013
3014         if (!intel_pstate->visible)
3015                 return 0;
3016         if (pstate->plane->type == DRM_PLANE_TYPE_CURSOR)
3017                 return 0;
3018         if (y && format != DRM_FORMAT_NV12)
3019                 return 0;
3020
3021         width = drm_rect_width(&intel_pstate->src) >> 16;
3022         height = drm_rect_height(&intel_pstate->src) >> 16;
3023
3024         if (intel_rotation_90_or_270(pstate->rotation))
3025                 swap(width, height);
3026
3027         /* for planar format */
3028         if (format == DRM_FORMAT_NV12) {
3029                 if (y)  /* y-plane data rate */
3030                         data_rate = width * height *
3031                                 drm_format_plane_cpp(format, 0);
3032                 else    /* uv-plane data rate */
3033                         data_rate = (width / 2) * (height / 2) *
3034                                 drm_format_plane_cpp(format, 1);
3035         } else {
3036                 /* for packed formats */
3037                 data_rate = width * height * drm_format_plane_cpp(format, 0);
3038         }
3039
3040         down_scale_amount = skl_plane_downscale_amount(intel_pstate);
3041
3042         return (uint64_t)data_rate * down_scale_amount >> 16;
3043 }
3044
3045 /*
3046  * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
3047  * a 8192x4096@32bpp framebuffer:
3048  *   3 * 4096 * 8192  * 4 < 2^32
3049  */
3050 static unsigned int
3051 skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate)
3052 {
3053         struct drm_crtc_state *cstate = &intel_cstate->base;
3054         struct drm_atomic_state *state = cstate->state;
3055         struct drm_crtc *crtc = cstate->crtc;
3056         struct drm_device *dev = crtc->dev;
3057         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3058         const struct drm_plane *plane;
3059         const struct intel_plane *intel_plane;
3060         struct drm_plane_state *pstate;
3061         unsigned int rate, total_data_rate = 0;
3062         int id;
3063         int i;
3064
3065         if (WARN_ON(!state))
3066                 return 0;
3067
3068         /* Calculate and cache data rate for each plane */
3069         for_each_plane_in_state(state, plane, pstate, i) {
3070                 id = skl_wm_plane_id(to_intel_plane(plane));
3071                 intel_plane = to_intel_plane(plane);
3072
3073                 if (intel_plane->pipe != intel_crtc->pipe)
3074                         continue;
3075
3076                 /* packed/uv */
3077                 rate = skl_plane_relative_data_rate(intel_cstate,
3078                                                     pstate, 0);
3079                 intel_cstate->wm.skl.plane_data_rate[id] = rate;
3080
3081                 /* y-plane */
3082                 rate = skl_plane_relative_data_rate(intel_cstate,
3083                                                     pstate, 1);
3084                 intel_cstate->wm.skl.plane_y_data_rate[id] = rate;
3085         }
3086
3087         /* Calculate CRTC's total data rate from cached values */
3088         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3089                 int id = skl_wm_plane_id(intel_plane);
3090
3091                 /* packed/uv */
3092                 total_data_rate += intel_cstate->wm.skl.plane_data_rate[id];
3093                 total_data_rate += intel_cstate->wm.skl.plane_y_data_rate[id];
3094         }
3095
3096         WARN_ON(cstate->plane_mask && total_data_rate == 0);
3097
3098         return total_data_rate;
3099 }
3100
3101 static uint16_t
3102 skl_ddb_min_alloc(const struct drm_plane_state *pstate,
3103                   const int y)
3104 {
3105         struct drm_framebuffer *fb = pstate->fb;
3106         struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
3107         uint32_t src_w, src_h;
3108         uint32_t min_scanlines = 8;
3109         uint8_t plane_bpp;
3110
3111         if (WARN_ON(!fb))
3112                 return 0;
3113
3114         /* For packed formats, no y-plane, return 0 */
3115         if (y && fb->pixel_format != DRM_FORMAT_NV12)
3116                 return 0;
3117
3118         /* For Non Y-tile return 8-blocks */
3119         if (fb->modifier[0] != I915_FORMAT_MOD_Y_TILED &&
3120             fb->modifier[0] != I915_FORMAT_MOD_Yf_TILED)
3121                 return 8;
3122
3123         src_w = drm_rect_width(&intel_pstate->src) >> 16;
3124         src_h = drm_rect_height(&intel_pstate->src) >> 16;
3125
3126         if (intel_rotation_90_or_270(pstate->rotation))
3127                 swap(src_w, src_h);
3128
3129         /* Halve UV plane width and height for NV12 */
3130         if (fb->pixel_format == DRM_FORMAT_NV12 && !y) {
3131                 src_w /= 2;
3132                 src_h /= 2;
3133         }
3134
3135         if (fb->pixel_format == DRM_FORMAT_NV12 && !y)
3136                 plane_bpp = drm_format_plane_cpp(fb->pixel_format, 1);
3137         else
3138                 plane_bpp = drm_format_plane_cpp(fb->pixel_format, 0);
3139
3140         if (intel_rotation_90_or_270(pstate->rotation)) {
3141                 switch (plane_bpp) {
3142                 case 1:
3143                         min_scanlines = 32;
3144                         break;
3145                 case 2:
3146                         min_scanlines = 16;
3147                         break;
3148                 case 4:
3149                         min_scanlines = 8;
3150                         break;
3151                 case 8:
3152                         min_scanlines = 4;
3153                         break;
3154                 default:
3155                         WARN(1, "Unsupported pixel depth %u for rotation",
3156                              plane_bpp);
3157                         min_scanlines = 32;
3158                 }
3159         }
3160
3161         return DIV_ROUND_UP((4 * src_w * plane_bpp), 512) * min_scanlines/4 + 3;
3162 }
3163
3164 static int
3165 skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
3166                       struct skl_ddb_allocation *ddb /* out */)
3167 {
3168         struct drm_atomic_state *state = cstate->base.state;
3169         struct drm_crtc *crtc = cstate->base.crtc;
3170         struct drm_device *dev = crtc->dev;
3171         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3172         struct intel_plane *intel_plane;
3173         struct drm_plane *plane;
3174         struct drm_plane_state *pstate;
3175         enum pipe pipe = intel_crtc->pipe;
3176         struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
3177         uint16_t alloc_size, start, cursor_blocks;
3178         uint16_t *minimum = cstate->wm.skl.minimum_blocks;
3179         uint16_t *y_minimum = cstate->wm.skl.minimum_y_blocks;
3180         unsigned int total_data_rate;
3181         int num_active;
3182         int id, i;
3183
3184         if (WARN_ON(!state))
3185                 return 0;
3186
3187         if (!cstate->base.active) {
3188                 ddb->pipe[pipe].start = ddb->pipe[pipe].end = 0;
3189                 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
3190                 memset(ddb->y_plane[pipe], 0, sizeof(ddb->y_plane[pipe]));
3191                 return 0;
3192         }
3193
3194         skl_ddb_get_pipe_allocation_limits(dev, cstate, alloc, &num_active);
3195         alloc_size = skl_ddb_entry_size(alloc);
3196         if (alloc_size == 0) {
3197                 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
3198                 return 0;
3199         }
3200
3201         cursor_blocks = skl_cursor_allocation(num_active);
3202         ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - cursor_blocks;
3203         ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
3204
3205         alloc_size -= cursor_blocks;
3206
3207         /* 1. Allocate the mininum required blocks for each active plane */
3208         for_each_plane_in_state(state, plane, pstate, i) {
3209                 intel_plane = to_intel_plane(plane);
3210                 id = skl_wm_plane_id(intel_plane);
3211
3212                 if (intel_plane->pipe != pipe)
3213                         continue;
3214
3215                 if (!to_intel_plane_state(pstate)->visible) {
3216                         minimum[id] = 0;
3217                         y_minimum[id] = 0;
3218                         continue;
3219                 }
3220                 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
3221                         minimum[id] = 0;
3222                         y_minimum[id] = 0;
3223                         continue;
3224                 }
3225
3226                 minimum[id] = skl_ddb_min_alloc(pstate, 0);
3227                 y_minimum[id] = skl_ddb_min_alloc(pstate, 1);
3228         }
3229
3230         for (i = 0; i < PLANE_CURSOR; i++) {
3231                 alloc_size -= minimum[i];
3232                 alloc_size -= y_minimum[i];
3233         }
3234
3235         /*
3236          * 2. Distribute the remaining space in proportion to the amount of
3237          * data each plane needs to fetch from memory.
3238          *
3239          * FIXME: we may not allocate every single block here.
3240          */
3241         total_data_rate = skl_get_total_relative_data_rate(cstate);
3242         if (total_data_rate == 0)
3243                 return 0;
3244
3245         start = alloc->start;
3246         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3247                 unsigned int data_rate, y_data_rate;
3248                 uint16_t plane_blocks, y_plane_blocks = 0;
3249                 int id = skl_wm_plane_id(intel_plane);
3250
3251                 data_rate = cstate->wm.skl.plane_data_rate[id];
3252
3253                 /*
3254                  * allocation for (packed formats) or (uv-plane part of planar format):
3255                  * promote the expression to 64 bits to avoid overflowing, the
3256                  * result is < available as data_rate / total_data_rate < 1
3257                  */
3258                 plane_blocks = minimum[id];
3259                 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
3260                                         total_data_rate);
3261
3262                 /* Leave disabled planes at (0,0) */
3263                 if (data_rate) {
3264                         ddb->plane[pipe][id].start = start;
3265                         ddb->plane[pipe][id].end = start + plane_blocks;
3266                 }
3267
3268                 start += plane_blocks;
3269
3270                 /*
3271                  * allocation for y_plane part of planar format:
3272                  */
3273                 y_data_rate = cstate->wm.skl.plane_y_data_rate[id];
3274
3275                 y_plane_blocks = y_minimum[id];
3276                 y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
3277                                         total_data_rate);
3278
3279                 if (y_data_rate) {
3280                         ddb->y_plane[pipe][id].start = start;
3281                         ddb->y_plane[pipe][id].end = start + y_plane_blocks;
3282                 }
3283
3284                 start += y_plane_blocks;
3285         }
3286
3287         return 0;
3288 }
3289
3290 static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
3291 {
3292         /* TODO: Take into account the scalers once we support them */
3293         return config->base.adjusted_mode.crtc_clock;
3294 }
3295
3296 /*
3297  * The max latency should be 257 (max the punit can code is 255 and we add 2us
3298  * for the read latency) and cpp should always be <= 8, so that
3299  * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3300  * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3301 */
3302 static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
3303 {
3304         uint32_t wm_intermediate_val, ret;
3305
3306         if (latency == 0)
3307                 return UINT_MAX;
3308
3309         wm_intermediate_val = latency * pixel_rate * cpp / 512;
3310         ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
3311
3312         return ret;
3313 }
3314
3315 static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
3316                                uint32_t horiz_pixels, uint8_t cpp,
3317                                uint64_t tiling, uint32_t latency)
3318 {
3319         uint32_t ret;
3320         uint32_t plane_bytes_per_line, plane_blocks_per_line;
3321         uint32_t wm_intermediate_val;
3322
3323         if (latency == 0)
3324                 return UINT_MAX;
3325
3326         plane_bytes_per_line = horiz_pixels * cpp;
3327
3328         if (tiling == I915_FORMAT_MOD_Y_TILED ||
3329             tiling == I915_FORMAT_MOD_Yf_TILED) {
3330                 plane_bytes_per_line *= 4;
3331                 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3332                 plane_blocks_per_line /= 4;
3333         } else {
3334                 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3335         }
3336
3337         wm_intermediate_val = latency * pixel_rate;
3338         ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
3339                                 plane_blocks_per_line;
3340
3341         return ret;
3342 }
3343
3344 static uint32_t skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cstate,
3345                                               struct intel_plane_state *pstate)
3346 {
3347         uint64_t adjusted_pixel_rate;
3348         uint64_t downscale_amount;
3349         uint64_t pixel_rate;
3350
3351         /* Shouldn't reach here on disabled planes... */
3352         if (WARN_ON(!pstate->visible))
3353                 return 0;
3354
3355         /*
3356          * Adjusted plane pixel rate is just the pipe's adjusted pixel rate
3357          * with additional adjustments for plane-specific scaling.
3358          */
3359         adjusted_pixel_rate = skl_pipe_pixel_rate(cstate);
3360         downscale_amount = skl_plane_downscale_amount(pstate);
3361
3362         pixel_rate = adjusted_pixel_rate * downscale_amount >> 16;
3363         WARN_ON(pixel_rate != clamp_t(uint32_t, pixel_rate, 0, ~0));
3364
3365         return pixel_rate;
3366 }
3367
3368 static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
3369                                 struct intel_crtc_state *cstate,
3370                                 struct intel_plane_state *intel_pstate,
3371                                 uint16_t ddb_allocation,
3372                                 int level,
3373                                 uint16_t *out_blocks, /* out */
3374                                 uint8_t *out_lines, /* out */
3375                                 bool *enabled /* out */)
3376 {
3377         struct drm_plane_state *pstate = &intel_pstate->base;
3378         struct drm_framebuffer *fb = pstate->fb;
3379         uint32_t latency = dev_priv->wm.skl_latency[level];
3380         uint32_t method1, method2;
3381         uint32_t plane_bytes_per_line, plane_blocks_per_line;
3382         uint32_t res_blocks, res_lines;
3383         uint32_t selected_result;
3384         uint8_t cpp;
3385         uint32_t width = 0, height = 0;
3386         uint32_t plane_pixel_rate;
3387
3388         if (latency == 0 || !cstate->base.active || !intel_pstate->visible) {
3389                 *enabled = false;
3390                 return 0;
3391         }
3392
3393         width = drm_rect_width(&intel_pstate->src) >> 16;
3394         height = drm_rect_height(&intel_pstate->src) >> 16;
3395
3396         if (intel_rotation_90_or_270(pstate->rotation))
3397                 swap(width, height);
3398
3399         cpp = drm_format_plane_cpp(fb->pixel_format, 0);
3400         plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate, intel_pstate);
3401
3402         method1 = skl_wm_method1(plane_pixel_rate, cpp, latency);
3403         method2 = skl_wm_method2(plane_pixel_rate,
3404                                  cstate->base.adjusted_mode.crtc_htotal,
3405                                  width,
3406                                  cpp,
3407                                  fb->modifier[0],
3408                                  latency);
3409
3410         plane_bytes_per_line = width * cpp;
3411         plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3412
3413         if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3414             fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
3415                 uint32_t min_scanlines = 4;
3416                 uint32_t y_tile_minimum;
3417                 if (intel_rotation_90_or_270(pstate->rotation)) {
3418                         int cpp = (fb->pixel_format == DRM_FORMAT_NV12) ?
3419                                 drm_format_plane_cpp(fb->pixel_format, 1) :
3420                                 drm_format_plane_cpp(fb->pixel_format, 0);
3421
3422                         switch (cpp) {
3423                         case 1:
3424                                 min_scanlines = 16;
3425                                 break;
3426                         case 2:
3427                                 min_scanlines = 8;
3428                                 break;
3429                         case 8:
3430                                 WARN(1, "Unsupported pixel depth for rotation");
3431                         }
3432                 }
3433                 y_tile_minimum = plane_blocks_per_line * min_scanlines;
3434                 selected_result = max(method2, y_tile_minimum);
3435         } else {
3436                 if ((ddb_allocation / plane_blocks_per_line) >= 1)
3437                         selected_result = min(method1, method2);
3438                 else
3439                         selected_result = method1;
3440         }
3441
3442         res_blocks = selected_result + 1;
3443         res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
3444
3445         if (level >= 1 && level <= 7) {
3446                 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3447                     fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED)
3448                         res_lines += 4;
3449                 else
3450                         res_blocks++;
3451         }
3452
3453         if (res_blocks >= ddb_allocation || res_lines > 31) {
3454                 *enabled = false;
3455
3456                 /*
3457                  * If there are no valid level 0 watermarks, then we can't
3458                  * support this display configuration.
3459                  */
3460                 if (level) {
3461                         return 0;
3462                 } else {
3463                         DRM_DEBUG_KMS("Requested display configuration exceeds system watermark limitations\n");
3464                         DRM_DEBUG_KMS("Plane %d.%d: blocks required = %u/%u, lines required = %u/31\n",
3465                                       to_intel_crtc(cstate->base.crtc)->pipe,
3466                                       skl_wm_plane_id(to_intel_plane(pstate->plane)),
3467                                       res_blocks, ddb_allocation, res_lines);
3468
3469                         return -EINVAL;
3470                 }
3471         }
3472
3473         *out_blocks = res_blocks;
3474         *out_lines = res_lines;
3475         *enabled = true;
3476
3477         return 0;
3478 }
3479
3480 static int
3481 skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3482                      struct skl_ddb_allocation *ddb,
3483                      struct intel_crtc_state *cstate,
3484                      int level,
3485                      struct skl_wm_level *result)
3486 {
3487         struct drm_device *dev = dev_priv->dev;
3488         struct drm_atomic_state *state = cstate->base.state;
3489         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
3490         struct drm_plane *plane;
3491         struct intel_plane *intel_plane;
3492         struct intel_plane_state *intel_pstate;
3493         uint16_t ddb_blocks;
3494         enum pipe pipe = intel_crtc->pipe;
3495         int ret;
3496
3497         /*
3498          * We'll only calculate watermarks for planes that are actually
3499          * enabled, so make sure all other planes are set as disabled.
3500          */
3501         memset(result, 0, sizeof(*result));
3502
3503         for_each_intel_plane_mask(dev, intel_plane, cstate->base.plane_mask) {
3504                 int i = skl_wm_plane_id(intel_plane);
3505
3506                 plane = &intel_plane->base;
3507                 intel_pstate = NULL;
3508                 if (state)
3509                         intel_pstate =
3510                                 intel_atomic_get_existing_plane_state(state,
3511                                                                       intel_plane);
3512
3513                 /*
3514                  * Note: If we start supporting multiple pending atomic commits
3515                  * against the same planes/CRTC's in the future, plane->state
3516                  * will no longer be the correct pre-state to use for the
3517                  * calculations here and we'll need to change where we get the
3518                  * 'unchanged' plane data from.
3519                  *
3520                  * For now this is fine because we only allow one queued commit
3521                  * against a CRTC.  Even if the plane isn't modified by this
3522                  * transaction and we don't have a plane lock, we still have
3523                  * the CRTC's lock, so we know that no other transactions are
3524                  * racing with us to update it.
3525                  */
3526                 if (!intel_pstate)
3527                         intel_pstate = to_intel_plane_state(plane->state);
3528
3529                 WARN_ON(!intel_pstate->base.fb);
3530
3531                 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
3532
3533                 ret = skl_compute_plane_wm(dev_priv,
3534                                            cstate,
3535                                            intel_pstate,
3536                                            ddb_blocks,
3537                                            level,
3538                                            &result->plane_res_b[i],
3539                                            &result->plane_res_l[i],
3540                                            &result->plane_en[i]);
3541                 if (ret)
3542                         return ret;
3543         }
3544
3545         return 0;
3546 }
3547
3548 static uint32_t
3549 skl_compute_linetime_wm(struct intel_crtc_state *cstate)
3550 {
3551         if (!cstate->base.active)
3552                 return 0;
3553
3554         if (WARN_ON(skl_pipe_pixel_rate(cstate) == 0))
3555                 return 0;
3556
3557         return DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * 1000,
3558                             skl_pipe_pixel_rate(cstate));
3559 }
3560
3561 static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
3562                                       struct skl_wm_level *trans_wm /* out */)
3563 {
3564         struct drm_crtc *crtc = cstate->base.crtc;
3565         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3566         struct intel_plane *intel_plane;
3567
3568         if (!cstate->base.active)
3569                 return;
3570
3571         /* Until we know more, just disable transition WMs */
3572         for_each_intel_plane_on_crtc(crtc->dev, intel_crtc, intel_plane) {
3573                 int i = skl_wm_plane_id(intel_plane);
3574
3575                 trans_wm->plane_en[i] = false;
3576         }
3577 }
3578
3579 static int skl_build_pipe_wm(struct intel_crtc_state *cstate,
3580                              struct skl_ddb_allocation *ddb,
3581                              struct skl_pipe_wm *pipe_wm)
3582 {
3583         struct drm_device *dev = cstate->base.crtc->dev;
3584         const struct drm_i915_private *dev_priv = dev->dev_private;
3585         int level, max_level = ilk_wm_max_level(dev);
3586         int ret;
3587
3588         for (level = 0; level <= max_level; level++) {
3589                 ret = skl_compute_wm_level(dev_priv, ddb, cstate,
3590                                            level, &pipe_wm->wm[level]);
3591                 if (ret)
3592                         return ret;
3593         }
3594         pipe_wm->linetime = skl_compute_linetime_wm(cstate);
3595
3596         skl_compute_transition_wm(cstate, &pipe_wm->trans_wm);
3597
3598         return 0;
3599 }
3600
3601 static void skl_compute_wm_results(struct drm_device *dev,
3602                                    struct skl_pipe_wm *p_wm,
3603                                    struct skl_wm_values *r,
3604                                    struct intel_crtc *intel_crtc)
3605 {
3606         int level, max_level = ilk_wm_max_level(dev);
3607         enum pipe pipe = intel_crtc->pipe;
3608         uint32_t temp;
3609         int i;
3610
3611         for (level = 0; level <= max_level; level++) {
3612                 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3613                         temp = 0;
3614
3615                         temp |= p_wm->wm[level].plane_res_l[i] <<
3616                                         PLANE_WM_LINES_SHIFT;
3617                         temp |= p_wm->wm[level].plane_res_b[i];
3618                         if (p_wm->wm[level].plane_en[i])
3619                                 temp |= PLANE_WM_EN;
3620
3621                         r->plane[pipe][i][level] = temp;
3622                 }
3623
3624                 temp = 0;
3625
3626                 temp |= p_wm->wm[level].plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3627                 temp |= p_wm->wm[level].plane_res_b[PLANE_CURSOR];
3628
3629                 if (p_wm->wm[level].plane_en[PLANE_CURSOR])
3630                         temp |= PLANE_WM_EN;
3631
3632                 r->plane[pipe][PLANE_CURSOR][level] = temp;
3633
3634         }
3635
3636         /* transition WMs */
3637         for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3638                 temp = 0;
3639                 temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT;
3640                 temp |= p_wm->trans_wm.plane_res_b[i];
3641                 if (p_wm->trans_wm.plane_en[i])
3642                         temp |= PLANE_WM_EN;
3643
3644                 r->plane_trans[pipe][i] = temp;
3645         }
3646
3647         temp = 0;
3648         temp |= p_wm->trans_wm.plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3649         temp |= p_wm->trans_wm.plane_res_b[PLANE_CURSOR];
3650         if (p_wm->trans_wm.plane_en[PLANE_CURSOR])
3651                 temp |= PLANE_WM_EN;
3652
3653         r->plane_trans[pipe][PLANE_CURSOR] = temp;
3654
3655         r->wm_linetime[pipe] = p_wm->linetime;
3656 }
3657
3658 static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
3659                                 i915_reg_t reg,
3660                                 const struct skl_ddb_entry *entry)
3661 {
3662         if (entry->end)
3663                 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3664         else
3665                 I915_WRITE(reg, 0);
3666 }
3667
3668 static void skl_write_wm_values(struct drm_i915_private *dev_priv,
3669                                 const struct skl_wm_values *new)
3670 {
3671         struct drm_device *dev = dev_priv->dev;
3672         struct intel_crtc *crtc;
3673
3674         for_each_intel_crtc(dev, crtc) {
3675                 int i, level, max_level = ilk_wm_max_level(dev);
3676                 enum pipe pipe = crtc->pipe;
3677
3678                 if ((new->dirty_pipes & drm_crtc_mask(&crtc->base)) == 0)
3679                         continue;
3680                 if (!crtc->active)
3681                         continue;
3682
3683                 I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]);
3684
3685                 for (level = 0; level <= max_level; level++) {
3686                         for (i = 0; i < intel_num_planes(crtc); i++)
3687                                 I915_WRITE(PLANE_WM(pipe, i, level),
3688                                            new->plane[pipe][i][level]);
3689                         I915_WRITE(CUR_WM(pipe, level),
3690                                    new->plane[pipe][PLANE_CURSOR][level]);
3691                 }
3692                 for (i = 0; i < intel_num_planes(crtc); i++)
3693                         I915_WRITE(PLANE_WM_TRANS(pipe, i),
3694                                    new->plane_trans[pipe][i]);
3695                 I915_WRITE(CUR_WM_TRANS(pipe),
3696                            new->plane_trans[pipe][PLANE_CURSOR]);
3697
3698                 for (i = 0; i < intel_num_planes(crtc); i++) {
3699                         skl_ddb_entry_write(dev_priv,
3700                                             PLANE_BUF_CFG(pipe, i),
3701                                             &new->ddb.plane[pipe][i]);
3702                         skl_ddb_entry_write(dev_priv,
3703                                             PLANE_NV12_BUF_CFG(pipe, i),
3704                                             &new->ddb.y_plane[pipe][i]);
3705                 }
3706
3707                 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
3708                                     &new->ddb.plane[pipe][PLANE_CURSOR]);
3709         }
3710 }
3711
3712 /*
3713  * When setting up a new DDB allocation arrangement, we need to correctly
3714  * sequence the times at which the new allocations for the pipes are taken into
3715  * account or we'll have pipes fetching from space previously allocated to
3716  * another pipe.
3717  *
3718  * Roughly the sequence looks like:
3719  *  1. re-allocate the pipe(s) with the allocation being reduced and not
3720  *     overlapping with a previous light-up pipe (another way to put it is:
3721  *     pipes with their new allocation strickly included into their old ones).
3722  *  2. re-allocate the other pipes that get their allocation reduced
3723  *  3. allocate the pipes having their allocation increased
3724  *
3725  * Steps 1. and 2. are here to take care of the following case:
3726  * - Initially DDB looks like this:
3727  *     |   B    |   C    |
3728  * - enable pipe A.
3729  * - pipe B has a reduced DDB allocation that overlaps with the old pipe C
3730  *   allocation
3731  *     |  A  |  B  |  C  |
3732  *
3733  * We need to sequence the re-allocation: C, B, A (and not B, C, A).
3734  */
3735
3736 static void
3737 skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int pass)
3738 {
3739         int plane;
3740
3741         DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass);
3742
3743         for_each_plane(dev_priv, pipe, plane) {
3744                 I915_WRITE(PLANE_SURF(pipe, plane),
3745                            I915_READ(PLANE_SURF(pipe, plane)));
3746         }
3747         I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3748 }
3749
3750 static bool
3751 skl_ddb_allocation_included(const struct skl_ddb_allocation *old,
3752                             const struct skl_ddb_allocation *new,
3753                             enum pipe pipe)
3754 {
3755         uint16_t old_size, new_size;
3756
3757         old_size = skl_ddb_entry_size(&old->pipe[pipe]);
3758         new_size = skl_ddb_entry_size(&new->pipe[pipe]);
3759
3760         return old_size != new_size &&
3761                new->pipe[pipe].start >= old->pipe[pipe].start &&
3762                new->pipe[pipe].end <= old->pipe[pipe].end;
3763 }
3764
3765 static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
3766                                 struct skl_wm_values *new_values)
3767 {
3768         struct drm_device *dev = dev_priv->dev;
3769         struct skl_ddb_allocation *cur_ddb, *new_ddb;
3770         bool reallocated[I915_MAX_PIPES] = {};
3771         struct intel_crtc *crtc;
3772         enum pipe pipe;
3773
3774         new_ddb = &new_values->ddb;
3775         cur_ddb = &dev_priv->wm.skl_hw.ddb;
3776
3777         /*
3778          * First pass: flush the pipes with the new allocation contained into
3779          * the old space.
3780          *
3781          * We'll wait for the vblank on those pipes to ensure we can safely
3782          * re-allocate the freed space without this pipe fetching from it.
3783          */
3784         for_each_intel_crtc(dev, crtc) {
3785                 if (!crtc->active)
3786                         continue;
3787
3788                 pipe = crtc->pipe;
3789
3790                 if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe))
3791                         continue;
3792
3793                 skl_wm_flush_pipe(dev_priv, pipe, 1);
3794                 intel_wait_for_vblank(dev, pipe);
3795
3796                 reallocated[pipe] = true;
3797         }
3798
3799
3800         /*
3801          * Second pass: flush the pipes that are having their allocation
3802          * reduced, but overlapping with a previous allocation.
3803          *
3804          * Here as well we need to wait for the vblank to make sure the freed
3805          * space is not used anymore.
3806          */
3807         for_each_intel_crtc(dev, crtc) {
3808                 if (!crtc->active)
3809                         continue;
3810
3811                 pipe = crtc->pipe;
3812
3813                 if (reallocated[pipe])
3814                         continue;
3815
3816                 if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) <
3817                     skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {
3818                         skl_wm_flush_pipe(dev_priv, pipe, 2);
3819                         intel_wait_for_vblank(dev, pipe);
3820                         reallocated[pipe] = true;
3821                 }
3822         }
3823
3824         /*
3825          * Third pass: flush the pipes that got more space allocated.
3826          *
3827          * We don't need to actively wait for the update here, next vblank
3828          * will just get more DDB space with the correct WM values.
3829          */
3830         for_each_intel_crtc(dev, crtc) {
3831                 if (!crtc->active)
3832                         continue;
3833
3834                 pipe = crtc->pipe;
3835
3836                 /*
3837                  * At this point, only the pipes more space than before are
3838                  * left to re-allocate.
3839                  */
3840                 if (reallocated[pipe])
3841                         continue;
3842
3843                 skl_wm_flush_pipe(dev_priv, pipe, 3);
3844         }
3845 }
3846
3847 static int skl_update_pipe_wm(struct drm_crtc_state *cstate,
3848                               struct skl_ddb_allocation *ddb, /* out */
3849                               struct skl_pipe_wm *pipe_wm, /* out */
3850                               bool *changed /* out */)
3851 {
3852         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->crtc);
3853         struct intel_crtc_state *intel_cstate = to_intel_crtc_state(cstate);
3854         int ret;
3855
3856         ret = skl_build_pipe_wm(intel_cstate, ddb, pipe_wm);
3857         if (ret)
3858                 return ret;
3859
3860         if (!memcmp(&intel_crtc->wm.active.skl, pipe_wm, sizeof(*pipe_wm)))
3861                 *changed = false;
3862         else
3863                 *changed = true;
3864
3865         return 0;
3866 }
3867
3868 static int
3869 skl_compute_ddb(struct drm_atomic_state *state)
3870 {
3871         struct drm_device *dev = state->dev;
3872         struct drm_i915_private *dev_priv = to_i915(dev);
3873         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3874         struct intel_crtc *intel_crtc;
3875         struct skl_ddb_allocation *ddb = &intel_state->wm_results.ddb;
3876         unsigned realloc_pipes = dev_priv->active_crtcs;
3877         int ret;
3878
3879         /*
3880          * If this is our first atomic update following hardware readout,
3881          * we can't trust the DDB that the BIOS programmed for us.  Let's
3882          * pretend that all pipes switched active status so that we'll
3883          * ensure a full DDB recompute.
3884          */
3885         if (dev_priv->wm.distrust_bios_wm)
3886                 intel_state->active_pipe_changes = ~0;
3887
3888         /*
3889          * If the modeset changes which CRTC's are active, we need to
3890          * recompute the DDB allocation for *all* active pipes, even
3891          * those that weren't otherwise being modified in any way by this
3892          * atomic commit.  Due to the shrinking of the per-pipe allocations
3893          * when new active CRTC's are added, it's possible for a pipe that
3894          * we were already using and aren't changing at all here to suddenly
3895          * become invalid if its DDB needs exceeds its new allocation.
3896          *
3897          * Note that if we wind up doing a full DDB recompute, we can't let
3898          * any other display updates race with this transaction, so we need
3899          * to grab the lock on *all* CRTC's.
3900          */
3901         if (intel_state->active_pipe_changes) {
3902                 realloc_pipes = ~0;
3903                 intel_state->wm_results.dirty_pipes = ~0;
3904         }
3905
3906         for_each_intel_crtc_mask(dev, intel_crtc, realloc_pipes) {
3907                 struct intel_crtc_state *cstate;
3908
3909                 cstate = intel_atomic_get_crtc_state(state, intel_crtc);
3910                 if (IS_ERR(cstate))
3911                         return PTR_ERR(cstate);
3912
3913                 ret = skl_allocate_pipe_ddb(cstate, ddb);
3914                 if (ret)
3915                         return ret;
3916         }
3917
3918         return 0;
3919 }
3920
3921 static int
3922 skl_compute_wm(struct drm_atomic_state *state)
3923 {
3924         struct drm_crtc *crtc;
3925         struct drm_crtc_state *cstate;
3926         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3927         struct skl_wm_values *results = &intel_state->wm_results;
3928         struct skl_pipe_wm *pipe_wm;
3929         bool changed = false;
3930         int ret, i;
3931
3932         /*
3933          * If this transaction isn't actually touching any CRTC's, don't
3934          * bother with watermark calculation.  Note that if we pass this
3935          * test, we're guaranteed to hold at least one CRTC state mutex,
3936          * which means we can safely use values like dev_priv->active_crtcs
3937          * since any racing commits that want to update them would need to
3938          * hold _all_ CRTC state mutexes.
3939          */
3940         for_each_crtc_in_state(state, crtc, cstate, i)
3941                 changed = true;
3942         if (!changed)
3943                 return 0;
3944
3945         /* Clear all dirty flags */
3946         results->dirty_pipes = 0;
3947
3948         ret = skl_compute_ddb(state);
3949         if (ret)
3950                 return ret;
3951
3952         /*
3953          * Calculate WM's for all pipes that are part of this transaction.
3954          * Note that the DDB allocation above may have added more CRTC's that
3955          * weren't otherwise being modified (and set bits in dirty_pipes) if
3956          * pipe allocations had to change.
3957          *
3958          * FIXME:  Now that we're doing this in the atomic check phase, we
3959          * should allow skl_update_pipe_wm() to return failure in cases where
3960          * no suitable watermark values can be found.
3961          */
3962         for_each_crtc_in_state(state, crtc, cstate, i) {
3963                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3964                 struct intel_crtc_state *intel_cstate =
3965                         to_intel_crtc_state(cstate);
3966
3967                 pipe_wm = &intel_cstate->wm.skl.optimal;
3968                 ret = skl_update_pipe_wm(cstate, &results->ddb, pipe_wm,
3969                                          &changed);
3970                 if (ret)
3971                         return ret;
3972
3973                 if (changed)
3974                         results->dirty_pipes |= drm_crtc_mask(crtc);
3975
3976                 if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0)
3977                         /* This pipe's WM's did not change */
3978                         continue;
3979
3980                 intel_cstate->update_wm_pre = true;
3981                 skl_compute_wm_results(crtc->dev, pipe_wm, results, intel_crtc);
3982         }
3983
3984         return 0;
3985 }
3986
3987 static void skl_update_wm(struct drm_crtc *crtc)
3988 {
3989         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3990         struct drm_device *dev = crtc->dev;
3991         struct drm_i915_private *dev_priv = dev->dev_private;
3992         struct skl_wm_values *results = &dev_priv->wm.skl_results;
3993         struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3994         struct skl_pipe_wm *pipe_wm = &cstate->wm.skl.optimal;
3995
3996         if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0)
3997                 return;
3998
3999         intel_crtc->wm.active.skl = *pipe_wm;
4000
4001         mutex_lock(&dev_priv->wm.wm_mutex);
4002
4003         skl_write_wm_values(dev_priv, results);
4004         skl_flush_wm_values(dev_priv, results);
4005
4006         /* store the new configuration */
4007         dev_priv->wm.skl_hw = *results;
4008
4009         mutex_unlock(&dev_priv->wm.wm_mutex);
4010 }
4011
4012 static void ilk_compute_wm_config(struct drm_device *dev,
4013                                   struct intel_wm_config *config)
4014 {
4015         struct intel_crtc *crtc;
4016
4017         /* Compute the currently _active_ config */
4018         for_each_intel_crtc(dev, crtc) {
4019                 const struct intel_pipe_wm *wm = &crtc->wm.active.ilk;
4020
4021                 if (!wm->pipe_enabled)
4022                         continue;
4023
4024                 config->sprites_enabled |= wm->sprites_enabled;
4025                 config->sprites_scaled |= wm->sprites_scaled;
4026                 config->num_pipes_active++;
4027         }
4028 }
4029
4030 static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
4031 {
4032         struct drm_device *dev = dev_priv->dev;
4033         struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
4034         struct ilk_wm_maximums max;
4035         struct intel_wm_config config = {};
4036         struct ilk_wm_values results = {};
4037         enum intel_ddb_partitioning partitioning;
4038
4039         ilk_compute_wm_config(dev, &config);
4040
4041         ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
4042         ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
4043
4044         /* 5/6 split only in single pipe config on IVB+ */
4045         if (INTEL_INFO(dev)->gen >= 7 &&
4046             config.num_pipes_active == 1 && config.sprites_enabled) {
4047                 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
4048                 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
4049
4050                 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
4051         } else {
4052                 best_lp_wm = &lp_wm_1_2;
4053         }
4054
4055         partitioning = (best_lp_wm == &lp_wm_1_2) ?
4056                        INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
4057
4058         ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
4059
4060         ilk_write_wm_values(dev_priv, &results);
4061 }
4062
4063 static void ilk_initial_watermarks(struct intel_crtc_state *cstate)
4064 {
4065         struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
4066         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
4067
4068         mutex_lock(&dev_priv->wm.wm_mutex);
4069         intel_crtc->wm.active.ilk = cstate->wm.ilk.intermediate;
4070         ilk_program_watermarks(dev_priv);
4071         mutex_unlock(&dev_priv->wm.wm_mutex);
4072 }
4073
4074 static void ilk_optimize_watermarks(struct intel_crtc_state *cstate)
4075 {
4076         struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
4077         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
4078
4079         mutex_lock(&dev_priv->wm.wm_mutex);
4080         if (cstate->wm.need_postvbl_update) {
4081                 intel_crtc->wm.active.ilk = cstate->wm.ilk.optimal;
4082                 ilk_program_watermarks(dev_priv);
4083         }
4084         mutex_unlock(&dev_priv->wm.wm_mutex);
4085 }
4086
4087 static void skl_pipe_wm_active_state(uint32_t val,
4088                                      struct skl_pipe_wm *active,
4089                                      bool is_transwm,
4090                                      bool is_cursor,
4091                                      int i,
4092                                      int level)
4093 {
4094         bool is_enabled = (val & PLANE_WM_EN) != 0;
4095
4096         if (!is_transwm) {
4097                 if (!is_cursor) {
4098                         active->wm[level].plane_en[i] = is_enabled;
4099                         active->wm[level].plane_res_b[i] =
4100                                         val & PLANE_WM_BLOCKS_MASK;
4101                         active->wm[level].plane_res_l[i] =
4102                                         (val >> PLANE_WM_LINES_SHIFT) &
4103                                                 PLANE_WM_LINES_MASK;
4104                 } else {
4105                         active->wm[level].plane_en[PLANE_CURSOR] = is_enabled;
4106                         active->wm[level].plane_res_b[PLANE_CURSOR] =
4107                                         val & PLANE_WM_BLOCKS_MASK;
4108                         active->wm[level].plane_res_l[PLANE_CURSOR] =
4109                                         (val >> PLANE_WM_LINES_SHIFT) &
4110                                                 PLANE_WM_LINES_MASK;
4111                 }
4112         } else {
4113                 if (!is_cursor) {
4114                         active->trans_wm.plane_en[i] = is_enabled;
4115                         active->trans_wm.plane_res_b[i] =
4116                                         val & PLANE_WM_BLOCKS_MASK;
4117                         active->trans_wm.plane_res_l[i] =
4118                                         (val >> PLANE_WM_LINES_SHIFT) &
4119                                                 PLANE_WM_LINES_MASK;
4120                 } else {
4121                         active->trans_wm.plane_en[PLANE_CURSOR] = is_enabled;
4122                         active->trans_wm.plane_res_b[PLANE_CURSOR] =
4123                                         val & PLANE_WM_BLOCKS_MASK;
4124                         active->trans_wm.plane_res_l[PLANE_CURSOR] =
4125                                         (val >> PLANE_WM_LINES_SHIFT) &
4126                                                 PLANE_WM_LINES_MASK;
4127                 }
4128         }
4129 }
4130
4131 static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
4132 {
4133         struct drm_device *dev = crtc->dev;
4134         struct drm_i915_private *dev_priv = dev->dev_private;
4135         struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
4136         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4137         struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
4138         struct skl_pipe_wm *active = &cstate->wm.skl.optimal;
4139         enum pipe pipe = intel_crtc->pipe;
4140         int level, i, max_level;
4141         uint32_t temp;
4142
4143         max_level = ilk_wm_max_level(dev);
4144
4145         hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
4146
4147         for (level = 0; level <= max_level; level++) {
4148                 for (i = 0; i < intel_num_planes(intel_crtc); i++)
4149                         hw->plane[pipe][i][level] =
4150                                         I915_READ(PLANE_WM(pipe, i, level));
4151                 hw->plane[pipe][PLANE_CURSOR][level] = I915_READ(CUR_WM(pipe, level));
4152         }
4153
4154         for (i = 0; i < intel_num_planes(intel_crtc); i++)
4155                 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
4156         hw->plane_trans[pipe][PLANE_CURSOR] = I915_READ(CUR_WM_TRANS(pipe));
4157
4158         if (!intel_crtc->active)
4159                 return;
4160
4161         hw->dirty_pipes |= drm_crtc_mask(crtc);
4162
4163         active->linetime = hw->wm_linetime[pipe];
4164
4165         for (level = 0; level <= max_level; level++) {
4166                 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
4167                         temp = hw->plane[pipe][i][level];
4168                         skl_pipe_wm_active_state(temp, active, false,
4169                                                 false, i, level);
4170                 }
4171                 temp = hw->plane[pipe][PLANE_CURSOR][level];
4172                 skl_pipe_wm_active_state(temp, active, false, true, i, level);
4173         }
4174
4175         for (i = 0; i < intel_num_planes(intel_crtc); i++) {
4176                 temp = hw->plane_trans[pipe][i];
4177                 skl_pipe_wm_active_state(temp, active, true, false, i, 0);
4178         }
4179
4180         temp = hw->plane_trans[pipe][PLANE_CURSOR];
4181         skl_pipe_wm_active_state(temp, active, true, true, i, 0);
4182
4183         intel_crtc->wm.active.skl = *active;
4184 }
4185
4186 void skl_wm_get_hw_state(struct drm_device *dev)
4187 {
4188         struct drm_i915_private *dev_priv = dev->dev_private;
4189         struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
4190         struct drm_crtc *crtc;
4191
4192         skl_ddb_get_hw_state(dev_priv, ddb);
4193         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
4194                 skl_pipe_wm_get_hw_state(crtc);
4195
4196         if (dev_priv->active_crtcs) {
4197                 /* Fully recompute DDB on first atomic commit */
4198                 dev_priv->wm.distrust_bios_wm = true;
4199         } else {
4200                 /* Easy/common case; just sanitize DDB now if everything off */
4201                 memset(ddb, 0, sizeof(*ddb));
4202         }
4203 }
4204
4205 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
4206 {
4207         struct drm_device *dev = crtc->dev;
4208         struct drm_i915_private *dev_priv = dev->dev_private;
4209         struct ilk_wm_values *hw = &dev_priv->wm.hw;
4210         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4211         struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
4212         struct intel_pipe_wm *active = &cstate->wm.ilk.optimal;
4213         enum pipe pipe = intel_crtc->pipe;
4214         static const i915_reg_t wm0_pipe_reg[] = {
4215                 [PIPE_A] = WM0_PIPEA_ILK,
4216                 [PIPE_B] = WM0_PIPEB_ILK,
4217                 [PIPE_C] = WM0_PIPEC_IVB,
4218         };
4219
4220         hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
4221         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4222                 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
4223
4224         memset(active, 0, sizeof(*active));
4225
4226         active->pipe_enabled = intel_crtc->active;
4227
4228         if (active->pipe_enabled) {
4229                 u32 tmp = hw->wm_pipe[pipe];
4230
4231                 /*
4232                  * For active pipes LP0 watermark is marked as
4233                  * enabled, and LP1+ watermaks as disabled since
4234                  * we can't really reverse compute them in case
4235                  * multiple pipes are active.
4236                  */
4237                 active->wm[0].enable = true;
4238                 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
4239                 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
4240                 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
4241                 active->linetime = hw->wm_linetime[pipe];
4242         } else {
4243                 int level, max_level = ilk_wm_max_level(dev);
4244
4245                 /*
4246                  * For inactive pipes, all watermark levels
4247                  * should be marked as enabled but zeroed,
4248                  * which is what we'd compute them to.
4249                  */
4250                 for (level = 0; level <= max_level; level++)
4251                         active->wm[level].enable = true;
4252         }
4253
4254         intel_crtc->wm.active.ilk = *active;
4255 }
4256
4257 #define _FW_WM(value, plane) \
4258         (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
4259 #define _FW_WM_VLV(value, plane) \
4260         (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
4261
4262 static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
4263                                struct vlv_wm_values *wm)
4264 {
4265         enum pipe pipe;
4266         uint32_t tmp;
4267
4268         for_each_pipe(dev_priv, pipe) {
4269                 tmp = I915_READ(VLV_DDL(pipe));
4270
4271                 wm->ddl[pipe].primary =
4272                         (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4273                 wm->ddl[pipe].cursor =
4274                         (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4275                 wm->ddl[pipe].sprite[0] =
4276                         (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4277                 wm->ddl[pipe].sprite[1] =
4278                         (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4279         }
4280
4281         tmp = I915_READ(DSPFW1);
4282         wm->sr.plane = _FW_WM(tmp, SR);
4283         wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB);
4284         wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB);
4285         wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA);
4286
4287         tmp = I915_READ(DSPFW2);
4288         wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB);
4289         wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA);
4290         wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA);
4291
4292         tmp = I915_READ(DSPFW3);
4293         wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
4294
4295         if (IS_CHERRYVIEW(dev_priv)) {
4296                 tmp = I915_READ(DSPFW7_CHV);
4297                 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4298                 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4299
4300                 tmp = I915_READ(DSPFW8_CHV);
4301                 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF);
4302                 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE);
4303
4304                 tmp = I915_READ(DSPFW9_CHV);
4305                 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC);
4306                 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC);
4307
4308                 tmp = I915_READ(DSPHOWM);
4309                 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4310                 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
4311                 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
4312                 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8;
4313                 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4314                 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4315                 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4316                 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4317                 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4318                 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4319         } else {
4320                 tmp = I915_READ(DSPFW7);
4321                 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4322                 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4323
4324                 tmp = I915_READ(DSPHOWM);
4325                 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4326                 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4327                 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4328                 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4329                 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4330                 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4331                 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4332         }
4333 }
4334
4335 #undef _FW_WM
4336 #undef _FW_WM_VLV
4337
4338 void vlv_wm_get_hw_state(struct drm_device *dev)
4339 {
4340         struct drm_i915_private *dev_priv = to_i915(dev);
4341         struct vlv_wm_values *wm = &dev_priv->wm.vlv;
4342         struct intel_plane *plane;
4343         enum pipe pipe;
4344         u32 val;
4345
4346         vlv_read_wm_values(dev_priv, wm);
4347
4348         for_each_intel_plane(dev, plane) {
4349                 switch (plane->base.type) {
4350                         int sprite;
4351                 case DRM_PLANE_TYPE_CURSOR:
4352                         plane->wm.fifo_size = 63;
4353                         break;
4354                 case DRM_PLANE_TYPE_PRIMARY:
4355                         plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0);
4356                         break;
4357                 case DRM_PLANE_TYPE_OVERLAY:
4358                         sprite = plane->plane;
4359                         plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1);
4360                         break;
4361                 }
4362         }
4363
4364         wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4365         wm->level = VLV_WM_LEVEL_PM2;
4366
4367         if (IS_CHERRYVIEW(dev_priv)) {
4368                 mutex_lock(&dev_priv->rps.hw_lock);
4369
4370                 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4371                 if (val & DSP_MAXFIFO_PM5_ENABLE)
4372                         wm->level = VLV_WM_LEVEL_PM5;
4373
4374                 /*
4375                  * If DDR DVFS is disabled in the BIOS, Punit
4376                  * will never ack the request. So if that happens
4377                  * assume we don't have to enable/disable DDR DVFS
4378                  * dynamically. To test that just set the REQ_ACK
4379                  * bit to poke the Punit, but don't change the
4380                  * HIGH/LOW bits so that we don't actually change
4381                  * the current state.
4382                  */
4383                 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4384                 val |= FORCE_DDR_FREQ_REQ_ACK;
4385                 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
4386
4387                 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
4388                               FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
4389                         DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
4390                                       "assuming DDR DVFS is disabled\n");
4391                         dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
4392                 } else {
4393                         val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4394                         if ((val & FORCE_DDR_HIGH_FREQ) == 0)
4395                                 wm->level = VLV_WM_LEVEL_DDR_DVFS;
4396                 }
4397
4398                 mutex_unlock(&dev_priv->rps.hw_lock);
4399         }
4400
4401         for_each_pipe(dev_priv, pipe)
4402                 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4403                               pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor,
4404                               wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]);
4405
4406         DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4407                       wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
4408 }
4409
4410 void ilk_wm_get_hw_state(struct drm_device *dev)
4411 {
4412         struct drm_i915_private *dev_priv = dev->dev_private;
4413         struct ilk_wm_values *hw = &dev_priv->wm.hw;
4414         struct drm_crtc *crtc;
4415
4416         for_each_crtc(dev, crtc)
4417                 ilk_pipe_wm_get_hw_state(crtc);
4418
4419         hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
4420         hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
4421         hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
4422
4423         hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
4424         if (INTEL_INFO(dev)->gen >= 7) {
4425                 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
4426                 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
4427         }
4428
4429         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4430                 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
4431                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4432         else if (IS_IVYBRIDGE(dev))
4433                 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
4434                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4435
4436         hw->enable_fbc_wm =
4437                 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
4438 }
4439
4440 /**
4441  * intel_update_watermarks - update FIFO watermark values based on current modes
4442  *
4443  * Calculate watermark values for the various WM regs based on current mode
4444  * and plane configuration.
4445  *
4446  * There are several cases to deal with here:
4447  *   - normal (i.e. non-self-refresh)
4448  *   - self-refresh (SR) mode
4449  *   - lines are large relative to FIFO size (buffer can hold up to 2)
4450  *   - lines are small relative to FIFO size (buffer can hold more than 2
4451  *     lines), so need to account for TLB latency
4452  *
4453  *   The normal calculation is:
4454  *     watermark = dotclock * bytes per pixel * latency
4455  *   where latency is platform & configuration dependent (we assume pessimal
4456  *   values here).
4457  *
4458  *   The SR calculation is:
4459  *     watermark = (trunc(latency/line time)+1) * surface width *
4460  *       bytes per pixel
4461  *   where
4462  *     line time = htotal / dotclock
4463  *     surface width = hdisplay for normal plane and 64 for cursor
4464  *   and latency is assumed to be high, as above.
4465  *
4466  * The final value programmed to the register should always be rounded up,
4467  * and include an extra 2 entries to account for clock crossings.
4468  *
4469  * We don't use the sprite, so we can ignore that.  And on Crestline we have
4470  * to set the non-SR watermarks to 8.
4471  */
4472 void intel_update_watermarks(struct drm_crtc *crtc)
4473 {
4474         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
4475
4476         if (dev_priv->display.update_wm)
4477                 dev_priv->display.update_wm(crtc);
4478 }
4479
4480 /*
4481  * Lock protecting IPS related data structures
4482  */
4483 DEFINE_SPINLOCK(mchdev_lock);
4484
4485 /* Global for IPS driver to get at the current i915 device. Protected by
4486  * mchdev_lock. */
4487 static struct drm_i915_private *i915_mch_dev;
4488
4489 bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val)
4490 {
4491         u16 rgvswctl;
4492
4493         assert_spin_locked(&mchdev_lock);
4494
4495         rgvswctl = I915_READ16(MEMSWCTL);
4496         if (rgvswctl & MEMCTL_CMD_STS) {
4497                 DRM_DEBUG("gpu busy, RCS change rejected\n");
4498                 return false; /* still busy with another command */
4499         }
4500
4501         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4502                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4503         I915_WRITE16(MEMSWCTL, rgvswctl);
4504         POSTING_READ16(MEMSWCTL);
4505
4506         rgvswctl |= MEMCTL_CMD_STS;
4507         I915_WRITE16(MEMSWCTL, rgvswctl);
4508
4509         return true;
4510 }
4511
4512 static void ironlake_enable_drps(struct drm_i915_private *dev_priv)
4513 {
4514         u32 rgvmodectl;
4515         u8 fmax, fmin, fstart, vstart;
4516
4517         spin_lock_irq(&mchdev_lock);
4518
4519         rgvmodectl = I915_READ(MEMMODECTL);
4520
4521         /* Enable temp reporting */
4522         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4523         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4524
4525         /* 100ms RC evaluation intervals */
4526         I915_WRITE(RCUPEI, 100000);
4527         I915_WRITE(RCDNEI, 100000);
4528
4529         /* Set max/min thresholds to 90ms and 80ms respectively */
4530         I915_WRITE(RCBMAXAVG, 90000);
4531         I915_WRITE(RCBMINAVG, 80000);
4532
4533         I915_WRITE(MEMIHYST, 1);
4534
4535         /* Set up min, max, and cur for interrupt handling */
4536         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4537         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4538         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4539                 MEMMODE_FSTART_SHIFT;
4540
4541         vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
4542                 PXVFREQ_PX_SHIFT;
4543
4544         dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4545         dev_priv->ips.fstart = fstart;
4546
4547         dev_priv->ips.max_delay = fstart;
4548         dev_priv->ips.min_delay = fmin;
4549         dev_priv->ips.cur_delay = fstart;
4550
4551         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4552                          fmax, fmin, fstart);
4553
4554         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4555
4556         /*
4557          * Interrupts will be enabled in ironlake_irq_postinstall
4558          */
4559
4560         I915_WRITE(VIDSTART, vstart);
4561         POSTING_READ(VIDSTART);
4562
4563         rgvmodectl |= MEMMODE_SWMODE_EN;
4564         I915_WRITE(MEMMODECTL, rgvmodectl);
4565
4566         if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
4567                 DRM_ERROR("stuck trying to change perf mode\n");
4568         mdelay(1);
4569
4570         ironlake_set_drps(dev_priv, fstart);
4571
4572         dev_priv->ips.last_count1 = I915_READ(DMIEC) +
4573                 I915_READ(DDREC) + I915_READ(CSIEC);
4574         dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
4575         dev_priv->ips.last_count2 = I915_READ(GFXEC);
4576         dev_priv->ips.last_time2 = ktime_get_raw_ns();
4577
4578         spin_unlock_irq(&mchdev_lock);
4579 }
4580
4581 static void ironlake_disable_drps(struct drm_i915_private *dev_priv)
4582 {
4583         u16 rgvswctl;
4584
4585         spin_lock_irq(&mchdev_lock);
4586
4587         rgvswctl = I915_READ16(MEMSWCTL);
4588
4589         /* Ack interrupts, disable EFC interrupt */
4590         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4591         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4592         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4593         I915_WRITE(DEIIR, DE_PCU_EVENT);
4594         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4595
4596         /* Go back to the starting frequency */
4597         ironlake_set_drps(dev_priv, dev_priv->ips.fstart);
4598         mdelay(1);
4599         rgvswctl |= MEMCTL_CMD_STS;
4600         I915_WRITE(MEMSWCTL, rgvswctl);
4601         mdelay(1);
4602
4603         spin_unlock_irq(&mchdev_lock);
4604 }
4605
4606 /* There's a funny hw issue where the hw returns all 0 when reading from
4607  * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4608  * ourselves, instead of doing a rmw cycle (which might result in us clearing
4609  * all limits and the gpu stuck at whatever frequency it is at atm).
4610  */
4611 static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
4612 {
4613         u32 limits;
4614
4615         /* Only set the down limit when we've reached the lowest level to avoid
4616          * getting more interrupts, otherwise leave this clear. This prevents a
4617          * race in the hw when coming out of rc6: There's a tiny window where
4618          * the hw runs at the minimal clock before selecting the desired
4619          * frequency, if the down threshold expires in that window we will not
4620          * receive a down interrupt. */
4621         if (IS_GEN9(dev_priv)) {
4622                 limits = (dev_priv->rps.max_freq_softlimit) << 23;
4623                 if (val <= dev_priv->rps.min_freq_softlimit)
4624                         limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4625         } else {
4626                 limits = dev_priv->rps.max_freq_softlimit << 24;
4627                 if (val <= dev_priv->rps.min_freq_softlimit)
4628                         limits |= dev_priv->rps.min_freq_softlimit << 16;
4629         }
4630
4631         return limits;
4632 }
4633
4634 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4635 {
4636         int new_power;
4637         u32 threshold_up = 0, threshold_down = 0; /* in % */
4638         u32 ei_up = 0, ei_down = 0;
4639
4640         new_power = dev_priv->rps.power;
4641         switch (dev_priv->rps.power) {
4642         case LOW_POWER:
4643                 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
4644                         new_power = BETWEEN;
4645                 break;
4646
4647         case BETWEEN:
4648                 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
4649                         new_power = LOW_POWER;
4650                 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
4651                         new_power = HIGH_POWER;
4652                 break;
4653
4654         case HIGH_POWER:
4655                 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
4656                         new_power = BETWEEN;
4657                 break;
4658         }
4659         /* Max/min bins are special */
4660         if (val <= dev_priv->rps.min_freq_softlimit)
4661                 new_power = LOW_POWER;
4662         if (val >= dev_priv->rps.max_freq_softlimit)
4663                 new_power = HIGH_POWER;
4664         if (new_power == dev_priv->rps.power)
4665                 return;
4666
4667         /* Note the units here are not exactly 1us, but 1280ns. */
4668         switch (new_power) {
4669         case LOW_POWER:
4670                 /* Upclock if more than 95% busy over 16ms */
4671                 ei_up = 16000;
4672                 threshold_up = 95;
4673
4674                 /* Downclock if less than 85% busy over 32ms */
4675                 ei_down = 32000;
4676                 threshold_down = 85;
4677                 break;
4678
4679         case BETWEEN:
4680                 /* Upclock if more than 90% busy over 13ms */
4681                 ei_up = 13000;
4682                 threshold_up = 90;
4683
4684                 /* Downclock if less than 75% busy over 32ms */
4685                 ei_down = 32000;
4686                 threshold_down = 75;
4687                 break;
4688
4689         case HIGH_POWER:
4690                 /* Upclock if more than 85% busy over 10ms */
4691                 ei_up = 10000;
4692                 threshold_up = 85;
4693
4694                 /* Downclock if less than 60% busy over 32ms */
4695                 ei_down = 32000;
4696                 threshold_down = 60;
4697                 break;
4698         }
4699
4700         I915_WRITE(GEN6_RP_UP_EI,
4701                 GT_INTERVAL_FROM_US(dev_priv, ei_up));
4702         I915_WRITE(GEN6_RP_UP_THRESHOLD,
4703                 GT_INTERVAL_FROM_US(dev_priv, (ei_up * threshold_up / 100)));
4704
4705         I915_WRITE(GEN6_RP_DOWN_EI,
4706                 GT_INTERVAL_FROM_US(dev_priv, ei_down));
4707         I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
4708                 GT_INTERVAL_FROM_US(dev_priv, (ei_down * threshold_down / 100)));
4709
4710          I915_WRITE(GEN6_RP_CONTROL,
4711                     GEN6_RP_MEDIA_TURBO |
4712                     GEN6_RP_MEDIA_HW_NORMAL_MODE |
4713                     GEN6_RP_MEDIA_IS_GFX |
4714                     GEN6_RP_ENABLE |
4715                     GEN6_RP_UP_BUSY_AVG |
4716                     GEN6_RP_DOWN_IDLE_AVG);
4717
4718         dev_priv->rps.power = new_power;
4719         dev_priv->rps.up_threshold = threshold_up;
4720         dev_priv->rps.down_threshold = threshold_down;
4721         dev_priv->rps.last_adj = 0;
4722 }
4723
4724 static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4725 {
4726         u32 mask = 0;
4727
4728         if (val > dev_priv->rps.min_freq_softlimit)
4729                 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
4730         if (val < dev_priv->rps.max_freq_softlimit)
4731                 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
4732
4733         mask &= dev_priv->pm_rps_events;
4734
4735         return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
4736 }
4737
4738 /* gen6_set_rps is called to update the frequency request, but should also be
4739  * called when the range (min_delay and max_delay) is modified so that we can
4740  * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
4741 static void gen6_set_rps(struct drm_i915_private *dev_priv, u8 val)
4742 {
4743         /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
4744         if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
4745                 return;
4746
4747         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4748         WARN_ON(val > dev_priv->rps.max_freq);
4749         WARN_ON(val < dev_priv->rps.min_freq);
4750
4751         /* min/max delay may still have been modified so be sure to
4752          * write the limits value.
4753          */
4754         if (val != dev_priv->rps.cur_freq) {
4755                 gen6_set_rps_thresholds(dev_priv, val);
4756
4757                 if (IS_GEN9(dev_priv))
4758                         I915_WRITE(GEN6_RPNSWREQ,
4759                                    GEN9_FREQUENCY(val));
4760                 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
4761                         I915_WRITE(GEN6_RPNSWREQ,
4762                                    HSW_FREQUENCY(val));
4763                 else
4764                         I915_WRITE(GEN6_RPNSWREQ,
4765                                    GEN6_FREQUENCY(val) |
4766                                    GEN6_OFFSET(0) |
4767                                    GEN6_AGGRESSIVE_TURBO);
4768         }
4769
4770         /* Make sure we continue to get interrupts
4771          * until we hit the minimum or maximum frequencies.
4772          */
4773         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
4774         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4775
4776         POSTING_READ(GEN6_RPNSWREQ);
4777
4778         dev_priv->rps.cur_freq = val;
4779         trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4780 }
4781
4782 static void valleyview_set_rps(struct drm_i915_private *dev_priv, u8 val)
4783 {
4784         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4785         WARN_ON(val > dev_priv->rps.max_freq);
4786         WARN_ON(val < dev_priv->rps.min_freq);
4787
4788         if (WARN_ONCE(IS_CHERRYVIEW(dev_priv) && (val & 1),
4789                       "Odd GPU freq value\n"))
4790                 val &= ~1;
4791
4792         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4793
4794         if (val != dev_priv->rps.cur_freq) {
4795                 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
4796                 if (!IS_CHERRYVIEW(dev_priv))
4797                         gen6_set_rps_thresholds(dev_priv, val);
4798         }
4799
4800         dev_priv->rps.cur_freq = val;
4801         trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4802 }
4803
4804 /* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
4805  *
4806  * * If Gfx is Idle, then
4807  * 1. Forcewake Media well.
4808  * 2. Request idle freq.
4809  * 3. Release Forcewake of Media well.
4810 */
4811 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
4812 {
4813         u32 val = dev_priv->rps.idle_freq;
4814
4815         if (dev_priv->rps.cur_freq <= val)
4816                 return;
4817
4818         /* Wake up the media well, as that takes a lot less
4819          * power than the Render well. */
4820         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
4821         valleyview_set_rps(dev_priv, val);
4822         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
4823 }
4824
4825 void gen6_rps_busy(struct drm_i915_private *dev_priv)
4826 {
4827         mutex_lock(&dev_priv->rps.hw_lock);
4828         if (dev_priv->rps.enabled) {
4829                 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
4830                         gen6_rps_reset_ei(dev_priv);
4831                 I915_WRITE(GEN6_PMINTRMSK,
4832                            gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
4833         }
4834         mutex_unlock(&dev_priv->rps.hw_lock);
4835 }
4836
4837 void gen6_rps_idle(struct drm_i915_private *dev_priv)
4838 {
4839         mutex_lock(&dev_priv->rps.hw_lock);
4840         if (dev_priv->rps.enabled) {
4841                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4842                         vlv_set_rps_idle(dev_priv);
4843                 else
4844                         gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
4845                 dev_priv->rps.last_adj = 0;
4846                 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
4847         }
4848         mutex_unlock(&dev_priv->rps.hw_lock);
4849
4850         spin_lock(&dev_priv->rps.client_lock);
4851         while (!list_empty(&dev_priv->rps.clients))
4852                 list_del_init(dev_priv->rps.clients.next);
4853         spin_unlock(&dev_priv->rps.client_lock);
4854 }
4855
4856 void gen6_rps_boost(struct drm_i915_private *dev_priv,
4857                     struct intel_rps_client *rps,
4858                     unsigned long submitted)
4859 {
4860         /* This is intentionally racy! We peek at the state here, then
4861          * validate inside the RPS worker.
4862          */
4863         if (!(dev_priv->mm.busy &&
4864               dev_priv->rps.enabled &&
4865               dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit))
4866                 return;
4867
4868         /* Force a RPS boost (and don't count it against the client) if
4869          * the GPU is severely congested.
4870          */
4871         if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
4872                 rps = NULL;
4873
4874         spin_lock(&dev_priv->rps.client_lock);
4875         if (rps == NULL || list_empty(&rps->link)) {
4876                 spin_lock_irq(&dev_priv->irq_lock);
4877                 if (dev_priv->rps.interrupts_enabled) {
4878                         dev_priv->rps.client_boost = true;
4879                         queue_work(dev_priv->wq, &dev_priv->rps.work);
4880                 }
4881                 spin_unlock_irq(&dev_priv->irq_lock);
4882
4883                 if (rps != NULL) {
4884                         list_add(&rps->link, &dev_priv->rps.clients);
4885                         rps->boosts++;
4886                 } else
4887                         dev_priv->rps.boosts++;
4888         }
4889         spin_unlock(&dev_priv->rps.client_lock);
4890 }
4891
4892 void intel_set_rps(struct drm_i915_private *dev_priv, u8 val)
4893 {
4894         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4895                 valleyview_set_rps(dev_priv, val);
4896         else
4897                 gen6_set_rps(dev_priv, val);
4898 }
4899
4900 static void gen9_disable_rc6(struct drm_i915_private *dev_priv)
4901 {
4902         I915_WRITE(GEN6_RC_CONTROL, 0);
4903         I915_WRITE(GEN9_PG_ENABLE, 0);
4904 }
4905
4906 static void gen9_disable_rps(struct drm_i915_private *dev_priv)
4907 {
4908         I915_WRITE(GEN6_RP_CONTROL, 0);
4909 }
4910
4911 static void gen6_disable_rps(struct drm_i915_private *dev_priv)
4912 {
4913         I915_WRITE(GEN6_RC_CONTROL, 0);
4914         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
4915         I915_WRITE(GEN6_RP_CONTROL, 0);
4916 }
4917
4918 static void cherryview_disable_rps(struct drm_i915_private *dev_priv)
4919 {
4920         I915_WRITE(GEN6_RC_CONTROL, 0);
4921 }
4922
4923 static void valleyview_disable_rps(struct drm_i915_private *dev_priv)
4924 {
4925         /* we're doing forcewake before Disabling RC6,
4926          * This what the BIOS expects when going into suspend */
4927         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4928
4929         I915_WRITE(GEN6_RC_CONTROL, 0);
4930
4931         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4932 }
4933
4934 static void intel_print_rc6_info(struct drm_i915_private *dev_priv, u32 mode)
4935 {
4936         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
4937                 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
4938                         mode = GEN6_RC_CTL_RC6_ENABLE;
4939                 else
4940                         mode = 0;
4941         }
4942         if (HAS_RC6p(dev_priv))
4943                 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n",
4944                               onoff(mode & GEN6_RC_CTL_RC6_ENABLE),
4945                               onoff(mode & GEN6_RC_CTL_RC6p_ENABLE),
4946                               onoff(mode & GEN6_RC_CTL_RC6pp_ENABLE));
4947
4948         else
4949                 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n",
4950                               onoff(mode & GEN6_RC_CTL_RC6_ENABLE));
4951 }
4952
4953 static bool bxt_check_bios_rc6_setup(struct drm_i915_private *dev_priv)
4954 {
4955         struct i915_ggtt *ggtt = &dev_priv->ggtt;
4956         bool enable_rc6 = true;
4957         unsigned long rc6_ctx_base;
4958
4959         if (!(I915_READ(RC6_LOCATION) & RC6_CTX_IN_DRAM)) {
4960                 DRM_DEBUG_KMS("RC6 Base location not set properly.\n");
4961                 enable_rc6 = false;
4962         }
4963
4964         /*
4965          * The exact context size is not known for BXT, so assume a page size
4966          * for this check.
4967          */
4968         rc6_ctx_base = I915_READ(RC6_CTX_BASE) & RC6_CTX_BASE_MASK;
4969         if (!((rc6_ctx_base >= ggtt->stolen_reserved_base) &&
4970               (rc6_ctx_base + PAGE_SIZE <= ggtt->stolen_reserved_base +
4971                                         ggtt->stolen_reserved_size))) {
4972                 DRM_DEBUG_KMS("RC6 Base address not as expected.\n");
4973                 enable_rc6 = false;
4974         }
4975
4976         if (!(((I915_READ(PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1) &&
4977               ((I915_READ(PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1) &&
4978               ((I915_READ(PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1) &&
4979               ((I915_READ(PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1))) {
4980                 DRM_DEBUG_KMS("Engine Idle wait time not set properly.\n");
4981                 enable_rc6 = false;
4982         }
4983
4984         if (!(I915_READ(GEN6_RC_CONTROL) & (GEN6_RC_CTL_RC6_ENABLE |
4985                                             GEN6_RC_CTL_HW_ENABLE)) &&
4986             ((I915_READ(GEN6_RC_CONTROL) & GEN6_RC_CTL_HW_ENABLE) ||
4987              !(I915_READ(GEN6_RC_STATE) & RC6_STATE))) {
4988                 DRM_DEBUG_KMS("HW/SW RC6 is not enabled by BIOS.\n");
4989                 enable_rc6 = false;
4990         }
4991
4992         return enable_rc6;
4993 }
4994
4995 int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6)
4996 {
4997         /* No RC6 before Ironlake and code is gone for ilk. */
4998         if (INTEL_INFO(dev_priv)->gen < 6)
4999                 return 0;
5000
5001         if (!enable_rc6)
5002                 return 0;
5003
5004         if (IS_BROXTON(dev_priv) && !bxt_check_bios_rc6_setup(dev_priv)) {
5005                 DRM_INFO("RC6 disabled by BIOS\n");
5006                 return 0;
5007         }
5008
5009         /* Respect the kernel parameter if it is set */
5010         if (enable_rc6 >= 0) {
5011                 int mask;
5012
5013                 if (HAS_RC6p(dev_priv))
5014                         mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
5015                                INTEL_RC6pp_ENABLE;
5016                 else
5017                         mask = INTEL_RC6_ENABLE;
5018
5019                 if ((enable_rc6 & mask) != enable_rc6)
5020                         DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
5021                                       enable_rc6 & mask, enable_rc6, mask);
5022
5023                 return enable_rc6 & mask;
5024         }
5025
5026         if (IS_IVYBRIDGE(dev_priv))
5027                 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
5028
5029         return INTEL_RC6_ENABLE;
5030 }
5031
5032 static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
5033 {
5034         uint32_t rp_state_cap;
5035         u32 ddcc_status = 0;
5036         int ret;
5037
5038         /* All of these values are in units of 50MHz */
5039         dev_priv->rps.cur_freq          = 0;
5040         /* static values from HW: RP0 > RP1 > RPn (min_freq) */
5041         if (IS_BROXTON(dev_priv)) {
5042                 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
5043                 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
5044                 dev_priv->rps.rp1_freq = (rp_state_cap >>  8) & 0xff;
5045                 dev_priv->rps.min_freq = (rp_state_cap >>  0) & 0xff;
5046         } else {
5047                 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
5048                 dev_priv->rps.rp0_freq = (rp_state_cap >>  0) & 0xff;
5049                 dev_priv->rps.rp1_freq = (rp_state_cap >>  8) & 0xff;
5050                 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
5051         }
5052
5053         /* hw_max = RP0 until we check for overclocking */
5054         dev_priv->rps.max_freq          = dev_priv->rps.rp0_freq;
5055
5056         dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
5057         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
5058             IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5059                 ret = sandybridge_pcode_read(dev_priv,
5060                                         HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
5061                                         &ddcc_status);
5062                 if (0 == ret)
5063                         dev_priv->rps.efficient_freq =
5064                                 clamp_t(u8,
5065                                         ((ddcc_status >> 8) & 0xff),
5066                                         dev_priv->rps.min_freq,
5067                                         dev_priv->rps.max_freq);
5068         }
5069
5070         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5071                 /* Store the frequency values in 16.66 MHZ units, which is
5072                    the natural hardware unit for SKL */
5073                 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
5074                 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
5075                 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
5076                 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
5077                 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
5078         }
5079
5080         dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5081
5082         /* Preserve min/max settings in case of re-init */
5083         if (dev_priv->rps.max_freq_softlimit == 0)
5084                 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5085
5086         if (dev_priv->rps.min_freq_softlimit == 0) {
5087                 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5088                         dev_priv->rps.min_freq_softlimit =
5089                                 max_t(int, dev_priv->rps.efficient_freq,
5090                                       intel_freq_opcode(dev_priv, 450));
5091                 else
5092                         dev_priv->rps.min_freq_softlimit =
5093                                 dev_priv->rps.min_freq;
5094         }
5095 }
5096
5097 /* See the Gen9_GT_PM_Programming_Guide doc for the below */
5098 static void gen9_enable_rps(struct drm_i915_private *dev_priv)
5099 {
5100         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5101
5102         gen6_init_rps_frequencies(dev_priv);
5103
5104         /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
5105         if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
5106                 /*
5107                  * BIOS could leave the Hw Turbo enabled, so need to explicitly
5108                  * clear out the Control register just to avoid inconsitency
5109                  * with debugfs interface, which will show  Turbo as enabled
5110                  * only and that is not expected by the User after adding the
5111                  * WaGsvDisableTurbo. Apart from this there is no problem even
5112                  * if the Turbo is left enabled in the Control register, as the
5113                  * Up/Down interrupts would remain masked.
5114                  */
5115                 gen9_disable_rps(dev_priv);
5116                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5117                 return;
5118         }
5119
5120         /* Program defaults and thresholds for RPS*/
5121         I915_WRITE(GEN6_RC_VIDEO_FREQ,
5122                 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
5123
5124         /* 1 second timeout*/
5125         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
5126                 GT_INTERVAL_FROM_US(dev_priv, 1000000));
5127
5128         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
5129
5130         /* Leaning on the below call to gen6_set_rps to program/setup the
5131          * Up/Down EI & threshold registers, as well as the RP_CONTROL,
5132          * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
5133         dev_priv->rps.power = HIGH_POWER; /* force a reset */
5134         gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
5135
5136         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5137 }
5138
5139 static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
5140 {
5141         struct intel_engine_cs *engine;
5142         uint32_t rc6_mask = 0;
5143
5144         /* 1a: Software RC state - RC0 */
5145         I915_WRITE(GEN6_RC_STATE, 0);
5146
5147         /* 1b: Get forcewake during program sequence. Although the driver
5148          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5149         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5150
5151         /* 2a: Disable RC states. */
5152         I915_WRITE(GEN6_RC_CONTROL, 0);
5153
5154         /* 2b: Program RC6 thresholds.*/
5155
5156         /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
5157         if (IS_SKYLAKE(dev_priv))
5158                 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
5159         else
5160                 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
5161         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5162         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5163         for_each_engine(engine, dev_priv)
5164                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5165
5166         if (HAS_GUC(dev_priv))
5167                 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
5168
5169         I915_WRITE(GEN6_RC_SLEEP, 0);
5170
5171         /* 2c: Program Coarse Power Gating Policies. */
5172         I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
5173         I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
5174
5175         /* 3a: Enable RC6 */
5176         if (intel_enable_rc6() & INTEL_RC6_ENABLE)
5177                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
5178         DRM_INFO("RC6 %s\n", onoff(rc6_mask & GEN6_RC_CTL_RC6_ENABLE));
5179         /* WaRsUseTimeoutMode */
5180         if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_D0) ||
5181             IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
5182                 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
5183                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5184                            GEN7_RC_CTL_TO_MODE |
5185                            rc6_mask);
5186         } else {
5187                 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
5188                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5189                            GEN6_RC_CTL_EI_MODE(1) |
5190                            rc6_mask);
5191         }
5192
5193         /*
5194          * 3b: Enable Coarse Power Gating only when RC6 is enabled.
5195          * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
5196          */
5197         if (NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
5198                 I915_WRITE(GEN9_PG_ENABLE, 0);
5199         else
5200                 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
5201                                 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
5202
5203         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5204 }
5205
5206 static void gen8_enable_rps(struct drm_i915_private *dev_priv)
5207 {
5208         struct intel_engine_cs *engine;
5209         uint32_t rc6_mask = 0;
5210
5211         /* 1a: Software RC state - RC0 */
5212         I915_WRITE(GEN6_RC_STATE, 0);
5213
5214         /* 1c & 1d: Get forcewake during program sequence. Although the driver
5215          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5216         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5217
5218         /* 2a: Disable RC states. */
5219         I915_WRITE(GEN6_RC_CONTROL, 0);
5220
5221         /* Initialize rps frequencies */
5222         gen6_init_rps_frequencies(dev_priv);
5223
5224         /* 2b: Program RC6 thresholds.*/
5225         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5226         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5227         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5228         for_each_engine(engine, dev_priv)
5229                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5230         I915_WRITE(GEN6_RC_SLEEP, 0);
5231         if (IS_BROADWELL(dev_priv))
5232                 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
5233         else
5234                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
5235
5236         /* 3: Enable RC6 */
5237         if (intel_enable_rc6() & INTEL_RC6_ENABLE)
5238                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
5239         intel_print_rc6_info(dev_priv, rc6_mask);
5240         if (IS_BROADWELL(dev_priv))
5241                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5242                                 GEN7_RC_CTL_TO_MODE |
5243                                 rc6_mask);
5244         else
5245                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5246                                 GEN6_RC_CTL_EI_MODE(1) |
5247                                 rc6_mask);
5248
5249         /* 4 Program defaults and thresholds for RPS*/
5250         I915_WRITE(GEN6_RPNSWREQ,
5251                    HSW_FREQUENCY(dev_priv->rps.rp1_freq));
5252         I915_WRITE(GEN6_RC_VIDEO_FREQ,
5253                    HSW_FREQUENCY(dev_priv->rps.rp1_freq));
5254         /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
5255         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
5256
5257         /* Docs recommend 900MHz, and 300 MHz respectively */
5258         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
5259                    dev_priv->rps.max_freq_softlimit << 24 |
5260                    dev_priv->rps.min_freq_softlimit << 16);
5261
5262         I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
5263         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
5264         I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
5265         I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
5266
5267         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5268
5269         /* 5: Enable RPS */
5270         I915_WRITE(GEN6_RP_CONTROL,
5271                    GEN6_RP_MEDIA_TURBO |
5272                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
5273                    GEN6_RP_MEDIA_IS_GFX |
5274                    GEN6_RP_ENABLE |
5275                    GEN6_RP_UP_BUSY_AVG |
5276                    GEN6_RP_DOWN_IDLE_AVG);
5277
5278         /* 6: Ring frequency + overclocking (our driver does this later */
5279
5280         dev_priv->rps.power = HIGH_POWER; /* force a reset */
5281         gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
5282
5283         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5284 }
5285
5286 static void gen6_enable_rps(struct drm_i915_private *dev_priv)
5287 {
5288         struct intel_engine_cs *engine;
5289         u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
5290         u32 gtfifodbg;
5291         int rc6_mode;
5292         int ret;
5293
5294         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5295
5296         /* Here begins a magic sequence of register writes to enable
5297          * auto-downclocking.
5298          *
5299          * Perhaps there might be some value in exposing these to
5300          * userspace...
5301          */
5302         I915_WRITE(GEN6_RC_STATE, 0);
5303
5304         /* Clear the DBG now so we don't confuse earlier errors */
5305         gtfifodbg = I915_READ(GTFIFODBG);
5306         if (gtfifodbg) {
5307                 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
5308                 I915_WRITE(GTFIFODBG, gtfifodbg);
5309         }
5310
5311         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5312
5313         /* Initialize rps frequencies */
5314         gen6_init_rps_frequencies(dev_priv);
5315
5316         /* disable the counters and set deterministic thresholds */
5317         I915_WRITE(GEN6_RC_CONTROL, 0);
5318
5319         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
5320         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
5321         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
5322         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5323         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5324
5325         for_each_engine(engine, dev_priv)
5326                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5327
5328         I915_WRITE(GEN6_RC_SLEEP, 0);
5329         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
5330         if (IS_IVYBRIDGE(dev_priv))
5331                 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
5332         else
5333                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
5334         I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
5335         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
5336
5337         /* Check if we are enabling RC6 */
5338         rc6_mode = intel_enable_rc6();
5339         if (rc6_mode & INTEL_RC6_ENABLE)
5340                 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
5341
5342         /* We don't use those on Haswell */
5343         if (!IS_HASWELL(dev_priv)) {
5344                 if (rc6_mode & INTEL_RC6p_ENABLE)
5345                         rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
5346
5347                 if (rc6_mode & INTEL_RC6pp_ENABLE)
5348                         rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
5349         }
5350
5351         intel_print_rc6_info(dev_priv, rc6_mask);
5352
5353         I915_WRITE(GEN6_RC_CONTROL,
5354                    rc6_mask |
5355                    GEN6_RC_CTL_EI_MODE(1) |
5356                    GEN6_RC_CTL_HW_ENABLE);
5357
5358         /* Power down if completely idle for over 50ms */
5359         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
5360         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5361
5362         ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
5363         if (ret)
5364                 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
5365
5366         ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
5367         if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
5368                 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
5369                                  (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
5370                                  (pcu_mbox & 0xff) * 50);
5371                 dev_priv->rps.max_freq = pcu_mbox & 0xff;
5372         }
5373
5374         dev_priv->rps.power = HIGH_POWER; /* force a reset */
5375         gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
5376
5377         rc6vids = 0;
5378         ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
5379         if (IS_GEN6(dev_priv) && ret) {
5380                 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
5381         } else if (IS_GEN6(dev_priv) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
5382                 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
5383                           GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
5384                 rc6vids &= 0xffff00;
5385                 rc6vids |= GEN6_ENCODE_RC6_VID(450);
5386                 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
5387                 if (ret)
5388                         DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
5389         }
5390
5391         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5392 }
5393
5394 static void __gen6_update_ring_freq(struct drm_i915_private *dev_priv)
5395 {
5396         int min_freq = 15;
5397         unsigned int gpu_freq;
5398         unsigned int max_ia_freq, min_ring_freq;
5399         unsigned int max_gpu_freq, min_gpu_freq;
5400         int scaling_factor = 180;
5401         struct cpufreq_policy *policy;
5402
5403         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5404
5405         policy = cpufreq_cpu_get(0);
5406         if (policy) {
5407                 max_ia_freq = policy->cpuinfo.max_freq;
5408                 cpufreq_cpu_put(policy);
5409         } else {
5410                 /*
5411                  * Default to measured freq if none found, PCU will ensure we
5412                  * don't go over
5413                  */
5414                 max_ia_freq = tsc_khz;
5415         }
5416
5417         /* Convert from kHz to MHz */
5418         max_ia_freq /= 1000;
5419
5420         min_ring_freq = I915_READ(DCLK) & 0xf;
5421         /* convert DDR frequency from units of 266.6MHz to bandwidth */
5422         min_ring_freq = mult_frac(min_ring_freq, 8, 3);
5423
5424         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5425                 /* Convert GT frequency to 50 HZ units */
5426                 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
5427                 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
5428         } else {
5429                 min_gpu_freq = dev_priv->rps.min_freq;
5430                 max_gpu_freq = dev_priv->rps.max_freq;
5431         }
5432
5433         /*
5434          * For each potential GPU frequency, load a ring frequency we'd like
5435          * to use for memory access.  We do this by specifying the IA frequency
5436          * the PCU should use as a reference to determine the ring frequency.
5437          */
5438         for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
5439                 int diff = max_gpu_freq - gpu_freq;
5440                 unsigned int ia_freq = 0, ring_freq = 0;
5441
5442                 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5443                         /*
5444                          * ring_freq = 2 * GT. ring_freq is in 100MHz units
5445                          * No floor required for ring frequency on SKL.
5446                          */
5447                         ring_freq = gpu_freq;
5448                 } else if (INTEL_INFO(dev_priv)->gen >= 8) {
5449                         /* max(2 * GT, DDR). NB: GT is 50MHz units */
5450                         ring_freq = max(min_ring_freq, gpu_freq);
5451                 } else if (IS_HASWELL(dev_priv)) {
5452                         ring_freq = mult_frac(gpu_freq, 5, 4);
5453                         ring_freq = max(min_ring_freq, ring_freq);
5454                         /* leave ia_freq as the default, chosen by cpufreq */
5455                 } else {
5456                         /* On older processors, there is no separate ring
5457                          * clock domain, so in order to boost the bandwidth
5458                          * of the ring, we need to upclock the CPU (ia_freq).
5459                          *
5460                          * For GPU frequencies less than 750MHz,
5461                          * just use the lowest ring freq.
5462                          */
5463                         if (gpu_freq < min_freq)
5464                                 ia_freq = 800;
5465                         else
5466                                 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
5467                         ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
5468                 }
5469
5470                 sandybridge_pcode_write(dev_priv,
5471                                         GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
5472                                         ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
5473                                         ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
5474                                         gpu_freq);
5475         }
5476 }
5477
5478 void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
5479 {
5480         if (!HAS_CORE_RING_FREQ(dev_priv))
5481                 return;
5482
5483         mutex_lock(&dev_priv->rps.hw_lock);
5484         __gen6_update_ring_freq(dev_priv);
5485         mutex_unlock(&dev_priv->rps.hw_lock);
5486 }
5487
5488 static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
5489 {
5490         u32 val, rp0;
5491
5492         val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5493
5494         switch (INTEL_INFO(dev_priv)->eu_total) {
5495         case 8:
5496                 /* (2 * 4) config */
5497                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5498                 break;
5499         case 12:
5500                 /* (2 * 6) config */
5501                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5502                 break;
5503         case 16:
5504                 /* (2 * 8) config */
5505         default:
5506                 /* Setting (2 * 8) Min RP0 for any other combination */
5507                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5508                 break;
5509         }
5510
5511         rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5512
5513         return rp0;
5514 }
5515
5516 static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5517 {
5518         u32 val, rpe;
5519
5520         val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5521         rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5522
5523         return rpe;
5524 }
5525
5526 static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5527 {
5528         u32 val, rp1;
5529
5530         val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5531         rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5532
5533         return rp1;
5534 }
5535
5536 static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5537 {
5538         u32 val, rp1;
5539
5540         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5541
5542         rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5543
5544         return rp1;
5545 }
5546
5547 static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
5548 {
5549         u32 val, rp0;
5550
5551         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5552
5553         rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5554         /* Clamp to max */
5555         rp0 = min_t(u32, rp0, 0xea);
5556
5557         return rp0;
5558 }
5559
5560 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5561 {
5562         u32 val, rpe;
5563
5564         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
5565         rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
5566         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
5567         rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5568
5569         return rpe;
5570 }
5571
5572 static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
5573 {
5574         u32 val;
5575
5576         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
5577         /*
5578          * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
5579          * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
5580          * a BYT-M B0 the above register contains 0xbf. Moreover when setting
5581          * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
5582          * to make sure it matches what Punit accepts.
5583          */
5584         return max_t(u32, val, 0xc0);
5585 }
5586
5587 /* Check that the pctx buffer wasn't move under us. */
5588 static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5589 {
5590         unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5591
5592         WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5593                              dev_priv->vlv_pctx->stolen->start);
5594 }
5595
5596
5597 /* Check that the pcbr address is not empty. */
5598 static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5599 {
5600         unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5601
5602         WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5603 }
5604
5605 static void cherryview_setup_pctx(struct drm_i915_private *dev_priv)
5606 {
5607         struct i915_ggtt *ggtt = &dev_priv->ggtt;
5608         unsigned long pctx_paddr, paddr;
5609         u32 pcbr;
5610         int pctx_size = 32*1024;
5611
5612         pcbr = I915_READ(VLV_PCBR);
5613         if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
5614                 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5615                 paddr = (dev_priv->mm.stolen_base +
5616                          (ggtt->stolen_size - pctx_size));
5617
5618                 pctx_paddr = (paddr & (~4095));
5619                 I915_WRITE(VLV_PCBR, pctx_paddr);
5620         }
5621
5622         DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5623 }
5624
5625 static void valleyview_setup_pctx(struct drm_i915_private *dev_priv)
5626 {
5627         struct drm_i915_gem_object *pctx;
5628         unsigned long pctx_paddr;
5629         u32 pcbr;
5630         int pctx_size = 24*1024;
5631
5632         mutex_lock(&dev_priv->dev->struct_mutex);
5633
5634         pcbr = I915_READ(VLV_PCBR);
5635         if (pcbr) {
5636                 /* BIOS set it up already, grab the pre-alloc'd space */
5637                 int pcbr_offset;
5638
5639                 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
5640                 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
5641                                                                       pcbr_offset,
5642                                                                       I915_GTT_OFFSET_NONE,
5643                                                                       pctx_size);
5644                 goto out;
5645         }
5646
5647         DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5648
5649         /*
5650          * From the Gunit register HAS:
5651          * The Gfx driver is expected to program this register and ensure
5652          * proper allocation within Gfx stolen memory.  For example, this
5653          * register should be programmed such than the PCBR range does not
5654          * overlap with other ranges, such as the frame buffer, protected
5655          * memory, or any other relevant ranges.
5656          */
5657         pctx = i915_gem_object_create_stolen(dev_priv->dev, pctx_size);
5658         if (!pctx) {
5659                 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
5660                 goto out;
5661         }
5662
5663         pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5664         I915_WRITE(VLV_PCBR, pctx_paddr);
5665
5666 out:
5667         DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5668         dev_priv->vlv_pctx = pctx;
5669         mutex_unlock(&dev_priv->dev->struct_mutex);
5670 }
5671
5672 static void valleyview_cleanup_pctx(struct drm_i915_private *dev_priv)
5673 {
5674         if (WARN_ON(!dev_priv->vlv_pctx))
5675                 return;
5676
5677         drm_gem_object_unreference_unlocked(&dev_priv->vlv_pctx->base);
5678         dev_priv->vlv_pctx = NULL;
5679 }
5680
5681 static void vlv_init_gpll_ref_freq(struct drm_i915_private *dev_priv)
5682 {
5683         dev_priv->rps.gpll_ref_freq =
5684                 vlv_get_cck_clock(dev_priv, "GPLL ref",
5685                                   CCK_GPLL_CLOCK_CONTROL,
5686                                   dev_priv->czclk_freq);
5687
5688         DRM_DEBUG_DRIVER("GPLL reference freq: %d kHz\n",
5689                          dev_priv->rps.gpll_ref_freq);
5690 }
5691
5692 static void valleyview_init_gt_powersave(struct drm_i915_private *dev_priv)
5693 {
5694         u32 val;
5695
5696         valleyview_setup_pctx(dev_priv);
5697
5698         vlv_init_gpll_ref_freq(dev_priv);
5699
5700         mutex_lock(&dev_priv->rps.hw_lock);
5701
5702         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5703         switch ((val >> 6) & 3) {
5704         case 0:
5705         case 1:
5706                 dev_priv->mem_freq = 800;
5707                 break;
5708         case 2:
5709                 dev_priv->mem_freq = 1066;
5710                 break;
5711         case 3:
5712                 dev_priv->mem_freq = 1333;
5713                 break;
5714         }
5715         DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5716
5717         dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5718         dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5719         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5720                          intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5721                          dev_priv->rps.max_freq);
5722
5723         dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5724         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5725                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5726                          dev_priv->rps.efficient_freq);
5727
5728         dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5729         DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
5730                          intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5731                          dev_priv->rps.rp1_freq);
5732
5733         dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5734         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5735                          intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5736                          dev_priv->rps.min_freq);
5737
5738         dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5739
5740         /* Preserve min/max settings in case of re-init */
5741         if (dev_priv->rps.max_freq_softlimit == 0)
5742                 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5743
5744         if (dev_priv->rps.min_freq_softlimit == 0)
5745                 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5746
5747         mutex_unlock(&dev_priv->rps.hw_lock);
5748 }
5749
5750 static void cherryview_init_gt_powersave(struct drm_i915_private *dev_priv)
5751 {
5752         u32 val;
5753
5754         cherryview_setup_pctx(dev_priv);
5755
5756         vlv_init_gpll_ref_freq(dev_priv);
5757
5758         mutex_lock(&dev_priv->rps.hw_lock);
5759
5760         mutex_lock(&dev_priv->sb_lock);
5761         val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
5762         mutex_unlock(&dev_priv->sb_lock);
5763
5764         switch ((val >> 2) & 0x7) {
5765         case 3:
5766                 dev_priv->mem_freq = 2000;
5767                 break;
5768         default:
5769                 dev_priv->mem_freq = 1600;
5770                 break;
5771         }
5772         DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5773
5774         dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5775         dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5776         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5777                          intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5778                          dev_priv->rps.max_freq);
5779
5780         dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5781         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5782                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5783                          dev_priv->rps.efficient_freq);
5784
5785         dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5786         DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
5787                          intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5788                          dev_priv->rps.rp1_freq);
5789
5790         /* PUnit validated range is only [RPe, RP0] */
5791         dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
5792         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5793                          intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5794                          dev_priv->rps.min_freq);
5795
5796         WARN_ONCE((dev_priv->rps.max_freq |
5797                    dev_priv->rps.efficient_freq |
5798                    dev_priv->rps.rp1_freq |
5799                    dev_priv->rps.min_freq) & 1,
5800                   "Odd GPU freq values\n");
5801
5802         dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5803
5804         /* Preserve min/max settings in case of re-init */
5805         if (dev_priv->rps.max_freq_softlimit == 0)
5806                 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5807
5808         if (dev_priv->rps.min_freq_softlimit == 0)
5809                 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5810
5811         mutex_unlock(&dev_priv->rps.hw_lock);
5812 }
5813
5814 static void valleyview_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
5815 {
5816         valleyview_cleanup_pctx(dev_priv);
5817 }
5818
5819 static void cherryview_enable_rps(struct drm_i915_private *dev_priv)
5820 {
5821         struct intel_engine_cs *engine;
5822         u32 gtfifodbg, val, rc6_mode = 0, pcbr;
5823
5824         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5825
5826         gtfifodbg = I915_READ(GTFIFODBG) & ~(GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV |
5827                                              GT_FIFO_FREE_ENTRIES_CHV);
5828         if (gtfifodbg) {
5829                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5830                                  gtfifodbg);
5831                 I915_WRITE(GTFIFODBG, gtfifodbg);
5832         }
5833
5834         cherryview_check_pctx(dev_priv);
5835
5836         /* 1a & 1b: Get forcewake during program sequence. Although the driver
5837          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5838         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5839
5840         /*  Disable RC states. */
5841         I915_WRITE(GEN6_RC_CONTROL, 0);
5842
5843         /* 2a: Program RC6 thresholds.*/
5844         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5845         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5846         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5847
5848         for_each_engine(engine, dev_priv)
5849                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5850         I915_WRITE(GEN6_RC_SLEEP, 0);
5851
5852         /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
5853         I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
5854
5855         /* allows RC6 residency counter to work */
5856         I915_WRITE(VLV_COUNTER_CONTROL,
5857                    _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
5858                                       VLV_MEDIA_RC6_COUNT_EN |
5859                                       VLV_RENDER_RC6_COUNT_EN));
5860
5861         /* For now we assume BIOS is allocating and populating the PCBR  */
5862         pcbr = I915_READ(VLV_PCBR);
5863
5864         /* 3: Enable RC6 */
5865         if ((intel_enable_rc6() & INTEL_RC6_ENABLE) &&
5866             (pcbr >> VLV_PCBR_ADDR_SHIFT))
5867                 rc6_mode = GEN7_RC_CTL_TO_MODE;
5868
5869         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5870
5871         /* 4 Program defaults and thresholds for RPS*/
5872         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
5873         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5874         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5875         I915_WRITE(GEN6_RP_UP_EI, 66000);
5876         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5877
5878         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5879
5880         /* 5: Enable RPS */
5881         I915_WRITE(GEN6_RP_CONTROL,
5882                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
5883                    GEN6_RP_MEDIA_IS_GFX |
5884                    GEN6_RP_ENABLE |
5885                    GEN6_RP_UP_BUSY_AVG |
5886                    GEN6_RP_DOWN_IDLE_AVG);
5887
5888         /* Setting Fixed Bias */
5889         val = VLV_OVERRIDE_EN |
5890                   VLV_SOC_TDP_EN |
5891                   CHV_BIAS_CPU_50_SOC_50;
5892         vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5893
5894         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5895
5896         /* RPS code assumes GPLL is used */
5897         WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5898
5899         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
5900         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5901
5902         dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5903         DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
5904                          intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
5905                          dev_priv->rps.cur_freq);
5906
5907         DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5908                          intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq),
5909                          dev_priv->rps.idle_freq);
5910
5911         valleyview_set_rps(dev_priv, dev_priv->rps.idle_freq);
5912
5913         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5914 }
5915
5916 static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
5917 {
5918         struct intel_engine_cs *engine;
5919         u32 gtfifodbg, val, rc6_mode = 0;
5920
5921         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5922
5923         valleyview_check_pctx(dev_priv);
5924
5925         gtfifodbg = I915_READ(GTFIFODBG);
5926         if (gtfifodbg) {
5927                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5928                                  gtfifodbg);
5929                 I915_WRITE(GTFIFODBG, gtfifodbg);
5930         }
5931
5932         /* If VLV, Forcewake all wells, else re-direct to regular path */
5933         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5934
5935         /*  Disable RC states. */
5936         I915_WRITE(GEN6_RC_CONTROL, 0);
5937
5938         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
5939         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5940         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5941         I915_WRITE(GEN6_RP_UP_EI, 66000);
5942         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5943
5944         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5945
5946         I915_WRITE(GEN6_RP_CONTROL,
5947                    GEN6_RP_MEDIA_TURBO |
5948                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
5949                    GEN6_RP_MEDIA_IS_GFX |
5950                    GEN6_RP_ENABLE |
5951                    GEN6_RP_UP_BUSY_AVG |
5952                    GEN6_RP_DOWN_IDLE_CONT);
5953
5954         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
5955         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5956         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5957
5958         for_each_engine(engine, dev_priv)
5959                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5960
5961         I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
5962
5963         /* allows RC6 residency counter to work */
5964         I915_WRITE(VLV_COUNTER_CONTROL,
5965                    _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
5966                                       VLV_RENDER_RC0_COUNT_EN |
5967                                       VLV_MEDIA_RC6_COUNT_EN |
5968                                       VLV_RENDER_RC6_COUNT_EN));
5969
5970         if (intel_enable_rc6() & INTEL_RC6_ENABLE)
5971                 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
5972
5973         intel_print_rc6_info(dev_priv, rc6_mode);
5974
5975         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5976
5977         /* Setting Fixed Bias */
5978         val = VLV_OVERRIDE_EN |
5979                   VLV_SOC_TDP_EN |
5980                   VLV_BIAS_CPU_125_SOC_875;
5981         vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5982
5983         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5984
5985         /* RPS code assumes GPLL is used */
5986         WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5987
5988         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
5989         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5990
5991         dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5992         DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
5993                          intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
5994                          dev_priv->rps.cur_freq);
5995
5996         DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5997                          intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq),
5998                          dev_priv->rps.idle_freq);
5999
6000         valleyview_set_rps(dev_priv, dev_priv->rps.idle_freq);
6001
6002         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6003 }
6004
6005 static unsigned long intel_pxfreq(u32 vidfreq)
6006 {
6007         unsigned long freq;
6008         int div = (vidfreq & 0x3f0000) >> 16;
6009         int post = (vidfreq & 0x3000) >> 12;
6010         int pre = (vidfreq & 0x7);
6011
6012         if (!pre)
6013                 return 0;
6014
6015         freq = ((div * 133333) / ((1<<post) * pre));
6016
6017         return freq;
6018 }
6019
6020 static const struct cparams {
6021         u16 i;
6022         u16 t;
6023         u16 m;
6024         u16 c;
6025 } cparams[] = {
6026         { 1, 1333, 301, 28664 },
6027         { 1, 1066, 294, 24460 },
6028         { 1, 800, 294, 25192 },
6029         { 0, 1333, 276, 27605 },
6030         { 0, 1066, 276, 27605 },
6031         { 0, 800, 231, 23784 },
6032 };
6033
6034 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
6035 {
6036         u64 total_count, diff, ret;
6037         u32 count1, count2, count3, m = 0, c = 0;
6038         unsigned long now = jiffies_to_msecs(jiffies), diff1;
6039         int i;
6040
6041         assert_spin_locked(&mchdev_lock);
6042
6043         diff1 = now - dev_priv->ips.last_time1;
6044
6045         /* Prevent division-by-zero if we are asking too fast.
6046          * Also, we don't get interesting results if we are polling
6047          * faster than once in 10ms, so just return the saved value
6048          * in such cases.
6049          */
6050         if (diff1 <= 10)
6051                 return dev_priv->ips.chipset_power;
6052
6053         count1 = I915_READ(DMIEC);
6054         count2 = I915_READ(DDREC);
6055         count3 = I915_READ(CSIEC);
6056
6057         total_count = count1 + count2 + count3;
6058
6059         /* FIXME: handle per-counter overflow */
6060         if (total_count < dev_priv->ips.last_count1) {
6061                 diff = ~0UL - dev_priv->ips.last_count1;
6062                 diff += total_count;
6063         } else {
6064                 diff = total_count - dev_priv->ips.last_count1;
6065         }
6066
6067         for (i = 0; i < ARRAY_SIZE(cparams); i++) {
6068                 if (cparams[i].i == dev_priv->ips.c_m &&
6069                     cparams[i].t == dev_priv->ips.r_t) {
6070                         m = cparams[i].m;
6071                         c = cparams[i].c;
6072                         break;
6073                 }
6074         }
6075
6076         diff = div_u64(diff, diff1);
6077         ret = ((m * diff) + c);
6078         ret = div_u64(ret, 10);
6079
6080         dev_priv->ips.last_count1 = total_count;
6081         dev_priv->ips.last_time1 = now;
6082
6083         dev_priv->ips.chipset_power = ret;
6084
6085         return ret;
6086 }
6087
6088 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
6089 {
6090         unsigned long val;
6091
6092         if (INTEL_INFO(dev_priv)->gen != 5)
6093                 return 0;
6094
6095         spin_lock_irq(&mchdev_lock);
6096
6097         val = __i915_chipset_val(dev_priv);
6098
6099         spin_unlock_irq(&mchdev_lock);
6100
6101         return val;
6102 }
6103
6104 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
6105 {
6106         unsigned long m, x, b;
6107         u32 tsfs;
6108
6109         tsfs = I915_READ(TSFS);
6110
6111         m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
6112         x = I915_READ8(TR1);
6113
6114         b = tsfs & TSFS_INTR_MASK;
6115
6116         return ((m * x) / 127) - b;
6117 }
6118
6119 static int _pxvid_to_vd(u8 pxvid)
6120 {
6121         if (pxvid == 0)
6122                 return 0;
6123
6124         if (pxvid >= 8 && pxvid < 31)
6125                 pxvid = 31;
6126
6127         return (pxvid + 2) * 125;
6128 }
6129
6130 static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
6131 {
6132         const int vd = _pxvid_to_vd(pxvid);
6133         const int vm = vd - 1125;
6134
6135         if (INTEL_INFO(dev_priv)->is_mobile)
6136                 return vm > 0 ? vm : 0;
6137
6138         return vd;
6139 }
6140
6141 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
6142 {
6143         u64 now, diff, diffms;
6144         u32 count;
6145
6146         assert_spin_locked(&mchdev_lock);
6147
6148         now = ktime_get_raw_ns();
6149         diffms = now - dev_priv->ips.last_time2;
6150         do_div(diffms, NSEC_PER_MSEC);
6151
6152         /* Don't divide by 0 */
6153         if (!diffms)
6154                 return;
6155
6156         count = I915_READ(GFXEC);
6157
6158         if (count < dev_priv->ips.last_count2) {
6159                 diff = ~0UL - dev_priv->ips.last_count2;
6160                 diff += count;
6161         } else {
6162                 diff = count - dev_priv->ips.last_count2;
6163         }
6164
6165         dev_priv->ips.last_count2 = count;
6166         dev_priv->ips.last_time2 = now;
6167
6168         /* More magic constants... */
6169         diff = diff * 1181;
6170         diff = div_u64(diff, diffms * 10);
6171         dev_priv->ips.gfx_power = diff;
6172 }
6173
6174 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
6175 {
6176         if (INTEL_INFO(dev_priv)->gen != 5)
6177                 return;
6178
6179         spin_lock_irq(&mchdev_lock);
6180
6181         __i915_update_gfx_val(dev_priv);
6182
6183         spin_unlock_irq(&mchdev_lock);
6184 }
6185
6186 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
6187 {
6188         unsigned long t, corr, state1, corr2, state2;
6189         u32 pxvid, ext_v;
6190
6191         assert_spin_locked(&mchdev_lock);
6192
6193         pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
6194         pxvid = (pxvid >> 24) & 0x7f;
6195         ext_v = pvid_to_extvid(dev_priv, pxvid);
6196
6197         state1 = ext_v;
6198
6199         t = i915_mch_val(dev_priv);
6200
6201         /* Revel in the empirically derived constants */
6202
6203         /* Correction factor in 1/100000 units */
6204         if (t > 80)
6205                 corr = ((t * 2349) + 135940);
6206         else if (t >= 50)
6207                 corr = ((t * 964) + 29317);
6208         else /* < 50 */
6209                 corr = ((t * 301) + 1004);
6210
6211         corr = corr * ((150142 * state1) / 10000 - 78642);
6212         corr /= 100000;
6213         corr2 = (corr * dev_priv->ips.corr);
6214
6215         state2 = (corr2 * state1) / 10000;
6216         state2 /= 100; /* convert to mW */
6217
6218         __i915_update_gfx_val(dev_priv);
6219
6220         return dev_priv->ips.gfx_power + state2;
6221 }
6222
6223 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
6224 {
6225         unsigned long val;
6226
6227         if (INTEL_INFO(dev_priv)->gen != 5)
6228                 return 0;
6229
6230         spin_lock_irq(&mchdev_lock);
6231
6232         val = __i915_gfx_val(dev_priv);
6233
6234         spin_unlock_irq(&mchdev_lock);
6235
6236         return val;
6237 }
6238
6239 /**
6240  * i915_read_mch_val - return value for IPS use
6241  *
6242  * Calculate and return a value for the IPS driver to use when deciding whether
6243  * we have thermal and power headroom to increase CPU or GPU power budget.
6244  */
6245 unsigned long i915_read_mch_val(void)
6246 {
6247         struct drm_i915_private *dev_priv;
6248         unsigned long chipset_val, graphics_val, ret = 0;
6249
6250         spin_lock_irq(&mchdev_lock);
6251         if (!i915_mch_dev)
6252                 goto out_unlock;
6253         dev_priv = i915_mch_dev;
6254
6255         chipset_val = __i915_chipset_val(dev_priv);
6256         graphics_val = __i915_gfx_val(dev_priv);
6257
6258         ret = chipset_val + graphics_val;
6259
6260 out_unlock:
6261         spin_unlock_irq(&mchdev_lock);
6262
6263         return ret;
6264 }
6265 EXPORT_SYMBOL_GPL(i915_read_mch_val);
6266
6267 /**
6268  * i915_gpu_raise - raise GPU frequency limit
6269  *
6270  * Raise the limit; IPS indicates we have thermal headroom.
6271  */
6272 bool i915_gpu_raise(void)
6273 {
6274         struct drm_i915_private *dev_priv;
6275         bool ret = true;
6276
6277         spin_lock_irq(&mchdev_lock);
6278         if (!i915_mch_dev) {
6279                 ret = false;
6280                 goto out_unlock;
6281         }
6282         dev_priv = i915_mch_dev;
6283
6284         if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
6285                 dev_priv->ips.max_delay--;
6286
6287 out_unlock:
6288         spin_unlock_irq(&mchdev_lock);
6289
6290         return ret;
6291 }
6292 EXPORT_SYMBOL_GPL(i915_gpu_raise);
6293
6294 /**
6295  * i915_gpu_lower - lower GPU frequency limit
6296  *
6297  * IPS indicates we're close to a thermal limit, so throttle back the GPU
6298  * frequency maximum.
6299  */
6300 bool i915_gpu_lower(void)
6301 {
6302         struct drm_i915_private *dev_priv;
6303         bool ret = true;
6304
6305         spin_lock_irq(&mchdev_lock);
6306         if (!i915_mch_dev) {
6307                 ret = false;
6308                 goto out_unlock;
6309         }
6310         dev_priv = i915_mch_dev;
6311
6312         if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
6313                 dev_priv->ips.max_delay++;
6314
6315 out_unlock:
6316         spin_unlock_irq(&mchdev_lock);
6317
6318         return ret;
6319 }
6320 EXPORT_SYMBOL_GPL(i915_gpu_lower);
6321
6322 /**
6323  * i915_gpu_busy - indicate GPU business to IPS
6324  *
6325  * Tell the IPS driver whether or not the GPU is busy.
6326  */
6327 bool i915_gpu_busy(void)
6328 {
6329         struct drm_i915_private *dev_priv;
6330         struct intel_engine_cs *engine;
6331         bool ret = false;
6332
6333         spin_lock_irq(&mchdev_lock);
6334         if (!i915_mch_dev)
6335                 goto out_unlock;
6336         dev_priv = i915_mch_dev;
6337
6338         for_each_engine(engine, dev_priv)
6339                 ret |= !list_empty(&engine->request_list);
6340
6341 out_unlock:
6342         spin_unlock_irq(&mchdev_lock);
6343
6344         return ret;
6345 }
6346 EXPORT_SYMBOL_GPL(i915_gpu_busy);
6347
6348 /**
6349  * i915_gpu_turbo_disable - disable graphics turbo
6350  *
6351  * Disable graphics turbo by resetting the max frequency and setting the
6352  * current frequency to the default.
6353  */
6354 bool i915_gpu_turbo_disable(void)
6355 {
6356         struct drm_i915_private *dev_priv;
6357         bool ret = true;
6358
6359         spin_lock_irq(&mchdev_lock);
6360         if (!i915_mch_dev) {
6361                 ret = false;
6362                 goto out_unlock;
6363         }
6364         dev_priv = i915_mch_dev;
6365
6366         dev_priv->ips.max_delay = dev_priv->ips.fstart;
6367
6368         if (!ironlake_set_drps(dev_priv, dev_priv->ips.fstart))
6369                 ret = false;
6370
6371 out_unlock:
6372         spin_unlock_irq(&mchdev_lock);
6373
6374         return ret;
6375 }
6376 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
6377
6378 /**
6379  * Tells the intel_ips driver that the i915 driver is now loaded, if
6380  * IPS got loaded first.
6381  *
6382  * This awkward dance is so that neither module has to depend on the
6383  * other in order for IPS to do the appropriate communication of
6384  * GPU turbo limits to i915.
6385  */
6386 static void
6387 ips_ping_for_i915_load(void)
6388 {
6389         void (*link)(void);
6390
6391         link = symbol_get(ips_link_to_i915_driver);
6392         if (link) {
6393                 link();
6394                 symbol_put(ips_link_to_i915_driver);
6395         }
6396 }
6397
6398 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
6399 {
6400         /* We only register the i915 ips part with intel-ips once everything is
6401          * set up, to avoid intel-ips sneaking in and reading bogus values. */
6402         spin_lock_irq(&mchdev_lock);
6403         i915_mch_dev = dev_priv;
6404         spin_unlock_irq(&mchdev_lock);
6405
6406         ips_ping_for_i915_load();
6407 }
6408
6409 void intel_gpu_ips_teardown(void)
6410 {
6411         spin_lock_irq(&mchdev_lock);
6412         i915_mch_dev = NULL;
6413         spin_unlock_irq(&mchdev_lock);
6414 }
6415
6416 static void intel_init_emon(struct drm_i915_private *dev_priv)
6417 {
6418         u32 lcfuse;
6419         u8 pxw[16];
6420         int i;
6421
6422         /* Disable to program */
6423         I915_WRITE(ECR, 0);
6424         POSTING_READ(ECR);
6425
6426         /* Program energy weights for various events */
6427         I915_WRITE(SDEW, 0x15040d00);
6428         I915_WRITE(CSIEW0, 0x007f0000);
6429         I915_WRITE(CSIEW1, 0x1e220004);
6430         I915_WRITE(CSIEW2, 0x04000004);
6431
6432         for (i = 0; i < 5; i++)
6433                 I915_WRITE(PEW(i), 0);
6434         for (i = 0; i < 3; i++)
6435                 I915_WRITE(DEW(i), 0);
6436
6437         /* Program P-state weights to account for frequency power adjustment */
6438         for (i = 0; i < 16; i++) {
6439                 u32 pxvidfreq = I915_READ(PXVFREQ(i));
6440                 unsigned long freq = intel_pxfreq(pxvidfreq);
6441                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6442                         PXVFREQ_PX_SHIFT;
6443                 unsigned long val;
6444
6445                 val = vid * vid;
6446                 val *= (freq / 1000);
6447                 val *= 255;
6448                 val /= (127*127*900);
6449                 if (val > 0xff)
6450                         DRM_ERROR("bad pxval: %ld\n", val);
6451                 pxw[i] = val;
6452         }
6453         /* Render standby states get 0 weight */
6454         pxw[14] = 0;
6455         pxw[15] = 0;
6456
6457         for (i = 0; i < 4; i++) {
6458                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6459                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
6460                 I915_WRITE(PXW(i), val);
6461         }
6462
6463         /* Adjust magic regs to magic values (more experimental results) */
6464         I915_WRITE(OGW0, 0);
6465         I915_WRITE(OGW1, 0);
6466         I915_WRITE(EG0, 0x00007f00);
6467         I915_WRITE(EG1, 0x0000000e);
6468         I915_WRITE(EG2, 0x000e0000);
6469         I915_WRITE(EG3, 0x68000300);
6470         I915_WRITE(EG4, 0x42000000);
6471         I915_WRITE(EG5, 0x00140031);
6472         I915_WRITE(EG6, 0);
6473         I915_WRITE(EG7, 0);
6474
6475         for (i = 0; i < 8; i++)
6476                 I915_WRITE(PXWL(i), 0);
6477
6478         /* Enable PMON + select events */
6479         I915_WRITE(ECR, 0x80000019);
6480
6481         lcfuse = I915_READ(LCFUSE02);
6482
6483         dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
6484 }
6485
6486 void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
6487 {
6488         /*
6489          * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6490          * requirement.
6491          */
6492         if (!i915.enable_rc6) {
6493                 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6494                 intel_runtime_pm_get(dev_priv);
6495         }
6496
6497         if (IS_CHERRYVIEW(dev_priv))
6498                 cherryview_init_gt_powersave(dev_priv);
6499         else if (IS_VALLEYVIEW(dev_priv))
6500                 valleyview_init_gt_powersave(dev_priv);
6501 }
6502
6503 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
6504 {
6505         if (IS_CHERRYVIEW(dev_priv))
6506                 return;
6507         else if (IS_VALLEYVIEW(dev_priv))
6508                 valleyview_cleanup_gt_powersave(dev_priv);
6509
6510         if (!i915.enable_rc6)
6511                 intel_runtime_pm_put(dev_priv);
6512 }
6513
6514 static void gen6_suspend_rps(struct drm_i915_private *dev_priv)
6515 {
6516         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
6517
6518         gen6_disable_rps_interrupts(dev_priv);
6519 }
6520
6521 /**
6522  * intel_suspend_gt_powersave - suspend PM work and helper threads
6523  * @dev_priv: i915 device
6524  *
6525  * We don't want to disable RC6 or other features here, we just want
6526  * to make sure any work we've queued has finished and won't bother
6527  * us while we're suspended.
6528  */
6529 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv)
6530 {
6531         if (INTEL_GEN(dev_priv) < 6)
6532                 return;
6533
6534         gen6_suspend_rps(dev_priv);
6535
6536         /* Force GPU to min freq during suspend */
6537         gen6_rps_idle(dev_priv);
6538 }
6539
6540 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
6541 {
6542         if (IS_IRONLAKE_M(dev_priv)) {
6543                 ironlake_disable_drps(dev_priv);
6544         } else if (INTEL_INFO(dev_priv)->gen >= 6) {
6545                 intel_suspend_gt_powersave(dev_priv);
6546
6547                 mutex_lock(&dev_priv->rps.hw_lock);
6548                 if (INTEL_INFO(dev_priv)->gen >= 9) {
6549                         gen9_disable_rc6(dev_priv);
6550                         gen9_disable_rps(dev_priv);
6551                 } else if (IS_CHERRYVIEW(dev_priv))
6552                         cherryview_disable_rps(dev_priv);
6553                 else if (IS_VALLEYVIEW(dev_priv))
6554                         valleyview_disable_rps(dev_priv);
6555                 else
6556                         gen6_disable_rps(dev_priv);
6557
6558                 dev_priv->rps.enabled = false;
6559                 mutex_unlock(&dev_priv->rps.hw_lock);
6560         }
6561 }
6562
6563 static void intel_gen6_powersave_work(struct work_struct *work)
6564 {
6565         struct drm_i915_private *dev_priv =
6566                 container_of(work, struct drm_i915_private,
6567                              rps.delayed_resume_work.work);
6568
6569         mutex_lock(&dev_priv->rps.hw_lock);
6570
6571         gen6_reset_rps_interrupts(dev_priv);
6572
6573         if (IS_CHERRYVIEW(dev_priv)) {
6574                 cherryview_enable_rps(dev_priv);
6575         } else if (IS_VALLEYVIEW(dev_priv)) {
6576                 valleyview_enable_rps(dev_priv);
6577         } else if (INTEL_INFO(dev_priv)->gen >= 9) {
6578                 gen9_enable_rc6(dev_priv);
6579                 gen9_enable_rps(dev_priv);
6580                 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
6581                         __gen6_update_ring_freq(dev_priv);
6582         } else if (IS_BROADWELL(dev_priv)) {
6583                 gen8_enable_rps(dev_priv);
6584                 __gen6_update_ring_freq(dev_priv);
6585         } else {
6586                 gen6_enable_rps(dev_priv);
6587                 __gen6_update_ring_freq(dev_priv);
6588         }
6589
6590         WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6591         WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6592
6593         WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6594         WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6595
6596         dev_priv->rps.enabled = true;
6597
6598         gen6_enable_rps_interrupts(dev_priv);
6599
6600         mutex_unlock(&dev_priv->rps.hw_lock);
6601
6602         intel_runtime_pm_put(dev_priv);
6603 }
6604
6605 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
6606 {
6607         /* Powersaving is controlled by the host when inside a VM */
6608         if (intel_vgpu_active(dev_priv))
6609                 return;
6610
6611         if (IS_IRONLAKE_M(dev_priv)) {
6612                 ironlake_enable_drps(dev_priv);
6613                 mutex_lock(&dev_priv->dev->struct_mutex);
6614                 intel_init_emon(dev_priv);
6615                 mutex_unlock(&dev_priv->dev->struct_mutex);
6616         } else if (INTEL_INFO(dev_priv)->gen >= 6) {
6617                 /*
6618                  * PCU communication is slow and this doesn't need to be
6619                  * done at any specific time, so do this out of our fast path
6620                  * to make resume and init faster.
6621                  *
6622                  * We depend on the HW RC6 power context save/restore
6623                  * mechanism when entering D3 through runtime PM suspend. So
6624                  * disable RPM until RPS/RC6 is properly setup. We can only
6625                  * get here via the driver load/system resume/runtime resume
6626                  * paths, so the _noresume version is enough (and in case of
6627                  * runtime resume it's necessary).
6628                  */
6629                 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
6630                                            round_jiffies_up_relative(HZ)))
6631                         intel_runtime_pm_get_noresume(dev_priv);
6632         }
6633 }
6634
6635 void intel_reset_gt_powersave(struct drm_i915_private *dev_priv)
6636 {
6637         if (INTEL_INFO(dev_priv)->gen < 6)
6638                 return;
6639
6640         gen6_suspend_rps(dev_priv);
6641         dev_priv->rps.enabled = false;
6642 }
6643
6644 static void ibx_init_clock_gating(struct drm_device *dev)
6645 {
6646         struct drm_i915_private *dev_priv = dev->dev_private;
6647
6648         /*
6649          * On Ibex Peak and Cougar Point, we need to disable clock
6650          * gating for the panel power sequencer or it will fail to
6651          * start up when no ports are active.
6652          */
6653         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6654 }
6655
6656 static void g4x_disable_trickle_feed(struct drm_device *dev)
6657 {
6658         struct drm_i915_private *dev_priv = dev->dev_private;
6659         enum pipe pipe;
6660
6661         for_each_pipe(dev_priv, pipe) {
6662                 I915_WRITE(DSPCNTR(pipe),
6663                            I915_READ(DSPCNTR(pipe)) |
6664                            DISPPLANE_TRICKLE_FEED_DISABLE);
6665
6666                 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6667                 POSTING_READ(DSPSURF(pipe));
6668         }
6669 }
6670
6671 static void ilk_init_lp_watermarks(struct drm_device *dev)
6672 {
6673         struct drm_i915_private *dev_priv = dev->dev_private;
6674
6675         I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6676         I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6677         I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6678
6679         /*
6680          * Don't touch WM1S_LP_EN here.
6681          * Doing so could cause underruns.
6682          */
6683 }
6684
6685 static void ironlake_init_clock_gating(struct drm_device *dev)
6686 {
6687         struct drm_i915_private *dev_priv = dev->dev_private;
6688         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6689
6690         /*
6691          * Required for FBC
6692          * WaFbcDisableDpfcClockGating:ilk
6693          */
6694         dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6695                    ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6696                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6697
6698         I915_WRITE(PCH_3DCGDIS0,
6699                    MARIUNIT_CLOCK_GATE_DISABLE |
6700                    SVSMUNIT_CLOCK_GATE_DISABLE);
6701         I915_WRITE(PCH_3DCGDIS1,
6702                    VFMUNIT_CLOCK_GATE_DISABLE);
6703
6704         /*
6705          * According to the spec the following bits should be set in
6706          * order to enable memory self-refresh
6707          * The bit 22/21 of 0x42004
6708          * The bit 5 of 0x42020
6709          * The bit 15 of 0x45000
6710          */
6711         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6712                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
6713                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
6714         dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6715         I915_WRITE(DISP_ARB_CTL,
6716                    (I915_READ(DISP_ARB_CTL) |
6717                     DISP_FBC_WM_DIS));
6718
6719         ilk_init_lp_watermarks(dev);
6720
6721         /*
6722          * Based on the document from hardware guys the following bits
6723          * should be set unconditionally in order to enable FBC.
6724          * The bit 22 of 0x42000
6725          * The bit 22 of 0x42004
6726          * The bit 7,8,9 of 0x42020.
6727          */
6728         if (IS_IRONLAKE_M(dev)) {
6729                 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6730                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6731                            I915_READ(ILK_DISPLAY_CHICKEN1) |
6732                            ILK_FBCQ_DIS);
6733                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6734                            I915_READ(ILK_DISPLAY_CHICKEN2) |
6735                            ILK_DPARB_GATE);
6736         }
6737
6738         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6739
6740         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6741                    I915_READ(ILK_DISPLAY_CHICKEN2) |
6742                    ILK_ELPIN_409_SELECT);
6743         I915_WRITE(_3D_CHICKEN2,
6744                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6745                    _3D_CHICKEN2_WM_READ_PIPELINED);
6746
6747         /* WaDisableRenderCachePipelinedFlush:ilk */
6748         I915_WRITE(CACHE_MODE_0,
6749                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
6750
6751         /* WaDisable_RenderCache_OperationalFlush:ilk */
6752         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6753
6754         g4x_disable_trickle_feed(dev);
6755
6756         ibx_init_clock_gating(dev);
6757 }
6758
6759 static void cpt_init_clock_gating(struct drm_device *dev)
6760 {
6761         struct drm_i915_private *dev_priv = dev->dev_private;
6762         int pipe;
6763         uint32_t val;
6764
6765         /*
6766          * On Ibex Peak and Cougar Point, we need to disable clock
6767          * gating for the panel power sequencer or it will fail to
6768          * start up when no ports are active.
6769          */
6770         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6771                    PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6772                    PCH_CPUNIT_CLOCK_GATE_DISABLE);
6773         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6774                    DPLS_EDP_PPS_FIX_DIS);
6775         /* The below fixes the weird display corruption, a few pixels shifted
6776          * downward, on (only) LVDS of some HP laptops with IVY.
6777          */
6778         for_each_pipe(dev_priv, pipe) {
6779                 val = I915_READ(TRANS_CHICKEN2(pipe));
6780                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6781                 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6782                 if (dev_priv->vbt.fdi_rx_polarity_inverted)
6783                         val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6784                 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
6785                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6786                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
6787                 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6788         }
6789         /* WADP0ClockGatingDisable */
6790         for_each_pipe(dev_priv, pipe) {
6791                 I915_WRITE(TRANS_CHICKEN1(pipe),
6792                            TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6793         }
6794 }
6795
6796 static void gen6_check_mch_setup(struct drm_device *dev)
6797 {
6798         struct drm_i915_private *dev_priv = dev->dev_private;
6799         uint32_t tmp;
6800
6801         tmp = I915_READ(MCH_SSKPD);
6802         if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
6803                 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
6804                               tmp);
6805 }
6806
6807 static void gen6_init_clock_gating(struct drm_device *dev)
6808 {
6809         struct drm_i915_private *dev_priv = dev->dev_private;
6810         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6811
6812         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6813
6814         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6815                    I915_READ(ILK_DISPLAY_CHICKEN2) |
6816                    ILK_ELPIN_409_SELECT);
6817
6818         /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
6819         I915_WRITE(_3D_CHICKEN,
6820                    _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
6821
6822         /* WaDisable_RenderCache_OperationalFlush:snb */
6823         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6824
6825         /*
6826          * BSpec recoomends 8x4 when MSAA is used,
6827          * however in practice 16x4 seems fastest.
6828          *
6829          * Note that PS/WM thread counts depend on the WIZ hashing
6830          * disable bit, which we don't touch here, but it's good
6831          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6832          */
6833         I915_WRITE(GEN6_GT_MODE,
6834                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6835
6836         ilk_init_lp_watermarks(dev);
6837
6838         I915_WRITE(CACHE_MODE_0,
6839                    _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6840
6841         I915_WRITE(GEN6_UCGCTL1,
6842                    I915_READ(GEN6_UCGCTL1) |
6843                    GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
6844                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6845
6846         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
6847          * gating disable must be set.  Failure to set it results in
6848          * flickering pixels due to Z write ordering failures after
6849          * some amount of runtime in the Mesa "fire" demo, and Unigine
6850          * Sanctuary and Tropics, and apparently anything else with
6851          * alpha test or pixel discard.
6852          *
6853          * According to the spec, bit 11 (RCCUNIT) must also be set,
6854          * but we didn't debug actual testcases to find it out.
6855          *
6856          * WaDisableRCCUnitClockGating:snb
6857          * WaDisableRCPBUnitClockGating:snb
6858          */
6859         I915_WRITE(GEN6_UCGCTL2,
6860                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
6861                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
6862
6863         /* WaStripsFansDisableFastClipPerformanceFix:snb */
6864         I915_WRITE(_3D_CHICKEN3,
6865                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6866
6867         /*
6868          * Bspec says:
6869          * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
6870          * 3DSTATE_SF number of SF output attributes is more than 16."
6871          */
6872         I915_WRITE(_3D_CHICKEN3,
6873                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
6874
6875         /*
6876          * According to the spec the following bits should be
6877          * set in order to enable memory self-refresh and fbc:
6878          * The bit21 and bit22 of 0x42000
6879          * The bit21 and bit22 of 0x42004
6880          * The bit5 and bit7 of 0x42020
6881          * The bit14 of 0x70180
6882          * The bit14 of 0x71180
6883          *
6884          * WaFbcAsynchFlipDisableFbcQueue:snb
6885          */
6886         I915_WRITE(ILK_DISPLAY_CHICKEN1,
6887                    I915_READ(ILK_DISPLAY_CHICKEN1) |
6888                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
6889         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6890                    I915_READ(ILK_DISPLAY_CHICKEN2) |
6891                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
6892         I915_WRITE(ILK_DSPCLK_GATE_D,
6893                    I915_READ(ILK_DSPCLK_GATE_D) |
6894                    ILK_DPARBUNIT_CLOCK_GATE_ENABLE  |
6895                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6896
6897         g4x_disable_trickle_feed(dev);
6898
6899         cpt_init_clock_gating(dev);
6900
6901         gen6_check_mch_setup(dev);
6902 }
6903
6904 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
6905 {
6906         uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
6907
6908         /*
6909          * WaVSThreadDispatchOverride:ivb,vlv
6910          *
6911          * This actually overrides the dispatch
6912          * mode for all thread types.
6913          */
6914         reg &= ~GEN7_FF_SCHED_MASK;
6915         reg |= GEN7_FF_TS_SCHED_HW;
6916         reg |= GEN7_FF_VS_SCHED_HW;
6917         reg |= GEN7_FF_DS_SCHED_HW;
6918
6919         I915_WRITE(GEN7_FF_THREAD_MODE, reg);
6920 }
6921
6922 static void lpt_init_clock_gating(struct drm_device *dev)
6923 {
6924         struct drm_i915_private *dev_priv = dev->dev_private;
6925
6926         /*
6927          * TODO: this bit should only be enabled when really needed, then
6928          * disabled when not needed anymore in order to save power.
6929          */
6930         if (HAS_PCH_LPT_LP(dev))
6931                 I915_WRITE(SOUTH_DSPCLK_GATE_D,
6932                            I915_READ(SOUTH_DSPCLK_GATE_D) |
6933                            PCH_LP_PARTITION_LEVEL_DISABLE);
6934
6935         /* WADPOClockGatingDisable:hsw */
6936         I915_WRITE(TRANS_CHICKEN1(PIPE_A),
6937                    I915_READ(TRANS_CHICKEN1(PIPE_A)) |
6938                    TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6939 }
6940
6941 static void lpt_suspend_hw(struct drm_device *dev)
6942 {
6943         struct drm_i915_private *dev_priv = dev->dev_private;
6944
6945         if (HAS_PCH_LPT_LP(dev)) {
6946                 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
6947
6948                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6949                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6950         }
6951 }
6952
6953 static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
6954                                    int general_prio_credits,
6955                                    int high_prio_credits)
6956 {
6957         u32 misccpctl;
6958
6959         /* WaTempDisableDOPClkGating:bdw */
6960         misccpctl = I915_READ(GEN7_MISCCPCTL);
6961         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
6962
6963         I915_WRITE(GEN8_L3SQCREG1,
6964                    L3_GENERAL_PRIO_CREDITS(general_prio_credits) |
6965                    L3_HIGH_PRIO_CREDITS(high_prio_credits));
6966
6967         /*
6968          * Wait at least 100 clocks before re-enabling clock gating.
6969          * See the definition of L3SQCREG1 in BSpec.
6970          */
6971         POSTING_READ(GEN8_L3SQCREG1);
6972         udelay(1);
6973         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
6974 }
6975
6976 static void kabylake_init_clock_gating(struct drm_device *dev)
6977 {
6978         struct drm_i915_private *dev_priv = dev->dev_private;
6979
6980         gen9_init_clock_gating(dev);
6981
6982         /* WaDisableSDEUnitClockGating:kbl */
6983         if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
6984                 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6985                            GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6986
6987         /* WaDisableGamClockGating:kbl */
6988         if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
6989                 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
6990                            GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
6991 }
6992
6993 static void skylake_init_clock_gating(struct drm_device *dev)
6994 {
6995         struct drm_i915_private *dev_priv = dev->dev_private;
6996
6997         gen9_init_clock_gating(dev);
6998
6999         /* WAC6entrylatency:skl */
7000         I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) |
7001                    FBC_LLC_FULLY_OPEN);
7002 }
7003
7004 static void broadwell_init_clock_gating(struct drm_device *dev)
7005 {
7006         struct drm_i915_private *dev_priv = dev->dev_private;
7007         enum pipe pipe;
7008
7009         ilk_init_lp_watermarks(dev);
7010
7011         /* WaSwitchSolVfFArbitrationPriority:bdw */
7012         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
7013
7014         /* WaPsrDPAMaskVBlankInSRD:bdw */
7015         I915_WRITE(CHICKEN_PAR1_1,
7016                    I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
7017
7018         /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
7019         for_each_pipe(dev_priv, pipe) {
7020                 I915_WRITE(CHICKEN_PIPESL_1(pipe),
7021                            I915_READ(CHICKEN_PIPESL_1(pipe)) |
7022                            BDW_DPRS_MASK_VBLANK_SRD);
7023         }
7024
7025         /* WaVSRefCountFullforceMissDisable:bdw */
7026         /* WaDSRefCountFullforceMissDisable:bdw */
7027         I915_WRITE(GEN7_FF_THREAD_MODE,
7028                    I915_READ(GEN7_FF_THREAD_MODE) &
7029                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
7030
7031         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7032                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
7033
7034         /* WaDisableSDEUnitClockGating:bdw */
7035         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7036                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
7037
7038         /* WaProgramL3SqcReg1Default:bdw */
7039         gen8_set_l3sqc_credits(dev_priv, 30, 2);
7040
7041         /*
7042          * WaGttCachingOffByDefault:bdw
7043          * GTT cache may not work with big pages, so if those
7044          * are ever enabled GTT cache may need to be disabled.
7045          */
7046         I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
7047
7048         /* WaKVMNotificationOnConfigChange:bdw */
7049         I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1)
7050                    | KVM_CONFIG_CHANGE_NOTIFICATION_SELECT);
7051
7052         lpt_init_clock_gating(dev);
7053 }
7054
7055 static void haswell_init_clock_gating(struct drm_device *dev)
7056 {
7057         struct drm_i915_private *dev_priv = dev->dev_private;
7058
7059         ilk_init_lp_watermarks(dev);
7060
7061         /* L3 caching of data atomics doesn't work -- disable it. */
7062         I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
7063         I915_WRITE(HSW_ROW_CHICKEN3,
7064                    _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
7065
7066         /* This is required by WaCatErrorRejectionIssue:hsw */
7067         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7068                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7069                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7070
7071         /* WaVSRefCountFullforceMissDisable:hsw */
7072         I915_WRITE(GEN7_FF_THREAD_MODE,
7073                    I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
7074
7075         /* WaDisable_RenderCache_OperationalFlush:hsw */
7076         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7077
7078         /* enable HiZ Raw Stall Optimization */
7079         I915_WRITE(CACHE_MODE_0_GEN7,
7080                    _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7081
7082         /* WaDisable4x2SubspanOptimization:hsw */
7083         I915_WRITE(CACHE_MODE_1,
7084                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7085
7086         /*
7087          * BSpec recommends 8x4 when MSAA is used,
7088          * however in practice 16x4 seems fastest.
7089          *
7090          * Note that PS/WM thread counts depend on the WIZ hashing
7091          * disable bit, which we don't touch here, but it's good
7092          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7093          */
7094         I915_WRITE(GEN7_GT_MODE,
7095                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7096
7097         /* WaSampleCChickenBitEnable:hsw */
7098         I915_WRITE(HALF_SLICE_CHICKEN3,
7099                    _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
7100
7101         /* WaSwitchSolVfFArbitrationPriority:hsw */
7102         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
7103
7104         /* WaRsPkgCStateDisplayPMReq:hsw */
7105         I915_WRITE(CHICKEN_PAR1_1,
7106                    I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
7107
7108         lpt_init_clock_gating(dev);
7109 }
7110
7111 static void ivybridge_init_clock_gating(struct drm_device *dev)
7112 {
7113         struct drm_i915_private *dev_priv = dev->dev_private;
7114         uint32_t snpcr;
7115
7116         ilk_init_lp_watermarks(dev);
7117
7118         I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
7119
7120         /* WaDisableEarlyCull:ivb */
7121         I915_WRITE(_3D_CHICKEN3,
7122                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7123
7124         /* WaDisableBackToBackFlipFix:ivb */
7125         I915_WRITE(IVB_CHICKEN3,
7126                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7127                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
7128
7129         /* WaDisablePSDDualDispatchEnable:ivb */
7130         if (IS_IVB_GT1(dev))
7131                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
7132                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
7133
7134         /* WaDisable_RenderCache_OperationalFlush:ivb */
7135         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7136
7137         /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
7138         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
7139                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
7140
7141         /* WaApplyL3ControlAndL3ChickenMode:ivb */
7142         I915_WRITE(GEN7_L3CNTLREG1,
7143                         GEN7_WA_FOR_GEN7_L3_CONTROL);
7144         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
7145                    GEN7_WA_L3_CHICKEN_MODE);
7146         if (IS_IVB_GT1(dev))
7147                 I915_WRITE(GEN7_ROW_CHICKEN2,
7148                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7149         else {
7150                 /* must write both registers */
7151                 I915_WRITE(GEN7_ROW_CHICKEN2,
7152                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7153                 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
7154                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7155         }
7156
7157         /* WaForceL3Serialization:ivb */
7158         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7159                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7160
7161         /*
7162          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
7163          * This implements the WaDisableRCZUnitClockGating:ivb workaround.
7164          */
7165         I915_WRITE(GEN6_UCGCTL2,
7166                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
7167
7168         /* This is required by WaCatErrorRejectionIssue:ivb */
7169         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7170                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7171                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7172
7173         g4x_disable_trickle_feed(dev);
7174
7175         gen7_setup_fixed_func_scheduler(dev_priv);
7176
7177         if (0) { /* causes HiZ corruption on ivb:gt1 */
7178                 /* enable HiZ Raw Stall Optimization */
7179                 I915_WRITE(CACHE_MODE_0_GEN7,
7180                            _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7181         }
7182
7183         /* WaDisable4x2SubspanOptimization:ivb */
7184         I915_WRITE(CACHE_MODE_1,
7185                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7186
7187         /*
7188          * BSpec recommends 8x4 when MSAA is used,
7189          * however in practice 16x4 seems fastest.
7190          *
7191          * Note that PS/WM thread counts depend on the WIZ hashing
7192          * disable bit, which we don't touch here, but it's good
7193          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7194          */
7195         I915_WRITE(GEN7_GT_MODE,
7196                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7197
7198         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
7199         snpcr &= ~GEN6_MBC_SNPCR_MASK;
7200         snpcr |= GEN6_MBC_SNPCR_MED;
7201         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
7202
7203         if (!HAS_PCH_NOP(dev))
7204                 cpt_init_clock_gating(dev);
7205
7206         gen6_check_mch_setup(dev);
7207 }
7208
7209 static void valleyview_init_clock_gating(struct drm_device *dev)
7210 {
7211         struct drm_i915_private *dev_priv = dev->dev_private;
7212
7213         /* WaDisableEarlyCull:vlv */
7214         I915_WRITE(_3D_CHICKEN3,
7215                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7216
7217         /* WaDisableBackToBackFlipFix:vlv */
7218         I915_WRITE(IVB_CHICKEN3,
7219                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7220                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
7221
7222         /* WaPsdDispatchEnable:vlv */
7223         /* WaDisablePSDDualDispatchEnable:vlv */
7224         I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
7225                    _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
7226                                       GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
7227
7228         /* WaDisable_RenderCache_OperationalFlush:vlv */
7229         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7230
7231         /* WaForceL3Serialization:vlv */
7232         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7233                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7234
7235         /* WaDisableDopClockGating:vlv */
7236         I915_WRITE(GEN7_ROW_CHICKEN2,
7237                    _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7238
7239         /* This is required by WaCatErrorRejectionIssue:vlv */
7240         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7241                    I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7242                    GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7243
7244         gen7_setup_fixed_func_scheduler(dev_priv);
7245
7246         /*
7247          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
7248          * This implements the WaDisableRCZUnitClockGating:vlv workaround.
7249          */
7250         I915_WRITE(GEN6_UCGCTL2,
7251                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
7252
7253         /* WaDisableL3Bank2xClockGate:vlv
7254          * Disabling L3 clock gating- MMIO 940c[25] = 1
7255          * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
7256         I915_WRITE(GEN7_UCGCTL4,
7257                    I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
7258
7259         /*
7260          * BSpec says this must be set, even though
7261          * WaDisable4x2SubspanOptimization isn't listed for VLV.
7262          */
7263         I915_WRITE(CACHE_MODE_1,
7264                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7265
7266         /*
7267          * BSpec recommends 8x4 when MSAA is used,
7268          * however in practice 16x4 seems fastest.
7269          *
7270          * Note that PS/WM thread counts depend on the WIZ hashing
7271          * disable bit, which we don't touch here, but it's good
7272          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7273          */
7274         I915_WRITE(GEN7_GT_MODE,
7275                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7276
7277         /*
7278          * WaIncreaseL3CreditsForVLVB0:vlv
7279          * This is the hardware default actually.
7280          */
7281         I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
7282
7283         /*
7284          * WaDisableVLVClockGating_VBIIssue:vlv
7285          * Disable clock gating on th GCFG unit to prevent a delay
7286          * in the reporting of vblank events.
7287          */
7288         I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
7289 }
7290
7291 static void cherryview_init_clock_gating(struct drm_device *dev)
7292 {
7293         struct drm_i915_private *dev_priv = dev->dev_private;
7294
7295         /* WaVSRefCountFullforceMissDisable:chv */
7296         /* WaDSRefCountFullforceMissDisable:chv */
7297         I915_WRITE(GEN7_FF_THREAD_MODE,
7298                    I915_READ(GEN7_FF_THREAD_MODE) &
7299                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
7300
7301         /* WaDisableSemaphoreAndSyncFlipWait:chv */
7302         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7303                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
7304
7305         /* WaDisableCSUnitClockGating:chv */
7306         I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7307                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
7308
7309         /* WaDisableSDEUnitClockGating:chv */
7310         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7311                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
7312
7313         /*
7314          * WaProgramL3SqcReg1Default:chv
7315          * See gfxspecs/Related Documents/Performance Guide/
7316          * LSQC Setting Recommendations.
7317          */
7318         gen8_set_l3sqc_credits(dev_priv, 38, 2);
7319
7320         /*
7321          * GTT cache may not work with big pages, so if those
7322          * are ever enabled GTT cache may need to be disabled.
7323          */
7324         I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
7325 }
7326
7327 static void g4x_init_clock_gating(struct drm_device *dev)
7328 {
7329         struct drm_i915_private *dev_priv = dev->dev_private;
7330         uint32_t dspclk_gate;
7331
7332         I915_WRITE(RENCLK_GATE_D1, 0);
7333         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7334                    GS_UNIT_CLOCK_GATE_DISABLE |
7335                    CL_UNIT_CLOCK_GATE_DISABLE);
7336         I915_WRITE(RAMCLK_GATE_D, 0);
7337         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7338                 OVRUNIT_CLOCK_GATE_DISABLE |
7339                 OVCUNIT_CLOCK_GATE_DISABLE;
7340         if (IS_GM45(dev))
7341                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7342         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
7343
7344         /* WaDisableRenderCachePipelinedFlush */
7345         I915_WRITE(CACHE_MODE_0,
7346                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
7347
7348         /* WaDisable_RenderCache_OperationalFlush:g4x */
7349         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7350
7351         g4x_disable_trickle_feed(dev);
7352 }
7353
7354 static void crestline_init_clock_gating(struct drm_device *dev)
7355 {
7356         struct drm_i915_private *dev_priv = dev->dev_private;
7357
7358         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7359         I915_WRITE(RENCLK_GATE_D2, 0);
7360         I915_WRITE(DSPCLK_GATE_D, 0);
7361         I915_WRITE(RAMCLK_GATE_D, 0);
7362         I915_WRITE16(DEUC, 0);
7363         I915_WRITE(MI_ARB_STATE,
7364                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7365
7366         /* WaDisable_RenderCache_OperationalFlush:gen4 */
7367         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7368 }
7369
7370 static void broadwater_init_clock_gating(struct drm_device *dev)
7371 {
7372         struct drm_i915_private *dev_priv = dev->dev_private;
7373
7374         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7375                    I965_RCC_CLOCK_GATE_DISABLE |
7376                    I965_RCPB_CLOCK_GATE_DISABLE |
7377                    I965_ISC_CLOCK_GATE_DISABLE |
7378                    I965_FBC_CLOCK_GATE_DISABLE);
7379         I915_WRITE(RENCLK_GATE_D2, 0);
7380         I915_WRITE(MI_ARB_STATE,
7381                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7382
7383         /* WaDisable_RenderCache_OperationalFlush:gen4 */
7384         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7385 }
7386
7387 static void gen3_init_clock_gating(struct drm_device *dev)
7388 {
7389         struct drm_i915_private *dev_priv = dev->dev_private;
7390         u32 dstate = I915_READ(D_STATE);
7391
7392         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7393                 DSTATE_DOT_CLOCK_GATING;
7394         I915_WRITE(D_STATE, dstate);
7395
7396         if (IS_PINEVIEW(dev))
7397                 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
7398
7399         /* IIR "flip pending" means done if this bit is set */
7400         I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
7401
7402         /* interrupts should cause a wake up from C3 */
7403         I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
7404
7405         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
7406         I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
7407
7408         I915_WRITE(MI_ARB_STATE,
7409                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7410 }
7411
7412 static void i85x_init_clock_gating(struct drm_device *dev)
7413 {
7414         struct drm_i915_private *dev_priv = dev->dev_private;
7415
7416         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
7417
7418         /* interrupts should cause a wake up from C3 */
7419         I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
7420                    _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
7421
7422         I915_WRITE(MEM_MODE,
7423                    _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
7424 }
7425
7426 static void i830_init_clock_gating(struct drm_device *dev)
7427 {
7428         struct drm_i915_private *dev_priv = dev->dev_private;
7429
7430         I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
7431
7432         I915_WRITE(MEM_MODE,
7433                    _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
7434                    _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
7435 }
7436
7437 void intel_init_clock_gating(struct drm_device *dev)
7438 {
7439         struct drm_i915_private *dev_priv = dev->dev_private;
7440
7441         dev_priv->display.init_clock_gating(dev);
7442 }
7443
7444 void intel_suspend_hw(struct drm_device *dev)
7445 {
7446         if (HAS_PCH_LPT(dev))
7447                 lpt_suspend_hw(dev);
7448 }
7449
7450 static void nop_init_clock_gating(struct drm_device *dev)
7451 {
7452         DRM_DEBUG_KMS("No clock gating settings or workarounds applied.\n");
7453 }
7454
7455 /**
7456  * intel_init_clock_gating_hooks - setup the clock gating hooks
7457  * @dev_priv: device private
7458  *
7459  * Setup the hooks that configure which clocks of a given platform can be
7460  * gated and also apply various GT and display specific workarounds for these
7461  * platforms. Note that some GT specific workarounds are applied separately
7462  * when GPU contexts or batchbuffers start their execution.
7463  */
7464 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
7465 {
7466         if (IS_SKYLAKE(dev_priv))
7467                 dev_priv->display.init_clock_gating = skylake_init_clock_gating;
7468         else if (IS_KABYLAKE(dev_priv))
7469                 dev_priv->display.init_clock_gating = kabylake_init_clock_gating;
7470         else if (IS_BROXTON(dev_priv))
7471                 dev_priv->display.init_clock_gating = bxt_init_clock_gating;
7472         else if (IS_BROADWELL(dev_priv))
7473                 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
7474         else if (IS_CHERRYVIEW(dev_priv))
7475                 dev_priv->display.init_clock_gating = cherryview_init_clock_gating;
7476         else if (IS_HASWELL(dev_priv))
7477                 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
7478         else if (IS_IVYBRIDGE(dev_priv))
7479                 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7480         else if (IS_VALLEYVIEW(dev_priv))
7481                 dev_priv->display.init_clock_gating = valleyview_init_clock_gating;
7482         else if (IS_GEN6(dev_priv))
7483                 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7484         else if (IS_GEN5(dev_priv))
7485                 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7486         else if (IS_G4X(dev_priv))
7487                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7488         else if (IS_CRESTLINE(dev_priv))
7489                 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7490         else if (IS_BROADWATER(dev_priv))
7491                 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7492         else if (IS_GEN3(dev_priv))
7493                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7494         else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
7495                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7496         else if (IS_GEN2(dev_priv))
7497                 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7498         else {
7499                 MISSING_CASE(INTEL_DEVID(dev_priv));
7500                 dev_priv->display.init_clock_gating = nop_init_clock_gating;
7501         }
7502 }
7503
7504 /* Set up chip specific power management-related functions */
7505 void intel_init_pm(struct drm_device *dev)
7506 {
7507         struct drm_i915_private *dev_priv = dev->dev_private;
7508
7509         intel_fbc_init(dev_priv);
7510
7511         /* For cxsr */
7512         if (IS_PINEVIEW(dev))
7513                 i915_pineview_get_mem_freq(dev);
7514         else if (IS_GEN5(dev))
7515                 i915_ironlake_get_mem_freq(dev);
7516
7517         /* For FIFO watermark updates */
7518         if (INTEL_INFO(dev)->gen >= 9) {
7519                 skl_setup_wm_latency(dev);
7520                 dev_priv->display.update_wm = skl_update_wm;
7521                 dev_priv->display.compute_global_watermarks = skl_compute_wm;
7522         } else if (HAS_PCH_SPLIT(dev)) {
7523                 ilk_setup_wm_latency(dev);
7524
7525                 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
7526                      dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7527                     (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
7528                      dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
7529                         dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
7530                         dev_priv->display.compute_intermediate_wm =
7531                                 ilk_compute_intermediate_wm;
7532                         dev_priv->display.initial_watermarks =
7533                                 ilk_initial_watermarks;
7534                         dev_priv->display.optimize_watermarks =
7535                                 ilk_optimize_watermarks;
7536                 } else {
7537                         DRM_DEBUG_KMS("Failed to read display plane latency. "
7538                                       "Disable CxSR\n");
7539                 }
7540         } else if (IS_CHERRYVIEW(dev)) {
7541                 vlv_setup_wm_latency(dev);
7542                 dev_priv->display.update_wm = vlv_update_wm;
7543         } else if (IS_VALLEYVIEW(dev)) {
7544                 vlv_setup_wm_latency(dev);
7545                 dev_priv->display.update_wm = vlv_update_wm;
7546         } else if (IS_PINEVIEW(dev)) {
7547                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7548                                             dev_priv->is_ddr3,
7549                                             dev_priv->fsb_freq,
7550                                             dev_priv->mem_freq)) {
7551                         DRM_INFO("failed to find known CxSR latency "
7552                                  "(found ddr%s fsb freq %d, mem freq %d), "
7553                                  "disabling CxSR\n",
7554                                  (dev_priv->is_ddr3 == 1) ? "3" : "2",
7555                                  dev_priv->fsb_freq, dev_priv->mem_freq);
7556                         /* Disable CxSR and never update its watermark again */
7557                         intel_set_memory_cxsr(dev_priv, false);
7558                         dev_priv->display.update_wm = NULL;
7559                 } else
7560                         dev_priv->display.update_wm = pineview_update_wm;
7561         } else if (IS_G4X(dev)) {
7562                 dev_priv->display.update_wm = g4x_update_wm;
7563         } else if (IS_GEN4(dev)) {
7564                 dev_priv->display.update_wm = i965_update_wm;
7565         } else if (IS_GEN3(dev)) {
7566                 dev_priv->display.update_wm = i9xx_update_wm;
7567                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7568         } else if (IS_GEN2(dev)) {
7569                 if (INTEL_INFO(dev)->num_pipes == 1) {
7570                         dev_priv->display.update_wm = i845_update_wm;
7571                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
7572                 } else {
7573                         dev_priv->display.update_wm = i9xx_update_wm;
7574                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
7575                 }
7576         } else {
7577                 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
7578         }
7579 }
7580
7581 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
7582 {
7583         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7584
7585         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7586                 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7587                 return -EAGAIN;
7588         }
7589
7590         I915_WRITE(GEN6_PCODE_DATA, *val);
7591         I915_WRITE(GEN6_PCODE_DATA1, 0);
7592         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7593
7594         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7595                      500)) {
7596                 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7597                 return -ETIMEDOUT;
7598         }
7599
7600         *val = I915_READ(GEN6_PCODE_DATA);
7601         I915_WRITE(GEN6_PCODE_DATA, 0);
7602
7603         return 0;
7604 }
7605
7606 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val)
7607 {
7608         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7609
7610         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7611                 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7612                 return -EAGAIN;
7613         }
7614
7615         I915_WRITE(GEN6_PCODE_DATA, val);
7616         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7617
7618         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7619                      500)) {
7620                 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7621                 return -ETIMEDOUT;
7622         }
7623
7624         I915_WRITE(GEN6_PCODE_DATA, 0);
7625
7626         return 0;
7627 }
7628
7629 static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7630 {
7631         /*
7632          * N = val - 0xb7
7633          * Slow = Fast = GPLL ref * N
7634          */
7635         return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * (val - 0xb7), 1000);
7636 }
7637
7638 static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
7639 {
7640         return DIV_ROUND_CLOSEST(1000 * val, dev_priv->rps.gpll_ref_freq) + 0xb7;
7641 }
7642
7643 static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
7644 {
7645         /*
7646          * N = val / 2
7647          * CU (slow) = CU2x (fast) / 2 = GPLL ref * N / 2
7648          */
7649         return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * val, 2 * 2 * 1000);
7650 }
7651
7652 static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
7653 {
7654         /* CHV needs even values */
7655         return DIV_ROUND_CLOSEST(2 * 1000 * val, dev_priv->rps.gpll_ref_freq) * 2;
7656 }
7657
7658 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
7659 {
7660         if (IS_GEN9(dev_priv))
7661                 return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
7662                                          GEN9_FREQ_SCALER);
7663         else if (IS_CHERRYVIEW(dev_priv))
7664                 return chv_gpu_freq(dev_priv, val);
7665         else if (IS_VALLEYVIEW(dev_priv))
7666                 return byt_gpu_freq(dev_priv, val);
7667         else
7668                 return val * GT_FREQUENCY_MULTIPLIER;
7669 }
7670
7671 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
7672 {
7673         if (IS_GEN9(dev_priv))
7674                 return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
7675                                          GT_FREQUENCY_MULTIPLIER);
7676         else if (IS_CHERRYVIEW(dev_priv))
7677                 return chv_freq_opcode(dev_priv, val);
7678         else if (IS_VALLEYVIEW(dev_priv))
7679                 return byt_freq_opcode(dev_priv, val);
7680         else
7681                 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
7682 }
7683
7684 struct request_boost {
7685         struct work_struct work;
7686         struct drm_i915_gem_request *req;
7687 };
7688
7689 static void __intel_rps_boost_work(struct work_struct *work)
7690 {
7691         struct request_boost *boost = container_of(work, struct request_boost, work);
7692         struct drm_i915_gem_request *req = boost->req;
7693
7694         if (!i915_gem_request_completed(req, true))
7695                 gen6_rps_boost(req->i915, NULL, req->emitted_jiffies);
7696
7697         i915_gem_request_unreference(req);
7698         kfree(boost);
7699 }
7700
7701 void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req)
7702 {
7703         struct request_boost *boost;
7704
7705         if (req == NULL || INTEL_GEN(req->i915) < 6)
7706                 return;
7707
7708         if (i915_gem_request_completed(req, true))
7709                 return;
7710
7711         boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
7712         if (boost == NULL)
7713                 return;
7714
7715         i915_gem_request_reference(req);
7716         boost->req = req;
7717
7718         INIT_WORK(&boost->work, __intel_rps_boost_work);
7719         queue_work(req->i915->wq, &boost->work);
7720 }
7721
7722 void intel_pm_setup(struct drm_device *dev)
7723 {
7724         struct drm_i915_private *dev_priv = dev->dev_private;
7725
7726         mutex_init(&dev_priv->rps.hw_lock);
7727         spin_lock_init(&dev_priv->rps.client_lock);
7728
7729         INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
7730                           intel_gen6_powersave_work);
7731         INIT_LIST_HEAD(&dev_priv->rps.clients);
7732         INIT_LIST_HEAD(&dev_priv->rps.semaphores.link);
7733         INIT_LIST_HEAD(&dev_priv->rps.mmioflips.link);
7734
7735         dev_priv->pm.suspended = false;
7736         atomic_set(&dev_priv->pm.wakeref_count, 0);
7737         atomic_set(&dev_priv->pm.atomic_seq, 0);
7738 }