drivers/gpu/drm/i915/intel_pm.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <linux/cpufreq.h>
  29 #include <drm/drm_plane_helper.h>
  30 #include "i915_drv.h"
  31 #include "intel_drv.h"
  32 #include "../../../platform/x86/intel_ips.h"
  33 #include <linux/module.h>
  34
  35 /**
  36  * DOC: RC6
  37  *
  38  * RC6 is a special power stage which allows the GPU to enter an very
  39  * low-voltage mode when idle, using down to 0V while at this stage.  This
  40  * stage is entered automatically when the GPU is idle when RC6 support is
  41  * enabled, and as soon as new workload arises GPU wakes up automatically as well.
  42  *
  43  * There are different RC6 modes available in Intel GPU, which differentiate
  44  * among each other with the latency required to enter and leave RC6 and
  45  * voltage consumed by the GPU in different states.
  46  *
  47  * The combination of the following flags define which states GPU is allowed
  48  * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
  49  * RC6pp is deepest RC6. Their support by hardware varies according to the
  50  * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
  51  * which brings the most power savings; deeper states save more power, but
  52  * require higher latency to switch to and wake up.
  53  */
  54 #define INTEL_RC6_ENABLE                        (1<<0)
  55 #define INTEL_RC6p_ENABLE                       (1<<1)
  56 #define INTEL_RC6pp_ENABLE                      (1<<2)
  57
  58 static void gen9_init_clock_gating(struct drm_device *dev)
  59 {
  60         struct drm_i915_private *dev_priv = dev->dev_private;
  61
  62         /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl */
  63         I915_WRITE(CHICKEN_PAR1_1,
  64                    I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
  65
  66         I915_WRITE(GEN8_CONFIG0,
  67                    I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES);
  68
  69         /* WaEnableChickenDCPR:skl,bxt,kbl */
  70         I915_WRITE(GEN8_CHICKEN_DCPR_1,
  71                    I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
  72
  73         /* WaFbcTurnOffFbcWatermark:skl,bxt,kbl */
  74         /* WaFbcWakeMemOn:skl,bxt,kbl */
  75         I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
  76                    DISP_FBC_WM_DIS |
  77                    DISP_FBC_MEMORY_WAKE);
  78
  79         /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl */
  80         I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
  81                    ILK_DPFC_DISABLE_DUMMY0);
  82 }
  83
  84 static void bxt_init_clock_gating(struct drm_device *dev)
  85 {
  86         struct drm_i915_private *dev_priv = to_i915(dev);
  87
  88         gen9_init_clock_gating(dev);
  89
  90         /* WaDisableSDEUnitClockGating:bxt */
  91         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
  92                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
  93
  94         /*
  95          * FIXME:
  96          * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
  97          */
  98         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
  99                    GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
 100
 101         /*
 102          * Wa: Backlight PWM may stop in the asserted state, causing backlight
 103          * to stay fully on.
 104          */
 105         if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
 106                 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
 107                            PWM1_GATING_DIS | PWM2_GATING_DIS);
 108 }
 109
 110 static void i915_pineview_get_mem_freq(struct drm_device *dev)
 111 {
 112         struct drm_i915_private *dev_priv = to_i915(dev);
 113         u32 tmp;
 114
 115         tmp = I915_READ(CLKCFG);
 116
 117         switch (tmp & CLKCFG_FSB_MASK) {
 118         case CLKCFG_FSB_533:
 119                 dev_priv->fsb_freq = 533; /* 133*4 */
 120                 break;
 121         case CLKCFG_FSB_800:
 122                 dev_priv->fsb_freq = 800; /* 200*4 */
 123                 break;
 124         case CLKCFG_FSB_667:
 125                 dev_priv->fsb_freq =  667; /* 167*4 */
 126                 break;
 127         case CLKCFG_FSB_400:
 128                 dev_priv->fsb_freq = 400; /* 100*4 */
 129                 break;
 130         }
 131
 132         switch (tmp & CLKCFG_MEM_MASK) {
 133         case CLKCFG_MEM_533:
 134                 dev_priv->mem_freq = 533;
 135                 break;
 136         case CLKCFG_MEM_667:
 137                 dev_priv->mem_freq = 667;
 138                 break;
 139         case CLKCFG_MEM_800:
 140                 dev_priv->mem_freq = 800;
 141                 break;
 142         }
 143
 144         /* detect pineview DDR3 setting */
 145         tmp = I915_READ(CSHRDDR3CTL);
 146         dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
 147 }
 148
 149 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
 150 {
 151         struct drm_i915_private *dev_priv = to_i915(dev);
 152         u16 ddrpll, csipll;
 153
 154         ddrpll = I915_READ16(DDRMPLL1);
 155         csipll = I915_READ16(CSIPLL0);
 156
 157         switch (ddrpll & 0xff) {
 158         case 0xc:
 159                 dev_priv->mem_freq = 800;
 160                 break;
 161         case 0x10:
 162                 dev_priv->mem_freq = 1066;
 163                 break;
 164         case 0x14:
 165                 dev_priv->mem_freq = 1333;
 166                 break;
 167         case 0x18:
 168                 dev_priv->mem_freq = 1600;
 169                 break;
 170         default:
 171                 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
 172                                  ddrpll & 0xff);
 173                 dev_priv->mem_freq = 0;
 174                 break;
 175         }
 176
 177         dev_priv->ips.r_t = dev_priv->mem_freq;
 178
 179         switch (csipll & 0x3ff) {
 180         case 0x00c:
 181                 dev_priv->fsb_freq = 3200;
 182                 break;
 183         case 0x00e:
 184                 dev_priv->fsb_freq = 3733;
 185                 break;
 186         case 0x010:
 187                 dev_priv->fsb_freq = 4266;
 188                 break;
 189         case 0x012:
 190                 dev_priv->fsb_freq = 4800;
 191                 break;
 192         case 0x014:
 193                 dev_priv->fsb_freq = 5333;
 194                 break;
 195         case 0x016:
 196                 dev_priv->fsb_freq = 5866;
 197                 break;
 198         case 0x018:
 199                 dev_priv->fsb_freq = 6400;
 200                 break;
 201         default:
 202                 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
 203                                  csipll & 0x3ff);
 204                 dev_priv->fsb_freq = 0;
 205                 break;
 206         }
 207
 208         if (dev_priv->fsb_freq == 3200) {
 209                 dev_priv->ips.c_m = 0;
 210         } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
 211                 dev_priv->ips.c_m = 1;
 212         } else {
 213                 dev_priv->ips.c_m = 2;
 214         }
 215 }
 216
 217 static const struct cxsr_latency cxsr_latency_table[] = {
 218         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
 219         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
 220         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
 221         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
 222         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
 223
 224         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
 225         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
 226         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
 227         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
 228         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
 229
 230         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
 231         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
 232         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
 233         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
 234         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
 235
 236         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
 237         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
 238         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
 239         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
 240         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
 241
 242         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
 243         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
 244         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
 245         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
 246         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
 247
 248         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
 249         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
 250         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
 251         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
 252         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
 253 };
 254
 255 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
 256                                                          int is_ddr3,
 257                                                          int fsb,
 258                                                          int mem)
 259 {
 260         const struct cxsr_latency *latency;
 261         int i;
 262
 263         if (fsb == 0 || mem == 0)
 264                 return NULL;
 265
 266         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
 267                 latency = &cxsr_latency_table[i];
 268                 if (is_desktop == latency->is_desktop &&
 269                     is_ddr3 == latency->is_ddr3 &&
 270                     fsb == latency->fsb_freq && mem == latency->mem_freq)
 271                         return latency;
 272         }
 273
 274         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 275
 276         return NULL;
 277 }
 278
 279 static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
 280 {
 281         u32 val;
 282
 283         mutex_lock(&dev_priv->rps.hw_lock);
 284
 285         val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
 286         if (enable)
 287                 val &= ~FORCE_DDR_HIGH_FREQ;
 288         else
 289                 val |= FORCE_DDR_HIGH_FREQ;
 290         val &= ~FORCE_DDR_LOW_FREQ;
 291         val |= FORCE_DDR_FREQ_REQ_ACK;
 292         vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
 293
 294         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
 295                       FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
 296                 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
 297
 298         mutex_unlock(&dev_priv->rps.hw_lock);
 299 }
 300
 301 static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
 302 {
 303         u32 val;
 304
 305         mutex_lock(&dev_priv->rps.hw_lock);
 306
 307         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
 308         if (enable)
 309                 val |= DSP_MAXFIFO_PM5_ENABLE;
 310         else
 311                 val &= ~DSP_MAXFIFO_PM5_ENABLE;
 312         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
 313
 314         mutex_unlock(&dev_priv->rps.hw_lock);
 315 }
 316
 317 #define FW_WM(value, plane) \
 318         (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
 319
 320 void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
 321 {
 322         struct drm_device *dev = &dev_priv->drm;
 323         u32 val;
 324
 325         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 326                 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
 327                 POSTING_READ(FW_BLC_SELF_VLV);
 328                 dev_priv->wm.vlv.cxsr = enable;
 329         } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
 330                 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
 331                 POSTING_READ(FW_BLC_SELF);
 332         } else if (IS_PINEVIEW(dev)) {
 333                 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
 334                 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
 335                 I915_WRITE(DSPFW3, val);
 336                 POSTING_READ(DSPFW3);
 337         } else if (IS_I945G(dev) || IS_I945GM(dev)) {
 338                 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
 339                                _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
 340                 I915_WRITE(FW_BLC_SELF, val);
 341                 POSTING_READ(FW_BLC_SELF);
 342         } else if (IS_I915GM(dev)) {
 343                 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
 344                                _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
 345                 I915_WRITE(INSTPM, val);
 346                 POSTING_READ(INSTPM);
 347         } else {
 348                 return;
 349         }
 350
 351         DRM_DEBUG_KMS("memory self-refresh is %s\n",
 352                       enable ? "enabled" : "disabled");
 353 }
 354
 355
 356 /*
 357  * Latency for FIFO fetches is dependent on several factors:
 358  *   - memory configuration (speed, channels)
 359  *   - chipset
 360  *   - current MCH state
 361  * It can be fairly high in some situations, so here we assume a fairly
 362  * pessimal value.  It's a tradeoff between extra memory fetches (if we
 363  * set this value too high, the FIFO will fetch frequently to stay full)
 364  * and power consumption (set it too low to save power and we might see
 365  * FIFO underruns and display "flicker").
 366  *
 367  * A value of 5us seems to be a good balance; safe for very low end
 368  * platforms but not overly aggressive on lower latency configs.
 369  */
 370 static const int pessimal_latency_ns = 5000;
 371
 372 #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
 373         ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
 374
 375 static int vlv_get_fifo_size(struct drm_device *dev,
 376                               enum pipe pipe, int plane)
 377 {
 378         struct drm_i915_private *dev_priv = to_i915(dev);
 379         int sprite0_start, sprite1_start, size;
 380
 381         switch (pipe) {
 382                 uint32_t dsparb, dsparb2, dsparb3;
 383         case PIPE_A:
 384                 dsparb = I915_READ(DSPARB);
 385                 dsparb2 = I915_READ(DSPARB2);
 386                 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
 387                 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
 388                 break;
 389         case PIPE_B:
 390                 dsparb = I915_READ(DSPARB);
 391                 dsparb2 = I915_READ(DSPARB2);
 392                 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
 393                 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
 394                 break;
 395         case PIPE_C:
 396                 dsparb2 = I915_READ(DSPARB2);
 397                 dsparb3 = I915_READ(DSPARB3);
 398                 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
 399                 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
 400                 break;
 401         default:
 402                 return 0;
 403         }
 404
 405         switch (plane) {
 406         case 0:
 407                 size = sprite0_start;
 408                 break;
 409         case 1:
 410                 size = sprite1_start - sprite0_start;
 411                 break;
 412         case 2:
 413                 size = 512 - 1 - sprite1_start;
 414                 break;
 415         default:
 416                 return 0;
 417         }
 418
 419         DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
 420                       pipe_name(pipe), plane == 0 ? "primary" : "sprite",
 421                       plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
 422                       size);
 423
 424         return size;
 425 }
 426
 427 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
 428 {
 429         struct drm_i915_private *dev_priv = to_i915(dev);
 430         uint32_t dsparb = I915_READ(DSPARB);
 431         int size;
 432
 433         size = dsparb & 0x7f;
 434         if (plane)
 435                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
 436
 437         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 438                       plane ? "B" : "A", size);
 439
 440         return size;
 441 }
 442
 443 static int i830_get_fifo_size(struct drm_device *dev, int plane)
 444 {
 445         struct drm_i915_private *dev_priv = to_i915(dev);
 446         uint32_t dsparb = I915_READ(DSPARB);
 447         int size;
 448
 449         size = dsparb & 0x1ff;
 450         if (plane)
 451                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
 452         size >>= 1; /* Convert to cachelines */
 453
 454         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 455                       plane ? "B" : "A", size);
 456
 457         return size;
 458 }
 459
 460 static int i845_get_fifo_size(struct drm_device *dev, int plane)
 461 {
 462         struct drm_i915_private *dev_priv = to_i915(dev);
 463         uint32_t dsparb = I915_READ(DSPARB);
 464         int size;
 465
 466         size = dsparb & 0x7f;
 467         size >>= 2; /* Convert to cachelines */
 468
 469         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 470                       plane ? "B" : "A",
 471                       size);
 472
 473         return size;
 474 }
 475
 476 /* Pineview has different values for various configs */
 477 static const struct intel_watermark_params pineview_display_wm = {
 478         .fifo_size = PINEVIEW_DISPLAY_FIFO,
 479         .max_wm = PINEVIEW_MAX_WM,
 480         .default_wm = PINEVIEW_DFT_WM,
 481         .guard_size = PINEVIEW_GUARD_WM,
 482         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 483 };
 484 static const struct intel_watermark_params pineview_display_hplloff_wm = {
 485         .fifo_size = PINEVIEW_DISPLAY_FIFO,
 486         .max_wm = PINEVIEW_MAX_WM,
 487         .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
 488         .guard_size = PINEVIEW_GUARD_WM,
 489         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 490 };
 491 static const struct intel_watermark_params pineview_cursor_wm = {
 492         .fifo_size = PINEVIEW_CURSOR_FIFO,
 493         .max_wm = PINEVIEW_CURSOR_MAX_WM,
 494         .default_wm = PINEVIEW_CURSOR_DFT_WM,
 495         .guard_size = PINEVIEW_CURSOR_GUARD_WM,
 496         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 497 };
 498 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
 499         .fifo_size = PINEVIEW_CURSOR_FIFO,
 500         .max_wm = PINEVIEW_CURSOR_MAX_WM,
 501         .default_wm = PINEVIEW_CURSOR_DFT_WM,
 502         .guard_size = PINEVIEW_CURSOR_GUARD_WM,
 503         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 504 };
 505 static const struct intel_watermark_params g4x_wm_info = {
 506         .fifo_size = G4X_FIFO_SIZE,
 507         .max_wm = G4X_MAX_WM,
 508         .default_wm = G4X_MAX_WM,
 509         .guard_size = 2,
 510         .cacheline_size = G4X_FIFO_LINE_SIZE,
 511 };
 512 static const struct intel_watermark_params g4x_cursor_wm_info = {
 513         .fifo_size = I965_CURSOR_FIFO,
 514         .max_wm = I965_CURSOR_MAX_WM,
 515         .default_wm = I965_CURSOR_DFT_WM,
 516         .guard_size = 2,
 517         .cacheline_size = G4X_FIFO_LINE_SIZE,
 518 };
 519 static const struct intel_watermark_params i965_cursor_wm_info = {
 520         .fifo_size = I965_CURSOR_FIFO,
 521         .max_wm = I965_CURSOR_MAX_WM,
 522         .default_wm = I965_CURSOR_DFT_WM,
 523         .guard_size = 2,
 524         .cacheline_size = I915_FIFO_LINE_SIZE,
 525 };
 526 static const struct intel_watermark_params i945_wm_info = {
 527         .fifo_size = I945_FIFO_SIZE,
 528         .max_wm = I915_MAX_WM,
 529         .default_wm = 1,
 530         .guard_size = 2,
 531         .cacheline_size = I915_FIFO_LINE_SIZE,
 532 };
 533 static const struct intel_watermark_params i915_wm_info = {
 534         .fifo_size = I915_FIFO_SIZE,
 535         .max_wm = I915_MAX_WM,
 536         .default_wm = 1,
 537         .guard_size = 2,
 538         .cacheline_size = I915_FIFO_LINE_SIZE,
 539 };
 540 static const struct intel_watermark_params i830_a_wm_info = {
 541         .fifo_size = I855GM_FIFO_SIZE,
 542         .max_wm = I915_MAX_WM,
 543         .default_wm = 1,
 544         .guard_size = 2,
 545         .cacheline_size = I830_FIFO_LINE_SIZE,
 546 };
 547 static const struct intel_watermark_params i830_bc_wm_info = {
 548         .fifo_size = I855GM_FIFO_SIZE,
 549         .max_wm = I915_MAX_WM/2,
 550         .default_wm = 1,
 551         .guard_size = 2,
 552         .cacheline_size = I830_FIFO_LINE_SIZE,
 553 };
 554 static const struct intel_watermark_params i845_wm_info = {
 555         .fifo_size = I830_FIFO_SIZE,
 556         .max_wm = I915_MAX_WM,
 557         .default_wm = 1,
 558         .guard_size = 2,
 559         .cacheline_size = I830_FIFO_LINE_SIZE,
 560 };
 561
 562 /**
 563  * intel_calculate_wm - calculate watermark level
 564  * @clock_in_khz: pixel clock
 565  * @wm: chip FIFO params
 566  * @cpp: bytes per pixel
 567  * @latency_ns: memory latency for the platform
 568  *
 569  * Calculate the watermark level (the level at which the display plane will
 570  * start fetching from memory again).  Each chip has a different display
 571  * FIFO size and allocation, so the caller needs to figure that out and pass
 572  * in the correct intel_watermark_params structure.
 573  *
 574  * As the pixel clock runs, the FIFO will be drained at a rate that depends
 575  * on the pixel size.  When it reaches the watermark level, it'll start
 576  * fetching FIFO line sized based chunks from memory until the FIFO fills
 577  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
 578  * will occur, and a display engine hang could result.
 579  */
 580 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
 581                                         const struct intel_watermark_params *wm,
 582                                         int fifo_size, int cpp,
 583                                         unsigned long latency_ns)
 584 {
 585         long entries_required, wm_size;
 586
 587         /*
 588          * Note: we need to make sure we don't overflow for various clock &
 589          * latency values.
 590          * clocks go from a few thousand to several hundred thousand.
 591          * latency is usually a few thousand
 592          */
 593         entries_required = ((clock_in_khz / 1000) * cpp * latency_ns) /
 594                 1000;
 595         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
 596
 597         DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
 598
 599         wm_size = fifo_size - (entries_required + wm->guard_size);
 600
 601         DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
 602
 603         /* Don't promote wm_size to unsigned... */
 604         if (wm_size > (long)wm->max_wm)
 605                 wm_size = wm->max_wm;
 606         if (wm_size <= 0)
 607                 wm_size = wm->default_wm;
 608
 609         /*
 610          * Bspec seems to indicate that the value shouldn't be lower than
 611          * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
 612          * Lets go for 8 which is the burst size since certain platforms
 613          * already use a hardcoded 8 (which is what the spec says should be
 614          * done).
 615          */
 616         if (wm_size <= 8)
 617                 wm_size = 8;
 618
 619         return wm_size;
 620 }
 621
 622 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
 623 {
 624         struct drm_crtc *crtc, *enabled = NULL;
 625
 626         for_each_crtc(dev, crtc) {
 627                 if (intel_crtc_active(crtc)) {
 628                         if (enabled)
 629                                 return NULL;
 630                         enabled = crtc;
 631                 }
 632         }
 633
 634         return enabled;
 635 }
 636
 637 static void pineview_update_wm(struct drm_crtc *unused_crtc)
 638 {
 639         struct drm_device *dev = unused_crtc->dev;
 640         struct drm_i915_private *dev_priv = to_i915(dev);
 641         struct drm_crtc *crtc;
 642         const struct cxsr_latency *latency;
 643         u32 reg;
 644         unsigned long wm;
 645
 646         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
 647                                          dev_priv->fsb_freq, dev_priv->mem_freq);
 648         if (!latency) {
 649                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 650                 intel_set_memory_cxsr(dev_priv, false);
 651                 return;
 652         }
 653
 654         crtc = single_enabled_crtc(dev);
 655         if (crtc) {
 656                 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
 657                 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
 658                 int clock = adjusted_mode->crtc_clock;
 659
 660                 /* Display SR */
 661                 wm = intel_calculate_wm(clock, &pineview_display_wm,
 662                                         pineview_display_wm.fifo_size,
 663                                         cpp, latency->display_sr);
 664                 reg = I915_READ(DSPFW1);
 665                 reg &= ~DSPFW_SR_MASK;
 666                 reg |= FW_WM(wm, SR);
 667                 I915_WRITE(DSPFW1, reg);
 668                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
 669
 670                 /* cursor SR */
 671                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
 672                                         pineview_display_wm.fifo_size,
 673                                         cpp, latency->cursor_sr);
 674                 reg = I915_READ(DSPFW3);
 675                 reg &= ~DSPFW_CURSOR_SR_MASK;
 676                 reg |= FW_WM(wm, CURSOR_SR);
 677                 I915_WRITE(DSPFW3, reg);
 678
 679                 /* Display HPLL off SR */
 680                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
 681                                         pineview_display_hplloff_wm.fifo_size,
 682                                         cpp, latency->display_hpll_disable);
 683                 reg = I915_READ(DSPFW3);
 684                 reg &= ~DSPFW_HPLL_SR_MASK;
 685                 reg |= FW_WM(wm, HPLL_SR);
 686                 I915_WRITE(DSPFW3, reg);
 687
 688                 /* cursor HPLL off SR */
 689                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
 690                                         pineview_display_hplloff_wm.fifo_size,
 691                                         cpp, latency->cursor_hpll_disable);
 692                 reg = I915_READ(DSPFW3);
 693                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
 694                 reg |= FW_WM(wm, HPLL_CURSOR);
 695                 I915_WRITE(DSPFW3, reg);
 696                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
 697
 698                 intel_set_memory_cxsr(dev_priv, true);
 699         } else {
 700                 intel_set_memory_cxsr(dev_priv, false);
 701         }
 702 }
 703
 704 static bool g4x_compute_wm0(struct drm_device *dev,
 705                             int plane,
 706                             const struct intel_watermark_params *display,
 707                             int display_latency_ns,
 708                             const struct intel_watermark_params *cursor,
 709                             int cursor_latency_ns,
 710                             int *plane_wm,
 711                             int *cursor_wm)
 712 {
 713         struct drm_crtc *crtc;
 714         const struct drm_display_mode *adjusted_mode;
 715         int htotal, hdisplay, clock, cpp;
 716         int line_time_us, line_count;
 717         int entries, tlb_miss;
 718
 719         crtc = intel_get_crtc_for_plane(dev, plane);
 720         if (!intel_crtc_active(crtc)) {
 721                 *cursor_wm = cursor->guard_size;
 722                 *plane_wm = display->guard_size;
 723                 return false;
 724         }
 725
 726         adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
 727         clock = adjusted_mode->crtc_clock;
 728         htotal = adjusted_mode->crtc_htotal;
 729         hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
 730         cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
 731
 732         /* Use the small buffer method to calculate plane watermark */
 733         entries = ((clock * cpp / 1000) * display_latency_ns) / 1000;
 734         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
 735         if (tlb_miss > 0)
 736                 entries += tlb_miss;
 737         entries = DIV_ROUND_UP(entries, display->cacheline_size);
 738         *plane_wm = entries + display->guard_size;
 739         if (*plane_wm > (int)display->max_wm)
 740                 *plane_wm = display->max_wm;
 741
 742         /* Use the large buffer method to calculate cursor watermark */
 743         line_time_us = max(htotal * 1000 / clock, 1);
 744         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
 745         entries = line_count * crtc->cursor->state->crtc_w * cpp;
 746         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
 747         if (tlb_miss > 0)
 748                 entries += tlb_miss;
 749         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
 750         *cursor_wm = entries + cursor->guard_size;
 751         if (*cursor_wm > (int)cursor->max_wm)
 752                 *cursor_wm = (int)cursor->max_wm;
 753
 754         return true;
 755 }
 756
 757 /*
 758  * Check the wm result.
 759  *
 760  * If any calculated watermark values is larger than the maximum value that
 761  * can be programmed into the associated watermark register, that watermark
 762  * must be disabled.
 763  */
 764 static bool g4x_check_srwm(struct drm_device *dev,
 765                            int display_wm, int cursor_wm,
 766                            const struct intel_watermark_params *display,
 767                            const struct intel_watermark_params *cursor)
 768 {
 769         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
 770                       display_wm, cursor_wm);
 771
 772         if (display_wm > display->max_wm) {
 773                 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
 774                               display_wm, display->max_wm);
 775                 return false;
 776         }
 777
 778         if (cursor_wm > cursor->max_wm) {
 779                 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
 780                               cursor_wm, cursor->max_wm);
 781                 return false;
 782         }
 783
 784         if (!(display_wm || cursor_wm)) {
 785                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
 786                 return false;
 787         }
 788
 789         return true;
 790 }
 791
 792 static bool g4x_compute_srwm(struct drm_device *dev,
 793                              int plane,
 794                              int latency_ns,
 795                              const struct intel_watermark_params *display,
 796                              const struct intel_watermark_params *cursor,
 797                              int *display_wm, int *cursor_wm)
 798 {
 799         struct drm_crtc *crtc;
 800         const struct drm_display_mode *adjusted_mode;
 801         int hdisplay, htotal, cpp, clock;
 802         unsigned long line_time_us;
 803         int line_count, line_size;
 804         int small, large;
 805         int entries;
 806
 807         if (!latency_ns) {
 808                 *display_wm = *cursor_wm = 0;
 809                 return false;
 810         }
 811
 812         crtc = intel_get_crtc_for_plane(dev, plane);
 813         adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
 814         clock = adjusted_mode->crtc_clock;
 815         htotal = adjusted_mode->crtc_htotal;
 816         hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
 817         cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
 818
 819         line_time_us = max(htotal * 1000 / clock, 1);
 820         line_count = (latency_ns / line_time_us + 1000) / 1000;
 821         line_size = hdisplay * cpp;
 822
 823         /* Use the minimum of the small and large buffer method for primary */
 824         small = ((clock * cpp / 1000) * latency_ns) / 1000;
 825         large = line_count * line_size;
 826
 827         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
 828         *display_wm = entries + display->guard_size;
 829
 830         /* calculate the self-refresh watermark for display cursor */
 831         entries = line_count * cpp * crtc->cursor->state->crtc_w;
 832         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
 833         *cursor_wm = entries + cursor->guard_size;
 834
 835         return g4x_check_srwm(dev,
 836                               *display_wm, *cursor_wm,
 837                               display, cursor);
 838 }
 839
 840 #define FW_WM_VLV(value, plane) \
 841         (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
 842
 843 static void vlv_write_wm_values(struct intel_crtc *crtc,
 844                                 const struct vlv_wm_values *wm)
 845 {
 846         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 847         enum pipe pipe = crtc->pipe;
 848
 849         I915_WRITE(VLV_DDL(pipe),
 850                    (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
 851                    (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
 852                    (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
 853                    (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
 854
 855         I915_WRITE(DSPFW1,
 856                    FW_WM(wm->sr.plane, SR) |
 857                    FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
 858                    FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
 859                    FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
 860         I915_WRITE(DSPFW2,
 861                    FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
 862                    FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
 863                    FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
 864         I915_WRITE(DSPFW3,
 865                    FW_WM(wm->sr.cursor, CURSOR_SR));
 866
 867         if (IS_CHERRYVIEW(dev_priv)) {
 868                 I915_WRITE(DSPFW7_CHV,
 869                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
 870                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
 871                 I915_WRITE(DSPFW8_CHV,
 872                            FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
 873                            FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
 874                 I915_WRITE(DSPFW9_CHV,
 875                            FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
 876                            FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
 877                 I915_WRITE(DSPHOWM,
 878                            FW_WM(wm->sr.plane >> 9, SR_HI) |
 879                            FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
 880                            FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
 881                            FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
 882                            FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
 883                            FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
 884                            FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
 885                            FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
 886                            FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
 887                            FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
 888         } else {
 889                 I915_WRITE(DSPFW7,
 890                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
 891                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
 892                 I915_WRITE(DSPHOWM,
 893                            FW_WM(wm->sr.plane >> 9, SR_HI) |
 894                            FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
 895                            FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
 896                            FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
 897                            FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
 898                            FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
 899                            FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
 900         }
 901
 902         /* zero (unused) WM1 watermarks */
 903         I915_WRITE(DSPFW4, 0);
 904         I915_WRITE(DSPFW5, 0);
 905         I915_WRITE(DSPFW6, 0);
 906         I915_WRITE(DSPHOWM1, 0);
 907
 908         POSTING_READ(DSPFW1);
 909 }
 910
 911 #undef FW_WM_VLV
 912
 913 enum vlv_wm_level {
 914         VLV_WM_LEVEL_PM2,
 915         VLV_WM_LEVEL_PM5,
 916         VLV_WM_LEVEL_DDR_DVFS,
 917 };
 918
 919 /* latency must be in 0.1us units. */
 920 static unsigned int vlv_wm_method2(unsigned int pixel_rate,
 921                                    unsigned int pipe_htotal,
 922                                    unsigned int horiz_pixels,
 923                                    unsigned int cpp,
 924                                    unsigned int latency)
 925 {
 926         unsigned int ret;
 927
 928         ret = (latency * pixel_rate) / (pipe_htotal * 10000);
 929         ret = (ret + 1) * horiz_pixels * cpp;
 930         ret = DIV_ROUND_UP(ret, 64);
 931
 932         return ret;
 933 }
 934
 935 static void vlv_setup_wm_latency(struct drm_device *dev)
 936 {
 937         struct drm_i915_private *dev_priv = to_i915(dev);
 938
 939         /* all latencies in usec */
 940         dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
 941
 942         dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
 943
 944         if (IS_CHERRYVIEW(dev_priv)) {
 945                 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
 946                 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
 947
 948                 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
 949         }
 950 }
 951
 952 static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
 953                                      struct intel_crtc *crtc,
 954                                      const struct intel_plane_state *state,
 955                                      int level)
 956 {
 957         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 958         int clock, htotal, cpp, width, wm;
 959
 960         if (dev_priv->wm.pri_latency[level] == 0)
 961                 return USHRT_MAX;
 962
 963         if (!state->visible)
 964                 return 0;
 965
 966         cpp = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
 967         clock = crtc->config->base.adjusted_mode.crtc_clock;
 968         htotal = crtc->config->base.adjusted_mode.crtc_htotal;
 969         width = crtc->config->pipe_src_w;
 970         if (WARN_ON(htotal == 0))
 971                 htotal = 1;
 972
 973         if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
 974                 /*
 975                  * FIXME the formula gives values that are
 976                  * too big for the cursor FIFO, and hence we
 977                  * would never be able to use cursors. For
 978                  * now just hardcode the watermark.
 979                  */
 980                 wm = 63;
 981         } else {
 982                 wm = vlv_wm_method2(clock, htotal, width, cpp,
 983                                     dev_priv->wm.pri_latency[level] * 10);
 984         }
 985
 986         return min_t(int, wm, USHRT_MAX);
 987 }
 988
 989 static void vlv_compute_fifo(struct intel_crtc *crtc)
 990 {
 991         struct drm_device *dev = crtc->base.dev;
 992         struct vlv_wm_state *wm_state = &crtc->wm_state;
 993         struct intel_plane *plane;
 994         unsigned int total_rate = 0;
 995         const int fifo_size = 512 - 1;
 996         int fifo_extra, fifo_left = fifo_size;
 997
 998         for_each_intel_plane_on_crtc(dev, crtc, plane) {
 999                 struct intel_plane_state *state =
1000                         to_intel_plane_state(plane->base.state);
1001
1002                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1003                         continue;
1004
1005                 if (state->visible) {
1006                         wm_state->num_active_planes++;
1007                         total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1008                 }
1009         }
1010
1011         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1012                 struct intel_plane_state *state =
1013                         to_intel_plane_state(plane->base.state);
1014                 unsigned int rate;
1015
1016                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1017                         plane->wm.fifo_size = 63;
1018                         continue;
1019                 }
1020
1021                 if (!state->visible) {
1022                         plane->wm.fifo_size = 0;
1023                         continue;
1024                 }
1025
1026                 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1027                 plane->wm.fifo_size = fifo_size * rate / total_rate;
1028                 fifo_left -= plane->wm.fifo_size;
1029         }
1030
1031         fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1032
1033         /* spread the remainder evenly */
1034         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1035                 int plane_extra;
1036
1037                 if (fifo_left == 0)
1038                         break;
1039
1040                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1041                         continue;
1042
1043                 /* give it all to the first plane if none are active */
1044                 if (plane->wm.fifo_size == 0 &&
1045                     wm_state->num_active_planes)
1046                         continue;
1047
1048                 plane_extra = min(fifo_extra, fifo_left);
1049                 plane->wm.fifo_size += plane_extra;
1050                 fifo_left -= plane_extra;
1051         }
1052
1053         WARN_ON(fifo_left != 0);
1054 }
1055
1056 static void vlv_invert_wms(struct intel_crtc *crtc)
1057 {
1058         struct vlv_wm_state *wm_state = &crtc->wm_state;
1059         int level;
1060
1061         for (level = 0; level < wm_state->num_levels; level++) {
1062                 struct drm_device *dev = crtc->base.dev;
1063                 const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1064                 struct intel_plane *plane;
1065
1066                 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
1067                 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor;
1068
1069                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1070                         switch (plane->base.type) {
1071                                 int sprite;
1072                         case DRM_PLANE_TYPE_CURSOR:
1073                                 wm_state->wm[level].cursor = plane->wm.fifo_size -
1074                                         wm_state->wm[level].cursor;
1075                                 break;
1076                         case DRM_PLANE_TYPE_PRIMARY:
1077                                 wm_state->wm[level].primary = plane->wm.fifo_size -
1078                                         wm_state->wm[level].primary;
1079                                 break;
1080                         case DRM_PLANE_TYPE_OVERLAY:
1081                                 sprite = plane->plane;
1082                                 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size -
1083                                         wm_state->wm[level].sprite[sprite];
1084                                 break;
1085                         }
1086                 }
1087         }
1088 }
1089
1090 static void vlv_compute_wm(struct intel_crtc *crtc)
1091 {
1092         struct drm_device *dev = crtc->base.dev;
1093         struct vlv_wm_state *wm_state = &crtc->wm_state;
1094         struct intel_plane *plane;
1095         int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1096         int level;
1097
1098         memset(wm_state, 0, sizeof(*wm_state));
1099
1100         wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
1101         wm_state->num_levels = to_i915(dev)->wm.max_level + 1;
1102
1103         wm_state->num_active_planes = 0;
1104
1105         vlv_compute_fifo(crtc);
1106
1107         if (wm_state->num_active_planes != 1)
1108                 wm_state->cxsr = false;
1109
1110         if (wm_state->cxsr) {
1111                 for (level = 0; level < wm_state->num_levels; level++) {
1112                         wm_state->sr[level].plane = sr_fifo_size;
1113                         wm_state->sr[level].cursor = 63;
1114                 }
1115         }
1116
1117         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1118                 struct intel_plane_state *state =
1119                         to_intel_plane_state(plane->base.state);
1120
1121                 if (!state->visible)
1122                         continue;
1123
1124                 /* normal watermarks */
1125                 for (level = 0; level < wm_state->num_levels; level++) {
1126                         int wm = vlv_compute_wm_level(plane, crtc, state, level);
1127                         int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511;
1128
1129                         /* hack */
1130                         if (WARN_ON(level == 0 && wm > max_wm))
1131                                 wm = max_wm;
1132
1133                         if (wm > plane->wm.fifo_size)
1134                                 break;
1135
1136                         switch (plane->base.type) {
1137                                 int sprite;
1138                         case DRM_PLANE_TYPE_CURSOR:
1139                                 wm_state->wm[level].cursor = wm;
1140                                 break;
1141                         case DRM_PLANE_TYPE_PRIMARY:
1142                                 wm_state->wm[level].primary = wm;
1143                                 break;
1144                         case DRM_PLANE_TYPE_OVERLAY:
1145                                 sprite = plane->plane;
1146                                 wm_state->wm[level].sprite[sprite] = wm;
1147                                 break;
1148                         }
1149                 }
1150
1151                 wm_state->num_levels = level;
1152
1153                 if (!wm_state->cxsr)
1154                         continue;
1155
1156                 /* maxfifo watermarks */
1157                 switch (plane->base.type) {
1158                         int sprite, level;
1159                 case DRM_PLANE_TYPE_CURSOR:
1160                         for (level = 0; level < wm_state->num_levels; level++)
1161                                 wm_state->sr[level].cursor =
1162                                         wm_state->wm[level].cursor;
1163                         break;
1164                 case DRM_PLANE_TYPE_PRIMARY:
1165                         for (level = 0; level < wm_state->num_levels; level++)
1166                                 wm_state->sr[level].plane =
1167                                         min(wm_state->sr[level].plane,
1168                                             wm_state->wm[level].primary);
1169                         break;
1170                 case DRM_PLANE_TYPE_OVERLAY:
1171                         sprite = plane->plane;
1172                         for (level = 0; level < wm_state->num_levels; level++)
1173                                 wm_state->sr[level].plane =
1174                                         min(wm_state->sr[level].plane,
1175                                             wm_state->wm[level].sprite[sprite]);
1176                         break;
1177                 }
1178         }
1179
1180         /* clear any (partially) filled invalid levels */
1181         for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) {
1182                 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1183                 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1184         }
1185
1186         vlv_invert_wms(crtc);
1187 }
1188
1189 #define VLV_FIFO(plane, value) \
1190         (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1191
1192 static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1193 {
1194         struct drm_device *dev = crtc->base.dev;
1195         struct drm_i915_private *dev_priv = to_i915(dev);
1196         struct intel_plane *plane;
1197         int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1198
1199         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1200                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1201                         WARN_ON(plane->wm.fifo_size != 63);
1202                         continue;
1203                 }
1204
1205                 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
1206                         sprite0_start = plane->wm.fifo_size;
1207                 else if (plane->plane == 0)
1208                         sprite1_start = sprite0_start + plane->wm.fifo_size;
1209                 else
1210                         fifo_size = sprite1_start + plane->wm.fifo_size;
1211         }
1212
1213         WARN_ON(fifo_size != 512 - 1);
1214
1215         DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1216                       pipe_name(crtc->pipe), sprite0_start,
1217                       sprite1_start, fifo_size);
1218
1219         switch (crtc->pipe) {
1220                 uint32_t dsparb, dsparb2, dsparb3;
1221         case PIPE_A:
1222                 dsparb = I915_READ(DSPARB);
1223                 dsparb2 = I915_READ(DSPARB2);
1224
1225                 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1226                             VLV_FIFO(SPRITEB, 0xff));
1227                 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1228                            VLV_FIFO(SPRITEB, sprite1_start));
1229
1230                 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1231                              VLV_FIFO(SPRITEB_HI, 0x1));
1232                 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1233                            VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1234
1235                 I915_WRITE(DSPARB, dsparb);
1236                 I915_WRITE(DSPARB2, dsparb2);
1237                 break;
1238         case PIPE_B:
1239                 dsparb = I915_READ(DSPARB);
1240                 dsparb2 = I915_READ(DSPARB2);
1241
1242                 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1243                             VLV_FIFO(SPRITED, 0xff));
1244                 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1245                            VLV_FIFO(SPRITED, sprite1_start));
1246
1247                 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1248                              VLV_FIFO(SPRITED_HI, 0xff));
1249                 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1250                            VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1251
1252                 I915_WRITE(DSPARB, dsparb);
1253                 I915_WRITE(DSPARB2, dsparb2);
1254                 break;
1255         case PIPE_C:
1256                 dsparb3 = I915_READ(DSPARB3);
1257                 dsparb2 = I915_READ(DSPARB2);
1258
1259                 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1260                              VLV_FIFO(SPRITEF, 0xff));
1261                 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1262                             VLV_FIFO(SPRITEF, sprite1_start));
1263
1264                 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1265                              VLV_FIFO(SPRITEF_HI, 0xff));
1266                 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1267                            VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1268
1269                 I915_WRITE(DSPARB3, dsparb3);
1270                 I915_WRITE(DSPARB2, dsparb2);
1271                 break;
1272         default:
1273                 break;
1274         }
1275 }
1276
1277 #undef VLV_FIFO
1278
1279 static void vlv_merge_wm(struct drm_device *dev,
1280                          struct vlv_wm_values *wm)
1281 {
1282         struct intel_crtc *crtc;
1283         int num_active_crtcs = 0;
1284
1285         wm->level = to_i915(dev)->wm.max_level;
1286         wm->cxsr = true;
1287
1288         for_each_intel_crtc(dev, crtc) {
1289                 const struct vlv_wm_state *wm_state = &crtc->wm_state;
1290
1291                 if (!crtc->active)
1292                         continue;
1293
1294                 if (!wm_state->cxsr)
1295                         wm->cxsr = false;
1296
1297                 num_active_crtcs++;
1298                 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1299         }
1300
1301         if (num_active_crtcs != 1)
1302                 wm->cxsr = false;
1303
1304         if (num_active_crtcs > 1)
1305                 wm->level = VLV_WM_LEVEL_PM2;
1306
1307         for_each_intel_crtc(dev, crtc) {
1308                 struct vlv_wm_state *wm_state = &crtc->wm_state;
1309                 enum pipe pipe = crtc->pipe;
1310
1311                 if (!crtc->active)
1312                         continue;
1313
1314                 wm->pipe[pipe] = wm_state->wm[wm->level];
1315                 if (wm->cxsr)
1316                         wm->sr = wm_state->sr[wm->level];
1317
1318                 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2;
1319                 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2;
1320                 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2;
1321                 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2;
1322         }
1323 }
1324
1325 static void vlv_update_wm(struct drm_crtc *crtc)
1326 {
1327         struct drm_device *dev = crtc->dev;
1328         struct drm_i915_private *dev_priv = to_i915(dev);
1329         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1330         enum pipe pipe = intel_crtc->pipe;
1331         struct vlv_wm_values wm = {};
1332
1333         vlv_compute_wm(intel_crtc);
1334         vlv_merge_wm(dev, &wm);
1335
1336         if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
1337                 /* FIXME should be part of crtc atomic commit */
1338                 vlv_pipe_set_fifo_size(intel_crtc);
1339                 return;
1340         }
1341
1342         if (wm.level < VLV_WM_LEVEL_DDR_DVFS &&
1343             dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS)
1344                 chv_set_memory_dvfs(dev_priv, false);
1345
1346         if (wm.level < VLV_WM_LEVEL_PM5 &&
1347             dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5)
1348                 chv_set_memory_pm5(dev_priv, false);
1349
1350         if (!wm.cxsr && dev_priv->wm.vlv.cxsr)
1351                 intel_set_memory_cxsr(dev_priv, false);
1352
1353         /* FIXME should be part of crtc atomic commit */
1354         vlv_pipe_set_fifo_size(intel_crtc);
1355
1356         vlv_write_wm_values(intel_crtc, &wm);
1357
1358         DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1359                       "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1360                       pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1361                       wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1],
1362                       wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr);
1363
1364         if (wm.cxsr && !dev_priv->wm.vlv.cxsr)
1365                 intel_set_memory_cxsr(dev_priv, true);
1366
1367         if (wm.level >= VLV_WM_LEVEL_PM5 &&
1368             dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5)
1369                 chv_set_memory_pm5(dev_priv, true);
1370
1371         if (wm.level >= VLV_WM_LEVEL_DDR_DVFS &&
1372             dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS)
1373                 chv_set_memory_dvfs(dev_priv, true);
1374
1375         dev_priv->wm.vlv = wm;
1376 }
1377
1378 #define single_plane_enabled(mask) is_power_of_2(mask)
1379
1380 static void g4x_update_wm(struct drm_crtc *crtc)
1381 {
1382         struct drm_device *dev = crtc->dev;
1383         static const int sr_latency_ns = 12000;
1384         struct drm_i915_private *dev_priv = to_i915(dev);
1385         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1386         int plane_sr, cursor_sr;
1387         unsigned int enabled = 0;
1388         bool cxsr_enabled;
1389
1390         if (g4x_compute_wm0(dev, PIPE_A,
1391                             &g4x_wm_info, pessimal_latency_ns,
1392                             &g4x_cursor_wm_info, pessimal_latency_ns,
1393                             &planea_wm, &cursora_wm))
1394                 enabled |= 1 << PIPE_A;
1395
1396         if (g4x_compute_wm0(dev, PIPE_B,
1397                             &g4x_wm_info, pessimal_latency_ns,
1398                             &g4x_cursor_wm_info, pessimal_latency_ns,
1399                             &planeb_wm, &cursorb_wm))
1400                 enabled |= 1 << PIPE_B;
1401
1402         if (single_plane_enabled(enabled) &&
1403             g4x_compute_srwm(dev, ffs(enabled) - 1,
1404                              sr_latency_ns,
1405                              &g4x_wm_info,
1406                              &g4x_cursor_wm_info,
1407                              &plane_sr, &cursor_sr)) {
1408                 cxsr_enabled = true;
1409         } else {
1410                 cxsr_enabled = false;
1411                 intel_set_memory_cxsr(dev_priv, false);
1412                 plane_sr = cursor_sr = 0;
1413         }
1414
1415         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1416                       "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1417                       planea_wm, cursora_wm,
1418                       planeb_wm, cursorb_wm,
1419                       plane_sr, cursor_sr);
1420
1421         I915_WRITE(DSPFW1,
1422                    FW_WM(plane_sr, SR) |
1423                    FW_WM(cursorb_wm, CURSORB) |
1424                    FW_WM(planeb_wm, PLANEB) |
1425                    FW_WM(planea_wm, PLANEA));
1426         I915_WRITE(DSPFW2,
1427                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1428                    FW_WM(cursora_wm, CURSORA));
1429         /* HPLL off in SR has some issues on G4x... disable it */
1430         I915_WRITE(DSPFW3,
1431                    (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1432                    FW_WM(cursor_sr, CURSOR_SR));
1433
1434         if (cxsr_enabled)
1435                 intel_set_memory_cxsr(dev_priv, true);
1436 }
1437
1438 static void i965_update_wm(struct drm_crtc *unused_crtc)
1439 {
1440         struct drm_device *dev = unused_crtc->dev;
1441         struct drm_i915_private *dev_priv = to_i915(dev);
1442         struct drm_crtc *crtc;
1443         int srwm = 1;
1444         int cursor_sr = 16;
1445         bool cxsr_enabled;
1446
1447         /* Calc sr entries for one plane configs */
1448         crtc = single_enabled_crtc(dev);
1449         if (crtc) {
1450                 /* self-refresh has much higher latency */
1451                 static const int sr_latency_ns = 12000;
1452                 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1453                 int clock = adjusted_mode->crtc_clock;
1454                 int htotal = adjusted_mode->crtc_htotal;
1455                 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
1456                 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
1457                 unsigned long line_time_us;
1458                 int entries;
1459
1460                 line_time_us = max(htotal * 1000 / clock, 1);
1461
1462                 /* Use ns/us then divide to preserve precision */
1463                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1464                         cpp * hdisplay;
1465                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1466                 srwm = I965_FIFO_SIZE - entries;
1467                 if (srwm < 0)
1468                         srwm = 1;
1469                 srwm &= 0x1ff;
1470                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1471                               entries, srwm);
1472
1473                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1474                         cpp * crtc->cursor->state->crtc_w;
1475                 entries = DIV_ROUND_UP(entries,
1476                                           i965_cursor_wm_info.cacheline_size);
1477                 cursor_sr = i965_cursor_wm_info.fifo_size -
1478                         (entries + i965_cursor_wm_info.guard_size);
1479
1480                 if (cursor_sr > i965_cursor_wm_info.max_wm)
1481                         cursor_sr = i965_cursor_wm_info.max_wm;
1482
1483                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1484                               "cursor %d\n", srwm, cursor_sr);
1485
1486                 cxsr_enabled = true;
1487         } else {
1488                 cxsr_enabled = false;
1489                 /* Turn off self refresh if both pipes are enabled */
1490                 intel_set_memory_cxsr(dev_priv, false);
1491         }
1492
1493         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1494                       srwm);
1495
1496         /* 965 has limitations... */
1497         I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1498                    FW_WM(8, CURSORB) |
1499                    FW_WM(8, PLANEB) |
1500                    FW_WM(8, PLANEA));
1501         I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1502                    FW_WM(8, PLANEC_OLD));
1503         /* update cursor SR watermark */
1504         I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
1505
1506         if (cxsr_enabled)
1507                 intel_set_memory_cxsr(dev_priv, true);
1508 }
1509
1510 #undef FW_WM
1511
1512 static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1513 {
1514         struct drm_device *dev = unused_crtc->dev;
1515         struct drm_i915_private *dev_priv = to_i915(dev);
1516         const struct intel_watermark_params *wm_info;
1517         uint32_t fwater_lo;
1518         uint32_t fwater_hi;
1519         int cwm, srwm = 1;
1520         int fifo_size;
1521         int planea_wm, planeb_wm;
1522         struct drm_crtc *crtc, *enabled = NULL;
1523
1524         if (IS_I945GM(dev))
1525                 wm_info = &i945_wm_info;
1526         else if (!IS_GEN2(dev))
1527                 wm_info = &i915_wm_info;
1528         else
1529                 wm_info = &i830_a_wm_info;
1530
1531         fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1532         crtc = intel_get_crtc_for_plane(dev, 0);
1533         if (intel_crtc_active(crtc)) {
1534                 const struct drm_display_mode *adjusted_mode;
1535                 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
1536                 if (IS_GEN2(dev))
1537                         cpp = 4;
1538
1539                 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1540                 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1541                                                wm_info, fifo_size, cpp,
1542                                                pessimal_latency_ns);
1543                 enabled = crtc;
1544         } else {
1545                 planea_wm = fifo_size - wm_info->guard_size;
1546                 if (planea_wm > (long)wm_info->max_wm)
1547                         planea_wm = wm_info->max_wm;
1548         }
1549
1550         if (IS_GEN2(dev))
1551                 wm_info = &i830_bc_wm_info;
1552
1553         fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1554         crtc = intel_get_crtc_for_plane(dev, 1);
1555         if (intel_crtc_active(crtc)) {
1556                 const struct drm_display_mode *adjusted_mode;
1557                 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
1558                 if (IS_GEN2(dev))
1559                         cpp = 4;
1560
1561                 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1562                 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1563                                                wm_info, fifo_size, cpp,
1564                                                pessimal_latency_ns);
1565                 if (enabled == NULL)
1566                         enabled = crtc;
1567                 else
1568                         enabled = NULL;
1569         } else {
1570                 planeb_wm = fifo_size - wm_info->guard_size;
1571                 if (planeb_wm > (long)wm_info->max_wm)
1572                         planeb_wm = wm_info->max_wm;
1573         }
1574
1575         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1576
1577         if (IS_I915GM(dev) && enabled) {
1578                 struct drm_i915_gem_object *obj;
1579
1580                 obj = intel_fb_obj(enabled->primary->state->fb);
1581
1582                 /* self-refresh seems busted with untiled */
1583                 if (obj->tiling_mode == I915_TILING_NONE)
1584                         enabled = NULL;
1585         }
1586
1587         /*
1588          * Overlay gets an aggressive default since video jitter is bad.
1589          */
1590         cwm = 2;
1591
1592         /* Play safe and disable self-refresh before adjusting watermarks. */
1593         intel_set_memory_cxsr(dev_priv, false);
1594
1595         /* Calc sr entries for one plane configs */
1596         if (HAS_FW_BLC(dev) && enabled) {
1597                 /* self-refresh has much higher latency */
1598                 static const int sr_latency_ns = 6000;
1599                 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(enabled)->config->base.adjusted_mode;
1600                 int clock = adjusted_mode->crtc_clock;
1601                 int htotal = adjusted_mode->crtc_htotal;
1602                 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
1603                 int cpp = drm_format_plane_cpp(enabled->primary->state->fb->pixel_format, 0);
1604                 unsigned long line_time_us;
1605                 int entries;
1606
1607                 line_time_us = max(htotal * 1000 / clock, 1);
1608
1609                 /* Use ns/us then divide to preserve precision */
1610                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1611                         cpp * hdisplay;
1612                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1613                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1614                 srwm = wm_info->fifo_size - entries;
1615                 if (srwm < 0)
1616                         srwm = 1;
1617
1618                 if (IS_I945G(dev) || IS_I945GM(dev))
1619                         I915_WRITE(FW_BLC_SELF,
1620                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1621                 else if (IS_I915GM(dev))
1622                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1623         }
1624
1625         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1626                       planea_wm, planeb_wm, cwm, srwm);
1627
1628         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1629         fwater_hi = (cwm & 0x1f);
1630
1631         /* Set request length to 8 cachelines per fetch */
1632         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1633         fwater_hi = fwater_hi | (1 << 8);
1634
1635         I915_WRITE(FW_BLC, fwater_lo);
1636         I915_WRITE(FW_BLC2, fwater_hi);
1637
1638         if (enabled)
1639                 intel_set_memory_cxsr(dev_priv, true);
1640 }
1641
1642 static void i845_update_wm(struct drm_crtc *unused_crtc)
1643 {
1644         struct drm_device *dev = unused_crtc->dev;
1645         struct drm_i915_private *dev_priv = to_i915(dev);
1646         struct drm_crtc *crtc;
1647         const struct drm_display_mode *adjusted_mode;
1648         uint32_t fwater_lo;
1649         int planea_wm;
1650
1651         crtc = single_enabled_crtc(dev);
1652         if (crtc == NULL)
1653                 return;
1654
1655         adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1656         planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1657                                        &i845_wm_info,
1658                                        dev_priv->display.get_fifo_size(dev, 0),
1659                                        4, pessimal_latency_ns);
1660         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1661         fwater_lo |= (3<<8) | planea_wm;
1662
1663         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1664
1665         I915_WRITE(FW_BLC, fwater_lo);
1666 }
1667
1668 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
1669 {
1670         uint32_t pixel_rate;
1671
1672         pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
1673
1674         /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1675          * adjust the pixel_rate here. */
1676
1677         if (pipe_config->pch_pfit.enabled) {
1678                 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
1679                 uint32_t pfit_size = pipe_config->pch_pfit.size;
1680
1681                 pipe_w = pipe_config->pipe_src_w;
1682                 pipe_h = pipe_config->pipe_src_h;
1683
1684                 pfit_w = (pfit_size >> 16) & 0xFFFF;
1685                 pfit_h = pfit_size & 0xFFFF;
1686                 if (pipe_w < pfit_w)
1687                         pipe_w = pfit_w;
1688                 if (pipe_h < pfit_h)
1689                         pipe_h = pfit_h;
1690
1691                 if (WARN_ON(!pfit_w || !pfit_h))
1692                         return pixel_rate;
1693
1694                 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1695                                      pfit_w * pfit_h);
1696         }
1697
1698         return pixel_rate;
1699 }
1700
1701 /* latency must be in 0.1us units. */
1702 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
1703 {
1704         uint64_t ret;
1705
1706         if (WARN(latency == 0, "Latency value missing\n"))
1707                 return UINT_MAX;
1708
1709         ret = (uint64_t) pixel_rate * cpp * latency;
1710         ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1711
1712         return ret;
1713 }
1714
1715 /* latency must be in 0.1us units. */
1716 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
1717                                uint32_t horiz_pixels, uint8_t cpp,
1718                                uint32_t latency)
1719 {
1720         uint32_t ret;
1721
1722         if (WARN(latency == 0, "Latency value missing\n"))
1723                 return UINT_MAX;
1724         if (WARN_ON(!pipe_htotal))
1725                 return UINT_MAX;
1726
1727         ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1728         ret = (ret + 1) * horiz_pixels * cpp;
1729         ret = DIV_ROUND_UP(ret, 64) + 2;
1730         return ret;
1731 }
1732
1733 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
1734                            uint8_t cpp)
1735 {
1736         /*
1737          * Neither of these should be possible since this function shouldn't be
1738          * called if the CRTC is off or the plane is invisible.  But let's be
1739          * extra paranoid to avoid a potential divide-by-zero if we screw up
1740          * elsewhere in the driver.
1741          */
1742         if (WARN_ON(!cpp))
1743                 return 0;
1744         if (WARN_ON(!horiz_pixels))
1745                 return 0;
1746
1747         return DIV_ROUND_UP(pri_val * 64, horiz_pixels * cpp) + 2;
1748 }
1749
1750 struct ilk_wm_maximums {
1751         uint16_t pri;
1752         uint16_t spr;
1753         uint16_t cur;
1754         uint16_t fbc;
1755 };
1756
1757 /*
1758  * For both WM_PIPE and WM_LP.
1759  * mem_value must be in 0.1us units.
1760  */
1761 static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
1762                                    const struct intel_plane_state *pstate,
1763                                    uint32_t mem_value,
1764                                    bool is_lp)
1765 {
1766         int cpp = pstate->base.fb ?
1767                 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
1768         uint32_t method1, method2;
1769
1770         if (!cstate->base.active || !pstate->visible)
1771                 return 0;
1772
1773         method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
1774
1775         if (!is_lp)
1776                 return method1;
1777
1778         method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1779                                  cstate->base.adjusted_mode.crtc_htotal,
1780                                  drm_rect_width(&pstate->dst),
1781                                  cpp, mem_value);
1782
1783         return min(method1, method2);
1784 }
1785
1786 /*
1787  * For both WM_PIPE and WM_LP.
1788  * mem_value must be in 0.1us units.
1789  */
1790 static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
1791                                    const struct intel_plane_state *pstate,
1792                                    uint32_t mem_value)
1793 {
1794         int cpp = pstate->base.fb ?
1795                 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
1796         uint32_t method1, method2;
1797
1798         if (!cstate->base.active || !pstate->visible)
1799                 return 0;
1800
1801         method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
1802         method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1803                                  cstate->base.adjusted_mode.crtc_htotal,
1804                                  drm_rect_width(&pstate->dst),
1805                                  cpp, mem_value);
1806         return min(method1, method2);
1807 }
1808
1809 /*
1810  * For both WM_PIPE and WM_LP.
1811  * mem_value must be in 0.1us units.
1812  */
1813 static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
1814                                    const struct intel_plane_state *pstate,
1815                                    uint32_t mem_value)
1816 {
1817         /*
1818          * We treat the cursor plane as always-on for the purposes of watermark
1819          * calculation.  Until we have two-stage watermark programming merged,
1820          * this is necessary to avoid flickering.
1821          */
1822         int cpp = 4;
1823         int width = pstate->visible ? pstate->base.crtc_w : 64;
1824
1825         if (!cstate->base.active)
1826                 return 0;
1827
1828         return ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1829                               cstate->base.adjusted_mode.crtc_htotal,
1830                               width, cpp, mem_value);
1831 }
1832
1833 /* Only for WM_LP. */
1834 static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
1835                                    const struct intel_plane_state *pstate,
1836                                    uint32_t pri_val)
1837 {
1838         int cpp = pstate->base.fb ?
1839                 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
1840
1841         if (!cstate->base.active || !pstate->visible)
1842                 return 0;
1843
1844         return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->dst), cpp);
1845 }
1846
1847 static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1848 {
1849         if (INTEL_INFO(dev)->gen >= 8)
1850                 return 3072;
1851         else if (INTEL_INFO(dev)->gen >= 7)
1852                 return 768;
1853         else
1854                 return 512;
1855 }
1856
1857 static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1858                                          int level, bool is_sprite)
1859 {
1860         if (INTEL_INFO(dev)->gen >= 8)
1861                 /* BDW primary/sprite plane watermarks */
1862                 return level == 0 ? 255 : 2047;
1863         else if (INTEL_INFO(dev)->gen >= 7)
1864                 /* IVB/HSW primary/sprite plane watermarks */
1865                 return level == 0 ? 127 : 1023;
1866         else if (!is_sprite)
1867                 /* ILK/SNB primary plane watermarks */
1868                 return level == 0 ? 127 : 511;
1869         else
1870                 /* ILK/SNB sprite plane watermarks */
1871                 return level == 0 ? 63 : 255;
1872 }
1873
1874 static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1875                                           int level)
1876 {
1877         if (INTEL_INFO(dev)->gen >= 7)
1878                 return level == 0 ? 63 : 255;
1879         else
1880                 return level == 0 ? 31 : 63;
1881 }
1882
1883 static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1884 {
1885         if (INTEL_INFO(dev)->gen >= 8)
1886                 return 31;
1887         else
1888                 return 15;
1889 }
1890
1891 /* Calculate the maximum primary/sprite plane watermark */
1892 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1893                                      int level,
1894                                      const struct intel_wm_config *config,
1895                                      enum intel_ddb_partitioning ddb_partitioning,
1896                                      bool is_sprite)
1897 {
1898         unsigned int fifo_size = ilk_display_fifo_size(dev);
1899
1900         /* if sprites aren't enabled, sprites get nothing */
1901         if (is_sprite && !config->sprites_enabled)
1902                 return 0;
1903
1904         /* HSW allows LP1+ watermarks even with multiple pipes */
1905         if (level == 0 || config->num_pipes_active > 1) {
1906                 fifo_size /= INTEL_INFO(dev)->num_pipes;
1907
1908                 /*
1909                  * For some reason the non self refresh
1910                  * FIFO size is only half of the self
1911                  * refresh FIFO size on ILK/SNB.
1912                  */
1913                 if (INTEL_INFO(dev)->gen <= 6)
1914                         fifo_size /= 2;
1915         }
1916
1917         if (config->sprites_enabled) {
1918                 /* level 0 is always calculated with 1:1 split */
1919                 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1920                         if (is_sprite)
1921                                 fifo_size *= 5;
1922                         fifo_size /= 6;
1923                 } else {
1924                         fifo_size /= 2;
1925                 }
1926         }
1927
1928         /* clamp to max that the registers can hold */
1929         return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
1930 }
1931
1932 /* Calculate the maximum cursor plane watermark */
1933 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
1934                                       int level,
1935                                       const struct intel_wm_config *config)
1936 {
1937         /* HSW LP1+ watermarks w/ multiple pipes */
1938         if (level > 0 && config->num_pipes_active > 1)
1939                 return 64;
1940
1941         /* otherwise just report max that registers can hold */
1942         return ilk_cursor_wm_reg_max(dev, level);
1943 }
1944
1945 static void ilk_compute_wm_maximums(const struct drm_device *dev,
1946                                     int level,
1947                                     const struct intel_wm_config *config,
1948                                     enum intel_ddb_partitioning ddb_partitioning,
1949                                     struct ilk_wm_maximums *max)
1950 {
1951         max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1952         max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1953         max->cur = ilk_cursor_wm_max(dev, level, config);
1954         max->fbc = ilk_fbc_wm_reg_max(dev);
1955 }
1956
1957 static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1958                                         int level,
1959                                         struct ilk_wm_maximums *max)
1960 {
1961         max->pri = ilk_plane_wm_reg_max(dev, level, false);
1962         max->spr = ilk_plane_wm_reg_max(dev, level, true);
1963         max->cur = ilk_cursor_wm_reg_max(dev, level);
1964         max->fbc = ilk_fbc_wm_reg_max(dev);
1965 }
1966
1967 static bool ilk_validate_wm_level(int level,
1968                                   const struct ilk_wm_maximums *max,
1969                                   struct intel_wm_level *result)
1970 {
1971         bool ret;
1972
1973         /* already determined to be invalid? */
1974         if (!result->enable)
1975                 return false;
1976
1977         result->enable = result->pri_val <= max->pri &&
1978                          result->spr_val <= max->spr &&
1979                          result->cur_val <= max->cur;
1980
1981         ret = result->enable;
1982
1983         /*
1984          * HACK until we can pre-compute everything,
1985          * and thus fail gracefully if LP0 watermarks
1986          * are exceeded...
1987          */
1988         if (level == 0 && !result->enable) {
1989                 if (result->pri_val > max->pri)
1990                         DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1991                                       level, result->pri_val, max->pri);
1992                 if (result->spr_val > max->spr)
1993                         DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
1994                                       level, result->spr_val, max->spr);
1995                 if (result->cur_val > max->cur)
1996                         DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
1997                                       level, result->cur_val, max->cur);
1998
1999                 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2000                 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2001                 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2002                 result->enable = true;
2003         }
2004
2005         return ret;
2006 }
2007
2008 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
2009                                  const struct intel_crtc *intel_crtc,
2010                                  int level,
2011                                  struct intel_crtc_state *cstate,
2012                                  struct intel_plane_state *pristate,
2013                                  struct intel_plane_state *sprstate,
2014                                  struct intel_plane_state *curstate,
2015                                  struct intel_wm_level *result)
2016 {
2017         uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2018         uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2019         uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2020
2021         /* WM1+ latency values stored in 0.5us units */
2022         if (level > 0) {
2023                 pri_latency *= 5;
2024                 spr_latency *= 5;
2025                 cur_latency *= 5;
2026         }
2027
2028         if (pristate) {
2029                 result->pri_val = ilk_compute_pri_wm(cstate, pristate,
2030                                                      pri_latency, level);
2031                 result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val);
2032         }
2033
2034         if (sprstate)
2035                 result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency);
2036
2037         if (curstate)
2038                 result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency);
2039
2040         result->enable = true;
2041 }
2042
2043 static uint32_t
2044 hsw_compute_linetime_wm(const struct intel_crtc_state *cstate)
2045 {
2046         const struct intel_atomic_state *intel_state =
2047                 to_intel_atomic_state(cstate->base.state);
2048         const struct drm_display_mode *adjusted_mode =
2049                 &cstate->base.adjusted_mode;
2050         u32 linetime, ips_linetime;
2051
2052         if (!cstate->base.active)
2053                 return 0;
2054         if (WARN_ON(adjusted_mode->crtc_clock == 0))
2055                 return 0;
2056         if (WARN_ON(intel_state->cdclk == 0))
2057                 return 0;
2058
2059         /* The WM are computed with base on how long it takes to fill a single
2060          * row at the given clock rate, multiplied by 8.
2061          * */
2062         linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2063                                      adjusted_mode->crtc_clock);
2064         ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2065                                          intel_state->cdclk);
2066
2067         return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2068                PIPE_WM_LINETIME_TIME(linetime);
2069 }
2070
2071 static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
2072 {
2073         struct drm_i915_private *dev_priv = to_i915(dev);
2074
2075         if (IS_GEN9(dev)) {
2076                 uint32_t val;
2077                 int ret, i;
2078                 int level, max_level = ilk_wm_max_level(dev);
2079
2080                 /* read the first set of memory latencies[0:3] */
2081                 val = 0; /* data0 to be programmed to 0 for first set */
2082                 mutex_lock(&dev_priv->rps.hw_lock);
2083                 ret = sandybridge_pcode_read(dev_priv,
2084                                              GEN9_PCODE_READ_MEM_LATENCY,
2085                                              &val);
2086                 mutex_unlock(&dev_priv->rps.hw_lock);
2087
2088                 if (ret) {
2089                         DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2090                         return;
2091                 }
2092
2093                 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2094                 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2095                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2096                 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2097                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2098                 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2099                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2100
2101                 /* read the second set of memory latencies[4:7] */
2102                 val = 1; /* data0 to be programmed to 1 for second set */
2103                 mutex_lock(&dev_priv->rps.hw_lock);
2104                 ret = sandybridge_pcode_read(dev_priv,
2105                                              GEN9_PCODE_READ_MEM_LATENCY,
2106                                              &val);
2107                 mutex_unlock(&dev_priv->rps.hw_lock);
2108                 if (ret) {
2109                         DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2110                         return;
2111                 }
2112
2113                 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2114                 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2115                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2116                 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2117                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2118                 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2119                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2120
2121                 /*
2122                  * WaWmMemoryReadLatency:skl
2123                  *
2124                  * punit doesn't take into account the read latency so we need
2125                  * to add 2us to the various latency levels we retrieve from
2126                  * the punit.
2127                  *   - W0 is a bit special in that it's the only level that
2128                  *   can't be disabled if we want to have display working, so
2129                  *   we always add 2us there.
2130                  *   - For levels >=1, punit returns 0us latency when they are
2131                  *   disabled, so we respect that and don't add 2us then
2132                  *
2133                  * Additionally, if a level n (n > 1) has a 0us latency, all
2134                  * levels m (m >= n) need to be disabled. We make sure to
2135                  * sanitize the values out of the punit to satisfy this
2136                  * requirement.
2137                  */
2138                 wm[0] += 2;
2139                 for (level = 1; level <= max_level; level++)
2140                         if (wm[level] != 0)
2141                                 wm[level] += 2;
2142                         else {
2143                                 for (i = level + 1; i <= max_level; i++)
2144                                         wm[i] = 0;
2145
2146                                 break;
2147                         }
2148         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2149                 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2150
2151                 wm[0] = (sskpd >> 56) & 0xFF;
2152                 if (wm[0] == 0)
2153                         wm[0] = sskpd & 0xF;
2154                 wm[1] = (sskpd >> 4) & 0xFF;
2155                 wm[2] = (sskpd >> 12) & 0xFF;
2156                 wm[3] = (sskpd >> 20) & 0x1FF;
2157                 wm[4] = (sskpd >> 32) & 0x1FF;
2158         } else if (INTEL_INFO(dev)->gen >= 6) {
2159                 uint32_t sskpd = I915_READ(MCH_SSKPD);
2160
2161                 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2162                 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2163                 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2164                 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2165         } else if (INTEL_INFO(dev)->gen >= 5) {
2166                 uint32_t mltr = I915_READ(MLTR_ILK);
2167
2168                 /* ILK primary LP0 latency is 700 ns */
2169                 wm[0] = 7;
2170                 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2171                 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2172         }
2173 }
2174
2175 static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2176 {
2177         /* ILK sprite LP0 latency is 1300 ns */
2178         if (IS_GEN5(dev))
2179                 wm[0] = 13;
2180 }
2181
2182 static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2183 {
2184         /* ILK cursor LP0 latency is 1300 ns */
2185         if (IS_GEN5(dev))
2186                 wm[0] = 13;
2187
2188         /* WaDoubleCursorLP3Latency:ivb */
2189         if (IS_IVYBRIDGE(dev))
2190                 wm[3] *= 2;
2191 }
2192
2193 int ilk_wm_max_level(const struct drm_device *dev)
2194 {
2195         /* how many WM levels are we expecting */
2196         if (INTEL_INFO(dev)->gen >= 9)
2197                 return 7;
2198         else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2199                 return 4;
2200         else if (INTEL_INFO(dev)->gen >= 6)
2201                 return 3;
2202         else
2203                 return 2;
2204 }
2205
2206 static void intel_print_wm_latency(struct drm_device *dev,
2207                                    const char *name,
2208                                    const uint16_t wm[8])
2209 {
2210         int level, max_level = ilk_wm_max_level(dev);
2211
2212         for (level = 0; level <= max_level; level++) {
2213                 unsigned int latency = wm[level];
2214
2215                 if (latency == 0) {
2216                         DRM_ERROR("%s WM%d latency not provided\n",
2217                                   name, level);
2218                         continue;
2219                 }
2220
2221                 /*
2222                  * - latencies are in us on gen9.
2223                  * - before then, WM1+ latency values are in 0.5us units
2224                  */
2225                 if (IS_GEN9(dev))
2226                         latency *= 10;
2227                 else if (level > 0)
2228                         latency *= 5;
2229
2230                 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2231                               name, level, wm[level],
2232                               latency / 10, latency % 10);
2233         }
2234 }
2235
2236 static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2237                                     uint16_t wm[5], uint16_t min)
2238 {
2239         int level, max_level = ilk_wm_max_level(&dev_priv->drm);
2240
2241         if (wm[0] >= min)
2242                 return false;
2243
2244         wm[0] = max(wm[0], min);
2245         for (level = 1; level <= max_level; level++)
2246                 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2247
2248         return true;
2249 }
2250
2251 static void snb_wm_latency_quirk(struct drm_device *dev)
2252 {
2253         struct drm_i915_private *dev_priv = to_i915(dev);
2254         bool changed;
2255
2256         /*
2257          * The BIOS provided WM memory latency values are often
2258          * inadequate for high resolution displays. Adjust them.
2259          */
2260         changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2261                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2262                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2263
2264         if (!changed)
2265                 return;
2266
2267         DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2268         intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2269         intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2270         intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2271 }
2272
2273 static void ilk_setup_wm_latency(struct drm_device *dev)
2274 {
2275         struct drm_i915_private *dev_priv = to_i915(dev);
2276
2277         intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2278
2279         memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2280                sizeof(dev_priv->wm.pri_latency));
2281         memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2282                sizeof(dev_priv->wm.pri_latency));
2283
2284         intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2285         intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
2286
2287         intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2288         intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2289         intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2290
2291         if (IS_GEN6(dev))
2292                 snb_wm_latency_quirk(dev);
2293 }
2294
2295 static void skl_setup_wm_latency(struct drm_device *dev)
2296 {
2297         struct drm_i915_private *dev_priv = to_i915(dev);
2298
2299         intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
2300         intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
2301 }
2302
2303 static bool ilk_validate_pipe_wm(struct drm_device *dev,
2304                                  struct intel_pipe_wm *pipe_wm)
2305 {
2306         /* LP0 watermark maximums depend on this pipe alone */
2307         const struct intel_wm_config config = {
2308                 .num_pipes_active = 1,
2309                 .sprites_enabled = pipe_wm->sprites_enabled,
2310                 .sprites_scaled = pipe_wm->sprites_scaled,
2311         };
2312         struct ilk_wm_maximums max;
2313
2314         /* LP0 watermarks always use 1/2 DDB partitioning */
2315         ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2316
2317         /* At least LP0 must be valid */
2318         if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) {
2319                 DRM_DEBUG_KMS("LP0 watermark invalid\n");
2320                 return false;
2321         }
2322
2323         return true;
2324 }
2325
2326 /* Compute new watermarks for the pipe */
2327 static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
2328 {
2329         struct drm_atomic_state *state = cstate->base.state;
2330         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
2331         struct intel_pipe_wm *pipe_wm;
2332         struct drm_device *dev = state->dev;
2333         const struct drm_i915_private *dev_priv = to_i915(dev);
2334         struct intel_plane *intel_plane;
2335         struct intel_plane_state *pristate = NULL;
2336         struct intel_plane_state *sprstate = NULL;
2337         struct intel_plane_state *curstate = NULL;
2338         int level, max_level = ilk_wm_max_level(dev), usable_level;
2339         struct ilk_wm_maximums max;
2340
2341         pipe_wm = &cstate->wm.ilk.optimal;
2342
2343         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2344                 struct intel_plane_state *ps;
2345
2346                 ps = intel_atomic_get_existing_plane_state(state,
2347                                                            intel_plane);
2348                 if (!ps)
2349                         continue;
2350
2351                 if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY)
2352                         pristate = ps;
2353                 else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY)
2354                         sprstate = ps;
2355                 else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
2356                         curstate = ps;
2357         }
2358
2359         pipe_wm->pipe_enabled = cstate->base.active;
2360         if (sprstate) {
2361                 pipe_wm->sprites_enabled = sprstate->visible;
2362                 pipe_wm->sprites_scaled = sprstate->visible &&
2363                         (drm_rect_width(&sprstate->dst) != drm_rect_width(&sprstate->src) >> 16 ||
2364                          drm_rect_height(&sprstate->dst) != drm_rect_height(&sprstate->src) >> 16);
2365         }
2366
2367         usable_level = max_level;
2368
2369         /* ILK/SNB: LP2+ watermarks only w/o sprites */
2370         if (INTEL_INFO(dev)->gen <= 6 && pipe_wm->sprites_enabled)
2371                 usable_level = 1;
2372
2373         /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2374         if (pipe_wm->sprites_scaled)
2375                 usable_level = 0;
2376
2377         ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
2378                              pristate, sprstate, curstate, &pipe_wm->raw_wm[0]);
2379
2380         memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm));
2381         pipe_wm->wm[0] = pipe_wm->raw_wm[0];
2382
2383         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2384                 pipe_wm->linetime = hsw_compute_linetime_wm(cstate);
2385
2386         if (!ilk_validate_pipe_wm(dev, pipe_wm))
2387                 return -EINVAL;
2388
2389         ilk_compute_wm_reg_maximums(dev, 1, &max);
2390
2391         for (level = 1; level <= max_level; level++) {
2392                 struct intel_wm_level *wm = &pipe_wm->raw_wm[level];
2393
2394                 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,
2395                                      pristate, sprstate, curstate, wm);
2396
2397                 /*
2398                  * Disable any watermark level that exceeds the
2399                  * register maximums since such watermarks are
2400                  * always invalid.
2401                  */
2402                 if (level > usable_level)
2403                         continue;
2404
2405                 if (ilk_validate_wm_level(level, &max, wm))
2406                         pipe_wm->wm[level] = *wm;
2407                 else
2408                         usable_level = level;
2409         }
2410
2411         return 0;
2412 }
2413
2414 /*
2415  * Build a set of 'intermediate' watermark values that satisfy both the old
2416  * state and the new state.  These can be programmed to the hardware
2417  * immediately.
2418  */
2419 static int ilk_compute_intermediate_wm(struct drm_device *dev,
2420                                        struct intel_crtc *intel_crtc,
2421                                        struct intel_crtc_state *newstate)
2422 {
2423         struct intel_pipe_wm *a = &newstate->wm.ilk.intermediate;
2424         struct intel_pipe_wm *b = &intel_crtc->wm.active.ilk;
2425         int level, max_level = ilk_wm_max_level(dev);
2426
2427         /*
2428          * Start with the final, target watermarks, then combine with the
2429          * currently active watermarks to get values that are safe both before
2430          * and after the vblank.
2431          */
2432         *a = newstate->wm.ilk.optimal;
2433         a->pipe_enabled |= b->pipe_enabled;
2434         a->sprites_enabled |= b->sprites_enabled;
2435         a->sprites_scaled |= b->sprites_scaled;
2436
2437         for (level = 0; level <= max_level; level++) {
2438                 struct intel_wm_level *a_wm = &a->wm[level];
2439                 const struct intel_wm_level *b_wm = &b->wm[level];
2440
2441                 a_wm->enable &= b_wm->enable;
2442                 a_wm->pri_val = max(a_wm->pri_val, b_wm->pri_val);
2443                 a_wm->spr_val = max(a_wm->spr_val, b_wm->spr_val);
2444                 a_wm->cur_val = max(a_wm->cur_val, b_wm->cur_val);
2445                 a_wm->fbc_val = max(a_wm->fbc_val, b_wm->fbc_val);
2446         }
2447
2448         /*
2449          * We need to make sure that these merged watermark values are
2450          * actually a valid configuration themselves.  If they're not,
2451          * there's no safe way to transition from the old state to
2452          * the new state, so we need to fail the atomic transaction.
2453          */
2454         if (!ilk_validate_pipe_wm(dev, a))
2455                 return -EINVAL;
2456
2457         /*
2458          * If our intermediate WM are identical to the final WM, then we can
2459          * omit the post-vblank programming; only update if it's different.
2460          */
2461         if (memcmp(a, &newstate->wm.ilk.optimal, sizeof(*a)) == 0)
2462                 newstate->wm.need_postvbl_update = false;
2463
2464         return 0;
2465 }
2466
2467 /*
2468  * Merge the watermarks from all active pipes for a specific level.
2469  */
2470 static void ilk_merge_wm_level(struct drm_device *dev,
2471                                int level,
2472                                struct intel_wm_level *ret_wm)
2473 {
2474         const struct intel_crtc *intel_crtc;
2475
2476         ret_wm->enable = true;
2477
2478         for_each_intel_crtc(dev, intel_crtc) {
2479                 const struct intel_pipe_wm *active = &intel_crtc->wm.active.ilk;
2480                 const struct intel_wm_level *wm = &active->wm[level];
2481
2482                 if (!active->pipe_enabled)
2483                         continue;
2484
2485                 /*
2486                  * The watermark values may have been used in the past,
2487                  * so we must maintain them in the registers for some
2488                  * time even if the level is now disabled.
2489                  */
2490                 if (!wm->enable)
2491                         ret_wm->enable = false;
2492
2493                 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2494                 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2495                 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2496                 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2497         }
2498 }
2499
2500 /*
2501  * Merge all low power watermarks for all active pipes.
2502  */
2503 static void ilk_wm_merge(struct drm_device *dev,
2504                          const struct intel_wm_config *config,
2505                          const struct ilk_wm_maximums *max,
2506                          struct intel_pipe_wm *merged)
2507 {
2508         struct drm_i915_private *dev_priv = to_i915(dev);
2509         int level, max_level = ilk_wm_max_level(dev);
2510         int last_enabled_level = max_level;
2511
2512         /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2513         if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2514             config->num_pipes_active > 1)
2515                 last_enabled_level = 0;
2516
2517         /* ILK: FBC WM must be disabled always */
2518         merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
2519
2520         /* merge each WM1+ level */
2521         for (level = 1; level <= max_level; level++) {
2522                 struct intel_wm_level *wm = &merged->wm[level];
2523
2524                 ilk_merge_wm_level(dev, level, wm);
2525
2526                 if (level > last_enabled_level)
2527                         wm->enable = false;
2528                 else if (!ilk_validate_wm_level(level, max, wm))
2529                         /* make sure all following levels get disabled */
2530                         last_enabled_level = level - 1;
2531
2532                 /*
2533                  * The spec says it is preferred to disable
2534                  * FBC WMs instead of disabling a WM level.
2535                  */
2536                 if (wm->fbc_val > max->fbc) {
2537                         if (wm->enable)
2538                                 merged->fbc_wm_enabled = false;
2539                         wm->fbc_val = 0;
2540                 }
2541         }
2542
2543         /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2544         /*
2545          * FIXME this is racy. FBC might get enabled later.
2546          * What we should check here is whether FBC can be
2547          * enabled sometime later.
2548          */
2549         if (IS_GEN5(dev) && !merged->fbc_wm_enabled &&
2550             intel_fbc_is_active(dev_priv)) {
2551                 for (level = 2; level <= max_level; level++) {
2552                         struct intel_wm_level *wm = &merged->wm[level];
2553
2554                         wm->enable = false;
2555                 }
2556         }
2557 }
2558
2559 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2560 {
2561         /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2562         return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2563 }
2564
2565 /* The value we need to program into the WM_LPx latency field */
2566 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2567 {
2568         struct drm_i915_private *dev_priv = to_i915(dev);
2569
2570         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2571                 return 2 * level;
2572         else
2573                 return dev_priv->wm.pri_latency[level];
2574 }
2575
2576 static void ilk_compute_wm_results(struct drm_device *dev,
2577                                    const struct intel_pipe_wm *merged,
2578                                    enum intel_ddb_partitioning partitioning,
2579                                    struct ilk_wm_values *results)
2580 {
2581         struct intel_crtc *intel_crtc;
2582         int level, wm_lp;
2583
2584         results->enable_fbc_wm = merged->fbc_wm_enabled;
2585         results->partitioning = partitioning;
2586
2587         /* LP1+ register values */
2588         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2589                 const struct intel_wm_level *r;
2590
2591                 level = ilk_wm_lp_to_level(wm_lp, merged);
2592
2593                 r = &merged->wm[level];
2594
2595                 /*
2596                  * Maintain the watermark values even if the level is
2597                  * disabled. Doing otherwise could cause underruns.
2598                  */
2599                 results->wm_lp[wm_lp - 1] =
2600                         (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
2601                         (r->pri_val << WM1_LP_SR_SHIFT) |
2602                         r->cur_val;
2603
2604                 if (r->enable)
2605                         results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2606
2607                 if (INTEL_INFO(dev)->gen >= 8)
2608                         results->wm_lp[wm_lp - 1] |=
2609                                 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2610                 else
2611                         results->wm_lp[wm_lp - 1] |=
2612                                 r->fbc_val << WM1_LP_FBC_SHIFT;
2613
2614                 /*
2615                  * Always set WM1S_LP_EN when spr_val != 0, even if the
2616                  * level is disabled. Doing otherwise could cause underruns.
2617                  */
2618                 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2619                         WARN_ON(wm_lp != 1);
2620                         results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2621                 } else
2622                         results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2623         }
2624
2625         /* LP0 register values */
2626         for_each_intel_crtc(dev, intel_crtc) {
2627                 enum pipe pipe = intel_crtc->pipe;
2628                 const struct intel_wm_level *r =
2629                         &intel_crtc->wm.active.ilk.wm[0];
2630
2631                 if (WARN_ON(!r->enable))
2632                         continue;
2633
2634                 results->wm_linetime[pipe] = intel_crtc->wm.active.ilk.linetime;
2635
2636                 results->wm_pipe[pipe] =
2637                         (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2638                         (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2639                         r->cur_val;
2640         }
2641 }
2642
2643 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2644  * case both are at the same level. Prefer r1 in case they're the same. */
2645 static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
2646                                                   struct intel_pipe_wm *r1,
2647                                                   struct intel_pipe_wm *r2)
2648 {
2649         int level, max_level = ilk_wm_max_level(dev);
2650         int level1 = 0, level2 = 0;
2651
2652         for (level = 1; level <= max_level; level++) {
2653                 if (r1->wm[level].enable)
2654                         level1 = level;
2655                 if (r2->wm[level].enable)
2656                         level2 = level;
2657         }
2658
2659         if (level1 == level2) {
2660                 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2661                         return r2;
2662                 else
2663                         return r1;
2664         } else if (level1 > level2) {
2665                 return r1;
2666         } else {
2667                 return r2;
2668         }
2669 }
2670
2671 /* dirty bits used to track which watermarks need changes */
2672 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2673 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2674 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2675 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2676 #define WM_DIRTY_FBC (1 << 24)
2677 #define WM_DIRTY_DDB (1 << 25)
2678
2679 static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
2680                                          const struct ilk_wm_values *old,
2681                                          const struct ilk_wm_values *new)
2682 {
2683         unsigned int dirty = 0;
2684         enum pipe pipe;
2685         int wm_lp;
2686
2687         for_each_pipe(dev_priv, pipe) {
2688                 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2689                         dirty |= WM_DIRTY_LINETIME(pipe);
2690                         /* Must disable LP1+ watermarks too */
2691                         dirty |= WM_DIRTY_LP_ALL;
2692                 }
2693
2694                 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2695                         dirty |= WM_DIRTY_PIPE(pipe);
2696                         /* Must disable LP1+ watermarks too */
2697                         dirty |= WM_DIRTY_LP_ALL;
2698                 }
2699         }
2700
2701         if (old->enable_fbc_wm != new->enable_fbc_wm) {
2702                 dirty |= WM_DIRTY_FBC;
2703                 /* Must disable LP1+ watermarks too */
2704                 dirty |= WM_DIRTY_LP_ALL;
2705         }
2706
2707         if (old->partitioning != new->partitioning) {
2708                 dirty |= WM_DIRTY_DDB;
2709                 /* Must disable LP1+ watermarks too */
2710                 dirty |= WM_DIRTY_LP_ALL;
2711         }
2712
2713         /* LP1+ watermarks already deemed dirty, no need to continue */
2714         if (dirty & WM_DIRTY_LP_ALL)
2715                 return dirty;
2716
2717         /* Find the lowest numbered LP1+ watermark in need of an update... */
2718         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2719                 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2720                     old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2721                         break;
2722         }
2723
2724         /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2725         for (; wm_lp <= 3; wm_lp++)
2726                 dirty |= WM_DIRTY_LP(wm_lp);
2727
2728         return dirty;
2729 }
2730
2731 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2732                                unsigned int dirty)
2733 {
2734         struct ilk_wm_values *previous = &dev_priv->wm.hw;
2735         bool changed = false;
2736
2737         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2738                 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2739                 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
2740                 changed = true;
2741         }
2742         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2743                 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2744                 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
2745                 changed = true;
2746         }
2747         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2748                 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2749                 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
2750                 changed = true;
2751         }
2752
2753         /*
2754          * Don't touch WM1S_LP_EN here.
2755          * Doing so could cause underruns.
2756          */
2757
2758         return changed;
2759 }
2760
2761 /*
2762  * The spec says we shouldn't write when we don't need, because every write
2763  * causes WMs to be re-evaluated, expending some power.
2764  */
2765 static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2766                                 struct ilk_wm_values *results)
2767 {
2768         struct drm_device *dev = &dev_priv->drm;
2769         struct ilk_wm_values *previous = &dev_priv->wm.hw;
2770         unsigned int dirty;
2771         uint32_t val;
2772
2773         dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
2774         if (!dirty)
2775                 return;
2776
2777         _ilk_disable_lp_wm(dev_priv, dirty);
2778
2779         if (dirty & WM_DIRTY_PIPE(PIPE_A))
2780                 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2781         if (dirty & WM_DIRTY_PIPE(PIPE_B))
2782                 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2783         if (dirty & WM_DIRTY_PIPE(PIPE_C))
2784                 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2785
2786         if (dirty & WM_DIRTY_LINETIME(PIPE_A))
2787                 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2788         if (dirty & WM_DIRTY_LINETIME(PIPE_B))
2789                 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2790         if (dirty & WM_DIRTY_LINETIME(PIPE_C))
2791                 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2792
2793         if (dirty & WM_DIRTY_DDB) {
2794                 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2795                         val = I915_READ(WM_MISC);
2796                         if (results->partitioning == INTEL_DDB_PART_1_2)
2797                                 val &= ~WM_MISC_DATA_PARTITION_5_6;
2798                         else
2799                                 val |= WM_MISC_DATA_PARTITION_5_6;
2800                         I915_WRITE(WM_MISC, val);
2801                 } else {
2802                         val = I915_READ(DISP_ARB_CTL2);
2803                         if (results->partitioning == INTEL_DDB_PART_1_2)
2804                                 val &= ~DISP_DATA_PARTITION_5_6;
2805                         else
2806                                 val |= DISP_DATA_PARTITION_5_6;
2807                         I915_WRITE(DISP_ARB_CTL2, val);
2808                 }
2809         }
2810
2811         if (dirty & WM_DIRTY_FBC) {
2812                 val = I915_READ(DISP_ARB_CTL);
2813                 if (results->enable_fbc_wm)
2814                         val &= ~DISP_FBC_WM_DIS;
2815                 else
2816                         val |= DISP_FBC_WM_DIS;
2817                 I915_WRITE(DISP_ARB_CTL, val);
2818         }
2819
2820         if (dirty & WM_DIRTY_LP(1) &&
2821             previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2822                 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2823
2824         if (INTEL_INFO(dev)->gen >= 7) {
2825                 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2826                         I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2827                 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2828                         I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2829         }
2830
2831         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
2832                 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2833         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
2834                 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2835         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
2836                 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2837
2838         dev_priv->wm.hw = *results;
2839 }
2840
2841 bool ilk_disable_lp_wm(struct drm_device *dev)
2842 {
2843         struct drm_i915_private *dev_priv = to_i915(dev);
2844
2845         return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2846 }
2847
2848 /*
2849  * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
2850  * different active planes.
2851  */
2852
2853 #define SKL_DDB_SIZE            896     /* in blocks */
2854 #define BXT_DDB_SIZE            512
2855
2856 /*
2857  * Return the index of a plane in the SKL DDB and wm result arrays.  Primary
2858  * plane is always in slot 0, cursor is always in slot I915_MAX_PLANES-1, and
2859  * other universal planes are in indices 1..n.  Note that this may leave unused
2860  * indices between the top "sprite" plane and the cursor.
2861  */
2862 static int
2863 skl_wm_plane_id(const struct intel_plane *plane)
2864 {
2865         switch (plane->base.type) {
2866         case DRM_PLANE_TYPE_PRIMARY:
2867                 return 0;
2868         case DRM_PLANE_TYPE_CURSOR:
2869                 return PLANE_CURSOR;
2870         case DRM_PLANE_TYPE_OVERLAY:
2871                 return plane->plane + 1;
2872         default:
2873                 MISSING_CASE(plane->base.type);
2874                 return plane->plane;
2875         }
2876 }
2877
2878 static void
2879 skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
2880                                    const struct intel_crtc_state *cstate,
2881                                    struct skl_ddb_entry *alloc, /* out */
2882                                    int *num_active /* out */)
2883 {
2884         struct drm_atomic_state *state = cstate->base.state;
2885         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
2886         struct drm_i915_private *dev_priv = to_i915(dev);
2887         struct drm_crtc *for_crtc = cstate->base.crtc;
2888         unsigned int pipe_size, ddb_size;
2889         int nth_active_pipe;
2890         int pipe = to_intel_crtc(for_crtc)->pipe;
2891
2892         if (WARN_ON(!state) || !cstate->base.active) {
2893                 alloc->start = 0;
2894                 alloc->end = 0;
2895                 *num_active = hweight32(dev_priv->active_crtcs);
2896                 return;
2897         }
2898
2899         if (intel_state->active_pipe_changes)
2900                 *num_active = hweight32(intel_state->active_crtcs);
2901         else
2902                 *num_active = hweight32(dev_priv->active_crtcs);
2903
2904         if (IS_BROXTON(dev))
2905                 ddb_size = BXT_DDB_SIZE;
2906         else
2907                 ddb_size = SKL_DDB_SIZE;
2908
2909         ddb_size -= 4; /* 4 blocks for bypass path allocation */
2910
2911         /*
2912          * If the state doesn't change the active CRTC's, then there's
2913          * no need to recalculate; the existing pipe allocation limits
2914          * should remain unchanged.  Note that we're safe from racing
2915          * commits since any racing commit that changes the active CRTC
2916          * list would need to grab _all_ crtc locks, including the one
2917          * we currently hold.
2918          */
2919         if (!intel_state->active_pipe_changes) {
2920                 *alloc = dev_priv->wm.skl_hw.ddb.pipe[pipe];
2921                 return;
2922         }
2923
2924         nth_active_pipe = hweight32(intel_state->active_crtcs &
2925                                     (drm_crtc_mask(for_crtc) - 1));
2926         pipe_size = ddb_size / hweight32(intel_state->active_crtcs);
2927         alloc->start = nth_active_pipe * ddb_size / *num_active;
2928         alloc->end = alloc->start + pipe_size;
2929 }
2930
2931 static unsigned int skl_cursor_allocation(int num_active)
2932 {
2933         if (num_active == 1)
2934                 return 32;
2935
2936         return 8;
2937 }
2938
2939 static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
2940 {
2941         entry->start = reg & 0x3ff;
2942         entry->end = (reg >> 16) & 0x3ff;
2943         if (entry->end)
2944                 entry->end += 1;
2945 }
2946
2947 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2948                           struct skl_ddb_allocation *ddb /* out */)
2949 {
2950         enum pipe pipe;
2951         int plane;
2952         u32 val;
2953
2954         memset(ddb, 0, sizeof(*ddb));
2955
2956         for_each_pipe(dev_priv, pipe) {
2957                 enum intel_display_power_domain power_domain;
2958
2959                 power_domain = POWER_DOMAIN_PIPE(pipe);
2960                 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
2961                         continue;
2962
2963                 for_each_plane(dev_priv, pipe, plane) {
2964                         val = I915_READ(PLANE_BUF_CFG(pipe, plane));
2965                         skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
2966                                                    val);
2967                 }
2968
2969                 val = I915_READ(CUR_BUF_CFG(pipe));
2970                 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR],
2971                                            val);
2972
2973                 intel_display_power_put(dev_priv, power_domain);
2974         }
2975 }
2976
2977 /*
2978  * Determines the downscale amount of a plane for the purposes of watermark calculations.
2979  * The bspec defines downscale amount as:
2980  *
2981  * """
2982  * Horizontal down scale amount = maximum[1, Horizontal source size /
2983  *                                           Horizontal destination size]
2984  * Vertical down scale amount = maximum[1, Vertical source size /
2985  *                                         Vertical destination size]
2986  * Total down scale amount = Horizontal down scale amount *
2987  *                           Vertical down scale amount
2988  * """
2989  *
2990  * Return value is provided in 16.16 fixed point form to retain fractional part.
2991  * Caller should take care of dividing & rounding off the value.
2992  */
2993 static uint32_t
2994 skl_plane_downscale_amount(const struct intel_plane_state *pstate)
2995 {
2996         uint32_t downscale_h, downscale_w;
2997         uint32_t src_w, src_h, dst_w, dst_h;
2998
2999         if (WARN_ON(!pstate->visible))
3000                 return DRM_PLANE_HELPER_NO_SCALING;
3001
3002         /* n.b., src is 16.16 fixed point, dst is whole integer */
3003         src_w = drm_rect_width(&pstate->src);
3004         src_h = drm_rect_height(&pstate->src);
3005         dst_w = drm_rect_width(&pstate->dst);
3006         dst_h = drm_rect_height(&pstate->dst);
3007         if (intel_rotation_90_or_270(pstate->base.rotation))
3008                 swap(dst_w, dst_h);
3009
3010         downscale_h = max(src_h / dst_h, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
3011         downscale_w = max(src_w / dst_w, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
3012
3013         /* Provide result in 16.16 fixed point */
3014         return (uint64_t)downscale_w * downscale_h >> 16;
3015 }
3016
3017 static unsigned int
3018 skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
3019                              const struct drm_plane_state *pstate,
3020                              int y)
3021 {
3022         struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
3023         struct drm_framebuffer *fb = pstate->fb;
3024         uint32_t down_scale_amount, data_rate;
3025         uint32_t width = 0, height = 0;
3026         unsigned format = fb ? fb->pixel_format : DRM_FORMAT_XRGB8888;
3027
3028         if (!intel_pstate->visible)
3029                 return 0;
3030         if (pstate->plane->type == DRM_PLANE_TYPE_CURSOR)
3031                 return 0;
3032         if (y && format != DRM_FORMAT_NV12)
3033                 return 0;
3034
3035         width = drm_rect_width(&intel_pstate->src) >> 16;
3036         height = drm_rect_height(&intel_pstate->src) >> 16;
3037
3038         if (intel_rotation_90_or_270(pstate->rotation))
3039                 swap(width, height);
3040
3041         /* for planar format */
3042         if (format == DRM_FORMAT_NV12) {
3043                 if (y)  /* y-plane data rate */
3044                         data_rate = width * height *
3045                                 drm_format_plane_cpp(format, 0);
3046                 else    /* uv-plane data rate */
3047                         data_rate = (width / 2) * (height / 2) *
3048                                 drm_format_plane_cpp(format, 1);
3049         } else {
3050                 /* for packed formats */
3051                 data_rate = width * height * drm_format_plane_cpp(format, 0);
3052         }
3053
3054         down_scale_amount = skl_plane_downscale_amount(intel_pstate);
3055
3056         return (uint64_t)data_rate * down_scale_amount >> 16;
3057 }
3058
3059 /*
3060  * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
3061  * a 8192x4096@32bpp framebuffer:
3062  *   3 * 4096 * 8192  * 4 < 2^32
3063  */
3064 static unsigned int
3065 skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate)
3066 {
3067         struct drm_crtc_state *cstate = &intel_cstate->base;
3068         struct drm_atomic_state *state = cstate->state;
3069         struct drm_crtc *crtc = cstate->crtc;
3070         struct drm_device *dev = crtc->dev;
3071         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3072         const struct drm_plane *plane;
3073         const struct intel_plane *intel_plane;
3074         struct drm_plane_state *pstate;
3075         unsigned int rate, total_data_rate = 0;
3076         int id;
3077         int i;
3078
3079         if (WARN_ON(!state))
3080                 return 0;
3081
3082         /* Calculate and cache data rate for each plane */
3083         for_each_plane_in_state(state, plane, pstate, i) {
3084                 id = skl_wm_plane_id(to_intel_plane(plane));
3085                 intel_plane = to_intel_plane(plane);
3086
3087                 if (intel_plane->pipe != intel_crtc->pipe)
3088                         continue;
3089
3090                 /* packed/uv */
3091                 rate = skl_plane_relative_data_rate(intel_cstate,
3092                                                     pstate, 0);
3093                 intel_cstate->wm.skl.plane_data_rate[id] = rate;
3094
3095                 /* y-plane */
3096                 rate = skl_plane_relative_data_rate(intel_cstate,
3097                                                     pstate, 1);
3098                 intel_cstate->wm.skl.plane_y_data_rate[id] = rate;
3099         }
3100
3101         /* Calculate CRTC's total data rate from cached values */
3102         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3103                 int id = skl_wm_plane_id(intel_plane);
3104
3105                 /* packed/uv */
3106                 total_data_rate += intel_cstate->wm.skl.plane_data_rate[id];
3107                 total_data_rate += intel_cstate->wm.skl.plane_y_data_rate[id];
3108         }
3109
3110         WARN_ON(cstate->plane_mask && total_data_rate == 0);
3111
3112         return total_data_rate;
3113 }
3114
3115 static uint16_t
3116 skl_ddb_min_alloc(const struct drm_plane_state *pstate,
3117                   const int y)
3118 {
3119         struct drm_framebuffer *fb = pstate->fb;
3120         struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
3121         uint32_t src_w, src_h;
3122         uint32_t min_scanlines = 8;
3123         uint8_t plane_bpp;
3124
3125         if (WARN_ON(!fb))
3126                 return 0;
3127
3128         /* For packed formats, no y-plane, return 0 */
3129         if (y && fb->pixel_format != DRM_FORMAT_NV12)
3130                 return 0;
3131
3132         /* For Non Y-tile return 8-blocks */
3133         if (fb->modifier[0] != I915_FORMAT_MOD_Y_TILED &&
3134             fb->modifier[0] != I915_FORMAT_MOD_Yf_TILED)
3135                 return 8;
3136
3137         src_w = drm_rect_width(&intel_pstate->src) >> 16;
3138         src_h = drm_rect_height(&intel_pstate->src) >> 16;
3139
3140         if (intel_rotation_90_or_270(pstate->rotation))
3141                 swap(src_w, src_h);
3142
3143         /* Halve UV plane width and height for NV12 */
3144         if (fb->pixel_format == DRM_FORMAT_NV12 && !y) {
3145                 src_w /= 2;
3146                 src_h /= 2;
3147         }
3148
3149         if (fb->pixel_format == DRM_FORMAT_NV12 && !y)
3150                 plane_bpp = drm_format_plane_cpp(fb->pixel_format, 1);
3151         else
3152                 plane_bpp = drm_format_plane_cpp(fb->pixel_format, 0);
3153
3154         if (intel_rotation_90_or_270(pstate->rotation)) {
3155                 switch (plane_bpp) {
3156                 case 1:
3157                         min_scanlines = 32;
3158                         break;
3159                 case 2:
3160                         min_scanlines = 16;
3161                         break;
3162                 case 4:
3163                         min_scanlines = 8;
3164                         break;
3165                 case 8:
3166                         min_scanlines = 4;
3167                         break;
3168                 default:
3169                         WARN(1, "Unsupported pixel depth %u for rotation",
3170                              plane_bpp);
3171                         min_scanlines = 32;
3172                 }
3173         }
3174
3175         return DIV_ROUND_UP((4 * src_w * plane_bpp), 512) * min_scanlines/4 + 3;
3176 }
3177
3178 static int
3179 skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
3180                       struct skl_ddb_allocation *ddb /* out */)
3181 {
3182         struct drm_atomic_state *state = cstate->base.state;
3183         struct drm_crtc *crtc = cstate->base.crtc;
3184         struct drm_device *dev = crtc->dev;
3185         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3186         struct intel_plane *intel_plane;
3187         struct drm_plane *plane;
3188         struct drm_plane_state *pstate;
3189         enum pipe pipe = intel_crtc->pipe;
3190         struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
3191         uint16_t alloc_size, start, cursor_blocks;
3192         uint16_t *minimum = cstate->wm.skl.minimum_blocks;
3193         uint16_t *y_minimum = cstate->wm.skl.minimum_y_blocks;
3194         unsigned int total_data_rate;
3195         int num_active;
3196         int id, i;
3197
3198         if (WARN_ON(!state))
3199                 return 0;
3200
3201         if (!cstate->base.active) {
3202                 ddb->pipe[pipe].start = ddb->pipe[pipe].end = 0;
3203                 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
3204                 memset(ddb->y_plane[pipe], 0, sizeof(ddb->y_plane[pipe]));
3205                 return 0;
3206         }
3207
3208         skl_ddb_get_pipe_allocation_limits(dev, cstate, alloc, &num_active);
3209         alloc_size = skl_ddb_entry_size(alloc);
3210         if (alloc_size == 0) {
3211                 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
3212                 return 0;
3213         }
3214
3215         cursor_blocks = skl_cursor_allocation(num_active);
3216         ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - cursor_blocks;
3217         ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
3218
3219         alloc_size -= cursor_blocks;
3220
3221         /* 1. Allocate the mininum required blocks for each active plane */
3222         for_each_plane_in_state(state, plane, pstate, i) {
3223                 intel_plane = to_intel_plane(plane);
3224                 id = skl_wm_plane_id(intel_plane);
3225
3226                 if (intel_plane->pipe != pipe)
3227                         continue;
3228
3229                 if (!to_intel_plane_state(pstate)->visible) {
3230                         minimum[id] = 0;
3231                         y_minimum[id] = 0;
3232                         continue;
3233                 }
3234                 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
3235                         minimum[id] = 0;
3236                         y_minimum[id] = 0;
3237                         continue;
3238                 }
3239
3240                 minimum[id] = skl_ddb_min_alloc(pstate, 0);
3241                 y_minimum[id] = skl_ddb_min_alloc(pstate, 1);
3242         }
3243
3244         for (i = 0; i < PLANE_CURSOR; i++) {
3245                 alloc_size -= minimum[i];
3246                 alloc_size -= y_minimum[i];
3247         }
3248
3249         /*
3250          * 2. Distribute the remaining space in proportion to the amount of
3251          * data each plane needs to fetch from memory.
3252          *
3253          * FIXME: we may not allocate every single block here.
3254          */
3255         total_data_rate = skl_get_total_relative_data_rate(cstate);
3256         if (total_data_rate == 0)
3257                 return 0;
3258
3259         start = alloc->start;
3260         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3261                 unsigned int data_rate, y_data_rate;
3262                 uint16_t plane_blocks, y_plane_blocks = 0;
3263                 int id = skl_wm_plane_id(intel_plane);
3264
3265                 data_rate = cstate->wm.skl.plane_data_rate[id];
3266
3267                 /*
3268                  * allocation for (packed formats) or (uv-plane part of planar format):
3269                  * promote the expression to 64 bits to avoid overflowing, the
3270                  * result is < available as data_rate / total_data_rate < 1
3271                  */
3272                 plane_blocks = minimum[id];
3273                 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
3274                                         total_data_rate);
3275
3276                 /* Leave disabled planes at (0,0) */
3277                 if (data_rate) {
3278                         ddb->plane[pipe][id].start = start;
3279                         ddb->plane[pipe][id].end = start + plane_blocks;
3280                 }
3281
3282                 start += plane_blocks;
3283
3284                 /*
3285                  * allocation for y_plane part of planar format:
3286                  */
3287                 y_data_rate = cstate->wm.skl.plane_y_data_rate[id];
3288
3289                 y_plane_blocks = y_minimum[id];
3290                 y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
3291                                         total_data_rate);
3292
3293                 if (y_data_rate) {
3294                         ddb->y_plane[pipe][id].start = start;
3295                         ddb->y_plane[pipe][id].end = start + y_plane_blocks;
3296                 }
3297
3298                 start += y_plane_blocks;
3299         }
3300
3301         return 0;
3302 }
3303
3304 static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
3305 {
3306         /* TODO: Take into account the scalers once we support them */
3307         return config->base.adjusted_mode.crtc_clock;
3308 }
3309
3310 /*
3311  * The max latency should be 257 (max the punit can code is 255 and we add 2us
3312  * for the read latency) and cpp should always be <= 8, so that
3313  * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3314  * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3315 */
3316 static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
3317 {
3318         uint32_t wm_intermediate_val, ret;
3319
3320         if (latency == 0)
3321                 return UINT_MAX;
3322
3323         wm_intermediate_val = latency * pixel_rate * cpp / 512;
3324         ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
3325
3326         return ret;
3327 }
3328
3329 static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
3330                                uint32_t horiz_pixels, uint8_t cpp,
3331                                uint64_t tiling, uint32_t latency)
3332 {
3333         uint32_t ret;
3334         uint32_t plane_bytes_per_line, plane_blocks_per_line;
3335         uint32_t wm_intermediate_val;
3336
3337         if (latency == 0)
3338                 return UINT_MAX;
3339
3340         plane_bytes_per_line = horiz_pixels * cpp;
3341
3342         if (tiling == I915_FORMAT_MOD_Y_TILED ||
3343             tiling == I915_FORMAT_MOD_Yf_TILED) {
3344                 plane_bytes_per_line *= 4;
3345                 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3346                 plane_blocks_per_line /= 4;
3347         } else if (tiling == DRM_FORMAT_MOD_NONE) {
3348                 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512) + 1;
3349         } else {
3350                 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3351         }
3352
3353         wm_intermediate_val = latency * pixel_rate;
3354         ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
3355                                 plane_blocks_per_line;
3356
3357         return ret;
3358 }
3359
3360 static uint32_t skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cstate,
3361                                               struct intel_plane_state *pstate)
3362 {
3363         uint64_t adjusted_pixel_rate;
3364         uint64_t downscale_amount;
3365         uint64_t pixel_rate;
3366
3367         /* Shouldn't reach here on disabled planes... */
3368         if (WARN_ON(!pstate->visible))
3369                 return 0;
3370
3371         /*
3372          * Adjusted plane pixel rate is just the pipe's adjusted pixel rate
3373          * with additional adjustments for plane-specific scaling.
3374          */
3375         adjusted_pixel_rate = skl_pipe_pixel_rate(cstate);
3376         downscale_amount = skl_plane_downscale_amount(pstate);
3377
3378         pixel_rate = adjusted_pixel_rate * downscale_amount >> 16;
3379         WARN_ON(pixel_rate != clamp_t(uint32_t, pixel_rate, 0, ~0));
3380
3381         return pixel_rate;
3382 }
3383
3384 static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
3385                                 struct intel_crtc_state *cstate,
3386                                 struct intel_plane_state *intel_pstate,
3387                                 uint16_t ddb_allocation,
3388                                 int level,
3389                                 uint16_t *out_blocks, /* out */
3390                                 uint8_t *out_lines, /* out */
3391                                 bool *enabled /* out */)
3392 {
3393         struct drm_plane_state *pstate = &intel_pstate->base;
3394         struct drm_framebuffer *fb = pstate->fb;
3395         uint32_t latency = dev_priv->wm.skl_latency[level];
3396         uint32_t method1, method2;
3397         uint32_t plane_bytes_per_line, plane_blocks_per_line;
3398         uint32_t res_blocks, res_lines;
3399         uint32_t selected_result;
3400         uint8_t cpp;
3401         uint32_t width = 0, height = 0;
3402         uint32_t plane_pixel_rate;
3403
3404         if (latency == 0 || !cstate->base.active || !intel_pstate->visible) {
3405                 *enabled = false;
3406                 return 0;
3407         }
3408
3409         width = drm_rect_width(&intel_pstate->src) >> 16;
3410         height = drm_rect_height(&intel_pstate->src) >> 16;
3411
3412         if (intel_rotation_90_or_270(pstate->rotation))
3413                 swap(width, height);
3414
3415         cpp = drm_format_plane_cpp(fb->pixel_format, 0);
3416         plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate, intel_pstate);
3417
3418         method1 = skl_wm_method1(plane_pixel_rate, cpp, latency);
3419         method2 = skl_wm_method2(plane_pixel_rate,
3420                                  cstate->base.adjusted_mode.crtc_htotal,
3421                                  width,
3422                                  cpp,
3423                                  fb->modifier[0],
3424                                  latency);
3425
3426         plane_bytes_per_line = width * cpp;
3427         plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3428
3429         if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3430             fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
3431                 uint32_t min_scanlines = 4;
3432                 uint32_t y_tile_minimum;
3433                 if (intel_rotation_90_or_270(pstate->rotation)) {
3434                         int cpp = (fb->pixel_format == DRM_FORMAT_NV12) ?
3435                                 drm_format_plane_cpp(fb->pixel_format, 1) :
3436                                 drm_format_plane_cpp(fb->pixel_format, 0);
3437
3438                         switch (cpp) {
3439                         case 1:
3440                                 min_scanlines = 16;
3441                                 break;
3442                         case 2:
3443                                 min_scanlines = 8;
3444                                 break;
3445                         case 8:
3446                                 WARN(1, "Unsupported pixel depth for rotation");
3447                         }
3448                 }
3449                 y_tile_minimum = plane_blocks_per_line * min_scanlines;
3450                 selected_result = max(method2, y_tile_minimum);
3451         } else {
3452                 if ((ddb_allocation / plane_blocks_per_line) >= 1)
3453                         selected_result = min(method1, method2);
3454                 else
3455                         selected_result = method1;
3456         }
3457
3458         res_blocks = selected_result + 1;
3459         res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
3460
3461         if (level >= 1 && level <= 7) {
3462                 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3463                     fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED)
3464                         res_lines += 4;
3465                 else
3466                         res_blocks++;
3467         }
3468
3469         if (res_blocks >= ddb_allocation || res_lines > 31) {
3470                 *enabled = false;
3471
3472                 /*
3473                  * If there are no valid level 0 watermarks, then we can't
3474                  * support this display configuration.
3475                  */
3476                 if (level) {
3477                         return 0;
3478                 } else {
3479                         DRM_DEBUG_KMS("Requested display configuration exceeds system watermark limitations\n");
3480                         DRM_DEBUG_KMS("Plane %d.%d: blocks required = %u/%u, lines required = %u/31\n",
3481                                       to_intel_crtc(cstate->base.crtc)->pipe,
3482                                       skl_wm_plane_id(to_intel_plane(pstate->plane)),
3483                                       res_blocks, ddb_allocation, res_lines);
3484
3485                         return -EINVAL;
3486                 }
3487         }
3488
3489         *out_blocks = res_blocks;
3490         *out_lines = res_lines;
3491         *enabled = true;
3492
3493         return 0;
3494 }
3495
3496 static int
3497 skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3498                      struct skl_ddb_allocation *ddb,
3499                      struct intel_crtc_state *cstate,
3500                      int level,
3501                      struct skl_wm_level *result)
3502 {
3503         struct drm_atomic_state *state = cstate->base.state;
3504         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
3505         struct drm_plane *plane;
3506         struct intel_plane *intel_plane;
3507         struct intel_plane_state *intel_pstate;
3508         uint16_t ddb_blocks;
3509         enum pipe pipe = intel_crtc->pipe;
3510         int ret;
3511
3512         /*
3513          * We'll only calculate watermarks for planes that are actually
3514          * enabled, so make sure all other planes are set as disabled.
3515          */
3516         memset(result, 0, sizeof(*result));
3517
3518         for_each_intel_plane_mask(&dev_priv->drm,
3519                                   intel_plane,
3520                                   cstate->base.plane_mask) {
3521                 int i = skl_wm_plane_id(intel_plane);
3522
3523                 plane = &intel_plane->base;
3524                 intel_pstate = NULL;
3525                 if (state)
3526                         intel_pstate =
3527                                 intel_atomic_get_existing_plane_state(state,
3528                                                                       intel_plane);
3529
3530                 /*
3531                  * Note: If we start supporting multiple pending atomic commits
3532                  * against the same planes/CRTC's in the future, plane->state
3533                  * will no longer be the correct pre-state to use for the
3534                  * calculations here and we'll need to change where we get the
3535                  * 'unchanged' plane data from.
3536                  *
3537                  * For now this is fine because we only allow one queued commit
3538                  * against a CRTC.  Even if the plane isn't modified by this
3539                  * transaction and we don't have a plane lock, we still have
3540                  * the CRTC's lock, so we know that no other transactions are
3541                  * racing with us to update it.
3542                  */
3543                 if (!intel_pstate)
3544                         intel_pstate = to_intel_plane_state(plane->state);
3545
3546                 WARN_ON(!intel_pstate->base.fb);
3547
3548                 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
3549
3550                 ret = skl_compute_plane_wm(dev_priv,
3551                                            cstate,
3552                                            intel_pstate,
3553                                            ddb_blocks,
3554                                            level,
3555                                            &result->plane_res_b[i],
3556                                            &result->plane_res_l[i],
3557                                            &result->plane_en[i]);
3558                 if (ret)
3559                         return ret;
3560         }
3561
3562         return 0;
3563 }
3564
3565 static uint32_t
3566 skl_compute_linetime_wm(struct intel_crtc_state *cstate)
3567 {
3568         if (!cstate->base.active)
3569                 return 0;
3570
3571         if (WARN_ON(skl_pipe_pixel_rate(cstate) == 0))
3572                 return 0;
3573
3574         return DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * 1000,
3575                             skl_pipe_pixel_rate(cstate));
3576 }
3577
3578 static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
3579                                       struct skl_wm_level *trans_wm /* out */)
3580 {
3581         struct drm_crtc *crtc = cstate->base.crtc;
3582         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3583         struct intel_plane *intel_plane;
3584
3585         if (!cstate->base.active)
3586                 return;
3587
3588         /* Until we know more, just disable transition WMs */
3589         for_each_intel_plane_on_crtc(crtc->dev, intel_crtc, intel_plane) {
3590                 int i = skl_wm_plane_id(intel_plane);
3591
3592                 trans_wm->plane_en[i] = false;
3593         }
3594 }
3595
3596 static int skl_build_pipe_wm(struct intel_crtc_state *cstate,
3597                              struct skl_ddb_allocation *ddb,
3598                              struct skl_pipe_wm *pipe_wm)
3599 {
3600         struct drm_device *dev = cstate->base.crtc->dev;
3601         const struct drm_i915_private *dev_priv = to_i915(dev);
3602         int level, max_level = ilk_wm_max_level(dev);
3603         int ret;
3604
3605         for (level = 0; level <= max_level; level++) {
3606                 ret = skl_compute_wm_level(dev_priv, ddb, cstate,
3607                                            level, &pipe_wm->wm[level]);
3608                 if (ret)
3609                         return ret;
3610         }
3611         pipe_wm->linetime = skl_compute_linetime_wm(cstate);
3612
3613         skl_compute_transition_wm(cstate, &pipe_wm->trans_wm);
3614
3615         return 0;
3616 }
3617
3618 static void skl_compute_wm_results(struct drm_device *dev,
3619                                    struct skl_pipe_wm *p_wm,
3620                                    struct skl_wm_values *r,
3621                                    struct intel_crtc *intel_crtc)
3622 {
3623         int level, max_level = ilk_wm_max_level(dev);
3624         enum pipe pipe = intel_crtc->pipe;
3625         uint32_t temp;
3626         int i;
3627
3628         for (level = 0; level <= max_level; level++) {
3629                 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3630                         temp = 0;
3631
3632                         temp |= p_wm->wm[level].plane_res_l[i] <<
3633                                         PLANE_WM_LINES_SHIFT;
3634                         temp |= p_wm->wm[level].plane_res_b[i];
3635                         if (p_wm->wm[level].plane_en[i])
3636                                 temp |= PLANE_WM_EN;
3637
3638                         r->plane[pipe][i][level] = temp;
3639                 }
3640
3641                 temp = 0;
3642
3643                 temp |= p_wm->wm[level].plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3644                 temp |= p_wm->wm[level].plane_res_b[PLANE_CURSOR];
3645
3646                 if (p_wm->wm[level].plane_en[PLANE_CURSOR])
3647                         temp |= PLANE_WM_EN;
3648
3649                 r->plane[pipe][PLANE_CURSOR][level] = temp;
3650
3651         }
3652
3653         /* transition WMs */
3654         for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3655                 temp = 0;
3656                 temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT;
3657                 temp |= p_wm->trans_wm.plane_res_b[i];
3658                 if (p_wm->trans_wm.plane_en[i])
3659                         temp |= PLANE_WM_EN;
3660
3661                 r->plane_trans[pipe][i] = temp;
3662         }
3663
3664         temp = 0;
3665         temp |= p_wm->trans_wm.plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3666         temp |= p_wm->trans_wm.plane_res_b[PLANE_CURSOR];
3667         if (p_wm->trans_wm.plane_en[PLANE_CURSOR])
3668                 temp |= PLANE_WM_EN;
3669
3670         r->plane_trans[pipe][PLANE_CURSOR] = temp;
3671
3672         r->wm_linetime[pipe] = p_wm->linetime;
3673 }
3674
3675 static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
3676                                 i915_reg_t reg,
3677                                 const struct skl_ddb_entry *entry)
3678 {
3679         if (entry->end)
3680                 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3681         else
3682                 I915_WRITE(reg, 0);
3683 }
3684
3685 static void skl_write_wm_values(struct drm_i915_private *dev_priv,
3686                                 const struct skl_wm_values *new)
3687 {
3688         struct drm_device *dev = &dev_priv->drm;
3689         struct intel_crtc *crtc;
3690
3691         for_each_intel_crtc(dev, crtc) {
3692                 int i, level, max_level = ilk_wm_max_level(dev);
3693                 enum pipe pipe = crtc->pipe;
3694
3695                 if ((new->dirty_pipes & drm_crtc_mask(&crtc->base)) == 0)
3696                         continue;
3697                 if (!crtc->active)
3698                         continue;
3699
3700                 I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]);
3701
3702                 for (level = 0; level <= max_level; level++) {
3703                         for (i = 0; i < intel_num_planes(crtc); i++)
3704                                 I915_WRITE(PLANE_WM(pipe, i, level),
3705                                            new->plane[pipe][i][level]);
3706                         I915_WRITE(CUR_WM(pipe, level),
3707                                    new->plane[pipe][PLANE_CURSOR][level]);
3708                 }
3709                 for (i = 0; i < intel_num_planes(crtc); i++)
3710                         I915_WRITE(PLANE_WM_TRANS(pipe, i),
3711                                    new->plane_trans[pipe][i]);
3712                 I915_WRITE(CUR_WM_TRANS(pipe),
3713                            new->plane_trans[pipe][PLANE_CURSOR]);
3714
3715                 for (i = 0; i < intel_num_planes(crtc); i++) {
3716                         skl_ddb_entry_write(dev_priv,
3717                                             PLANE_BUF_CFG(pipe, i),
3718                                             &new->ddb.plane[pipe][i]);
3719                         skl_ddb_entry_write(dev_priv,
3720                                             PLANE_NV12_BUF_CFG(pipe, i),
3721                                             &new->ddb.y_plane[pipe][i]);
3722                 }
3723
3724                 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
3725                                     &new->ddb.plane[pipe][PLANE_CURSOR]);
3726         }
3727 }
3728
3729 /*
3730  * When setting up a new DDB allocation arrangement, we need to correctly
3731  * sequence the times at which the new allocations for the pipes are taken into
3732  * account or we'll have pipes fetching from space previously allocated to
3733  * another pipe.
3734  *
3735  * Roughly the sequence looks like:
3736  *  1. re-allocate the pipe(s) with the allocation being reduced and not
3737  *     overlapping with a previous light-up pipe (another way to put it is:
3738  *     pipes with their new allocation strickly included into their old ones).
3739  *  2. re-allocate the other pipes that get their allocation reduced
3740  *  3. allocate the pipes having their allocation increased
3741  *
3742  * Steps 1. and 2. are here to take care of the following case:
3743  * - Initially DDB looks like this:
3744  *     |   B    |   C    |
3745  * - enable pipe A.
3746  * - pipe B has a reduced DDB allocation that overlaps with the old pipe C
3747  *   allocation
3748  *     |  A  |  B  |  C  |
3749  *
3750  * We need to sequence the re-allocation: C, B, A (and not B, C, A).
3751  */
3752
3753 static void
3754 skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int pass)
3755 {
3756         int plane;
3757
3758         DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass);
3759
3760         for_each_plane(dev_priv, pipe, plane) {
3761                 I915_WRITE(PLANE_SURF(pipe, plane),
3762                            I915_READ(PLANE_SURF(pipe, plane)));
3763         }
3764         I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3765 }
3766
3767 static bool
3768 skl_ddb_allocation_included(const struct skl_ddb_allocation *old,
3769                             const struct skl_ddb_allocation *new,
3770                             enum pipe pipe)
3771 {
3772         uint16_t old_size, new_size;
3773
3774         old_size = skl_ddb_entry_size(&old->pipe[pipe]);
3775         new_size = skl_ddb_entry_size(&new->pipe[pipe]);
3776
3777         return old_size != new_size &&
3778                new->pipe[pipe].start >= old->pipe[pipe].start &&
3779                new->pipe[pipe].end <= old->pipe[pipe].end;
3780 }
3781
3782 static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
3783                                 struct skl_wm_values *new_values)
3784 {
3785         struct drm_device *dev = &dev_priv->drm;
3786         struct skl_ddb_allocation *cur_ddb, *new_ddb;
3787         bool reallocated[I915_MAX_PIPES] = {};
3788         struct intel_crtc *crtc;
3789         enum pipe pipe;
3790
3791         new_ddb = &new_values->ddb;
3792         cur_ddb = &dev_priv->wm.skl_hw.ddb;
3793
3794         /*
3795          * First pass: flush the pipes with the new allocation contained into
3796          * the old space.
3797          *
3798          * We'll wait for the vblank on those pipes to ensure we can safely
3799          * re-allocate the freed space without this pipe fetching from it.
3800          */
3801         for_each_intel_crtc(dev, crtc) {
3802                 if (!crtc->active)
3803                         continue;
3804
3805                 pipe = crtc->pipe;
3806
3807                 if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe))
3808                         continue;
3809
3810                 skl_wm_flush_pipe(dev_priv, pipe, 1);
3811                 intel_wait_for_vblank(dev, pipe);
3812
3813                 reallocated[pipe] = true;
3814         }
3815
3816
3817         /*
3818          * Second pass: flush the pipes that are having their allocation
3819          * reduced, but overlapping with a previous allocation.
3820          *
3821          * Here as well we need to wait for the vblank to make sure the freed
3822          * space is not used anymore.
3823          */
3824         for_each_intel_crtc(dev, crtc) {
3825                 if (!crtc->active)
3826                         continue;
3827
3828                 pipe = crtc->pipe;
3829
3830                 if (reallocated[pipe])
3831                         continue;
3832
3833                 if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) <
3834                     skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {
3835                         skl_wm_flush_pipe(dev_priv, pipe, 2);
3836                         intel_wait_for_vblank(dev, pipe);
3837                         reallocated[pipe] = true;
3838                 }
3839         }
3840
3841         /*
3842          * Third pass: flush the pipes that got more space allocated.
3843          *
3844          * We don't need to actively wait for the update here, next vblank
3845          * will just get more DDB space with the correct WM values.
3846          */
3847         for_each_intel_crtc(dev, crtc) {
3848                 if (!crtc->active)
3849                         continue;
3850
3851                 pipe = crtc->pipe;
3852
3853                 /*
3854                  * At this point, only the pipes more space than before are
3855                  * left to re-allocate.
3856                  */
3857                 if (reallocated[pipe])
3858                         continue;
3859
3860                 skl_wm_flush_pipe(dev_priv, pipe, 3);
3861         }
3862 }
3863
3864 static int skl_update_pipe_wm(struct drm_crtc_state *cstate,
3865                               struct skl_ddb_allocation *ddb, /* out */
3866                               struct skl_pipe_wm *pipe_wm, /* out */
3867                               bool *changed /* out */)
3868 {
3869         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->crtc);
3870         struct intel_crtc_state *intel_cstate = to_intel_crtc_state(cstate);
3871         int ret;
3872
3873         ret = skl_build_pipe_wm(intel_cstate, ddb, pipe_wm);
3874         if (ret)
3875                 return ret;
3876
3877         if (!memcmp(&intel_crtc->wm.active.skl, pipe_wm, sizeof(*pipe_wm)))
3878                 *changed = false;
3879         else
3880                 *changed = true;
3881
3882         return 0;
3883 }
3884
3885 static uint32_t
3886 pipes_modified(struct drm_atomic_state *state)
3887 {
3888         struct drm_crtc *crtc;
3889         struct drm_crtc_state *cstate;
3890         uint32_t i, ret = 0;
3891
3892         for_each_crtc_in_state(state, crtc, cstate, i)
3893                 ret |= drm_crtc_mask(crtc);
3894
3895         return ret;
3896 }
3897
3898 static int
3899 skl_compute_ddb(struct drm_atomic_state *state)
3900 {
3901         struct drm_device *dev = state->dev;
3902         struct drm_i915_private *dev_priv = to_i915(dev);
3903         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3904         struct intel_crtc *intel_crtc;
3905         struct skl_ddb_allocation *ddb = &intel_state->wm_results.ddb;
3906         uint32_t realloc_pipes = pipes_modified(state);
3907         int ret;
3908
3909         /*
3910          * If this is our first atomic update following hardware readout,
3911          * we can't trust the DDB that the BIOS programmed for us.  Let's
3912          * pretend that all pipes switched active status so that we'll
3913          * ensure a full DDB recompute.
3914          */
3915         if (dev_priv->wm.distrust_bios_wm) {
3916                 ret = drm_modeset_lock(&dev->mode_config.connection_mutex,
3917                                        state->acquire_ctx);
3918                 if (ret)
3919                         return ret;
3920
3921                 intel_state->active_pipe_changes = ~0;
3922
3923                 /*
3924                  * We usually only initialize intel_state->active_crtcs if we
3925                  * we're doing a modeset; make sure this field is always
3926                  * initialized during the sanitization process that happens
3927                  * on the first commit too.
3928                  */
3929                 if (!intel_state->modeset)
3930                         intel_state->active_crtcs = dev_priv->active_crtcs;
3931         }
3932
3933         /*
3934          * If the modeset changes which CRTC's are active, we need to
3935          * recompute the DDB allocation for *all* active pipes, even
3936          * those that weren't otherwise being modified in any way by this
3937          * atomic commit.  Due to the shrinking of the per-pipe allocations
3938          * when new active CRTC's are added, it's possible for a pipe that
3939          * we were already using and aren't changing at all here to suddenly
3940          * become invalid if its DDB needs exceeds its new allocation.
3941          *
3942          * Note that if we wind up doing a full DDB recompute, we can't let
3943          * any other display updates race with this transaction, so we need
3944          * to grab the lock on *all* CRTC's.
3945          */
3946         if (intel_state->active_pipe_changes) {
3947                 realloc_pipes = ~0;
3948                 intel_state->wm_results.dirty_pipes = ~0;
3949         }
3950
3951         for_each_intel_crtc_mask(dev, intel_crtc, realloc_pipes) {
3952                 struct intel_crtc_state *cstate;
3953
3954                 cstate = intel_atomic_get_crtc_state(state, intel_crtc);
3955                 if (IS_ERR(cstate))
3956                         return PTR_ERR(cstate);
3957
3958                 ret = skl_allocate_pipe_ddb(cstate, ddb);
3959                 if (ret)
3960                         return ret;
3961         }
3962
3963         return 0;
3964 }
3965
3966 static int
3967 skl_compute_wm(struct drm_atomic_state *state)
3968 {
3969         struct drm_crtc *crtc;
3970         struct drm_crtc_state *cstate;
3971         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3972         struct skl_wm_values *results = &intel_state->wm_results;
3973         struct skl_pipe_wm *pipe_wm;
3974         bool changed = false;
3975         int ret, i;
3976
3977         /*
3978          * If this transaction isn't actually touching any CRTC's, don't
3979          * bother with watermark calculation.  Note that if we pass this
3980          * test, we're guaranteed to hold at least one CRTC state mutex,
3981          * which means we can safely use values like dev_priv->active_crtcs
3982          * since any racing commits that want to update them would need to
3983          * hold _all_ CRTC state mutexes.
3984          */
3985         for_each_crtc_in_state(state, crtc, cstate, i)
3986                 changed = true;
3987         if (!changed)
3988                 return 0;
3989
3990         /* Clear all dirty flags */
3991         results->dirty_pipes = 0;
3992
3993         ret = skl_compute_ddb(state);
3994         if (ret)
3995                 return ret;
3996
3997         /*
3998          * Calculate WM's for all pipes that are part of this transaction.
3999          * Note that the DDB allocation above may have added more CRTC's that
4000          * weren't otherwise being modified (and set bits in dirty_pipes) if
4001          * pipe allocations had to change.
4002          *
4003          * FIXME:  Now that we're doing this in the atomic check phase, we
4004          * should allow skl_update_pipe_wm() to return failure in cases where
4005          * no suitable watermark values can be found.
4006          */
4007         for_each_crtc_in_state(state, crtc, cstate, i) {
4008                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4009                 struct intel_crtc_state *intel_cstate =
4010                         to_intel_crtc_state(cstate);
4011
4012                 pipe_wm = &intel_cstate->wm.skl.optimal;
4013                 ret = skl_update_pipe_wm(cstate, &results->ddb, pipe_wm,
4014                                          &changed);
4015                 if (ret)
4016                         return ret;
4017
4018                 if (changed)
4019                         results->dirty_pipes |= drm_crtc_mask(crtc);
4020
4021                 if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0)
4022                         /* This pipe's WM's did not change */
4023                         continue;
4024
4025                 intel_cstate->update_wm_pre = true;
4026                 skl_compute_wm_results(crtc->dev, pipe_wm, results, intel_crtc);
4027         }
4028
4029         return 0;
4030 }
4031
4032 static void skl_update_wm(struct drm_crtc *crtc)
4033 {
4034         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4035         struct drm_device *dev = crtc->dev;
4036         struct drm_i915_private *dev_priv = to_i915(dev);
4037         struct skl_wm_values *results = &dev_priv->wm.skl_results;
4038         struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
4039         struct skl_pipe_wm *pipe_wm = &cstate->wm.skl.optimal;
4040
4041         if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0)
4042                 return;
4043
4044         intel_crtc->wm.active.skl = *pipe_wm;
4045
4046         mutex_lock(&dev_priv->wm.wm_mutex);
4047
4048         skl_write_wm_values(dev_priv, results);
4049         skl_flush_wm_values(dev_priv, results);
4050
4051         /* store the new configuration */
4052         dev_priv->wm.skl_hw = *results;
4053
4054         mutex_unlock(&dev_priv->wm.wm_mutex);
4055 }
4056
4057 static void ilk_compute_wm_config(struct drm_device *dev,
4058                                   struct intel_wm_config *config)
4059 {
4060         struct intel_crtc *crtc;
4061
4062         /* Compute the currently _active_ config */
4063         for_each_intel_crtc(dev, crtc) {
4064                 const struct intel_pipe_wm *wm = &crtc->wm.active.ilk;
4065
4066                 if (!wm->pipe_enabled)
4067                         continue;
4068
4069                 config->sprites_enabled |= wm->sprites_enabled;
4070                 config->sprites_scaled |= wm->sprites_scaled;
4071                 config->num_pipes_active++;
4072         }
4073 }
4074
4075 static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
4076 {
4077         struct drm_device *dev = &dev_priv->drm;
4078         struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
4079         struct ilk_wm_maximums max;
4080         struct intel_wm_config config = {};
4081         struct ilk_wm_values results = {};
4082         enum intel_ddb_partitioning partitioning;
4083
4084         ilk_compute_wm_config(dev, &config);
4085
4086         ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
4087         ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
4088
4089         /* 5/6 split only in single pipe config on IVB+ */
4090         if (INTEL_INFO(dev)->gen >= 7 &&
4091             config.num_pipes_active == 1 && config.sprites_enabled) {
4092                 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
4093                 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
4094
4095                 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
4096         } else {
4097                 best_lp_wm = &lp_wm_1_2;
4098         }
4099
4100         partitioning = (best_lp_wm == &lp_wm_1_2) ?
4101                        INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
4102
4103         ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
4104
4105         ilk_write_wm_values(dev_priv, &results);
4106 }
4107
4108 static void ilk_initial_watermarks(struct intel_crtc_state *cstate)
4109 {
4110         struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
4111         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
4112
4113         mutex_lock(&dev_priv->wm.wm_mutex);
4114         intel_crtc->wm.active.ilk = cstate->wm.ilk.intermediate;
4115         ilk_program_watermarks(dev_priv);
4116         mutex_unlock(&dev_priv->wm.wm_mutex);
4117 }
4118
4119 static void ilk_optimize_watermarks(struct intel_crtc_state *cstate)
4120 {
4121         struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
4122         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
4123
4124         mutex_lock(&dev_priv->wm.wm_mutex);
4125         if (cstate->wm.need_postvbl_update) {
4126                 intel_crtc->wm.active.ilk = cstate->wm.ilk.optimal;
4127                 ilk_program_watermarks(dev_priv);
4128         }
4129         mutex_unlock(&dev_priv->wm.wm_mutex);
4130 }
4131
4132 static void skl_pipe_wm_active_state(uint32_t val,
4133                                      struct skl_pipe_wm *active,
4134                                      bool is_transwm,
4135                                      bool is_cursor,
4136                                      int i,
4137                                      int level)
4138 {
4139         bool is_enabled = (val & PLANE_WM_EN) != 0;
4140
4141         if (!is_transwm) {
4142                 if (!is_cursor) {
4143                         active->wm[level].plane_en[i] = is_enabled;
4144                         active->wm[level].plane_res_b[i] =
4145                                         val & PLANE_WM_BLOCKS_MASK;
4146                         active->wm[level].plane_res_l[i] =
4147                                         (val >> PLANE_WM_LINES_SHIFT) &
4148                                                 PLANE_WM_LINES_MASK;
4149                 } else {
4150                         active->wm[level].plane_en[PLANE_CURSOR] = is_enabled;
4151                         active->wm[level].plane_res_b[PLANE_CURSOR] =
4152                                         val & PLANE_WM_BLOCKS_MASK;
4153                         active->wm[level].plane_res_l[PLANE_CURSOR] =
4154                                         (val >> PLANE_WM_LINES_SHIFT) &
4155                                                 PLANE_WM_LINES_MASK;
4156                 }
4157         } else {
4158                 if (!is_cursor) {
4159                         active->trans_wm.plane_en[i] = is_enabled;
4160                         active->trans_wm.plane_res_b[i] =
4161                                         val & PLANE_WM_BLOCKS_MASK;
4162                         active->trans_wm.plane_res_l[i] =
4163                                         (val >> PLANE_WM_LINES_SHIFT) &
4164                                                 PLANE_WM_LINES_MASK;
4165                 } else {
4166                         active->trans_wm.plane_en[PLANE_CURSOR] = is_enabled;
4167                         active->trans_wm.plane_res_b[PLANE_CURSOR] =
4168                                         val & PLANE_WM_BLOCKS_MASK;
4169                         active->trans_wm.plane_res_l[PLANE_CURSOR] =
4170                                         (val >> PLANE_WM_LINES_SHIFT) &
4171                                                 PLANE_WM_LINES_MASK;
4172                 }
4173         }
4174 }
4175
4176 static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
4177 {
4178         struct drm_device *dev = crtc->dev;
4179         struct drm_i915_private *dev_priv = to_i915(dev);
4180         struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
4181         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4182         struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
4183         struct skl_pipe_wm *active = &cstate->wm.skl.optimal;
4184         enum pipe pipe = intel_crtc->pipe;
4185         int level, i, max_level;
4186         uint32_t temp;
4187
4188         max_level = ilk_wm_max_level(dev);
4189
4190         hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
4191
4192         for (level = 0; level <= max_level; level++) {
4193                 for (i = 0; i < intel_num_planes(intel_crtc); i++)
4194                         hw->plane[pipe][i][level] =
4195                                         I915_READ(PLANE_WM(pipe, i, level));
4196                 hw->plane[pipe][PLANE_CURSOR][level] = I915_READ(CUR_WM(pipe, level));
4197         }
4198
4199         for (i = 0; i < intel_num_planes(intel_crtc); i++)
4200                 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
4201         hw->plane_trans[pipe][PLANE_CURSOR] = I915_READ(CUR_WM_TRANS(pipe));
4202
4203         if (!intel_crtc->active)
4204                 return;
4205
4206         hw->dirty_pipes |= drm_crtc_mask(crtc);
4207
4208         active->linetime = hw->wm_linetime[pipe];
4209
4210         for (level = 0; level <= max_level; level++) {
4211                 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
4212                         temp = hw->plane[pipe][i][level];
4213                         skl_pipe_wm_active_state(temp, active, false,
4214                                                 false, i, level);
4215                 }
4216                 temp = hw->plane[pipe][PLANE_CURSOR][level];
4217                 skl_pipe_wm_active_state(temp, active, false, true, i, level);
4218         }
4219
4220         for (i = 0; i < intel_num_planes(intel_crtc); i++) {
4221                 temp = hw->plane_trans[pipe][i];
4222                 skl_pipe_wm_active_state(temp, active, true, false, i, 0);
4223         }
4224
4225         temp = hw->plane_trans[pipe][PLANE_CURSOR];
4226         skl_pipe_wm_active_state(temp, active, true, true, i, 0);
4227
4228         intel_crtc->wm.active.skl = *active;
4229 }
4230
4231 void skl_wm_get_hw_state(struct drm_device *dev)
4232 {
4233         struct drm_i915_private *dev_priv = to_i915(dev);
4234         struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
4235         struct drm_crtc *crtc;
4236
4237         skl_ddb_get_hw_state(dev_priv, ddb);
4238         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
4239                 skl_pipe_wm_get_hw_state(crtc);
4240
4241         if (dev_priv->active_crtcs) {
4242                 /* Fully recompute DDB on first atomic commit */
4243                 dev_priv->wm.distrust_bios_wm = true;
4244         } else {
4245                 /* Easy/common case; just sanitize DDB now if everything off */
4246                 memset(ddb, 0, sizeof(*ddb));
4247         }
4248 }
4249
4250 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
4251 {
4252         struct drm_device *dev = crtc->dev;
4253         struct drm_i915_private *dev_priv = to_i915(dev);
4254         struct ilk_wm_values *hw = &dev_priv->wm.hw;
4255         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4256         struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
4257         struct intel_pipe_wm *active = &cstate->wm.ilk.optimal;
4258         enum pipe pipe = intel_crtc->pipe;
4259         static const i915_reg_t wm0_pipe_reg[] = {
4260                 [PIPE_A] = WM0_PIPEA_ILK,
4261                 [PIPE_B] = WM0_PIPEB_ILK,
4262                 [PIPE_C] = WM0_PIPEC_IVB,
4263         };
4264
4265         hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
4266         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4267                 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
4268
4269         memset(active, 0, sizeof(*active));
4270
4271         active->pipe_enabled = intel_crtc->active;
4272
4273         if (active->pipe_enabled) {
4274                 u32 tmp = hw->wm_pipe[pipe];
4275
4276                 /*
4277                  * For active pipes LP0 watermark is marked as
4278                  * enabled, and LP1+ watermaks as disabled since
4279                  * we can't really reverse compute them in case
4280                  * multiple pipes are active.
4281                  */
4282                 active->wm[0].enable = true;
4283                 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
4284                 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
4285                 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
4286                 active->linetime = hw->wm_linetime[pipe];
4287         } else {
4288                 int level, max_level = ilk_wm_max_level(dev);
4289
4290                 /*
4291                  * For inactive pipes, all watermark levels
4292                  * should be marked as enabled but zeroed,
4293                  * which is what we'd compute them to.
4294                  */
4295                 for (level = 0; level <= max_level; level++)
4296                         active->wm[level].enable = true;
4297         }
4298
4299         intel_crtc->wm.active.ilk = *active;
4300 }
4301
4302 #define _FW_WM(value, plane) \
4303         (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
4304 #define _FW_WM_VLV(value, plane) \
4305         (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
4306
4307 static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
4308                                struct vlv_wm_values *wm)
4309 {
4310         enum pipe pipe;
4311         uint32_t tmp;
4312
4313         for_each_pipe(dev_priv, pipe) {
4314                 tmp = I915_READ(VLV_DDL(pipe));
4315
4316                 wm->ddl[pipe].primary =
4317                         (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4318                 wm->ddl[pipe].cursor =
4319                         (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4320                 wm->ddl[pipe].sprite[0] =
4321                         (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4322                 wm->ddl[pipe].sprite[1] =
4323                         (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4324         }
4325
4326         tmp = I915_READ(DSPFW1);
4327         wm->sr.plane = _FW_WM(tmp, SR);
4328         wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB);
4329         wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB);
4330         wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA);
4331
4332         tmp = I915_READ(DSPFW2);
4333         wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB);
4334         wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA);
4335         wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA);
4336
4337         tmp = I915_READ(DSPFW3);
4338         wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
4339
4340         if (IS_CHERRYVIEW(dev_priv)) {
4341                 tmp = I915_READ(DSPFW7_CHV);
4342                 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4343                 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4344
4345                 tmp = I915_READ(DSPFW8_CHV);
4346                 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF);
4347                 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE);
4348
4349                 tmp = I915_READ(DSPFW9_CHV);
4350                 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC);
4351                 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC);
4352
4353                 tmp = I915_READ(DSPHOWM);
4354                 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4355                 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
4356                 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
4357                 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8;
4358                 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4359                 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4360                 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4361                 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4362                 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4363                 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4364         } else {
4365                 tmp = I915_READ(DSPFW7);
4366                 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4367                 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4368
4369                 tmp = I915_READ(DSPHOWM);
4370                 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4371                 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4372                 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4373                 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4374                 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4375                 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4376                 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4377         }
4378 }
4379
4380 #undef _FW_WM
4381 #undef _FW_WM_VLV
4382
4383 void vlv_wm_get_hw_state(struct drm_device *dev)
4384 {
4385         struct drm_i915_private *dev_priv = to_i915(dev);
4386         struct vlv_wm_values *wm = &dev_priv->wm.vlv;
4387         struct intel_plane *plane;
4388         enum pipe pipe;
4389         u32 val;
4390
4391         vlv_read_wm_values(dev_priv, wm);
4392
4393         for_each_intel_plane(dev, plane) {
4394                 switch (plane->base.type) {
4395                         int sprite;
4396                 case DRM_PLANE_TYPE_CURSOR:
4397                         plane->wm.fifo_size = 63;
4398                         break;
4399                 case DRM_PLANE_TYPE_PRIMARY:
4400                         plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0);
4401                         break;
4402                 case DRM_PLANE_TYPE_OVERLAY:
4403                         sprite = plane->plane;
4404                         plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1);
4405                         break;
4406                 }
4407         }
4408
4409         wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4410         wm->level = VLV_WM_LEVEL_PM2;
4411
4412         if (IS_CHERRYVIEW(dev_priv)) {
4413                 mutex_lock(&dev_priv->rps.hw_lock);
4414
4415                 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4416                 if (val & DSP_MAXFIFO_PM5_ENABLE)
4417                         wm->level = VLV_WM_LEVEL_PM5;
4418
4419                 /*
4420                  * If DDR DVFS is disabled in the BIOS, Punit
4421                  * will never ack the request. So if that happens
4422                  * assume we don't have to enable/disable DDR DVFS
4423                  * dynamically. To test that just set the REQ_ACK
4424                  * bit to poke the Punit, but don't change the
4425                  * HIGH/LOW bits so that we don't actually change
4426                  * the current state.
4427                  */
4428                 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4429                 val |= FORCE_DDR_FREQ_REQ_ACK;
4430                 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
4431
4432                 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
4433                               FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
4434                         DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
4435                                       "assuming DDR DVFS is disabled\n");
4436                         dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
4437                 } else {
4438                         val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4439                         if ((val & FORCE_DDR_HIGH_FREQ) == 0)
4440                                 wm->level = VLV_WM_LEVEL_DDR_DVFS;
4441                 }
4442
4443                 mutex_unlock(&dev_priv->rps.hw_lock);
4444         }
4445
4446         for_each_pipe(dev_priv, pipe)
4447                 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4448                               pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor,
4449                               wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]);
4450
4451         DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4452                       wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
4453 }
4454
4455 void ilk_wm_get_hw_state(struct drm_device *dev)
4456 {
4457         struct drm_i915_private *dev_priv = to_i915(dev);
4458         struct ilk_wm_values *hw = &dev_priv->wm.hw;
4459         struct drm_crtc *crtc;
4460
4461         for_each_crtc(dev, crtc)
4462                 ilk_pipe_wm_get_hw_state(crtc);
4463
4464         hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
4465         hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
4466         hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
4467
4468         hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
4469         if (INTEL_INFO(dev)->gen >= 7) {
4470                 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
4471                 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
4472         }
4473
4474         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4475                 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
4476                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4477         else if (IS_IVYBRIDGE(dev))
4478                 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
4479                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4480
4481         hw->enable_fbc_wm =
4482                 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
4483 }
4484
4485 /**
4486  * intel_update_watermarks - update FIFO watermark values based on current modes
4487  *
4488  * Calculate watermark values for the various WM regs based on current mode
4489  * and plane configuration.
4490  *
4491  * There are several cases to deal with here:
4492  *   - normal (i.e. non-self-refresh)
4493  *   - self-refresh (SR) mode
4494  *   - lines are large relative to FIFO size (buffer can hold up to 2)
4495  *   - lines are small relative to FIFO size (buffer can hold more than 2
4496  *     lines), so need to account for TLB latency
4497  *
4498  *   The normal calculation is:
4499  *     watermark = dotclock * bytes per pixel * latency
4500  *   where latency is platform & configuration dependent (we assume pessimal
4501  *   values here).
4502  *
4503  *   The SR calculation is:
4504  *     watermark = (trunc(latency/line time)+1) * surface width *
4505  *       bytes per pixel
4506  *   where
4507  *     line time = htotal / dotclock
4508  *     surface width = hdisplay for normal plane and 64 for cursor
4509  *   and latency is assumed to be high, as above.
4510  *
4511  * The final value programmed to the register should always be rounded up,
4512  * and include an extra 2 entries to account for clock crossings.
4513  *
4514  * We don't use the sprite, so we can ignore that.  And on Crestline we have
4515  * to set the non-SR watermarks to 8.
4516  */
4517 void intel_update_watermarks(struct drm_crtc *crtc)
4518 {
4519         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
4520
4521         if (dev_priv->display.update_wm)
4522                 dev_priv->display.update_wm(crtc);
4523 }
4524
4525 /*
4526  * Lock protecting IPS related data structures
4527  */
4528 DEFINE_SPINLOCK(mchdev_lock);
4529
4530 /* Global for IPS driver to get at the current i915 device. Protected by
4531  * mchdev_lock. */
4532 static struct drm_i915_private *i915_mch_dev;
4533
4534 bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val)
4535 {
4536         u16 rgvswctl;
4537
4538         assert_spin_locked(&mchdev_lock);
4539
4540         rgvswctl = I915_READ16(MEMSWCTL);
4541         if (rgvswctl & MEMCTL_CMD_STS) {
4542                 DRM_DEBUG("gpu busy, RCS change rejected\n");
4543                 return false; /* still busy with another command */
4544         }
4545
4546         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4547                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4548         I915_WRITE16(MEMSWCTL, rgvswctl);
4549         POSTING_READ16(MEMSWCTL);
4550
4551         rgvswctl |= MEMCTL_CMD_STS;
4552         I915_WRITE16(MEMSWCTL, rgvswctl);
4553
4554         return true;
4555 }
4556
4557 static void ironlake_enable_drps(struct drm_i915_private *dev_priv)
4558 {
4559         u32 rgvmodectl;
4560         u8 fmax, fmin, fstart, vstart;
4561
4562         spin_lock_irq(&mchdev_lock);
4563
4564         rgvmodectl = I915_READ(MEMMODECTL);
4565
4566         /* Enable temp reporting */
4567         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4568         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4569
4570         /* 100ms RC evaluation intervals */
4571         I915_WRITE(RCUPEI, 100000);
4572         I915_WRITE(RCDNEI, 100000);
4573
4574         /* Set max/min thresholds to 90ms and 80ms respectively */
4575         I915_WRITE(RCBMAXAVG, 90000);
4576         I915_WRITE(RCBMINAVG, 80000);
4577
4578         I915_WRITE(MEMIHYST, 1);
4579
4580         /* Set up min, max, and cur for interrupt handling */
4581         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4582         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4583         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4584                 MEMMODE_FSTART_SHIFT;
4585
4586         vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
4587                 PXVFREQ_PX_SHIFT;
4588
4589         dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4590         dev_priv->ips.fstart = fstart;
4591
4592         dev_priv->ips.max_delay = fstart;
4593         dev_priv->ips.min_delay = fmin;
4594         dev_priv->ips.cur_delay = fstart;
4595
4596         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4597                          fmax, fmin, fstart);
4598
4599         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4600
4601         /*
4602          * Interrupts will be enabled in ironlake_irq_postinstall
4603          */
4604
4605         I915_WRITE(VIDSTART, vstart);
4606         POSTING_READ(VIDSTART);
4607
4608         rgvmodectl |= MEMMODE_SWMODE_EN;
4609         I915_WRITE(MEMMODECTL, rgvmodectl);
4610
4611         if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
4612                 DRM_ERROR("stuck trying to change perf mode\n");
4613         mdelay(1);
4614
4615         ironlake_set_drps(dev_priv, fstart);
4616
4617         dev_priv->ips.last_count1 = I915_READ(DMIEC) +
4618                 I915_READ(DDREC) + I915_READ(CSIEC);
4619         dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
4620         dev_priv->ips.last_count2 = I915_READ(GFXEC);
4621         dev_priv->ips.last_time2 = ktime_get_raw_ns();
4622
4623         spin_unlock_irq(&mchdev_lock);
4624 }
4625
4626 static void ironlake_disable_drps(struct drm_i915_private *dev_priv)
4627 {
4628         u16 rgvswctl;
4629
4630         spin_lock_irq(&mchdev_lock);
4631
4632         rgvswctl = I915_READ16(MEMSWCTL);
4633
4634         /* Ack interrupts, disable EFC interrupt */
4635         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4636         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4637         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4638         I915_WRITE(DEIIR, DE_PCU_EVENT);
4639         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4640
4641         /* Go back to the starting frequency */
4642         ironlake_set_drps(dev_priv, dev_priv->ips.fstart);
4643         mdelay(1);
4644         rgvswctl |= MEMCTL_CMD_STS;
4645         I915_WRITE(MEMSWCTL, rgvswctl);
4646         mdelay(1);
4647
4648         spin_unlock_irq(&mchdev_lock);
4649 }
4650
4651 /* There's a funny hw issue where the hw returns all 0 when reading from
4652  * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4653  * ourselves, instead of doing a rmw cycle (which might result in us clearing
4654  * all limits and the gpu stuck at whatever frequency it is at atm).
4655  */
4656 static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
4657 {
4658         u32 limits;
4659
4660         /* Only set the down limit when we've reached the lowest level to avoid
4661          * getting more interrupts, otherwise leave this clear. This prevents a
4662          * race in the hw when coming out of rc6: There's a tiny window where
4663          * the hw runs at the minimal clock before selecting the desired
4664          * frequency, if the down threshold expires in that window we will not
4665          * receive a down interrupt. */
4666         if (IS_GEN9(dev_priv)) {
4667                 limits = (dev_priv->rps.max_freq_softlimit) << 23;
4668                 if (val <= dev_priv->rps.min_freq_softlimit)
4669                         limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4670         } else {
4671                 limits = dev_priv->rps.max_freq_softlimit << 24;
4672                 if (val <= dev_priv->rps.min_freq_softlimit)
4673                         limits |= dev_priv->rps.min_freq_softlimit << 16;
4674         }
4675
4676         return limits;
4677 }
4678
4679 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4680 {
4681         int new_power;
4682         u32 threshold_up = 0, threshold_down = 0; /* in % */
4683         u32 ei_up = 0, ei_down = 0;
4684
4685         new_power = dev_priv->rps.power;
4686         switch (dev_priv->rps.power) {
4687         case LOW_POWER:
4688                 if (val > dev_priv->rps.efficient_freq + 1 &&
4689                     val > dev_priv->rps.cur_freq)
4690                         new_power = BETWEEN;
4691                 break;
4692
4693         case BETWEEN:
4694                 if (val <= dev_priv->rps.efficient_freq &&
4695                     val < dev_priv->rps.cur_freq)
4696                         new_power = LOW_POWER;
4697                 else if (val >= dev_priv->rps.rp0_freq &&
4698                          val > dev_priv->rps.cur_freq)
4699                         new_power = HIGH_POWER;
4700                 break;
4701
4702         case HIGH_POWER:
4703                 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 &&
4704                     val < dev_priv->rps.cur_freq)
4705                         new_power = BETWEEN;
4706                 break;
4707         }
4708         /* Max/min bins are special */
4709         if (val <= dev_priv->rps.min_freq_softlimit)
4710                 new_power = LOW_POWER;
4711         if (val >= dev_priv->rps.max_freq_softlimit)
4712                 new_power = HIGH_POWER;
4713         if (new_power == dev_priv->rps.power)
4714                 return;
4715
4716         /* Note the units here are not exactly 1us, but 1280ns. */
4717         switch (new_power) {
4718         case LOW_POWER:
4719                 /* Upclock if more than 95% busy over 16ms */
4720                 ei_up = 16000;
4721                 threshold_up = 95;
4722
4723                 /* Downclock if less than 85% busy over 32ms */
4724                 ei_down = 32000;
4725                 threshold_down = 85;
4726                 break;
4727
4728         case BETWEEN:
4729                 /* Upclock if more than 90% busy over 13ms */
4730                 ei_up = 13000;
4731                 threshold_up = 90;
4732
4733                 /* Downclock if less than 75% busy over 32ms */
4734                 ei_down = 32000;
4735                 threshold_down = 75;
4736                 break;
4737
4738         case HIGH_POWER:
4739                 /* Upclock if more than 85% busy over 10ms */
4740                 ei_up = 10000;
4741                 threshold_up = 85;
4742
4743                 /* Downclock if less than 60% busy over 32ms */
4744                 ei_down = 32000;
4745                 threshold_down = 60;
4746                 break;
4747         }
4748
4749         I915_WRITE(GEN6_RP_UP_EI,
4750                    GT_INTERVAL_FROM_US(dev_priv, ei_up));
4751         I915_WRITE(GEN6_RP_UP_THRESHOLD,
4752                    GT_INTERVAL_FROM_US(dev_priv,
4753                                        ei_up * threshold_up / 100));
4754
4755         I915_WRITE(GEN6_RP_DOWN_EI,
4756                    GT_INTERVAL_FROM_US(dev_priv, ei_down));
4757         I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
4758                    GT_INTERVAL_FROM_US(dev_priv,
4759                                        ei_down * threshold_down / 100));
4760
4761         I915_WRITE(GEN6_RP_CONTROL,
4762                    GEN6_RP_MEDIA_TURBO |
4763                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
4764                    GEN6_RP_MEDIA_IS_GFX |
4765                    GEN6_RP_ENABLE |
4766                    GEN6_RP_UP_BUSY_AVG |
4767                    GEN6_RP_DOWN_IDLE_AVG);
4768
4769         dev_priv->rps.power = new_power;
4770         dev_priv->rps.up_threshold = threshold_up;
4771         dev_priv->rps.down_threshold = threshold_down;
4772         dev_priv->rps.last_adj = 0;
4773 }
4774
4775 static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4776 {
4777         u32 mask = 0;
4778
4779         if (val > dev_priv->rps.min_freq_softlimit)
4780                 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
4781         if (val < dev_priv->rps.max_freq_softlimit)
4782                 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
4783
4784         mask &= dev_priv->pm_rps_events;
4785
4786         return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
4787 }
4788
4789 /* gen6_set_rps is called to update the frequency request, but should also be
4790  * called when the range (min_delay and max_delay) is modified so that we can
4791  * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
4792 static void gen6_set_rps(struct drm_i915_private *dev_priv, u8 val)
4793 {
4794         /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
4795         if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
4796                 return;
4797
4798         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4799         WARN_ON(val > dev_priv->rps.max_freq);
4800         WARN_ON(val < dev_priv->rps.min_freq);
4801
4802         /* min/max delay may still have been modified so be sure to
4803          * write the limits value.
4804          */
4805         if (val != dev_priv->rps.cur_freq) {
4806                 gen6_set_rps_thresholds(dev_priv, val);
4807
4808                 if (IS_GEN9(dev_priv))
4809                         I915_WRITE(GEN6_RPNSWREQ,
4810                                    GEN9_FREQUENCY(val));
4811                 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
4812                         I915_WRITE(GEN6_RPNSWREQ,
4813                                    HSW_FREQUENCY(val));
4814                 else
4815                         I915_WRITE(GEN6_RPNSWREQ,
4816                                    GEN6_FREQUENCY(val) |
4817                                    GEN6_OFFSET(0) |
4818                                    GEN6_AGGRESSIVE_TURBO);
4819         }
4820
4821         /* Make sure we continue to get interrupts
4822          * until we hit the minimum or maximum frequencies.
4823          */
4824         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
4825         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4826
4827         POSTING_READ(GEN6_RPNSWREQ);
4828
4829         dev_priv->rps.cur_freq = val;
4830         trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4831 }
4832
4833 static void valleyview_set_rps(struct drm_i915_private *dev_priv, u8 val)
4834 {
4835         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4836         WARN_ON(val > dev_priv->rps.max_freq);
4837         WARN_ON(val < dev_priv->rps.min_freq);
4838
4839         if (WARN_ONCE(IS_CHERRYVIEW(dev_priv) && (val & 1),
4840                       "Odd GPU freq value\n"))
4841                 val &= ~1;
4842
4843         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4844
4845         if (val != dev_priv->rps.cur_freq) {
4846                 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
4847                 if (!IS_CHERRYVIEW(dev_priv))
4848                         gen6_set_rps_thresholds(dev_priv, val);
4849         }
4850
4851         dev_priv->rps.cur_freq = val;
4852         trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4853 }
4854
4855 /* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
4856  *
4857  * * If Gfx is Idle, then
4858  * 1. Forcewake Media well.
4859  * 2. Request idle freq.
4860  * 3. Release Forcewake of Media well.
4861 */
4862 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
4863 {
4864         u32 val = dev_priv->rps.idle_freq;
4865
4866         if (dev_priv->rps.cur_freq <= val)
4867                 return;
4868
4869         /* Wake up the media well, as that takes a lot less
4870          * power than the Render well. */
4871         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
4872         valleyview_set_rps(dev_priv, val);
4873         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
4874 }
4875
4876 void gen6_rps_busy(struct drm_i915_private *dev_priv)
4877 {
4878         mutex_lock(&dev_priv->rps.hw_lock);
4879         if (dev_priv->rps.enabled) {
4880                 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
4881                         gen6_rps_reset_ei(dev_priv);
4882                 I915_WRITE(GEN6_PMINTRMSK,
4883                            gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
4884
4885                 gen6_enable_rps_interrupts(dev_priv);
4886
4887                 /* Ensure we start at the user's desired frequency */
4888                 intel_set_rps(dev_priv,
4889                               clamp(dev_priv->rps.cur_freq,
4890                                     dev_priv->rps.min_freq_softlimit,
4891                                     dev_priv->rps.max_freq_softlimit));
4892         }
4893         mutex_unlock(&dev_priv->rps.hw_lock);
4894 }
4895
4896 void gen6_rps_idle(struct drm_i915_private *dev_priv)
4897 {
4898         /* Flush our bottom-half so that it does not race with us
4899          * setting the idle frequency and so that it is bounded by
4900          * our rpm wakeref. And then disable the interrupts to stop any
4901          * futher RPS reclocking whilst we are asleep.
4902          */
4903         gen6_disable_rps_interrupts(dev_priv);
4904
4905         mutex_lock(&dev_priv->rps.hw_lock);
4906         if (dev_priv->rps.enabled) {
4907                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4908                         vlv_set_rps_idle(dev_priv);
4909                 else
4910                         gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
4911                 dev_priv->rps.last_adj = 0;
4912                 I915_WRITE(GEN6_PMINTRMSK,
4913                            gen6_sanitize_rps_pm_mask(dev_priv, ~0));
4914         }
4915         mutex_unlock(&dev_priv->rps.hw_lock);
4916
4917         spin_lock(&dev_priv->rps.client_lock);
4918         while (!list_empty(&dev_priv->rps.clients))
4919                 list_del_init(dev_priv->rps.clients.next);
4920         spin_unlock(&dev_priv->rps.client_lock);
4921 }
4922
4923 void gen6_rps_boost(struct drm_i915_private *dev_priv,
4924                     struct intel_rps_client *rps,
4925                     unsigned long submitted)
4926 {
4927         /* This is intentionally racy! We peek at the state here, then
4928          * validate inside the RPS worker.
4929          */
4930         if (!(dev_priv->gt.awake &&
4931               dev_priv->rps.enabled &&
4932               dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit))
4933                 return;
4934
4935         /* Force a RPS boost (and don't count it against the client) if
4936          * the GPU is severely congested.
4937          */
4938         if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
4939                 rps = NULL;
4940
4941         spin_lock(&dev_priv->rps.client_lock);
4942         if (rps == NULL || list_empty(&rps->link)) {
4943                 spin_lock_irq(&dev_priv->irq_lock);
4944                 if (dev_priv->rps.interrupts_enabled) {
4945                         dev_priv->rps.client_boost = true;
4946                         schedule_work(&dev_priv->rps.work);
4947                 }
4948                 spin_unlock_irq(&dev_priv->irq_lock);
4949
4950                 if (rps != NULL) {
4951                         list_add(&rps->link, &dev_priv->rps.clients);
4952                         rps->boosts++;
4953                 } else
4954                         dev_priv->rps.boosts++;
4955         }
4956         spin_unlock(&dev_priv->rps.client_lock);
4957 }
4958
4959 void intel_set_rps(struct drm_i915_private *dev_priv, u8 val)
4960 {
4961         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4962                 valleyview_set_rps(dev_priv, val);
4963         else
4964                 gen6_set_rps(dev_priv, val);
4965 }
4966
4967 static void gen9_disable_rc6(struct drm_i915_private *dev_priv)
4968 {
4969         I915_WRITE(GEN6_RC_CONTROL, 0);
4970         I915_WRITE(GEN9_PG_ENABLE, 0);
4971 }
4972
4973 static void gen9_disable_rps(struct drm_i915_private *dev_priv)
4974 {
4975         I915_WRITE(GEN6_RP_CONTROL, 0);
4976 }
4977
4978 static void gen6_disable_rps(struct drm_i915_private *dev_priv)
4979 {
4980         I915_WRITE(GEN6_RC_CONTROL, 0);
4981         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
4982         I915_WRITE(GEN6_RP_CONTROL, 0);
4983 }
4984
4985 static void cherryview_disable_rps(struct drm_i915_private *dev_priv)
4986 {
4987         I915_WRITE(GEN6_RC_CONTROL, 0);
4988 }
4989
4990 static void valleyview_disable_rps(struct drm_i915_private *dev_priv)
4991 {
4992         /* we're doing forcewake before Disabling RC6,
4993          * This what the BIOS expects when going into suspend */
4994         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4995
4996         I915_WRITE(GEN6_RC_CONTROL, 0);
4997
4998         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4999 }
5000
5001 static void intel_print_rc6_info(struct drm_i915_private *dev_priv, u32 mode)
5002 {
5003         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5004                 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
5005                         mode = GEN6_RC_CTL_RC6_ENABLE;
5006                 else
5007                         mode = 0;
5008         }
5009         if (HAS_RC6p(dev_priv))
5010                 DRM_DEBUG_DRIVER("Enabling RC6 states: "
5011                                  "RC6 %s RC6p %s RC6pp %s\n",
5012                                  onoff(mode & GEN6_RC_CTL_RC6_ENABLE),
5013                                  onoff(mode & GEN6_RC_CTL_RC6p_ENABLE),
5014                                  onoff(mode & GEN6_RC_CTL_RC6pp_ENABLE));
5015
5016         else
5017                 DRM_DEBUG_DRIVER("Enabling RC6 states: RC6 %s\n",
5018                                  onoff(mode & GEN6_RC_CTL_RC6_ENABLE));
5019 }
5020
5021 static bool bxt_check_bios_rc6_setup(struct drm_i915_private *dev_priv)
5022 {
5023         struct i915_ggtt *ggtt = &dev_priv->ggtt;
5024         bool enable_rc6 = true;
5025         unsigned long rc6_ctx_base;
5026         u32 rc_ctl;
5027         int rc_sw_target;
5028
5029         rc_ctl = I915_READ(GEN6_RC_CONTROL);
5030         rc_sw_target = (I915_READ(GEN6_RC_STATE) & RC_SW_TARGET_STATE_MASK) >>
5031                        RC_SW_TARGET_STATE_SHIFT;
5032         DRM_DEBUG_DRIVER("BIOS enabled RC states: "
5033                          "HW_CTRL %s HW_RC6 %s SW_TARGET_STATE %x\n",
5034                          onoff(rc_ctl & GEN6_RC_CTL_HW_ENABLE),
5035                          onoff(rc_ctl & GEN6_RC_CTL_RC6_ENABLE),
5036                          rc_sw_target);
5037
5038         if (!(I915_READ(RC6_LOCATION) & RC6_CTX_IN_DRAM)) {
5039                 DRM_DEBUG_DRIVER("RC6 Base location not set properly.\n");
5040                 enable_rc6 = false;
5041         }
5042
5043         /*
5044          * The exact context size is not known for BXT, so assume a page size
5045          * for this check.
5046          */
5047         rc6_ctx_base = I915_READ(RC6_CTX_BASE) & RC6_CTX_BASE_MASK;
5048         if (!((rc6_ctx_base >= ggtt->stolen_reserved_base) &&
5049               (rc6_ctx_base + PAGE_SIZE <= ggtt->stolen_reserved_base +
5050                                         ggtt->stolen_reserved_size))) {
5051                 DRM_DEBUG_DRIVER("RC6 Base address not as expected.\n");
5052                 enable_rc6 = false;
5053         }
5054
5055         if (!(((I915_READ(PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1) &&
5056               ((I915_READ(PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1) &&
5057               ((I915_READ(PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1) &&
5058               ((I915_READ(PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1))) {
5059                 DRM_DEBUG_DRIVER("Engine Idle wait time not set properly.\n");
5060                 enable_rc6 = false;
5061         }
5062
5063         if (!I915_READ(GEN8_PUSHBUS_CONTROL) ||
5064             !I915_READ(GEN8_PUSHBUS_ENABLE) ||
5065             !I915_READ(GEN8_PUSHBUS_SHIFT)) {
5066                 DRM_DEBUG_DRIVER("Pushbus not setup properly.\n");
5067                 enable_rc6 = false;
5068         }
5069
5070         if (!I915_READ(GEN6_GFXPAUSE)) {
5071                 DRM_DEBUG_DRIVER("GFX pause not setup properly.\n");
5072                 enable_rc6 = false;
5073         }
5074
5075         if (!I915_READ(GEN8_MISC_CTRL0)) {
5076                 DRM_DEBUG_DRIVER("GPM control not setup properly.\n");
5077                 enable_rc6 = false;
5078         }
5079
5080         return enable_rc6;
5081 }
5082
5083 int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6)
5084 {
5085         /* No RC6 before Ironlake and code is gone for ilk. */
5086         if (INTEL_INFO(dev_priv)->gen < 6)
5087                 return 0;
5088
5089         if (!enable_rc6)
5090                 return 0;
5091
5092         if (IS_BROXTON(dev_priv) && !bxt_check_bios_rc6_setup(dev_priv)) {
5093                 DRM_INFO("RC6 disabled by BIOS\n");
5094                 return 0;
5095         }
5096
5097         /* Respect the kernel parameter if it is set */
5098         if (enable_rc6 >= 0) {
5099                 int mask;
5100
5101                 if (HAS_RC6p(dev_priv))
5102                         mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
5103                                INTEL_RC6pp_ENABLE;
5104                 else
5105                         mask = INTEL_RC6_ENABLE;
5106
5107                 if ((enable_rc6 & mask) != enable_rc6)
5108                         DRM_DEBUG_DRIVER("Adjusting RC6 mask to %d "
5109                                          "(requested %d, valid %d)\n",
5110                                          enable_rc6 & mask, enable_rc6, mask);
5111
5112                 return enable_rc6 & mask;
5113         }
5114
5115         if (IS_IVYBRIDGE(dev_priv))
5116                 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
5117
5118         return INTEL_RC6_ENABLE;
5119 }
5120
5121 static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
5122 {
5123         uint32_t rp_state_cap;
5124         u32 ddcc_status = 0;
5125         int ret;
5126
5127         /* All of these values are in units of 50MHz */
5128         dev_priv->rps.cur_freq          = 0;
5129         /* static values from HW: RP0 > RP1 > RPn (min_freq) */
5130         if (IS_BROXTON(dev_priv)) {
5131                 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
5132                 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
5133                 dev_priv->rps.rp1_freq = (rp_state_cap >>  8) & 0xff;
5134                 dev_priv->rps.min_freq = (rp_state_cap >>  0) & 0xff;
5135         } else {
5136                 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
5137                 dev_priv->rps.rp0_freq = (rp_state_cap >>  0) & 0xff;
5138                 dev_priv->rps.rp1_freq = (rp_state_cap >>  8) & 0xff;
5139                 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
5140         }
5141
5142         /* hw_max = RP0 until we check for overclocking */
5143         dev_priv->rps.max_freq          = dev_priv->rps.rp0_freq;
5144
5145         dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
5146         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
5147             IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5148                 ret = sandybridge_pcode_read(dev_priv,
5149                                         HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
5150                                         &ddcc_status);
5151                 if (0 == ret)
5152                         dev_priv->rps.efficient_freq =
5153                                 clamp_t(u8,
5154                                         ((ddcc_status >> 8) & 0xff),
5155                                         dev_priv->rps.min_freq,
5156                                         dev_priv->rps.max_freq);
5157         }
5158
5159         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5160                 /* Store the frequency values in 16.66 MHZ units, which is
5161                    the natural hardware unit for SKL */
5162                 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
5163                 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
5164                 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
5165                 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
5166                 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
5167         }
5168
5169         dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5170
5171         /* Preserve min/max settings in case of re-init */
5172         if (dev_priv->rps.max_freq_softlimit == 0)
5173                 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5174
5175         if (dev_priv->rps.min_freq_softlimit == 0) {
5176                 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5177                         dev_priv->rps.min_freq_softlimit =
5178                                 max_t(int, dev_priv->rps.efficient_freq,
5179                                       intel_freq_opcode(dev_priv, 450));
5180                 else
5181                         dev_priv->rps.min_freq_softlimit =
5182                                 dev_priv->rps.min_freq;
5183         }
5184 }
5185
5186 /* See the Gen9_GT_PM_Programming_Guide doc for the below */
5187 static void gen9_enable_rps(struct drm_i915_private *dev_priv)
5188 {
5189         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5190
5191         gen6_init_rps_frequencies(dev_priv);
5192
5193         /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
5194         if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
5195                 /*
5196                  * BIOS could leave the Hw Turbo enabled, so need to explicitly
5197                  * clear out the Control register just to avoid inconsitency
5198                  * with debugfs interface, which will show  Turbo as enabled
5199                  * only and that is not expected by the User after adding the
5200                  * WaGsvDisableTurbo. Apart from this there is no problem even
5201                  * if the Turbo is left enabled in the Control register, as the
5202                  * Up/Down interrupts would remain masked.
5203                  */
5204                 gen9_disable_rps(dev_priv);
5205                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5206                 return;
5207         }
5208
5209         /* Program defaults and thresholds for RPS*/
5210         I915_WRITE(GEN6_RC_VIDEO_FREQ,
5211                 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
5212
5213         /* 1 second timeout*/
5214         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
5215                 GT_INTERVAL_FROM_US(dev_priv, 1000000));
5216
5217         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
5218
5219         /* Leaning on the below call to gen6_set_rps to program/setup the
5220          * Up/Down EI & threshold registers, as well as the RP_CONTROL,
5221          * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
5222         dev_priv->rps.power = HIGH_POWER; /* force a reset */
5223         gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
5224
5225         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5226 }
5227
5228 static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
5229 {
5230         struct intel_engine_cs *engine;
5231         uint32_t rc6_mask = 0;
5232
5233         /* 1a: Software RC state - RC0 */
5234         I915_WRITE(GEN6_RC_STATE, 0);
5235
5236         /* 1b: Get forcewake during program sequence. Although the driver
5237          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5238         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5239
5240         /* 2a: Disable RC states. */
5241         I915_WRITE(GEN6_RC_CONTROL, 0);
5242
5243         /* 2b: Program RC6 thresholds.*/
5244
5245         /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
5246         if (IS_SKYLAKE(dev_priv))
5247                 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
5248         else
5249                 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
5250         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5251         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5252         for_each_engine(engine, dev_priv)
5253                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5254
5255         if (HAS_GUC(dev_priv))
5256                 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
5257
5258         I915_WRITE(GEN6_RC_SLEEP, 0);
5259
5260         /* 2c: Program Coarse Power Gating Policies. */
5261         I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
5262         I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
5263
5264         /* 3a: Enable RC6 */
5265         if (intel_enable_rc6() & INTEL_RC6_ENABLE)
5266                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
5267         DRM_INFO("RC6 %s\n", onoff(rc6_mask & GEN6_RC_CTL_RC6_ENABLE));
5268         /* WaRsUseTimeoutMode */
5269         if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_D0) ||
5270             IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
5271                 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
5272                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5273                            GEN7_RC_CTL_TO_MODE |
5274                            rc6_mask);
5275         } else {
5276                 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
5277                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5278                            GEN6_RC_CTL_EI_MODE(1) |
5279                            rc6_mask);
5280         }
5281
5282         /*
5283          * 3b: Enable Coarse Power Gating only when RC6 is enabled.
5284          * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
5285          */
5286         if (NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
5287                 I915_WRITE(GEN9_PG_ENABLE, 0);
5288         else
5289                 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
5290                                 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
5291
5292         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5293 }
5294
5295 static void gen8_enable_rps(struct drm_i915_private *dev_priv)
5296 {
5297         struct intel_engine_cs *engine;
5298         uint32_t rc6_mask = 0;
5299
5300         /* 1a: Software RC state - RC0 */
5301         I915_WRITE(GEN6_RC_STATE, 0);
5302
5303         /* 1c & 1d: Get forcewake during program sequence. Although the driver
5304          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5305         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5306
5307         /* 2a: Disable RC states. */
5308         I915_WRITE(GEN6_RC_CONTROL, 0);
5309
5310         /* Initialize rps frequencies */
5311         gen6_init_rps_frequencies(dev_priv);
5312
5313         /* 2b: Program RC6 thresholds.*/
5314         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5315         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5316         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5317         for_each_engine(engine, dev_priv)
5318                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5319         I915_WRITE(GEN6_RC_SLEEP, 0);
5320         if (IS_BROADWELL(dev_priv))
5321                 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
5322         else
5323                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
5324
5325         /* 3: Enable RC6 */
5326         if (intel_enable_rc6() & INTEL_RC6_ENABLE)
5327                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
5328         intel_print_rc6_info(dev_priv, rc6_mask);
5329         if (IS_BROADWELL(dev_priv))
5330                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5331                                 GEN7_RC_CTL_TO_MODE |
5332                                 rc6_mask);
5333         else
5334                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5335                                 GEN6_RC_CTL_EI_MODE(1) |
5336                                 rc6_mask);
5337
5338         /* 4 Program defaults and thresholds for RPS*/
5339         I915_WRITE(GEN6_RPNSWREQ,
5340                    HSW_FREQUENCY(dev_priv->rps.rp1_freq));
5341         I915_WRITE(GEN6_RC_VIDEO_FREQ,
5342                    HSW_FREQUENCY(dev_priv->rps.rp1_freq));
5343         /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
5344         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
5345
5346         /* Docs recommend 900MHz, and 300 MHz respectively */
5347         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
5348                    dev_priv->rps.max_freq_softlimit << 24 |
5349                    dev_priv->rps.min_freq_softlimit << 16);
5350
5351         I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
5352         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
5353         I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
5354         I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
5355
5356         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5357
5358         /* 5: Enable RPS */
5359         I915_WRITE(GEN6_RP_CONTROL,
5360                    GEN6_RP_MEDIA_TURBO |
5361                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
5362                    GEN6_RP_MEDIA_IS_GFX |
5363                    GEN6_RP_ENABLE |
5364                    GEN6_RP_UP_BUSY_AVG |
5365                    GEN6_RP_DOWN_IDLE_AVG);
5366
5367         /* 6: Ring frequency + overclocking (our driver does this later */
5368
5369         dev_priv->rps.power = HIGH_POWER; /* force a reset */
5370         gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
5371
5372         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5373 }
5374
5375 static void gen6_enable_rps(struct drm_i915_private *dev_priv)
5376 {
5377         struct intel_engine_cs *engine;
5378         u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
5379         u32 gtfifodbg;
5380         int rc6_mode;
5381         int ret;
5382
5383         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5384
5385         /* Here begins a magic sequence of register writes to enable
5386          * auto-downclocking.
5387          *
5388          * Perhaps there might be some value in exposing these to
5389          * userspace...
5390          */
5391         I915_WRITE(GEN6_RC_STATE, 0);
5392
5393         /* Clear the DBG now so we don't confuse earlier errors */
5394         gtfifodbg = I915_READ(GTFIFODBG);
5395         if (gtfifodbg) {
5396                 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
5397                 I915_WRITE(GTFIFODBG, gtfifodbg);
5398         }
5399
5400         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5401
5402         /* Initialize rps frequencies */
5403         gen6_init_rps_frequencies(dev_priv);
5404
5405         /* disable the counters and set deterministic thresholds */
5406         I915_WRITE(GEN6_RC_CONTROL, 0);
5407
5408         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
5409         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
5410         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
5411         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5412         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5413
5414         for_each_engine(engine, dev_priv)
5415                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5416
5417         I915_WRITE(GEN6_RC_SLEEP, 0);
5418         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
5419         if (IS_IVYBRIDGE(dev_priv))
5420                 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
5421         else
5422                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
5423         I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
5424         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
5425
5426         /* Check if we are enabling RC6 */
5427         rc6_mode = intel_enable_rc6();
5428         if (rc6_mode & INTEL_RC6_ENABLE)
5429                 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
5430
5431         /* We don't use those on Haswell */
5432         if (!IS_HASWELL(dev_priv)) {
5433                 if (rc6_mode & INTEL_RC6p_ENABLE)
5434                         rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
5435
5436                 if (rc6_mode & INTEL_RC6pp_ENABLE)
5437                         rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
5438         }
5439
5440         intel_print_rc6_info(dev_priv, rc6_mask);
5441
5442         I915_WRITE(GEN6_RC_CONTROL,
5443                    rc6_mask |
5444                    GEN6_RC_CTL_EI_MODE(1) |
5445                    GEN6_RC_CTL_HW_ENABLE);
5446
5447         /* Power down if completely idle for over 50ms */
5448         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
5449         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5450
5451         ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
5452         if (ret)
5453                 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
5454
5455         ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
5456         if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
5457                 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
5458                                  (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
5459                                  (pcu_mbox & 0xff) * 50);
5460                 dev_priv->rps.max_freq = pcu_mbox & 0xff;
5461         }
5462
5463         dev_priv->rps.power = HIGH_POWER; /* force a reset */
5464         gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
5465
5466         rc6vids = 0;
5467         ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
5468         if (IS_GEN6(dev_priv) && ret) {
5469                 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
5470         } else if (IS_GEN6(dev_priv) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
5471                 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
5472                           GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
5473                 rc6vids &= 0xffff00;
5474                 rc6vids |= GEN6_ENCODE_RC6_VID(450);
5475                 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
5476                 if (ret)
5477                         DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
5478         }
5479
5480         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5481 }
5482
5483 static void __gen6_update_ring_freq(struct drm_i915_private *dev_priv)
5484 {
5485         int min_freq = 15;
5486         unsigned int gpu_freq;
5487         unsigned int max_ia_freq, min_ring_freq;
5488         unsigned int max_gpu_freq, min_gpu_freq;
5489         int scaling_factor = 180;
5490         struct cpufreq_policy *policy;
5491
5492         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5493
5494         policy = cpufreq_cpu_get(0);
5495         if (policy) {
5496                 max_ia_freq = policy->cpuinfo.max_freq;
5497                 cpufreq_cpu_put(policy);
5498         } else {
5499                 /*
5500                  * Default to measured freq if none found, PCU will ensure we
5501                  * don't go over
5502                  */
5503                 max_ia_freq = tsc_khz;
5504         }
5505
5506         /* Convert from kHz to MHz */
5507         max_ia_freq /= 1000;
5508
5509         min_ring_freq = I915_READ(DCLK) & 0xf;
5510         /* convert DDR frequency from units of 266.6MHz to bandwidth */
5511         min_ring_freq = mult_frac(min_ring_freq, 8, 3);
5512
5513         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5514                 /* Convert GT frequency to 50 HZ units */
5515                 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
5516                 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
5517         } else {
5518                 min_gpu_freq = dev_priv->rps.min_freq;
5519                 max_gpu_freq = dev_priv->rps.max_freq;
5520         }
5521
5522         /*
5523          * For each potential GPU frequency, load a ring frequency we'd like
5524          * to use for memory access.  We do this by specifying the IA frequency
5525          * the PCU should use as a reference to determine the ring frequency.
5526          */
5527         for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
5528                 int diff = max_gpu_freq - gpu_freq;
5529                 unsigned int ia_freq = 0, ring_freq = 0;
5530
5531                 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5532                         /*
5533                          * ring_freq = 2 * GT. ring_freq is in 100MHz units
5534                          * No floor required for ring frequency on SKL.
5535                          */
5536                         ring_freq = gpu_freq;
5537                 } else if (INTEL_INFO(dev_priv)->gen >= 8) {
5538                         /* max(2 * GT, DDR). NB: GT is 50MHz units */
5539                         ring_freq = max(min_ring_freq, gpu_freq);
5540                 } else if (IS_HASWELL(dev_priv)) {
5541                         ring_freq = mult_frac(gpu_freq, 5, 4);
5542                         ring_freq = max(min_ring_freq, ring_freq);
5543                         /* leave ia_freq as the default, chosen by cpufreq */
5544                 } else {
5545                         /* On older processors, there is no separate ring
5546                          * clock domain, so in order to boost the bandwidth
5547                          * of the ring, we need to upclock the CPU (ia_freq).
5548                          *
5549                          * For GPU frequencies less than 750MHz,
5550                          * just use the lowest ring freq.
5551                          */
5552                         if (gpu_freq < min_freq)
5553                                 ia_freq = 800;
5554                         else
5555                                 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
5556                         ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
5557                 }
5558
5559                 sandybridge_pcode_write(dev_priv,
5560                                         GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
5561                                         ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
5562                                         ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
5563                                         gpu_freq);
5564         }
5565 }
5566
5567 void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
5568 {
5569         if (!HAS_CORE_RING_FREQ(dev_priv))
5570                 return;
5571
5572         mutex_lock(&dev_priv->rps.hw_lock);
5573         __gen6_update_ring_freq(dev_priv);
5574         mutex_unlock(&dev_priv->rps.hw_lock);
5575 }
5576
5577 static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
5578 {
5579         u32 val, rp0;
5580
5581         val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5582
5583         switch (INTEL_INFO(dev_priv)->eu_total) {
5584         case 8:
5585                 /* (2 * 4) config */
5586                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5587                 break;
5588         case 12:
5589                 /* (2 * 6) config */
5590                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5591                 break;
5592         case 16:
5593                 /* (2 * 8) config */
5594         default:
5595                 /* Setting (2 * 8) Min RP0 for any other combination */
5596                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5597                 break;
5598         }
5599
5600         rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5601
5602         return rp0;
5603 }
5604
5605 static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5606 {
5607         u32 val, rpe;
5608
5609         val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5610         rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5611
5612         return rpe;
5613 }
5614
5615 static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5616 {
5617         u32 val, rp1;
5618
5619         val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5620         rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5621
5622         return rp1;
5623 }
5624
5625 static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5626 {
5627         u32 val, rp1;
5628
5629         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5630
5631         rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5632
5633         return rp1;
5634 }
5635
5636 static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
5637 {
5638         u32 val, rp0;
5639
5640         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5641
5642         rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5643         /* Clamp to max */
5644         rp0 = min_t(u32, rp0, 0xea);
5645
5646         return rp0;
5647 }
5648
5649 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5650 {
5651         u32 val, rpe;
5652
5653         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
5654         rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
5655         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
5656         rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5657
5658         return rpe;
5659 }
5660
5661 static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
5662 {
5663         u32 val;
5664
5665         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
5666         /*
5667          * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
5668          * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
5669          * a BYT-M B0 the above register contains 0xbf. Moreover when setting
5670          * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
5671          * to make sure it matches what Punit accepts.
5672          */
5673         return max_t(u32, val, 0xc0);
5674 }
5675
5676 /* Check that the pctx buffer wasn't move under us. */
5677 static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5678 {
5679         unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5680
5681         WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5682                              dev_priv->vlv_pctx->stolen->start);
5683 }
5684
5685
5686 /* Check that the pcbr address is not empty. */
5687 static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5688 {
5689         unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5690
5691         WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5692 }
5693
5694 static void cherryview_setup_pctx(struct drm_i915_private *dev_priv)
5695 {
5696         struct i915_ggtt *ggtt = &dev_priv->ggtt;
5697         unsigned long pctx_paddr, paddr;
5698         u32 pcbr;
5699         int pctx_size = 32*1024;
5700
5701         pcbr = I915_READ(VLV_PCBR);
5702         if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
5703                 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5704                 paddr = (dev_priv->mm.stolen_base +
5705                          (ggtt->stolen_size - pctx_size));
5706
5707                 pctx_paddr = (paddr & (~4095));
5708                 I915_WRITE(VLV_PCBR, pctx_paddr);
5709         }
5710
5711         DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5712 }
5713
5714 static void valleyview_setup_pctx(struct drm_i915_private *dev_priv)
5715 {
5716         struct drm_i915_gem_object *pctx;
5717         unsigned long pctx_paddr;
5718         u32 pcbr;
5719         int pctx_size = 24*1024;
5720
5721         mutex_lock(&dev_priv->drm.struct_mutex);
5722
5723         pcbr = I915_READ(VLV_PCBR);
5724         if (pcbr) {
5725                 /* BIOS set it up already, grab the pre-alloc'd space */
5726                 int pcbr_offset;
5727
5728                 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
5729                 pctx = i915_gem_object_create_stolen_for_preallocated(&dev_priv->drm,
5730                                                                       pcbr_offset,
5731                                                                       I915_GTT_OFFSET_NONE,
5732                                                                       pctx_size);
5733                 goto out;
5734         }
5735
5736         DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5737
5738         /*
5739          * From the Gunit register HAS:
5740          * The Gfx driver is expected to program this register and ensure
5741          * proper allocation within Gfx stolen memory.  For example, this
5742          * register should be programmed such than the PCBR range does not
5743          * overlap with other ranges, such as the frame buffer, protected
5744          * memory, or any other relevant ranges.
5745          */
5746         pctx = i915_gem_object_create_stolen(&dev_priv->drm, pctx_size);
5747         if (!pctx) {
5748                 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
5749                 goto out;
5750         }
5751
5752         pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5753         I915_WRITE(VLV_PCBR, pctx_paddr);
5754
5755 out:
5756         DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5757         dev_priv->vlv_pctx = pctx;
5758         mutex_unlock(&dev_priv->drm.struct_mutex);
5759 }
5760
5761 static void valleyview_cleanup_pctx(struct drm_i915_private *dev_priv)
5762 {
5763         if (WARN_ON(!dev_priv->vlv_pctx))
5764                 return;
5765
5766         drm_gem_object_unreference_unlocked(&dev_priv->vlv_pctx->base);
5767         dev_priv->vlv_pctx = NULL;
5768 }
5769
5770 static void vlv_init_gpll_ref_freq(struct drm_i915_private *dev_priv)
5771 {
5772         dev_priv->rps.gpll_ref_freq =
5773                 vlv_get_cck_clock(dev_priv, "GPLL ref",
5774                                   CCK_GPLL_CLOCK_CONTROL,
5775                                   dev_priv->czclk_freq);
5776
5777         DRM_DEBUG_DRIVER("GPLL reference freq: %d kHz\n",
5778                          dev_priv->rps.gpll_ref_freq);
5779 }
5780
5781 static void valleyview_init_gt_powersave(struct drm_i915_private *dev_priv)
5782 {
5783         u32 val;
5784
5785         valleyview_setup_pctx(dev_priv);
5786
5787         vlv_init_gpll_ref_freq(dev_priv);
5788
5789         mutex_lock(&dev_priv->rps.hw_lock);
5790
5791         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5792         switch ((val >> 6) & 3) {
5793         case 0:
5794         case 1:
5795                 dev_priv->mem_freq = 800;
5796                 break;
5797         case 2:
5798                 dev_priv->mem_freq = 1066;
5799                 break;
5800         case 3:
5801                 dev_priv->mem_freq = 1333;
5802                 break;
5803         }
5804         DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5805
5806         dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5807         dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5808         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5809                          intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5810                          dev_priv->rps.max_freq);
5811
5812         dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5813         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5814                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5815                          dev_priv->rps.efficient_freq);
5816
5817         dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5818         DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
5819                          intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5820                          dev_priv->rps.rp1_freq);
5821
5822         dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5823         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5824                          intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5825                          dev_priv->rps.min_freq);
5826
5827         dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5828
5829         /* Preserve min/max settings in case of re-init */
5830         if (dev_priv->rps.max_freq_softlimit == 0)
5831                 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5832
5833         if (dev_priv->rps.min_freq_softlimit == 0)
5834                 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5835
5836         mutex_unlock(&dev_priv->rps.hw_lock);
5837 }
5838
5839 static void cherryview_init_gt_powersave(struct drm_i915_private *dev_priv)
5840 {
5841         u32 val;
5842
5843         cherryview_setup_pctx(dev_priv);
5844
5845         vlv_init_gpll_ref_freq(dev_priv);
5846
5847         mutex_lock(&dev_priv->rps.hw_lock);
5848
5849         mutex_lock(&dev_priv->sb_lock);
5850         val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
5851         mutex_unlock(&dev_priv->sb_lock);
5852
5853         switch ((val >> 2) & 0x7) {
5854         case 3:
5855                 dev_priv->mem_freq = 2000;
5856                 break;
5857         default:
5858                 dev_priv->mem_freq = 1600;
5859                 break;
5860         }
5861         DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5862
5863         dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5864         dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5865         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5866                          intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5867                          dev_priv->rps.max_freq);
5868
5869         dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5870         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5871                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5872                          dev_priv->rps.efficient_freq);
5873
5874         dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5875         DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
5876                          intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5877                          dev_priv->rps.rp1_freq);
5878
5879         /* PUnit validated range is only [RPe, RP0] */
5880         dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
5881         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5882                          intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5883                          dev_priv->rps.min_freq);
5884
5885         WARN_ONCE((dev_priv->rps.max_freq |
5886                    dev_priv->rps.efficient_freq |
5887                    dev_priv->rps.rp1_freq |
5888                    dev_priv->rps.min_freq) & 1,
5889                   "Odd GPU freq values\n");
5890
5891         dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5892
5893         /* Preserve min/max settings in case of re-init */
5894         if (dev_priv->rps.max_freq_softlimit == 0)
5895                 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5896
5897         if (dev_priv->rps.min_freq_softlimit == 0)
5898                 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5899
5900         mutex_unlock(&dev_priv->rps.hw_lock);
5901 }
5902
5903 static void valleyview_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
5904 {
5905         valleyview_cleanup_pctx(dev_priv);
5906 }
5907
5908 static void cherryview_enable_rps(struct drm_i915_private *dev_priv)
5909 {
5910         struct intel_engine_cs *engine;
5911         u32 gtfifodbg, val, rc6_mode = 0, pcbr;
5912
5913         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5914
5915         gtfifodbg = I915_READ(GTFIFODBG) & ~(GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV |
5916                                              GT_FIFO_FREE_ENTRIES_CHV);
5917         if (gtfifodbg) {
5918                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5919                                  gtfifodbg);
5920                 I915_WRITE(GTFIFODBG, gtfifodbg);
5921         }
5922
5923         cherryview_check_pctx(dev_priv);
5924
5925         /* 1a & 1b: Get forcewake during program sequence. Although the driver
5926          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5927         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5928
5929         /*  Disable RC states. */
5930         I915_WRITE(GEN6_RC_CONTROL, 0);
5931
5932         /* 2a: Program RC6 thresholds.*/
5933         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5934         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5935         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5936
5937         for_each_engine(engine, dev_priv)
5938                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5939         I915_WRITE(GEN6_RC_SLEEP, 0);
5940
5941         /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
5942         I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
5943
5944         /* allows RC6 residency counter to work */
5945         I915_WRITE(VLV_COUNTER_CONTROL,
5946                    _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
5947                                       VLV_MEDIA_RC6_COUNT_EN |
5948                                       VLV_RENDER_RC6_COUNT_EN));
5949
5950         /* For now we assume BIOS is allocating and populating the PCBR  */
5951         pcbr = I915_READ(VLV_PCBR);
5952
5953         /* 3: Enable RC6 */
5954         if ((intel_enable_rc6() & INTEL_RC6_ENABLE) &&
5955             (pcbr >> VLV_PCBR_ADDR_SHIFT))
5956                 rc6_mode = GEN7_RC_CTL_TO_MODE;
5957
5958         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5959
5960         /* 4 Program defaults and thresholds for RPS*/
5961         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
5962         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5963         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5964         I915_WRITE(GEN6_RP_UP_EI, 66000);
5965         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5966
5967         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5968
5969         /* 5: Enable RPS */
5970         I915_WRITE(GEN6_RP_CONTROL,
5971                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
5972                    GEN6_RP_MEDIA_IS_GFX |
5973                    GEN6_RP_ENABLE |
5974                    GEN6_RP_UP_BUSY_AVG |
5975                    GEN6_RP_DOWN_IDLE_AVG);
5976
5977         /* Setting Fixed Bias */
5978         val = VLV_OVERRIDE_EN |
5979                   VLV_SOC_TDP_EN |
5980                   CHV_BIAS_CPU_50_SOC_50;
5981         vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5982
5983         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5984
5985         /* RPS code assumes GPLL is used */
5986         WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5987
5988         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
5989         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5990
5991         dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5992         DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
5993                          intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
5994                          dev_priv->rps.cur_freq);
5995
5996         DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5997                          intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq),
5998                          dev_priv->rps.idle_freq);
5999
6000         valleyview_set_rps(dev_priv, dev_priv->rps.idle_freq);
6001
6002         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6003 }
6004
6005 static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
6006 {
6007         struct intel_engine_cs *engine;
6008         u32 gtfifodbg, val, rc6_mode = 0;
6009
6010         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6011
6012         valleyview_check_pctx(dev_priv);
6013
6014         gtfifodbg = I915_READ(GTFIFODBG);
6015         if (gtfifodbg) {
6016                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
6017                                  gtfifodbg);
6018                 I915_WRITE(GTFIFODBG, gtfifodbg);
6019         }
6020
6021         /* If VLV, Forcewake all wells, else re-direct to regular path */
6022         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6023
6024         /*  Disable RC states. */
6025         I915_WRITE(GEN6_RC_CONTROL, 0);
6026
6027         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
6028         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
6029         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
6030         I915_WRITE(GEN6_RP_UP_EI, 66000);
6031         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
6032
6033         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6034
6035         I915_WRITE(GEN6_RP_CONTROL,
6036                    GEN6_RP_MEDIA_TURBO |
6037                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
6038                    GEN6_RP_MEDIA_IS_GFX |
6039                    GEN6_RP_ENABLE |
6040                    GEN6_RP_UP_BUSY_AVG |
6041                    GEN6_RP_DOWN_IDLE_CONT);
6042
6043         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
6044         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
6045         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
6046
6047         for_each_engine(engine, dev_priv)
6048                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
6049
6050         I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
6051
6052         /* allows RC6 residency counter to work */
6053         I915_WRITE(VLV_COUNTER_CONTROL,
6054                    _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
6055                                       VLV_RENDER_RC0_COUNT_EN |
6056                                       VLV_MEDIA_RC6_COUNT_EN |
6057                                       VLV_RENDER_RC6_COUNT_EN));
6058
6059         if (intel_enable_rc6() & INTEL_RC6_ENABLE)
6060                 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
6061
6062         intel_print_rc6_info(dev_priv, rc6_mode);
6063
6064         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
6065
6066         /* Setting Fixed Bias */
6067         val = VLV_OVERRIDE_EN |
6068                   VLV_SOC_TDP_EN |
6069                   VLV_BIAS_CPU_125_SOC_875;
6070         vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
6071
6072         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
6073
6074         /* RPS code assumes GPLL is used */
6075         WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
6076
6077         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
6078         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
6079
6080         dev_priv->rps.cur_freq = (val >> 8) & 0xff;
6081         DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
6082                          intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
6083                          dev_priv->rps.cur_freq);
6084
6085         DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
6086                          intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq),
6087                          dev_priv->rps.idle_freq);
6088
6089         valleyview_set_rps(dev_priv, dev_priv->rps.idle_freq);
6090
6091         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6092 }
6093
6094 static unsigned long intel_pxfreq(u32 vidfreq)
6095 {
6096         unsigned long freq;
6097         int div = (vidfreq & 0x3f0000) >> 16;
6098         int post = (vidfreq & 0x3000) >> 12;
6099         int pre = (vidfreq & 0x7);
6100
6101         if (!pre)
6102                 return 0;
6103
6104         freq = ((div * 133333) / ((1<<post) * pre));
6105
6106         return freq;
6107 }
6108
6109 static const struct cparams {
6110         u16 i;
6111         u16 t;
6112         u16 m;
6113         u16 c;
6114 } cparams[] = {
6115         { 1, 1333, 301, 28664 },
6116         { 1, 1066, 294, 24460 },
6117         { 1, 800, 294, 25192 },
6118         { 0, 1333, 276, 27605 },
6119         { 0, 1066, 276, 27605 },
6120         { 0, 800, 231, 23784 },
6121 };
6122
6123 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
6124 {
6125         u64 total_count, diff, ret;
6126         u32 count1, count2, count3, m = 0, c = 0;
6127         unsigned long now = jiffies_to_msecs(jiffies), diff1;
6128         int i;
6129
6130         assert_spin_locked(&mchdev_lock);
6131
6132         diff1 = now - dev_priv->ips.last_time1;
6133
6134         /* Prevent division-by-zero if we are asking too fast.
6135          * Also, we don't get interesting results if we are polling
6136          * faster than once in 10ms, so just return the saved value
6137          * in such cases.
6138          */
6139         if (diff1 <= 10)
6140                 return dev_priv->ips.chipset_power;
6141
6142         count1 = I915_READ(DMIEC);
6143         count2 = I915_READ(DDREC);
6144         count3 = I915_READ(CSIEC);
6145
6146         total_count = count1 + count2 + count3;
6147
6148         /* FIXME: handle per-counter overflow */
6149         if (total_count < dev_priv->ips.last_count1) {
6150                 diff = ~0UL - dev_priv->ips.last_count1;
6151                 diff += total_count;
6152         } else {
6153                 diff = total_count - dev_priv->ips.last_count1;
6154         }
6155
6156         for (i = 0; i < ARRAY_SIZE(cparams); i++) {
6157                 if (cparams[i].i == dev_priv->ips.c_m &&
6158                     cparams[i].t == dev_priv->ips.r_t) {
6159                         m = cparams[i].m;
6160                         c = cparams[i].c;
6161                         break;
6162                 }
6163         }
6164
6165         diff = div_u64(diff, diff1);
6166         ret = ((m * diff) + c);
6167         ret = div_u64(ret, 10);
6168
6169         dev_priv->ips.last_count1 = total_count;
6170         dev_priv->ips.last_time1 = now;
6171
6172         dev_priv->ips.chipset_power = ret;
6173
6174         return ret;
6175 }
6176
6177 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
6178 {
6179         unsigned long val;
6180
6181         if (INTEL_INFO(dev_priv)->gen != 5)
6182                 return 0;
6183
6184         spin_lock_irq(&mchdev_lock);
6185
6186         val = __i915_chipset_val(dev_priv);
6187
6188         spin_unlock_irq(&mchdev_lock);
6189
6190         return val;
6191 }
6192
6193 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
6194 {
6195         unsigned long m, x, b;
6196         u32 tsfs;
6197
6198         tsfs = I915_READ(TSFS);
6199
6200         m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
6201         x = I915_READ8(TR1);
6202
6203         b = tsfs & TSFS_INTR_MASK;
6204
6205         return ((m * x) / 127) - b;
6206 }
6207
6208 static int _pxvid_to_vd(u8 pxvid)
6209 {
6210         if (pxvid == 0)
6211                 return 0;
6212
6213         if (pxvid >= 8 && pxvid < 31)
6214                 pxvid = 31;
6215
6216         return (pxvid + 2) * 125;
6217 }
6218
6219 static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
6220 {
6221         const int vd = _pxvid_to_vd(pxvid);
6222         const int vm = vd - 1125;
6223
6224         if (INTEL_INFO(dev_priv)->is_mobile)
6225                 return vm > 0 ? vm : 0;
6226
6227         return vd;
6228 }
6229
6230 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
6231 {
6232         u64 now, diff, diffms;
6233         u32 count;
6234
6235         assert_spin_locked(&mchdev_lock);
6236
6237         now = ktime_get_raw_ns();
6238         diffms = now - dev_priv->ips.last_time2;
6239         do_div(diffms, NSEC_PER_MSEC);
6240
6241         /* Don't divide by 0 */
6242         if (!diffms)
6243                 return;
6244
6245         count = I915_READ(GFXEC);
6246
6247         if (count < dev_priv->ips.last_count2) {
6248                 diff = ~0UL - dev_priv->ips.last_count2;
6249                 diff += count;
6250         } else {
6251                 diff = count - dev_priv->ips.last_count2;
6252         }
6253
6254         dev_priv->ips.last_count2 = count;
6255         dev_priv->ips.last_time2 = now;
6256
6257         /* More magic constants... */
6258         diff = diff * 1181;
6259         diff = div_u64(diff, diffms * 10);
6260         dev_priv->ips.gfx_power = diff;
6261 }
6262
6263 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
6264 {
6265         if (INTEL_INFO(dev_priv)->gen != 5)
6266                 return;
6267
6268         spin_lock_irq(&mchdev_lock);
6269
6270         __i915_update_gfx_val(dev_priv);
6271
6272         spin_unlock_irq(&mchdev_lock);
6273 }
6274
6275 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
6276 {
6277         unsigned long t, corr, state1, corr2, state2;
6278         u32 pxvid, ext_v;
6279
6280         assert_spin_locked(&mchdev_lock);
6281
6282         pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
6283         pxvid = (pxvid >> 24) & 0x7f;
6284         ext_v = pvid_to_extvid(dev_priv, pxvid);
6285
6286         state1 = ext_v;
6287
6288         t = i915_mch_val(dev_priv);
6289
6290         /* Revel in the empirically derived constants */
6291
6292         /* Correction factor in 1/100000 units */
6293         if (t > 80)
6294                 corr = ((t * 2349) + 135940);
6295         else if (t >= 50)
6296                 corr = ((t * 964) + 29317);
6297         else /* < 50 */
6298                 corr = ((t * 301) + 1004);
6299
6300         corr = corr * ((150142 * state1) / 10000 - 78642);
6301         corr /= 100000;
6302         corr2 = (corr * dev_priv->ips.corr);
6303
6304         state2 = (corr2 * state1) / 10000;
6305         state2 /= 100; /* convert to mW */
6306
6307         __i915_update_gfx_val(dev_priv);
6308
6309         return dev_priv->ips.gfx_power + state2;
6310 }
6311
6312 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
6313 {
6314         unsigned long val;
6315
6316         if (INTEL_INFO(dev_priv)->gen != 5)
6317                 return 0;
6318
6319         spin_lock_irq(&mchdev_lock);
6320
6321         val = __i915_gfx_val(dev_priv);
6322
6323         spin_unlock_irq(&mchdev_lock);
6324
6325         return val;
6326 }
6327
6328 /**
6329  * i915_read_mch_val - return value for IPS use
6330  *
6331  * Calculate and return a value for the IPS driver to use when deciding whether
6332  * we have thermal and power headroom to increase CPU or GPU power budget.
6333  */
6334 unsigned long i915_read_mch_val(void)
6335 {
6336         struct drm_i915_private *dev_priv;
6337         unsigned long chipset_val, graphics_val, ret = 0;
6338
6339         spin_lock_irq(&mchdev_lock);
6340         if (!i915_mch_dev)
6341                 goto out_unlock;
6342         dev_priv = i915_mch_dev;
6343
6344         chipset_val = __i915_chipset_val(dev_priv);
6345         graphics_val = __i915_gfx_val(dev_priv);
6346
6347         ret = chipset_val + graphics_val;
6348
6349 out_unlock:
6350         spin_unlock_irq(&mchdev_lock);
6351
6352         return ret;
6353 }
6354 EXPORT_SYMBOL_GPL(i915_read_mch_val);
6355
6356 /**
6357  * i915_gpu_raise - raise GPU frequency limit
6358  *
6359  * Raise the limit; IPS indicates we have thermal headroom.
6360  */
6361 bool i915_gpu_raise(void)
6362 {
6363         struct drm_i915_private *dev_priv;
6364         bool ret = true;
6365
6366         spin_lock_irq(&mchdev_lock);
6367         if (!i915_mch_dev) {
6368                 ret = false;
6369                 goto out_unlock;
6370         }
6371         dev_priv = i915_mch_dev;
6372
6373         if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
6374                 dev_priv->ips.max_delay--;
6375
6376 out_unlock:
6377         spin_unlock_irq(&mchdev_lock);
6378
6379         return ret;
6380 }
6381 EXPORT_SYMBOL_GPL(i915_gpu_raise);
6382
6383 /**
6384  * i915_gpu_lower - lower GPU frequency limit
6385  *
6386  * IPS indicates we're close to a thermal limit, so throttle back the GPU
6387  * frequency maximum.
6388  */
6389 bool i915_gpu_lower(void)
6390 {
6391         struct drm_i915_private *dev_priv;
6392         bool ret = true;
6393
6394         spin_lock_irq(&mchdev_lock);
6395         if (!i915_mch_dev) {
6396                 ret = false;
6397                 goto out_unlock;
6398         }
6399         dev_priv = i915_mch_dev;
6400
6401         if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
6402                 dev_priv->ips.max_delay++;
6403
6404 out_unlock:
6405         spin_unlock_irq(&mchdev_lock);
6406
6407         return ret;
6408 }
6409 EXPORT_SYMBOL_GPL(i915_gpu_lower);
6410
6411 /**
6412  * i915_gpu_busy - indicate GPU business to IPS
6413  *
6414  * Tell the IPS driver whether or not the GPU is busy.
6415  */
6416 bool i915_gpu_busy(void)
6417 {
6418         struct drm_i915_private *dev_priv;
6419         struct intel_engine_cs *engine;
6420         bool ret = false;
6421
6422         spin_lock_irq(&mchdev_lock);
6423         if (!i915_mch_dev)
6424                 goto out_unlock;
6425         dev_priv = i915_mch_dev;
6426
6427         for_each_engine(engine, dev_priv)
6428                 ret |= !list_empty(&engine->request_list);
6429
6430 out_unlock:
6431         spin_unlock_irq(&mchdev_lock);
6432
6433         return ret;
6434 }
6435 EXPORT_SYMBOL_GPL(i915_gpu_busy);
6436
6437 /**
6438  * i915_gpu_turbo_disable - disable graphics turbo
6439  *
6440  * Disable graphics turbo by resetting the max frequency and setting the
6441  * current frequency to the default.
6442  */
6443 bool i915_gpu_turbo_disable(void)
6444 {
6445         struct drm_i915_private *dev_priv;
6446         bool ret = true;
6447
6448         spin_lock_irq(&mchdev_lock);
6449         if (!i915_mch_dev) {
6450                 ret = false;
6451                 goto out_unlock;
6452         }
6453         dev_priv = i915_mch_dev;
6454
6455         dev_priv->ips.max_delay = dev_priv->ips.fstart;
6456
6457         if (!ironlake_set_drps(dev_priv, dev_priv->ips.fstart))
6458                 ret = false;
6459
6460 out_unlock:
6461         spin_unlock_irq(&mchdev_lock);
6462
6463         return ret;
6464 }
6465 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
6466
6467 /**
6468  * Tells the intel_ips driver that the i915 driver is now loaded, if
6469  * IPS got loaded first.
6470  *
6471  * This awkward dance is so that neither module has to depend on the
6472  * other in order for IPS to do the appropriate communication of
6473  * GPU turbo limits to i915.
6474  */
6475 static void
6476 ips_ping_for_i915_load(void)
6477 {
6478         void (*link)(void);
6479
6480         link = symbol_get(ips_link_to_i915_driver);
6481         if (link) {
6482                 link();
6483                 symbol_put(ips_link_to_i915_driver);
6484         }
6485 }
6486
6487 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
6488 {
6489         /* We only register the i915 ips part with intel-ips once everything is
6490          * set up, to avoid intel-ips sneaking in and reading bogus values. */
6491         spin_lock_irq(&mchdev_lock);
6492         i915_mch_dev = dev_priv;
6493         spin_unlock_irq(&mchdev_lock);
6494
6495         ips_ping_for_i915_load();
6496 }
6497
6498 void intel_gpu_ips_teardown(void)
6499 {
6500         spin_lock_irq(&mchdev_lock);
6501         i915_mch_dev = NULL;
6502         spin_unlock_irq(&mchdev_lock);
6503 }
6504
6505 static void intel_init_emon(struct drm_i915_private *dev_priv)
6506 {
6507         u32 lcfuse;
6508         u8 pxw[16];
6509         int i;
6510
6511         /* Disable to program */
6512         I915_WRITE(ECR, 0);
6513         POSTING_READ(ECR);
6514
6515         /* Program energy weights for various events */
6516         I915_WRITE(SDEW, 0x15040d00);
6517         I915_WRITE(CSIEW0, 0x007f0000);
6518         I915_WRITE(CSIEW1, 0x1e220004);
6519         I915_WRITE(CSIEW2, 0x04000004);
6520
6521         for (i = 0; i < 5; i++)
6522                 I915_WRITE(PEW(i), 0);
6523         for (i = 0; i < 3; i++)
6524                 I915_WRITE(DEW(i), 0);
6525
6526         /* Program P-state weights to account for frequency power adjustment */
6527         for (i = 0; i < 16; i++) {
6528                 u32 pxvidfreq = I915_READ(PXVFREQ(i));
6529                 unsigned long freq = intel_pxfreq(pxvidfreq);
6530                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6531                         PXVFREQ_PX_SHIFT;
6532                 unsigned long val;
6533
6534                 val = vid * vid;
6535                 val *= (freq / 1000);
6536                 val *= 255;
6537                 val /= (127*127*900);
6538                 if (val > 0xff)
6539                         DRM_ERROR("bad pxval: %ld\n", val);
6540                 pxw[i] = val;
6541         }
6542         /* Render standby states get 0 weight */
6543         pxw[14] = 0;
6544         pxw[15] = 0;
6545
6546         for (i = 0; i < 4; i++) {
6547                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6548                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
6549                 I915_WRITE(PXW(i), val);
6550         }
6551
6552         /* Adjust magic regs to magic values (more experimental results) */
6553         I915_WRITE(OGW0, 0);
6554         I915_WRITE(OGW1, 0);
6555         I915_WRITE(EG0, 0x00007f00);
6556         I915_WRITE(EG1, 0x0000000e);
6557         I915_WRITE(EG2, 0x000e0000);
6558         I915_WRITE(EG3, 0x68000300);
6559         I915_WRITE(EG4, 0x42000000);
6560         I915_WRITE(EG5, 0x00140031);
6561         I915_WRITE(EG6, 0);
6562         I915_WRITE(EG7, 0);
6563
6564         for (i = 0; i < 8; i++)
6565                 I915_WRITE(PXWL(i), 0);
6566
6567         /* Enable PMON + select events */
6568         I915_WRITE(ECR, 0x80000019);
6569
6570         lcfuse = I915_READ(LCFUSE02);
6571
6572         dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
6573 }
6574
6575 void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
6576 {
6577         /*
6578          * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6579          * requirement.
6580          */
6581         if (!i915.enable_rc6) {
6582                 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6583                 intel_runtime_pm_get(dev_priv);
6584         }
6585
6586         if (IS_CHERRYVIEW(dev_priv))
6587                 cherryview_init_gt_powersave(dev_priv);
6588         else if (IS_VALLEYVIEW(dev_priv))
6589                 valleyview_init_gt_powersave(dev_priv);
6590 }
6591
6592 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
6593 {
6594         if (IS_VALLEYVIEW(dev_priv))
6595                 valleyview_cleanup_gt_powersave(dev_priv);
6596
6597         if (!i915.enable_rc6)
6598                 intel_runtime_pm_put(dev_priv);
6599 }
6600
6601 static void gen6_suspend_rps(struct drm_i915_private *dev_priv)
6602 {
6603         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
6604
6605         gen6_disable_rps_interrupts(dev_priv);
6606 }
6607
6608 /**
6609  * intel_suspend_gt_powersave - suspend PM work and helper threads
6610  * @dev_priv: i915 device
6611  *
6612  * We don't want to disable RC6 or other features here, we just want
6613  * to make sure any work we've queued has finished and won't bother
6614  * us while we're suspended.
6615  */
6616 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv)
6617 {
6618         if (INTEL_GEN(dev_priv) < 6)
6619                 return;
6620
6621         gen6_suspend_rps(dev_priv);
6622
6623         /* Force GPU to min freq during suspend */
6624         gen6_rps_idle(dev_priv);
6625 }
6626
6627 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
6628 {
6629         if (IS_IRONLAKE_M(dev_priv)) {
6630                 ironlake_disable_drps(dev_priv);
6631         } else if (INTEL_INFO(dev_priv)->gen >= 6) {
6632                 intel_suspend_gt_powersave(dev_priv);
6633
6634                 mutex_lock(&dev_priv->rps.hw_lock);
6635                 if (INTEL_INFO(dev_priv)->gen >= 9) {
6636                         gen9_disable_rc6(dev_priv);
6637                         gen9_disable_rps(dev_priv);
6638                 } else if (IS_CHERRYVIEW(dev_priv))
6639                         cherryview_disable_rps(dev_priv);
6640                 else if (IS_VALLEYVIEW(dev_priv))
6641                         valleyview_disable_rps(dev_priv);
6642                 else
6643                         gen6_disable_rps(dev_priv);
6644
6645                 dev_priv->rps.enabled = false;
6646                 mutex_unlock(&dev_priv->rps.hw_lock);
6647         }
6648 }
6649
6650 static void intel_gen6_powersave_work(struct work_struct *work)
6651 {
6652         struct drm_i915_private *dev_priv =
6653                 container_of(work, struct drm_i915_private,
6654                              rps.delayed_resume_work.work);
6655
6656         mutex_lock(&dev_priv->rps.hw_lock);
6657
6658         gen6_reset_rps_interrupts(dev_priv);
6659
6660         if (IS_CHERRYVIEW(dev_priv)) {
6661                 cherryview_enable_rps(dev_priv);
6662         } else if (IS_VALLEYVIEW(dev_priv)) {
6663                 valleyview_enable_rps(dev_priv);
6664         } else if (INTEL_INFO(dev_priv)->gen >= 9) {
6665                 gen9_enable_rc6(dev_priv);
6666                 gen9_enable_rps(dev_priv);
6667                 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
6668                         __gen6_update_ring_freq(dev_priv);
6669         } else if (IS_BROADWELL(dev_priv)) {
6670                 gen8_enable_rps(dev_priv);
6671                 __gen6_update_ring_freq(dev_priv);
6672         } else {
6673                 gen6_enable_rps(dev_priv);
6674                 __gen6_update_ring_freq(dev_priv);
6675         }
6676
6677         WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6678         WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6679
6680         WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6681         WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6682
6683         dev_priv->rps.enabled = true;
6684
6685         gen6_enable_rps_interrupts(dev_priv);
6686
6687         mutex_unlock(&dev_priv->rps.hw_lock);
6688
6689         intel_runtime_pm_put(dev_priv);
6690 }
6691
6692 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
6693 {
6694         /* Powersaving is controlled by the host when inside a VM */
6695         if (intel_vgpu_active(dev_priv))
6696                 return;
6697
6698         if (IS_IRONLAKE_M(dev_priv)) {
6699                 ironlake_enable_drps(dev_priv);
6700                 mutex_lock(&dev_priv->drm.struct_mutex);
6701                 intel_init_emon(dev_priv);
6702                 mutex_unlock(&dev_priv->drm.struct_mutex);
6703         } else if (INTEL_INFO(dev_priv)->gen >= 6) {
6704                 /*
6705                  * PCU communication is slow and this doesn't need to be
6706                  * done at any specific time, so do this out of our fast path
6707                  * to make resume and init faster.
6708                  *
6709                  * We depend on the HW RC6 power context save/restore
6710                  * mechanism when entering D3 through runtime PM suspend. So
6711                  * disable RPM until RPS/RC6 is properly setup. We can only
6712                  * get here via the driver load/system resume/runtime resume
6713                  * paths, so the _noresume version is enough (and in case of
6714                  * runtime resume it's necessary).
6715                  */
6716                 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
6717                                            round_jiffies_up_relative(HZ)))
6718                         intel_runtime_pm_get_noresume(dev_priv);
6719         }
6720 }
6721
6722 void intel_reset_gt_powersave(struct drm_i915_private *dev_priv)
6723 {
6724         if (INTEL_INFO(dev_priv)->gen < 6)
6725                 return;
6726
6727         gen6_suspend_rps(dev_priv);
6728         dev_priv->rps.enabled = false;
6729 }
6730
6731 static void ibx_init_clock_gating(struct drm_device *dev)
6732 {
6733         struct drm_i915_private *dev_priv = to_i915(dev);
6734
6735         /*
6736          * On Ibex Peak and Cougar Point, we need to disable clock
6737          * gating for the panel power sequencer or it will fail to
6738          * start up when no ports are active.
6739          */
6740         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6741 }
6742
6743 static void g4x_disable_trickle_feed(struct drm_device *dev)
6744 {
6745         struct drm_i915_private *dev_priv = to_i915(dev);
6746         enum pipe pipe;
6747
6748         for_each_pipe(dev_priv, pipe) {
6749                 I915_WRITE(DSPCNTR(pipe),
6750                            I915_READ(DSPCNTR(pipe)) |
6751                            DISPPLANE_TRICKLE_FEED_DISABLE);
6752
6753                 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6754                 POSTING_READ(DSPSURF(pipe));
6755         }
6756 }
6757
6758 static void ilk_init_lp_watermarks(struct drm_device *dev)
6759 {
6760         struct drm_i915_private *dev_priv = to_i915(dev);
6761
6762         I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6763         I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6764         I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6765
6766         /*
6767          * Don't touch WM1S_LP_EN here.
6768          * Doing so could cause underruns.
6769          */
6770 }
6771
6772 static void ironlake_init_clock_gating(struct drm_device *dev)
6773 {
6774         struct drm_i915_private *dev_priv = to_i915(dev);
6775         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6776
6777         /*
6778          * Required for FBC
6779          * WaFbcDisableDpfcClockGating:ilk
6780          */
6781         dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6782                    ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6783                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6784
6785         I915_WRITE(PCH_3DCGDIS0,
6786                    MARIUNIT_CLOCK_GATE_DISABLE |
6787                    SVSMUNIT_CLOCK_GATE_DISABLE);
6788         I915_WRITE(PCH_3DCGDIS1,
6789                    VFMUNIT_CLOCK_GATE_DISABLE);
6790
6791         /*
6792          * According to the spec the following bits should be set in
6793          * order to enable memory self-refresh
6794          * The bit 22/21 of 0x42004
6795          * The bit 5 of 0x42020
6796          * The bit 15 of 0x45000
6797          */
6798         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6799                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
6800                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
6801         dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6802         I915_WRITE(DISP_ARB_CTL,
6803                    (I915_READ(DISP_ARB_CTL) |
6804                     DISP_FBC_WM_DIS));
6805
6806         ilk_init_lp_watermarks(dev);
6807
6808         /*
6809          * Based on the document from hardware guys the following bits
6810          * should be set unconditionally in order to enable FBC.
6811          * The bit 22 of 0x42000
6812          * The bit 22 of 0x42004
6813          * The bit 7,8,9 of 0x42020.
6814          */
6815         if (IS_IRONLAKE_M(dev)) {
6816                 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6817                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6818                            I915_READ(ILK_DISPLAY_CHICKEN1) |
6819                            ILK_FBCQ_DIS);
6820                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6821                            I915_READ(ILK_DISPLAY_CHICKEN2) |
6822                            ILK_DPARB_GATE);
6823         }
6824
6825         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6826
6827         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6828                    I915_READ(ILK_DISPLAY_CHICKEN2) |
6829                    ILK_ELPIN_409_SELECT);
6830         I915_WRITE(_3D_CHICKEN2,
6831                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6832                    _3D_CHICKEN2_WM_READ_PIPELINED);
6833
6834         /* WaDisableRenderCachePipelinedFlush:ilk */
6835         I915_WRITE(CACHE_MODE_0,
6836                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
6837
6838         /* WaDisable_RenderCache_OperationalFlush:ilk */
6839         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6840
6841         g4x_disable_trickle_feed(dev);
6842
6843         ibx_init_clock_gating(dev);
6844 }
6845
6846 static void cpt_init_clock_gating(struct drm_device *dev)
6847 {
6848         struct drm_i915_private *dev_priv = to_i915(dev);
6849         int pipe;
6850         uint32_t val;
6851
6852         /*
6853          * On Ibex Peak and Cougar Point, we need to disable clock
6854          * gating for the panel power sequencer or it will fail to
6855          * start up when no ports are active.
6856          */
6857         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6858                    PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6859                    PCH_CPUNIT_CLOCK_GATE_DISABLE);
6860         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6861                    DPLS_EDP_PPS_FIX_DIS);
6862         /* The below fixes the weird display corruption, a few pixels shifted
6863          * downward, on (only) LVDS of some HP laptops with IVY.
6864          */
6865         for_each_pipe(dev_priv, pipe) {
6866                 val = I915_READ(TRANS_CHICKEN2(pipe));
6867                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6868                 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6869                 if (dev_priv->vbt.fdi_rx_polarity_inverted)
6870                         val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6871                 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
6872                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6873                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
6874                 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6875         }
6876         /* WADP0ClockGatingDisable */
6877         for_each_pipe(dev_priv, pipe) {
6878                 I915_WRITE(TRANS_CHICKEN1(pipe),
6879                            TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6880         }
6881 }
6882
6883 static void gen6_check_mch_setup(struct drm_device *dev)
6884 {
6885         struct drm_i915_private *dev_priv = to_i915(dev);
6886         uint32_t tmp;
6887
6888         tmp = I915_READ(MCH_SSKPD);
6889         if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
6890                 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
6891                               tmp);
6892 }
6893
6894 static void gen6_init_clock_gating(struct drm_device *dev)
6895 {
6896         struct drm_i915_private *dev_priv = to_i915(dev);
6897         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6898
6899         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6900
6901         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6902                    I915_READ(ILK_DISPLAY_CHICKEN2) |
6903                    ILK_ELPIN_409_SELECT);
6904
6905         /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
6906         I915_WRITE(_3D_CHICKEN,
6907                    _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
6908
6909         /* WaDisable_RenderCache_OperationalFlush:snb */
6910         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6911
6912         /*
6913          * BSpec recoomends 8x4 when MSAA is used,
6914          * however in practice 16x4 seems fastest.
6915          *
6916          * Note that PS/WM thread counts depend on the WIZ hashing
6917          * disable bit, which we don't touch here, but it's good
6918          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6919          */
6920         I915_WRITE(GEN6_GT_MODE,
6921                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6922
6923         ilk_init_lp_watermarks(dev);
6924
6925         I915_WRITE(CACHE_MODE_0,
6926                    _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6927
6928         I915_WRITE(GEN6_UCGCTL1,
6929                    I915_READ(GEN6_UCGCTL1) |
6930                    GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
6931                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6932
6933         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
6934          * gating disable must be set.  Failure to set it results in
6935          * flickering pixels due to Z write ordering failures after
6936          * some amount of runtime in the Mesa "fire" demo, and Unigine
6937          * Sanctuary and Tropics, and apparently anything else with
6938          * alpha test or pixel discard.
6939          *
6940          * According to the spec, bit 11 (RCCUNIT) must also be set,
6941          * but we didn't debug actual testcases to find it out.
6942          *
6943          * WaDisableRCCUnitClockGating:snb
6944          * WaDisableRCPBUnitClockGating:snb
6945          */
6946         I915_WRITE(GEN6_UCGCTL2,
6947                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
6948                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
6949
6950         /* WaStripsFansDisableFastClipPerformanceFix:snb */
6951         I915_WRITE(_3D_CHICKEN3,
6952                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6953
6954         /*
6955          * Bspec says:
6956          * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
6957          * 3DSTATE_SF number of SF output attributes is more than 16."
6958          */
6959         I915_WRITE(_3D_CHICKEN3,
6960                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
6961
6962         /*
6963          * According to the spec the following bits should be
6964          * set in order to enable memory self-refresh and fbc:
6965          * The bit21 and bit22 of 0x42000
6966          * The bit21 and bit22 of 0x42004
6967          * The bit5 and bit7 of 0x42020
6968          * The bit14 of 0x70180
6969          * The bit14 of 0x71180
6970          *
6971          * WaFbcAsynchFlipDisableFbcQueue:snb
6972          */
6973         I915_WRITE(ILK_DISPLAY_CHICKEN1,
6974                    I915_READ(ILK_DISPLAY_CHICKEN1) |
6975                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
6976         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6977                    I915_READ(ILK_DISPLAY_CHICKEN2) |
6978                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
6979         I915_WRITE(ILK_DSPCLK_GATE_D,
6980                    I915_READ(ILK_DSPCLK_GATE_D) |
6981                    ILK_DPARBUNIT_CLOCK_GATE_ENABLE  |
6982                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6983
6984         g4x_disable_trickle_feed(dev);
6985
6986         cpt_init_clock_gating(dev);
6987
6988         gen6_check_mch_setup(dev);
6989 }
6990
6991 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
6992 {
6993         uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
6994
6995         /*
6996          * WaVSThreadDispatchOverride:ivb,vlv
6997          *
6998          * This actually overrides the dispatch
6999          * mode for all thread types.
7000          */
7001         reg &= ~GEN7_FF_SCHED_MASK;
7002         reg |= GEN7_FF_TS_SCHED_HW;
7003         reg |= GEN7_FF_VS_SCHED_HW;
7004         reg |= GEN7_FF_DS_SCHED_HW;
7005
7006         I915_WRITE(GEN7_FF_THREAD_MODE, reg);
7007 }
7008
7009 static void lpt_init_clock_gating(struct drm_device *dev)
7010 {
7011         struct drm_i915_private *dev_priv = to_i915(dev);
7012
7013         /*
7014          * TODO: this bit should only be enabled when really needed, then
7015          * disabled when not needed anymore in order to save power.
7016          */
7017         if (HAS_PCH_LPT_LP(dev))
7018                 I915_WRITE(SOUTH_DSPCLK_GATE_D,
7019                            I915_READ(SOUTH_DSPCLK_GATE_D) |
7020                            PCH_LP_PARTITION_LEVEL_DISABLE);
7021
7022         /* WADPOClockGatingDisable:hsw */
7023         I915_WRITE(TRANS_CHICKEN1(PIPE_A),
7024                    I915_READ(TRANS_CHICKEN1(PIPE_A)) |
7025                    TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
7026 }
7027
7028 static void lpt_suspend_hw(struct drm_device *dev)
7029 {
7030         struct drm_i915_private *dev_priv = to_i915(dev);
7031
7032         if (HAS_PCH_LPT_LP(dev)) {
7033                 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
7034
7035                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7036                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7037         }
7038 }
7039
7040 static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
7041                                    int general_prio_credits,
7042                                    int high_prio_credits)
7043 {
7044         u32 misccpctl;
7045
7046         /* WaTempDisableDOPClkGating:bdw */
7047         misccpctl = I915_READ(GEN7_MISCCPCTL);
7048         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
7049
7050         I915_WRITE(GEN8_L3SQCREG1,
7051                    L3_GENERAL_PRIO_CREDITS(general_prio_credits) |
7052                    L3_HIGH_PRIO_CREDITS(high_prio_credits));
7053
7054         /*
7055          * Wait at least 100 clocks before re-enabling clock gating.
7056          * See the definition of L3SQCREG1 in BSpec.
7057          */
7058         POSTING_READ(GEN8_L3SQCREG1);
7059         udelay(1);
7060         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
7061 }
7062
7063 static void kabylake_init_clock_gating(struct drm_device *dev)
7064 {
7065         struct drm_i915_private *dev_priv = dev->dev_private;
7066
7067         gen9_init_clock_gating(dev);
7068
7069         /* WaDisableSDEUnitClockGating:kbl */
7070         if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
7071                 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7072                            GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
7073
7074         /* WaDisableGamClockGating:kbl */
7075         if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
7076                 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7077                            GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
7078
7079         /* WaFbcNukeOnHostModify:kbl */
7080         I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
7081                    ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
7082 }
7083
7084 static void skylake_init_clock_gating(struct drm_device *dev)
7085 {
7086         struct drm_i915_private *dev_priv = dev->dev_private;
7087
7088         gen9_init_clock_gating(dev);
7089
7090         /* WAC6entrylatency:skl */
7091         I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) |
7092                    FBC_LLC_FULLY_OPEN);
7093
7094         /* WaFbcNukeOnHostModify:skl */
7095         I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
7096                    ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
7097 }
7098
7099 static void broadwell_init_clock_gating(struct drm_device *dev)
7100 {
7101         struct drm_i915_private *dev_priv = to_i915(dev);
7102         enum pipe pipe;
7103
7104         ilk_init_lp_watermarks(dev);
7105
7106         /* WaSwitchSolVfFArbitrationPriority:bdw */
7107         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
7108
7109         /* WaPsrDPAMaskVBlankInSRD:bdw */
7110         I915_WRITE(CHICKEN_PAR1_1,
7111                    I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
7112
7113         /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
7114         for_each_pipe(dev_priv, pipe) {
7115                 I915_WRITE(CHICKEN_PIPESL_1(pipe),
7116                            I915_READ(CHICKEN_PIPESL_1(pipe)) |
7117                            BDW_DPRS_MASK_VBLANK_SRD);
7118         }
7119
7120         /* WaVSRefCountFullforceMissDisable:bdw */
7121         /* WaDSRefCountFullforceMissDisable:bdw */
7122         I915_WRITE(GEN7_FF_THREAD_MODE,
7123                    I915_READ(GEN7_FF_THREAD_MODE) &
7124                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
7125
7126         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7127                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
7128
7129         /* WaDisableSDEUnitClockGating:bdw */
7130         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7131                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
7132
7133         /* WaProgramL3SqcReg1Default:bdw */
7134         gen8_set_l3sqc_credits(dev_priv, 30, 2);
7135
7136         /*
7137          * WaGttCachingOffByDefault:bdw
7138          * GTT cache may not work with big pages, so if those
7139          * are ever enabled GTT cache may need to be disabled.
7140          */
7141         I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
7142
7143         /* WaKVMNotificationOnConfigChange:bdw */
7144         I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1)
7145                    | KVM_CONFIG_CHANGE_NOTIFICATION_SELECT);
7146
7147         lpt_init_clock_gating(dev);
7148 }
7149
7150 static void haswell_init_clock_gating(struct drm_device *dev)
7151 {
7152         struct drm_i915_private *dev_priv = to_i915(dev);
7153
7154         ilk_init_lp_watermarks(dev);
7155
7156         /* L3 caching of data atomics doesn't work -- disable it. */
7157         I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
7158         I915_WRITE(HSW_ROW_CHICKEN3,
7159                    _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
7160
7161         /* This is required by WaCatErrorRejectionIssue:hsw */
7162         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7163                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7164                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7165
7166         /* WaVSRefCountFullforceMissDisable:hsw */
7167         I915_WRITE(GEN7_FF_THREAD_MODE,
7168                    I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
7169
7170         /* WaDisable_RenderCache_OperationalFlush:hsw */
7171         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7172
7173         /* enable HiZ Raw Stall Optimization */
7174         I915_WRITE(CACHE_MODE_0_GEN7,
7175                    _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7176
7177         /* WaDisable4x2SubspanOptimization:hsw */
7178         I915_WRITE(CACHE_MODE_1,
7179                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7180
7181         /*
7182          * BSpec recommends 8x4 when MSAA is used,
7183          * however in practice 16x4 seems fastest.
7184          *
7185          * Note that PS/WM thread counts depend on the WIZ hashing
7186          * disable bit, which we don't touch here, but it's good
7187          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7188          */
7189         I915_WRITE(GEN7_GT_MODE,
7190                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7191
7192         /* WaSampleCChickenBitEnable:hsw */
7193         I915_WRITE(HALF_SLICE_CHICKEN3,
7194                    _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
7195
7196         /* WaSwitchSolVfFArbitrationPriority:hsw */
7197         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
7198
7199         /* WaRsPkgCStateDisplayPMReq:hsw */
7200         I915_WRITE(CHICKEN_PAR1_1,
7201                    I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
7202
7203         lpt_init_clock_gating(dev);
7204 }
7205
7206 static void ivybridge_init_clock_gating(struct drm_device *dev)
7207 {
7208         struct drm_i915_private *dev_priv = to_i915(dev);
7209         uint32_t snpcr;
7210
7211         ilk_init_lp_watermarks(dev);
7212
7213         I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
7214
7215         /* WaDisableEarlyCull:ivb */
7216         I915_WRITE(_3D_CHICKEN3,
7217                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7218
7219         /* WaDisableBackToBackFlipFix:ivb */
7220         I915_WRITE(IVB_CHICKEN3,
7221                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7222                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
7223
7224         /* WaDisablePSDDualDispatchEnable:ivb */
7225         if (IS_IVB_GT1(dev))
7226                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
7227                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
7228
7229         /* WaDisable_RenderCache_OperationalFlush:ivb */
7230         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7231
7232         /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
7233         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
7234                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
7235
7236         /* WaApplyL3ControlAndL3ChickenMode:ivb */
7237         I915_WRITE(GEN7_L3CNTLREG1,
7238                         GEN7_WA_FOR_GEN7_L3_CONTROL);
7239         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
7240                    GEN7_WA_L3_CHICKEN_MODE);
7241         if (IS_IVB_GT1(dev))
7242                 I915_WRITE(GEN7_ROW_CHICKEN2,
7243                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7244         else {
7245                 /* must write both registers */
7246                 I915_WRITE(GEN7_ROW_CHICKEN2,
7247                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7248                 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
7249                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7250         }
7251
7252         /* WaForceL3Serialization:ivb */
7253         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7254                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7255
7256         /*
7257          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
7258          * This implements the WaDisableRCZUnitClockGating:ivb workaround.
7259          */
7260         I915_WRITE(GEN6_UCGCTL2,
7261                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
7262
7263         /* This is required by WaCatErrorRejectionIssue:ivb */
7264         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7265                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7266                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7267
7268         g4x_disable_trickle_feed(dev);
7269
7270         gen7_setup_fixed_func_scheduler(dev_priv);
7271
7272         if (0) { /* causes HiZ corruption on ivb:gt1 */
7273                 /* enable HiZ Raw Stall Optimization */
7274                 I915_WRITE(CACHE_MODE_0_GEN7,
7275                            _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7276         }
7277
7278         /* WaDisable4x2SubspanOptimization:ivb */
7279         I915_WRITE(CACHE_MODE_1,
7280                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7281
7282         /*
7283          * BSpec recommends 8x4 when MSAA is used,
7284          * however in practice 16x4 seems fastest.
7285          *
7286          * Note that PS/WM thread counts depend on the WIZ hashing
7287          * disable bit, which we don't touch here, but it's good
7288          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7289          */
7290         I915_WRITE(GEN7_GT_MODE,
7291                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7292
7293         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
7294         snpcr &= ~GEN6_MBC_SNPCR_MASK;
7295         snpcr |= GEN6_MBC_SNPCR_MED;
7296         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
7297
7298         if (!HAS_PCH_NOP(dev))
7299                 cpt_init_clock_gating(dev);
7300
7301         gen6_check_mch_setup(dev);
7302 }
7303
7304 static void valleyview_init_clock_gating(struct drm_device *dev)
7305 {
7306         struct drm_i915_private *dev_priv = to_i915(dev);
7307
7308         /* WaDisableEarlyCull:vlv */
7309         I915_WRITE(_3D_CHICKEN3,
7310                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7311
7312         /* WaDisableBackToBackFlipFix:vlv */
7313         I915_WRITE(IVB_CHICKEN3,
7314                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7315                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
7316
7317         /* WaPsdDispatchEnable:vlv */
7318         /* WaDisablePSDDualDispatchEnable:vlv */
7319         I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
7320                    _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
7321                                       GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
7322
7323         /* WaDisable_RenderCache_OperationalFlush:vlv */
7324         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7325
7326         /* WaForceL3Serialization:vlv */
7327         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7328                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7329
7330         /* WaDisableDopClockGating:vlv */
7331         I915_WRITE(GEN7_ROW_CHICKEN2,
7332                    _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7333
7334         /* This is required by WaCatErrorRejectionIssue:vlv */
7335         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7336                    I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7337                    GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7338
7339         gen7_setup_fixed_func_scheduler(dev_priv);
7340
7341         /*
7342          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
7343          * This implements the WaDisableRCZUnitClockGating:vlv workaround.
7344          */
7345         I915_WRITE(GEN6_UCGCTL2,
7346                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
7347
7348         /* WaDisableL3Bank2xClockGate:vlv
7349          * Disabling L3 clock gating- MMIO 940c[25] = 1
7350          * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
7351         I915_WRITE(GEN7_UCGCTL4,
7352                    I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
7353
7354         /*
7355          * BSpec says this must be set, even though
7356          * WaDisable4x2SubspanOptimization isn't listed for VLV.
7357          */
7358         I915_WRITE(CACHE_MODE_1,
7359                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7360
7361         /*
7362          * BSpec recommends 8x4 when MSAA is used,
7363          * however in practice 16x4 seems fastest.
7364          *
7365          * Note that PS/WM thread counts depend on the WIZ hashing
7366          * disable bit, which we don't touch here, but it's good
7367          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7368          */
7369         I915_WRITE(GEN7_GT_MODE,
7370                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7371
7372         /*
7373          * WaIncreaseL3CreditsForVLVB0:vlv
7374          * This is the hardware default actually.
7375          */
7376         I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
7377
7378         /*
7379          * WaDisableVLVClockGating_VBIIssue:vlv
7380          * Disable clock gating on th GCFG unit to prevent a delay
7381          * in the reporting of vblank events.
7382          */
7383         I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
7384 }
7385
7386 static void cherryview_init_clock_gating(struct drm_device *dev)
7387 {
7388         struct drm_i915_private *dev_priv = to_i915(dev);
7389
7390         /* WaVSRefCountFullforceMissDisable:chv */
7391         /* WaDSRefCountFullforceMissDisable:chv */
7392         I915_WRITE(GEN7_FF_THREAD_MODE,
7393                    I915_READ(GEN7_FF_THREAD_MODE) &
7394                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
7395
7396         /* WaDisableSemaphoreAndSyncFlipWait:chv */
7397         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7398                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
7399
7400         /* WaDisableCSUnitClockGating:chv */
7401         I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7402                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
7403
7404         /* WaDisableSDEUnitClockGating:chv */
7405         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7406                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
7407
7408         /*
7409          * WaProgramL3SqcReg1Default:chv
7410          * See gfxspecs/Related Documents/Performance Guide/
7411          * LSQC Setting Recommendations.
7412          */
7413         gen8_set_l3sqc_credits(dev_priv, 38, 2);
7414
7415         /*
7416          * GTT cache may not work with big pages, so if those
7417          * are ever enabled GTT cache may need to be disabled.
7418          */
7419         I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
7420 }
7421
7422 static void g4x_init_clock_gating(struct drm_device *dev)
7423 {
7424         struct drm_i915_private *dev_priv = to_i915(dev);
7425         uint32_t dspclk_gate;
7426
7427         I915_WRITE(RENCLK_GATE_D1, 0);
7428         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7429                    GS_UNIT_CLOCK_GATE_DISABLE |
7430                    CL_UNIT_CLOCK_GATE_DISABLE);
7431         I915_WRITE(RAMCLK_GATE_D, 0);
7432         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7433                 OVRUNIT_CLOCK_GATE_DISABLE |
7434                 OVCUNIT_CLOCK_GATE_DISABLE;
7435         if (IS_GM45(dev))
7436                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7437         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
7438
7439         /* WaDisableRenderCachePipelinedFlush */
7440         I915_WRITE(CACHE_MODE_0,
7441                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
7442
7443         /* WaDisable_RenderCache_OperationalFlush:g4x */
7444         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7445
7446         g4x_disable_trickle_feed(dev);
7447 }
7448
7449 static void crestline_init_clock_gating(struct drm_device *dev)
7450 {
7451         struct drm_i915_private *dev_priv = to_i915(dev);
7452
7453         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7454         I915_WRITE(RENCLK_GATE_D2, 0);
7455         I915_WRITE(DSPCLK_GATE_D, 0);
7456         I915_WRITE(RAMCLK_GATE_D, 0);
7457         I915_WRITE16(DEUC, 0);
7458         I915_WRITE(MI_ARB_STATE,
7459                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7460
7461         /* WaDisable_RenderCache_OperationalFlush:gen4 */
7462         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7463 }
7464
7465 static void broadwater_init_clock_gating(struct drm_device *dev)
7466 {
7467         struct drm_i915_private *dev_priv = to_i915(dev);
7468
7469         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7470                    I965_RCC_CLOCK_GATE_DISABLE |
7471                    I965_RCPB_CLOCK_GATE_DISABLE |
7472                    I965_ISC_CLOCK_GATE_DISABLE |
7473                    I965_FBC_CLOCK_GATE_DISABLE);
7474         I915_WRITE(RENCLK_GATE_D2, 0);
7475         I915_WRITE(MI_ARB_STATE,
7476                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7477
7478         /* WaDisable_RenderCache_OperationalFlush:gen4 */
7479         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7480 }
7481
7482 static void gen3_init_clock_gating(struct drm_device *dev)
7483 {
7484         struct drm_i915_private *dev_priv = to_i915(dev);
7485         u32 dstate = I915_READ(D_STATE);
7486
7487         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7488                 DSTATE_DOT_CLOCK_GATING;
7489         I915_WRITE(D_STATE, dstate);
7490
7491         if (IS_PINEVIEW(dev))
7492                 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
7493
7494         /* IIR "flip pending" means done if this bit is set */
7495         I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
7496
7497         /* interrupts should cause a wake up from C3 */
7498         I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
7499
7500         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
7501         I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
7502
7503         I915_WRITE(MI_ARB_STATE,
7504                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7505 }
7506
7507 static void i85x_init_clock_gating(struct drm_device *dev)
7508 {
7509         struct drm_i915_private *dev_priv = to_i915(dev);
7510
7511         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
7512
7513         /* interrupts should cause a wake up from C3 */
7514         I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
7515                    _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
7516
7517         I915_WRITE(MEM_MODE,
7518                    _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
7519 }
7520
7521 static void i830_init_clock_gating(struct drm_device *dev)
7522 {
7523         struct drm_i915_private *dev_priv = to_i915(dev);
7524
7525         I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
7526
7527         I915_WRITE(MEM_MODE,
7528                    _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
7529                    _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
7530 }
7531
7532 void intel_init_clock_gating(struct drm_device *dev)
7533 {
7534         struct drm_i915_private *dev_priv = to_i915(dev);
7535
7536         dev_priv->display.init_clock_gating(dev);
7537 }
7538
7539 void intel_suspend_hw(struct drm_device *dev)
7540 {
7541         if (HAS_PCH_LPT(dev))
7542                 lpt_suspend_hw(dev);
7543 }
7544
7545 static void nop_init_clock_gating(struct drm_device *dev)
7546 {
7547         DRM_DEBUG_KMS("No clock gating settings or workarounds applied.\n");
7548 }
7549
7550 /**
7551  * intel_init_clock_gating_hooks - setup the clock gating hooks
7552  * @dev_priv: device private
7553  *
7554  * Setup the hooks that configure which clocks of a given platform can be
7555  * gated and also apply various GT and display specific workarounds for these
7556  * platforms. Note that some GT specific workarounds are applied separately
7557  * when GPU contexts or batchbuffers start their execution.
7558  */
7559 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
7560 {
7561         if (IS_SKYLAKE(dev_priv))
7562                 dev_priv->display.init_clock_gating = skylake_init_clock_gating;
7563         else if (IS_KABYLAKE(dev_priv))
7564                 dev_priv->display.init_clock_gating = kabylake_init_clock_gating;
7565         else if (IS_BROXTON(dev_priv))
7566                 dev_priv->display.init_clock_gating = bxt_init_clock_gating;
7567         else if (IS_BROADWELL(dev_priv))
7568                 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
7569         else if (IS_CHERRYVIEW(dev_priv))
7570                 dev_priv->display.init_clock_gating = cherryview_init_clock_gating;
7571         else if (IS_HASWELL(dev_priv))
7572                 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
7573         else if (IS_IVYBRIDGE(dev_priv))
7574                 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7575         else if (IS_VALLEYVIEW(dev_priv))
7576                 dev_priv->display.init_clock_gating = valleyview_init_clock_gating;
7577         else if (IS_GEN6(dev_priv))
7578                 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7579         else if (IS_GEN5(dev_priv))
7580                 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7581         else if (IS_G4X(dev_priv))
7582                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7583         else if (IS_CRESTLINE(dev_priv))
7584                 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7585         else if (IS_BROADWATER(dev_priv))
7586                 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7587         else if (IS_GEN3(dev_priv))
7588                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7589         else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
7590                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7591         else if (IS_GEN2(dev_priv))
7592                 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7593         else {
7594                 MISSING_CASE(INTEL_DEVID(dev_priv));
7595                 dev_priv->display.init_clock_gating = nop_init_clock_gating;
7596         }
7597 }
7598
7599 /* Set up chip specific power management-related functions */
7600 void intel_init_pm(struct drm_device *dev)
7601 {
7602         struct drm_i915_private *dev_priv = to_i915(dev);
7603
7604         intel_fbc_init(dev_priv);
7605
7606         /* For cxsr */
7607         if (IS_PINEVIEW(dev))
7608                 i915_pineview_get_mem_freq(dev);
7609         else if (IS_GEN5(dev))
7610                 i915_ironlake_get_mem_freq(dev);
7611
7612         /* For FIFO watermark updates */
7613         if (INTEL_INFO(dev)->gen >= 9) {
7614                 skl_setup_wm_latency(dev);
7615                 dev_priv->display.update_wm = skl_update_wm;
7616                 dev_priv->display.compute_global_watermarks = skl_compute_wm;
7617         } else if (HAS_PCH_SPLIT(dev)) {
7618                 ilk_setup_wm_latency(dev);
7619
7620                 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
7621                      dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7622                     (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
7623                      dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
7624                         dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
7625                         dev_priv->display.compute_intermediate_wm =
7626                                 ilk_compute_intermediate_wm;
7627                         dev_priv->display.initial_watermarks =
7628                                 ilk_initial_watermarks;
7629                         dev_priv->display.optimize_watermarks =
7630                                 ilk_optimize_watermarks;
7631                 } else {
7632                         DRM_DEBUG_KMS("Failed to read display plane latency. "
7633                                       "Disable CxSR\n");
7634                 }
7635         } else if (IS_CHERRYVIEW(dev)) {
7636                 vlv_setup_wm_latency(dev);
7637                 dev_priv->display.update_wm = vlv_update_wm;
7638         } else if (IS_VALLEYVIEW(dev)) {
7639                 vlv_setup_wm_latency(dev);
7640                 dev_priv->display.update_wm = vlv_update_wm;
7641         } else if (IS_PINEVIEW(dev)) {
7642                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7643                                             dev_priv->is_ddr3,
7644                                             dev_priv->fsb_freq,
7645                                             dev_priv->mem_freq)) {
7646                         DRM_INFO("failed to find known CxSR latency "
7647                                  "(found ddr%s fsb freq %d, mem freq %d), "
7648                                  "disabling CxSR\n",
7649                                  (dev_priv->is_ddr3 == 1) ? "3" : "2",
7650                                  dev_priv->fsb_freq, dev_priv->mem_freq);
7651                         /* Disable CxSR and never update its watermark again */
7652                         intel_set_memory_cxsr(dev_priv, false);
7653                         dev_priv->display.update_wm = NULL;
7654                 } else
7655                         dev_priv->display.update_wm = pineview_update_wm;
7656         } else if (IS_G4X(dev)) {
7657                 dev_priv->display.update_wm = g4x_update_wm;
7658         } else if (IS_GEN4(dev)) {
7659                 dev_priv->display.update_wm = i965_update_wm;
7660         } else if (IS_GEN3(dev)) {
7661                 dev_priv->display.update_wm = i9xx_update_wm;
7662                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7663         } else if (IS_GEN2(dev)) {
7664                 if (INTEL_INFO(dev)->num_pipes == 1) {
7665                         dev_priv->display.update_wm = i845_update_wm;
7666                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
7667                 } else {
7668                         dev_priv->display.update_wm = i9xx_update_wm;
7669                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
7670                 }
7671         } else {
7672                 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
7673         }
7674 }
7675
7676 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
7677 {
7678         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7679
7680         /* GEN6_PCODE_* are outside of the forcewake domain, we can
7681          * use te fw I915_READ variants to reduce the amount of work
7682          * required when reading/writing.
7683          */
7684
7685         if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7686                 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7687                 return -EAGAIN;
7688         }
7689
7690         I915_WRITE_FW(GEN6_PCODE_DATA, *val);
7691         I915_WRITE_FW(GEN6_PCODE_DATA1, 0);
7692         I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7693
7694         if (intel_wait_for_register_fw(dev_priv,
7695                                        GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
7696                                        500)) {
7697                 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7698                 return -ETIMEDOUT;
7699         }
7700
7701         *val = I915_READ_FW(GEN6_PCODE_DATA);
7702         I915_WRITE_FW(GEN6_PCODE_DATA, 0);
7703
7704         return 0;
7705 }
7706
7707 int sandybridge_pcode_write(struct drm_i915_private *dev_priv,
7708                                u32 mbox, u32 val)
7709 {
7710         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7711
7712         /* GEN6_PCODE_* are outside of the forcewake domain, we can
7713          * use te fw I915_READ variants to reduce the amount of work
7714          * required when reading/writing.
7715          */
7716
7717         if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7718                 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7719                 return -EAGAIN;
7720         }
7721
7722         I915_WRITE_FW(GEN6_PCODE_DATA, val);
7723         I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7724
7725         if (intel_wait_for_register_fw(dev_priv,
7726                                        GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
7727                                        500)) {
7728                 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7729                 return -ETIMEDOUT;
7730         }
7731
7732         I915_WRITE_FW(GEN6_PCODE_DATA, 0);
7733
7734         return 0;
7735 }
7736
7737 static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7738 {
7739         /*
7740          * N = val - 0xb7
7741          * Slow = Fast = GPLL ref * N
7742          */
7743         return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * (val - 0xb7), 1000);
7744 }
7745
7746 static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
7747 {
7748         return DIV_ROUND_CLOSEST(1000 * val, dev_priv->rps.gpll_ref_freq) + 0xb7;
7749 }
7750
7751 static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
7752 {
7753         /*
7754          * N = val / 2
7755          * CU (slow) = CU2x (fast) / 2 = GPLL ref * N / 2
7756          */
7757         return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * val, 2 * 2 * 1000);
7758 }
7759
7760 static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
7761 {
7762         /* CHV needs even values */
7763         return DIV_ROUND_CLOSEST(2 * 1000 * val, dev_priv->rps.gpll_ref_freq) * 2;
7764 }
7765
7766 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
7767 {
7768         if (IS_GEN9(dev_priv))
7769                 return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
7770                                          GEN9_FREQ_SCALER);
7771         else if (IS_CHERRYVIEW(dev_priv))
7772                 return chv_gpu_freq(dev_priv, val);
7773         else if (IS_VALLEYVIEW(dev_priv))
7774                 return byt_gpu_freq(dev_priv, val);
7775         else
7776                 return val * GT_FREQUENCY_MULTIPLIER;
7777 }
7778
7779 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
7780 {
7781         if (IS_GEN9(dev_priv))
7782                 return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
7783                                          GT_FREQUENCY_MULTIPLIER);
7784         else if (IS_CHERRYVIEW(dev_priv))
7785                 return chv_freq_opcode(dev_priv, val);
7786         else if (IS_VALLEYVIEW(dev_priv))
7787                 return byt_freq_opcode(dev_priv, val);
7788         else
7789                 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
7790 }
7791
7792 struct request_boost {
7793         struct work_struct work;
7794         struct drm_i915_gem_request *req;
7795 };
7796
7797 static void __intel_rps_boost_work(struct work_struct *work)
7798 {
7799         struct request_boost *boost = container_of(work, struct request_boost, work);
7800         struct drm_i915_gem_request *req = boost->req;
7801
7802         if (!i915_gem_request_completed(req))
7803                 gen6_rps_boost(req->i915, NULL, req->emitted_jiffies);
7804
7805         i915_gem_request_unreference(req);
7806         kfree(boost);
7807 }
7808
7809 void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req)
7810 {
7811         struct request_boost *boost;
7812
7813         if (req == NULL || INTEL_GEN(req->i915) < 6)
7814                 return;
7815
7816         if (i915_gem_request_completed(req))
7817                 return;
7818
7819         boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
7820         if (boost == NULL)
7821                 return;
7822
7823         i915_gem_request_reference(req);
7824         boost->req = req;
7825
7826         INIT_WORK(&boost->work, __intel_rps_boost_work);
7827         queue_work(req->i915->wq, &boost->work);
7828 }
7829
7830 void intel_pm_setup(struct drm_device *dev)
7831 {
7832         struct drm_i915_private *dev_priv = to_i915(dev);
7833
7834         mutex_init(&dev_priv->rps.hw_lock);
7835         spin_lock_init(&dev_priv->rps.client_lock);
7836
7837         INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
7838                           intel_gen6_powersave_work);
7839         INIT_LIST_HEAD(&dev_priv->rps.clients);
7840         INIT_LIST_HEAD(&dev_priv->rps.semaphores.link);
7841         INIT_LIST_HEAD(&dev_priv->rps.mmioflips.link);
7842
7843         dev_priv->pm.suspended = false;
7844         atomic_set(&dev_priv->pm.wakeref_count, 0);
7845         atomic_set(&dev_priv->pm.atomic_seq, 0);
7846 }