drivers/gpu/drm/i915/intel_pm.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <linux/cpufreq.h>
  29 #include "i915_drv.h"
  30 #include "intel_drv.h"
  31 #include "../../../platform/x86/intel_ips.h"
  32 #include <linux/module.h>
  33
  34 /**
  35  * DOC: RC6
  36  *
  37  * RC6 is a special power stage which allows the GPU to enter an very
  38  * low-voltage mode when idle, using down to 0V while at this stage.  This
  39  * stage is entered automatically when the GPU is idle when RC6 support is
  40  * enabled, and as soon as new workload arises GPU wakes up automatically as well.
  41  *
  42  * There are different RC6 modes available in Intel GPU, which differentiate
  43  * among each other with the latency required to enter and leave RC6 and
  44  * voltage consumed by the GPU in different states.
  45  *
  46  * The combination of the following flags define which states GPU is allowed
  47  * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
  48  * RC6pp is deepest RC6. Their support by hardware varies according to the
  49  * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
  50  * which brings the most power savings; deeper states save more power, but
  51  * require higher latency to switch to and wake up.
  52  */
  53 #define INTEL_RC6_ENABLE                        (1<<0)
  54 #define INTEL_RC6p_ENABLE                       (1<<1)
  55 #define INTEL_RC6pp_ENABLE                      (1<<2)
  56
  57 static void bxt_init_clock_gating(struct drm_device *dev)
  58 {
  59         struct drm_i915_private *dev_priv = dev->dev_private;
  60
  61         /* See Bspec note for PSR2_CTL bit 31, Wa#828:bxt */
  62         I915_WRITE(CHICKEN_PAR1_1,
  63                    I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
  64
  65         /* WaDisableSDEUnitClockGating:bxt */
  66         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
  67                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
  68
  69         /*
  70          * FIXME:
  71          * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
  72          */
  73         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
  74                    GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
  75
  76         /*
  77          * Wa: Backlight PWM may stop in the asserted state, causing backlight
  78          * to stay fully on.
  79          */
  80         if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
  81                 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
  82                            PWM1_GATING_DIS | PWM2_GATING_DIS);
  83 }
  84
  85 static void i915_pineview_get_mem_freq(struct drm_device *dev)
  86 {
  87         struct drm_i915_private *dev_priv = dev->dev_private;
  88         u32 tmp;
  89
  90         tmp = I915_READ(CLKCFG);
  91
  92         switch (tmp & CLKCFG_FSB_MASK) {
  93         case CLKCFG_FSB_533:
  94                 dev_priv->fsb_freq = 533; /* 133*4 */
  95                 break;
  96         case CLKCFG_FSB_800:
  97                 dev_priv->fsb_freq = 800; /* 200*4 */
  98                 break;
  99         case CLKCFG_FSB_667:
 100                 dev_priv->fsb_freq =  667; /* 167*4 */
 101                 break;
 102         case CLKCFG_FSB_400:
 103                 dev_priv->fsb_freq = 400; /* 100*4 */
 104                 break;
 105         }
 106
 107         switch (tmp & CLKCFG_MEM_MASK) {
 108         case CLKCFG_MEM_533:
 109                 dev_priv->mem_freq = 533;
 110                 break;
 111         case CLKCFG_MEM_667:
 112                 dev_priv->mem_freq = 667;
 113                 break;
 114         case CLKCFG_MEM_800:
 115                 dev_priv->mem_freq = 800;
 116                 break;
 117         }
 118
 119         /* detect pineview DDR3 setting */
 120         tmp = I915_READ(CSHRDDR3CTL);
 121         dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
 122 }
 123
 124 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
 125 {
 126         struct drm_i915_private *dev_priv = dev->dev_private;
 127         u16 ddrpll, csipll;
 128
 129         ddrpll = I915_READ16(DDRMPLL1);
 130         csipll = I915_READ16(CSIPLL0);
 131
 132         switch (ddrpll & 0xff) {
 133         case 0xc:
 134                 dev_priv->mem_freq = 800;
 135                 break;
 136         case 0x10:
 137                 dev_priv->mem_freq = 1066;
 138                 break;
 139         case 0x14:
 140                 dev_priv->mem_freq = 1333;
 141                 break;
 142         case 0x18:
 143                 dev_priv->mem_freq = 1600;
 144                 break;
 145         default:
 146                 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
 147                                  ddrpll & 0xff);
 148                 dev_priv->mem_freq = 0;
 149                 break;
 150         }
 151
 152         dev_priv->ips.r_t = dev_priv->mem_freq;
 153
 154         switch (csipll & 0x3ff) {
 155         case 0x00c:
 156                 dev_priv->fsb_freq = 3200;
 157                 break;
 158         case 0x00e:
 159                 dev_priv->fsb_freq = 3733;
 160                 break;
 161         case 0x010:
 162                 dev_priv->fsb_freq = 4266;
 163                 break;
 164         case 0x012:
 165                 dev_priv->fsb_freq = 4800;
 166                 break;
 167         case 0x014:
 168                 dev_priv->fsb_freq = 5333;
 169                 break;
 170         case 0x016:
 171                 dev_priv->fsb_freq = 5866;
 172                 break;
 173         case 0x018:
 174                 dev_priv->fsb_freq = 6400;
 175                 break;
 176         default:
 177                 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
 178                                  csipll & 0x3ff);
 179                 dev_priv->fsb_freq = 0;
 180                 break;
 181         }
 182
 183         if (dev_priv->fsb_freq == 3200) {
 184                 dev_priv->ips.c_m = 0;
 185         } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
 186                 dev_priv->ips.c_m = 1;
 187         } else {
 188                 dev_priv->ips.c_m = 2;
 189         }
 190 }
 191
 192 static const struct cxsr_latency cxsr_latency_table[] = {
 193         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
 194         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
 195         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
 196         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
 197         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
 198
 199         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
 200         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
 201         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
 202         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
 203         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
 204
 205         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
 206         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
 207         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
 208         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
 209         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
 210
 211         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
 212         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
 213         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
 214         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
 215         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
 216
 217         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
 218         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
 219         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
 220         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
 221         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
 222
 223         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
 224         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
 225         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
 226         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
 227         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
 228 };
 229
 230 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
 231                                                          int is_ddr3,
 232                                                          int fsb,
 233                                                          int mem)
 234 {
 235         const struct cxsr_latency *latency;
 236         int i;
 237
 238         if (fsb == 0 || mem == 0)
 239                 return NULL;
 240
 241         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
 242                 latency = &cxsr_latency_table[i];
 243                 if (is_desktop == latency->is_desktop &&
 244                     is_ddr3 == latency->is_ddr3 &&
 245                     fsb == latency->fsb_freq && mem == latency->mem_freq)
 246                         return latency;
 247         }
 248
 249         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 250
 251         return NULL;
 252 }
 253
 254 static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
 255 {
 256         u32 val;
 257
 258         mutex_lock(&dev_priv->rps.hw_lock);
 259
 260         val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
 261         if (enable)
 262                 val &= ~FORCE_DDR_HIGH_FREQ;
 263         else
 264                 val |= FORCE_DDR_HIGH_FREQ;
 265         val &= ~FORCE_DDR_LOW_FREQ;
 266         val |= FORCE_DDR_FREQ_REQ_ACK;
 267         vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
 268
 269         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
 270                       FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
 271                 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
 272
 273         mutex_unlock(&dev_priv->rps.hw_lock);
 274 }
 275
 276 static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
 277 {
 278         u32 val;
 279
 280         mutex_lock(&dev_priv->rps.hw_lock);
 281
 282         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
 283         if (enable)
 284                 val |= DSP_MAXFIFO_PM5_ENABLE;
 285         else
 286                 val &= ~DSP_MAXFIFO_PM5_ENABLE;
 287         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
 288
 289         mutex_unlock(&dev_priv->rps.hw_lock);
 290 }
 291
 292 #define FW_WM(value, plane) \
 293         (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
 294
 295 void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
 296 {
 297         struct drm_device *dev = dev_priv->dev;
 298         u32 val;
 299
 300         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 301                 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
 302                 POSTING_READ(FW_BLC_SELF_VLV);
 303                 dev_priv->wm.vlv.cxsr = enable;
 304         } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
 305                 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
 306                 POSTING_READ(FW_BLC_SELF);
 307         } else if (IS_PINEVIEW(dev)) {
 308                 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
 309                 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
 310                 I915_WRITE(DSPFW3, val);
 311                 POSTING_READ(DSPFW3);
 312         } else if (IS_I945G(dev) || IS_I945GM(dev)) {
 313                 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
 314                                _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
 315                 I915_WRITE(FW_BLC_SELF, val);
 316                 POSTING_READ(FW_BLC_SELF);
 317         } else if (IS_I915GM(dev)) {
 318                 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
 319                                _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
 320                 I915_WRITE(INSTPM, val);
 321                 POSTING_READ(INSTPM);
 322         } else {
 323                 return;
 324         }
 325
 326         DRM_DEBUG_KMS("memory self-refresh is %s\n",
 327                       enable ? "enabled" : "disabled");
 328 }
 329
 330
 331 /*
 332  * Latency for FIFO fetches is dependent on several factors:
 333  *   - memory configuration (speed, channels)
 334  *   - chipset
 335  *   - current MCH state
 336  * It can be fairly high in some situations, so here we assume a fairly
 337  * pessimal value.  It's a tradeoff between extra memory fetches (if we
 338  * set this value too high, the FIFO will fetch frequently to stay full)
 339  * and power consumption (set it too low to save power and we might see
 340  * FIFO underruns and display "flicker").
 341  *
 342  * A value of 5us seems to be a good balance; safe for very low end
 343  * platforms but not overly aggressive on lower latency configs.
 344  */
 345 static const int pessimal_latency_ns = 5000;
 346
 347 #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
 348         ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
 349
 350 static int vlv_get_fifo_size(struct drm_device *dev,
 351                               enum pipe pipe, int plane)
 352 {
 353         struct drm_i915_private *dev_priv = dev->dev_private;
 354         int sprite0_start, sprite1_start, size;
 355
 356         switch (pipe) {
 357                 uint32_t dsparb, dsparb2, dsparb3;
 358         case PIPE_A:
 359                 dsparb = I915_READ(DSPARB);
 360                 dsparb2 = I915_READ(DSPARB2);
 361                 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
 362                 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
 363                 break;
 364         case PIPE_B:
 365                 dsparb = I915_READ(DSPARB);
 366                 dsparb2 = I915_READ(DSPARB2);
 367                 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
 368                 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
 369                 break;
 370         case PIPE_C:
 371                 dsparb2 = I915_READ(DSPARB2);
 372                 dsparb3 = I915_READ(DSPARB3);
 373                 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
 374                 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
 375                 break;
 376         default:
 377                 return 0;
 378         }
 379
 380         switch (plane) {
 381         case 0:
 382                 size = sprite0_start;
 383                 break;
 384         case 1:
 385                 size = sprite1_start - sprite0_start;
 386                 break;
 387         case 2:
 388                 size = 512 - 1 - sprite1_start;
 389                 break;
 390         default:
 391                 return 0;
 392         }
 393
 394         DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
 395                       pipe_name(pipe), plane == 0 ? "primary" : "sprite",
 396                       plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
 397                       size);
 398
 399         return size;
 400 }
 401
 402 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
 403 {
 404         struct drm_i915_private *dev_priv = dev->dev_private;
 405         uint32_t dsparb = I915_READ(DSPARB);
 406         int size;
 407
 408         size = dsparb & 0x7f;
 409         if (plane)
 410                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
 411
 412         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 413                       plane ? "B" : "A", size);
 414
 415         return size;
 416 }
 417
 418 static int i830_get_fifo_size(struct drm_device *dev, int plane)
 419 {
 420         struct drm_i915_private *dev_priv = dev->dev_private;
 421         uint32_t dsparb = I915_READ(DSPARB);
 422         int size;
 423
 424         size = dsparb & 0x1ff;
 425         if (plane)
 426                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
 427         size >>= 1; /* Convert to cachelines */
 428
 429         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 430                       plane ? "B" : "A", size);
 431
 432         return size;
 433 }
 434
 435 static int i845_get_fifo_size(struct drm_device *dev, int plane)
 436 {
 437         struct drm_i915_private *dev_priv = dev->dev_private;
 438         uint32_t dsparb = I915_READ(DSPARB);
 439         int size;
 440
 441         size = dsparb & 0x7f;
 442         size >>= 2; /* Convert to cachelines */
 443
 444         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 445                       plane ? "B" : "A",
 446                       size);
 447
 448         return size;
 449 }
 450
 451 /* Pineview has different values for various configs */
 452 static const struct intel_watermark_params pineview_display_wm = {
 453         .fifo_size = PINEVIEW_DISPLAY_FIFO,
 454         .max_wm = PINEVIEW_MAX_WM,
 455         .default_wm = PINEVIEW_DFT_WM,
 456         .guard_size = PINEVIEW_GUARD_WM,
 457         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 458 };
 459 static const struct intel_watermark_params pineview_display_hplloff_wm = {
 460         .fifo_size = PINEVIEW_DISPLAY_FIFO,
 461         .max_wm = PINEVIEW_MAX_WM,
 462         .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
 463         .guard_size = PINEVIEW_GUARD_WM,
 464         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 465 };
 466 static const struct intel_watermark_params pineview_cursor_wm = {
 467         .fifo_size = PINEVIEW_CURSOR_FIFO,
 468         .max_wm = PINEVIEW_CURSOR_MAX_WM,
 469         .default_wm = PINEVIEW_CURSOR_DFT_WM,
 470         .guard_size = PINEVIEW_CURSOR_GUARD_WM,
 471         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 472 };
 473 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
 474         .fifo_size = PINEVIEW_CURSOR_FIFO,
 475         .max_wm = PINEVIEW_CURSOR_MAX_WM,
 476         .default_wm = PINEVIEW_CURSOR_DFT_WM,
 477         .guard_size = PINEVIEW_CURSOR_GUARD_WM,
 478         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 479 };
 480 static const struct intel_watermark_params g4x_wm_info = {
 481         .fifo_size = G4X_FIFO_SIZE,
 482         .max_wm = G4X_MAX_WM,
 483         .default_wm = G4X_MAX_WM,
 484         .guard_size = 2,
 485         .cacheline_size = G4X_FIFO_LINE_SIZE,
 486 };
 487 static const struct intel_watermark_params g4x_cursor_wm_info = {
 488         .fifo_size = I965_CURSOR_FIFO,
 489         .max_wm = I965_CURSOR_MAX_WM,
 490         .default_wm = I965_CURSOR_DFT_WM,
 491         .guard_size = 2,
 492         .cacheline_size = G4X_FIFO_LINE_SIZE,
 493 };
 494 static const struct intel_watermark_params i965_cursor_wm_info = {
 495         .fifo_size = I965_CURSOR_FIFO,
 496         .max_wm = I965_CURSOR_MAX_WM,
 497         .default_wm = I965_CURSOR_DFT_WM,
 498         .guard_size = 2,
 499         .cacheline_size = I915_FIFO_LINE_SIZE,
 500 };
 501 static const struct intel_watermark_params i945_wm_info = {
 502         .fifo_size = I945_FIFO_SIZE,
 503         .max_wm = I915_MAX_WM,
 504         .default_wm = 1,
 505         .guard_size = 2,
 506         .cacheline_size = I915_FIFO_LINE_SIZE,
 507 };
 508 static const struct intel_watermark_params i915_wm_info = {
 509         .fifo_size = I915_FIFO_SIZE,
 510         .max_wm = I915_MAX_WM,
 511         .default_wm = 1,
 512         .guard_size = 2,
 513         .cacheline_size = I915_FIFO_LINE_SIZE,
 514 };
 515 static const struct intel_watermark_params i830_a_wm_info = {
 516         .fifo_size = I855GM_FIFO_SIZE,
 517         .max_wm = I915_MAX_WM,
 518         .default_wm = 1,
 519         .guard_size = 2,
 520         .cacheline_size = I830_FIFO_LINE_SIZE,
 521 };
 522 static const struct intel_watermark_params i830_bc_wm_info = {
 523         .fifo_size = I855GM_FIFO_SIZE,
 524         .max_wm = I915_MAX_WM/2,
 525         .default_wm = 1,
 526         .guard_size = 2,
 527         .cacheline_size = I830_FIFO_LINE_SIZE,
 528 };
 529 static const struct intel_watermark_params i845_wm_info = {
 530         .fifo_size = I830_FIFO_SIZE,
 531         .max_wm = I915_MAX_WM,
 532         .default_wm = 1,
 533         .guard_size = 2,
 534         .cacheline_size = I830_FIFO_LINE_SIZE,
 535 };
 536
 537 /**
 538  * intel_calculate_wm - calculate watermark level
 539  * @clock_in_khz: pixel clock
 540  * @wm: chip FIFO params
 541  * @cpp: bytes per pixel
 542  * @latency_ns: memory latency for the platform
 543  *
 544  * Calculate the watermark level (the level at which the display plane will
 545  * start fetching from memory again).  Each chip has a different display
 546  * FIFO size and allocation, so the caller needs to figure that out and pass
 547  * in the correct intel_watermark_params structure.
 548  *
 549  * As the pixel clock runs, the FIFO will be drained at a rate that depends
 550  * on the pixel size.  When it reaches the watermark level, it'll start
 551  * fetching FIFO line sized based chunks from memory until the FIFO fills
 552  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
 553  * will occur, and a display engine hang could result.
 554  */
 555 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
 556                                         const struct intel_watermark_params *wm,
 557                                         int fifo_size, int cpp,
 558                                         unsigned long latency_ns)
 559 {
 560         long entries_required, wm_size;
 561
 562         /*
 563          * Note: we need to make sure we don't overflow for various clock &
 564          * latency values.
 565          * clocks go from a few thousand to several hundred thousand.
 566          * latency is usually a few thousand
 567          */
 568         entries_required = ((clock_in_khz / 1000) * cpp * latency_ns) /
 569                 1000;
 570         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
 571
 572         DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
 573
 574         wm_size = fifo_size - (entries_required + wm->guard_size);
 575
 576         DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
 577
 578         /* Don't promote wm_size to unsigned... */
 579         if (wm_size > (long)wm->max_wm)
 580                 wm_size = wm->max_wm;
 581         if (wm_size <= 0)
 582                 wm_size = wm->default_wm;
 583
 584         /*
 585          * Bspec seems to indicate that the value shouldn't be lower than
 586          * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
 587          * Lets go for 8 which is the burst size since certain platforms
 588          * already use a hardcoded 8 (which is what the spec says should be
 589          * done).
 590          */
 591         if (wm_size <= 8)
 592                 wm_size = 8;
 593
 594         return wm_size;
 595 }
 596
 597 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
 598 {
 599         struct drm_crtc *crtc, *enabled = NULL;
 600
 601         for_each_crtc(dev, crtc) {
 602                 if (intel_crtc_active(crtc)) {
 603                         if (enabled)
 604                                 return NULL;
 605                         enabled = crtc;
 606                 }
 607         }
 608
 609         return enabled;
 610 }
 611
 612 static void pineview_update_wm(struct drm_crtc *unused_crtc)
 613 {
 614         struct drm_device *dev = unused_crtc->dev;
 615         struct drm_i915_private *dev_priv = dev->dev_private;
 616         struct drm_crtc *crtc;
 617         const struct cxsr_latency *latency;
 618         u32 reg;
 619         unsigned long wm;
 620
 621         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
 622                                          dev_priv->fsb_freq, dev_priv->mem_freq);
 623         if (!latency) {
 624                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 625                 intel_set_memory_cxsr(dev_priv, false);
 626                 return;
 627         }
 628
 629         crtc = single_enabled_crtc(dev);
 630         if (crtc) {
 631                 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
 632                 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
 633                 int clock = adjusted_mode->crtc_clock;
 634
 635                 /* Display SR */
 636                 wm = intel_calculate_wm(clock, &pineview_display_wm,
 637                                         pineview_display_wm.fifo_size,
 638                                         cpp, latency->display_sr);
 639                 reg = I915_READ(DSPFW1);
 640                 reg &= ~DSPFW_SR_MASK;
 641                 reg |= FW_WM(wm, SR);
 642                 I915_WRITE(DSPFW1, reg);
 643                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
 644
 645                 /* cursor SR */
 646                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
 647                                         pineview_display_wm.fifo_size,
 648                                         cpp, latency->cursor_sr);
 649                 reg = I915_READ(DSPFW3);
 650                 reg &= ~DSPFW_CURSOR_SR_MASK;
 651                 reg |= FW_WM(wm, CURSOR_SR);
 652                 I915_WRITE(DSPFW3, reg);
 653
 654                 /* Display HPLL off SR */
 655                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
 656                                         pineview_display_hplloff_wm.fifo_size,
 657                                         cpp, latency->display_hpll_disable);
 658                 reg = I915_READ(DSPFW3);
 659                 reg &= ~DSPFW_HPLL_SR_MASK;
 660                 reg |= FW_WM(wm, HPLL_SR);
 661                 I915_WRITE(DSPFW3, reg);
 662
 663                 /* cursor HPLL off SR */
 664                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
 665                                         pineview_display_hplloff_wm.fifo_size,
 666                                         cpp, latency->cursor_hpll_disable);
 667                 reg = I915_READ(DSPFW3);
 668                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
 669                 reg |= FW_WM(wm, HPLL_CURSOR);
 670                 I915_WRITE(DSPFW3, reg);
 671                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
 672
 673                 intel_set_memory_cxsr(dev_priv, true);
 674         } else {
 675                 intel_set_memory_cxsr(dev_priv, false);
 676         }
 677 }
 678
 679 static bool g4x_compute_wm0(struct drm_device *dev,
 680                             int plane,
 681                             const struct intel_watermark_params *display,
 682                             int display_latency_ns,
 683                             const struct intel_watermark_params *cursor,
 684                             int cursor_latency_ns,
 685                             int *plane_wm,
 686                             int *cursor_wm)
 687 {
 688         struct drm_crtc *crtc;
 689         const struct drm_display_mode *adjusted_mode;
 690         int htotal, hdisplay, clock, cpp;
 691         int line_time_us, line_count;
 692         int entries, tlb_miss;
 693
 694         crtc = intel_get_crtc_for_plane(dev, plane);
 695         if (!intel_crtc_active(crtc)) {
 696                 *cursor_wm = cursor->guard_size;
 697                 *plane_wm = display->guard_size;
 698                 return false;
 699         }
 700
 701         adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
 702         clock = adjusted_mode->crtc_clock;
 703         htotal = adjusted_mode->crtc_htotal;
 704         hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
 705         cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
 706
 707         /* Use the small buffer method to calculate plane watermark */
 708         entries = ((clock * cpp / 1000) * display_latency_ns) / 1000;
 709         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
 710         if (tlb_miss > 0)
 711                 entries += tlb_miss;
 712         entries = DIV_ROUND_UP(entries, display->cacheline_size);
 713         *plane_wm = entries + display->guard_size;
 714         if (*plane_wm > (int)display->max_wm)
 715                 *plane_wm = display->max_wm;
 716
 717         /* Use the large buffer method to calculate cursor watermark */
 718         line_time_us = max(htotal * 1000 / clock, 1);
 719         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
 720         entries = line_count * crtc->cursor->state->crtc_w * cpp;
 721         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
 722         if (tlb_miss > 0)
 723                 entries += tlb_miss;
 724         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
 725         *cursor_wm = entries + cursor->guard_size;
 726         if (*cursor_wm > (int)cursor->max_wm)
 727                 *cursor_wm = (int)cursor->max_wm;
 728
 729         return true;
 730 }
 731
 732 /*
 733  * Check the wm result.
 734  *
 735  * If any calculated watermark values is larger than the maximum value that
 736  * can be programmed into the associated watermark register, that watermark
 737  * must be disabled.
 738  */
 739 static bool g4x_check_srwm(struct drm_device *dev,
 740                            int display_wm, int cursor_wm,
 741                            const struct intel_watermark_params *display,
 742                            const struct intel_watermark_params *cursor)
 743 {
 744         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
 745                       display_wm, cursor_wm);
 746
 747         if (display_wm > display->max_wm) {
 748                 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
 749                               display_wm, display->max_wm);
 750                 return false;
 751         }
 752
 753         if (cursor_wm > cursor->max_wm) {
 754                 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
 755                               cursor_wm, cursor->max_wm);
 756                 return false;
 757         }
 758
 759         if (!(display_wm || cursor_wm)) {
 760                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
 761                 return false;
 762         }
 763
 764         return true;
 765 }
 766
 767 static bool g4x_compute_srwm(struct drm_device *dev,
 768                              int plane,
 769                              int latency_ns,
 770                              const struct intel_watermark_params *display,
 771                              const struct intel_watermark_params *cursor,
 772                              int *display_wm, int *cursor_wm)
 773 {
 774         struct drm_crtc *crtc;
 775         const struct drm_display_mode *adjusted_mode;
 776         int hdisplay, htotal, cpp, clock;
 777         unsigned long line_time_us;
 778         int line_count, line_size;
 779         int small, large;
 780         int entries;
 781
 782         if (!latency_ns) {
 783                 *display_wm = *cursor_wm = 0;
 784                 return false;
 785         }
 786
 787         crtc = intel_get_crtc_for_plane(dev, plane);
 788         adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
 789         clock = adjusted_mode->crtc_clock;
 790         htotal = adjusted_mode->crtc_htotal;
 791         hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
 792         cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
 793
 794         line_time_us = max(htotal * 1000 / clock, 1);
 795         line_count = (latency_ns / line_time_us + 1000) / 1000;
 796         line_size = hdisplay * cpp;
 797
 798         /* Use the minimum of the small and large buffer method for primary */
 799         small = ((clock * cpp / 1000) * latency_ns) / 1000;
 800         large = line_count * line_size;
 801
 802         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
 803         *display_wm = entries + display->guard_size;
 804
 805         /* calculate the self-refresh watermark for display cursor */
 806         entries = line_count * cpp * crtc->cursor->state->crtc_w;
 807         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
 808         *cursor_wm = entries + cursor->guard_size;
 809
 810         return g4x_check_srwm(dev,
 811                               *display_wm, *cursor_wm,
 812                               display, cursor);
 813 }
 814
 815 #define FW_WM_VLV(value, plane) \
 816         (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
 817
 818 static void vlv_write_wm_values(struct intel_crtc *crtc,
 819                                 const struct vlv_wm_values *wm)
 820 {
 821         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 822         enum pipe pipe = crtc->pipe;
 823
 824         I915_WRITE(VLV_DDL(pipe),
 825                    (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
 826                    (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
 827                    (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
 828                    (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
 829
 830         I915_WRITE(DSPFW1,
 831                    FW_WM(wm->sr.plane, SR) |
 832                    FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
 833                    FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
 834                    FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
 835         I915_WRITE(DSPFW2,
 836                    FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
 837                    FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
 838                    FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
 839         I915_WRITE(DSPFW3,
 840                    FW_WM(wm->sr.cursor, CURSOR_SR));
 841
 842         if (IS_CHERRYVIEW(dev_priv)) {
 843                 I915_WRITE(DSPFW7_CHV,
 844                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
 845                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
 846                 I915_WRITE(DSPFW8_CHV,
 847                            FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
 848                            FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
 849                 I915_WRITE(DSPFW9_CHV,
 850                            FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
 851                            FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
 852                 I915_WRITE(DSPHOWM,
 853                            FW_WM(wm->sr.plane >> 9, SR_HI) |
 854                            FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
 855                            FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
 856                            FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
 857                            FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
 858                            FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
 859                            FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
 860                            FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
 861                            FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
 862                            FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
 863         } else {
 864                 I915_WRITE(DSPFW7,
 865                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
 866                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
 867                 I915_WRITE(DSPHOWM,
 868                            FW_WM(wm->sr.plane >> 9, SR_HI) |
 869                            FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
 870                            FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
 871                            FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
 872                            FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
 873                            FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
 874                            FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
 875         }
 876
 877         /* zero (unused) WM1 watermarks */
 878         I915_WRITE(DSPFW4, 0);
 879         I915_WRITE(DSPFW5, 0);
 880         I915_WRITE(DSPFW6, 0);
 881         I915_WRITE(DSPHOWM1, 0);
 882
 883         POSTING_READ(DSPFW1);
 884 }
 885
 886 #undef FW_WM_VLV
 887
 888 enum vlv_wm_level {
 889         VLV_WM_LEVEL_PM2,
 890         VLV_WM_LEVEL_PM5,
 891         VLV_WM_LEVEL_DDR_DVFS,
 892 };
 893
 894 /* latency must be in 0.1us units. */
 895 static unsigned int vlv_wm_method2(unsigned int pixel_rate,
 896                                    unsigned int pipe_htotal,
 897                                    unsigned int horiz_pixels,
 898                                    unsigned int cpp,
 899                                    unsigned int latency)
 900 {
 901         unsigned int ret;
 902
 903         ret = (latency * pixel_rate) / (pipe_htotal * 10000);
 904         ret = (ret + 1) * horiz_pixels * cpp;
 905         ret = DIV_ROUND_UP(ret, 64);
 906
 907         return ret;
 908 }
 909
 910 static void vlv_setup_wm_latency(struct drm_device *dev)
 911 {
 912         struct drm_i915_private *dev_priv = dev->dev_private;
 913
 914         /* all latencies in usec */
 915         dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
 916
 917         dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
 918
 919         if (IS_CHERRYVIEW(dev_priv)) {
 920                 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
 921                 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
 922
 923                 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
 924         }
 925 }
 926
 927 static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
 928                                      struct intel_crtc *crtc,
 929                                      const struct intel_plane_state *state,
 930                                      int level)
 931 {
 932         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 933         int clock, htotal, cpp, width, wm;
 934
 935         if (dev_priv->wm.pri_latency[level] == 0)
 936                 return USHRT_MAX;
 937
 938         if (!state->visible)
 939                 return 0;
 940
 941         cpp = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
 942         clock = crtc->config->base.adjusted_mode.crtc_clock;
 943         htotal = crtc->config->base.adjusted_mode.crtc_htotal;
 944         width = crtc->config->pipe_src_w;
 945         if (WARN_ON(htotal == 0))
 946                 htotal = 1;
 947
 948         if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
 949                 /*
 950                  * FIXME the formula gives values that are
 951                  * too big for the cursor FIFO, and hence we
 952                  * would never be able to use cursors. For
 953                  * now just hardcode the watermark.
 954                  */
 955                 wm = 63;
 956         } else {
 957                 wm = vlv_wm_method2(clock, htotal, width, cpp,
 958                                     dev_priv->wm.pri_latency[level] * 10);
 959         }
 960
 961         return min_t(int, wm, USHRT_MAX);
 962 }
 963
 964 static void vlv_compute_fifo(struct intel_crtc *crtc)
 965 {
 966         struct drm_device *dev = crtc->base.dev;
 967         struct vlv_wm_state *wm_state = &crtc->wm_state;
 968         struct intel_plane *plane;
 969         unsigned int total_rate = 0;
 970         const int fifo_size = 512 - 1;
 971         int fifo_extra, fifo_left = fifo_size;
 972
 973         for_each_intel_plane_on_crtc(dev, crtc, plane) {
 974                 struct intel_plane_state *state =
 975                         to_intel_plane_state(plane->base.state);
 976
 977                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
 978                         continue;
 979
 980                 if (state->visible) {
 981                         wm_state->num_active_planes++;
 982                         total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0);
 983                 }
 984         }
 985
 986         for_each_intel_plane_on_crtc(dev, crtc, plane) {
 987                 struct intel_plane_state *state =
 988                         to_intel_plane_state(plane->base.state);
 989                 unsigned int rate;
 990
 991                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
 992                         plane->wm.fifo_size = 63;
 993                         continue;
 994                 }
 995
 996                 if (!state->visible) {
 997                         plane->wm.fifo_size = 0;
 998                         continue;
 999                 }
1000
1001                 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1002                 plane->wm.fifo_size = fifo_size * rate / total_rate;
1003                 fifo_left -= plane->wm.fifo_size;
1004         }
1005
1006         fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1007
1008         /* spread the remainder evenly */
1009         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1010                 int plane_extra;
1011
1012                 if (fifo_left == 0)
1013                         break;
1014
1015                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1016                         continue;
1017
1018                 /* give it all to the first plane if none are active */
1019                 if (plane->wm.fifo_size == 0 &&
1020                     wm_state->num_active_planes)
1021                         continue;
1022
1023                 plane_extra = min(fifo_extra, fifo_left);
1024                 plane->wm.fifo_size += plane_extra;
1025                 fifo_left -= plane_extra;
1026         }
1027
1028         WARN_ON(fifo_left != 0);
1029 }
1030
1031 static void vlv_invert_wms(struct intel_crtc *crtc)
1032 {
1033         struct vlv_wm_state *wm_state = &crtc->wm_state;
1034         int level;
1035
1036         for (level = 0; level < wm_state->num_levels; level++) {
1037                 struct drm_device *dev = crtc->base.dev;
1038                 const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1039                 struct intel_plane *plane;
1040
1041                 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
1042                 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor;
1043
1044                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1045                         switch (plane->base.type) {
1046                                 int sprite;
1047                         case DRM_PLANE_TYPE_CURSOR:
1048                                 wm_state->wm[level].cursor = plane->wm.fifo_size -
1049                                         wm_state->wm[level].cursor;
1050                                 break;
1051                         case DRM_PLANE_TYPE_PRIMARY:
1052                                 wm_state->wm[level].primary = plane->wm.fifo_size -
1053                                         wm_state->wm[level].primary;
1054                                 break;
1055                         case DRM_PLANE_TYPE_OVERLAY:
1056                                 sprite = plane->plane;
1057                                 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size -
1058                                         wm_state->wm[level].sprite[sprite];
1059                                 break;
1060                         }
1061                 }
1062         }
1063 }
1064
1065 static void vlv_compute_wm(struct intel_crtc *crtc)
1066 {
1067         struct drm_device *dev = crtc->base.dev;
1068         struct vlv_wm_state *wm_state = &crtc->wm_state;
1069         struct intel_plane *plane;
1070         int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1071         int level;
1072
1073         memset(wm_state, 0, sizeof(*wm_state));
1074
1075         wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
1076         wm_state->num_levels = to_i915(dev)->wm.max_level + 1;
1077
1078         wm_state->num_active_planes = 0;
1079
1080         vlv_compute_fifo(crtc);
1081
1082         if (wm_state->num_active_planes != 1)
1083                 wm_state->cxsr = false;
1084
1085         if (wm_state->cxsr) {
1086                 for (level = 0; level < wm_state->num_levels; level++) {
1087                         wm_state->sr[level].plane = sr_fifo_size;
1088                         wm_state->sr[level].cursor = 63;
1089                 }
1090         }
1091
1092         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1093                 struct intel_plane_state *state =
1094                         to_intel_plane_state(plane->base.state);
1095
1096                 if (!state->visible)
1097                         continue;
1098
1099                 /* normal watermarks */
1100                 for (level = 0; level < wm_state->num_levels; level++) {
1101                         int wm = vlv_compute_wm_level(plane, crtc, state, level);
1102                         int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511;
1103
1104                         /* hack */
1105                         if (WARN_ON(level == 0 && wm > max_wm))
1106                                 wm = max_wm;
1107
1108                         if (wm > plane->wm.fifo_size)
1109                                 break;
1110
1111                         switch (plane->base.type) {
1112                                 int sprite;
1113                         case DRM_PLANE_TYPE_CURSOR:
1114                                 wm_state->wm[level].cursor = wm;
1115                                 break;
1116                         case DRM_PLANE_TYPE_PRIMARY:
1117                                 wm_state->wm[level].primary = wm;
1118                                 break;
1119                         case DRM_PLANE_TYPE_OVERLAY:
1120                                 sprite = plane->plane;
1121                                 wm_state->wm[level].sprite[sprite] = wm;
1122                                 break;
1123                         }
1124                 }
1125
1126                 wm_state->num_levels = level;
1127
1128                 if (!wm_state->cxsr)
1129                         continue;
1130
1131                 /* maxfifo watermarks */
1132                 switch (plane->base.type) {
1133                         int sprite, level;
1134                 case DRM_PLANE_TYPE_CURSOR:
1135                         for (level = 0; level < wm_state->num_levels; level++)
1136                                 wm_state->sr[level].cursor =
1137                                         wm_state->wm[level].cursor;
1138                         break;
1139                 case DRM_PLANE_TYPE_PRIMARY:
1140                         for (level = 0; level < wm_state->num_levels; level++)
1141                                 wm_state->sr[level].plane =
1142                                         min(wm_state->sr[level].plane,
1143                                             wm_state->wm[level].primary);
1144                         break;
1145                 case DRM_PLANE_TYPE_OVERLAY:
1146                         sprite = plane->plane;
1147                         for (level = 0; level < wm_state->num_levels; level++)
1148                                 wm_state->sr[level].plane =
1149                                         min(wm_state->sr[level].plane,
1150                                             wm_state->wm[level].sprite[sprite]);
1151                         break;
1152                 }
1153         }
1154
1155         /* clear any (partially) filled invalid levels */
1156         for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) {
1157                 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1158                 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1159         }
1160
1161         vlv_invert_wms(crtc);
1162 }
1163
1164 #define VLV_FIFO(plane, value) \
1165         (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1166
1167 static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1168 {
1169         struct drm_device *dev = crtc->base.dev;
1170         struct drm_i915_private *dev_priv = to_i915(dev);
1171         struct intel_plane *plane;
1172         int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1173
1174         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1175                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1176                         WARN_ON(plane->wm.fifo_size != 63);
1177                         continue;
1178                 }
1179
1180                 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
1181                         sprite0_start = plane->wm.fifo_size;
1182                 else if (plane->plane == 0)
1183                         sprite1_start = sprite0_start + plane->wm.fifo_size;
1184                 else
1185                         fifo_size = sprite1_start + plane->wm.fifo_size;
1186         }
1187
1188         WARN_ON(fifo_size != 512 - 1);
1189
1190         DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1191                       pipe_name(crtc->pipe), sprite0_start,
1192                       sprite1_start, fifo_size);
1193
1194         switch (crtc->pipe) {
1195                 uint32_t dsparb, dsparb2, dsparb3;
1196         case PIPE_A:
1197                 dsparb = I915_READ(DSPARB);
1198                 dsparb2 = I915_READ(DSPARB2);
1199
1200                 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1201                             VLV_FIFO(SPRITEB, 0xff));
1202                 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1203                            VLV_FIFO(SPRITEB, sprite1_start));
1204
1205                 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1206                              VLV_FIFO(SPRITEB_HI, 0x1));
1207                 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1208                            VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1209
1210                 I915_WRITE(DSPARB, dsparb);
1211                 I915_WRITE(DSPARB2, dsparb2);
1212                 break;
1213         case PIPE_B:
1214                 dsparb = I915_READ(DSPARB);
1215                 dsparb2 = I915_READ(DSPARB2);
1216
1217                 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1218                             VLV_FIFO(SPRITED, 0xff));
1219                 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1220                            VLV_FIFO(SPRITED, sprite1_start));
1221
1222                 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1223                              VLV_FIFO(SPRITED_HI, 0xff));
1224                 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1225                            VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1226
1227                 I915_WRITE(DSPARB, dsparb);
1228                 I915_WRITE(DSPARB2, dsparb2);
1229                 break;
1230         case PIPE_C:
1231                 dsparb3 = I915_READ(DSPARB3);
1232                 dsparb2 = I915_READ(DSPARB2);
1233
1234                 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1235                              VLV_FIFO(SPRITEF, 0xff));
1236                 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1237                             VLV_FIFO(SPRITEF, sprite1_start));
1238
1239                 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1240                              VLV_FIFO(SPRITEF_HI, 0xff));
1241                 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1242                            VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1243
1244                 I915_WRITE(DSPARB3, dsparb3);
1245                 I915_WRITE(DSPARB2, dsparb2);
1246                 break;
1247         default:
1248                 break;
1249         }
1250 }
1251
1252 #undef VLV_FIFO
1253
1254 static void vlv_merge_wm(struct drm_device *dev,
1255                          struct vlv_wm_values *wm)
1256 {
1257         struct intel_crtc *crtc;
1258         int num_active_crtcs = 0;
1259
1260         wm->level = to_i915(dev)->wm.max_level;
1261         wm->cxsr = true;
1262
1263         for_each_intel_crtc(dev, crtc) {
1264                 const struct vlv_wm_state *wm_state = &crtc->wm_state;
1265
1266                 if (!crtc->active)
1267                         continue;
1268
1269                 if (!wm_state->cxsr)
1270                         wm->cxsr = false;
1271
1272                 num_active_crtcs++;
1273                 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1274         }
1275
1276         if (num_active_crtcs != 1)
1277                 wm->cxsr = false;
1278
1279         if (num_active_crtcs > 1)
1280                 wm->level = VLV_WM_LEVEL_PM2;
1281
1282         for_each_intel_crtc(dev, crtc) {
1283                 struct vlv_wm_state *wm_state = &crtc->wm_state;
1284                 enum pipe pipe = crtc->pipe;
1285
1286                 if (!crtc->active)
1287                         continue;
1288
1289                 wm->pipe[pipe] = wm_state->wm[wm->level];
1290                 if (wm->cxsr)
1291                         wm->sr = wm_state->sr[wm->level];
1292
1293                 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2;
1294                 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2;
1295                 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2;
1296                 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2;
1297         }
1298 }
1299
1300 static void vlv_update_wm(struct drm_crtc *crtc)
1301 {
1302         struct drm_device *dev = crtc->dev;
1303         struct drm_i915_private *dev_priv = dev->dev_private;
1304         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1305         enum pipe pipe = intel_crtc->pipe;
1306         struct vlv_wm_values wm = {};
1307
1308         vlv_compute_wm(intel_crtc);
1309         vlv_merge_wm(dev, &wm);
1310
1311         if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
1312                 /* FIXME should be part of crtc atomic commit */
1313                 vlv_pipe_set_fifo_size(intel_crtc);
1314                 return;
1315         }
1316
1317         if (wm.level < VLV_WM_LEVEL_DDR_DVFS &&
1318             dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS)
1319                 chv_set_memory_dvfs(dev_priv, false);
1320
1321         if (wm.level < VLV_WM_LEVEL_PM5 &&
1322             dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5)
1323                 chv_set_memory_pm5(dev_priv, false);
1324
1325         if (!wm.cxsr && dev_priv->wm.vlv.cxsr)
1326                 intel_set_memory_cxsr(dev_priv, false);
1327
1328         /* FIXME should be part of crtc atomic commit */
1329         vlv_pipe_set_fifo_size(intel_crtc);
1330
1331         vlv_write_wm_values(intel_crtc, &wm);
1332
1333         DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1334                       "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1335                       pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1336                       wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1],
1337                       wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr);
1338
1339         if (wm.cxsr && !dev_priv->wm.vlv.cxsr)
1340                 intel_set_memory_cxsr(dev_priv, true);
1341
1342         if (wm.level >= VLV_WM_LEVEL_PM5 &&
1343             dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5)
1344                 chv_set_memory_pm5(dev_priv, true);
1345
1346         if (wm.level >= VLV_WM_LEVEL_DDR_DVFS &&
1347             dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS)
1348                 chv_set_memory_dvfs(dev_priv, true);
1349
1350         dev_priv->wm.vlv = wm;
1351 }
1352
1353 #define single_plane_enabled(mask) is_power_of_2(mask)
1354
1355 static void g4x_update_wm(struct drm_crtc *crtc)
1356 {
1357         struct drm_device *dev = crtc->dev;
1358         static const int sr_latency_ns = 12000;
1359         struct drm_i915_private *dev_priv = dev->dev_private;
1360         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1361         int plane_sr, cursor_sr;
1362         unsigned int enabled = 0;
1363         bool cxsr_enabled;
1364
1365         if (g4x_compute_wm0(dev, PIPE_A,
1366                             &g4x_wm_info, pessimal_latency_ns,
1367                             &g4x_cursor_wm_info, pessimal_latency_ns,
1368                             &planea_wm, &cursora_wm))
1369                 enabled |= 1 << PIPE_A;
1370
1371         if (g4x_compute_wm0(dev, PIPE_B,
1372                             &g4x_wm_info, pessimal_latency_ns,
1373                             &g4x_cursor_wm_info, pessimal_latency_ns,
1374                             &planeb_wm, &cursorb_wm))
1375                 enabled |= 1 << PIPE_B;
1376
1377         if (single_plane_enabled(enabled) &&
1378             g4x_compute_srwm(dev, ffs(enabled) - 1,
1379                              sr_latency_ns,
1380                              &g4x_wm_info,
1381                              &g4x_cursor_wm_info,
1382                              &plane_sr, &cursor_sr)) {
1383                 cxsr_enabled = true;
1384         } else {
1385                 cxsr_enabled = false;
1386                 intel_set_memory_cxsr(dev_priv, false);
1387                 plane_sr = cursor_sr = 0;
1388         }
1389
1390         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1391                       "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1392                       planea_wm, cursora_wm,
1393                       planeb_wm, cursorb_wm,
1394                       plane_sr, cursor_sr);
1395
1396         I915_WRITE(DSPFW1,
1397                    FW_WM(plane_sr, SR) |
1398                    FW_WM(cursorb_wm, CURSORB) |
1399                    FW_WM(planeb_wm, PLANEB) |
1400                    FW_WM(planea_wm, PLANEA));
1401         I915_WRITE(DSPFW2,
1402                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1403                    FW_WM(cursora_wm, CURSORA));
1404         /* HPLL off in SR has some issues on G4x... disable it */
1405         I915_WRITE(DSPFW3,
1406                    (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1407                    FW_WM(cursor_sr, CURSOR_SR));
1408
1409         if (cxsr_enabled)
1410                 intel_set_memory_cxsr(dev_priv, true);
1411 }
1412
1413 static void i965_update_wm(struct drm_crtc *unused_crtc)
1414 {
1415         struct drm_device *dev = unused_crtc->dev;
1416         struct drm_i915_private *dev_priv = dev->dev_private;
1417         struct drm_crtc *crtc;
1418         int srwm = 1;
1419         int cursor_sr = 16;
1420         bool cxsr_enabled;
1421
1422         /* Calc sr entries for one plane configs */
1423         crtc = single_enabled_crtc(dev);
1424         if (crtc) {
1425                 /* self-refresh has much higher latency */
1426                 static const int sr_latency_ns = 12000;
1427                 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1428                 int clock = adjusted_mode->crtc_clock;
1429                 int htotal = adjusted_mode->crtc_htotal;
1430                 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
1431                 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
1432                 unsigned long line_time_us;
1433                 int entries;
1434
1435                 line_time_us = max(htotal * 1000 / clock, 1);
1436
1437                 /* Use ns/us then divide to preserve precision */
1438                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1439                         cpp * hdisplay;
1440                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1441                 srwm = I965_FIFO_SIZE - entries;
1442                 if (srwm < 0)
1443                         srwm = 1;
1444                 srwm &= 0x1ff;
1445                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1446                               entries, srwm);
1447
1448                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1449                         cpp * crtc->cursor->state->crtc_w;
1450                 entries = DIV_ROUND_UP(entries,
1451                                           i965_cursor_wm_info.cacheline_size);
1452                 cursor_sr = i965_cursor_wm_info.fifo_size -
1453                         (entries + i965_cursor_wm_info.guard_size);
1454
1455                 if (cursor_sr > i965_cursor_wm_info.max_wm)
1456                         cursor_sr = i965_cursor_wm_info.max_wm;
1457
1458                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1459                               "cursor %d\n", srwm, cursor_sr);
1460
1461                 cxsr_enabled = true;
1462         } else {
1463                 cxsr_enabled = false;
1464                 /* Turn off self refresh if both pipes are enabled */
1465                 intel_set_memory_cxsr(dev_priv, false);
1466         }
1467
1468         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1469                       srwm);
1470
1471         /* 965 has limitations... */
1472         I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1473                    FW_WM(8, CURSORB) |
1474                    FW_WM(8, PLANEB) |
1475                    FW_WM(8, PLANEA));
1476         I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1477                    FW_WM(8, PLANEC_OLD));
1478         /* update cursor SR watermark */
1479         I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
1480
1481         if (cxsr_enabled)
1482                 intel_set_memory_cxsr(dev_priv, true);
1483 }
1484
1485 #undef FW_WM
1486
1487 static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1488 {
1489         struct drm_device *dev = unused_crtc->dev;
1490         struct drm_i915_private *dev_priv = dev->dev_private;
1491         const struct intel_watermark_params *wm_info;
1492         uint32_t fwater_lo;
1493         uint32_t fwater_hi;
1494         int cwm, srwm = 1;
1495         int fifo_size;
1496         int planea_wm, planeb_wm;
1497         struct drm_crtc *crtc, *enabled = NULL;
1498
1499         if (IS_I945GM(dev))
1500                 wm_info = &i945_wm_info;
1501         else if (!IS_GEN2(dev))
1502                 wm_info = &i915_wm_info;
1503         else
1504                 wm_info = &i830_a_wm_info;
1505
1506         fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1507         crtc = intel_get_crtc_for_plane(dev, 0);
1508         if (intel_crtc_active(crtc)) {
1509                 const struct drm_display_mode *adjusted_mode;
1510                 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
1511                 if (IS_GEN2(dev))
1512                         cpp = 4;
1513
1514                 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1515                 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1516                                                wm_info, fifo_size, cpp,
1517                                                pessimal_latency_ns);
1518                 enabled = crtc;
1519         } else {
1520                 planea_wm = fifo_size - wm_info->guard_size;
1521                 if (planea_wm > (long)wm_info->max_wm)
1522                         planea_wm = wm_info->max_wm;
1523         }
1524
1525         if (IS_GEN2(dev))
1526                 wm_info = &i830_bc_wm_info;
1527
1528         fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1529         crtc = intel_get_crtc_for_plane(dev, 1);
1530         if (intel_crtc_active(crtc)) {
1531                 const struct drm_display_mode *adjusted_mode;
1532                 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
1533                 if (IS_GEN2(dev))
1534                         cpp = 4;
1535
1536                 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1537                 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1538                                                wm_info, fifo_size, cpp,
1539                                                pessimal_latency_ns);
1540                 if (enabled == NULL)
1541                         enabled = crtc;
1542                 else
1543                         enabled = NULL;
1544         } else {
1545                 planeb_wm = fifo_size - wm_info->guard_size;
1546                 if (planeb_wm > (long)wm_info->max_wm)
1547                         planeb_wm = wm_info->max_wm;
1548         }
1549
1550         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1551
1552         if (IS_I915GM(dev) && enabled) {
1553                 struct drm_i915_gem_object *obj;
1554
1555                 obj = intel_fb_obj(enabled->primary->state->fb);
1556
1557                 /* self-refresh seems busted with untiled */
1558                 if (obj->tiling_mode == I915_TILING_NONE)
1559                         enabled = NULL;
1560         }
1561
1562         /*
1563          * Overlay gets an aggressive default since video jitter is bad.
1564          */
1565         cwm = 2;
1566
1567         /* Play safe and disable self-refresh before adjusting watermarks. */
1568         intel_set_memory_cxsr(dev_priv, false);
1569
1570         /* Calc sr entries for one plane configs */
1571         if (HAS_FW_BLC(dev) && enabled) {
1572                 /* self-refresh has much higher latency */
1573                 static const int sr_latency_ns = 6000;
1574                 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(enabled)->config->base.adjusted_mode;
1575                 int clock = adjusted_mode->crtc_clock;
1576                 int htotal = adjusted_mode->crtc_htotal;
1577                 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
1578                 int cpp = drm_format_plane_cpp(enabled->primary->state->fb->pixel_format, 0);
1579                 unsigned long line_time_us;
1580                 int entries;
1581
1582                 line_time_us = max(htotal * 1000 / clock, 1);
1583
1584                 /* Use ns/us then divide to preserve precision */
1585                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1586                         cpp * hdisplay;
1587                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1588                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1589                 srwm = wm_info->fifo_size - entries;
1590                 if (srwm < 0)
1591                         srwm = 1;
1592
1593                 if (IS_I945G(dev) || IS_I945GM(dev))
1594                         I915_WRITE(FW_BLC_SELF,
1595                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1596                 else if (IS_I915GM(dev))
1597                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1598         }
1599
1600         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1601                       planea_wm, planeb_wm, cwm, srwm);
1602
1603         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1604         fwater_hi = (cwm & 0x1f);
1605
1606         /* Set request length to 8 cachelines per fetch */
1607         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1608         fwater_hi = fwater_hi | (1 << 8);
1609
1610         I915_WRITE(FW_BLC, fwater_lo);
1611         I915_WRITE(FW_BLC2, fwater_hi);
1612
1613         if (enabled)
1614                 intel_set_memory_cxsr(dev_priv, true);
1615 }
1616
1617 static void i845_update_wm(struct drm_crtc *unused_crtc)
1618 {
1619         struct drm_device *dev = unused_crtc->dev;
1620         struct drm_i915_private *dev_priv = dev->dev_private;
1621         struct drm_crtc *crtc;
1622         const struct drm_display_mode *adjusted_mode;
1623         uint32_t fwater_lo;
1624         int planea_wm;
1625
1626         crtc = single_enabled_crtc(dev);
1627         if (crtc == NULL)
1628                 return;
1629
1630         adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1631         planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1632                                        &i845_wm_info,
1633                                        dev_priv->display.get_fifo_size(dev, 0),
1634                                        4, pessimal_latency_ns);
1635         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1636         fwater_lo |= (3<<8) | planea_wm;
1637
1638         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1639
1640         I915_WRITE(FW_BLC, fwater_lo);
1641 }
1642
1643 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
1644 {
1645         uint32_t pixel_rate;
1646
1647         pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
1648
1649         /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1650          * adjust the pixel_rate here. */
1651
1652         if (pipe_config->pch_pfit.enabled) {
1653                 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
1654                 uint32_t pfit_size = pipe_config->pch_pfit.size;
1655
1656                 pipe_w = pipe_config->pipe_src_w;
1657                 pipe_h = pipe_config->pipe_src_h;
1658
1659                 pfit_w = (pfit_size >> 16) & 0xFFFF;
1660                 pfit_h = pfit_size & 0xFFFF;
1661                 if (pipe_w < pfit_w)
1662                         pipe_w = pfit_w;
1663                 if (pipe_h < pfit_h)
1664                         pipe_h = pfit_h;
1665
1666                 if (WARN_ON(!pfit_w || !pfit_h))
1667                         return pixel_rate;
1668
1669                 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1670                                      pfit_w * pfit_h);
1671         }
1672
1673         return pixel_rate;
1674 }
1675
1676 /* latency must be in 0.1us units. */
1677 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
1678 {
1679         uint64_t ret;
1680
1681         if (WARN(latency == 0, "Latency value missing\n"))
1682                 return UINT_MAX;
1683
1684         ret = (uint64_t) pixel_rate * cpp * latency;
1685         ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1686
1687         return ret;
1688 }
1689
1690 /* latency must be in 0.1us units. */
1691 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
1692                                uint32_t horiz_pixels, uint8_t cpp,
1693                                uint32_t latency)
1694 {
1695         uint32_t ret;
1696
1697         if (WARN(latency == 0, "Latency value missing\n"))
1698                 return UINT_MAX;
1699         if (WARN_ON(!pipe_htotal))
1700                 return UINT_MAX;
1701
1702         ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1703         ret = (ret + 1) * horiz_pixels * cpp;
1704         ret = DIV_ROUND_UP(ret, 64) + 2;
1705         return ret;
1706 }
1707
1708 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
1709                            uint8_t cpp)
1710 {
1711         /*
1712          * Neither of these should be possible since this function shouldn't be
1713          * called if the CRTC is off or the plane is invisible.  But let's be
1714          * extra paranoid to avoid a potential divide-by-zero if we screw up
1715          * elsewhere in the driver.
1716          */
1717         if (WARN_ON(!cpp))
1718                 return 0;
1719         if (WARN_ON(!horiz_pixels))
1720                 return 0;
1721
1722         return DIV_ROUND_UP(pri_val * 64, horiz_pixels * cpp) + 2;
1723 }
1724
1725 struct ilk_wm_maximums {
1726         uint16_t pri;
1727         uint16_t spr;
1728         uint16_t cur;
1729         uint16_t fbc;
1730 };
1731
1732 /*
1733  * For both WM_PIPE and WM_LP.
1734  * mem_value must be in 0.1us units.
1735  */
1736 static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
1737                                    const struct intel_plane_state *pstate,
1738                                    uint32_t mem_value,
1739                                    bool is_lp)
1740 {
1741         int cpp = pstate->base.fb ?
1742                 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
1743         uint32_t method1, method2;
1744
1745         if (!cstate->base.active || !pstate->visible)
1746                 return 0;
1747
1748         method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
1749
1750         if (!is_lp)
1751                 return method1;
1752
1753         method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1754                                  cstate->base.adjusted_mode.crtc_htotal,
1755                                  drm_rect_width(&pstate->dst),
1756                                  cpp, mem_value);
1757
1758         return min(method1, method2);
1759 }
1760
1761 /*
1762  * For both WM_PIPE and WM_LP.
1763  * mem_value must be in 0.1us units.
1764  */
1765 static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
1766                                    const struct intel_plane_state *pstate,
1767                                    uint32_t mem_value)
1768 {
1769         int cpp = pstate->base.fb ?
1770                 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
1771         uint32_t method1, method2;
1772
1773         if (!cstate->base.active || !pstate->visible)
1774                 return 0;
1775
1776         method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
1777         method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1778                                  cstate->base.adjusted_mode.crtc_htotal,
1779                                  drm_rect_width(&pstate->dst),
1780                                  cpp, mem_value);
1781         return min(method1, method2);
1782 }
1783
1784 /*
1785  * For both WM_PIPE and WM_LP.
1786  * mem_value must be in 0.1us units.
1787  */
1788 static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
1789                                    const struct intel_plane_state *pstate,
1790                                    uint32_t mem_value)
1791 {
1792         /*
1793          * We treat the cursor plane as always-on for the purposes of watermark
1794          * calculation.  Until we have two-stage watermark programming merged,
1795          * this is necessary to avoid flickering.
1796          */
1797         int cpp = 4;
1798         int width = pstate->visible ? pstate->base.crtc_w : 64;
1799
1800         if (!cstate->base.active)
1801                 return 0;
1802
1803         return ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1804                               cstate->base.adjusted_mode.crtc_htotal,
1805                               width, cpp, mem_value);
1806 }
1807
1808 /* Only for WM_LP. */
1809 static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
1810                                    const struct intel_plane_state *pstate,
1811                                    uint32_t pri_val)
1812 {
1813         int cpp = pstate->base.fb ?
1814                 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
1815
1816         if (!cstate->base.active || !pstate->visible)
1817                 return 0;
1818
1819         return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->dst), cpp);
1820 }
1821
1822 static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1823 {
1824         if (INTEL_INFO(dev)->gen >= 8)
1825                 return 3072;
1826         else if (INTEL_INFO(dev)->gen >= 7)
1827                 return 768;
1828         else
1829                 return 512;
1830 }
1831
1832 static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1833                                          int level, bool is_sprite)
1834 {
1835         if (INTEL_INFO(dev)->gen >= 8)
1836                 /* BDW primary/sprite plane watermarks */
1837                 return level == 0 ? 255 : 2047;
1838         else if (INTEL_INFO(dev)->gen >= 7)
1839                 /* IVB/HSW primary/sprite plane watermarks */
1840                 return level == 0 ? 127 : 1023;
1841         else if (!is_sprite)
1842                 /* ILK/SNB primary plane watermarks */
1843                 return level == 0 ? 127 : 511;
1844         else
1845                 /* ILK/SNB sprite plane watermarks */
1846                 return level == 0 ? 63 : 255;
1847 }
1848
1849 static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1850                                           int level)
1851 {
1852         if (INTEL_INFO(dev)->gen >= 7)
1853                 return level == 0 ? 63 : 255;
1854         else
1855                 return level == 0 ? 31 : 63;
1856 }
1857
1858 static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1859 {
1860         if (INTEL_INFO(dev)->gen >= 8)
1861                 return 31;
1862         else
1863                 return 15;
1864 }
1865
1866 /* Calculate the maximum primary/sprite plane watermark */
1867 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1868                                      int level,
1869                                      const struct intel_wm_config *config,
1870                                      enum intel_ddb_partitioning ddb_partitioning,
1871                                      bool is_sprite)
1872 {
1873         unsigned int fifo_size = ilk_display_fifo_size(dev);
1874
1875         /* if sprites aren't enabled, sprites get nothing */
1876         if (is_sprite && !config->sprites_enabled)
1877                 return 0;
1878
1879         /* HSW allows LP1+ watermarks even with multiple pipes */
1880         if (level == 0 || config->num_pipes_active > 1) {
1881                 fifo_size /= INTEL_INFO(dev)->num_pipes;
1882
1883                 /*
1884                  * For some reason the non self refresh
1885                  * FIFO size is only half of the self
1886                  * refresh FIFO size on ILK/SNB.
1887                  */
1888                 if (INTEL_INFO(dev)->gen <= 6)
1889                         fifo_size /= 2;
1890         }
1891
1892         if (config->sprites_enabled) {
1893                 /* level 0 is always calculated with 1:1 split */
1894                 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1895                         if (is_sprite)
1896                                 fifo_size *= 5;
1897                         fifo_size /= 6;
1898                 } else {
1899                         fifo_size /= 2;
1900                 }
1901         }
1902
1903         /* clamp to max that the registers can hold */
1904         return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
1905 }
1906
1907 /* Calculate the maximum cursor plane watermark */
1908 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
1909                                       int level,
1910                                       const struct intel_wm_config *config)
1911 {
1912         /* HSW LP1+ watermarks w/ multiple pipes */
1913         if (level > 0 && config->num_pipes_active > 1)
1914                 return 64;
1915
1916         /* otherwise just report max that registers can hold */
1917         return ilk_cursor_wm_reg_max(dev, level);
1918 }
1919
1920 static void ilk_compute_wm_maximums(const struct drm_device *dev,
1921                                     int level,
1922                                     const struct intel_wm_config *config,
1923                                     enum intel_ddb_partitioning ddb_partitioning,
1924                                     struct ilk_wm_maximums *max)
1925 {
1926         max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1927         max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1928         max->cur = ilk_cursor_wm_max(dev, level, config);
1929         max->fbc = ilk_fbc_wm_reg_max(dev);
1930 }
1931
1932 static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1933                                         int level,
1934                                         struct ilk_wm_maximums *max)
1935 {
1936         max->pri = ilk_plane_wm_reg_max(dev, level, false);
1937         max->spr = ilk_plane_wm_reg_max(dev, level, true);
1938         max->cur = ilk_cursor_wm_reg_max(dev, level);
1939         max->fbc = ilk_fbc_wm_reg_max(dev);
1940 }
1941
1942 static bool ilk_validate_wm_level(int level,
1943                                   const struct ilk_wm_maximums *max,
1944                                   struct intel_wm_level *result)
1945 {
1946         bool ret;
1947
1948         /* already determined to be invalid? */
1949         if (!result->enable)
1950                 return false;
1951
1952         result->enable = result->pri_val <= max->pri &&
1953                          result->spr_val <= max->spr &&
1954                          result->cur_val <= max->cur;
1955
1956         ret = result->enable;
1957
1958         /*
1959          * HACK until we can pre-compute everything,
1960          * and thus fail gracefully if LP0 watermarks
1961          * are exceeded...
1962          */
1963         if (level == 0 && !result->enable) {
1964                 if (result->pri_val > max->pri)
1965                         DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1966                                       level, result->pri_val, max->pri);
1967                 if (result->spr_val > max->spr)
1968                         DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
1969                                       level, result->spr_val, max->spr);
1970                 if (result->cur_val > max->cur)
1971                         DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
1972                                       level, result->cur_val, max->cur);
1973
1974                 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
1975                 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
1976                 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
1977                 result->enable = true;
1978         }
1979
1980         return ret;
1981 }
1982
1983 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
1984                                  const struct intel_crtc *intel_crtc,
1985                                  int level,
1986                                  struct intel_crtc_state *cstate,
1987                                  struct intel_plane_state *pristate,
1988                                  struct intel_plane_state *sprstate,
1989                                  struct intel_plane_state *curstate,
1990                                  struct intel_wm_level *result)
1991 {
1992         uint16_t pri_latency = dev_priv->wm.pri_latency[level];
1993         uint16_t spr_latency = dev_priv->wm.spr_latency[level];
1994         uint16_t cur_latency = dev_priv->wm.cur_latency[level];
1995
1996         /* WM1+ latency values stored in 0.5us units */
1997         if (level > 0) {
1998                 pri_latency *= 5;
1999                 spr_latency *= 5;
2000                 cur_latency *= 5;
2001         }
2002
2003         if (pristate) {
2004                 result->pri_val = ilk_compute_pri_wm(cstate, pristate,
2005                                                      pri_latency, level);
2006                 result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val);
2007         }
2008
2009         if (sprstate)
2010                 result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency);
2011
2012         if (curstate)
2013                 result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency);
2014
2015         result->enable = true;
2016 }
2017
2018 static uint32_t
2019 hsw_compute_linetime_wm(const struct intel_crtc_state *cstate)
2020 {
2021         const struct intel_atomic_state *intel_state =
2022                 to_intel_atomic_state(cstate->base.state);
2023         const struct drm_display_mode *adjusted_mode =
2024                 &cstate->base.adjusted_mode;
2025         u32 linetime, ips_linetime;
2026
2027         if (!cstate->base.active)
2028                 return 0;
2029         if (WARN_ON(adjusted_mode->crtc_clock == 0))
2030                 return 0;
2031         if (WARN_ON(intel_state->cdclk == 0))
2032                 return 0;
2033
2034         /* The WM are computed with base on how long it takes to fill a single
2035          * row at the given clock rate, multiplied by 8.
2036          * */
2037         linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2038                                      adjusted_mode->crtc_clock);
2039         ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2040                                          intel_state->cdclk);
2041
2042         return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2043                PIPE_WM_LINETIME_TIME(linetime);
2044 }
2045
2046 static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
2047 {
2048         struct drm_i915_private *dev_priv = dev->dev_private;
2049
2050         if (IS_GEN9(dev)) {
2051                 uint32_t val;
2052                 int ret, i;
2053                 int level, max_level = ilk_wm_max_level(dev);
2054
2055                 /* read the first set of memory latencies[0:3] */
2056                 val = 0; /* data0 to be programmed to 0 for first set */
2057                 mutex_lock(&dev_priv->rps.hw_lock);
2058                 ret = sandybridge_pcode_read(dev_priv,
2059                                              GEN9_PCODE_READ_MEM_LATENCY,
2060                                              &val);
2061                 mutex_unlock(&dev_priv->rps.hw_lock);
2062
2063                 if (ret) {
2064                         DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2065                         return;
2066                 }
2067
2068                 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2069                 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2070                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2071                 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2072                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2073                 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2074                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2075
2076                 /* read the second set of memory latencies[4:7] */
2077                 val = 1; /* data0 to be programmed to 1 for second set */
2078                 mutex_lock(&dev_priv->rps.hw_lock);
2079                 ret = sandybridge_pcode_read(dev_priv,
2080                                              GEN9_PCODE_READ_MEM_LATENCY,
2081                                              &val);
2082                 mutex_unlock(&dev_priv->rps.hw_lock);
2083                 if (ret) {
2084                         DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2085                         return;
2086                 }
2087
2088                 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2089                 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2090                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2091                 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2092                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2093                 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2094                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2095
2096                 /*
2097                  * WaWmMemoryReadLatency:skl
2098                  *
2099                  * punit doesn't take into account the read latency so we need
2100                  * to add 2us to the various latency levels we retrieve from
2101                  * the punit.
2102                  *   - W0 is a bit special in that it's the only level that
2103                  *   can't be disabled if we want to have display working, so
2104                  *   we always add 2us there.
2105                  *   - For levels >=1, punit returns 0us latency when they are
2106                  *   disabled, so we respect that and don't add 2us then
2107                  *
2108                  * Additionally, if a level n (n > 1) has a 0us latency, all
2109                  * levels m (m >= n) need to be disabled. We make sure to
2110                  * sanitize the values out of the punit to satisfy this
2111                  * requirement.
2112                  */
2113                 wm[0] += 2;
2114                 for (level = 1; level <= max_level; level++)
2115                         if (wm[level] != 0)
2116                                 wm[level] += 2;
2117                         else {
2118                                 for (i = level + 1; i <= max_level; i++)
2119                                         wm[i] = 0;
2120
2121                                 break;
2122                         }
2123         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2124                 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2125
2126                 wm[0] = (sskpd >> 56) & 0xFF;
2127                 if (wm[0] == 0)
2128                         wm[0] = sskpd & 0xF;
2129                 wm[1] = (sskpd >> 4) & 0xFF;
2130                 wm[2] = (sskpd >> 12) & 0xFF;
2131                 wm[3] = (sskpd >> 20) & 0x1FF;
2132                 wm[4] = (sskpd >> 32) & 0x1FF;
2133         } else if (INTEL_INFO(dev)->gen >= 6) {
2134                 uint32_t sskpd = I915_READ(MCH_SSKPD);
2135
2136                 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2137                 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2138                 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2139                 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2140         } else if (INTEL_INFO(dev)->gen >= 5) {
2141                 uint32_t mltr = I915_READ(MLTR_ILK);
2142
2143                 /* ILK primary LP0 latency is 700 ns */
2144                 wm[0] = 7;
2145                 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2146                 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2147         }
2148 }
2149
2150 static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2151 {
2152         /* ILK sprite LP0 latency is 1300 ns */
2153         if (IS_GEN5(dev))
2154                 wm[0] = 13;
2155 }
2156
2157 static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2158 {
2159         /* ILK cursor LP0 latency is 1300 ns */
2160         if (IS_GEN5(dev))
2161                 wm[0] = 13;
2162
2163         /* WaDoubleCursorLP3Latency:ivb */
2164         if (IS_IVYBRIDGE(dev))
2165                 wm[3] *= 2;
2166 }
2167
2168 int ilk_wm_max_level(const struct drm_device *dev)
2169 {
2170         /* how many WM levels are we expecting */
2171         if (INTEL_INFO(dev)->gen >= 9)
2172                 return 7;
2173         else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2174                 return 4;
2175         else if (INTEL_INFO(dev)->gen >= 6)
2176                 return 3;
2177         else
2178                 return 2;
2179 }
2180
2181 static void intel_print_wm_latency(struct drm_device *dev,
2182                                    const char *name,
2183                                    const uint16_t wm[8])
2184 {
2185         int level, max_level = ilk_wm_max_level(dev);
2186
2187         for (level = 0; level <= max_level; level++) {
2188                 unsigned int latency = wm[level];
2189
2190                 if (latency == 0) {
2191                         DRM_ERROR("%s WM%d latency not provided\n",
2192                                   name, level);
2193                         continue;
2194                 }
2195
2196                 /*
2197                  * - latencies are in us on gen9.
2198                  * - before then, WM1+ latency values are in 0.5us units
2199                  */
2200                 if (IS_GEN9(dev))
2201                         latency *= 10;
2202                 else if (level > 0)
2203                         latency *= 5;
2204
2205                 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2206                               name, level, wm[level],
2207                               latency / 10, latency % 10);
2208         }
2209 }
2210
2211 static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2212                                     uint16_t wm[5], uint16_t min)
2213 {
2214         int level, max_level = ilk_wm_max_level(dev_priv->dev);
2215
2216         if (wm[0] >= min)
2217                 return false;
2218
2219         wm[0] = max(wm[0], min);
2220         for (level = 1; level <= max_level; level++)
2221                 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2222
2223         return true;
2224 }
2225
2226 static void snb_wm_latency_quirk(struct drm_device *dev)
2227 {
2228         struct drm_i915_private *dev_priv = dev->dev_private;
2229         bool changed;
2230
2231         /*
2232          * The BIOS provided WM memory latency values are often
2233          * inadequate for high resolution displays. Adjust them.
2234          */
2235         changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2236                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2237                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2238
2239         if (!changed)
2240                 return;
2241
2242         DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2243         intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2244         intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2245         intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2246 }
2247
2248 static void ilk_setup_wm_latency(struct drm_device *dev)
2249 {
2250         struct drm_i915_private *dev_priv = dev->dev_private;
2251
2252         intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2253
2254         memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2255                sizeof(dev_priv->wm.pri_latency));
2256         memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2257                sizeof(dev_priv->wm.pri_latency));
2258
2259         intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2260         intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
2261
2262         intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2263         intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2264         intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2265
2266         if (IS_GEN6(dev))
2267                 snb_wm_latency_quirk(dev);
2268 }
2269
2270 static void skl_setup_wm_latency(struct drm_device *dev)
2271 {
2272         struct drm_i915_private *dev_priv = dev->dev_private;
2273
2274         intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
2275         intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
2276 }
2277
2278 static bool ilk_validate_pipe_wm(struct drm_device *dev,
2279                                  struct intel_pipe_wm *pipe_wm)
2280 {
2281         /* LP0 watermark maximums depend on this pipe alone */
2282         const struct intel_wm_config config = {
2283                 .num_pipes_active = 1,
2284                 .sprites_enabled = pipe_wm->sprites_enabled,
2285                 .sprites_scaled = pipe_wm->sprites_scaled,
2286         };
2287         struct ilk_wm_maximums max;
2288
2289         /* LP0 watermarks always use 1/2 DDB partitioning */
2290         ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2291
2292         /* At least LP0 must be valid */
2293         if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) {
2294                 DRM_DEBUG_KMS("LP0 watermark invalid\n");
2295                 return false;
2296         }
2297
2298         return true;
2299 }
2300
2301 /* Compute new watermarks for the pipe */
2302 static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
2303 {
2304         struct drm_atomic_state *state = cstate->base.state;
2305         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
2306         struct intel_pipe_wm *pipe_wm;
2307         struct drm_device *dev = state->dev;
2308         const struct drm_i915_private *dev_priv = dev->dev_private;
2309         struct intel_plane *intel_plane;
2310         struct intel_plane_state *pristate = NULL;
2311         struct intel_plane_state *sprstate = NULL;
2312         struct intel_plane_state *curstate = NULL;
2313         int level, max_level = ilk_wm_max_level(dev), usable_level;
2314         struct ilk_wm_maximums max;
2315
2316         pipe_wm = &cstate->wm.ilk.optimal;
2317
2318         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2319                 struct intel_plane_state *ps;
2320
2321                 ps = intel_atomic_get_existing_plane_state(state,
2322                                                            intel_plane);
2323                 if (!ps)
2324                         continue;
2325
2326                 if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY)
2327                         pristate = ps;
2328                 else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY)
2329                         sprstate = ps;
2330                 else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
2331                         curstate = ps;
2332         }
2333
2334         pipe_wm->pipe_enabled = cstate->base.active;
2335         if (sprstate) {
2336                 pipe_wm->sprites_enabled = sprstate->visible;
2337                 pipe_wm->sprites_scaled = sprstate->visible &&
2338                         (drm_rect_width(&sprstate->dst) != drm_rect_width(&sprstate->src) >> 16 ||
2339                          drm_rect_height(&sprstate->dst) != drm_rect_height(&sprstate->src) >> 16);
2340         }
2341
2342         usable_level = max_level;
2343
2344         /* ILK/SNB: LP2+ watermarks only w/o sprites */
2345         if (INTEL_INFO(dev)->gen <= 6 && pipe_wm->sprites_enabled)
2346                 usable_level = 1;
2347
2348         /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2349         if (pipe_wm->sprites_scaled)
2350                 usable_level = 0;
2351
2352         ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
2353                              pristate, sprstate, curstate, &pipe_wm->raw_wm[0]);
2354
2355         memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm));
2356         pipe_wm->wm[0] = pipe_wm->raw_wm[0];
2357
2358         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2359                 pipe_wm->linetime = hsw_compute_linetime_wm(cstate);
2360
2361         if (!ilk_validate_pipe_wm(dev, pipe_wm))
2362                 return -EINVAL;
2363
2364         ilk_compute_wm_reg_maximums(dev, 1, &max);
2365
2366         for (level = 1; level <= max_level; level++) {
2367                 struct intel_wm_level *wm = &pipe_wm->raw_wm[level];
2368
2369                 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,
2370                                      pristate, sprstate, curstate, wm);
2371
2372                 /*
2373                  * Disable any watermark level that exceeds the
2374                  * register maximums since such watermarks are
2375                  * always invalid.
2376                  */
2377                 if (level > usable_level)
2378                         continue;
2379
2380                 if (ilk_validate_wm_level(level, &max, wm))
2381                         pipe_wm->wm[level] = *wm;
2382                 else
2383                         usable_level = level;
2384         }
2385
2386         return 0;
2387 }
2388
2389 /*
2390  * Build a set of 'intermediate' watermark values that satisfy both the old
2391  * state and the new state.  These can be programmed to the hardware
2392  * immediately.
2393  */
2394 static int ilk_compute_intermediate_wm(struct drm_device *dev,
2395                                        struct intel_crtc *intel_crtc,
2396                                        struct intel_crtc_state *newstate)
2397 {
2398         struct intel_pipe_wm *a = &newstate->wm.ilk.intermediate;
2399         struct intel_pipe_wm *b = &intel_crtc->wm.active.ilk;
2400         int level, max_level = ilk_wm_max_level(dev);
2401
2402         /*
2403          * Start with the final, target watermarks, then combine with the
2404          * currently active watermarks to get values that are safe both before
2405          * and after the vblank.
2406          */
2407         *a = newstate->wm.ilk.optimal;
2408         a->pipe_enabled |= b->pipe_enabled;
2409         a->sprites_enabled |= b->sprites_enabled;
2410         a->sprites_scaled |= b->sprites_scaled;
2411
2412         for (level = 0; level <= max_level; level++) {
2413                 struct intel_wm_level *a_wm = &a->wm[level];
2414                 const struct intel_wm_level *b_wm = &b->wm[level];
2415
2416                 a_wm->enable &= b_wm->enable;
2417                 a_wm->pri_val = max(a_wm->pri_val, b_wm->pri_val);
2418                 a_wm->spr_val = max(a_wm->spr_val, b_wm->spr_val);
2419                 a_wm->cur_val = max(a_wm->cur_val, b_wm->cur_val);
2420                 a_wm->fbc_val = max(a_wm->fbc_val, b_wm->fbc_val);
2421         }
2422
2423         /*
2424          * We need to make sure that these merged watermark values are
2425          * actually a valid configuration themselves.  If they're not,
2426          * there's no safe way to transition from the old state to
2427          * the new state, so we need to fail the atomic transaction.
2428          */
2429         if (!ilk_validate_pipe_wm(dev, a))
2430                 return -EINVAL;
2431
2432         /*
2433          * If our intermediate WM are identical to the final WM, then we can
2434          * omit the post-vblank programming; only update if it's different.
2435          */
2436         if (memcmp(a, &newstate->wm.ilk.optimal, sizeof(*a)) == 0)
2437                 newstate->wm.need_postvbl_update = false;
2438
2439         return 0;
2440 }
2441
2442 /*
2443  * Merge the watermarks from all active pipes for a specific level.
2444  */
2445 static void ilk_merge_wm_level(struct drm_device *dev,
2446                                int level,
2447                                struct intel_wm_level *ret_wm)
2448 {
2449         const struct intel_crtc *intel_crtc;
2450
2451         ret_wm->enable = true;
2452
2453         for_each_intel_crtc(dev, intel_crtc) {
2454                 const struct intel_pipe_wm *active = &intel_crtc->wm.active.ilk;
2455                 const struct intel_wm_level *wm = &active->wm[level];
2456
2457                 if (!active->pipe_enabled)
2458                         continue;
2459
2460                 /*
2461                  * The watermark values may have been used in the past,
2462                  * so we must maintain them in the registers for some
2463                  * time even if the level is now disabled.
2464                  */
2465                 if (!wm->enable)
2466                         ret_wm->enable = false;
2467
2468                 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2469                 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2470                 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2471                 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2472         }
2473 }
2474
2475 /*
2476  * Merge all low power watermarks for all active pipes.
2477  */
2478 static void ilk_wm_merge(struct drm_device *dev,
2479                          const struct intel_wm_config *config,
2480                          const struct ilk_wm_maximums *max,
2481                          struct intel_pipe_wm *merged)
2482 {
2483         struct drm_i915_private *dev_priv = dev->dev_private;
2484         int level, max_level = ilk_wm_max_level(dev);
2485         int last_enabled_level = max_level;
2486
2487         /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2488         if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2489             config->num_pipes_active > 1)
2490                 last_enabled_level = 0;
2491
2492         /* ILK: FBC WM must be disabled always */
2493         merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
2494
2495         /* merge each WM1+ level */
2496         for (level = 1; level <= max_level; level++) {
2497                 struct intel_wm_level *wm = &merged->wm[level];
2498
2499                 ilk_merge_wm_level(dev, level, wm);
2500
2501                 if (level > last_enabled_level)
2502                         wm->enable = false;
2503                 else if (!ilk_validate_wm_level(level, max, wm))
2504                         /* make sure all following levels get disabled */
2505                         last_enabled_level = level - 1;
2506
2507                 /*
2508                  * The spec says it is preferred to disable
2509                  * FBC WMs instead of disabling a WM level.
2510                  */
2511                 if (wm->fbc_val > max->fbc) {
2512                         if (wm->enable)
2513                                 merged->fbc_wm_enabled = false;
2514                         wm->fbc_val = 0;
2515                 }
2516         }
2517
2518         /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2519         /*
2520          * FIXME this is racy. FBC might get enabled later.
2521          * What we should check here is whether FBC can be
2522          * enabled sometime later.
2523          */
2524         if (IS_GEN5(dev) && !merged->fbc_wm_enabled &&
2525             intel_fbc_is_active(dev_priv)) {
2526                 for (level = 2; level <= max_level; level++) {
2527                         struct intel_wm_level *wm = &merged->wm[level];
2528
2529                         wm->enable = false;
2530                 }
2531         }
2532 }
2533
2534 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2535 {
2536         /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2537         return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2538 }
2539
2540 /* The value we need to program into the WM_LPx latency field */
2541 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2542 {
2543         struct drm_i915_private *dev_priv = dev->dev_private;
2544
2545         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2546                 return 2 * level;
2547         else
2548                 return dev_priv->wm.pri_latency[level];
2549 }
2550
2551 static void ilk_compute_wm_results(struct drm_device *dev,
2552                                    const struct intel_pipe_wm *merged,
2553                                    enum intel_ddb_partitioning partitioning,
2554                                    struct ilk_wm_values *results)
2555 {
2556         struct intel_crtc *intel_crtc;
2557         int level, wm_lp;
2558
2559         results->enable_fbc_wm = merged->fbc_wm_enabled;
2560         results->partitioning = partitioning;
2561
2562         /* LP1+ register values */
2563         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2564                 const struct intel_wm_level *r;
2565
2566                 level = ilk_wm_lp_to_level(wm_lp, merged);
2567
2568                 r = &merged->wm[level];
2569
2570                 /*
2571                  * Maintain the watermark values even if the level is
2572                  * disabled. Doing otherwise could cause underruns.
2573                  */
2574                 results->wm_lp[wm_lp - 1] =
2575                         (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
2576                         (r->pri_val << WM1_LP_SR_SHIFT) |
2577                         r->cur_val;
2578
2579                 if (r->enable)
2580                         results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2581
2582                 if (INTEL_INFO(dev)->gen >= 8)
2583                         results->wm_lp[wm_lp - 1] |=
2584                                 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2585                 else
2586                         results->wm_lp[wm_lp - 1] |=
2587                                 r->fbc_val << WM1_LP_FBC_SHIFT;
2588
2589                 /*
2590                  * Always set WM1S_LP_EN when spr_val != 0, even if the
2591                  * level is disabled. Doing otherwise could cause underruns.
2592                  */
2593                 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2594                         WARN_ON(wm_lp != 1);
2595                         results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2596                 } else
2597                         results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2598         }
2599
2600         /* LP0 register values */
2601         for_each_intel_crtc(dev, intel_crtc) {
2602                 enum pipe pipe = intel_crtc->pipe;
2603                 const struct intel_wm_level *r =
2604                         &intel_crtc->wm.active.ilk.wm[0];
2605
2606                 if (WARN_ON(!r->enable))
2607                         continue;
2608
2609                 results->wm_linetime[pipe] = intel_crtc->wm.active.ilk.linetime;
2610
2611                 results->wm_pipe[pipe] =
2612                         (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2613                         (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2614                         r->cur_val;
2615         }
2616 }
2617
2618 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2619  * case both are at the same level. Prefer r1 in case they're the same. */
2620 static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
2621                                                   struct intel_pipe_wm *r1,
2622                                                   struct intel_pipe_wm *r2)
2623 {
2624         int level, max_level = ilk_wm_max_level(dev);
2625         int level1 = 0, level2 = 0;
2626
2627         for (level = 1; level <= max_level; level++) {
2628                 if (r1->wm[level].enable)
2629                         level1 = level;
2630                 if (r2->wm[level].enable)
2631                         level2 = level;
2632         }
2633
2634         if (level1 == level2) {
2635                 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2636                         return r2;
2637                 else
2638                         return r1;
2639         } else if (level1 > level2) {
2640                 return r1;
2641         } else {
2642                 return r2;
2643         }
2644 }
2645
2646 /* dirty bits used to track which watermarks need changes */
2647 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2648 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2649 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2650 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2651 #define WM_DIRTY_FBC (1 << 24)
2652 #define WM_DIRTY_DDB (1 << 25)
2653
2654 static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
2655                                          const struct ilk_wm_values *old,
2656                                          const struct ilk_wm_values *new)
2657 {
2658         unsigned int dirty = 0;
2659         enum pipe pipe;
2660         int wm_lp;
2661
2662         for_each_pipe(dev_priv, pipe) {
2663                 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2664                         dirty |= WM_DIRTY_LINETIME(pipe);
2665                         /* Must disable LP1+ watermarks too */
2666                         dirty |= WM_DIRTY_LP_ALL;
2667                 }
2668
2669                 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2670                         dirty |= WM_DIRTY_PIPE(pipe);
2671                         /* Must disable LP1+ watermarks too */
2672                         dirty |= WM_DIRTY_LP_ALL;
2673                 }
2674         }
2675
2676         if (old->enable_fbc_wm != new->enable_fbc_wm) {
2677                 dirty |= WM_DIRTY_FBC;
2678                 /* Must disable LP1+ watermarks too */
2679                 dirty |= WM_DIRTY_LP_ALL;
2680         }
2681
2682         if (old->partitioning != new->partitioning) {
2683                 dirty |= WM_DIRTY_DDB;
2684                 /* Must disable LP1+ watermarks too */
2685                 dirty |= WM_DIRTY_LP_ALL;
2686         }
2687
2688         /* LP1+ watermarks already deemed dirty, no need to continue */
2689         if (dirty & WM_DIRTY_LP_ALL)
2690                 return dirty;
2691
2692         /* Find the lowest numbered LP1+ watermark in need of an update... */
2693         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2694                 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2695                     old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2696                         break;
2697         }
2698
2699         /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2700         for (; wm_lp <= 3; wm_lp++)
2701                 dirty |= WM_DIRTY_LP(wm_lp);
2702
2703         return dirty;
2704 }
2705
2706 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2707                                unsigned int dirty)
2708 {
2709         struct ilk_wm_values *previous = &dev_priv->wm.hw;
2710         bool changed = false;
2711
2712         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2713                 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2714                 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
2715                 changed = true;
2716         }
2717         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2718                 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2719                 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
2720                 changed = true;
2721         }
2722         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2723                 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2724                 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
2725                 changed = true;
2726         }
2727
2728         /*
2729          * Don't touch WM1S_LP_EN here.
2730          * Doing so could cause underruns.
2731          */
2732
2733         return changed;
2734 }
2735
2736 /*
2737  * The spec says we shouldn't write when we don't need, because every write
2738  * causes WMs to be re-evaluated, expending some power.
2739  */
2740 static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2741                                 struct ilk_wm_values *results)
2742 {
2743         struct drm_device *dev = dev_priv->dev;
2744         struct ilk_wm_values *previous = &dev_priv->wm.hw;
2745         unsigned int dirty;
2746         uint32_t val;
2747
2748         dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
2749         if (!dirty)
2750                 return;
2751
2752         _ilk_disable_lp_wm(dev_priv, dirty);
2753
2754         if (dirty & WM_DIRTY_PIPE(PIPE_A))
2755                 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2756         if (dirty & WM_DIRTY_PIPE(PIPE_B))
2757                 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2758         if (dirty & WM_DIRTY_PIPE(PIPE_C))
2759                 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2760
2761         if (dirty & WM_DIRTY_LINETIME(PIPE_A))
2762                 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2763         if (dirty & WM_DIRTY_LINETIME(PIPE_B))
2764                 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2765         if (dirty & WM_DIRTY_LINETIME(PIPE_C))
2766                 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2767
2768         if (dirty & WM_DIRTY_DDB) {
2769                 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2770                         val = I915_READ(WM_MISC);
2771                         if (results->partitioning == INTEL_DDB_PART_1_2)
2772                                 val &= ~WM_MISC_DATA_PARTITION_5_6;
2773                         else
2774                                 val |= WM_MISC_DATA_PARTITION_5_6;
2775                         I915_WRITE(WM_MISC, val);
2776                 } else {
2777                         val = I915_READ(DISP_ARB_CTL2);
2778                         if (results->partitioning == INTEL_DDB_PART_1_2)
2779                                 val &= ~DISP_DATA_PARTITION_5_6;
2780                         else
2781                                 val |= DISP_DATA_PARTITION_5_6;
2782                         I915_WRITE(DISP_ARB_CTL2, val);
2783                 }
2784         }
2785
2786         if (dirty & WM_DIRTY_FBC) {
2787                 val = I915_READ(DISP_ARB_CTL);
2788                 if (results->enable_fbc_wm)
2789                         val &= ~DISP_FBC_WM_DIS;
2790                 else
2791                         val |= DISP_FBC_WM_DIS;
2792                 I915_WRITE(DISP_ARB_CTL, val);
2793         }
2794
2795         if (dirty & WM_DIRTY_LP(1) &&
2796             previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2797                 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2798
2799         if (INTEL_INFO(dev)->gen >= 7) {
2800                 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2801                         I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2802                 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2803                         I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2804         }
2805
2806         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
2807                 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2808         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
2809                 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2810         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
2811                 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2812
2813         dev_priv->wm.hw = *results;
2814 }
2815
2816 bool ilk_disable_lp_wm(struct drm_device *dev)
2817 {
2818         struct drm_i915_private *dev_priv = dev->dev_private;
2819
2820         return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2821 }
2822
2823 /*
2824  * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
2825  * different active planes.
2826  */
2827
2828 #define SKL_DDB_SIZE            896     /* in blocks */
2829 #define BXT_DDB_SIZE            512
2830
2831 /*
2832  * Return the index of a plane in the SKL DDB and wm result arrays.  Primary
2833  * plane is always in slot 0, cursor is always in slot I915_MAX_PLANES-1, and
2834  * other universal planes are in indices 1..n.  Note that this may leave unused
2835  * indices between the top "sprite" plane and the cursor.
2836  */
2837 static int
2838 skl_wm_plane_id(const struct intel_plane *plane)
2839 {
2840         switch (plane->base.type) {
2841         case DRM_PLANE_TYPE_PRIMARY:
2842                 return 0;
2843         case DRM_PLANE_TYPE_CURSOR:
2844                 return PLANE_CURSOR;
2845         case DRM_PLANE_TYPE_OVERLAY:
2846                 return plane->plane + 1;
2847         default:
2848                 MISSING_CASE(plane->base.type);
2849                 return plane->plane;
2850         }
2851 }
2852
2853 static void
2854 skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
2855                                    const struct intel_crtc_state *cstate,
2856                                    struct skl_ddb_entry *alloc, /* out */
2857                                    int *num_active /* out */)
2858 {
2859         struct drm_atomic_state *state = cstate->base.state;
2860         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
2861         struct drm_i915_private *dev_priv = to_i915(dev);
2862         struct drm_crtc *for_crtc = cstate->base.crtc;
2863         unsigned int pipe_size, ddb_size;
2864         int nth_active_pipe;
2865         int pipe = to_intel_crtc(for_crtc)->pipe;
2866
2867         if (WARN_ON(!state) || !cstate->base.active) {
2868                 alloc->start = 0;
2869                 alloc->end = 0;
2870                 *num_active = hweight32(dev_priv->active_crtcs);
2871                 return;
2872         }
2873
2874         if (intel_state->active_pipe_changes)
2875                 *num_active = hweight32(intel_state->active_crtcs);
2876         else
2877                 *num_active = hweight32(dev_priv->active_crtcs);
2878
2879         if (IS_BROXTON(dev))
2880                 ddb_size = BXT_DDB_SIZE;
2881         else
2882                 ddb_size = SKL_DDB_SIZE;
2883
2884         ddb_size -= 4; /* 4 blocks for bypass path allocation */
2885
2886         /*
2887          * If the state doesn't change the active CRTC's, then there's
2888          * no need to recalculate; the existing pipe allocation limits
2889          * should remain unchanged.  Note that we're safe from racing
2890          * commits since any racing commit that changes the active CRTC
2891          * list would need to grab _all_ crtc locks, including the one
2892          * we currently hold.
2893          */
2894         if (!intel_state->active_pipe_changes) {
2895                 *alloc = dev_priv->wm.skl_hw.ddb.pipe[pipe];
2896                 return;
2897         }
2898
2899         nth_active_pipe = hweight32(intel_state->active_crtcs &
2900                                     (drm_crtc_mask(for_crtc) - 1));
2901         pipe_size = ddb_size / hweight32(intel_state->active_crtcs);
2902         alloc->start = nth_active_pipe * ddb_size / *num_active;
2903         alloc->end = alloc->start + pipe_size;
2904 }
2905
2906 static unsigned int skl_cursor_allocation(int num_active)
2907 {
2908         if (num_active == 1)
2909                 return 32;
2910
2911         return 8;
2912 }
2913
2914 static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
2915 {
2916         entry->start = reg & 0x3ff;
2917         entry->end = (reg >> 16) & 0x3ff;
2918         if (entry->end)
2919                 entry->end += 1;
2920 }
2921
2922 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2923                           struct skl_ddb_allocation *ddb /* out */)
2924 {
2925         enum pipe pipe;
2926         int plane;
2927         u32 val;
2928
2929         memset(ddb, 0, sizeof(*ddb));
2930
2931         for_each_pipe(dev_priv, pipe) {
2932                 enum intel_display_power_domain power_domain;
2933
2934                 power_domain = POWER_DOMAIN_PIPE(pipe);
2935                 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
2936                         continue;
2937
2938                 for_each_plane(dev_priv, pipe, plane) {
2939                         val = I915_READ(PLANE_BUF_CFG(pipe, plane));
2940                         skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
2941                                                    val);
2942                 }
2943
2944                 val = I915_READ(CUR_BUF_CFG(pipe));
2945                 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR],
2946                                            val);
2947
2948                 intel_display_power_put(dev_priv, power_domain);
2949         }
2950 }
2951
2952 static unsigned int
2953 skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
2954                              const struct drm_plane_state *pstate,
2955                              int y)
2956 {
2957         struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
2958         struct drm_framebuffer *fb = pstate->fb;
2959         uint32_t width = 0, height = 0;
2960         unsigned format = fb ? fb->pixel_format : DRM_FORMAT_XRGB8888;
2961
2962         if (!intel_pstate->visible)
2963                 return 0;
2964         if (pstate->plane->type == DRM_PLANE_TYPE_CURSOR)
2965                 return 0;
2966         if (y && format != DRM_FORMAT_NV12)
2967                 return 0;
2968
2969         width = drm_rect_width(&intel_pstate->src) >> 16;
2970         height = drm_rect_height(&intel_pstate->src) >> 16;
2971
2972         if (intel_rotation_90_or_270(pstate->rotation))
2973                 swap(width, height);
2974
2975         /* for planar format */
2976         if (format == DRM_FORMAT_NV12) {
2977                 if (y)  /* y-plane data rate */
2978                         return width * height *
2979                                 drm_format_plane_cpp(format, 0);
2980                 else    /* uv-plane data rate */
2981                         return (width / 2) * (height / 2) *
2982                                 drm_format_plane_cpp(format, 1);
2983         }
2984
2985         /* for packed formats */
2986         return width * height * drm_format_plane_cpp(format, 0);
2987 }
2988
2989 /*
2990  * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
2991  * a 8192x4096@32bpp framebuffer:
2992  *   3 * 4096 * 8192  * 4 < 2^32
2993  */
2994 static unsigned int
2995 skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate)
2996 {
2997         struct drm_crtc_state *cstate = &intel_cstate->base;
2998         struct drm_atomic_state *state = cstate->state;
2999         struct drm_crtc *crtc = cstate->crtc;
3000         struct drm_device *dev = crtc->dev;
3001         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3002         const struct drm_plane *plane;
3003         const struct intel_plane *intel_plane;
3004         struct drm_plane_state *pstate;
3005         unsigned int rate, total_data_rate = 0;
3006         int id;
3007         int i;
3008
3009         if (WARN_ON(!state))
3010                 return 0;
3011
3012         /* Calculate and cache data rate for each plane */
3013         for_each_plane_in_state(state, plane, pstate, i) {
3014                 id = skl_wm_plane_id(to_intel_plane(plane));
3015                 intel_plane = to_intel_plane(plane);
3016
3017                 if (intel_plane->pipe != intel_crtc->pipe)
3018                         continue;
3019
3020                 /* packed/uv */
3021                 rate = skl_plane_relative_data_rate(intel_cstate,
3022                                                     pstate, 0);
3023                 intel_cstate->wm.skl.plane_data_rate[id] = rate;
3024
3025                 /* y-plane */
3026                 rate = skl_plane_relative_data_rate(intel_cstate,
3027                                                     pstate, 1);
3028                 intel_cstate->wm.skl.plane_y_data_rate[id] = rate;
3029         }
3030
3031         /* Calculate CRTC's total data rate from cached values */
3032         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3033                 int id = skl_wm_plane_id(intel_plane);
3034
3035                 /* packed/uv */
3036                 total_data_rate += intel_cstate->wm.skl.plane_data_rate[id];
3037                 total_data_rate += intel_cstate->wm.skl.plane_y_data_rate[id];
3038         }
3039
3040         WARN_ON(cstate->plane_mask && total_data_rate == 0);
3041
3042         return total_data_rate;
3043 }
3044
3045 static int
3046 skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
3047                       struct skl_ddb_allocation *ddb /* out */)
3048 {
3049         struct drm_atomic_state *state = cstate->base.state;
3050         struct drm_crtc *crtc = cstate->base.crtc;
3051         struct drm_device *dev = crtc->dev;
3052         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3053         struct intel_plane *intel_plane;
3054         struct drm_plane *plane;
3055         struct drm_plane_state *pstate;
3056         enum pipe pipe = intel_crtc->pipe;
3057         struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
3058         uint16_t alloc_size, start, cursor_blocks;
3059         uint16_t *minimum = cstate->wm.skl.minimum_blocks;
3060         uint16_t *y_minimum = cstate->wm.skl.minimum_y_blocks;
3061         unsigned int total_data_rate;
3062         int num_active;
3063         int id, i;
3064
3065         if (WARN_ON(!state))
3066                 return 0;
3067
3068         if (!cstate->base.active) {
3069                 ddb->pipe[pipe].start = ddb->pipe[pipe].end = 0;
3070                 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
3071                 memset(ddb->y_plane[pipe], 0, sizeof(ddb->y_plane[pipe]));
3072                 return 0;
3073         }
3074
3075         skl_ddb_get_pipe_allocation_limits(dev, cstate, alloc, &num_active);
3076         alloc_size = skl_ddb_entry_size(alloc);
3077         if (alloc_size == 0) {
3078                 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
3079                 return 0;
3080         }
3081
3082         cursor_blocks = skl_cursor_allocation(num_active);
3083         ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - cursor_blocks;
3084         ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
3085
3086         alloc_size -= cursor_blocks;
3087
3088         /* 1. Allocate the mininum required blocks for each active plane */
3089         for_each_plane_in_state(state, plane, pstate, i) {
3090                 intel_plane = to_intel_plane(plane);
3091                 id = skl_wm_plane_id(intel_plane);
3092
3093                 if (intel_plane->pipe != pipe)
3094                         continue;
3095
3096                 if (!to_intel_plane_state(pstate)->visible) {
3097                         minimum[id] = 0;
3098                         y_minimum[id] = 0;
3099                         continue;
3100                 }
3101                 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
3102                         minimum[id] = 0;
3103                         y_minimum[id] = 0;
3104                         continue;
3105                 }
3106
3107                 minimum[id] = 8;
3108                 if (pstate->fb->pixel_format == DRM_FORMAT_NV12)
3109                         y_minimum[id] = 8;
3110                 else
3111                         y_minimum[id] = 0;
3112         }
3113
3114         for (i = 0; i < PLANE_CURSOR; i++) {
3115                 alloc_size -= minimum[i];
3116                 alloc_size -= y_minimum[i];
3117         }
3118
3119         /*
3120          * 2. Distribute the remaining space in proportion to the amount of
3121          * data each plane needs to fetch from memory.
3122          *
3123          * FIXME: we may not allocate every single block here.
3124          */
3125         total_data_rate = skl_get_total_relative_data_rate(cstate);
3126         if (total_data_rate == 0)
3127                 return 0;
3128
3129         start = alloc->start;
3130         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3131                 unsigned int data_rate, y_data_rate;
3132                 uint16_t plane_blocks, y_plane_blocks = 0;
3133                 int id = skl_wm_plane_id(intel_plane);
3134
3135                 data_rate = cstate->wm.skl.plane_data_rate[id];
3136
3137                 /*
3138                  * allocation for (packed formats) or (uv-plane part of planar format):
3139                  * promote the expression to 64 bits to avoid overflowing, the
3140                  * result is < available as data_rate / total_data_rate < 1
3141                  */
3142                 plane_blocks = minimum[id];
3143                 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
3144                                         total_data_rate);
3145
3146                 /* Leave disabled planes at (0,0) */
3147                 if (data_rate) {
3148                         ddb->plane[pipe][id].start = start;
3149                         ddb->plane[pipe][id].end = start + plane_blocks;
3150                 }
3151
3152                 start += plane_blocks;
3153
3154                 /*
3155                  * allocation for y_plane part of planar format:
3156                  */
3157                 y_data_rate = cstate->wm.skl.plane_y_data_rate[id];
3158
3159                 y_plane_blocks = y_minimum[id];
3160                 y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
3161                                         total_data_rate);
3162
3163                 if (y_data_rate) {
3164                         ddb->y_plane[pipe][id].start = start;
3165                         ddb->y_plane[pipe][id].end = start + y_plane_blocks;
3166                 }
3167
3168                 start += y_plane_blocks;
3169         }
3170
3171         return 0;
3172 }
3173
3174 static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
3175 {
3176         /* TODO: Take into account the scalers once we support them */
3177         return config->base.adjusted_mode.crtc_clock;
3178 }
3179
3180 /*
3181  * The max latency should be 257 (max the punit can code is 255 and we add 2us
3182  * for the read latency) and cpp should always be <= 8, so that
3183  * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3184  * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3185 */
3186 static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
3187 {
3188         uint32_t wm_intermediate_val, ret;
3189
3190         if (latency == 0)
3191                 return UINT_MAX;
3192
3193         wm_intermediate_val = latency * pixel_rate * cpp / 512;
3194         ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
3195
3196         return ret;
3197 }
3198
3199 static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
3200                                uint32_t horiz_pixels, uint8_t cpp,
3201                                uint64_t tiling, uint32_t latency)
3202 {
3203         uint32_t ret;
3204         uint32_t plane_bytes_per_line, plane_blocks_per_line;
3205         uint32_t wm_intermediate_val;
3206
3207         if (latency == 0)
3208                 return UINT_MAX;
3209
3210         plane_bytes_per_line = horiz_pixels * cpp;
3211
3212         if (tiling == I915_FORMAT_MOD_Y_TILED ||
3213             tiling == I915_FORMAT_MOD_Yf_TILED) {
3214                 plane_bytes_per_line *= 4;
3215                 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3216                 plane_blocks_per_line /= 4;
3217         } else {
3218                 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3219         }
3220
3221         wm_intermediate_val = latency * pixel_rate;
3222         ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
3223                                 plane_blocks_per_line;
3224
3225         return ret;
3226 }
3227
3228 static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
3229                                 struct intel_crtc_state *cstate,
3230                                 struct intel_plane_state *intel_pstate,
3231                                 uint16_t ddb_allocation,
3232                                 int level,
3233                                 uint16_t *out_blocks, /* out */
3234                                 uint8_t *out_lines, /* out */
3235                                 bool *enabled /* out */)
3236 {
3237         struct drm_plane_state *pstate = &intel_pstate->base;
3238         struct drm_framebuffer *fb = pstate->fb;
3239         uint32_t latency = dev_priv->wm.skl_latency[level];
3240         uint32_t method1, method2;
3241         uint32_t plane_bytes_per_line, plane_blocks_per_line;
3242         uint32_t res_blocks, res_lines;
3243         uint32_t selected_result;
3244         uint8_t cpp;
3245         uint32_t width = 0, height = 0;
3246
3247         if (latency == 0 || !cstate->base.active || !intel_pstate->visible) {
3248                 *enabled = false;
3249                 return 0;
3250         }
3251
3252         width = drm_rect_width(&intel_pstate->src) >> 16;
3253         height = drm_rect_height(&intel_pstate->src) >> 16;
3254
3255         if (intel_rotation_90_or_270(pstate->rotation))
3256                 swap(width, height);
3257
3258         cpp = drm_format_plane_cpp(fb->pixel_format, 0);
3259         method1 = skl_wm_method1(skl_pipe_pixel_rate(cstate),
3260                                  cpp, latency);
3261         method2 = skl_wm_method2(skl_pipe_pixel_rate(cstate),
3262                                  cstate->base.adjusted_mode.crtc_htotal,
3263                                  width,
3264                                  cpp,
3265                                  fb->modifier[0],
3266                                  latency);
3267
3268         plane_bytes_per_line = width * cpp;
3269         plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3270
3271         if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3272             fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
3273                 uint32_t min_scanlines = 4;
3274                 uint32_t y_tile_minimum;
3275                 if (intel_rotation_90_or_270(pstate->rotation)) {
3276                         int cpp = (fb->pixel_format == DRM_FORMAT_NV12) ?
3277                                 drm_format_plane_cpp(fb->pixel_format, 1) :
3278                                 drm_format_plane_cpp(fb->pixel_format, 0);
3279
3280                         switch (cpp) {
3281                         case 1:
3282                                 min_scanlines = 16;
3283                                 break;
3284                         case 2:
3285                                 min_scanlines = 8;
3286                                 break;
3287                         case 8:
3288                                 WARN(1, "Unsupported pixel depth for rotation");
3289                         }
3290                 }
3291                 y_tile_minimum = plane_blocks_per_line * min_scanlines;
3292                 selected_result = max(method2, y_tile_minimum);
3293         } else {
3294                 if ((ddb_allocation / plane_blocks_per_line) >= 1)
3295                         selected_result = min(method1, method2);
3296                 else
3297                         selected_result = method1;
3298         }
3299
3300         res_blocks = selected_result + 1;
3301         res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
3302
3303         if (level >= 1 && level <= 7) {
3304                 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3305                     fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED)
3306                         res_lines += 4;
3307                 else
3308                         res_blocks++;
3309         }
3310
3311         if (res_blocks >= ddb_allocation || res_lines > 31) {
3312                 *enabled = false;
3313
3314                 /*
3315                  * If there are no valid level 0 watermarks, then we can't
3316                  * support this display configuration.
3317                  */
3318                 if (level) {
3319                         return 0;
3320                 } else {
3321                         DRM_DEBUG_KMS("Requested display configuration exceeds system watermark limitations\n");
3322                         DRM_DEBUG_KMS("Plane %d.%d: blocks required = %u/%u, lines required = %u/31\n",
3323                                       to_intel_crtc(cstate->base.crtc)->pipe,
3324                                       skl_wm_plane_id(to_intel_plane(pstate->plane)),
3325                                       res_blocks, ddb_allocation, res_lines);
3326
3327                         return -EINVAL;
3328                 }
3329         }
3330
3331         *out_blocks = res_blocks;
3332         *out_lines = res_lines;
3333         *enabled = true;
3334
3335         return 0;
3336 }
3337
3338 static int
3339 skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3340                      struct skl_ddb_allocation *ddb,
3341                      struct intel_crtc_state *cstate,
3342                      int level,
3343                      struct skl_wm_level *result)
3344 {
3345         struct drm_device *dev = dev_priv->dev;
3346         struct drm_atomic_state *state = cstate->base.state;
3347         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
3348         struct drm_plane *plane;
3349         struct intel_plane *intel_plane;
3350         struct intel_plane_state *intel_pstate;
3351         uint16_t ddb_blocks;
3352         enum pipe pipe = intel_crtc->pipe;
3353         int ret;
3354
3355         /*
3356          * We'll only calculate watermarks for planes that are actually
3357          * enabled, so make sure all other planes are set as disabled.
3358          */
3359         memset(result, 0, sizeof(*result));
3360
3361         for_each_intel_plane_mask(dev, intel_plane, cstate->base.plane_mask) {
3362                 int i = skl_wm_plane_id(intel_plane);
3363
3364                 plane = &intel_plane->base;
3365                 intel_pstate = NULL;
3366                 if (state)
3367                         intel_pstate =
3368                                 intel_atomic_get_existing_plane_state(state,
3369                                                                       intel_plane);
3370
3371                 /*
3372                  * Note: If we start supporting multiple pending atomic commits
3373                  * against the same planes/CRTC's in the future, plane->state
3374                  * will no longer be the correct pre-state to use for the
3375                  * calculations here and we'll need to change where we get the
3376                  * 'unchanged' plane data from.
3377                  *
3378                  * For now this is fine because we only allow one queued commit
3379                  * against a CRTC.  Even if the plane isn't modified by this
3380                  * transaction and we don't have a plane lock, we still have
3381                  * the CRTC's lock, so we know that no other transactions are
3382                  * racing with us to update it.
3383                  */
3384                 if (!intel_pstate)
3385                         intel_pstate = to_intel_plane_state(plane->state);
3386
3387                 WARN_ON(!intel_pstate->base.fb);
3388
3389                 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
3390
3391                 ret = skl_compute_plane_wm(dev_priv,
3392                                            cstate,
3393                                            intel_pstate,
3394                                            ddb_blocks,
3395                                            level,
3396                                            &result->plane_res_b[i],
3397                                            &result->plane_res_l[i],
3398                                            &result->plane_en[i]);
3399                 if (ret)
3400                         return ret;
3401         }
3402
3403         return 0;
3404 }
3405
3406 static uint32_t
3407 skl_compute_linetime_wm(struct intel_crtc_state *cstate)
3408 {
3409         if (!cstate->base.active)
3410                 return 0;
3411
3412         if (WARN_ON(skl_pipe_pixel_rate(cstate) == 0))
3413                 return 0;
3414
3415         return DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * 1000,
3416                             skl_pipe_pixel_rate(cstate));
3417 }
3418
3419 static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
3420                                       struct skl_wm_level *trans_wm /* out */)
3421 {
3422         struct drm_crtc *crtc = cstate->base.crtc;
3423         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3424         struct intel_plane *intel_plane;
3425
3426         if (!cstate->base.active)
3427                 return;
3428
3429         /* Until we know more, just disable transition WMs */
3430         for_each_intel_plane_on_crtc(crtc->dev, intel_crtc, intel_plane) {
3431                 int i = skl_wm_plane_id(intel_plane);
3432
3433                 trans_wm->plane_en[i] = false;
3434         }
3435 }
3436
3437 static int skl_build_pipe_wm(struct intel_crtc_state *cstate,
3438                              struct skl_ddb_allocation *ddb,
3439                              struct skl_pipe_wm *pipe_wm)
3440 {
3441         struct drm_device *dev = cstate->base.crtc->dev;
3442         const struct drm_i915_private *dev_priv = dev->dev_private;
3443         int level, max_level = ilk_wm_max_level(dev);
3444         int ret;
3445
3446         for (level = 0; level <= max_level; level++) {
3447                 ret = skl_compute_wm_level(dev_priv, ddb, cstate,
3448                                            level, &pipe_wm->wm[level]);
3449                 if (ret)
3450                         return ret;
3451         }
3452         pipe_wm->linetime = skl_compute_linetime_wm(cstate);
3453
3454         skl_compute_transition_wm(cstate, &pipe_wm->trans_wm);
3455
3456         return 0;
3457 }
3458
3459 static void skl_compute_wm_results(struct drm_device *dev,
3460                                    struct skl_pipe_wm *p_wm,
3461                                    struct skl_wm_values *r,
3462                                    struct intel_crtc *intel_crtc)
3463 {
3464         int level, max_level = ilk_wm_max_level(dev);
3465         enum pipe pipe = intel_crtc->pipe;
3466         uint32_t temp;
3467         int i;
3468
3469         for (level = 0; level <= max_level; level++) {
3470                 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3471                         temp = 0;
3472
3473                         temp |= p_wm->wm[level].plane_res_l[i] <<
3474                                         PLANE_WM_LINES_SHIFT;
3475                         temp |= p_wm->wm[level].plane_res_b[i];
3476                         if (p_wm->wm[level].plane_en[i])
3477                                 temp |= PLANE_WM_EN;
3478
3479                         r->plane[pipe][i][level] = temp;
3480                 }
3481
3482                 temp = 0;
3483
3484                 temp |= p_wm->wm[level].plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3485                 temp |= p_wm->wm[level].plane_res_b[PLANE_CURSOR];
3486
3487                 if (p_wm->wm[level].plane_en[PLANE_CURSOR])
3488                         temp |= PLANE_WM_EN;
3489
3490                 r->plane[pipe][PLANE_CURSOR][level] = temp;
3491
3492         }
3493
3494         /* transition WMs */
3495         for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3496                 temp = 0;
3497                 temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT;
3498                 temp |= p_wm->trans_wm.plane_res_b[i];
3499                 if (p_wm->trans_wm.plane_en[i])
3500                         temp |= PLANE_WM_EN;
3501
3502                 r->plane_trans[pipe][i] = temp;
3503         }
3504
3505         temp = 0;
3506         temp |= p_wm->trans_wm.plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3507         temp |= p_wm->trans_wm.plane_res_b[PLANE_CURSOR];
3508         if (p_wm->trans_wm.plane_en[PLANE_CURSOR])
3509                 temp |= PLANE_WM_EN;
3510
3511         r->plane_trans[pipe][PLANE_CURSOR] = temp;
3512
3513         r->wm_linetime[pipe] = p_wm->linetime;
3514 }
3515
3516 static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
3517                                 i915_reg_t reg,
3518                                 const struct skl_ddb_entry *entry)
3519 {
3520         if (entry->end)
3521                 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3522         else
3523                 I915_WRITE(reg, 0);
3524 }
3525
3526 static void skl_write_wm_values(struct drm_i915_private *dev_priv,
3527                                 const struct skl_wm_values *new)
3528 {
3529         struct drm_device *dev = dev_priv->dev;
3530         struct intel_crtc *crtc;
3531
3532         for_each_intel_crtc(dev, crtc) {
3533                 int i, level, max_level = ilk_wm_max_level(dev);
3534                 enum pipe pipe = crtc->pipe;
3535
3536                 if ((new->dirty_pipes & drm_crtc_mask(&crtc->base)) == 0)
3537                         continue;
3538                 if (!crtc->active)
3539                         continue;
3540
3541                 I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]);
3542
3543                 for (level = 0; level <= max_level; level++) {
3544                         for (i = 0; i < intel_num_planes(crtc); i++)
3545                                 I915_WRITE(PLANE_WM(pipe, i, level),
3546                                            new->plane[pipe][i][level]);
3547                         I915_WRITE(CUR_WM(pipe, level),
3548                                    new->plane[pipe][PLANE_CURSOR][level]);
3549                 }
3550                 for (i = 0; i < intel_num_planes(crtc); i++)
3551                         I915_WRITE(PLANE_WM_TRANS(pipe, i),
3552                                    new->plane_trans[pipe][i]);
3553                 I915_WRITE(CUR_WM_TRANS(pipe),
3554                            new->plane_trans[pipe][PLANE_CURSOR]);
3555
3556                 for (i = 0; i < intel_num_planes(crtc); i++) {
3557                         skl_ddb_entry_write(dev_priv,
3558                                             PLANE_BUF_CFG(pipe, i),
3559                                             &new->ddb.plane[pipe][i]);
3560                         skl_ddb_entry_write(dev_priv,
3561                                             PLANE_NV12_BUF_CFG(pipe, i),
3562                                             &new->ddb.y_plane[pipe][i]);
3563                 }
3564
3565                 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
3566                                     &new->ddb.plane[pipe][PLANE_CURSOR]);
3567         }
3568 }
3569
3570 /*
3571  * When setting up a new DDB allocation arrangement, we need to correctly
3572  * sequence the times at which the new allocations for the pipes are taken into
3573  * account or we'll have pipes fetching from space previously allocated to
3574  * another pipe.
3575  *
3576  * Roughly the sequence looks like:
3577  *  1. re-allocate the pipe(s) with the allocation being reduced and not
3578  *     overlapping with a previous light-up pipe (another way to put it is:
3579  *     pipes with their new allocation strickly included into their old ones).
3580  *  2. re-allocate the other pipes that get their allocation reduced
3581  *  3. allocate the pipes having their allocation increased
3582  *
3583  * Steps 1. and 2. are here to take care of the following case:
3584  * - Initially DDB looks like this:
3585  *     |   B    |   C    |
3586  * - enable pipe A.
3587  * - pipe B has a reduced DDB allocation that overlaps with the old pipe C
3588  *   allocation
3589  *     |  A  |  B  |  C  |
3590  *
3591  * We need to sequence the re-allocation: C, B, A (and not B, C, A).
3592  */
3593
3594 static void
3595 skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int pass)
3596 {
3597         int plane;
3598
3599         DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass);
3600
3601         for_each_plane(dev_priv, pipe, plane) {
3602                 I915_WRITE(PLANE_SURF(pipe, plane),
3603                            I915_READ(PLANE_SURF(pipe, plane)));
3604         }
3605         I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3606 }
3607
3608 static bool
3609 skl_ddb_allocation_included(const struct skl_ddb_allocation *old,
3610                             const struct skl_ddb_allocation *new,
3611                             enum pipe pipe)
3612 {
3613         uint16_t old_size, new_size;
3614
3615         old_size = skl_ddb_entry_size(&old->pipe[pipe]);
3616         new_size = skl_ddb_entry_size(&new->pipe[pipe]);
3617
3618         return old_size != new_size &&
3619                new->pipe[pipe].start >= old->pipe[pipe].start &&
3620                new->pipe[pipe].end <= old->pipe[pipe].end;
3621 }
3622
3623 static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
3624                                 struct skl_wm_values *new_values)
3625 {
3626         struct drm_device *dev = dev_priv->dev;
3627         struct skl_ddb_allocation *cur_ddb, *new_ddb;
3628         bool reallocated[I915_MAX_PIPES] = {};
3629         struct intel_crtc *crtc;
3630         enum pipe pipe;
3631
3632         new_ddb = &new_values->ddb;
3633         cur_ddb = &dev_priv->wm.skl_hw.ddb;
3634
3635         /*
3636          * First pass: flush the pipes with the new allocation contained into
3637          * the old space.
3638          *
3639          * We'll wait for the vblank on those pipes to ensure we can safely
3640          * re-allocate the freed space without this pipe fetching from it.
3641          */
3642         for_each_intel_crtc(dev, crtc) {
3643                 if (!crtc->active)
3644                         continue;
3645
3646                 pipe = crtc->pipe;
3647
3648                 if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe))
3649                         continue;
3650
3651                 skl_wm_flush_pipe(dev_priv, pipe, 1);
3652                 intel_wait_for_vblank(dev, pipe);
3653
3654                 reallocated[pipe] = true;
3655         }
3656
3657
3658         /*
3659          * Second pass: flush the pipes that are having their allocation
3660          * reduced, but overlapping with a previous allocation.
3661          *
3662          * Here as well we need to wait for the vblank to make sure the freed
3663          * space is not used anymore.
3664          */
3665         for_each_intel_crtc(dev, crtc) {
3666                 if (!crtc->active)
3667                         continue;
3668
3669                 pipe = crtc->pipe;
3670
3671                 if (reallocated[pipe])
3672                         continue;
3673
3674                 if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) <
3675                     skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {
3676                         skl_wm_flush_pipe(dev_priv, pipe, 2);
3677                         intel_wait_for_vblank(dev, pipe);
3678                         reallocated[pipe] = true;
3679                 }
3680         }
3681
3682         /*
3683          * Third pass: flush the pipes that got more space allocated.
3684          *
3685          * We don't need to actively wait for the update here, next vblank
3686          * will just get more DDB space with the correct WM values.
3687          */
3688         for_each_intel_crtc(dev, crtc) {
3689                 if (!crtc->active)
3690                         continue;
3691
3692                 pipe = crtc->pipe;
3693
3694                 /*
3695                  * At this point, only the pipes more space than before are
3696                  * left to re-allocate.
3697                  */
3698                 if (reallocated[pipe])
3699                         continue;
3700
3701                 skl_wm_flush_pipe(dev_priv, pipe, 3);
3702         }
3703 }
3704
3705 static int skl_update_pipe_wm(struct drm_crtc_state *cstate,
3706                               struct skl_ddb_allocation *ddb, /* out */
3707                               struct skl_pipe_wm *pipe_wm, /* out */
3708                               bool *changed /* out */)
3709 {
3710         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->crtc);
3711         struct intel_crtc_state *intel_cstate = to_intel_crtc_state(cstate);
3712         int ret;
3713
3714         ret = skl_build_pipe_wm(intel_cstate, ddb, pipe_wm);
3715         if (ret)
3716                 return ret;
3717
3718         if (!memcmp(&intel_crtc->wm.active.skl, pipe_wm, sizeof(*pipe_wm)))
3719                 *changed = false;
3720         else
3721                 *changed = true;
3722
3723         return 0;
3724 }
3725
3726 static int
3727 skl_compute_ddb(struct drm_atomic_state *state)
3728 {
3729         struct drm_device *dev = state->dev;
3730         struct drm_i915_private *dev_priv = to_i915(dev);
3731         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3732         struct intel_crtc *intel_crtc;
3733         struct skl_ddb_allocation *ddb = &intel_state->wm_results.ddb;
3734         unsigned realloc_pipes = dev_priv->active_crtcs;
3735         int ret;
3736
3737         /*
3738          * If this is our first atomic update following hardware readout,
3739          * we can't trust the DDB that the BIOS programmed for us.  Let's
3740          * pretend that all pipes switched active status so that we'll
3741          * ensure a full DDB recompute.
3742          */
3743         if (dev_priv->wm.distrust_bios_wm)
3744                 intel_state->active_pipe_changes = ~0;
3745
3746         /*
3747          * If the modeset changes which CRTC's are active, we need to
3748          * recompute the DDB allocation for *all* active pipes, even
3749          * those that weren't otherwise being modified in any way by this
3750          * atomic commit.  Due to the shrinking of the per-pipe allocations
3751          * when new active CRTC's are added, it's possible for a pipe that
3752          * we were already using and aren't changing at all here to suddenly
3753          * become invalid if its DDB needs exceeds its new allocation.
3754          *
3755          * Note that if we wind up doing a full DDB recompute, we can't let
3756          * any other display updates race with this transaction, so we need
3757          * to grab the lock on *all* CRTC's.
3758          */
3759         if (intel_state->active_pipe_changes) {
3760                 realloc_pipes = ~0;
3761                 intel_state->wm_results.dirty_pipes = ~0;
3762         }
3763
3764         for_each_intel_crtc_mask(dev, intel_crtc, realloc_pipes) {
3765                 struct intel_crtc_state *cstate;
3766
3767                 cstate = intel_atomic_get_crtc_state(state, intel_crtc);
3768                 if (IS_ERR(cstate))
3769                         return PTR_ERR(cstate);
3770
3771                 ret = skl_allocate_pipe_ddb(cstate, ddb);
3772                 if (ret)
3773                         return ret;
3774         }
3775
3776         return 0;
3777 }
3778
3779 static int
3780 skl_compute_wm(struct drm_atomic_state *state)
3781 {
3782         struct drm_crtc *crtc;
3783         struct drm_crtc_state *cstate;
3784         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3785         struct skl_wm_values *results = &intel_state->wm_results;
3786         struct skl_pipe_wm *pipe_wm;
3787         bool changed = false;
3788         int ret, i;
3789
3790         /*
3791          * If this transaction isn't actually touching any CRTC's, don't
3792          * bother with watermark calculation.  Note that if we pass this
3793          * test, we're guaranteed to hold at least one CRTC state mutex,
3794          * which means we can safely use values like dev_priv->active_crtcs
3795          * since any racing commits that want to update them would need to
3796          * hold _all_ CRTC state mutexes.
3797          */
3798         for_each_crtc_in_state(state, crtc, cstate, i)
3799                 changed = true;
3800         if (!changed)
3801                 return 0;
3802
3803         /* Clear all dirty flags */
3804         results->dirty_pipes = 0;
3805
3806         ret = skl_compute_ddb(state);
3807         if (ret)
3808                 return ret;
3809
3810         /*
3811          * Calculate WM's for all pipes that are part of this transaction.
3812          * Note that the DDB allocation above may have added more CRTC's that
3813          * weren't otherwise being modified (and set bits in dirty_pipes) if
3814          * pipe allocations had to change.
3815          *
3816          * FIXME:  Now that we're doing this in the atomic check phase, we
3817          * should allow skl_update_pipe_wm() to return failure in cases where
3818          * no suitable watermark values can be found.
3819          */
3820         for_each_crtc_in_state(state, crtc, cstate, i) {
3821                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3822                 struct intel_crtc_state *intel_cstate =
3823                         to_intel_crtc_state(cstate);
3824
3825                 pipe_wm = &intel_cstate->wm.skl.optimal;
3826                 ret = skl_update_pipe_wm(cstate, &results->ddb, pipe_wm,
3827                                          &changed);
3828                 if (ret)
3829                         return ret;
3830
3831                 if (changed)
3832                         results->dirty_pipes |= drm_crtc_mask(crtc);
3833
3834                 if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0)
3835                         /* This pipe's WM's did not change */
3836                         continue;
3837
3838                 intel_cstate->update_wm_pre = true;
3839                 skl_compute_wm_results(crtc->dev, pipe_wm, results, intel_crtc);
3840         }
3841
3842         return 0;
3843 }
3844
3845 static void skl_update_wm(struct drm_crtc *crtc)
3846 {
3847         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3848         struct drm_device *dev = crtc->dev;
3849         struct drm_i915_private *dev_priv = dev->dev_private;
3850         struct skl_wm_values *results = &dev_priv->wm.skl_results;
3851         struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3852         struct skl_pipe_wm *pipe_wm = &cstate->wm.skl.optimal;
3853
3854         if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0)
3855                 return;
3856
3857         intel_crtc->wm.active.skl = *pipe_wm;
3858
3859         mutex_lock(&dev_priv->wm.wm_mutex);
3860
3861         skl_write_wm_values(dev_priv, results);
3862         skl_flush_wm_values(dev_priv, results);
3863
3864         /* store the new configuration */
3865         dev_priv->wm.skl_hw = *results;
3866
3867         mutex_unlock(&dev_priv->wm.wm_mutex);
3868 }
3869
3870 static void ilk_compute_wm_config(struct drm_device *dev,
3871                                   struct intel_wm_config *config)
3872 {
3873         struct intel_crtc *crtc;
3874
3875         /* Compute the currently _active_ config */
3876         for_each_intel_crtc(dev, crtc) {
3877                 const struct intel_pipe_wm *wm = &crtc->wm.active.ilk;
3878
3879                 if (!wm->pipe_enabled)
3880                         continue;
3881
3882                 config->sprites_enabled |= wm->sprites_enabled;
3883                 config->sprites_scaled |= wm->sprites_scaled;
3884                 config->num_pipes_active++;
3885         }
3886 }
3887
3888 static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
3889 {
3890         struct drm_device *dev = dev_priv->dev;
3891         struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
3892         struct ilk_wm_maximums max;
3893         struct intel_wm_config config = {};
3894         struct ilk_wm_values results = {};
3895         enum intel_ddb_partitioning partitioning;
3896
3897         ilk_compute_wm_config(dev, &config);
3898
3899         ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
3900         ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
3901
3902         /* 5/6 split only in single pipe config on IVB+ */
3903         if (INTEL_INFO(dev)->gen >= 7 &&
3904             config.num_pipes_active == 1 && config.sprites_enabled) {
3905                 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
3906                 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
3907
3908                 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
3909         } else {
3910                 best_lp_wm = &lp_wm_1_2;
3911         }
3912
3913         partitioning = (best_lp_wm == &lp_wm_1_2) ?
3914                        INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
3915
3916         ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
3917
3918         ilk_write_wm_values(dev_priv, &results);
3919 }
3920
3921 static void ilk_initial_watermarks(struct intel_crtc_state *cstate)
3922 {
3923         struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
3924         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
3925
3926         mutex_lock(&dev_priv->wm.wm_mutex);
3927         intel_crtc->wm.active.ilk = cstate->wm.ilk.intermediate;
3928         ilk_program_watermarks(dev_priv);
3929         mutex_unlock(&dev_priv->wm.wm_mutex);
3930 }
3931
3932 static void ilk_optimize_watermarks(struct intel_crtc_state *cstate)
3933 {
3934         struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
3935         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
3936
3937         mutex_lock(&dev_priv->wm.wm_mutex);
3938         if (cstate->wm.need_postvbl_update) {
3939                 intel_crtc->wm.active.ilk = cstate->wm.ilk.optimal;
3940                 ilk_program_watermarks(dev_priv);
3941         }
3942         mutex_unlock(&dev_priv->wm.wm_mutex);
3943 }
3944
3945 static void skl_pipe_wm_active_state(uint32_t val,
3946                                      struct skl_pipe_wm *active,
3947                                      bool is_transwm,
3948                                      bool is_cursor,
3949                                      int i,
3950                                      int level)
3951 {
3952         bool is_enabled = (val & PLANE_WM_EN) != 0;
3953
3954         if (!is_transwm) {
3955                 if (!is_cursor) {
3956                         active->wm[level].plane_en[i] = is_enabled;
3957                         active->wm[level].plane_res_b[i] =
3958                                         val & PLANE_WM_BLOCKS_MASK;
3959                         active->wm[level].plane_res_l[i] =
3960                                         (val >> PLANE_WM_LINES_SHIFT) &
3961                                                 PLANE_WM_LINES_MASK;
3962                 } else {
3963                         active->wm[level].plane_en[PLANE_CURSOR] = is_enabled;
3964                         active->wm[level].plane_res_b[PLANE_CURSOR] =
3965                                         val & PLANE_WM_BLOCKS_MASK;
3966                         active->wm[level].plane_res_l[PLANE_CURSOR] =
3967                                         (val >> PLANE_WM_LINES_SHIFT) &
3968                                                 PLANE_WM_LINES_MASK;
3969                 }
3970         } else {
3971                 if (!is_cursor) {
3972                         active->trans_wm.plane_en[i] = is_enabled;
3973                         active->trans_wm.plane_res_b[i] =
3974                                         val & PLANE_WM_BLOCKS_MASK;
3975                         active->trans_wm.plane_res_l[i] =
3976                                         (val >> PLANE_WM_LINES_SHIFT) &
3977                                                 PLANE_WM_LINES_MASK;
3978                 } else {
3979                         active->trans_wm.plane_en[PLANE_CURSOR] = is_enabled;
3980                         active->trans_wm.plane_res_b[PLANE_CURSOR] =
3981                                         val & PLANE_WM_BLOCKS_MASK;
3982                         active->trans_wm.plane_res_l[PLANE_CURSOR] =
3983                                         (val >> PLANE_WM_LINES_SHIFT) &
3984                                                 PLANE_WM_LINES_MASK;
3985                 }
3986         }
3987 }
3988
3989 static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3990 {
3991         struct drm_device *dev = crtc->dev;
3992         struct drm_i915_private *dev_priv = dev->dev_private;
3993         struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
3994         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3995         struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3996         struct skl_pipe_wm *active = &cstate->wm.skl.optimal;
3997         enum pipe pipe = intel_crtc->pipe;
3998         int level, i, max_level;
3999         uint32_t temp;
4000
4001         max_level = ilk_wm_max_level(dev);
4002
4003         hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
4004
4005         for (level = 0; level <= max_level; level++) {
4006                 for (i = 0; i < intel_num_planes(intel_crtc); i++)
4007                         hw->plane[pipe][i][level] =
4008                                         I915_READ(PLANE_WM(pipe, i, level));
4009                 hw->plane[pipe][PLANE_CURSOR][level] = I915_READ(CUR_WM(pipe, level));
4010         }
4011
4012         for (i = 0; i < intel_num_planes(intel_crtc); i++)
4013                 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
4014         hw->plane_trans[pipe][PLANE_CURSOR] = I915_READ(CUR_WM_TRANS(pipe));
4015
4016         if (!intel_crtc->active)
4017                 return;
4018
4019         hw->dirty_pipes |= drm_crtc_mask(crtc);
4020
4021         active->linetime = hw->wm_linetime[pipe];
4022
4023         for (level = 0; level <= max_level; level++) {
4024                 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
4025                         temp = hw->plane[pipe][i][level];
4026                         skl_pipe_wm_active_state(temp, active, false,
4027                                                 false, i, level);
4028                 }
4029                 temp = hw->plane[pipe][PLANE_CURSOR][level];
4030                 skl_pipe_wm_active_state(temp, active, false, true, i, level);
4031         }
4032
4033         for (i = 0; i < intel_num_planes(intel_crtc); i++) {
4034                 temp = hw->plane_trans[pipe][i];
4035                 skl_pipe_wm_active_state(temp, active, true, false, i, 0);
4036         }
4037
4038         temp = hw->plane_trans[pipe][PLANE_CURSOR];
4039         skl_pipe_wm_active_state(temp, active, true, true, i, 0);
4040
4041         intel_crtc->wm.active.skl = *active;
4042 }
4043
4044 void skl_wm_get_hw_state(struct drm_device *dev)
4045 {
4046         struct drm_i915_private *dev_priv = dev->dev_private;
4047         struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
4048         struct drm_crtc *crtc;
4049
4050         skl_ddb_get_hw_state(dev_priv, ddb);
4051         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
4052                 skl_pipe_wm_get_hw_state(crtc);
4053
4054         if (dev_priv->active_crtcs) {
4055                 /* Fully recompute DDB on first atomic commit */
4056                 dev_priv->wm.distrust_bios_wm = true;
4057         } else {
4058                 /* Easy/common case; just sanitize DDB now if everything off */
4059                 memset(ddb, 0, sizeof(*ddb));
4060         }
4061 }
4062
4063 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
4064 {
4065         struct drm_device *dev = crtc->dev;
4066         struct drm_i915_private *dev_priv = dev->dev_private;
4067         struct ilk_wm_values *hw = &dev_priv->wm.hw;
4068         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4069         struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
4070         struct intel_pipe_wm *active = &cstate->wm.ilk.optimal;
4071         enum pipe pipe = intel_crtc->pipe;
4072         static const i915_reg_t wm0_pipe_reg[] = {
4073                 [PIPE_A] = WM0_PIPEA_ILK,
4074                 [PIPE_B] = WM0_PIPEB_ILK,
4075                 [PIPE_C] = WM0_PIPEC_IVB,
4076         };
4077
4078         hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
4079         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4080                 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
4081
4082         memset(active, 0, sizeof(*active));
4083
4084         active->pipe_enabled = intel_crtc->active;
4085
4086         if (active->pipe_enabled) {
4087                 u32 tmp = hw->wm_pipe[pipe];
4088
4089                 /*
4090                  * For active pipes LP0 watermark is marked as
4091                  * enabled, and LP1+ watermaks as disabled since
4092                  * we can't really reverse compute them in case
4093                  * multiple pipes are active.
4094                  */
4095                 active->wm[0].enable = true;
4096                 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
4097                 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
4098                 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
4099                 active->linetime = hw->wm_linetime[pipe];
4100         } else {
4101                 int level, max_level = ilk_wm_max_level(dev);
4102
4103                 /*
4104                  * For inactive pipes, all watermark levels
4105                  * should be marked as enabled but zeroed,
4106                  * which is what we'd compute them to.
4107                  */
4108                 for (level = 0; level <= max_level; level++)
4109                         active->wm[level].enable = true;
4110         }
4111
4112         intel_crtc->wm.active.ilk = *active;
4113 }
4114
4115 #define _FW_WM(value, plane) \
4116         (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
4117 #define _FW_WM_VLV(value, plane) \
4118         (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
4119
4120 static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
4121                                struct vlv_wm_values *wm)
4122 {
4123         enum pipe pipe;
4124         uint32_t tmp;
4125
4126         for_each_pipe(dev_priv, pipe) {
4127                 tmp = I915_READ(VLV_DDL(pipe));
4128
4129                 wm->ddl[pipe].primary =
4130                         (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4131                 wm->ddl[pipe].cursor =
4132                         (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4133                 wm->ddl[pipe].sprite[0] =
4134                         (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4135                 wm->ddl[pipe].sprite[1] =
4136                         (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4137         }
4138
4139         tmp = I915_READ(DSPFW1);
4140         wm->sr.plane = _FW_WM(tmp, SR);
4141         wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB);
4142         wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB);
4143         wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA);
4144
4145         tmp = I915_READ(DSPFW2);
4146         wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB);
4147         wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA);
4148         wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA);
4149
4150         tmp = I915_READ(DSPFW3);
4151         wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
4152
4153         if (IS_CHERRYVIEW(dev_priv)) {
4154                 tmp = I915_READ(DSPFW7_CHV);
4155                 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4156                 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4157
4158                 tmp = I915_READ(DSPFW8_CHV);
4159                 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF);
4160                 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE);
4161
4162                 tmp = I915_READ(DSPFW9_CHV);
4163                 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC);
4164                 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC);
4165
4166                 tmp = I915_READ(DSPHOWM);
4167                 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4168                 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
4169                 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
4170                 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8;
4171                 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4172                 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4173                 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4174                 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4175                 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4176                 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4177         } else {
4178                 tmp = I915_READ(DSPFW7);
4179                 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4180                 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4181
4182                 tmp = I915_READ(DSPHOWM);
4183                 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4184                 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4185                 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4186                 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4187                 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4188                 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4189                 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4190         }
4191 }
4192
4193 #undef _FW_WM
4194 #undef _FW_WM_VLV
4195
4196 void vlv_wm_get_hw_state(struct drm_device *dev)
4197 {
4198         struct drm_i915_private *dev_priv = to_i915(dev);
4199         struct vlv_wm_values *wm = &dev_priv->wm.vlv;
4200         struct intel_plane *plane;
4201         enum pipe pipe;
4202         u32 val;
4203
4204         vlv_read_wm_values(dev_priv, wm);
4205
4206         for_each_intel_plane(dev, plane) {
4207                 switch (plane->base.type) {
4208                         int sprite;
4209                 case DRM_PLANE_TYPE_CURSOR:
4210                         plane->wm.fifo_size = 63;
4211                         break;
4212                 case DRM_PLANE_TYPE_PRIMARY:
4213                         plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0);
4214                         break;
4215                 case DRM_PLANE_TYPE_OVERLAY:
4216                         sprite = plane->plane;
4217                         plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1);
4218                         break;
4219                 }
4220         }
4221
4222         wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4223         wm->level = VLV_WM_LEVEL_PM2;
4224
4225         if (IS_CHERRYVIEW(dev_priv)) {
4226                 mutex_lock(&dev_priv->rps.hw_lock);
4227
4228                 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4229                 if (val & DSP_MAXFIFO_PM5_ENABLE)
4230                         wm->level = VLV_WM_LEVEL_PM5;
4231
4232                 /*
4233                  * If DDR DVFS is disabled in the BIOS, Punit
4234                  * will never ack the request. So if that happens
4235                  * assume we don't have to enable/disable DDR DVFS
4236                  * dynamically. To test that just set the REQ_ACK
4237                  * bit to poke the Punit, but don't change the
4238                  * HIGH/LOW bits so that we don't actually change
4239                  * the current state.
4240                  */
4241                 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4242                 val |= FORCE_DDR_FREQ_REQ_ACK;
4243                 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
4244
4245                 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
4246                               FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
4247                         DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
4248                                       "assuming DDR DVFS is disabled\n");
4249                         dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
4250                 } else {
4251                         val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4252                         if ((val & FORCE_DDR_HIGH_FREQ) == 0)
4253                                 wm->level = VLV_WM_LEVEL_DDR_DVFS;
4254                 }
4255
4256                 mutex_unlock(&dev_priv->rps.hw_lock);
4257         }
4258
4259         for_each_pipe(dev_priv, pipe)
4260                 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4261                               pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor,
4262                               wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]);
4263
4264         DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4265                       wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
4266 }
4267
4268 void ilk_wm_get_hw_state(struct drm_device *dev)
4269 {
4270         struct drm_i915_private *dev_priv = dev->dev_private;
4271         struct ilk_wm_values *hw = &dev_priv->wm.hw;
4272         struct drm_crtc *crtc;
4273
4274         for_each_crtc(dev, crtc)
4275                 ilk_pipe_wm_get_hw_state(crtc);
4276
4277         hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
4278         hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
4279         hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
4280
4281         hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
4282         if (INTEL_INFO(dev)->gen >= 7) {
4283                 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
4284                 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
4285         }
4286
4287         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4288                 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
4289                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4290         else if (IS_IVYBRIDGE(dev))
4291                 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
4292                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4293
4294         hw->enable_fbc_wm =
4295                 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
4296 }
4297
4298 /**
4299  * intel_update_watermarks - update FIFO watermark values based on current modes
4300  *
4301  * Calculate watermark values for the various WM regs based on current mode
4302  * and plane configuration.
4303  *
4304  * There are several cases to deal with here:
4305  *   - normal (i.e. non-self-refresh)
4306  *   - self-refresh (SR) mode
4307  *   - lines are large relative to FIFO size (buffer can hold up to 2)
4308  *   - lines are small relative to FIFO size (buffer can hold more than 2
4309  *     lines), so need to account for TLB latency
4310  *
4311  *   The normal calculation is:
4312  *     watermark = dotclock * bytes per pixel * latency
4313  *   where latency is platform & configuration dependent (we assume pessimal
4314  *   values here).
4315  *
4316  *   The SR calculation is:
4317  *     watermark = (trunc(latency/line time)+1) * surface width *
4318  *       bytes per pixel
4319  *   where
4320  *     line time = htotal / dotclock
4321  *     surface width = hdisplay for normal plane and 64 for cursor
4322  *   and latency is assumed to be high, as above.
4323  *
4324  * The final value programmed to the register should always be rounded up,
4325  * and include an extra 2 entries to account for clock crossings.
4326  *
4327  * We don't use the sprite, so we can ignore that.  And on Crestline we have
4328  * to set the non-SR watermarks to 8.
4329  */
4330 void intel_update_watermarks(struct drm_crtc *crtc)
4331 {
4332         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
4333
4334         if (dev_priv->display.update_wm)
4335                 dev_priv->display.update_wm(crtc);
4336 }
4337
4338 /*
4339  * Lock protecting IPS related data structures
4340  */
4341 DEFINE_SPINLOCK(mchdev_lock);
4342
4343 /* Global for IPS driver to get at the current i915 device. Protected by
4344  * mchdev_lock. */
4345 static struct drm_i915_private *i915_mch_dev;
4346
4347 bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val)
4348 {
4349         u16 rgvswctl;
4350
4351         assert_spin_locked(&mchdev_lock);
4352
4353         rgvswctl = I915_READ16(MEMSWCTL);
4354         if (rgvswctl & MEMCTL_CMD_STS) {
4355                 DRM_DEBUG("gpu busy, RCS change rejected\n");
4356                 return false; /* still busy with another command */
4357         }
4358
4359         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4360                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4361         I915_WRITE16(MEMSWCTL, rgvswctl);
4362         POSTING_READ16(MEMSWCTL);
4363
4364         rgvswctl |= MEMCTL_CMD_STS;
4365         I915_WRITE16(MEMSWCTL, rgvswctl);
4366
4367         return true;
4368 }
4369
4370 static void ironlake_enable_drps(struct drm_i915_private *dev_priv)
4371 {
4372         u32 rgvmodectl;
4373         u8 fmax, fmin, fstart, vstart;
4374
4375         spin_lock_irq(&mchdev_lock);
4376
4377         rgvmodectl = I915_READ(MEMMODECTL);
4378
4379         /* Enable temp reporting */
4380         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4381         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4382
4383         /* 100ms RC evaluation intervals */
4384         I915_WRITE(RCUPEI, 100000);
4385         I915_WRITE(RCDNEI, 100000);
4386
4387         /* Set max/min thresholds to 90ms and 80ms respectively */
4388         I915_WRITE(RCBMAXAVG, 90000);
4389         I915_WRITE(RCBMINAVG, 80000);
4390
4391         I915_WRITE(MEMIHYST, 1);
4392
4393         /* Set up min, max, and cur for interrupt handling */
4394         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4395         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4396         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4397                 MEMMODE_FSTART_SHIFT;
4398
4399         vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
4400                 PXVFREQ_PX_SHIFT;
4401
4402         dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4403         dev_priv->ips.fstart = fstart;
4404
4405         dev_priv->ips.max_delay = fstart;
4406         dev_priv->ips.min_delay = fmin;
4407         dev_priv->ips.cur_delay = fstart;
4408
4409         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4410                          fmax, fmin, fstart);
4411
4412         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4413
4414         /*
4415          * Interrupts will be enabled in ironlake_irq_postinstall
4416          */
4417
4418         I915_WRITE(VIDSTART, vstart);
4419         POSTING_READ(VIDSTART);
4420
4421         rgvmodectl |= MEMMODE_SWMODE_EN;
4422         I915_WRITE(MEMMODECTL, rgvmodectl);
4423
4424         if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
4425                 DRM_ERROR("stuck trying to change perf mode\n");
4426         mdelay(1);
4427
4428         ironlake_set_drps(dev_priv, fstart);
4429
4430         dev_priv->ips.last_count1 = I915_READ(DMIEC) +
4431                 I915_READ(DDREC) + I915_READ(CSIEC);
4432         dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
4433         dev_priv->ips.last_count2 = I915_READ(GFXEC);
4434         dev_priv->ips.last_time2 = ktime_get_raw_ns();
4435
4436         spin_unlock_irq(&mchdev_lock);
4437 }
4438
4439 static void ironlake_disable_drps(struct drm_i915_private *dev_priv)
4440 {
4441         u16 rgvswctl;
4442
4443         spin_lock_irq(&mchdev_lock);
4444
4445         rgvswctl = I915_READ16(MEMSWCTL);
4446
4447         /* Ack interrupts, disable EFC interrupt */
4448         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4449         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4450         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4451         I915_WRITE(DEIIR, DE_PCU_EVENT);
4452         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4453
4454         /* Go back to the starting frequency */
4455         ironlake_set_drps(dev_priv, dev_priv->ips.fstart);
4456         mdelay(1);
4457         rgvswctl |= MEMCTL_CMD_STS;
4458         I915_WRITE(MEMSWCTL, rgvswctl);
4459         mdelay(1);
4460
4461         spin_unlock_irq(&mchdev_lock);
4462 }
4463
4464 /* There's a funny hw issue where the hw returns all 0 when reading from
4465  * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4466  * ourselves, instead of doing a rmw cycle (which might result in us clearing
4467  * all limits and the gpu stuck at whatever frequency it is at atm).
4468  */
4469 static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
4470 {
4471         u32 limits;
4472
4473         /* Only set the down limit when we've reached the lowest level to avoid
4474          * getting more interrupts, otherwise leave this clear. This prevents a
4475          * race in the hw when coming out of rc6: There's a tiny window where
4476          * the hw runs at the minimal clock before selecting the desired
4477          * frequency, if the down threshold expires in that window we will not
4478          * receive a down interrupt. */
4479         if (IS_GEN9(dev_priv)) {
4480                 limits = (dev_priv->rps.max_freq_softlimit) << 23;
4481                 if (val <= dev_priv->rps.min_freq_softlimit)
4482                         limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4483         } else {
4484                 limits = dev_priv->rps.max_freq_softlimit << 24;
4485                 if (val <= dev_priv->rps.min_freq_softlimit)
4486                         limits |= dev_priv->rps.min_freq_softlimit << 16;
4487         }
4488
4489         return limits;
4490 }
4491
4492 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4493 {
4494         int new_power;
4495         u32 threshold_up = 0, threshold_down = 0; /* in % */
4496         u32 ei_up = 0, ei_down = 0;
4497
4498         new_power = dev_priv->rps.power;
4499         switch (dev_priv->rps.power) {
4500         case LOW_POWER:
4501                 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
4502                         new_power = BETWEEN;
4503                 break;
4504
4505         case BETWEEN:
4506                 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
4507                         new_power = LOW_POWER;
4508                 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
4509                         new_power = HIGH_POWER;
4510                 break;
4511
4512         case HIGH_POWER:
4513                 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
4514                         new_power = BETWEEN;
4515                 break;
4516         }
4517         /* Max/min bins are special */
4518         if (val <= dev_priv->rps.min_freq_softlimit)
4519                 new_power = LOW_POWER;
4520         if (val >= dev_priv->rps.max_freq_softlimit)
4521                 new_power = HIGH_POWER;
4522         if (new_power == dev_priv->rps.power)
4523                 return;
4524
4525         /* Note the units here are not exactly 1us, but 1280ns. */
4526         switch (new_power) {
4527         case LOW_POWER:
4528                 /* Upclock if more than 95% busy over 16ms */
4529                 ei_up = 16000;
4530                 threshold_up = 95;
4531
4532                 /* Downclock if less than 85% busy over 32ms */
4533                 ei_down = 32000;
4534                 threshold_down = 85;
4535                 break;
4536
4537         case BETWEEN:
4538                 /* Upclock if more than 90% busy over 13ms */
4539                 ei_up = 13000;
4540                 threshold_up = 90;
4541
4542                 /* Downclock if less than 75% busy over 32ms */
4543                 ei_down = 32000;
4544                 threshold_down = 75;
4545                 break;
4546
4547         case HIGH_POWER:
4548                 /* Upclock if more than 85% busy over 10ms */
4549                 ei_up = 10000;
4550                 threshold_up = 85;
4551
4552                 /* Downclock if less than 60% busy over 32ms */
4553                 ei_down = 32000;
4554                 threshold_down = 60;
4555                 break;
4556         }
4557
4558         I915_WRITE(GEN6_RP_UP_EI,
4559                 GT_INTERVAL_FROM_US(dev_priv, ei_up));
4560         I915_WRITE(GEN6_RP_UP_THRESHOLD,
4561                 GT_INTERVAL_FROM_US(dev_priv, (ei_up * threshold_up / 100)));
4562
4563         I915_WRITE(GEN6_RP_DOWN_EI,
4564                 GT_INTERVAL_FROM_US(dev_priv, ei_down));
4565         I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
4566                 GT_INTERVAL_FROM_US(dev_priv, (ei_down * threshold_down / 100)));
4567
4568          I915_WRITE(GEN6_RP_CONTROL,
4569                     GEN6_RP_MEDIA_TURBO |
4570                     GEN6_RP_MEDIA_HW_NORMAL_MODE |
4571                     GEN6_RP_MEDIA_IS_GFX |
4572                     GEN6_RP_ENABLE |
4573                     GEN6_RP_UP_BUSY_AVG |
4574                     GEN6_RP_DOWN_IDLE_AVG);
4575
4576         dev_priv->rps.power = new_power;
4577         dev_priv->rps.up_threshold = threshold_up;
4578         dev_priv->rps.down_threshold = threshold_down;
4579         dev_priv->rps.last_adj = 0;
4580 }
4581
4582 static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4583 {
4584         u32 mask = 0;
4585
4586         if (val > dev_priv->rps.min_freq_softlimit)
4587                 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
4588         if (val < dev_priv->rps.max_freq_softlimit)
4589                 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
4590
4591         mask &= dev_priv->pm_rps_events;
4592
4593         return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
4594 }
4595
4596 /* gen6_set_rps is called to update the frequency request, but should also be
4597  * called when the range (min_delay and max_delay) is modified so that we can
4598  * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
4599 static void gen6_set_rps(struct drm_i915_private *dev_priv, u8 val)
4600 {
4601         /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
4602         if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
4603                 return;
4604
4605         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4606         WARN_ON(val > dev_priv->rps.max_freq);
4607         WARN_ON(val < dev_priv->rps.min_freq);
4608
4609         /* min/max delay may still have been modified so be sure to
4610          * write the limits value.
4611          */
4612         if (val != dev_priv->rps.cur_freq) {
4613                 gen6_set_rps_thresholds(dev_priv, val);
4614
4615                 if (IS_GEN9(dev_priv))
4616                         I915_WRITE(GEN6_RPNSWREQ,
4617                                    GEN9_FREQUENCY(val));
4618                 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
4619                         I915_WRITE(GEN6_RPNSWREQ,
4620                                    HSW_FREQUENCY(val));
4621                 else
4622                         I915_WRITE(GEN6_RPNSWREQ,
4623                                    GEN6_FREQUENCY(val) |
4624                                    GEN6_OFFSET(0) |
4625                                    GEN6_AGGRESSIVE_TURBO);
4626         }
4627
4628         /* Make sure we continue to get interrupts
4629          * until we hit the minimum or maximum frequencies.
4630          */
4631         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
4632         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4633
4634         POSTING_READ(GEN6_RPNSWREQ);
4635
4636         dev_priv->rps.cur_freq = val;
4637         trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4638 }
4639
4640 static void valleyview_set_rps(struct drm_i915_private *dev_priv, u8 val)
4641 {
4642         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4643         WARN_ON(val > dev_priv->rps.max_freq);
4644         WARN_ON(val < dev_priv->rps.min_freq);
4645
4646         if (WARN_ONCE(IS_CHERRYVIEW(dev_priv) && (val & 1),
4647                       "Odd GPU freq value\n"))
4648                 val &= ~1;
4649
4650         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4651
4652         if (val != dev_priv->rps.cur_freq) {
4653                 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
4654                 if (!IS_CHERRYVIEW(dev_priv))
4655                         gen6_set_rps_thresholds(dev_priv, val);
4656         }
4657
4658         dev_priv->rps.cur_freq = val;
4659         trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4660 }
4661
4662 /* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
4663  *
4664  * * If Gfx is Idle, then
4665  * 1. Forcewake Media well.
4666  * 2. Request idle freq.
4667  * 3. Release Forcewake of Media well.
4668 */
4669 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
4670 {
4671         u32 val = dev_priv->rps.idle_freq;
4672
4673         if (dev_priv->rps.cur_freq <= val)
4674                 return;
4675
4676         /* Wake up the media well, as that takes a lot less
4677          * power than the Render well. */
4678         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
4679         valleyview_set_rps(dev_priv, val);
4680         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
4681 }
4682
4683 void gen6_rps_busy(struct drm_i915_private *dev_priv)
4684 {
4685         mutex_lock(&dev_priv->rps.hw_lock);
4686         if (dev_priv->rps.enabled) {
4687                 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
4688                         gen6_rps_reset_ei(dev_priv);
4689                 I915_WRITE(GEN6_PMINTRMSK,
4690                            gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
4691         }
4692         mutex_unlock(&dev_priv->rps.hw_lock);
4693 }
4694
4695 void gen6_rps_idle(struct drm_i915_private *dev_priv)
4696 {
4697         mutex_lock(&dev_priv->rps.hw_lock);
4698         if (dev_priv->rps.enabled) {
4699                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4700                         vlv_set_rps_idle(dev_priv);
4701                 else
4702                         gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
4703                 dev_priv->rps.last_adj = 0;
4704                 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
4705         }
4706         mutex_unlock(&dev_priv->rps.hw_lock);
4707
4708         spin_lock(&dev_priv->rps.client_lock);
4709         while (!list_empty(&dev_priv->rps.clients))
4710                 list_del_init(dev_priv->rps.clients.next);
4711         spin_unlock(&dev_priv->rps.client_lock);
4712 }
4713
4714 void gen6_rps_boost(struct drm_i915_private *dev_priv,
4715                     struct intel_rps_client *rps,
4716                     unsigned long submitted)
4717 {
4718         /* This is intentionally racy! We peek at the state here, then
4719          * validate inside the RPS worker.
4720          */
4721         if (!(dev_priv->mm.busy &&
4722               dev_priv->rps.enabled &&
4723               dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit))
4724                 return;
4725
4726         /* Force a RPS boost (and don't count it against the client) if
4727          * the GPU is severely congested.
4728          */
4729         if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
4730                 rps = NULL;
4731
4732         spin_lock(&dev_priv->rps.client_lock);
4733         if (rps == NULL || list_empty(&rps->link)) {
4734                 spin_lock_irq(&dev_priv->irq_lock);
4735                 if (dev_priv->rps.interrupts_enabled) {
4736                         dev_priv->rps.client_boost = true;
4737                         queue_work(dev_priv->wq, &dev_priv->rps.work);
4738                 }
4739                 spin_unlock_irq(&dev_priv->irq_lock);
4740
4741                 if (rps != NULL) {
4742                         list_add(&rps->link, &dev_priv->rps.clients);
4743                         rps->boosts++;
4744                 } else
4745                         dev_priv->rps.boosts++;
4746         }
4747         spin_unlock(&dev_priv->rps.client_lock);
4748 }
4749
4750 void intel_set_rps(struct drm_i915_private *dev_priv, u8 val)
4751 {
4752         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4753                 valleyview_set_rps(dev_priv, val);
4754         else
4755                 gen6_set_rps(dev_priv, val);
4756 }
4757
4758 static void gen9_disable_rc6(struct drm_i915_private *dev_priv)
4759 {
4760         I915_WRITE(GEN6_RC_CONTROL, 0);
4761         I915_WRITE(GEN9_PG_ENABLE, 0);
4762 }
4763
4764 static void gen9_disable_rps(struct drm_i915_private *dev_priv)
4765 {
4766         I915_WRITE(GEN6_RP_CONTROL, 0);
4767 }
4768
4769 static void gen6_disable_rps(struct drm_i915_private *dev_priv)
4770 {
4771         I915_WRITE(GEN6_RC_CONTROL, 0);
4772         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
4773         I915_WRITE(GEN6_RP_CONTROL, 0);
4774 }
4775
4776 static void cherryview_disable_rps(struct drm_i915_private *dev_priv)
4777 {
4778         I915_WRITE(GEN6_RC_CONTROL, 0);
4779 }
4780
4781 static void valleyview_disable_rps(struct drm_i915_private *dev_priv)
4782 {
4783         /* we're doing forcewake before Disabling RC6,
4784          * This what the BIOS expects when going into suspend */
4785         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4786
4787         I915_WRITE(GEN6_RC_CONTROL, 0);
4788
4789         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4790 }
4791
4792 static void intel_print_rc6_info(struct drm_i915_private *dev_priv, u32 mode)
4793 {
4794         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
4795                 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
4796                         mode = GEN6_RC_CTL_RC6_ENABLE;
4797                 else
4798                         mode = 0;
4799         }
4800         if (HAS_RC6p(dev_priv))
4801                 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n",
4802                               onoff(mode & GEN6_RC_CTL_RC6_ENABLE),
4803                               onoff(mode & GEN6_RC_CTL_RC6p_ENABLE),
4804                               onoff(mode & GEN6_RC_CTL_RC6pp_ENABLE));
4805
4806         else
4807                 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n",
4808                               onoff(mode & GEN6_RC_CTL_RC6_ENABLE));
4809 }
4810
4811 static bool bxt_check_bios_rc6_setup(struct drm_i915_private *dev_priv)
4812 {
4813         struct i915_ggtt *ggtt = &dev_priv->ggtt;
4814         bool enable_rc6 = true;
4815         unsigned long rc6_ctx_base;
4816
4817         if (!(I915_READ(RC6_LOCATION) & RC6_CTX_IN_DRAM)) {
4818                 DRM_DEBUG_KMS("RC6 Base location not set properly.\n");
4819                 enable_rc6 = false;
4820         }
4821
4822         /*
4823          * The exact context size is not known for BXT, so assume a page size
4824          * for this check.
4825          */
4826         rc6_ctx_base = I915_READ(RC6_CTX_BASE) & RC6_CTX_BASE_MASK;
4827         if (!((rc6_ctx_base >= ggtt->stolen_reserved_base) &&
4828               (rc6_ctx_base + PAGE_SIZE <= ggtt->stolen_reserved_base +
4829                                         ggtt->stolen_reserved_size))) {
4830                 DRM_DEBUG_KMS("RC6 Base address not as expected.\n");
4831                 enable_rc6 = false;
4832         }
4833
4834         if (!(((I915_READ(PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1) &&
4835               ((I915_READ(PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1) &&
4836               ((I915_READ(PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1) &&
4837               ((I915_READ(PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1))) {
4838                 DRM_DEBUG_KMS("Engine Idle wait time not set properly.\n");
4839                 enable_rc6 = false;
4840         }
4841
4842         if (!(I915_READ(GEN6_RC_CONTROL) & (GEN6_RC_CTL_RC6_ENABLE |
4843                                             GEN6_RC_CTL_HW_ENABLE)) &&
4844             ((I915_READ(GEN6_RC_CONTROL) & GEN6_RC_CTL_HW_ENABLE) ||
4845              !(I915_READ(GEN6_RC_STATE) & RC6_STATE))) {
4846                 DRM_DEBUG_KMS("HW/SW RC6 is not enabled by BIOS.\n");
4847                 enable_rc6 = false;
4848         }
4849
4850         return enable_rc6;
4851 }
4852
4853 int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6)
4854 {
4855         /* No RC6 before Ironlake and code is gone for ilk. */
4856         if (INTEL_INFO(dev_priv)->gen < 6)
4857                 return 0;
4858
4859         if (!enable_rc6)
4860                 return 0;
4861
4862         if (IS_BROXTON(dev_priv) && !bxt_check_bios_rc6_setup(dev_priv)) {
4863                 DRM_INFO("RC6 disabled by BIOS\n");
4864                 return 0;
4865         }
4866
4867         /* Respect the kernel parameter if it is set */
4868         if (enable_rc6 >= 0) {
4869                 int mask;
4870
4871                 if (HAS_RC6p(dev_priv))
4872                         mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
4873                                INTEL_RC6pp_ENABLE;
4874                 else
4875                         mask = INTEL_RC6_ENABLE;
4876
4877                 if ((enable_rc6 & mask) != enable_rc6)
4878                         DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
4879                                       enable_rc6 & mask, enable_rc6, mask);
4880
4881                 return enable_rc6 & mask;
4882         }
4883
4884         if (IS_IVYBRIDGE(dev_priv))
4885                 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
4886
4887         return INTEL_RC6_ENABLE;
4888 }
4889
4890 static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
4891 {
4892         uint32_t rp_state_cap;
4893         u32 ddcc_status = 0;
4894         int ret;
4895
4896         /* All of these values are in units of 50MHz */
4897         dev_priv->rps.cur_freq          = 0;
4898         /* static values from HW: RP0 > RP1 > RPn (min_freq) */
4899         if (IS_BROXTON(dev_priv)) {
4900                 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
4901                 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
4902                 dev_priv->rps.rp1_freq = (rp_state_cap >>  8) & 0xff;
4903                 dev_priv->rps.min_freq = (rp_state_cap >>  0) & 0xff;
4904         } else {
4905                 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
4906                 dev_priv->rps.rp0_freq = (rp_state_cap >>  0) & 0xff;
4907                 dev_priv->rps.rp1_freq = (rp_state_cap >>  8) & 0xff;
4908                 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
4909         }
4910
4911         /* hw_max = RP0 until we check for overclocking */
4912         dev_priv->rps.max_freq          = dev_priv->rps.rp0_freq;
4913
4914         dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
4915         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
4916             IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
4917                 ret = sandybridge_pcode_read(dev_priv,
4918                                         HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
4919                                         &ddcc_status);
4920                 if (0 == ret)
4921                         dev_priv->rps.efficient_freq =
4922                                 clamp_t(u8,
4923                                         ((ddcc_status >> 8) & 0xff),
4924                                         dev_priv->rps.min_freq,
4925                                         dev_priv->rps.max_freq);
4926         }
4927
4928         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
4929                 /* Store the frequency values in 16.66 MHZ units, which is
4930                    the natural hardware unit for SKL */
4931                 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
4932                 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
4933                 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
4934                 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
4935                 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
4936         }
4937
4938         dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
4939
4940         /* Preserve min/max settings in case of re-init */
4941         if (dev_priv->rps.max_freq_softlimit == 0)
4942                 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4943
4944         if (dev_priv->rps.min_freq_softlimit == 0) {
4945                 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
4946                         dev_priv->rps.min_freq_softlimit =
4947                                 max_t(int, dev_priv->rps.efficient_freq,
4948                                       intel_freq_opcode(dev_priv, 450));
4949                 else
4950                         dev_priv->rps.min_freq_softlimit =
4951                                 dev_priv->rps.min_freq;
4952         }
4953 }
4954
4955 /* See the Gen9_GT_PM_Programming_Guide doc for the below */
4956 static void gen9_enable_rps(struct drm_i915_private *dev_priv)
4957 {
4958         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4959
4960         gen6_init_rps_frequencies(dev_priv);
4961
4962         /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
4963         if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
4964                 /*
4965                  * BIOS could leave the Hw Turbo enabled, so need to explicitly
4966                  * clear out the Control register just to avoid inconsitency
4967                  * with debugfs interface, which will show  Turbo as enabled
4968                  * only and that is not expected by the User after adding the
4969                  * WaGsvDisableTurbo. Apart from this there is no problem even
4970                  * if the Turbo is left enabled in the Control register, as the
4971                  * Up/Down interrupts would remain masked.
4972                  */
4973                 gen9_disable_rps(dev_priv);
4974                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4975                 return;
4976         }
4977
4978         /* Program defaults and thresholds for RPS*/
4979         I915_WRITE(GEN6_RC_VIDEO_FREQ,
4980                 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
4981
4982         /* 1 second timeout*/
4983         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
4984                 GT_INTERVAL_FROM_US(dev_priv, 1000000));
4985
4986         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
4987
4988         /* Leaning on the below call to gen6_set_rps to program/setup the
4989          * Up/Down EI & threshold registers, as well as the RP_CONTROL,
4990          * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
4991         dev_priv->rps.power = HIGH_POWER; /* force a reset */
4992         gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
4993
4994         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4995 }
4996
4997 static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
4998 {
4999         struct intel_engine_cs *engine;
5000         uint32_t rc6_mask = 0;
5001
5002         /* 1a: Software RC state - RC0 */
5003         I915_WRITE(GEN6_RC_STATE, 0);
5004
5005         /* 1b: Get forcewake during program sequence. Although the driver
5006          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5007         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5008
5009         /* 2a: Disable RC states. */
5010         I915_WRITE(GEN6_RC_CONTROL, 0);
5011
5012         /* 2b: Program RC6 thresholds.*/
5013
5014         /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
5015         if (IS_SKYLAKE(dev_priv))
5016                 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
5017         else
5018                 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
5019         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5020         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5021         for_each_engine(engine, dev_priv)
5022                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5023
5024         if (HAS_GUC(dev_priv))
5025                 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
5026
5027         I915_WRITE(GEN6_RC_SLEEP, 0);
5028
5029         /* 2c: Program Coarse Power Gating Policies. */
5030         I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
5031         I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
5032
5033         /* 3a: Enable RC6 */
5034         if (intel_enable_rc6() & INTEL_RC6_ENABLE)
5035                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
5036         DRM_INFO("RC6 %s\n", onoff(rc6_mask & GEN6_RC_CTL_RC6_ENABLE));
5037         /* WaRsUseTimeoutMode */
5038         if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_D0) ||
5039             IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
5040                 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
5041                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5042                            GEN7_RC_CTL_TO_MODE |
5043                            rc6_mask);
5044         } else {
5045                 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
5046                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5047                            GEN6_RC_CTL_EI_MODE(1) |
5048                            rc6_mask);
5049         }
5050
5051         /*
5052          * 3b: Enable Coarse Power Gating only when RC6 is enabled.
5053          * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
5054          */
5055         if (NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
5056                 I915_WRITE(GEN9_PG_ENABLE, 0);
5057         else
5058                 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
5059                                 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
5060
5061         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5062 }
5063
5064 static void gen8_enable_rps(struct drm_i915_private *dev_priv)
5065 {
5066         struct intel_engine_cs *engine;
5067         uint32_t rc6_mask = 0;
5068
5069         /* 1a: Software RC state - RC0 */
5070         I915_WRITE(GEN6_RC_STATE, 0);
5071
5072         /* 1c & 1d: Get forcewake during program sequence. Although the driver
5073          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5074         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5075
5076         /* 2a: Disable RC states. */
5077         I915_WRITE(GEN6_RC_CONTROL, 0);
5078
5079         /* Initialize rps frequencies */
5080         gen6_init_rps_frequencies(dev_priv);
5081
5082         /* 2b: Program RC6 thresholds.*/
5083         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5084         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5085         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5086         for_each_engine(engine, dev_priv)
5087                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5088         I915_WRITE(GEN6_RC_SLEEP, 0);
5089         if (IS_BROADWELL(dev_priv))
5090                 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
5091         else
5092                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
5093
5094         /* 3: Enable RC6 */
5095         if (intel_enable_rc6() & INTEL_RC6_ENABLE)
5096                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
5097         intel_print_rc6_info(dev_priv, rc6_mask);
5098         if (IS_BROADWELL(dev_priv))
5099                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5100                                 GEN7_RC_CTL_TO_MODE |
5101                                 rc6_mask);
5102         else
5103                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5104                                 GEN6_RC_CTL_EI_MODE(1) |
5105                                 rc6_mask);
5106
5107         /* 4 Program defaults and thresholds for RPS*/
5108         I915_WRITE(GEN6_RPNSWREQ,
5109                    HSW_FREQUENCY(dev_priv->rps.rp1_freq));
5110         I915_WRITE(GEN6_RC_VIDEO_FREQ,
5111                    HSW_FREQUENCY(dev_priv->rps.rp1_freq));
5112         /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
5113         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
5114
5115         /* Docs recommend 900MHz, and 300 MHz respectively */
5116         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
5117                    dev_priv->rps.max_freq_softlimit << 24 |
5118                    dev_priv->rps.min_freq_softlimit << 16);
5119
5120         I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
5121         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
5122         I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
5123         I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
5124
5125         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5126
5127         /* 5: Enable RPS */
5128         I915_WRITE(GEN6_RP_CONTROL,
5129                    GEN6_RP_MEDIA_TURBO |
5130                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
5131                    GEN6_RP_MEDIA_IS_GFX |
5132                    GEN6_RP_ENABLE |
5133                    GEN6_RP_UP_BUSY_AVG |
5134                    GEN6_RP_DOWN_IDLE_AVG);
5135
5136         /* 6: Ring frequency + overclocking (our driver does this later */
5137
5138         dev_priv->rps.power = HIGH_POWER; /* force a reset */
5139         gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
5140
5141         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5142 }
5143
5144 static void gen6_enable_rps(struct drm_i915_private *dev_priv)
5145 {
5146         struct intel_engine_cs *engine;
5147         u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
5148         u32 gtfifodbg;
5149         int rc6_mode;
5150         int ret;
5151
5152         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5153
5154         /* Here begins a magic sequence of register writes to enable
5155          * auto-downclocking.
5156          *
5157          * Perhaps there might be some value in exposing these to
5158          * userspace...
5159          */
5160         I915_WRITE(GEN6_RC_STATE, 0);
5161
5162         /* Clear the DBG now so we don't confuse earlier errors */
5163         gtfifodbg = I915_READ(GTFIFODBG);
5164         if (gtfifodbg) {
5165                 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
5166                 I915_WRITE(GTFIFODBG, gtfifodbg);
5167         }
5168
5169         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5170
5171         /* Initialize rps frequencies */
5172         gen6_init_rps_frequencies(dev_priv);
5173
5174         /* disable the counters and set deterministic thresholds */
5175         I915_WRITE(GEN6_RC_CONTROL, 0);
5176
5177         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
5178         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
5179         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
5180         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5181         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5182
5183         for_each_engine(engine, dev_priv)
5184                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5185
5186         I915_WRITE(GEN6_RC_SLEEP, 0);
5187         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
5188         if (IS_IVYBRIDGE(dev_priv))
5189                 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
5190         else
5191                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
5192         I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
5193         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
5194
5195         /* Check if we are enabling RC6 */
5196         rc6_mode = intel_enable_rc6();
5197         if (rc6_mode & INTEL_RC6_ENABLE)
5198                 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
5199
5200         /* We don't use those on Haswell */
5201         if (!IS_HASWELL(dev_priv)) {
5202                 if (rc6_mode & INTEL_RC6p_ENABLE)
5203                         rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
5204
5205                 if (rc6_mode & INTEL_RC6pp_ENABLE)
5206                         rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
5207         }
5208
5209         intel_print_rc6_info(dev_priv, rc6_mask);
5210
5211         I915_WRITE(GEN6_RC_CONTROL,
5212                    rc6_mask |
5213                    GEN6_RC_CTL_EI_MODE(1) |
5214                    GEN6_RC_CTL_HW_ENABLE);
5215
5216         /* Power down if completely idle for over 50ms */
5217         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
5218         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5219
5220         ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
5221         if (ret)
5222                 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
5223
5224         ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
5225         if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
5226                 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
5227                                  (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
5228                                  (pcu_mbox & 0xff) * 50);
5229                 dev_priv->rps.max_freq = pcu_mbox & 0xff;
5230         }
5231
5232         dev_priv->rps.power = HIGH_POWER; /* force a reset */
5233         gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
5234
5235         rc6vids = 0;
5236         ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
5237         if (IS_GEN6(dev_priv) && ret) {
5238                 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
5239         } else if (IS_GEN6(dev_priv) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
5240                 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
5241                           GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
5242                 rc6vids &= 0xffff00;
5243                 rc6vids |= GEN6_ENCODE_RC6_VID(450);
5244                 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
5245                 if (ret)
5246                         DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
5247         }
5248
5249         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5250 }
5251
5252 static void __gen6_update_ring_freq(struct drm_i915_private *dev_priv)
5253 {
5254         int min_freq = 15;
5255         unsigned int gpu_freq;
5256         unsigned int max_ia_freq, min_ring_freq;
5257         unsigned int max_gpu_freq, min_gpu_freq;
5258         int scaling_factor = 180;
5259         struct cpufreq_policy *policy;
5260
5261         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5262
5263         policy = cpufreq_cpu_get(0);
5264         if (policy) {
5265                 max_ia_freq = policy->cpuinfo.max_freq;
5266                 cpufreq_cpu_put(policy);
5267         } else {
5268                 /*
5269                  * Default to measured freq if none found, PCU will ensure we
5270                  * don't go over
5271                  */
5272                 max_ia_freq = tsc_khz;
5273         }
5274
5275         /* Convert from kHz to MHz */
5276         max_ia_freq /= 1000;
5277
5278         min_ring_freq = I915_READ(DCLK) & 0xf;
5279         /* convert DDR frequency from units of 266.6MHz to bandwidth */
5280         min_ring_freq = mult_frac(min_ring_freq, 8, 3);
5281
5282         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5283                 /* Convert GT frequency to 50 HZ units */
5284                 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
5285                 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
5286         } else {
5287                 min_gpu_freq = dev_priv->rps.min_freq;
5288                 max_gpu_freq = dev_priv->rps.max_freq;
5289         }
5290
5291         /*
5292          * For each potential GPU frequency, load a ring frequency we'd like
5293          * to use for memory access.  We do this by specifying the IA frequency
5294          * the PCU should use as a reference to determine the ring frequency.
5295          */
5296         for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
5297                 int diff = max_gpu_freq - gpu_freq;
5298                 unsigned int ia_freq = 0, ring_freq = 0;
5299
5300                 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5301                         /*
5302                          * ring_freq = 2 * GT. ring_freq is in 100MHz units
5303                          * No floor required for ring frequency on SKL.
5304                          */
5305                         ring_freq = gpu_freq;
5306                 } else if (INTEL_INFO(dev_priv)->gen >= 8) {
5307                         /* max(2 * GT, DDR). NB: GT is 50MHz units */
5308                         ring_freq = max(min_ring_freq, gpu_freq);
5309                 } else if (IS_HASWELL(dev_priv)) {
5310                         ring_freq = mult_frac(gpu_freq, 5, 4);
5311                         ring_freq = max(min_ring_freq, ring_freq);
5312                         /* leave ia_freq as the default, chosen by cpufreq */
5313                 } else {
5314                         /* On older processors, there is no separate ring
5315                          * clock domain, so in order to boost the bandwidth
5316                          * of the ring, we need to upclock the CPU (ia_freq).
5317                          *
5318                          * For GPU frequencies less than 750MHz,
5319                          * just use the lowest ring freq.
5320                          */
5321                         if (gpu_freq < min_freq)
5322                                 ia_freq = 800;
5323                         else
5324                                 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
5325                         ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
5326                 }
5327
5328                 sandybridge_pcode_write(dev_priv,
5329                                         GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
5330                                         ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
5331                                         ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
5332                                         gpu_freq);
5333         }
5334 }
5335
5336 void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
5337 {
5338         if (!HAS_CORE_RING_FREQ(dev_priv))
5339                 return;
5340
5341         mutex_lock(&dev_priv->rps.hw_lock);
5342         __gen6_update_ring_freq(dev_priv);
5343         mutex_unlock(&dev_priv->rps.hw_lock);
5344 }
5345
5346 static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
5347 {
5348         u32 val, rp0;
5349
5350         val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5351
5352         switch (INTEL_INFO(dev_priv)->eu_total) {
5353         case 8:
5354                 /* (2 * 4) config */
5355                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5356                 break;
5357         case 12:
5358                 /* (2 * 6) config */
5359                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5360                 break;
5361         case 16:
5362                 /* (2 * 8) config */
5363         default:
5364                 /* Setting (2 * 8) Min RP0 for any other combination */
5365                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5366                 break;
5367         }
5368
5369         rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5370
5371         return rp0;
5372 }
5373
5374 static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5375 {
5376         u32 val, rpe;
5377
5378         val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5379         rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5380
5381         return rpe;
5382 }
5383
5384 static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5385 {
5386         u32 val, rp1;
5387
5388         val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5389         rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5390
5391         return rp1;
5392 }
5393
5394 static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5395 {
5396         u32 val, rp1;
5397
5398         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5399
5400         rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5401
5402         return rp1;
5403 }
5404
5405 static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
5406 {
5407         u32 val, rp0;
5408
5409         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5410
5411         rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5412         /* Clamp to max */
5413         rp0 = min_t(u32, rp0, 0xea);
5414
5415         return rp0;
5416 }
5417
5418 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5419 {
5420         u32 val, rpe;
5421
5422         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
5423         rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
5424         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
5425         rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5426
5427         return rpe;
5428 }
5429
5430 static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
5431 {
5432         u32 val;
5433
5434         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
5435         /*
5436          * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
5437          * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
5438          * a BYT-M B0 the above register contains 0xbf. Moreover when setting
5439          * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
5440          * to make sure it matches what Punit accepts.
5441          */
5442         return max_t(u32, val, 0xc0);
5443 }
5444
5445 /* Check that the pctx buffer wasn't move under us. */
5446 static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5447 {
5448         unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5449
5450         WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5451                              dev_priv->vlv_pctx->stolen->start);
5452 }
5453
5454
5455 /* Check that the pcbr address is not empty. */
5456 static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5457 {
5458         unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5459
5460         WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5461 }
5462
5463 static void cherryview_setup_pctx(struct drm_i915_private *dev_priv)
5464 {
5465         struct i915_ggtt *ggtt = &dev_priv->ggtt;
5466         unsigned long pctx_paddr, paddr;
5467         u32 pcbr;
5468         int pctx_size = 32*1024;
5469
5470         pcbr = I915_READ(VLV_PCBR);
5471         if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
5472                 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5473                 paddr = (dev_priv->mm.stolen_base +
5474                          (ggtt->stolen_size - pctx_size));
5475
5476                 pctx_paddr = (paddr & (~4095));
5477                 I915_WRITE(VLV_PCBR, pctx_paddr);
5478         }
5479
5480         DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5481 }
5482
5483 static void valleyview_setup_pctx(struct drm_i915_private *dev_priv)
5484 {
5485         struct drm_i915_gem_object *pctx;
5486         unsigned long pctx_paddr;
5487         u32 pcbr;
5488         int pctx_size = 24*1024;
5489
5490         mutex_lock(&dev_priv->dev->struct_mutex);
5491
5492         pcbr = I915_READ(VLV_PCBR);
5493         if (pcbr) {
5494                 /* BIOS set it up already, grab the pre-alloc'd space */
5495                 int pcbr_offset;
5496
5497                 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
5498                 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
5499                                                                       pcbr_offset,
5500                                                                       I915_GTT_OFFSET_NONE,
5501                                                                       pctx_size);
5502                 goto out;
5503         }
5504
5505         DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5506
5507         /*
5508          * From the Gunit register HAS:
5509          * The Gfx driver is expected to program this register and ensure
5510          * proper allocation within Gfx stolen memory.  For example, this
5511          * register should be programmed such than the PCBR range does not
5512          * overlap with other ranges, such as the frame buffer, protected
5513          * memory, or any other relevant ranges.
5514          */
5515         pctx = i915_gem_object_create_stolen(dev_priv->dev, pctx_size);
5516         if (!pctx) {
5517                 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
5518                 goto out;
5519         }
5520
5521         pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5522         I915_WRITE(VLV_PCBR, pctx_paddr);
5523
5524 out:
5525         DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5526         dev_priv->vlv_pctx = pctx;
5527         mutex_unlock(&dev_priv->dev->struct_mutex);
5528 }
5529
5530 static void valleyview_cleanup_pctx(struct drm_i915_private *dev_priv)
5531 {
5532         if (WARN_ON(!dev_priv->vlv_pctx))
5533                 return;
5534
5535         drm_gem_object_unreference_unlocked(&dev_priv->vlv_pctx->base);
5536         dev_priv->vlv_pctx = NULL;
5537 }
5538
5539 static void vlv_init_gpll_ref_freq(struct drm_i915_private *dev_priv)
5540 {
5541         dev_priv->rps.gpll_ref_freq =
5542                 vlv_get_cck_clock(dev_priv, "GPLL ref",
5543                                   CCK_GPLL_CLOCK_CONTROL,
5544                                   dev_priv->czclk_freq);
5545
5546         DRM_DEBUG_DRIVER("GPLL reference freq: %d kHz\n",
5547                          dev_priv->rps.gpll_ref_freq);
5548 }
5549
5550 static void valleyview_init_gt_powersave(struct drm_i915_private *dev_priv)
5551 {
5552         u32 val;
5553
5554         valleyview_setup_pctx(dev_priv);
5555
5556         vlv_init_gpll_ref_freq(dev_priv);
5557
5558         mutex_lock(&dev_priv->rps.hw_lock);
5559
5560         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5561         switch ((val >> 6) & 3) {
5562         case 0:
5563         case 1:
5564                 dev_priv->mem_freq = 800;
5565                 break;
5566         case 2:
5567                 dev_priv->mem_freq = 1066;
5568                 break;
5569         case 3:
5570                 dev_priv->mem_freq = 1333;
5571                 break;
5572         }
5573         DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5574
5575         dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5576         dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5577         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5578                          intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5579                          dev_priv->rps.max_freq);
5580
5581         dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5582         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5583                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5584                          dev_priv->rps.efficient_freq);
5585
5586         dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5587         DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
5588                          intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5589                          dev_priv->rps.rp1_freq);
5590
5591         dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5592         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5593                          intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5594                          dev_priv->rps.min_freq);
5595
5596         dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5597
5598         /* Preserve min/max settings in case of re-init */
5599         if (dev_priv->rps.max_freq_softlimit == 0)
5600                 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5601
5602         if (dev_priv->rps.min_freq_softlimit == 0)
5603                 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5604
5605         mutex_unlock(&dev_priv->rps.hw_lock);
5606 }
5607
5608 static void cherryview_init_gt_powersave(struct drm_i915_private *dev_priv)
5609 {
5610         u32 val;
5611
5612         cherryview_setup_pctx(dev_priv);
5613
5614         vlv_init_gpll_ref_freq(dev_priv);
5615
5616         mutex_lock(&dev_priv->rps.hw_lock);
5617
5618         mutex_lock(&dev_priv->sb_lock);
5619         val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
5620         mutex_unlock(&dev_priv->sb_lock);
5621
5622         switch ((val >> 2) & 0x7) {
5623         case 3:
5624                 dev_priv->mem_freq = 2000;
5625                 break;
5626         default:
5627                 dev_priv->mem_freq = 1600;
5628                 break;
5629         }
5630         DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5631
5632         dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5633         dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5634         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5635                          intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5636                          dev_priv->rps.max_freq);
5637
5638         dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5639         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5640                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5641                          dev_priv->rps.efficient_freq);
5642
5643         dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5644         DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
5645                          intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5646                          dev_priv->rps.rp1_freq);
5647
5648         /* PUnit validated range is only [RPe, RP0] */
5649         dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
5650         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5651                          intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5652                          dev_priv->rps.min_freq);
5653
5654         WARN_ONCE((dev_priv->rps.max_freq |
5655                    dev_priv->rps.efficient_freq |
5656                    dev_priv->rps.rp1_freq |
5657                    dev_priv->rps.min_freq) & 1,
5658                   "Odd GPU freq values\n");
5659
5660         dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5661
5662         /* Preserve min/max settings in case of re-init */
5663         if (dev_priv->rps.max_freq_softlimit == 0)
5664                 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5665
5666         if (dev_priv->rps.min_freq_softlimit == 0)
5667                 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5668
5669         mutex_unlock(&dev_priv->rps.hw_lock);
5670 }
5671
5672 static void valleyview_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
5673 {
5674         valleyview_cleanup_pctx(dev_priv);
5675 }
5676
5677 static void cherryview_enable_rps(struct drm_i915_private *dev_priv)
5678 {
5679         struct intel_engine_cs *engine;
5680         u32 gtfifodbg, val, rc6_mode = 0, pcbr;
5681
5682         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5683
5684         gtfifodbg = I915_READ(GTFIFODBG) & ~(GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV |
5685                                              GT_FIFO_FREE_ENTRIES_CHV);
5686         if (gtfifodbg) {
5687                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5688                                  gtfifodbg);
5689                 I915_WRITE(GTFIFODBG, gtfifodbg);
5690         }
5691
5692         cherryview_check_pctx(dev_priv);
5693
5694         /* 1a & 1b: Get forcewake during program sequence. Although the driver
5695          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5696         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5697
5698         /*  Disable RC states. */
5699         I915_WRITE(GEN6_RC_CONTROL, 0);
5700
5701         /* 2a: Program RC6 thresholds.*/
5702         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5703         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5704         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5705
5706         for_each_engine(engine, dev_priv)
5707                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5708         I915_WRITE(GEN6_RC_SLEEP, 0);
5709
5710         /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
5711         I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
5712
5713         /* allows RC6 residency counter to work */
5714         I915_WRITE(VLV_COUNTER_CONTROL,
5715                    _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
5716                                       VLV_MEDIA_RC6_COUNT_EN |
5717                                       VLV_RENDER_RC6_COUNT_EN));
5718
5719         /* For now we assume BIOS is allocating and populating the PCBR  */
5720         pcbr = I915_READ(VLV_PCBR);
5721
5722         /* 3: Enable RC6 */
5723         if ((intel_enable_rc6() & INTEL_RC6_ENABLE) &&
5724             (pcbr >> VLV_PCBR_ADDR_SHIFT))
5725                 rc6_mode = GEN7_RC_CTL_TO_MODE;
5726
5727         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5728
5729         /* 4 Program defaults and thresholds for RPS*/
5730         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
5731         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5732         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5733         I915_WRITE(GEN6_RP_UP_EI, 66000);
5734         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5735
5736         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5737
5738         /* 5: Enable RPS */
5739         I915_WRITE(GEN6_RP_CONTROL,
5740                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
5741                    GEN6_RP_MEDIA_IS_GFX |
5742                    GEN6_RP_ENABLE |
5743                    GEN6_RP_UP_BUSY_AVG |
5744                    GEN6_RP_DOWN_IDLE_AVG);
5745
5746         /* Setting Fixed Bias */
5747         val = VLV_OVERRIDE_EN |
5748                   VLV_SOC_TDP_EN |
5749                   CHV_BIAS_CPU_50_SOC_50;
5750         vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5751
5752         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5753
5754         /* RPS code assumes GPLL is used */
5755         WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5756
5757         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
5758         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5759
5760         dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5761         DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
5762                          intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
5763                          dev_priv->rps.cur_freq);
5764
5765         DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5766                          intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq),
5767                          dev_priv->rps.idle_freq);
5768
5769         valleyview_set_rps(dev_priv, dev_priv->rps.idle_freq);
5770
5771         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5772 }
5773
5774 static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
5775 {
5776         struct intel_engine_cs *engine;
5777         u32 gtfifodbg, val, rc6_mode = 0;
5778
5779         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5780
5781         valleyview_check_pctx(dev_priv);
5782
5783         gtfifodbg = I915_READ(GTFIFODBG);
5784         if (gtfifodbg) {
5785                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5786                                  gtfifodbg);
5787                 I915_WRITE(GTFIFODBG, gtfifodbg);
5788         }
5789
5790         /* If VLV, Forcewake all wells, else re-direct to regular path */
5791         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5792
5793         /*  Disable RC states. */
5794         I915_WRITE(GEN6_RC_CONTROL, 0);
5795
5796         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
5797         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5798         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5799         I915_WRITE(GEN6_RP_UP_EI, 66000);
5800         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5801
5802         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5803
5804         I915_WRITE(GEN6_RP_CONTROL,
5805                    GEN6_RP_MEDIA_TURBO |
5806                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
5807                    GEN6_RP_MEDIA_IS_GFX |
5808                    GEN6_RP_ENABLE |
5809                    GEN6_RP_UP_BUSY_AVG |
5810                    GEN6_RP_DOWN_IDLE_CONT);
5811
5812         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
5813         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5814         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5815
5816         for_each_engine(engine, dev_priv)
5817                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5818
5819         I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
5820
5821         /* allows RC6 residency counter to work */
5822         I915_WRITE(VLV_COUNTER_CONTROL,
5823                    _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
5824                                       VLV_RENDER_RC0_COUNT_EN |
5825                                       VLV_MEDIA_RC6_COUNT_EN |
5826                                       VLV_RENDER_RC6_COUNT_EN));
5827
5828         if (intel_enable_rc6() & INTEL_RC6_ENABLE)
5829                 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
5830
5831         intel_print_rc6_info(dev_priv, rc6_mode);
5832
5833         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5834
5835         /* Setting Fixed Bias */
5836         val = VLV_OVERRIDE_EN |
5837                   VLV_SOC_TDP_EN |
5838                   VLV_BIAS_CPU_125_SOC_875;
5839         vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5840
5841         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5842
5843         /* RPS code assumes GPLL is used */
5844         WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5845
5846         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
5847         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5848
5849         dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5850         DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
5851                          intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
5852                          dev_priv->rps.cur_freq);
5853
5854         DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5855                          intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq),
5856                          dev_priv->rps.idle_freq);
5857
5858         valleyview_set_rps(dev_priv, dev_priv->rps.idle_freq);
5859
5860         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5861 }
5862
5863 static unsigned long intel_pxfreq(u32 vidfreq)
5864 {
5865         unsigned long freq;
5866         int div = (vidfreq & 0x3f0000) >> 16;
5867         int post = (vidfreq & 0x3000) >> 12;
5868         int pre = (vidfreq & 0x7);
5869
5870         if (!pre)
5871                 return 0;
5872
5873         freq = ((div * 133333) / ((1<<post) * pre));
5874
5875         return freq;
5876 }
5877
5878 static const struct cparams {
5879         u16 i;
5880         u16 t;
5881         u16 m;
5882         u16 c;
5883 } cparams[] = {
5884         { 1, 1333, 301, 28664 },
5885         { 1, 1066, 294, 24460 },
5886         { 1, 800, 294, 25192 },
5887         { 0, 1333, 276, 27605 },
5888         { 0, 1066, 276, 27605 },
5889         { 0, 800, 231, 23784 },
5890 };
5891
5892 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
5893 {
5894         u64 total_count, diff, ret;
5895         u32 count1, count2, count3, m = 0, c = 0;
5896         unsigned long now = jiffies_to_msecs(jiffies), diff1;
5897         int i;
5898
5899         assert_spin_locked(&mchdev_lock);
5900
5901         diff1 = now - dev_priv->ips.last_time1;
5902
5903         /* Prevent division-by-zero if we are asking too fast.
5904          * Also, we don't get interesting results if we are polling
5905          * faster than once in 10ms, so just return the saved value
5906          * in such cases.
5907          */
5908         if (diff1 <= 10)
5909                 return dev_priv->ips.chipset_power;
5910
5911         count1 = I915_READ(DMIEC);
5912         count2 = I915_READ(DDREC);
5913         count3 = I915_READ(CSIEC);
5914
5915         total_count = count1 + count2 + count3;
5916
5917         /* FIXME: handle per-counter overflow */
5918         if (total_count < dev_priv->ips.last_count1) {
5919                 diff = ~0UL - dev_priv->ips.last_count1;
5920                 diff += total_count;
5921         } else {
5922                 diff = total_count - dev_priv->ips.last_count1;
5923         }
5924
5925         for (i = 0; i < ARRAY_SIZE(cparams); i++) {
5926                 if (cparams[i].i == dev_priv->ips.c_m &&
5927                     cparams[i].t == dev_priv->ips.r_t) {
5928                         m = cparams[i].m;
5929                         c = cparams[i].c;
5930                         break;
5931                 }
5932         }
5933
5934         diff = div_u64(diff, diff1);
5935         ret = ((m * diff) + c);
5936         ret = div_u64(ret, 10);
5937
5938         dev_priv->ips.last_count1 = total_count;
5939         dev_priv->ips.last_time1 = now;
5940
5941         dev_priv->ips.chipset_power = ret;
5942
5943         return ret;
5944 }
5945
5946 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
5947 {
5948         unsigned long val;
5949
5950         if (INTEL_INFO(dev_priv)->gen != 5)
5951                 return 0;
5952
5953         spin_lock_irq(&mchdev_lock);
5954
5955         val = __i915_chipset_val(dev_priv);
5956
5957         spin_unlock_irq(&mchdev_lock);
5958
5959         return val;
5960 }
5961
5962 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
5963 {
5964         unsigned long m, x, b;
5965         u32 tsfs;
5966
5967         tsfs = I915_READ(TSFS);
5968
5969         m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
5970         x = I915_READ8(TR1);
5971
5972         b = tsfs & TSFS_INTR_MASK;
5973
5974         return ((m * x) / 127) - b;
5975 }
5976
5977 static int _pxvid_to_vd(u8 pxvid)
5978 {
5979         if (pxvid == 0)
5980                 return 0;
5981
5982         if (pxvid >= 8 && pxvid < 31)
5983                 pxvid = 31;
5984
5985         return (pxvid + 2) * 125;
5986 }
5987
5988 static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
5989 {
5990         const int vd = _pxvid_to_vd(pxvid);
5991         const int vm = vd - 1125;
5992
5993         if (INTEL_INFO(dev_priv)->is_mobile)
5994                 return vm > 0 ? vm : 0;
5995
5996         return vd;
5997 }
5998
5999 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
6000 {
6001         u64 now, diff, diffms;
6002         u32 count;
6003
6004         assert_spin_locked(&mchdev_lock);
6005
6006         now = ktime_get_raw_ns();
6007         diffms = now - dev_priv->ips.last_time2;
6008         do_div(diffms, NSEC_PER_MSEC);
6009
6010         /* Don't divide by 0 */
6011         if (!diffms)
6012                 return;
6013
6014         count = I915_READ(GFXEC);
6015
6016         if (count < dev_priv->ips.last_count2) {
6017                 diff = ~0UL - dev_priv->ips.last_count2;
6018                 diff += count;
6019         } else {
6020                 diff = count - dev_priv->ips.last_count2;
6021         }
6022
6023         dev_priv->ips.last_count2 = count;
6024         dev_priv->ips.last_time2 = now;
6025
6026         /* More magic constants... */
6027         diff = diff * 1181;
6028         diff = div_u64(diff, diffms * 10);
6029         dev_priv->ips.gfx_power = diff;
6030 }
6031
6032 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
6033 {
6034         if (INTEL_INFO(dev_priv)->gen != 5)
6035                 return;
6036
6037         spin_lock_irq(&mchdev_lock);
6038
6039         __i915_update_gfx_val(dev_priv);
6040
6041         spin_unlock_irq(&mchdev_lock);
6042 }
6043
6044 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
6045 {
6046         unsigned long t, corr, state1, corr2, state2;
6047         u32 pxvid, ext_v;
6048
6049         assert_spin_locked(&mchdev_lock);
6050
6051         pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
6052         pxvid = (pxvid >> 24) & 0x7f;
6053         ext_v = pvid_to_extvid(dev_priv, pxvid);
6054
6055         state1 = ext_v;
6056
6057         t = i915_mch_val(dev_priv);
6058
6059         /* Revel in the empirically derived constants */
6060
6061         /* Correction factor in 1/100000 units */
6062         if (t > 80)
6063                 corr = ((t * 2349) + 135940);
6064         else if (t >= 50)
6065                 corr = ((t * 964) + 29317);
6066         else /* < 50 */
6067                 corr = ((t * 301) + 1004);
6068
6069         corr = corr * ((150142 * state1) / 10000 - 78642);
6070         corr /= 100000;
6071         corr2 = (corr * dev_priv->ips.corr);
6072
6073         state2 = (corr2 * state1) / 10000;
6074         state2 /= 100; /* convert to mW */
6075
6076         __i915_update_gfx_val(dev_priv);
6077
6078         return dev_priv->ips.gfx_power + state2;
6079 }
6080
6081 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
6082 {
6083         unsigned long val;
6084
6085         if (INTEL_INFO(dev_priv)->gen != 5)
6086                 return 0;
6087
6088         spin_lock_irq(&mchdev_lock);
6089
6090         val = __i915_gfx_val(dev_priv);
6091
6092         spin_unlock_irq(&mchdev_lock);
6093
6094         return val;
6095 }
6096
6097 /**
6098  * i915_read_mch_val - return value for IPS use
6099  *
6100  * Calculate and return a value for the IPS driver to use when deciding whether
6101  * we have thermal and power headroom to increase CPU or GPU power budget.
6102  */
6103 unsigned long i915_read_mch_val(void)
6104 {
6105         struct drm_i915_private *dev_priv;
6106         unsigned long chipset_val, graphics_val, ret = 0;
6107
6108         spin_lock_irq(&mchdev_lock);
6109         if (!i915_mch_dev)
6110                 goto out_unlock;
6111         dev_priv = i915_mch_dev;
6112
6113         chipset_val = __i915_chipset_val(dev_priv);
6114         graphics_val = __i915_gfx_val(dev_priv);
6115
6116         ret = chipset_val + graphics_val;
6117
6118 out_unlock:
6119         spin_unlock_irq(&mchdev_lock);
6120
6121         return ret;
6122 }
6123 EXPORT_SYMBOL_GPL(i915_read_mch_val);
6124
6125 /**
6126  * i915_gpu_raise - raise GPU frequency limit
6127  *
6128  * Raise the limit; IPS indicates we have thermal headroom.
6129  */
6130 bool i915_gpu_raise(void)
6131 {
6132         struct drm_i915_private *dev_priv;
6133         bool ret = true;
6134
6135         spin_lock_irq(&mchdev_lock);
6136         if (!i915_mch_dev) {
6137                 ret = false;
6138                 goto out_unlock;
6139         }
6140         dev_priv = i915_mch_dev;
6141
6142         if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
6143                 dev_priv->ips.max_delay--;
6144
6145 out_unlock:
6146         spin_unlock_irq(&mchdev_lock);
6147
6148         return ret;
6149 }
6150 EXPORT_SYMBOL_GPL(i915_gpu_raise);
6151
6152 /**
6153  * i915_gpu_lower - lower GPU frequency limit
6154  *
6155  * IPS indicates we're close to a thermal limit, so throttle back the GPU
6156  * frequency maximum.
6157  */
6158 bool i915_gpu_lower(void)
6159 {
6160         struct drm_i915_private *dev_priv;
6161         bool ret = true;
6162
6163         spin_lock_irq(&mchdev_lock);
6164         if (!i915_mch_dev) {
6165                 ret = false;
6166                 goto out_unlock;
6167         }
6168         dev_priv = i915_mch_dev;
6169
6170         if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
6171                 dev_priv->ips.max_delay++;
6172
6173 out_unlock:
6174         spin_unlock_irq(&mchdev_lock);
6175
6176         return ret;
6177 }
6178 EXPORT_SYMBOL_GPL(i915_gpu_lower);
6179
6180 /**
6181  * i915_gpu_busy - indicate GPU business to IPS
6182  *
6183  * Tell the IPS driver whether or not the GPU is busy.
6184  */
6185 bool i915_gpu_busy(void)
6186 {
6187         struct drm_i915_private *dev_priv;
6188         struct intel_engine_cs *engine;
6189         bool ret = false;
6190
6191         spin_lock_irq(&mchdev_lock);
6192         if (!i915_mch_dev)
6193                 goto out_unlock;
6194         dev_priv = i915_mch_dev;
6195
6196         for_each_engine(engine, dev_priv)
6197                 ret |= !list_empty(&engine->request_list);
6198
6199 out_unlock:
6200         spin_unlock_irq(&mchdev_lock);
6201
6202         return ret;
6203 }
6204 EXPORT_SYMBOL_GPL(i915_gpu_busy);
6205
6206 /**
6207  * i915_gpu_turbo_disable - disable graphics turbo
6208  *
6209  * Disable graphics turbo by resetting the max frequency and setting the
6210  * current frequency to the default.
6211  */
6212 bool i915_gpu_turbo_disable(void)
6213 {
6214         struct drm_i915_private *dev_priv;
6215         bool ret = true;
6216
6217         spin_lock_irq(&mchdev_lock);
6218         if (!i915_mch_dev) {
6219                 ret = false;
6220                 goto out_unlock;
6221         }
6222         dev_priv = i915_mch_dev;
6223
6224         dev_priv->ips.max_delay = dev_priv->ips.fstart;
6225
6226         if (!ironlake_set_drps(dev_priv, dev_priv->ips.fstart))
6227                 ret = false;
6228
6229 out_unlock:
6230         spin_unlock_irq(&mchdev_lock);
6231
6232         return ret;
6233 }
6234 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
6235
6236 /**
6237  * Tells the intel_ips driver that the i915 driver is now loaded, if
6238  * IPS got loaded first.
6239  *
6240  * This awkward dance is so that neither module has to depend on the
6241  * other in order for IPS to do the appropriate communication of
6242  * GPU turbo limits to i915.
6243  */
6244 static void
6245 ips_ping_for_i915_load(void)
6246 {
6247         void (*link)(void);
6248
6249         link = symbol_get(ips_link_to_i915_driver);
6250         if (link) {
6251                 link();
6252                 symbol_put(ips_link_to_i915_driver);
6253         }
6254 }
6255
6256 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
6257 {
6258         /* We only register the i915 ips part with intel-ips once everything is
6259          * set up, to avoid intel-ips sneaking in and reading bogus values. */
6260         spin_lock_irq(&mchdev_lock);
6261         i915_mch_dev = dev_priv;
6262         spin_unlock_irq(&mchdev_lock);
6263
6264         ips_ping_for_i915_load();
6265 }
6266
6267 void intel_gpu_ips_teardown(void)
6268 {
6269         spin_lock_irq(&mchdev_lock);
6270         i915_mch_dev = NULL;
6271         spin_unlock_irq(&mchdev_lock);
6272 }
6273
6274 static void intel_init_emon(struct drm_i915_private *dev_priv)
6275 {
6276         u32 lcfuse;
6277         u8 pxw[16];
6278         int i;
6279
6280         /* Disable to program */
6281         I915_WRITE(ECR, 0);
6282         POSTING_READ(ECR);
6283
6284         /* Program energy weights for various events */
6285         I915_WRITE(SDEW, 0x15040d00);
6286         I915_WRITE(CSIEW0, 0x007f0000);
6287         I915_WRITE(CSIEW1, 0x1e220004);
6288         I915_WRITE(CSIEW2, 0x04000004);
6289
6290         for (i = 0; i < 5; i++)
6291                 I915_WRITE(PEW(i), 0);
6292         for (i = 0; i < 3; i++)
6293                 I915_WRITE(DEW(i), 0);
6294
6295         /* Program P-state weights to account for frequency power adjustment */
6296         for (i = 0; i < 16; i++) {
6297                 u32 pxvidfreq = I915_READ(PXVFREQ(i));
6298                 unsigned long freq = intel_pxfreq(pxvidfreq);
6299                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6300                         PXVFREQ_PX_SHIFT;
6301                 unsigned long val;
6302
6303                 val = vid * vid;
6304                 val *= (freq / 1000);
6305                 val *= 255;
6306                 val /= (127*127*900);
6307                 if (val > 0xff)
6308                         DRM_ERROR("bad pxval: %ld\n", val);
6309                 pxw[i] = val;
6310         }
6311         /* Render standby states get 0 weight */
6312         pxw[14] = 0;
6313         pxw[15] = 0;
6314
6315         for (i = 0; i < 4; i++) {
6316                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6317                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
6318                 I915_WRITE(PXW(i), val);
6319         }
6320
6321         /* Adjust magic regs to magic values (more experimental results) */
6322         I915_WRITE(OGW0, 0);
6323         I915_WRITE(OGW1, 0);
6324         I915_WRITE(EG0, 0x00007f00);
6325         I915_WRITE(EG1, 0x0000000e);
6326         I915_WRITE(EG2, 0x000e0000);
6327         I915_WRITE(EG3, 0x68000300);
6328         I915_WRITE(EG4, 0x42000000);
6329         I915_WRITE(EG5, 0x00140031);
6330         I915_WRITE(EG6, 0);
6331         I915_WRITE(EG7, 0);
6332
6333         for (i = 0; i < 8; i++)
6334                 I915_WRITE(PXWL(i), 0);
6335
6336         /* Enable PMON + select events */
6337         I915_WRITE(ECR, 0x80000019);
6338
6339         lcfuse = I915_READ(LCFUSE02);
6340
6341         dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
6342 }
6343
6344 void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
6345 {
6346         /*
6347          * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6348          * requirement.
6349          */
6350         if (!i915.enable_rc6) {
6351                 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6352                 intel_runtime_pm_get(dev_priv);
6353         }
6354
6355         if (IS_CHERRYVIEW(dev_priv))
6356                 cherryview_init_gt_powersave(dev_priv);
6357         else if (IS_VALLEYVIEW(dev_priv))
6358                 valleyview_init_gt_powersave(dev_priv);
6359 }
6360
6361 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
6362 {
6363         if (IS_CHERRYVIEW(dev_priv))
6364                 return;
6365         else if (IS_VALLEYVIEW(dev_priv))
6366                 valleyview_cleanup_gt_powersave(dev_priv);
6367
6368         if (!i915.enable_rc6)
6369                 intel_runtime_pm_put(dev_priv);
6370 }
6371
6372 static void gen6_suspend_rps(struct drm_i915_private *dev_priv)
6373 {
6374         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
6375
6376         gen6_disable_rps_interrupts(dev_priv);
6377 }
6378
6379 /**
6380  * intel_suspend_gt_powersave - suspend PM work and helper threads
6381  * @dev_priv: i915 device
6382  *
6383  * We don't want to disable RC6 or other features here, we just want
6384  * to make sure any work we've queued has finished and won't bother
6385  * us while we're suspended.
6386  */
6387 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv)
6388 {
6389         if (INTEL_GEN(dev_priv) < 6)
6390                 return;
6391
6392         gen6_suspend_rps(dev_priv);
6393
6394         /* Force GPU to min freq during suspend */
6395         gen6_rps_idle(dev_priv);
6396 }
6397
6398 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
6399 {
6400         if (IS_IRONLAKE_M(dev_priv)) {
6401                 ironlake_disable_drps(dev_priv);
6402         } else if (INTEL_INFO(dev_priv)->gen >= 6) {
6403                 intel_suspend_gt_powersave(dev_priv);
6404
6405                 mutex_lock(&dev_priv->rps.hw_lock);
6406                 if (INTEL_INFO(dev_priv)->gen >= 9) {
6407                         gen9_disable_rc6(dev_priv);
6408                         gen9_disable_rps(dev_priv);
6409                 } else if (IS_CHERRYVIEW(dev_priv))
6410                         cherryview_disable_rps(dev_priv);
6411                 else if (IS_VALLEYVIEW(dev_priv))
6412                         valleyview_disable_rps(dev_priv);
6413                 else
6414                         gen6_disable_rps(dev_priv);
6415
6416                 dev_priv->rps.enabled = false;
6417                 mutex_unlock(&dev_priv->rps.hw_lock);
6418         }
6419 }
6420
6421 static void intel_gen6_powersave_work(struct work_struct *work)
6422 {
6423         struct drm_i915_private *dev_priv =
6424                 container_of(work, struct drm_i915_private,
6425                              rps.delayed_resume_work.work);
6426
6427         mutex_lock(&dev_priv->rps.hw_lock);
6428
6429         gen6_reset_rps_interrupts(dev_priv);
6430
6431         if (IS_CHERRYVIEW(dev_priv)) {
6432                 cherryview_enable_rps(dev_priv);
6433         } else if (IS_VALLEYVIEW(dev_priv)) {
6434                 valleyview_enable_rps(dev_priv);
6435         } else if (INTEL_INFO(dev_priv)->gen >= 9) {
6436                 gen9_enable_rc6(dev_priv);
6437                 gen9_enable_rps(dev_priv);
6438                 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
6439                         __gen6_update_ring_freq(dev_priv);
6440         } else if (IS_BROADWELL(dev_priv)) {
6441                 gen8_enable_rps(dev_priv);
6442                 __gen6_update_ring_freq(dev_priv);
6443         } else {
6444                 gen6_enable_rps(dev_priv);
6445                 __gen6_update_ring_freq(dev_priv);
6446         }
6447
6448         WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6449         WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6450
6451         WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6452         WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6453
6454         dev_priv->rps.enabled = true;
6455
6456         gen6_enable_rps_interrupts(dev_priv);
6457
6458         mutex_unlock(&dev_priv->rps.hw_lock);
6459
6460         intel_runtime_pm_put(dev_priv);
6461 }
6462
6463 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
6464 {
6465         /* Powersaving is controlled by the host when inside a VM */
6466         if (intel_vgpu_active(dev_priv))
6467                 return;
6468
6469         if (IS_IRONLAKE_M(dev_priv)) {
6470                 ironlake_enable_drps(dev_priv);
6471                 mutex_lock(&dev_priv->dev->struct_mutex);
6472                 intel_init_emon(dev_priv);
6473                 mutex_unlock(&dev_priv->dev->struct_mutex);
6474         } else if (INTEL_INFO(dev_priv)->gen >= 6) {
6475                 /*
6476                  * PCU communication is slow and this doesn't need to be
6477                  * done at any specific time, so do this out of our fast path
6478                  * to make resume and init faster.
6479                  *
6480                  * We depend on the HW RC6 power context save/restore
6481                  * mechanism when entering D3 through runtime PM suspend. So
6482                  * disable RPM until RPS/RC6 is properly setup. We can only
6483                  * get here via the driver load/system resume/runtime resume
6484                  * paths, so the _noresume version is enough (and in case of
6485                  * runtime resume it's necessary).
6486                  */
6487                 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
6488                                            round_jiffies_up_relative(HZ)))
6489                         intel_runtime_pm_get_noresume(dev_priv);
6490         }
6491 }
6492
6493 void intel_reset_gt_powersave(struct drm_i915_private *dev_priv)
6494 {
6495         if (INTEL_INFO(dev_priv)->gen < 6)
6496                 return;
6497
6498         gen6_suspend_rps(dev_priv);
6499         dev_priv->rps.enabled = false;
6500 }
6501
6502 static void ibx_init_clock_gating(struct drm_device *dev)
6503 {
6504         struct drm_i915_private *dev_priv = dev->dev_private;
6505
6506         /*
6507          * On Ibex Peak and Cougar Point, we need to disable clock
6508          * gating for the panel power sequencer or it will fail to
6509          * start up when no ports are active.
6510          */
6511         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6512 }
6513
6514 static void g4x_disable_trickle_feed(struct drm_device *dev)
6515 {
6516         struct drm_i915_private *dev_priv = dev->dev_private;
6517         enum pipe pipe;
6518
6519         for_each_pipe(dev_priv, pipe) {
6520                 I915_WRITE(DSPCNTR(pipe),
6521                            I915_READ(DSPCNTR(pipe)) |
6522                            DISPPLANE_TRICKLE_FEED_DISABLE);
6523
6524                 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6525                 POSTING_READ(DSPSURF(pipe));
6526         }
6527 }
6528
6529 static void ilk_init_lp_watermarks(struct drm_device *dev)
6530 {
6531         struct drm_i915_private *dev_priv = dev->dev_private;
6532
6533         I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6534         I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6535         I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6536
6537         /*
6538          * Don't touch WM1S_LP_EN here.
6539          * Doing so could cause underruns.
6540          */
6541 }
6542
6543 static void ironlake_init_clock_gating(struct drm_device *dev)
6544 {
6545         struct drm_i915_private *dev_priv = dev->dev_private;
6546         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6547
6548         /*
6549          * Required for FBC
6550          * WaFbcDisableDpfcClockGating:ilk
6551          */
6552         dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6553                    ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6554                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6555
6556         I915_WRITE(PCH_3DCGDIS0,
6557                    MARIUNIT_CLOCK_GATE_DISABLE |
6558                    SVSMUNIT_CLOCK_GATE_DISABLE);
6559         I915_WRITE(PCH_3DCGDIS1,
6560                    VFMUNIT_CLOCK_GATE_DISABLE);
6561
6562         /*
6563          * According to the spec the following bits should be set in
6564          * order to enable memory self-refresh
6565          * The bit 22/21 of 0x42004
6566          * The bit 5 of 0x42020
6567          * The bit 15 of 0x45000
6568          */
6569         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6570                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
6571                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
6572         dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6573         I915_WRITE(DISP_ARB_CTL,
6574                    (I915_READ(DISP_ARB_CTL) |
6575                     DISP_FBC_WM_DIS));
6576
6577         ilk_init_lp_watermarks(dev);
6578
6579         /*
6580          * Based on the document from hardware guys the following bits
6581          * should be set unconditionally in order to enable FBC.
6582          * The bit 22 of 0x42000
6583          * The bit 22 of 0x42004
6584          * The bit 7,8,9 of 0x42020.
6585          */
6586         if (IS_IRONLAKE_M(dev)) {
6587                 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6588                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6589                            I915_READ(ILK_DISPLAY_CHICKEN1) |
6590                            ILK_FBCQ_DIS);
6591                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6592                            I915_READ(ILK_DISPLAY_CHICKEN2) |
6593                            ILK_DPARB_GATE);
6594         }
6595
6596         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6597
6598         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6599                    I915_READ(ILK_DISPLAY_CHICKEN2) |
6600                    ILK_ELPIN_409_SELECT);
6601         I915_WRITE(_3D_CHICKEN2,
6602                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6603                    _3D_CHICKEN2_WM_READ_PIPELINED);
6604
6605         /* WaDisableRenderCachePipelinedFlush:ilk */
6606         I915_WRITE(CACHE_MODE_0,
6607                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
6608
6609         /* WaDisable_RenderCache_OperationalFlush:ilk */
6610         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6611
6612         g4x_disable_trickle_feed(dev);
6613
6614         ibx_init_clock_gating(dev);
6615 }
6616
6617 static void cpt_init_clock_gating(struct drm_device *dev)
6618 {
6619         struct drm_i915_private *dev_priv = dev->dev_private;
6620         int pipe;
6621         uint32_t val;
6622
6623         /*
6624          * On Ibex Peak and Cougar Point, we need to disable clock
6625          * gating for the panel power sequencer or it will fail to
6626          * start up when no ports are active.
6627          */
6628         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6629                    PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6630                    PCH_CPUNIT_CLOCK_GATE_DISABLE);
6631         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6632                    DPLS_EDP_PPS_FIX_DIS);
6633         /* The below fixes the weird display corruption, a few pixels shifted
6634          * downward, on (only) LVDS of some HP laptops with IVY.
6635          */
6636         for_each_pipe(dev_priv, pipe) {
6637                 val = I915_READ(TRANS_CHICKEN2(pipe));
6638                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6639                 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6640                 if (dev_priv->vbt.fdi_rx_polarity_inverted)
6641                         val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6642                 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
6643                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6644                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
6645                 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6646         }
6647         /* WADP0ClockGatingDisable */
6648         for_each_pipe(dev_priv, pipe) {
6649                 I915_WRITE(TRANS_CHICKEN1(pipe),
6650                            TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6651         }
6652 }
6653
6654 static void gen6_check_mch_setup(struct drm_device *dev)
6655 {
6656         struct drm_i915_private *dev_priv = dev->dev_private;
6657         uint32_t tmp;
6658
6659         tmp = I915_READ(MCH_SSKPD);
6660         if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
6661                 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
6662                               tmp);
6663 }
6664
6665 static void gen6_init_clock_gating(struct drm_device *dev)
6666 {
6667         struct drm_i915_private *dev_priv = dev->dev_private;
6668         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6669
6670         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6671
6672         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6673                    I915_READ(ILK_DISPLAY_CHICKEN2) |
6674                    ILK_ELPIN_409_SELECT);
6675
6676         /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
6677         I915_WRITE(_3D_CHICKEN,
6678                    _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
6679
6680         /* WaDisable_RenderCache_OperationalFlush:snb */
6681         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6682
6683         /*
6684          * BSpec recoomends 8x4 when MSAA is used,
6685          * however in practice 16x4 seems fastest.
6686          *
6687          * Note that PS/WM thread counts depend on the WIZ hashing
6688          * disable bit, which we don't touch here, but it's good
6689          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6690          */
6691         I915_WRITE(GEN6_GT_MODE,
6692                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6693
6694         ilk_init_lp_watermarks(dev);
6695
6696         I915_WRITE(CACHE_MODE_0,
6697                    _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6698
6699         I915_WRITE(GEN6_UCGCTL1,
6700                    I915_READ(GEN6_UCGCTL1) |
6701                    GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
6702                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6703
6704         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
6705          * gating disable must be set.  Failure to set it results in
6706          * flickering pixels due to Z write ordering failures after
6707          * some amount of runtime in the Mesa "fire" demo, and Unigine
6708          * Sanctuary and Tropics, and apparently anything else with
6709          * alpha test or pixel discard.
6710          *
6711          * According to the spec, bit 11 (RCCUNIT) must also be set,
6712          * but we didn't debug actual testcases to find it out.
6713          *
6714          * WaDisableRCCUnitClockGating:snb
6715          * WaDisableRCPBUnitClockGating:snb
6716          */
6717         I915_WRITE(GEN6_UCGCTL2,
6718                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
6719                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
6720
6721         /* WaStripsFansDisableFastClipPerformanceFix:snb */
6722         I915_WRITE(_3D_CHICKEN3,
6723                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6724
6725         /*
6726          * Bspec says:
6727          * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
6728          * 3DSTATE_SF number of SF output attributes is more than 16."
6729          */
6730         I915_WRITE(_3D_CHICKEN3,
6731                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
6732
6733         /*
6734          * According to the spec the following bits should be
6735          * set in order to enable memory self-refresh and fbc:
6736          * The bit21 and bit22 of 0x42000
6737          * The bit21 and bit22 of 0x42004
6738          * The bit5 and bit7 of 0x42020
6739          * The bit14 of 0x70180
6740          * The bit14 of 0x71180
6741          *
6742          * WaFbcAsynchFlipDisableFbcQueue:snb
6743          */
6744         I915_WRITE(ILK_DISPLAY_CHICKEN1,
6745                    I915_READ(ILK_DISPLAY_CHICKEN1) |
6746                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
6747         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6748                    I915_READ(ILK_DISPLAY_CHICKEN2) |
6749                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
6750         I915_WRITE(ILK_DSPCLK_GATE_D,
6751                    I915_READ(ILK_DSPCLK_GATE_D) |
6752                    ILK_DPARBUNIT_CLOCK_GATE_ENABLE  |
6753                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6754
6755         g4x_disable_trickle_feed(dev);
6756
6757         cpt_init_clock_gating(dev);
6758
6759         gen6_check_mch_setup(dev);
6760 }
6761
6762 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
6763 {
6764         uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
6765
6766         /*
6767          * WaVSThreadDispatchOverride:ivb,vlv
6768          *
6769          * This actually overrides the dispatch
6770          * mode for all thread types.
6771          */
6772         reg &= ~GEN7_FF_SCHED_MASK;
6773         reg |= GEN7_FF_TS_SCHED_HW;
6774         reg |= GEN7_FF_VS_SCHED_HW;
6775         reg |= GEN7_FF_DS_SCHED_HW;
6776
6777         I915_WRITE(GEN7_FF_THREAD_MODE, reg);
6778 }
6779
6780 static void lpt_init_clock_gating(struct drm_device *dev)
6781 {
6782         struct drm_i915_private *dev_priv = dev->dev_private;
6783
6784         /*
6785          * TODO: this bit should only be enabled when really needed, then
6786          * disabled when not needed anymore in order to save power.
6787          */
6788         if (HAS_PCH_LPT_LP(dev))
6789                 I915_WRITE(SOUTH_DSPCLK_GATE_D,
6790                            I915_READ(SOUTH_DSPCLK_GATE_D) |
6791                            PCH_LP_PARTITION_LEVEL_DISABLE);
6792
6793         /* WADPOClockGatingDisable:hsw */
6794         I915_WRITE(TRANS_CHICKEN1(PIPE_A),
6795                    I915_READ(TRANS_CHICKEN1(PIPE_A)) |
6796                    TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6797 }
6798
6799 static void lpt_suspend_hw(struct drm_device *dev)
6800 {
6801         struct drm_i915_private *dev_priv = dev->dev_private;
6802
6803         if (HAS_PCH_LPT_LP(dev)) {
6804                 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
6805
6806                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6807                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6808         }
6809 }
6810
6811 static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
6812                                    int general_prio_credits,
6813                                    int high_prio_credits)
6814 {
6815         u32 misccpctl;
6816
6817         /* WaTempDisableDOPClkGating:bdw */
6818         misccpctl = I915_READ(GEN7_MISCCPCTL);
6819         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
6820
6821         I915_WRITE(GEN8_L3SQCREG1,
6822                    L3_GENERAL_PRIO_CREDITS(general_prio_credits) |
6823                    L3_HIGH_PRIO_CREDITS(high_prio_credits));
6824
6825         /*
6826          * Wait at least 100 clocks before re-enabling clock gating.
6827          * See the definition of L3SQCREG1 in BSpec.
6828          */
6829         POSTING_READ(GEN8_L3SQCREG1);
6830         udelay(1);
6831         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
6832 }
6833
6834 static void skylake_init_clock_gating(struct drm_device *dev)
6835 {
6836         struct drm_i915_private *dev_priv = dev->dev_private;
6837
6838         /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,kbl */
6839         I915_WRITE(CHICKEN_PAR1_1,
6840                    I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
6841 }
6842
6843 static void broadwell_init_clock_gating(struct drm_device *dev)
6844 {
6845         struct drm_i915_private *dev_priv = dev->dev_private;
6846         enum pipe pipe;
6847
6848         ilk_init_lp_watermarks(dev);
6849
6850         /* WaSwitchSolVfFArbitrationPriority:bdw */
6851         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6852
6853         /* WaPsrDPAMaskVBlankInSRD:bdw */
6854         I915_WRITE(CHICKEN_PAR1_1,
6855                    I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
6856
6857         /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
6858         for_each_pipe(dev_priv, pipe) {
6859                 I915_WRITE(CHICKEN_PIPESL_1(pipe),
6860                            I915_READ(CHICKEN_PIPESL_1(pipe)) |
6861                            BDW_DPRS_MASK_VBLANK_SRD);
6862         }
6863
6864         /* WaVSRefCountFullforceMissDisable:bdw */
6865         /* WaDSRefCountFullforceMissDisable:bdw */
6866         I915_WRITE(GEN7_FF_THREAD_MODE,
6867                    I915_READ(GEN7_FF_THREAD_MODE) &
6868                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
6869
6870         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6871                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
6872
6873         /* WaDisableSDEUnitClockGating:bdw */
6874         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6875                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6876
6877         /* WaProgramL3SqcReg1Default:bdw */
6878         gen8_set_l3sqc_credits(dev_priv, 30, 2);
6879
6880         /*
6881          * WaGttCachingOffByDefault:bdw
6882          * GTT cache may not work with big pages, so if those
6883          * are ever enabled GTT cache may need to be disabled.
6884          */
6885         I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
6886
6887         lpt_init_clock_gating(dev);
6888 }
6889
6890 static void haswell_init_clock_gating(struct drm_device *dev)
6891 {
6892         struct drm_i915_private *dev_priv = dev->dev_private;
6893
6894         ilk_init_lp_watermarks(dev);
6895
6896         /* L3 caching of data atomics doesn't work -- disable it. */
6897         I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
6898         I915_WRITE(HSW_ROW_CHICKEN3,
6899                    _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
6900
6901         /* This is required by WaCatErrorRejectionIssue:hsw */
6902         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6903                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6904                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6905
6906         /* WaVSRefCountFullforceMissDisable:hsw */
6907         I915_WRITE(GEN7_FF_THREAD_MODE,
6908                    I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
6909
6910         /* WaDisable_RenderCache_OperationalFlush:hsw */
6911         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6912
6913         /* enable HiZ Raw Stall Optimization */
6914         I915_WRITE(CACHE_MODE_0_GEN7,
6915                    _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6916
6917         /* WaDisable4x2SubspanOptimization:hsw */
6918         I915_WRITE(CACHE_MODE_1,
6919                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6920
6921         /*
6922          * BSpec recommends 8x4 when MSAA is used,
6923          * however in practice 16x4 seems fastest.
6924          *
6925          * Note that PS/WM thread counts depend on the WIZ hashing
6926          * disable bit, which we don't touch here, but it's good
6927          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6928          */
6929         I915_WRITE(GEN7_GT_MODE,
6930                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6931
6932         /* WaSampleCChickenBitEnable:hsw */
6933         I915_WRITE(HALF_SLICE_CHICKEN3,
6934                    _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
6935
6936         /* WaSwitchSolVfFArbitrationPriority:hsw */
6937         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6938
6939         /* WaRsPkgCStateDisplayPMReq:hsw */
6940         I915_WRITE(CHICKEN_PAR1_1,
6941                    I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
6942
6943         lpt_init_clock_gating(dev);
6944 }
6945
6946 static void ivybridge_init_clock_gating(struct drm_device *dev)
6947 {
6948         struct drm_i915_private *dev_priv = dev->dev_private;
6949         uint32_t snpcr;
6950
6951         ilk_init_lp_watermarks(dev);
6952
6953         I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6954
6955         /* WaDisableEarlyCull:ivb */
6956         I915_WRITE(_3D_CHICKEN3,
6957                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6958
6959         /* WaDisableBackToBackFlipFix:ivb */
6960         I915_WRITE(IVB_CHICKEN3,
6961                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6962                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
6963
6964         /* WaDisablePSDDualDispatchEnable:ivb */
6965         if (IS_IVB_GT1(dev))
6966                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6967                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
6968
6969         /* WaDisable_RenderCache_OperationalFlush:ivb */
6970         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6971
6972         /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6973         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
6974                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
6975
6976         /* WaApplyL3ControlAndL3ChickenMode:ivb */
6977         I915_WRITE(GEN7_L3CNTLREG1,
6978                         GEN7_WA_FOR_GEN7_L3_CONTROL);
6979         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
6980                    GEN7_WA_L3_CHICKEN_MODE);
6981         if (IS_IVB_GT1(dev))
6982                 I915_WRITE(GEN7_ROW_CHICKEN2,
6983                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6984         else {
6985                 /* must write both registers */
6986                 I915_WRITE(GEN7_ROW_CHICKEN2,
6987                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6988                 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
6989                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6990         }
6991
6992         /* WaForceL3Serialization:ivb */
6993         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6994                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6995
6996         /*
6997          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
6998          * This implements the WaDisableRCZUnitClockGating:ivb workaround.
6999          */
7000         I915_WRITE(GEN6_UCGCTL2,
7001                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
7002
7003         /* This is required by WaCatErrorRejectionIssue:ivb */
7004         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7005                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7006                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7007
7008         g4x_disable_trickle_feed(dev);
7009
7010         gen7_setup_fixed_func_scheduler(dev_priv);
7011
7012         if (0) { /* causes HiZ corruption on ivb:gt1 */
7013                 /* enable HiZ Raw Stall Optimization */
7014                 I915_WRITE(CACHE_MODE_0_GEN7,
7015                            _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7016         }
7017
7018         /* WaDisable4x2SubspanOptimization:ivb */
7019         I915_WRITE(CACHE_MODE_1,
7020                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7021
7022         /*
7023          * BSpec recommends 8x4 when MSAA is used,
7024          * however in practice 16x4 seems fastest.
7025          *
7026          * Note that PS/WM thread counts depend on the WIZ hashing
7027          * disable bit, which we don't touch here, but it's good
7028          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7029          */
7030         I915_WRITE(GEN7_GT_MODE,
7031                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7032
7033         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
7034         snpcr &= ~GEN6_MBC_SNPCR_MASK;
7035         snpcr |= GEN6_MBC_SNPCR_MED;
7036         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
7037
7038         if (!HAS_PCH_NOP(dev))
7039                 cpt_init_clock_gating(dev);
7040
7041         gen6_check_mch_setup(dev);
7042 }
7043
7044 static void valleyview_init_clock_gating(struct drm_device *dev)
7045 {
7046         struct drm_i915_private *dev_priv = dev->dev_private;
7047
7048         /* WaDisableEarlyCull:vlv */
7049         I915_WRITE(_3D_CHICKEN3,
7050                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7051
7052         /* WaDisableBackToBackFlipFix:vlv */
7053         I915_WRITE(IVB_CHICKEN3,
7054                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7055                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
7056
7057         /* WaPsdDispatchEnable:vlv */
7058         /* WaDisablePSDDualDispatchEnable:vlv */
7059         I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
7060                    _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
7061                                       GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
7062
7063         /* WaDisable_RenderCache_OperationalFlush:vlv */
7064         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7065
7066         /* WaForceL3Serialization:vlv */
7067         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7068                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7069
7070         /* WaDisableDopClockGating:vlv */
7071         I915_WRITE(GEN7_ROW_CHICKEN2,
7072                    _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7073
7074         /* This is required by WaCatErrorRejectionIssue:vlv */
7075         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7076                    I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7077                    GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7078
7079         gen7_setup_fixed_func_scheduler(dev_priv);
7080
7081         /*
7082          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
7083          * This implements the WaDisableRCZUnitClockGating:vlv workaround.
7084          */
7085         I915_WRITE(GEN6_UCGCTL2,
7086                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
7087
7088         /* WaDisableL3Bank2xClockGate:vlv
7089          * Disabling L3 clock gating- MMIO 940c[25] = 1
7090          * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
7091         I915_WRITE(GEN7_UCGCTL4,
7092                    I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
7093
7094         /*
7095          * BSpec says this must be set, even though
7096          * WaDisable4x2SubspanOptimization isn't listed for VLV.
7097          */
7098         I915_WRITE(CACHE_MODE_1,
7099                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7100
7101         /*
7102          * BSpec recommends 8x4 when MSAA is used,
7103          * however in practice 16x4 seems fastest.
7104          *
7105          * Note that PS/WM thread counts depend on the WIZ hashing
7106          * disable bit, which we don't touch here, but it's good
7107          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7108          */
7109         I915_WRITE(GEN7_GT_MODE,
7110                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7111
7112         /*
7113          * WaIncreaseL3CreditsForVLVB0:vlv
7114          * This is the hardware default actually.
7115          */
7116         I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
7117
7118         /*
7119          * WaDisableVLVClockGating_VBIIssue:vlv
7120          * Disable clock gating on th GCFG unit to prevent a delay
7121          * in the reporting of vblank events.
7122          */
7123         I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
7124 }
7125
7126 static void cherryview_init_clock_gating(struct drm_device *dev)
7127 {
7128         struct drm_i915_private *dev_priv = dev->dev_private;
7129
7130         /* WaVSRefCountFullforceMissDisable:chv */
7131         /* WaDSRefCountFullforceMissDisable:chv */
7132         I915_WRITE(GEN7_FF_THREAD_MODE,
7133                    I915_READ(GEN7_FF_THREAD_MODE) &
7134                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
7135
7136         /* WaDisableSemaphoreAndSyncFlipWait:chv */
7137         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7138                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
7139
7140         /* WaDisableCSUnitClockGating:chv */
7141         I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7142                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
7143
7144         /* WaDisableSDEUnitClockGating:chv */
7145         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7146                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
7147
7148         /*
7149          * WaProgramL3SqcReg1Default:chv
7150          * See gfxspecs/Related Documents/Performance Guide/
7151          * LSQC Setting Recommendations.
7152          */
7153         gen8_set_l3sqc_credits(dev_priv, 38, 2);
7154
7155         /*
7156          * GTT cache may not work with big pages, so if those
7157          * are ever enabled GTT cache may need to be disabled.
7158          */
7159         I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
7160 }
7161
7162 static void g4x_init_clock_gating(struct drm_device *dev)
7163 {
7164         struct drm_i915_private *dev_priv = dev->dev_private;
7165         uint32_t dspclk_gate;
7166
7167         I915_WRITE(RENCLK_GATE_D1, 0);
7168         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7169                    GS_UNIT_CLOCK_GATE_DISABLE |
7170                    CL_UNIT_CLOCK_GATE_DISABLE);
7171         I915_WRITE(RAMCLK_GATE_D, 0);
7172         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7173                 OVRUNIT_CLOCK_GATE_DISABLE |
7174                 OVCUNIT_CLOCK_GATE_DISABLE;
7175         if (IS_GM45(dev))
7176                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7177         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
7178
7179         /* WaDisableRenderCachePipelinedFlush */
7180         I915_WRITE(CACHE_MODE_0,
7181                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
7182
7183         /* WaDisable_RenderCache_OperationalFlush:g4x */
7184         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7185
7186         g4x_disable_trickle_feed(dev);
7187 }
7188
7189 static void crestline_init_clock_gating(struct drm_device *dev)
7190 {
7191         struct drm_i915_private *dev_priv = dev->dev_private;
7192
7193         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7194         I915_WRITE(RENCLK_GATE_D2, 0);
7195         I915_WRITE(DSPCLK_GATE_D, 0);
7196         I915_WRITE(RAMCLK_GATE_D, 0);
7197         I915_WRITE16(DEUC, 0);
7198         I915_WRITE(MI_ARB_STATE,
7199                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7200
7201         /* WaDisable_RenderCache_OperationalFlush:gen4 */
7202         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7203 }
7204
7205 static void broadwater_init_clock_gating(struct drm_device *dev)
7206 {
7207         struct drm_i915_private *dev_priv = dev->dev_private;
7208
7209         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7210                    I965_RCC_CLOCK_GATE_DISABLE |
7211                    I965_RCPB_CLOCK_GATE_DISABLE |
7212                    I965_ISC_CLOCK_GATE_DISABLE |
7213                    I965_FBC_CLOCK_GATE_DISABLE);
7214         I915_WRITE(RENCLK_GATE_D2, 0);
7215         I915_WRITE(MI_ARB_STATE,
7216                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7217
7218         /* WaDisable_RenderCache_OperationalFlush:gen4 */
7219         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7220 }
7221
7222 static void gen3_init_clock_gating(struct drm_device *dev)
7223 {
7224         struct drm_i915_private *dev_priv = dev->dev_private;
7225         u32 dstate = I915_READ(D_STATE);
7226
7227         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7228                 DSTATE_DOT_CLOCK_GATING;
7229         I915_WRITE(D_STATE, dstate);
7230
7231         if (IS_PINEVIEW(dev))
7232                 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
7233
7234         /* IIR "flip pending" means done if this bit is set */
7235         I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
7236
7237         /* interrupts should cause a wake up from C3 */
7238         I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
7239
7240         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
7241         I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
7242
7243         I915_WRITE(MI_ARB_STATE,
7244                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7245 }
7246
7247 static void i85x_init_clock_gating(struct drm_device *dev)
7248 {
7249         struct drm_i915_private *dev_priv = dev->dev_private;
7250
7251         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
7252
7253         /* interrupts should cause a wake up from C3 */
7254         I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
7255                    _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
7256
7257         I915_WRITE(MEM_MODE,
7258                    _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
7259 }
7260
7261 static void i830_init_clock_gating(struct drm_device *dev)
7262 {
7263         struct drm_i915_private *dev_priv = dev->dev_private;
7264
7265         I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
7266
7267         I915_WRITE(MEM_MODE,
7268                    _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
7269                    _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
7270 }
7271
7272 void intel_init_clock_gating(struct drm_device *dev)
7273 {
7274         struct drm_i915_private *dev_priv = dev->dev_private;
7275
7276         dev_priv->display.init_clock_gating(dev);
7277 }
7278
7279 void intel_suspend_hw(struct drm_device *dev)
7280 {
7281         if (HAS_PCH_LPT(dev))
7282                 lpt_suspend_hw(dev);
7283 }
7284
7285 static void nop_init_clock_gating(struct drm_device *dev)
7286 {
7287         DRM_DEBUG_KMS("No clock gating settings or workarounds applied.\n");
7288 }
7289
7290 /**
7291  * intel_init_clock_gating_hooks - setup the clock gating hooks
7292  * @dev_priv: device private
7293  *
7294  * Setup the hooks that configure which clocks of a given platform can be
7295  * gated and also apply various GT and display specific workarounds for these
7296  * platforms. Note that some GT specific workarounds are applied separately
7297  * when GPU contexts or batchbuffers start their execution.
7298  */
7299 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
7300 {
7301         if (IS_SKYLAKE(dev_priv))
7302                 dev_priv->display.init_clock_gating = skylake_init_clock_gating;
7303         else if (IS_KABYLAKE(dev_priv))
7304                 dev_priv->display.init_clock_gating = skylake_init_clock_gating;
7305         else if (IS_BROXTON(dev_priv))
7306                 dev_priv->display.init_clock_gating = bxt_init_clock_gating;
7307         else if (IS_BROADWELL(dev_priv))
7308                 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
7309         else if (IS_CHERRYVIEW(dev_priv))
7310                 dev_priv->display.init_clock_gating = cherryview_init_clock_gating;
7311         else if (IS_HASWELL(dev_priv))
7312                 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
7313         else if (IS_IVYBRIDGE(dev_priv))
7314                 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7315         else if (IS_VALLEYVIEW(dev_priv))
7316                 dev_priv->display.init_clock_gating = valleyview_init_clock_gating;
7317         else if (IS_GEN6(dev_priv))
7318                 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7319         else if (IS_GEN5(dev_priv))
7320                 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7321         else if (IS_G4X(dev_priv))
7322                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7323         else if (IS_CRESTLINE(dev_priv))
7324                 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7325         else if (IS_BROADWATER(dev_priv))
7326                 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7327         else if (IS_GEN3(dev_priv))
7328                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7329         else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
7330                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7331         else if (IS_GEN2(dev_priv))
7332                 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7333         else {
7334                 MISSING_CASE(INTEL_DEVID(dev_priv));
7335                 dev_priv->display.init_clock_gating = nop_init_clock_gating;
7336         }
7337 }
7338
7339 /* Set up chip specific power management-related functions */
7340 void intel_init_pm(struct drm_device *dev)
7341 {
7342         struct drm_i915_private *dev_priv = dev->dev_private;
7343
7344         intel_fbc_init(dev_priv);
7345
7346         /* For cxsr */
7347         if (IS_PINEVIEW(dev))
7348                 i915_pineview_get_mem_freq(dev);
7349         else if (IS_GEN5(dev))
7350                 i915_ironlake_get_mem_freq(dev);
7351
7352         /* For FIFO watermark updates */
7353         if (INTEL_INFO(dev)->gen >= 9) {
7354                 skl_setup_wm_latency(dev);
7355                 dev_priv->display.update_wm = skl_update_wm;
7356                 dev_priv->display.compute_global_watermarks = skl_compute_wm;
7357         } else if (HAS_PCH_SPLIT(dev)) {
7358                 ilk_setup_wm_latency(dev);
7359
7360                 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
7361                      dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7362                     (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
7363                      dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
7364                         dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
7365                         dev_priv->display.compute_intermediate_wm =
7366                                 ilk_compute_intermediate_wm;
7367                         dev_priv->display.initial_watermarks =
7368                                 ilk_initial_watermarks;
7369                         dev_priv->display.optimize_watermarks =
7370                                 ilk_optimize_watermarks;
7371                 } else {
7372                         DRM_DEBUG_KMS("Failed to read display plane latency. "
7373                                       "Disable CxSR\n");
7374                 }
7375         } else if (IS_CHERRYVIEW(dev)) {
7376                 vlv_setup_wm_latency(dev);
7377                 dev_priv->display.update_wm = vlv_update_wm;
7378         } else if (IS_VALLEYVIEW(dev)) {
7379                 vlv_setup_wm_latency(dev);
7380                 dev_priv->display.update_wm = vlv_update_wm;
7381         } else if (IS_PINEVIEW(dev)) {
7382                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7383                                             dev_priv->is_ddr3,
7384                                             dev_priv->fsb_freq,
7385                                             dev_priv->mem_freq)) {
7386                         DRM_INFO("failed to find known CxSR latency "
7387                                  "(found ddr%s fsb freq %d, mem freq %d), "
7388                                  "disabling CxSR\n",
7389                                  (dev_priv->is_ddr3 == 1) ? "3" : "2",
7390                                  dev_priv->fsb_freq, dev_priv->mem_freq);
7391                         /* Disable CxSR and never update its watermark again */
7392                         intel_set_memory_cxsr(dev_priv, false);
7393                         dev_priv->display.update_wm = NULL;
7394                 } else
7395                         dev_priv->display.update_wm = pineview_update_wm;
7396         } else if (IS_G4X(dev)) {
7397                 dev_priv->display.update_wm = g4x_update_wm;
7398         } else if (IS_GEN4(dev)) {
7399                 dev_priv->display.update_wm = i965_update_wm;
7400         } else if (IS_GEN3(dev)) {
7401                 dev_priv->display.update_wm = i9xx_update_wm;
7402                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7403         } else if (IS_GEN2(dev)) {
7404                 if (INTEL_INFO(dev)->num_pipes == 1) {
7405                         dev_priv->display.update_wm = i845_update_wm;
7406                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
7407                 } else {
7408                         dev_priv->display.update_wm = i9xx_update_wm;
7409                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
7410                 }
7411         } else {
7412                 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
7413         }
7414 }
7415
7416 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
7417 {
7418         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7419
7420         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7421                 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7422                 return -EAGAIN;
7423         }
7424
7425         I915_WRITE(GEN6_PCODE_DATA, *val);
7426         I915_WRITE(GEN6_PCODE_DATA1, 0);
7427         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7428
7429         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7430                      500)) {
7431                 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7432                 return -ETIMEDOUT;
7433         }
7434
7435         *val = I915_READ(GEN6_PCODE_DATA);
7436         I915_WRITE(GEN6_PCODE_DATA, 0);
7437
7438         return 0;
7439 }
7440
7441 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val)
7442 {
7443         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7444
7445         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7446                 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7447                 return -EAGAIN;
7448         }
7449
7450         I915_WRITE(GEN6_PCODE_DATA, val);
7451         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7452
7453         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7454                      500)) {
7455                 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7456                 return -ETIMEDOUT;
7457         }
7458
7459         I915_WRITE(GEN6_PCODE_DATA, 0);
7460
7461         return 0;
7462 }
7463
7464 static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7465 {
7466         /*
7467          * N = val - 0xb7
7468          * Slow = Fast = GPLL ref * N
7469          */
7470         return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * (val - 0xb7), 1000);
7471 }
7472
7473 static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
7474 {
7475         return DIV_ROUND_CLOSEST(1000 * val, dev_priv->rps.gpll_ref_freq) + 0xb7;
7476 }
7477
7478 static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
7479 {
7480         /*
7481          * N = val / 2
7482          * CU (slow) = CU2x (fast) / 2 = GPLL ref * N / 2
7483          */
7484         return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * val, 2 * 2 * 1000);
7485 }
7486
7487 static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
7488 {
7489         /* CHV needs even values */
7490         return DIV_ROUND_CLOSEST(2 * 1000 * val, dev_priv->rps.gpll_ref_freq) * 2;
7491 }
7492
7493 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
7494 {
7495         if (IS_GEN9(dev_priv))
7496                 return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
7497                                          GEN9_FREQ_SCALER);
7498         else if (IS_CHERRYVIEW(dev_priv))
7499                 return chv_gpu_freq(dev_priv, val);
7500         else if (IS_VALLEYVIEW(dev_priv))
7501                 return byt_gpu_freq(dev_priv, val);
7502         else
7503                 return val * GT_FREQUENCY_MULTIPLIER;
7504 }
7505
7506 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
7507 {
7508         if (IS_GEN9(dev_priv))
7509                 return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
7510                                          GT_FREQUENCY_MULTIPLIER);
7511         else if (IS_CHERRYVIEW(dev_priv))
7512                 return chv_freq_opcode(dev_priv, val);
7513         else if (IS_VALLEYVIEW(dev_priv))
7514                 return byt_freq_opcode(dev_priv, val);
7515         else
7516                 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
7517 }
7518
7519 struct request_boost {
7520         struct work_struct work;
7521         struct drm_i915_gem_request *req;
7522 };
7523
7524 static void __intel_rps_boost_work(struct work_struct *work)
7525 {
7526         struct request_boost *boost = container_of(work, struct request_boost, work);
7527         struct drm_i915_gem_request *req = boost->req;
7528
7529         if (!i915_gem_request_completed(req, true))
7530                 gen6_rps_boost(req->i915, NULL, req->emitted_jiffies);
7531
7532         i915_gem_request_unreference(req);
7533         kfree(boost);
7534 }
7535
7536 void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req)
7537 {
7538         struct request_boost *boost;
7539
7540         if (req == NULL || INTEL_GEN(req->i915) < 6)
7541                 return;
7542
7543         if (i915_gem_request_completed(req, true))
7544                 return;
7545
7546         boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
7547         if (boost == NULL)
7548                 return;
7549
7550         i915_gem_request_reference(req);
7551         boost->req = req;
7552
7553         INIT_WORK(&boost->work, __intel_rps_boost_work);
7554         queue_work(req->i915->wq, &boost->work);
7555 }
7556
7557 void intel_pm_setup(struct drm_device *dev)
7558 {
7559         struct drm_i915_private *dev_priv = dev->dev_private;
7560
7561         mutex_init(&dev_priv->rps.hw_lock);
7562         spin_lock_init(&dev_priv->rps.client_lock);
7563
7564         INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
7565                           intel_gen6_powersave_work);
7566         INIT_LIST_HEAD(&dev_priv->rps.clients);
7567         INIT_LIST_HEAD(&dev_priv->rps.semaphores.link);
7568         INIT_LIST_HEAD(&dev_priv->rps.mmioflips.link);
7569
7570         dev_priv->pm.suspended = false;
7571         atomic_set(&dev_priv->pm.wakeref_count, 0);
7572         atomic_set(&dev_priv->pm.atomic_seq, 0);
7573 }