drivers/gpu/drm/i915/intel_psr.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 /**
  25  * DOC: Panel Self Refresh (PSR/SRD)
  26  *
  27  * Since Haswell Display controller supports Panel Self-Refresh on display
  28  * panels witch have a remote frame buffer (RFB) implemented according to PSR
  29  * spec in eDP1.3. PSR feature allows the display to go to lower standby states
  30  * when system is idle but display is on as it eliminates display refresh
  31  * request to DDR memory completely as long as the frame buffer for that
  32  * display is unchanged.
  33  *
  34  * Panel Self Refresh must be supported by both Hardware (source) and
  35  * Panel (sink).
  36  *
  37  * PSR saves power by caching the framebuffer in the panel RFB, which allows us
  38  * to power down the link and memory controller. For DSI panels the same idea
  39  * is called "manual mode".
  40  *
  41  * The implementation uses the hardware-based PSR support which automatically
  42  * enters/exits self-refresh mode. The hardware takes care of sending the
  43  * required DP aux message and could even retrain the link (that part isn't
  44  * enabled yet though). The hardware also keeps track of any frontbuffer
  45  * changes to know when to exit self-refresh mode again. Unfortunately that
  46  * part doesn't work too well, hence why the i915 PSR support uses the
  47  * software frontbuffer tracking to make sure it doesn't miss a screen
  48  * update. For this integration intel_psr_invalidate() and intel_psr_flush()
  49  * get called by the frontbuffer tracking code. Note that because of locking
  50  * issues the self-refresh re-enable code is done from a work queue, which
  51  * must be correctly synchronized/cancelled when shutting down the pipe."
  52  */
  53
  54 #include <drm/drmP.h>
  55
  56 #include "intel_drv.h"
  57 #include "i915_drv.h"
  58
  59 static bool is_edp_psr(struct intel_dp *intel_dp)
  60 {
  61         return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
  62 }
  63
  64 static bool vlv_is_psr_active_on_pipe(struct drm_device *dev, int pipe)
  65 {
  66         struct drm_i915_private *dev_priv = dev->dev_private;
  67         uint32_t val;
  68
  69         val = I915_READ(VLV_PSRSTAT(pipe)) &
  70               VLV_EDP_PSR_CURR_STATE_MASK;
  71         return (val == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
  72                (val == VLV_EDP_PSR_ACTIVE_SF_UPDATE);
  73 }
  74
  75 static void intel_psr_write_vsc(struct intel_dp *intel_dp,
  76                                 const struct edp_vsc_psr *vsc_psr)
  77 {
  78         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
  79         struct drm_device *dev = dig_port->base.base.dev;
  80         struct drm_i915_private *dev_priv = dev->dev_private;
  81         struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
  82         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
  83         i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
  84         uint32_t *data = (uint32_t *) vsc_psr;
  85         unsigned int i;
  86
  87         /* As per BSPec (Pipe Video Data Island Packet), we need to disable
  88            the video DIP being updated before program video DIP data buffer
  89            registers for DIP being updated. */
  90         I915_WRITE(ctl_reg, 0);
  91         POSTING_READ(ctl_reg);
  92
  93         for (i = 0; i < sizeof(*vsc_psr); i += 4) {
  94                 I915_WRITE(HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder,
  95                                                    i >> 2), *data);
  96                 data++;
  97         }
  98         for (; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4)
  99                 I915_WRITE(HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder,
 100                                                    i >> 2), 0);
 101
 102         I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
 103         POSTING_READ(ctl_reg);
 104 }
 105
 106 static void vlv_psr_setup_vsc(struct intel_dp *intel_dp)
 107 {
 108         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 109         struct drm_device *dev = intel_dig_port->base.base.dev;
 110         struct drm_i915_private *dev_priv = dev->dev_private;
 111         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
 112         enum pipe pipe = to_intel_crtc(crtc)->pipe;
 113         uint32_t val;
 114
 115         /* VLV auto-generate VSC package as per EDP 1.3 spec, Table 3.10 */
 116         val  = I915_READ(VLV_VSCSDP(pipe));
 117         val &= ~VLV_EDP_PSR_SDP_FREQ_MASK;
 118         val |= VLV_EDP_PSR_SDP_FREQ_EVFRAME;
 119         I915_WRITE(VLV_VSCSDP(pipe), val);
 120 }
 121
 122 static void skl_psr_setup_su_vsc(struct intel_dp *intel_dp)
 123 {
 124         struct edp_vsc_psr psr_vsc;
 125
 126         /* Prepare VSC Header for SU as per EDP 1.4 spec, Table 6.11 */
 127         memset(&psr_vsc, 0, sizeof(psr_vsc));
 128         psr_vsc.sdp_header.HB0 = 0;
 129         psr_vsc.sdp_header.HB1 = 0x7;
 130         psr_vsc.sdp_header.HB2 = 0x3;
 131         psr_vsc.sdp_header.HB3 = 0xb;
 132         intel_psr_write_vsc(intel_dp, &psr_vsc);
 133 }
 134
 135 static void hsw_psr_setup_vsc(struct intel_dp *intel_dp)
 136 {
 137         struct edp_vsc_psr psr_vsc;
 138
 139         /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
 140         memset(&psr_vsc, 0, sizeof(psr_vsc));
 141         psr_vsc.sdp_header.HB0 = 0;
 142         psr_vsc.sdp_header.HB1 = 0x7;
 143         psr_vsc.sdp_header.HB2 = 0x2;
 144         psr_vsc.sdp_header.HB3 = 0x8;
 145         intel_psr_write_vsc(intel_dp, &psr_vsc);
 146 }
 147
 148 static void vlv_psr_enable_sink(struct intel_dp *intel_dp)
 149 {
 150         drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
 151                            DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
 152 }
 153
 154 static i915_reg_t psr_aux_ctl_reg(struct drm_i915_private *dev_priv,
 155                                        enum port port)
 156 {
 157         if (INTEL_INFO(dev_priv)->gen >= 9)
 158                 return DP_AUX_CH_CTL(port);
 159         else
 160                 return EDP_PSR_AUX_CTL;
 161 }
 162
 163 static i915_reg_t psr_aux_data_reg(struct drm_i915_private *dev_priv,
 164                                         enum port port, int index)
 165 {
 166         if (INTEL_INFO(dev_priv)->gen >= 9)
 167                 return DP_AUX_CH_DATA(port, index);
 168         else
 169                 return EDP_PSR_AUX_DATA(index);
 170 }
 171
 172 static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
 173 {
 174         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 175         struct drm_device *dev = dig_port->base.base.dev;
 176         struct drm_i915_private *dev_priv = dev->dev_private;
 177         uint32_t aux_clock_divider;
 178         i915_reg_t aux_ctl_reg;
 179         int precharge = 0x3;
 180         static const uint8_t aux_msg[] = {
 181                 [0] = DP_AUX_NATIVE_WRITE << 4,
 182                 [1] = DP_SET_POWER >> 8,
 183                 [2] = DP_SET_POWER & 0xff,
 184                 [3] = 1 - 1,
 185                 [4] = DP_SET_POWER_D0,
 186         };
 187         enum port port = dig_port->port;
 188         int i;
 189
 190         BUILD_BUG_ON(sizeof(aux_msg) > 20);
 191
 192         aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
 193
 194         /* Enable AUX frame sync at sink */
 195         if (dev_priv->psr.aux_frame_sync)
 196                 drm_dp_dpcd_writeb(&intel_dp->aux,
 197                                 DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF,
 198                                 DP_AUX_FRAME_SYNC_ENABLE);
 199
 200         aux_ctl_reg = psr_aux_ctl_reg(dev_priv, port);
 201
 202         /* Setup AUX registers */
 203         for (i = 0; i < sizeof(aux_msg); i += 4)
 204                 I915_WRITE(psr_aux_data_reg(dev_priv, port, i >> 2),
 205                            intel_dp_pack_aux(&aux_msg[i], sizeof(aux_msg) - i));
 206
 207         if (INTEL_INFO(dev)->gen >= 9) {
 208                 uint32_t val;
 209
 210                 val = I915_READ(aux_ctl_reg);
 211                 val &= ~DP_AUX_CH_CTL_TIME_OUT_MASK;
 212                 val |= DP_AUX_CH_CTL_TIME_OUT_1600us;
 213                 val &= ~DP_AUX_CH_CTL_MESSAGE_SIZE_MASK;
 214                 val |= (sizeof(aux_msg) << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
 215                 /* Use hardcoded data values for PSR, frame sync and GTC */
 216                 val &= ~DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL;
 217                 val &= ~DP_AUX_CH_CTL_FS_DATA_AUX_REG_SKL;
 218                 val &= ~DP_AUX_CH_CTL_GTC_DATA_AUX_REG_SKL;
 219                 I915_WRITE(aux_ctl_reg, val);
 220         } else {
 221                 I915_WRITE(aux_ctl_reg,
 222                    DP_AUX_CH_CTL_TIME_OUT_400us |
 223                    (sizeof(aux_msg) << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 224                    (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 225                    (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
 226         }
 227
 228         drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, DP_PSR_ENABLE);
 229 }
 230
 231 static void vlv_psr_enable_source(struct intel_dp *intel_dp)
 232 {
 233         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 234         struct drm_device *dev = dig_port->base.base.dev;
 235         struct drm_i915_private *dev_priv = dev->dev_private;
 236         struct drm_crtc *crtc = dig_port->base.base.crtc;
 237         enum pipe pipe = to_intel_crtc(crtc)->pipe;
 238
 239         /* Transition from PSR_state 0 to PSR_state 1, i.e. PSR Inactive */
 240         I915_WRITE(VLV_PSRCTL(pipe),
 241                    VLV_EDP_PSR_MODE_SW_TIMER |
 242                    VLV_EDP_PSR_SRC_TRANSMITTER_STATE |
 243                    VLV_EDP_PSR_ENABLE);
 244 }
 245
 246 static void vlv_psr_activate(struct intel_dp *intel_dp)
 247 {
 248         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 249         struct drm_device *dev = dig_port->base.base.dev;
 250         struct drm_i915_private *dev_priv = dev->dev_private;
 251         struct drm_crtc *crtc = dig_port->base.base.crtc;
 252         enum pipe pipe = to_intel_crtc(crtc)->pipe;
 253
 254         /* Let's do the transition from PSR_state 1 to PSR_state 2
 255          * that is PSR transition to active - static frame transmission.
 256          * Then Hardware is responsible for the transition to PSR_state 3
 257          * that is PSR active - no Remote Frame Buffer (RFB) update.
 258          */
 259         I915_WRITE(VLV_PSRCTL(pipe), I915_READ(VLV_PSRCTL(pipe)) |
 260                    VLV_EDP_PSR_ACTIVE_ENTRY);
 261 }
 262
 263 static void hsw_psr_enable_source(struct intel_dp *intel_dp)
 264 {
 265         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 266         struct drm_device *dev = dig_port->base.base.dev;
 267         struct drm_i915_private *dev_priv = dev->dev_private;
 268
 269         uint32_t max_sleep_time = 0x1f;
 270         /* Lately it was identified that depending on panel idle frame count
 271          * calculated at HW can be off by 1. So let's use what came
 272          * from VBT + 1.
 273          * There are also other cases where panel demands at least 4
 274          * but VBT is not being set. To cover these 2 cases lets use
 275          * at least 5 when VBT isn't set to be on the safest side.
 276          */
 277         uint32_t idle_frames = dev_priv->vbt.psr.idle_frames ?
 278                                dev_priv->vbt.psr.idle_frames + 1 : 5;
 279         uint32_t val = 0x0;
 280         const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
 281
 282         if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
 283                 /* Sink should be able to train with the 5 or 6 idle patterns */
 284                 idle_frames += 4;
 285         }
 286
 287         I915_WRITE(EDP_PSR_CTL, val |
 288                    (IS_BROADWELL(dev) ? 0 : link_entry_time) |
 289                    max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
 290                    idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
 291                    EDP_PSR_ENABLE);
 292
 293         if (dev_priv->psr.psr2_support)
 294                 I915_WRITE(EDP_PSR2_CTL, EDP_PSR2_ENABLE |
 295                                 EDP_SU_TRACK_ENABLE | EDP_PSR2_TP2_TIME_100);
 296 }
 297
 298 static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
 299 {
 300         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 301         struct drm_device *dev = dig_port->base.base.dev;
 302         struct drm_i915_private *dev_priv = dev->dev_private;
 303         struct drm_crtc *crtc = dig_port->base.base.crtc;
 304         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 305
 306         lockdep_assert_held(&dev_priv->psr.lock);
 307         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
 308         WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
 309
 310         dev_priv->psr.source_ok = false;
 311
 312         if (IS_HASWELL(dev) && dig_port->port != PORT_A) {
 313                 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
 314                 return false;
 315         }
 316
 317         if (!i915.enable_psr) {
 318                 DRM_DEBUG_KMS("PSR disable by flag\n");
 319                 return false;
 320         }
 321
 322         if (IS_HASWELL(dev) &&
 323             I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config->cpu_transcoder)) &
 324                       S3D_ENABLE) {
 325                 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
 326                 return false;
 327         }
 328
 329         if (IS_HASWELL(dev) &&
 330             intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
 331                 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
 332                 return false;
 333         }
 334
 335         if (!IS_VALLEYVIEW(dev) && ((dev_priv->vbt.psr.full_link) ||
 336                                     (dig_port->port != PORT_A))) {
 337                 DRM_DEBUG_KMS("PSR condition failed: Link Standby requested/needed but not supported on this platform\n");
 338                 return false;
 339         }
 340
 341         dev_priv->psr.source_ok = true;
 342         return true;
 343 }
 344
 345 static void intel_psr_activate(struct intel_dp *intel_dp)
 346 {
 347         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 348         struct drm_device *dev = intel_dig_port->base.base.dev;
 349         struct drm_i915_private *dev_priv = dev->dev_private;
 350
 351         WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE);
 352         WARN_ON(dev_priv->psr.active);
 353         lockdep_assert_held(&dev_priv->psr.lock);
 354
 355         /* Enable/Re-enable PSR on the host */
 356         if (HAS_DDI(dev))
 357                 /* On HSW+ after we enable PSR on source it will activate it
 358                  * as soon as it match configure idle_frame count. So
 359                  * we just actually enable it here on activation time.
 360                  */
 361                 hsw_psr_enable_source(intel_dp);
 362         else
 363                 vlv_psr_activate(intel_dp);
 364
 365         dev_priv->psr.active = true;
 366 }
 367
 368 /**
 369  * intel_psr_enable - Enable PSR
 370  * @intel_dp: Intel DP
 371  *
 372  * This function can only be called after the pipe is fully trained and enabled.
 373  */
 374 void intel_psr_enable(struct intel_dp *intel_dp)
 375 {
 376         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 377         struct drm_device *dev = intel_dig_port->base.base.dev;
 378         struct drm_i915_private *dev_priv = dev->dev_private;
 379         struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
 380
 381         if (!HAS_PSR(dev)) {
 382                 DRM_DEBUG_KMS("PSR not supported on this platform\n");
 383                 return;
 384         }
 385
 386         if (!is_edp_psr(intel_dp)) {
 387                 DRM_DEBUG_KMS("PSR not supported by this panel\n");
 388                 return;
 389         }
 390
 391         mutex_lock(&dev_priv->psr.lock);
 392         if (dev_priv->psr.enabled) {
 393                 DRM_DEBUG_KMS("PSR already in use\n");
 394                 goto unlock;
 395         }
 396
 397         if (!intel_psr_match_conditions(intel_dp))
 398                 goto unlock;
 399
 400         dev_priv->psr.busy_frontbuffer_bits = 0;
 401
 402         if (HAS_DDI(dev)) {
 403                 hsw_psr_setup_vsc(intel_dp);
 404
 405                 if (dev_priv->psr.psr2_support) {
 406                         /* PSR2 is restricted to work with panel resolutions upto 3200x2000 */
 407                         if (crtc->config->pipe_src_w > 3200 ||
 408                                 crtc->config->pipe_src_h > 2000)
 409                                 dev_priv->psr.psr2_support = false;
 410                         else
 411                                 skl_psr_setup_su_vsc(intel_dp);
 412                 }
 413
 414                 /*
 415                  * Per Spec: Avoid continuous PSR exit by masking MEMUP and HPD.
 416                  * Also mask LPSP to avoid dependency on other drivers that
 417                  * might block runtime_pm besides preventing other hw tracking
 418                  * issues now we can rely on frontbuffer tracking.
 419                  */
 420                 I915_WRITE(EDP_PSR_DEBUG_CTL, EDP_PSR_DEBUG_MASK_MEMUP |
 421                            EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
 422
 423                 /* Enable PSR on the panel */
 424                 hsw_psr_enable_sink(intel_dp);
 425
 426                 if (INTEL_INFO(dev)->gen >= 9)
 427                         intel_psr_activate(intel_dp);
 428         } else {
 429                 vlv_psr_setup_vsc(intel_dp);
 430
 431                 /* Enable PSR on the panel */
 432                 vlv_psr_enable_sink(intel_dp);
 433
 434                 /* On HSW+ enable_source also means go to PSR entry/active
 435                  * state as soon as idle_frame achieved and here would be
 436                  * to soon. However on VLV enable_source just enable PSR
 437                  * but let it on inactive state. So we might do this prior
 438                  * to active transition, i.e. here.
 439                  */
 440                 vlv_psr_enable_source(intel_dp);
 441         }
 442
 443         /*
 444          * FIXME: Activation should happen immediately since this function
 445          * is just called after pipe is fully trained and enabled.
 446          * However on every platform we face issues when first activation
 447          * follows a modeset so quickly.
 448          *     - On VLV/CHV we get bank screen on first activation
 449          *     - On HSW/BDW we get a recoverable frozen screen until next
 450          *       exit-activate sequence.
 451          */
 452         if (INTEL_INFO(dev)->gen < 9)
 453                 schedule_delayed_work(&dev_priv->psr.work,
 454                                       msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
 455
 456         dev_priv->psr.enabled = intel_dp;
 457 unlock:
 458         mutex_unlock(&dev_priv->psr.lock);
 459 }
 460
 461 static void vlv_psr_disable(struct intel_dp *intel_dp)
 462 {
 463         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 464         struct drm_device *dev = intel_dig_port->base.base.dev;
 465         struct drm_i915_private *dev_priv = dev->dev_private;
 466         struct intel_crtc *intel_crtc =
 467                 to_intel_crtc(intel_dig_port->base.base.crtc);
 468         uint32_t val;
 469
 470         if (dev_priv->psr.active) {
 471                 /* Put VLV PSR back to PSR_state 0 that is PSR Disabled. */
 472                 if (wait_for((I915_READ(VLV_PSRSTAT(intel_crtc->pipe)) &
 473                               VLV_EDP_PSR_IN_TRANS) == 0, 1))
 474                         WARN(1, "PSR transition took longer than expected\n");
 475
 476                 val = I915_READ(VLV_PSRCTL(intel_crtc->pipe));
 477                 val &= ~VLV_EDP_PSR_ACTIVE_ENTRY;
 478                 val &= ~VLV_EDP_PSR_ENABLE;
 479                 val &= ~VLV_EDP_PSR_MODE_MASK;
 480                 I915_WRITE(VLV_PSRCTL(intel_crtc->pipe), val);
 481
 482                 dev_priv->psr.active = false;
 483         } else {
 484                 WARN_ON(vlv_is_psr_active_on_pipe(dev, intel_crtc->pipe));
 485         }
 486 }
 487
 488 static void hsw_psr_disable(struct intel_dp *intel_dp)
 489 {
 490         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 491         struct drm_device *dev = intel_dig_port->base.base.dev;
 492         struct drm_i915_private *dev_priv = dev->dev_private;
 493
 494         if (dev_priv->psr.active) {
 495                 I915_WRITE(EDP_PSR_CTL,
 496                            I915_READ(EDP_PSR_CTL) & ~EDP_PSR_ENABLE);
 497
 498                 /* Wait till PSR is idle */
 499                 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL) &
 500                                EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
 501                         DRM_ERROR("Timed out waiting for PSR Idle State\n");
 502
 503                 dev_priv->psr.active = false;
 504         } else {
 505                 WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE);
 506         }
 507 }
 508
 509 /**
 510  * intel_psr_disable - Disable PSR
 511  * @intel_dp: Intel DP
 512  *
 513  * This function needs to be called before disabling pipe.
 514  */
 515 void intel_psr_disable(struct intel_dp *intel_dp)
 516 {
 517         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 518         struct drm_device *dev = intel_dig_port->base.base.dev;
 519         struct drm_i915_private *dev_priv = dev->dev_private;
 520
 521         mutex_lock(&dev_priv->psr.lock);
 522         if (!dev_priv->psr.enabled) {
 523                 mutex_unlock(&dev_priv->psr.lock);
 524                 return;
 525         }
 526
 527         if (HAS_DDI(dev))
 528                 hsw_psr_disable(intel_dp);
 529         else
 530                 vlv_psr_disable(intel_dp);
 531
 532         dev_priv->psr.enabled = NULL;
 533         mutex_unlock(&dev_priv->psr.lock);
 534
 535         cancel_delayed_work_sync(&dev_priv->psr.work);
 536 }
 537
 538 static void intel_psr_work(struct work_struct *work)
 539 {
 540         struct drm_i915_private *dev_priv =
 541                 container_of(work, typeof(*dev_priv), psr.work.work);
 542         struct intel_dp *intel_dp = dev_priv->psr.enabled;
 543         struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
 544         enum pipe pipe = to_intel_crtc(crtc)->pipe;
 545
 546         /* We have to make sure PSR is ready for re-enable
 547          * otherwise it keeps disabled until next full enable/disable cycle.
 548          * PSR might take some time to get fully disabled
 549          * and be ready for re-enable.
 550          */
 551         if (HAS_DDI(dev_priv->dev)) {
 552                 if (wait_for((I915_READ(EDP_PSR_STATUS_CTL) &
 553                               EDP_PSR_STATUS_STATE_MASK) == 0, 50)) {
 554                         DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
 555                         return;
 556                 }
 557         } else {
 558                 if (wait_for((I915_READ(VLV_PSRSTAT(pipe)) &
 559                               VLV_EDP_PSR_IN_TRANS) == 0, 1)) {
 560                         DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
 561                         return;
 562                 }
 563         }
 564         mutex_lock(&dev_priv->psr.lock);
 565         intel_dp = dev_priv->psr.enabled;
 566
 567         if (!intel_dp)
 568                 goto unlock;
 569
 570         /*
 571          * The delayed work can race with an invalidate hence we need to
 572          * recheck. Since psr_flush first clears this and then reschedules we
 573          * won't ever miss a flush when bailing out here.
 574          */
 575         if (dev_priv->psr.busy_frontbuffer_bits)
 576                 goto unlock;
 577
 578         intel_psr_activate(intel_dp);
 579 unlock:
 580         mutex_unlock(&dev_priv->psr.lock);
 581 }
 582
 583 static void intel_psr_exit(struct drm_device *dev)
 584 {
 585         struct drm_i915_private *dev_priv = dev->dev_private;
 586         struct intel_dp *intel_dp = dev_priv->psr.enabled;
 587         struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
 588         enum pipe pipe = to_intel_crtc(crtc)->pipe;
 589         u32 val;
 590
 591         if (!dev_priv->psr.active)
 592                 return;
 593
 594         if (HAS_DDI(dev)) {
 595                 val = I915_READ(EDP_PSR_CTL);
 596
 597                 WARN_ON(!(val & EDP_PSR_ENABLE));
 598
 599                 I915_WRITE(EDP_PSR_CTL, val & ~EDP_PSR_ENABLE);
 600         } else {
 601                 val = I915_READ(VLV_PSRCTL(pipe));
 602
 603                 /* Here we do the transition from PSR_state 3 to PSR_state 5
 604                  * directly once PSR State 4 that is active with single frame
 605                  * update can be skipped. PSR_state 5 that is PSR exit then
 606                  * Hardware is responsible to transition back to PSR_state 1
 607                  * that is PSR inactive. Same state after
 608                  * vlv_edp_psr_enable_source.
 609                  */
 610                 val &= ~VLV_EDP_PSR_ACTIVE_ENTRY;
 611                 I915_WRITE(VLV_PSRCTL(pipe), val);
 612
 613                 /* Send AUX wake up - Spec says after transitioning to PSR
 614                  * active we have to send AUX wake up by writing 01h in DPCD
 615                  * 600h of sink device.
 616                  * XXX: This might slow down the transition, but without this
 617                  * HW doesn't complete the transition to PSR_state 1 and we
 618                  * never get the screen updated.
 619                  */
 620                 drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
 621                                    DP_SET_POWER_D0);
 622         }
 623
 624         dev_priv->psr.active = false;
 625 }
 626
 627 /**
 628  * intel_psr_single_frame_update - Single Frame Update
 629  * @dev: DRM device
 630  * @frontbuffer_bits: frontbuffer plane tracking bits
 631  *
 632  * Some platforms support a single frame update feature that is used to
 633  * send and update only one frame on Remote Frame Buffer.
 634  * So far it is only implemented for Valleyview and Cherryview because
 635  * hardware requires this to be done before a page flip.
 636  */
 637 void intel_psr_single_frame_update(struct drm_device *dev,
 638                                    unsigned frontbuffer_bits)
 639 {
 640         struct drm_i915_private *dev_priv = dev->dev_private;
 641         struct drm_crtc *crtc;
 642         enum pipe pipe;
 643         u32 val;
 644
 645         /*
 646          * Single frame update is already supported on BDW+ but it requires
 647          * many W/A and it isn't really needed.
 648          */
 649         if (!IS_VALLEYVIEW(dev))
 650                 return;
 651
 652         mutex_lock(&dev_priv->psr.lock);
 653         if (!dev_priv->psr.enabled) {
 654                 mutex_unlock(&dev_priv->psr.lock);
 655                 return;
 656         }
 657
 658         crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
 659         pipe = to_intel_crtc(crtc)->pipe;
 660
 661         if (frontbuffer_bits & INTEL_FRONTBUFFER_ALL_MASK(pipe)) {
 662                 val = I915_READ(VLV_PSRCTL(pipe));
 663
 664                 /*
 665                  * We need to set this bit before writing registers for a flip.
 666                  * This bit will be self-clear when it gets to the PSR active state.
 667                  */
 668                 I915_WRITE(VLV_PSRCTL(pipe), val | VLV_EDP_PSR_SINGLE_FRAME_UPDATE);
 669         }
 670         mutex_unlock(&dev_priv->psr.lock);
 671 }
 672
 673 /**
 674  * intel_psr_invalidate - Invalidade PSR
 675  * @dev: DRM device
 676  * @frontbuffer_bits: frontbuffer plane tracking bits
 677  *
 678  * Since the hardware frontbuffer tracking has gaps we need to integrate
 679  * with the software frontbuffer tracking. This function gets called every
 680  * time frontbuffer rendering starts and a buffer gets dirtied. PSR must be
 681  * disabled if the frontbuffer mask contains a buffer relevant to PSR.
 682  *
 683  * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits."
 684  */
 685 void intel_psr_invalidate(struct drm_device *dev,
 686                           unsigned frontbuffer_bits)
 687 {
 688         struct drm_i915_private *dev_priv = dev->dev_private;
 689         struct drm_crtc *crtc;
 690         enum pipe pipe;
 691
 692         mutex_lock(&dev_priv->psr.lock);
 693         if (!dev_priv->psr.enabled) {
 694                 mutex_unlock(&dev_priv->psr.lock);
 695                 return;
 696         }
 697
 698         crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
 699         pipe = to_intel_crtc(crtc)->pipe;
 700
 701         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
 702         dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits;
 703
 704         if (frontbuffer_bits)
 705                 intel_psr_exit(dev);
 706
 707         mutex_unlock(&dev_priv->psr.lock);
 708 }
 709
 710 /**
 711  * intel_psr_flush - Flush PSR
 712  * @dev: DRM device
 713  * @frontbuffer_bits: frontbuffer plane tracking bits
 714  * @origin: which operation caused the flush
 715  *
 716  * Since the hardware frontbuffer tracking has gaps we need to integrate
 717  * with the software frontbuffer tracking. This function gets called every
 718  * time frontbuffer rendering has completed and flushed out to memory. PSR
 719  * can be enabled again if no other frontbuffer relevant to PSR is dirty.
 720  *
 721  * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits.
 722  */
 723 void intel_psr_flush(struct drm_device *dev,
 724                      unsigned frontbuffer_bits, enum fb_op_origin origin)
 725 {
 726         struct drm_i915_private *dev_priv = dev->dev_private;
 727         struct drm_crtc *crtc;
 728         enum pipe pipe;
 729
 730         mutex_lock(&dev_priv->psr.lock);
 731         if (!dev_priv->psr.enabled) {
 732                 mutex_unlock(&dev_priv->psr.lock);
 733                 return;
 734         }
 735
 736         crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
 737         pipe = to_intel_crtc(crtc)->pipe;
 738
 739         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
 740         dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits;
 741
 742         /* By definition flush = invalidate + flush */
 743         if (frontbuffer_bits)
 744                 intel_psr_exit(dev);
 745
 746         if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
 747                 if (!work_busy(&dev_priv->psr.work.work))
 748                         schedule_delayed_work(&dev_priv->psr.work,
 749                                               msecs_to_jiffies(100));
 750         mutex_unlock(&dev_priv->psr.lock);
 751 }
 752
 753 /**
 754  * intel_psr_init - Init basic PSR work and mutex.
 755  * @dev: DRM device
 756  *
 757  * This function is  called only once at driver load to initialize basic
 758  * PSR stuff.
 759  */
 760 void intel_psr_init(struct drm_device *dev)
 761 {
 762         struct drm_i915_private *dev_priv = dev->dev_private;
 763
 764         dev_priv->psr_mmio_base = IS_HASWELL(dev_priv) ?
 765                 HSW_EDP_PSR_BASE : BDW_EDP_PSR_BASE;
 766
 767         INIT_DELAYED_WORK(&dev_priv->psr.work, intel_psr_work);
 768         mutex_init(&dev_priv->psr.lock);
 769 }