drivers/gpu/drm/i915/intel_psr.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 /**
  25  * DOC: Panel Self Refresh (PSR/SRD)
  26  *
  27  * Since Haswell Display controller supports Panel Self-Refresh on display
  28  * panels witch have a remote frame buffer (RFB) implemented according to PSR
  29  * spec in eDP1.3. PSR feature allows the display to go to lower standby states
  30  * when system is idle but display is on as it eliminates display refresh
  31  * request to DDR memory completely as long as the frame buffer for that
  32  * display is unchanged.
  33  *
  34  * Panel Self Refresh must be supported by both Hardware (source) and
  35  * Panel (sink).
  36  *
  37  * PSR saves power by caching the framebuffer in the panel RFB, which allows us
  38  * to power down the link and memory controller. For DSI panels the same idea
  39  * is called "manual mode".
  40  *
  41  * The implementation uses the hardware-based PSR support which automatically
  42  * enters/exits self-refresh mode. The hardware takes care of sending the
  43  * required DP aux message and could even retrain the link (that part isn't
  44  * enabled yet though). The hardware also keeps track of any frontbuffer
  45  * changes to know when to exit self-refresh mode again. Unfortunately that
  46  * part doesn't work too well, hence why the i915 PSR support uses the
  47  * software frontbuffer tracking to make sure it doesn't miss a screen
  48  * update. For this integration intel_psr_invalidate() and intel_psr_flush()
  49  * get called by the frontbuffer tracking code. Note that because of locking
  50  * issues the self-refresh re-enable code is done from a work queue, which
  51  * must be correctly synchronized/cancelled when shutting down the pipe."
  52  */
  53
  54 #include <drm/drmP.h>
  55
  56 #include "intel_drv.h"
  57 #include "i915_drv.h"
  58
  59 static bool is_edp_psr(struct intel_dp *intel_dp)
  60 {
  61         return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
  62 }
  63
  64 static bool vlv_is_psr_active_on_pipe(struct drm_device *dev, int pipe)
  65 {
  66         struct drm_i915_private *dev_priv = dev->dev_private;
  67         uint32_t val;
  68
  69         val = I915_READ(VLV_PSRSTAT(pipe)) &
  70               VLV_EDP_PSR_CURR_STATE_MASK;
  71         return (val == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
  72                (val == VLV_EDP_PSR_ACTIVE_SF_UPDATE);
  73 }
  74
  75 static void intel_psr_write_vsc(struct intel_dp *intel_dp,
  76                                 const struct edp_vsc_psr *vsc_psr)
  77 {
  78         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
  79         struct drm_device *dev = dig_port->base.base.dev;
  80         struct drm_i915_private *dev_priv = dev->dev_private;
  81         struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
  82         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
  83         i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
  84         uint32_t *data = (uint32_t *) vsc_psr;
  85         unsigned int i;
  86
  87         /* As per BSPec (Pipe Video Data Island Packet), we need to disable
  88            the video DIP being updated before program video DIP data buffer
  89            registers for DIP being updated. */
  90         I915_WRITE(ctl_reg, 0);
  91         POSTING_READ(ctl_reg);
  92
  93         for (i = 0; i < sizeof(*vsc_psr); i += 4) {
  94                 I915_WRITE(HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder,
  95                                                    i >> 2), *data);
  96                 data++;
  97         }
  98         for (; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4)
  99                 I915_WRITE(HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder,
 100                                                    i >> 2), 0);
 101
 102         I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
 103         POSTING_READ(ctl_reg);
 104 }
 105
 106 static void vlv_psr_setup_vsc(struct intel_dp *intel_dp)
 107 {
 108         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 109         struct drm_device *dev = intel_dig_port->base.base.dev;
 110         struct drm_i915_private *dev_priv = dev->dev_private;
 111         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
 112         enum pipe pipe = to_intel_crtc(crtc)->pipe;
 113         uint32_t val;
 114
 115         /* VLV auto-generate VSC package as per EDP 1.3 spec, Table 3.10 */
 116         val  = I915_READ(VLV_VSCSDP(pipe));
 117         val &= ~VLV_EDP_PSR_SDP_FREQ_MASK;
 118         val |= VLV_EDP_PSR_SDP_FREQ_EVFRAME;
 119         I915_WRITE(VLV_VSCSDP(pipe), val);
 120 }
 121
 122 static void skl_psr_setup_su_vsc(struct intel_dp *intel_dp)
 123 {
 124         struct edp_vsc_psr psr_vsc;
 125
 126         /* Prepare VSC Header for SU as per EDP 1.4 spec, Table 6.11 */
 127         memset(&psr_vsc, 0, sizeof(psr_vsc));
 128         psr_vsc.sdp_header.HB0 = 0;
 129         psr_vsc.sdp_header.HB1 = 0x7;
 130         psr_vsc.sdp_header.HB2 = 0x3;
 131         psr_vsc.sdp_header.HB3 = 0xb;
 132         intel_psr_write_vsc(intel_dp, &psr_vsc);
 133 }
 134
 135 static void hsw_psr_setup_vsc(struct intel_dp *intel_dp)
 136 {
 137         struct edp_vsc_psr psr_vsc;
 138
 139         /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
 140         memset(&psr_vsc, 0, sizeof(psr_vsc));
 141         psr_vsc.sdp_header.HB0 = 0;
 142         psr_vsc.sdp_header.HB1 = 0x7;
 143         psr_vsc.sdp_header.HB2 = 0x2;
 144         psr_vsc.sdp_header.HB3 = 0x8;
 145         intel_psr_write_vsc(intel_dp, &psr_vsc);
 146 }
 147
 148 static void vlv_psr_enable_sink(struct intel_dp *intel_dp)
 149 {
 150         drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
 151                            DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
 152 }
 153
 154 static i915_reg_t psr_aux_ctl_reg(struct drm_i915_private *dev_priv,
 155                                        enum port port)
 156 {
 157         if (INTEL_INFO(dev_priv)->gen >= 9)
 158                 return DP_AUX_CH_CTL(port);
 159         else
 160                 return EDP_PSR_AUX_CTL;
 161 }
 162
 163 static i915_reg_t psr_aux_data_reg(struct drm_i915_private *dev_priv,
 164                                         enum port port, int index)
 165 {
 166         if (INTEL_INFO(dev_priv)->gen >= 9)
 167                 return DP_AUX_CH_DATA(port, index);
 168         else
 169                 return EDP_PSR_AUX_DATA(index);
 170 }
 171
 172 static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
 173 {
 174         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 175         struct drm_device *dev = dig_port->base.base.dev;
 176         struct drm_i915_private *dev_priv = dev->dev_private;
 177         uint32_t aux_clock_divider;
 178         i915_reg_t aux_ctl_reg;
 179         int precharge = 0x3;
 180         static const uint8_t aux_msg[] = {
 181                 [0] = DP_AUX_NATIVE_WRITE << 4,
 182                 [1] = DP_SET_POWER >> 8,
 183                 [2] = DP_SET_POWER & 0xff,
 184                 [3] = 1 - 1,
 185                 [4] = DP_SET_POWER_D0,
 186         };
 187         enum port port = dig_port->port;
 188         int i;
 189
 190         BUILD_BUG_ON(sizeof(aux_msg) > 20);
 191
 192         aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
 193
 194         /* Enable AUX frame sync at sink */
 195         if (dev_priv->psr.aux_frame_sync)
 196                 drm_dp_dpcd_writeb(&intel_dp->aux,
 197                                 DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF,
 198                                 DP_AUX_FRAME_SYNC_ENABLE);
 199
 200         aux_ctl_reg = psr_aux_ctl_reg(dev_priv, port);
 201
 202         /* Setup AUX registers */
 203         for (i = 0; i < sizeof(aux_msg); i += 4)
 204                 I915_WRITE(psr_aux_data_reg(dev_priv, port, i >> 2),
 205                            intel_dp_pack_aux(&aux_msg[i], sizeof(aux_msg) - i));
 206
 207         if (INTEL_INFO(dev)->gen >= 9) {
 208                 uint32_t val;
 209
 210                 val = I915_READ(aux_ctl_reg);
 211                 val &= ~DP_AUX_CH_CTL_TIME_OUT_MASK;
 212                 val |= DP_AUX_CH_CTL_TIME_OUT_1600us;
 213                 val &= ~DP_AUX_CH_CTL_MESSAGE_SIZE_MASK;
 214                 val |= (sizeof(aux_msg) << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
 215                 /* Use hardcoded data values for PSR, frame sync and GTC */
 216                 val &= ~DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL;
 217                 val &= ~DP_AUX_CH_CTL_FS_DATA_AUX_REG_SKL;
 218                 val &= ~DP_AUX_CH_CTL_GTC_DATA_AUX_REG_SKL;
 219                 I915_WRITE(aux_ctl_reg, val);
 220         } else {
 221                 I915_WRITE(aux_ctl_reg,
 222                    DP_AUX_CH_CTL_TIME_OUT_400us |
 223                    (sizeof(aux_msg) << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 224                    (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 225                    (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
 226         }
 227
 228         if (dev_priv->psr.link_standby)
 229                 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
 230                                    DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
 231         else
 232                 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
 233                                    DP_PSR_ENABLE);
 234 }
 235
 236 static void vlv_psr_enable_source(struct intel_dp *intel_dp)
 237 {
 238         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 239         struct drm_device *dev = dig_port->base.base.dev;
 240         struct drm_i915_private *dev_priv = dev->dev_private;
 241         struct drm_crtc *crtc = dig_port->base.base.crtc;
 242         enum pipe pipe = to_intel_crtc(crtc)->pipe;
 243
 244         /* Transition from PSR_state 0 to PSR_state 1, i.e. PSR Inactive */
 245         I915_WRITE(VLV_PSRCTL(pipe),
 246                    VLV_EDP_PSR_MODE_SW_TIMER |
 247                    VLV_EDP_PSR_SRC_TRANSMITTER_STATE |
 248                    VLV_EDP_PSR_ENABLE);
 249 }
 250
 251 static void vlv_psr_activate(struct intel_dp *intel_dp)
 252 {
 253         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 254         struct drm_device *dev = dig_port->base.base.dev;
 255         struct drm_i915_private *dev_priv = dev->dev_private;
 256         struct drm_crtc *crtc = dig_port->base.base.crtc;
 257         enum pipe pipe = to_intel_crtc(crtc)->pipe;
 258
 259         /* Let's do the transition from PSR_state 1 to PSR_state 2
 260          * that is PSR transition to active - static frame transmission.
 261          * Then Hardware is responsible for the transition to PSR_state 3
 262          * that is PSR active - no Remote Frame Buffer (RFB) update.
 263          */
 264         I915_WRITE(VLV_PSRCTL(pipe), I915_READ(VLV_PSRCTL(pipe)) |
 265                    VLV_EDP_PSR_ACTIVE_ENTRY);
 266 }
 267
 268 static void hsw_psr_enable_source(struct intel_dp *intel_dp)
 269 {
 270         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 271         struct drm_device *dev = dig_port->base.base.dev;
 272         struct drm_i915_private *dev_priv = dev->dev_private;
 273
 274         uint32_t max_sleep_time = 0x1f;
 275         /*
 276          * Let's respect VBT in case VBT asks a higher idle_frame value.
 277          * Let's use 6 as the minimum to cover all known cases including
 278          * the off-by-one issue that HW has in some cases. Also there are
 279          * cases where sink should be able to train
 280          * with the 5 or 6 idle patterns.
 281          */
 282         uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
 283         uint32_t val = 0x0;
 284
 285         if (IS_HASWELL(dev))
 286                 val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
 287
 288         if (dev_priv->psr.link_standby)
 289                 val |= EDP_PSR_LINK_STANDBY;
 290
 291         I915_WRITE(EDP_PSR_CTL, val |
 292                    max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
 293                    idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
 294                    EDP_PSR_ENABLE);
 295
 296         if (dev_priv->psr.psr2_support)
 297                 I915_WRITE(EDP_PSR2_CTL, EDP_PSR2_ENABLE |
 298                                 EDP_SU_TRACK_ENABLE | EDP_PSR2_TP2_TIME_100);
 299 }
 300
 301 static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
 302 {
 303         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 304         struct drm_device *dev = dig_port->base.base.dev;
 305         struct drm_i915_private *dev_priv = dev->dev_private;
 306         struct drm_crtc *crtc = dig_port->base.base.crtc;
 307         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 308
 309         lockdep_assert_held(&dev_priv->psr.lock);
 310         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
 311         WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
 312
 313         dev_priv->psr.source_ok = false;
 314
 315         /*
 316          * HSW spec explicitly says PSR is tied to port A.
 317          * BDW+ platforms with DDI implementation of PSR have different
 318          * PSR registers per transcoder and we only implement transcoder EDP
 319          * ones. Since by Display design transcoder EDP is tied to port A
 320          * we can safely escape based on the port A.
 321          */
 322         if (HAS_DDI(dev) && dig_port->port != PORT_A) {
 323                 DRM_DEBUG_KMS("PSR condition failed: Port not supported\n");
 324                 return false;
 325         }
 326
 327         if (!i915.enable_psr) {
 328                 DRM_DEBUG_KMS("PSR disable by flag\n");
 329                 return false;
 330         }
 331
 332         if (IS_HASWELL(dev) &&
 333             I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config->cpu_transcoder)) &
 334                       S3D_ENABLE) {
 335                 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
 336                 return false;
 337         }
 338
 339         if (IS_HASWELL(dev) &&
 340             intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
 341                 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
 342                 return false;
 343         }
 344
 345         dev_priv->psr.source_ok = true;
 346         return true;
 347 }
 348
 349 static void intel_psr_activate(struct intel_dp *intel_dp)
 350 {
 351         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 352         struct drm_device *dev = intel_dig_port->base.base.dev;
 353         struct drm_i915_private *dev_priv = dev->dev_private;
 354
 355         WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE);
 356         WARN_ON(dev_priv->psr.active);
 357         lockdep_assert_held(&dev_priv->psr.lock);
 358
 359         /* Enable/Re-enable PSR on the host */
 360         if (HAS_DDI(dev))
 361                 /* On HSW+ after we enable PSR on source it will activate it
 362                  * as soon as it match configure idle_frame count. So
 363                  * we just actually enable it here on activation time.
 364                  */
 365                 hsw_psr_enable_source(intel_dp);
 366         else
 367                 vlv_psr_activate(intel_dp);
 368
 369         dev_priv->psr.active = true;
 370 }
 371
 372 /**
 373  * intel_psr_enable - Enable PSR
 374  * @intel_dp: Intel DP
 375  *
 376  * This function can only be called after the pipe is fully trained and enabled.
 377  */
 378 void intel_psr_enable(struct intel_dp *intel_dp)
 379 {
 380         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 381         struct drm_device *dev = intel_dig_port->base.base.dev;
 382         struct drm_i915_private *dev_priv = dev->dev_private;
 383         struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
 384
 385         if (!HAS_PSR(dev)) {
 386                 DRM_DEBUG_KMS("PSR not supported on this platform\n");
 387                 return;
 388         }
 389
 390         if (!is_edp_psr(intel_dp)) {
 391                 DRM_DEBUG_KMS("PSR not supported by this panel\n");
 392                 return;
 393         }
 394
 395         mutex_lock(&dev_priv->psr.lock);
 396         if (dev_priv->psr.enabled) {
 397                 DRM_DEBUG_KMS("PSR already in use\n");
 398                 goto unlock;
 399         }
 400
 401         if (!intel_psr_match_conditions(intel_dp))
 402                 goto unlock;
 403
 404         dev_priv->psr.busy_frontbuffer_bits = 0;
 405
 406         if (HAS_DDI(dev)) {
 407                 hsw_psr_setup_vsc(intel_dp);
 408
 409                 if (dev_priv->psr.psr2_support) {
 410                         /* PSR2 is restricted to work with panel resolutions upto 3200x2000 */
 411                         if (crtc->config->pipe_src_w > 3200 ||
 412                                 crtc->config->pipe_src_h > 2000)
 413                                 dev_priv->psr.psr2_support = false;
 414                         else
 415                                 skl_psr_setup_su_vsc(intel_dp);
 416                 }
 417
 418                 /*
 419                  * Per Spec: Avoid continuous PSR exit by masking MEMUP and HPD.
 420                  * Also mask LPSP to avoid dependency on other drivers that
 421                  * might block runtime_pm besides preventing other hw tracking
 422                  * issues now we can rely on frontbuffer tracking.
 423                  */
 424                 I915_WRITE(EDP_PSR_DEBUG_CTL, EDP_PSR_DEBUG_MASK_MEMUP |
 425                            EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
 426
 427                 /* Enable PSR on the panel */
 428                 hsw_psr_enable_sink(intel_dp);
 429
 430                 if (INTEL_INFO(dev)->gen >= 9)
 431                         intel_psr_activate(intel_dp);
 432         } else {
 433                 vlv_psr_setup_vsc(intel_dp);
 434
 435                 /* Enable PSR on the panel */
 436                 vlv_psr_enable_sink(intel_dp);
 437
 438                 /* On HSW+ enable_source also means go to PSR entry/active
 439                  * state as soon as idle_frame achieved and here would be
 440                  * to soon. However on VLV enable_source just enable PSR
 441                  * but let it on inactive state. So we might do this prior
 442                  * to active transition, i.e. here.
 443                  */
 444                 vlv_psr_enable_source(intel_dp);
 445         }
 446
 447         /*
 448          * FIXME: Activation should happen immediately since this function
 449          * is just called after pipe is fully trained and enabled.
 450          * However on every platform we face issues when first activation
 451          * follows a modeset so quickly.
 452          *     - On VLV/CHV we get bank screen on first activation
 453          *     - On HSW/BDW we get a recoverable frozen screen until next
 454          *       exit-activate sequence.
 455          */
 456         if (INTEL_INFO(dev)->gen < 9)
 457                 schedule_delayed_work(&dev_priv->psr.work,
 458                                       msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
 459
 460         dev_priv->psr.enabled = intel_dp;
 461 unlock:
 462         mutex_unlock(&dev_priv->psr.lock);
 463 }
 464
 465 static void vlv_psr_disable(struct intel_dp *intel_dp)
 466 {
 467         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 468         struct drm_device *dev = intel_dig_port->base.base.dev;
 469         struct drm_i915_private *dev_priv = dev->dev_private;
 470         struct intel_crtc *intel_crtc =
 471                 to_intel_crtc(intel_dig_port->base.base.crtc);
 472         uint32_t val;
 473
 474         if (dev_priv->psr.active) {
 475                 /* Put VLV PSR back to PSR_state 0 that is PSR Disabled. */
 476                 if (wait_for((I915_READ(VLV_PSRSTAT(intel_crtc->pipe)) &
 477                               VLV_EDP_PSR_IN_TRANS) == 0, 1))
 478                         WARN(1, "PSR transition took longer than expected\n");
 479
 480                 val = I915_READ(VLV_PSRCTL(intel_crtc->pipe));
 481                 val &= ~VLV_EDP_PSR_ACTIVE_ENTRY;
 482                 val &= ~VLV_EDP_PSR_ENABLE;
 483                 val &= ~VLV_EDP_PSR_MODE_MASK;
 484                 I915_WRITE(VLV_PSRCTL(intel_crtc->pipe), val);
 485
 486                 dev_priv->psr.active = false;
 487         } else {
 488                 WARN_ON(vlv_is_psr_active_on_pipe(dev, intel_crtc->pipe));
 489         }
 490 }
 491
 492 static void hsw_psr_disable(struct intel_dp *intel_dp)
 493 {
 494         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 495         struct drm_device *dev = intel_dig_port->base.base.dev;
 496         struct drm_i915_private *dev_priv = dev->dev_private;
 497
 498         if (dev_priv->psr.active) {
 499                 I915_WRITE(EDP_PSR_CTL,
 500                            I915_READ(EDP_PSR_CTL) & ~EDP_PSR_ENABLE);
 501
 502                 /* Wait till PSR is idle */
 503                 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL) &
 504                                EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
 505                         DRM_ERROR("Timed out waiting for PSR Idle State\n");
 506
 507                 dev_priv->psr.active = false;
 508         } else {
 509                 WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE);
 510         }
 511 }
 512
 513 /**
 514  * intel_psr_disable - Disable PSR
 515  * @intel_dp: Intel DP
 516  *
 517  * This function needs to be called before disabling pipe.
 518  */
 519 void intel_psr_disable(struct intel_dp *intel_dp)
 520 {
 521         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 522         struct drm_device *dev = intel_dig_port->base.base.dev;
 523         struct drm_i915_private *dev_priv = dev->dev_private;
 524
 525         mutex_lock(&dev_priv->psr.lock);
 526         if (!dev_priv->psr.enabled) {
 527                 mutex_unlock(&dev_priv->psr.lock);
 528                 return;
 529         }
 530
 531         /* Disable PSR on Source */
 532         if (HAS_DDI(dev))
 533                 hsw_psr_disable(intel_dp);
 534         else
 535                 vlv_psr_disable(intel_dp);
 536
 537         /* Disable PSR on Sink */
 538         drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0);
 539
 540         dev_priv->psr.enabled = NULL;
 541         mutex_unlock(&dev_priv->psr.lock);
 542
 543         cancel_delayed_work_sync(&dev_priv->psr.work);
 544 }
 545
 546 static void intel_psr_work(struct work_struct *work)
 547 {
 548         struct drm_i915_private *dev_priv =
 549                 container_of(work, typeof(*dev_priv), psr.work.work);
 550         struct intel_dp *intel_dp = dev_priv->psr.enabled;
 551         struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
 552         enum pipe pipe = to_intel_crtc(crtc)->pipe;
 553
 554         /* We have to make sure PSR is ready for re-enable
 555          * otherwise it keeps disabled until next full enable/disable cycle.
 556          * PSR might take some time to get fully disabled
 557          * and be ready for re-enable.
 558          */
 559         if (HAS_DDI(dev_priv->dev)) {
 560                 if (wait_for((I915_READ(EDP_PSR_STATUS_CTL) &
 561                               EDP_PSR_STATUS_STATE_MASK) == 0, 50)) {
 562                         DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
 563                         return;
 564                 }
 565         } else {
 566                 if (wait_for((I915_READ(VLV_PSRSTAT(pipe)) &
 567                               VLV_EDP_PSR_IN_TRANS) == 0, 1)) {
 568                         DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
 569                         return;
 570                 }
 571         }
 572         mutex_lock(&dev_priv->psr.lock);
 573         intel_dp = dev_priv->psr.enabled;
 574
 575         if (!intel_dp)
 576                 goto unlock;
 577
 578         /*
 579          * The delayed work can race with an invalidate hence we need to
 580          * recheck. Since psr_flush first clears this and then reschedules we
 581          * won't ever miss a flush when bailing out here.
 582          */
 583         if (dev_priv->psr.busy_frontbuffer_bits)
 584                 goto unlock;
 585
 586         intel_psr_activate(intel_dp);
 587 unlock:
 588         mutex_unlock(&dev_priv->psr.lock);
 589 }
 590
 591 static void intel_psr_exit(struct drm_device *dev)
 592 {
 593         struct drm_i915_private *dev_priv = dev->dev_private;
 594         struct intel_dp *intel_dp = dev_priv->psr.enabled;
 595         struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
 596         enum pipe pipe = to_intel_crtc(crtc)->pipe;
 597         u32 val;
 598
 599         if (!dev_priv->psr.active)
 600                 return;
 601
 602         if (HAS_DDI(dev)) {
 603                 val = I915_READ(EDP_PSR_CTL);
 604
 605                 WARN_ON(!(val & EDP_PSR_ENABLE));
 606
 607                 I915_WRITE(EDP_PSR_CTL, val & ~EDP_PSR_ENABLE);
 608         } else {
 609                 val = I915_READ(VLV_PSRCTL(pipe));
 610
 611                 /* Here we do the transition from PSR_state 3 to PSR_state 5
 612                  * directly once PSR State 4 that is active with single frame
 613                  * update can be skipped. PSR_state 5 that is PSR exit then
 614                  * Hardware is responsible to transition back to PSR_state 1
 615                  * that is PSR inactive. Same state after
 616                  * vlv_edp_psr_enable_source.
 617                  */
 618                 val &= ~VLV_EDP_PSR_ACTIVE_ENTRY;
 619                 I915_WRITE(VLV_PSRCTL(pipe), val);
 620
 621                 /* Send AUX wake up - Spec says after transitioning to PSR
 622                  * active we have to send AUX wake up by writing 01h in DPCD
 623                  * 600h of sink device.
 624                  * XXX: This might slow down the transition, but without this
 625                  * HW doesn't complete the transition to PSR_state 1 and we
 626                  * never get the screen updated.
 627                  */
 628                 drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
 629                                    DP_SET_POWER_D0);
 630         }
 631
 632         dev_priv->psr.active = false;
 633 }
 634
 635 /**
 636  * intel_psr_single_frame_update - Single Frame Update
 637  * @dev: DRM device
 638  * @frontbuffer_bits: frontbuffer plane tracking bits
 639  *
 640  * Some platforms support a single frame update feature that is used to
 641  * send and update only one frame on Remote Frame Buffer.
 642  * So far it is only implemented for Valleyview and Cherryview because
 643  * hardware requires this to be done before a page flip.
 644  */
 645 void intel_psr_single_frame_update(struct drm_device *dev,
 646                                    unsigned frontbuffer_bits)
 647 {
 648         struct drm_i915_private *dev_priv = dev->dev_private;
 649         struct drm_crtc *crtc;
 650         enum pipe pipe;
 651         u32 val;
 652
 653         /*
 654          * Single frame update is already supported on BDW+ but it requires
 655          * many W/A and it isn't really needed.
 656          */
 657         if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev))
 658                 return;
 659
 660         mutex_lock(&dev_priv->psr.lock);
 661         if (!dev_priv->psr.enabled) {
 662                 mutex_unlock(&dev_priv->psr.lock);
 663                 return;
 664         }
 665
 666         crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
 667         pipe = to_intel_crtc(crtc)->pipe;
 668
 669         if (frontbuffer_bits & INTEL_FRONTBUFFER_ALL_MASK(pipe)) {
 670                 val = I915_READ(VLV_PSRCTL(pipe));
 671
 672                 /*
 673                  * We need to set this bit before writing registers for a flip.
 674                  * This bit will be self-clear when it gets to the PSR active state.
 675                  */
 676                 I915_WRITE(VLV_PSRCTL(pipe), val | VLV_EDP_PSR_SINGLE_FRAME_UPDATE);
 677         }
 678         mutex_unlock(&dev_priv->psr.lock);
 679 }
 680
 681 /**
 682  * intel_psr_invalidate - Invalidade PSR
 683  * @dev: DRM device
 684  * @frontbuffer_bits: frontbuffer plane tracking bits
 685  *
 686  * Since the hardware frontbuffer tracking has gaps we need to integrate
 687  * with the software frontbuffer tracking. This function gets called every
 688  * time frontbuffer rendering starts and a buffer gets dirtied. PSR must be
 689  * disabled if the frontbuffer mask contains a buffer relevant to PSR.
 690  *
 691  * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits."
 692  */
 693 void intel_psr_invalidate(struct drm_device *dev,
 694                           unsigned frontbuffer_bits)
 695 {
 696         struct drm_i915_private *dev_priv = dev->dev_private;
 697         struct drm_crtc *crtc;
 698         enum pipe pipe;
 699
 700         mutex_lock(&dev_priv->psr.lock);
 701         if (!dev_priv->psr.enabled) {
 702                 mutex_unlock(&dev_priv->psr.lock);
 703                 return;
 704         }
 705
 706         crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
 707         pipe = to_intel_crtc(crtc)->pipe;
 708
 709         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
 710         dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits;
 711
 712         if (frontbuffer_bits)
 713                 intel_psr_exit(dev);
 714
 715         mutex_unlock(&dev_priv->psr.lock);
 716 }
 717
 718 /**
 719  * intel_psr_flush - Flush PSR
 720  * @dev: DRM device
 721  * @frontbuffer_bits: frontbuffer plane tracking bits
 722  * @origin: which operation caused the flush
 723  *
 724  * Since the hardware frontbuffer tracking has gaps we need to integrate
 725  * with the software frontbuffer tracking. This function gets called every
 726  * time frontbuffer rendering has completed and flushed out to memory. PSR
 727  * can be enabled again if no other frontbuffer relevant to PSR is dirty.
 728  *
 729  * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits.
 730  */
 731 void intel_psr_flush(struct drm_device *dev,
 732                      unsigned frontbuffer_bits, enum fb_op_origin origin)
 733 {
 734         struct drm_i915_private *dev_priv = dev->dev_private;
 735         struct drm_crtc *crtc;
 736         enum pipe pipe;
 737
 738         mutex_lock(&dev_priv->psr.lock);
 739         if (!dev_priv->psr.enabled) {
 740                 mutex_unlock(&dev_priv->psr.lock);
 741                 return;
 742         }
 743
 744         crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
 745         pipe = to_intel_crtc(crtc)->pipe;
 746
 747         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
 748         dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits;
 749
 750         /* By definition flush = invalidate + flush */
 751         if (frontbuffer_bits)
 752                 intel_psr_exit(dev);
 753
 754         if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
 755                 if (!work_busy(&dev_priv->psr.work.work))
 756                         schedule_delayed_work(&dev_priv->psr.work,
 757                                               msecs_to_jiffies(100));
 758         mutex_unlock(&dev_priv->psr.lock);
 759 }
 760
 761 /**
 762  * intel_psr_init - Init basic PSR work and mutex.
 763  * @dev: DRM device
 764  *
 765  * This function is  called only once at driver load to initialize basic
 766  * PSR stuff.
 767  */
 768 void intel_psr_init(struct drm_device *dev)
 769 {
 770         struct drm_i915_private *dev_priv = dev->dev_private;
 771
 772         dev_priv->psr_mmio_base = IS_HASWELL(dev_priv) ?
 773                 HSW_EDP_PSR_BASE : BDW_EDP_PSR_BASE;
 774
 775         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
 776                 /* HSW and BDW require workarounds that we don't implement. */
 777                 dev_priv->psr.link_standby = false;
 778         else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 779                 /* On VLV and CHV only standby mode is supported. */
 780                 dev_priv->psr.link_standby = true;
 781         else
 782                 /* For new platforms let's respect VBT back again */
 783                 dev_priv->psr.link_standby = dev_priv->vbt.psr.full_link;
 784
 785         INIT_DELAYED_WORK(&dev_priv->psr.work, intel_psr_work);
 786         mutex_init(&dev_priv->psr.lock);
 787 }