drivers/gpu/drm/i915/intel_psr.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 /**
  25  * DOC: Panel Self Refresh (PSR/SRD)
  26  *
  27  * Since Haswell Display controller supports Panel Self-Refresh on display
  28  * panels witch have a remote frame buffer (RFB) implemented according to PSR
  29  * spec in eDP1.3. PSR feature allows the display to go to lower standby states
  30  * when system is idle but display is on as it eliminates display refresh
  31  * request to DDR memory completely as long as the frame buffer for that
  32  * display is unchanged.
  33  *
  34  * Panel Self Refresh must be supported by both Hardware (source) and
  35  * Panel (sink).
  36  *
  37  * PSR saves power by caching the framebuffer in the panel RFB, which allows us
  38  * to power down the link and memory controller. For DSI panels the same idea
  39  * is called "manual mode".
  40  *
  41  * The implementation uses the hardware-based PSR support which automatically
  42  * enters/exits self-refresh mode. The hardware takes care of sending the
  43  * required DP aux message and could even retrain the link (that part isn't
  44  * enabled yet though). The hardware also keeps track of any frontbuffer
  45  * changes to know when to exit self-refresh mode again. Unfortunately that
  46  * part doesn't work too well, hence why the i915 PSR support uses the
  47  * software frontbuffer tracking to make sure it doesn't miss a screen
  48  * update. For this integration intel_psr_invalidate() and intel_psr_flush()
  49  * get called by the frontbuffer tracking code. Note that because of locking
  50  * issues the self-refresh re-enable code is done from a work queue, which
  51  * must be correctly synchronized/cancelled when shutting down the pipe."
  52  */
  53
  54 #include <drm/drmP.h>
  55
  56 #include "intel_drv.h"
  57 #include "i915_drv.h"
  58
  59 static bool is_edp_psr(struct intel_dp *intel_dp)
  60 {
  61         return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
  62 }
  63
  64 static bool vlv_is_psr_active_on_pipe(struct drm_device *dev, int pipe)
  65 {
  66         struct drm_i915_private *dev_priv = dev->dev_private;
  67         uint32_t val;
  68
  69         val = I915_READ(VLV_PSRSTAT(pipe)) &
  70               VLV_EDP_PSR_CURR_STATE_MASK;
  71         return (val == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
  72                (val == VLV_EDP_PSR_ACTIVE_SF_UPDATE);
  73 }
  74
  75 static void intel_psr_write_vsc(struct intel_dp *intel_dp,
  76                                 const struct edp_vsc_psr *vsc_psr)
  77 {
  78         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
  79         struct drm_device *dev = dig_port->base.base.dev;
  80         struct drm_i915_private *dev_priv = dev->dev_private;
  81         struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
  82         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
  83         i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
  84         uint32_t *data = (uint32_t *) vsc_psr;
  85         unsigned int i;
  86
  87         /* As per BSPec (Pipe Video Data Island Packet), we need to disable
  88            the video DIP being updated before program video DIP data buffer
  89            registers for DIP being updated. */
  90         I915_WRITE(ctl_reg, 0);
  91         POSTING_READ(ctl_reg);
  92
  93         for (i = 0; i < sizeof(*vsc_psr); i += 4) {
  94                 I915_WRITE(HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder,
  95                                                    i >> 2), *data);
  96                 data++;
  97         }
  98         for (; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4)
  99                 I915_WRITE(HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder,
 100                                                    i >> 2), 0);
 101
 102         I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
 103         POSTING_READ(ctl_reg);
 104 }
 105
 106 static void vlv_psr_setup_vsc(struct intel_dp *intel_dp)
 107 {
 108         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 109         struct drm_device *dev = intel_dig_port->base.base.dev;
 110         struct drm_i915_private *dev_priv = dev->dev_private;
 111         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
 112         enum pipe pipe = to_intel_crtc(crtc)->pipe;
 113         uint32_t val;
 114
 115         /* VLV auto-generate VSC package as per EDP 1.3 spec, Table 3.10 */
 116         val  = I915_READ(VLV_VSCSDP(pipe));
 117         val &= ~VLV_EDP_PSR_SDP_FREQ_MASK;
 118         val |= VLV_EDP_PSR_SDP_FREQ_EVFRAME;
 119         I915_WRITE(VLV_VSCSDP(pipe), val);
 120 }
 121
 122 static void skl_psr_setup_su_vsc(struct intel_dp *intel_dp)
 123 {
 124         struct edp_vsc_psr psr_vsc;
 125
 126         /* Prepare VSC Header for SU as per EDP 1.4 spec, Table 6.11 */
 127         memset(&psr_vsc, 0, sizeof(psr_vsc));
 128         psr_vsc.sdp_header.HB0 = 0;
 129         psr_vsc.sdp_header.HB1 = 0x7;
 130         psr_vsc.sdp_header.HB2 = 0x3;
 131         psr_vsc.sdp_header.HB3 = 0xb;
 132         intel_psr_write_vsc(intel_dp, &psr_vsc);
 133 }
 134
 135 static void hsw_psr_setup_vsc(struct intel_dp *intel_dp)
 136 {
 137         struct edp_vsc_psr psr_vsc;
 138
 139         /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
 140         memset(&psr_vsc, 0, sizeof(psr_vsc));
 141         psr_vsc.sdp_header.HB0 = 0;
 142         psr_vsc.sdp_header.HB1 = 0x7;
 143         psr_vsc.sdp_header.HB2 = 0x2;
 144         psr_vsc.sdp_header.HB3 = 0x8;
 145         intel_psr_write_vsc(intel_dp, &psr_vsc);
 146 }
 147
 148 static void vlv_psr_enable_sink(struct intel_dp *intel_dp)
 149 {
 150         drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
 151                            DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
 152 }
 153
 154 static i915_reg_t psr_aux_ctl_reg(struct drm_i915_private *dev_priv,
 155                                        enum port port)
 156 {
 157         if (INTEL_INFO(dev_priv)->gen >= 9)
 158                 return DP_AUX_CH_CTL(port);
 159         else
 160                 return EDP_PSR_AUX_CTL;
 161 }
 162
 163 static i915_reg_t psr_aux_data_reg(struct drm_i915_private *dev_priv,
 164                                         enum port port, int index)
 165 {
 166         if (INTEL_INFO(dev_priv)->gen >= 9)
 167                 return DP_AUX_CH_DATA(port, index);
 168         else
 169                 return EDP_PSR_AUX_DATA(index);
 170 }
 171
 172 static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
 173 {
 174         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 175         struct drm_device *dev = dig_port->base.base.dev;
 176         struct drm_i915_private *dev_priv = dev->dev_private;
 177         uint32_t aux_clock_divider;
 178         i915_reg_t aux_ctl_reg;
 179         static const uint8_t aux_msg[] = {
 180                 [0] = DP_AUX_NATIVE_WRITE << 4,
 181                 [1] = DP_SET_POWER >> 8,
 182                 [2] = DP_SET_POWER & 0xff,
 183                 [3] = 1 - 1,
 184                 [4] = DP_SET_POWER_D0,
 185         };
 186         enum port port = dig_port->port;
 187         u32 aux_ctl;
 188         int i;
 189
 190         BUILD_BUG_ON(sizeof(aux_msg) > 20);
 191
 192         aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
 193
 194         /* Enable AUX frame sync at sink */
 195         if (dev_priv->psr.aux_frame_sync)
 196                 drm_dp_dpcd_writeb(&intel_dp->aux,
 197                                 DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF,
 198                                 DP_AUX_FRAME_SYNC_ENABLE);
 199
 200         if (dev_priv->psr.link_standby)
 201                 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
 202                                    DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
 203         else
 204                 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
 205                                    DP_PSR_ENABLE);
 206
 207         aux_ctl_reg = psr_aux_ctl_reg(dev_priv, port);
 208
 209         /* Setup AUX registers */
 210         for (i = 0; i < sizeof(aux_msg); i += 4)
 211                 I915_WRITE(psr_aux_data_reg(dev_priv, port, i >> 2),
 212                            intel_dp_pack_aux(&aux_msg[i], sizeof(aux_msg) - i));
 213
 214         aux_ctl = intel_dp->get_aux_send_ctl(intel_dp, 0, sizeof(aux_msg),
 215                                              aux_clock_divider);
 216         I915_WRITE(aux_ctl_reg, aux_ctl);
 217 }
 218
 219 static void vlv_psr_enable_source(struct intel_dp *intel_dp)
 220 {
 221         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 222         struct drm_device *dev = dig_port->base.base.dev;
 223         struct drm_i915_private *dev_priv = dev->dev_private;
 224         struct drm_crtc *crtc = dig_port->base.base.crtc;
 225         enum pipe pipe = to_intel_crtc(crtc)->pipe;
 226
 227         /* Transition from PSR_state 0 to PSR_state 1, i.e. PSR Inactive */
 228         I915_WRITE(VLV_PSRCTL(pipe),
 229                    VLV_EDP_PSR_MODE_SW_TIMER |
 230                    VLV_EDP_PSR_SRC_TRANSMITTER_STATE |
 231                    VLV_EDP_PSR_ENABLE);
 232 }
 233
 234 static void vlv_psr_activate(struct intel_dp *intel_dp)
 235 {
 236         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 237         struct drm_device *dev = dig_port->base.base.dev;
 238         struct drm_i915_private *dev_priv = dev->dev_private;
 239         struct drm_crtc *crtc = dig_port->base.base.crtc;
 240         enum pipe pipe = to_intel_crtc(crtc)->pipe;
 241
 242         /* Let's do the transition from PSR_state 1 to PSR_state 2
 243          * that is PSR transition to active - static frame transmission.
 244          * Then Hardware is responsible for the transition to PSR_state 3
 245          * that is PSR active - no Remote Frame Buffer (RFB) update.
 246          */
 247         I915_WRITE(VLV_PSRCTL(pipe), I915_READ(VLV_PSRCTL(pipe)) |
 248                    VLV_EDP_PSR_ACTIVE_ENTRY);
 249 }
 250
 251 static void hsw_psr_enable_source(struct intel_dp *intel_dp)
 252 {
 253         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 254         struct drm_device *dev = dig_port->base.base.dev;
 255         struct drm_i915_private *dev_priv = dev->dev_private;
 256
 257         uint32_t max_sleep_time = 0x1f;
 258         /* Lately it was identified that depending on panel idle frame count
 259          * calculated at HW can be off by 1. So let's use what came
 260          * from VBT + 1.
 261          * There are also other cases where panel demands at least 4
 262          * but VBT is not being set. To cover these 2 cases lets use
 263          * at least 5 when VBT isn't set to be on the safest side.
 264          */
 265         uint32_t idle_frames = dev_priv->vbt.psr.idle_frames + 1;
 266         uint32_t val = EDP_PSR_ENABLE;
 267
 268         val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT;
 269         val |= idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
 270
 271         if (IS_HASWELL(dev))
 272                 val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
 273
 274         if (dev_priv->psr.link_standby)
 275                 val |= EDP_PSR_LINK_STANDBY;
 276
 277         if (dev_priv->vbt.psr.tp1_wakeup_time > 5)
 278                 val |= EDP_PSR_TP1_TIME_2500us;
 279         else if (dev_priv->vbt.psr.tp1_wakeup_time > 1)
 280                 val |= EDP_PSR_TP1_TIME_500us;
 281         else if (dev_priv->vbt.psr.tp1_wakeup_time > 0)
 282                 val |= EDP_PSR_TP1_TIME_100us;
 283         else
 284                 val |= EDP_PSR_TP1_TIME_0us;
 285
 286         if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
 287                 val |= EDP_PSR_TP2_TP3_TIME_2500us;
 288         else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
 289                 val |= EDP_PSR_TP2_TP3_TIME_500us;
 290         else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
 291                 val |= EDP_PSR_TP2_TP3_TIME_100us;
 292         else
 293                 val |= EDP_PSR_TP2_TP3_TIME_0us;
 294
 295         if (intel_dp_source_supports_hbr2(intel_dp) &&
 296             drm_dp_tps3_supported(intel_dp->dpcd))
 297                 val |= EDP_PSR_TP1_TP3_SEL;
 298         else
 299                 val |= EDP_PSR_TP1_TP2_SEL;
 300
 301         I915_WRITE(EDP_PSR_CTL, val);
 302
 303         if (!dev_priv->psr.psr2_support)
 304                 return;
 305
 306         /* FIXME: selective update is probably totally broken because it doesn't
 307          * mesh at all with our frontbuffer tracking. And the hw alone isn't
 308          * good enough. */
 309         val = EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE;
 310
 311         if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
 312                 val |= EDP_PSR2_TP2_TIME_2500;
 313         else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
 314                 val |= EDP_PSR2_TP2_TIME_500;
 315         else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
 316                 val |= EDP_PSR2_TP2_TIME_100;
 317         else
 318                 val |= EDP_PSR2_TP2_TIME_50;
 319
 320         I915_WRITE(EDP_PSR2_CTL, val);
 321 }
 322
 323 static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
 324 {
 325         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 326         struct drm_device *dev = dig_port->base.base.dev;
 327         struct drm_i915_private *dev_priv = dev->dev_private;
 328         struct drm_crtc *crtc = dig_port->base.base.crtc;
 329         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 330
 331         lockdep_assert_held(&dev_priv->psr.lock);
 332         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
 333         WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
 334
 335         dev_priv->psr.source_ok = false;
 336
 337         /*
 338          * HSW spec explicitly says PSR is tied to port A.
 339          * BDW+ platforms with DDI implementation of PSR have different
 340          * PSR registers per transcoder and we only implement transcoder EDP
 341          * ones. Since by Display design transcoder EDP is tied to port A
 342          * we can safely escape based on the port A.
 343          */
 344         if (HAS_DDI(dev) && dig_port->port != PORT_A) {
 345                 DRM_DEBUG_KMS("PSR condition failed: Port not supported\n");
 346                 return false;
 347         }
 348
 349         if (!i915.enable_psr) {
 350                 DRM_DEBUG_KMS("PSR disable by flag\n");
 351                 return false;
 352         }
 353
 354         if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
 355             !dev_priv->psr.link_standby) {
 356                 DRM_ERROR("PSR condition failed: Link off requested but not supported on this platform\n");
 357                 return false;
 358         }
 359
 360         if (IS_HASWELL(dev) &&
 361             I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config->cpu_transcoder)) &
 362                       S3D_ENABLE) {
 363                 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
 364                 return false;
 365         }
 366
 367         if (IS_HASWELL(dev) &&
 368             intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
 369                 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
 370                 return false;
 371         }
 372
 373         dev_priv->psr.source_ok = true;
 374         return true;
 375 }
 376
 377 static void intel_psr_activate(struct intel_dp *intel_dp)
 378 {
 379         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 380         struct drm_device *dev = intel_dig_port->base.base.dev;
 381         struct drm_i915_private *dev_priv = dev->dev_private;
 382
 383         WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE);
 384         WARN_ON(dev_priv->psr.active);
 385         lockdep_assert_held(&dev_priv->psr.lock);
 386
 387         /* Enable/Re-enable PSR on the host */
 388         if (HAS_DDI(dev))
 389                 /* On HSW+ after we enable PSR on source it will activate it
 390                  * as soon as it match configure idle_frame count. So
 391                  * we just actually enable it here on activation time.
 392                  */
 393                 hsw_psr_enable_source(intel_dp);
 394         else
 395                 vlv_psr_activate(intel_dp);
 396
 397         dev_priv->psr.active = true;
 398 }
 399
 400 /**
 401  * intel_psr_enable - Enable PSR
 402  * @intel_dp: Intel DP
 403  *
 404  * This function can only be called after the pipe is fully trained and enabled.
 405  */
 406 void intel_psr_enable(struct intel_dp *intel_dp)
 407 {
 408         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 409         struct drm_device *dev = intel_dig_port->base.base.dev;
 410         struct drm_i915_private *dev_priv = dev->dev_private;
 411         struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
 412
 413         if (!HAS_PSR(dev)) {
 414                 DRM_DEBUG_KMS("PSR not supported on this platform\n");
 415                 return;
 416         }
 417
 418         if (!is_edp_psr(intel_dp)) {
 419                 DRM_DEBUG_KMS("PSR not supported by this panel\n");
 420                 return;
 421         }
 422
 423         mutex_lock(&dev_priv->psr.lock);
 424         if (dev_priv->psr.enabled) {
 425                 DRM_DEBUG_KMS("PSR already in use\n");
 426                 goto unlock;
 427         }
 428
 429         if (!intel_psr_match_conditions(intel_dp))
 430                 goto unlock;
 431
 432         dev_priv->psr.busy_frontbuffer_bits = 0;
 433
 434         if (HAS_DDI(dev)) {
 435                 hsw_psr_setup_vsc(intel_dp);
 436
 437                 if (dev_priv->psr.psr2_support) {
 438                         /* PSR2 is restricted to work with panel resolutions upto 3200x2000 */
 439                         if (crtc->config->pipe_src_w > 3200 ||
 440                                 crtc->config->pipe_src_h > 2000)
 441                                 dev_priv->psr.psr2_support = false;
 442                         else
 443                                 skl_psr_setup_su_vsc(intel_dp);
 444                 }
 445
 446                 /*
 447                  * Per Spec: Avoid continuous PSR exit by masking MEMUP and HPD.
 448                  * Also mask LPSP to avoid dependency on other drivers that
 449                  * might block runtime_pm besides preventing other hw tracking
 450                  * issues now we can rely on frontbuffer tracking.
 451                  */
 452                 I915_WRITE(EDP_PSR_DEBUG_CTL, EDP_PSR_DEBUG_MASK_MEMUP |
 453                            EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
 454
 455                 /* Enable PSR on the panel */
 456                 hsw_psr_enable_sink(intel_dp);
 457
 458                 if (INTEL_INFO(dev)->gen >= 9)
 459                         intel_psr_activate(intel_dp);
 460         } else {
 461                 vlv_psr_setup_vsc(intel_dp);
 462
 463                 /* Enable PSR on the panel */
 464                 vlv_psr_enable_sink(intel_dp);
 465
 466                 /* On HSW+ enable_source also means go to PSR entry/active
 467                  * state as soon as idle_frame achieved and here would be
 468                  * to soon. However on VLV enable_source just enable PSR
 469                  * but let it on inactive state. So we might do this prior
 470                  * to active transition, i.e. here.
 471                  */
 472                 vlv_psr_enable_source(intel_dp);
 473         }
 474
 475         /*
 476          * FIXME: Activation should happen immediately since this function
 477          * is just called after pipe is fully trained and enabled.
 478          * However on every platform we face issues when first activation
 479          * follows a modeset so quickly.
 480          *     - On VLV/CHV we get bank screen on first activation
 481          *     - On HSW/BDW we get a recoverable frozen screen until next
 482          *       exit-activate sequence.
 483          */
 484         if (INTEL_INFO(dev)->gen < 9)
 485                 schedule_delayed_work(&dev_priv->psr.work,
 486                                       msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
 487
 488         dev_priv->psr.enabled = intel_dp;
 489 unlock:
 490         mutex_unlock(&dev_priv->psr.lock);
 491 }
 492
 493 static void vlv_psr_disable(struct intel_dp *intel_dp)
 494 {
 495         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 496         struct drm_device *dev = intel_dig_port->base.base.dev;
 497         struct drm_i915_private *dev_priv = dev->dev_private;
 498         struct intel_crtc *intel_crtc =
 499                 to_intel_crtc(intel_dig_port->base.base.crtc);
 500         uint32_t val;
 501
 502         if (dev_priv->psr.active) {
 503                 /* Put VLV PSR back to PSR_state 0 that is PSR Disabled. */
 504                 if (intel_wait_for_register(dev_priv,
 505                                             VLV_PSRSTAT(intel_crtc->pipe),
 506                                             VLV_EDP_PSR_IN_TRANS,
 507                                             0,
 508                                             1))
 509                         WARN(1, "PSR transition took longer than expected\n");
 510
 511                 val = I915_READ(VLV_PSRCTL(intel_crtc->pipe));
 512                 val &= ~VLV_EDP_PSR_ACTIVE_ENTRY;
 513                 val &= ~VLV_EDP_PSR_ENABLE;
 514                 val &= ~VLV_EDP_PSR_MODE_MASK;
 515                 I915_WRITE(VLV_PSRCTL(intel_crtc->pipe), val);
 516
 517                 dev_priv->psr.active = false;
 518         } else {
 519                 WARN_ON(vlv_is_psr_active_on_pipe(dev, intel_crtc->pipe));
 520         }
 521 }
 522
 523 static void hsw_psr_disable(struct intel_dp *intel_dp)
 524 {
 525         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 526         struct drm_device *dev = intel_dig_port->base.base.dev;
 527         struct drm_i915_private *dev_priv = dev->dev_private;
 528
 529         if (dev_priv->psr.active) {
 530                 I915_WRITE(EDP_PSR_CTL,
 531                            I915_READ(EDP_PSR_CTL) & ~EDP_PSR_ENABLE);
 532
 533                 /* Wait till PSR is idle */
 534                 if (intel_wait_for_register(dev_priv,
 535                                             EDP_PSR_STATUS_CTL,
 536                                             EDP_PSR_STATUS_STATE_MASK,
 537                                             0,
 538                                             2000))
 539                         DRM_ERROR("Timed out waiting for PSR Idle State\n");
 540
 541                 dev_priv->psr.active = false;
 542         } else {
 543                 WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE);
 544         }
 545 }
 546
 547 /**
 548  * intel_psr_disable - Disable PSR
 549  * @intel_dp: Intel DP
 550  *
 551  * This function needs to be called before disabling pipe.
 552  */
 553 void intel_psr_disable(struct intel_dp *intel_dp)
 554 {
 555         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 556         struct drm_device *dev = intel_dig_port->base.base.dev;
 557         struct drm_i915_private *dev_priv = dev->dev_private;
 558
 559         mutex_lock(&dev_priv->psr.lock);
 560         if (!dev_priv->psr.enabled) {
 561                 mutex_unlock(&dev_priv->psr.lock);
 562                 return;
 563         }
 564
 565         /* Disable PSR on Source */
 566         if (HAS_DDI(dev))
 567                 hsw_psr_disable(intel_dp);
 568         else
 569                 vlv_psr_disable(intel_dp);
 570
 571         /* Disable PSR on Sink */
 572         drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0);
 573
 574         dev_priv->psr.enabled = NULL;
 575         mutex_unlock(&dev_priv->psr.lock);
 576
 577         cancel_delayed_work_sync(&dev_priv->psr.work);
 578 }
 579
 580 static void intel_psr_work(struct work_struct *work)
 581 {
 582         struct drm_i915_private *dev_priv =
 583                 container_of(work, typeof(*dev_priv), psr.work.work);
 584         struct intel_dp *intel_dp = dev_priv->psr.enabled;
 585         struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
 586         enum pipe pipe = to_intel_crtc(crtc)->pipe;
 587
 588         /* We have to make sure PSR is ready for re-enable
 589          * otherwise it keeps disabled until next full enable/disable cycle.
 590          * PSR might take some time to get fully disabled
 591          * and be ready for re-enable.
 592          */
 593         if (HAS_DDI(dev_priv)) {
 594                 if (wait_for((I915_READ(EDP_PSR_STATUS_CTL) &
 595                               EDP_PSR_STATUS_STATE_MASK) == 0, 50)) {
 596                         DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
 597                         return;
 598                 }
 599         } else {
 600                 if (wait_for((I915_READ(VLV_PSRSTAT(pipe)) &
 601                               VLV_EDP_PSR_IN_TRANS) == 0, 1)) {
 602                         DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
 603                         return;
 604                 }
 605         }
 606         mutex_lock(&dev_priv->psr.lock);
 607         intel_dp = dev_priv->psr.enabled;
 608
 609         if (!intel_dp)
 610                 goto unlock;
 611
 612         /*
 613          * The delayed work can race with an invalidate hence we need to
 614          * recheck. Since psr_flush first clears this and then reschedules we
 615          * won't ever miss a flush when bailing out here.
 616          */
 617         if (dev_priv->psr.busy_frontbuffer_bits)
 618                 goto unlock;
 619
 620         intel_psr_activate(intel_dp);
 621 unlock:
 622         mutex_unlock(&dev_priv->psr.lock);
 623 }
 624
 625 static void intel_psr_exit(struct drm_device *dev)
 626 {
 627         struct drm_i915_private *dev_priv = dev->dev_private;
 628         struct intel_dp *intel_dp = dev_priv->psr.enabled;
 629         struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
 630         enum pipe pipe = to_intel_crtc(crtc)->pipe;
 631         u32 val;
 632
 633         if (!dev_priv->psr.active)
 634                 return;
 635
 636         if (HAS_DDI(dev)) {
 637                 val = I915_READ(EDP_PSR_CTL);
 638
 639                 WARN_ON(!(val & EDP_PSR_ENABLE));
 640
 641                 I915_WRITE(EDP_PSR_CTL, val & ~EDP_PSR_ENABLE);
 642         } else {
 643                 val = I915_READ(VLV_PSRCTL(pipe));
 644
 645                 /* Here we do the transition from PSR_state 3 to PSR_state 5
 646                  * directly once PSR State 4 that is active with single frame
 647                  * update can be skipped. PSR_state 5 that is PSR exit then
 648                  * Hardware is responsible to transition back to PSR_state 1
 649                  * that is PSR inactive. Same state after
 650                  * vlv_edp_psr_enable_source.
 651                  */
 652                 val &= ~VLV_EDP_PSR_ACTIVE_ENTRY;
 653                 I915_WRITE(VLV_PSRCTL(pipe), val);
 654
 655                 /* Send AUX wake up - Spec says after transitioning to PSR
 656                  * active we have to send AUX wake up by writing 01h in DPCD
 657                  * 600h of sink device.
 658                  * XXX: This might slow down the transition, but without this
 659                  * HW doesn't complete the transition to PSR_state 1 and we
 660                  * never get the screen updated.
 661                  */
 662                 drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
 663                                    DP_SET_POWER_D0);
 664         }
 665
 666         dev_priv->psr.active = false;
 667 }
 668
 669 /**
 670  * intel_psr_single_frame_update - Single Frame Update
 671  * @dev: DRM device
 672  * @frontbuffer_bits: frontbuffer plane tracking bits
 673  *
 674  * Some platforms support a single frame update feature that is used to
 675  * send and update only one frame on Remote Frame Buffer.
 676  * So far it is only implemented for Valleyview and Cherryview because
 677  * hardware requires this to be done before a page flip.
 678  */
 679 void intel_psr_single_frame_update(struct drm_device *dev,
 680                                    unsigned frontbuffer_bits)
 681 {
 682         struct drm_i915_private *dev_priv = dev->dev_private;
 683         struct drm_crtc *crtc;
 684         enum pipe pipe;
 685         u32 val;
 686
 687         /*
 688          * Single frame update is already supported on BDW+ but it requires
 689          * many W/A and it isn't really needed.
 690          */
 691         if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev))
 692                 return;
 693
 694         mutex_lock(&dev_priv->psr.lock);
 695         if (!dev_priv->psr.enabled) {
 696                 mutex_unlock(&dev_priv->psr.lock);
 697                 return;
 698         }
 699
 700         crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
 701         pipe = to_intel_crtc(crtc)->pipe;
 702
 703         if (frontbuffer_bits & INTEL_FRONTBUFFER_ALL_MASK(pipe)) {
 704                 val = I915_READ(VLV_PSRCTL(pipe));
 705
 706                 /*
 707                  * We need to set this bit before writing registers for a flip.
 708                  * This bit will be self-clear when it gets to the PSR active state.
 709                  */
 710                 I915_WRITE(VLV_PSRCTL(pipe), val | VLV_EDP_PSR_SINGLE_FRAME_UPDATE);
 711         }
 712         mutex_unlock(&dev_priv->psr.lock);
 713 }
 714
 715 /**
 716  * intel_psr_invalidate - Invalidade PSR
 717  * @dev: DRM device
 718  * @frontbuffer_bits: frontbuffer plane tracking bits
 719  *
 720  * Since the hardware frontbuffer tracking has gaps we need to integrate
 721  * with the software frontbuffer tracking. This function gets called every
 722  * time frontbuffer rendering starts and a buffer gets dirtied. PSR must be
 723  * disabled if the frontbuffer mask contains a buffer relevant to PSR.
 724  *
 725  * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits."
 726  */
 727 void intel_psr_invalidate(struct drm_device *dev,
 728                           unsigned frontbuffer_bits)
 729 {
 730         struct drm_i915_private *dev_priv = dev->dev_private;
 731         struct drm_crtc *crtc;
 732         enum pipe pipe;
 733
 734         mutex_lock(&dev_priv->psr.lock);
 735         if (!dev_priv->psr.enabled) {
 736                 mutex_unlock(&dev_priv->psr.lock);
 737                 return;
 738         }
 739
 740         crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
 741         pipe = to_intel_crtc(crtc)->pipe;
 742
 743         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
 744         dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits;
 745
 746         if (frontbuffer_bits)
 747                 intel_psr_exit(dev);
 748
 749         mutex_unlock(&dev_priv->psr.lock);
 750 }
 751
 752 /**
 753  * intel_psr_flush - Flush PSR
 754  * @dev: DRM device
 755  * @frontbuffer_bits: frontbuffer plane tracking bits
 756  * @origin: which operation caused the flush
 757  *
 758  * Since the hardware frontbuffer tracking has gaps we need to integrate
 759  * with the software frontbuffer tracking. This function gets called every
 760  * time frontbuffer rendering has completed and flushed out to memory. PSR
 761  * can be enabled again if no other frontbuffer relevant to PSR is dirty.
 762  *
 763  * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits.
 764  */
 765 void intel_psr_flush(struct drm_device *dev,
 766                      unsigned frontbuffer_bits, enum fb_op_origin origin)
 767 {
 768         struct drm_i915_private *dev_priv = dev->dev_private;
 769         struct drm_crtc *crtc;
 770         enum pipe pipe;
 771
 772         mutex_lock(&dev_priv->psr.lock);
 773         if (!dev_priv->psr.enabled) {
 774                 mutex_unlock(&dev_priv->psr.lock);
 775                 return;
 776         }
 777
 778         crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
 779         pipe = to_intel_crtc(crtc)->pipe;
 780
 781         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
 782         dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits;
 783
 784         /* By definition flush = invalidate + flush */
 785         if (frontbuffer_bits)
 786                 intel_psr_exit(dev);
 787
 788         if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
 789                 if (!work_busy(&dev_priv->psr.work.work))
 790                         schedule_delayed_work(&dev_priv->psr.work,
 791                                               msecs_to_jiffies(100));
 792         mutex_unlock(&dev_priv->psr.lock);
 793 }
 794
 795 /**
 796  * intel_psr_init - Init basic PSR work and mutex.
 797  * @dev: DRM device
 798  *
 799  * This function is  called only once at driver load to initialize basic
 800  * PSR stuff.
 801  */
 802 void intel_psr_init(struct drm_device *dev)
 803 {
 804         struct drm_i915_private *dev_priv = dev->dev_private;
 805
 806         dev_priv->psr_mmio_base = IS_HASWELL(dev_priv) ?
 807                 HSW_EDP_PSR_BASE : BDW_EDP_PSR_BASE;
 808
 809         /* Per platform default */
 810         if (i915.enable_psr == -1) {
 811                 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
 812                         i915.enable_psr = 1;
 813                 else
 814                         i915.enable_psr = 0;
 815         }
 816
 817         /* Set link_standby x link_off defaults */
 818         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
 819                 /* HSW and BDW require workarounds that we don't implement. */
 820                 dev_priv->psr.link_standby = false;
 821         else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 822                 /* On VLV and CHV only standby mode is supported. */
 823                 dev_priv->psr.link_standby = true;
 824         else
 825                 /* For new platforms let's respect VBT back again */
 826                 dev_priv->psr.link_standby = dev_priv->vbt.psr.full_link;
 827
 828         /* Override link_standby x link_off defaults */
 829         if (i915.enable_psr == 2 && !dev_priv->psr.link_standby) {
 830                 DRM_DEBUG_KMS("PSR: Forcing link standby\n");
 831                 dev_priv->psr.link_standby = true;
 832         }
 833         if (i915.enable_psr == 3 && dev_priv->psr.link_standby) {
 834                 DRM_DEBUG_KMS("PSR: Forcing main link off\n");
 835                 dev_priv->psr.link_standby = false;
 836         }
 837
 838         INIT_DELAYED_WORK(&dev_priv->psr.work, intel_psr_work);
 839         mutex_init(&dev_priv->psr.lock);
 840 }