drivers/gpu/drm/i915/intel_psr.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 /**
  25  * DOC: Panel Self Refresh (PSR/SRD)
  26  *
  27  * Since Haswell Display controller supports Panel Self-Refresh on display
  28  * panels witch have a remote frame buffer (RFB) implemented according to PSR
  29  * spec in eDP1.3. PSR feature allows the display to go to lower standby states
  30  * when system is idle but display is on as it eliminates display refresh
  31  * request to DDR memory completely as long as the frame buffer for that
  32  * display is unchanged.
  33  *
  34  * Panel Self Refresh must be supported by both Hardware (source) and
  35  * Panel (sink).
  36  *
  37  * PSR saves power by caching the framebuffer in the panel RFB, which allows us
  38  * to power down the link and memory controller. For DSI panels the same idea
  39  * is called "manual mode".
  40  *
  41  * The implementation uses the hardware-based PSR support which automatically
  42  * enters/exits self-refresh mode. The hardware takes care of sending the
  43  * required DP aux message and could even retrain the link (that part isn't
  44  * enabled yet though). The hardware also keeps track of any frontbuffer
  45  * changes to know when to exit self-refresh mode again. Unfortunately that
  46  * part doesn't work too well, hence why the i915 PSR support uses the
  47  * software frontbuffer tracking to make sure it doesn't miss a screen
  48  * update. For this integration intel_psr_invalidate() and intel_psr_flush()
  49  * get called by the frontbuffer tracking code. Note that because of locking
  50  * issues the self-refresh re-enable code is done from a work queue, which
  51  * must be correctly synchronized/cancelled when shutting down the pipe."
  52  */
  53
  54 #include <drm/drmP.h>
  55
  56 #include "intel_drv.h"
  57 #include "i915_drv.h"
  58
  59 static bool is_edp_psr(struct intel_dp *intel_dp)
  60 {
  61         return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
  62 }
  63
  64 static bool vlv_is_psr_active_on_pipe(struct drm_device *dev, int pipe)
  65 {
  66         struct drm_i915_private *dev_priv = dev->dev_private;
  67         uint32_t val;
  68
  69         val = I915_READ(VLV_PSRSTAT(pipe)) &
  70               VLV_EDP_PSR_CURR_STATE_MASK;
  71         return (val == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
  72                (val == VLV_EDP_PSR_ACTIVE_SF_UPDATE);
  73 }
  74
  75 static void intel_psr_write_vsc(struct intel_dp *intel_dp,
  76                                 const struct edp_vsc_psr *vsc_psr)
  77 {
  78         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
  79         struct drm_device *dev = dig_port->base.base.dev;
  80         struct drm_i915_private *dev_priv = dev->dev_private;
  81         struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
  82         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
  83         i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
  84         uint32_t *data = (uint32_t *) vsc_psr;
  85         unsigned int i;
  86
  87         /* As per BSPec (Pipe Video Data Island Packet), we need to disable
  88            the video DIP being updated before program video DIP data buffer
  89            registers for DIP being updated. */
  90         I915_WRITE(ctl_reg, 0);
  91         POSTING_READ(ctl_reg);
  92
  93         for (i = 0; i < sizeof(*vsc_psr); i += 4) {
  94                 I915_WRITE(HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder,
  95                                                    i >> 2), *data);
  96                 data++;
  97         }
  98         for (; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4)
  99                 I915_WRITE(HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder,
 100                                                    i >> 2), 0);
 101
 102         I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
 103         POSTING_READ(ctl_reg);
 104 }
 105
 106 static void vlv_psr_setup_vsc(struct intel_dp *intel_dp)
 107 {
 108         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 109         struct drm_device *dev = intel_dig_port->base.base.dev;
 110         struct drm_i915_private *dev_priv = dev->dev_private;
 111         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
 112         enum pipe pipe = to_intel_crtc(crtc)->pipe;
 113         uint32_t val;
 114
 115         /* VLV auto-generate VSC package as per EDP 1.3 spec, Table 3.10 */
 116         val  = I915_READ(VLV_VSCSDP(pipe));
 117         val &= ~VLV_EDP_PSR_SDP_FREQ_MASK;
 118         val |= VLV_EDP_PSR_SDP_FREQ_EVFRAME;
 119         I915_WRITE(VLV_VSCSDP(pipe), val);
 120 }
 121
 122 static void skl_psr_setup_su_vsc(struct intel_dp *intel_dp)
 123 {
 124         struct edp_vsc_psr psr_vsc;
 125
 126         /* Prepare VSC Header for SU as per EDP 1.4 spec, Table 6.11 */
 127         memset(&psr_vsc, 0, sizeof(psr_vsc));
 128         psr_vsc.sdp_header.HB0 = 0;
 129         psr_vsc.sdp_header.HB1 = 0x7;
 130         psr_vsc.sdp_header.HB2 = 0x3;
 131         psr_vsc.sdp_header.HB3 = 0xb;
 132         intel_psr_write_vsc(intel_dp, &psr_vsc);
 133 }
 134
 135 static void hsw_psr_setup_vsc(struct intel_dp *intel_dp)
 136 {
 137         struct edp_vsc_psr psr_vsc;
 138
 139         /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
 140         memset(&psr_vsc, 0, sizeof(psr_vsc));
 141         psr_vsc.sdp_header.HB0 = 0;
 142         psr_vsc.sdp_header.HB1 = 0x7;
 143         psr_vsc.sdp_header.HB2 = 0x2;
 144         psr_vsc.sdp_header.HB3 = 0x8;
 145         intel_psr_write_vsc(intel_dp, &psr_vsc);
 146 }
 147
 148 static void vlv_psr_enable_sink(struct intel_dp *intel_dp)
 149 {
 150         drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
 151                            DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
 152 }
 153
 154 static i915_reg_t psr_aux_ctl_reg(struct drm_i915_private *dev_priv,
 155                                        enum port port)
 156 {
 157         if (INTEL_INFO(dev_priv)->gen >= 9)
 158                 return DP_AUX_CH_CTL(port);
 159         else
 160                 return EDP_PSR_AUX_CTL;
 161 }
 162
 163 static i915_reg_t psr_aux_data_reg(struct drm_i915_private *dev_priv,
 164                                         enum port port, int index)
 165 {
 166         if (INTEL_INFO(dev_priv)->gen >= 9)
 167                 return DP_AUX_CH_DATA(port, index);
 168         else
 169                 return EDP_PSR_AUX_DATA(index);
 170 }
 171
 172 static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
 173 {
 174         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 175         struct drm_device *dev = dig_port->base.base.dev;
 176         struct drm_i915_private *dev_priv = dev->dev_private;
 177         uint32_t aux_clock_divider;
 178         i915_reg_t aux_ctl_reg;
 179         int precharge = 0x3;
 180         static const uint8_t aux_msg[] = {
 181                 [0] = DP_AUX_NATIVE_WRITE << 4,
 182                 [1] = DP_SET_POWER >> 8,
 183                 [2] = DP_SET_POWER & 0xff,
 184                 [3] = 1 - 1,
 185                 [4] = DP_SET_POWER_D0,
 186         };
 187         enum port port = dig_port->port;
 188         int i;
 189
 190         BUILD_BUG_ON(sizeof(aux_msg) > 20);
 191
 192         aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
 193
 194         /* Enable AUX frame sync at sink */
 195         if (dev_priv->psr.aux_frame_sync)
 196                 drm_dp_dpcd_writeb(&intel_dp->aux,
 197                                 DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF,
 198                                 DP_AUX_FRAME_SYNC_ENABLE);
 199
 200         aux_ctl_reg = psr_aux_ctl_reg(dev_priv, port);
 201
 202         /* Setup AUX registers */
 203         for (i = 0; i < sizeof(aux_msg); i += 4)
 204                 I915_WRITE(psr_aux_data_reg(dev_priv, port, i >> 2),
 205                            intel_dp_pack_aux(&aux_msg[i], sizeof(aux_msg) - i));
 206
 207         if (INTEL_INFO(dev)->gen >= 9) {
 208                 uint32_t val;
 209
 210                 val = I915_READ(aux_ctl_reg);
 211                 val &= ~DP_AUX_CH_CTL_TIME_OUT_MASK;
 212                 val |= DP_AUX_CH_CTL_TIME_OUT_1600us;
 213                 val &= ~DP_AUX_CH_CTL_MESSAGE_SIZE_MASK;
 214                 val |= (sizeof(aux_msg) << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
 215                 /* Use hardcoded data values for PSR, frame sync and GTC */
 216                 val &= ~DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL;
 217                 val &= ~DP_AUX_CH_CTL_FS_DATA_AUX_REG_SKL;
 218                 val &= ~DP_AUX_CH_CTL_GTC_DATA_AUX_REG_SKL;
 219                 I915_WRITE(aux_ctl_reg, val);
 220         } else {
 221                 I915_WRITE(aux_ctl_reg,
 222                    DP_AUX_CH_CTL_TIME_OUT_400us |
 223                    (sizeof(aux_msg) << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 224                    (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 225                    (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
 226         }
 227
 228         if (dev_priv->psr.link_standby)
 229                 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
 230                                    DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
 231         else
 232                 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
 233                                    DP_PSR_ENABLE);
 234 }
 235
 236 static void vlv_psr_enable_source(struct intel_dp *intel_dp)
 237 {
 238         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 239         struct drm_device *dev = dig_port->base.base.dev;
 240         struct drm_i915_private *dev_priv = dev->dev_private;
 241         struct drm_crtc *crtc = dig_port->base.base.crtc;
 242         enum pipe pipe = to_intel_crtc(crtc)->pipe;
 243
 244         /* Transition from PSR_state 0 to PSR_state 1, i.e. PSR Inactive */
 245         I915_WRITE(VLV_PSRCTL(pipe),
 246                    VLV_EDP_PSR_MODE_SW_TIMER |
 247                    VLV_EDP_PSR_SRC_TRANSMITTER_STATE |
 248                    VLV_EDP_PSR_ENABLE);
 249 }
 250
 251 static void vlv_psr_activate(struct intel_dp *intel_dp)
 252 {
 253         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 254         struct drm_device *dev = dig_port->base.base.dev;
 255         struct drm_i915_private *dev_priv = dev->dev_private;
 256         struct drm_crtc *crtc = dig_port->base.base.crtc;
 257         enum pipe pipe = to_intel_crtc(crtc)->pipe;
 258
 259         /* Let's do the transition from PSR_state 1 to PSR_state 2
 260          * that is PSR transition to active - static frame transmission.
 261          * Then Hardware is responsible for the transition to PSR_state 3
 262          * that is PSR active - no Remote Frame Buffer (RFB) update.
 263          */
 264         I915_WRITE(VLV_PSRCTL(pipe), I915_READ(VLV_PSRCTL(pipe)) |
 265                    VLV_EDP_PSR_ACTIVE_ENTRY);
 266 }
 267
 268 static void hsw_psr_enable_source(struct intel_dp *intel_dp)
 269 {
 270         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 271         struct drm_device *dev = dig_port->base.base.dev;
 272         struct drm_i915_private *dev_priv = dev->dev_private;
 273
 274         uint32_t max_sleep_time = 0x1f;
 275         /*
 276          * Let's respect VBT in case VBT asks a higher idle_frame value.
 277          * Let's use 6 as the minimum to cover all known cases including
 278          * the off-by-one issue that HW has in some cases. Also there are
 279          * cases where sink should be able to train
 280          * with the 5 or 6 idle patterns.
 281          */
 282         uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
 283         uint32_t val = EDP_PSR_ENABLE;
 284
 285         val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT;
 286         val |= idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
 287
 288         if (IS_HASWELL(dev))
 289                 val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
 290
 291         if (dev_priv->psr.link_standby)
 292                 val |= EDP_PSR_LINK_STANDBY;
 293
 294         if (dev_priv->vbt.psr.tp1_wakeup_time > 5)
 295                 val |= EDP_PSR_TP1_TIME_2500us;
 296         else if (dev_priv->vbt.psr.tp1_wakeup_time > 1)
 297                 val |= EDP_PSR_TP1_TIME_500us;
 298         else if (dev_priv->vbt.psr.tp1_wakeup_time > 0)
 299                 val |= EDP_PSR_TP1_TIME_100us;
 300         else
 301                 val |= EDP_PSR_TP1_TIME_0us;
 302
 303         if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
 304                 val |= EDP_PSR_TP2_TP3_TIME_2500us;
 305         else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
 306                 val |= EDP_PSR_TP2_TP3_TIME_500us;
 307         else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
 308                 val |= EDP_PSR_TP2_TP3_TIME_100us;
 309         else
 310                 val |= EDP_PSR_TP2_TP3_TIME_0us;
 311
 312         if (intel_dp_source_supports_hbr2(intel_dp) &&
 313             drm_dp_tps3_supported(intel_dp->dpcd))
 314                 val |= EDP_PSR_TP1_TP3_SEL;
 315         else
 316                 val |= EDP_PSR_TP1_TP2_SEL;
 317
 318         I915_WRITE(EDP_PSR_CTL, val);
 319
 320         if (!dev_priv->psr.psr2_support)
 321                 return;
 322
 323         /* FIXME: selective update is probably totally broken because it doesn't
 324          * mesh at all with our frontbuffer tracking. And the hw alone isn't
 325          * good enough. */
 326         val = EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE;
 327
 328         if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
 329                 val |= EDP_PSR2_TP2_TIME_2500;
 330         else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
 331                 val |= EDP_PSR2_TP2_TIME_500;
 332         else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
 333                 val |= EDP_PSR2_TP2_TIME_100;
 334         else
 335                 val |= EDP_PSR2_TP2_TIME_50;
 336
 337         I915_WRITE(EDP_PSR2_CTL, val);
 338 }
 339
 340 static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
 341 {
 342         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 343         struct drm_device *dev = dig_port->base.base.dev;
 344         struct drm_i915_private *dev_priv = dev->dev_private;
 345         struct drm_crtc *crtc = dig_port->base.base.crtc;
 346         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 347
 348         lockdep_assert_held(&dev_priv->psr.lock);
 349         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
 350         WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
 351
 352         dev_priv->psr.source_ok = false;
 353
 354         /*
 355          * HSW spec explicitly says PSR is tied to port A.
 356          * BDW+ platforms with DDI implementation of PSR have different
 357          * PSR registers per transcoder and we only implement transcoder EDP
 358          * ones. Since by Display design transcoder EDP is tied to port A
 359          * we can safely escape based on the port A.
 360          */
 361         if (HAS_DDI(dev) && dig_port->port != PORT_A) {
 362                 DRM_DEBUG_KMS("PSR condition failed: Port not supported\n");
 363                 return false;
 364         }
 365
 366         if (!i915.enable_psr) {
 367                 DRM_DEBUG_KMS("PSR disable by flag\n");
 368                 return false;
 369         }
 370
 371         if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
 372             !dev_priv->psr.link_standby) {
 373                 DRM_ERROR("PSR condition failed: Link off requested but not supported on this platform\n");
 374                 return false;
 375         }
 376
 377         if (IS_HASWELL(dev) &&
 378             I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config->cpu_transcoder)) &
 379                       S3D_ENABLE) {
 380                 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
 381                 return false;
 382         }
 383
 384         if (IS_HASWELL(dev) &&
 385             intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
 386                 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
 387                 return false;
 388         }
 389
 390         dev_priv->psr.source_ok = true;
 391         return true;
 392 }
 393
 394 static void intel_psr_activate(struct intel_dp *intel_dp)
 395 {
 396         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 397         struct drm_device *dev = intel_dig_port->base.base.dev;
 398         struct drm_i915_private *dev_priv = dev->dev_private;
 399
 400         WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE);
 401         WARN_ON(dev_priv->psr.active);
 402         lockdep_assert_held(&dev_priv->psr.lock);
 403
 404         /* Enable/Re-enable PSR on the host */
 405         if (HAS_DDI(dev))
 406                 /* On HSW+ after we enable PSR on source it will activate it
 407                  * as soon as it match configure idle_frame count. So
 408                  * we just actually enable it here on activation time.
 409                  */
 410                 hsw_psr_enable_source(intel_dp);
 411         else
 412                 vlv_psr_activate(intel_dp);
 413
 414         dev_priv->psr.active = true;
 415 }
 416
 417 /**
 418  * intel_psr_enable - Enable PSR
 419  * @intel_dp: Intel DP
 420  *
 421  * This function can only be called after the pipe is fully trained and enabled.
 422  */
 423 void intel_psr_enable(struct intel_dp *intel_dp)
 424 {
 425         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 426         struct drm_device *dev = intel_dig_port->base.base.dev;
 427         struct drm_i915_private *dev_priv = dev->dev_private;
 428         struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
 429
 430         if (!HAS_PSR(dev)) {
 431                 DRM_DEBUG_KMS("PSR not supported on this platform\n");
 432                 return;
 433         }
 434
 435         if (!is_edp_psr(intel_dp)) {
 436                 DRM_DEBUG_KMS("PSR not supported by this panel\n");
 437                 return;
 438         }
 439
 440         mutex_lock(&dev_priv->psr.lock);
 441         if (dev_priv->psr.enabled) {
 442                 DRM_DEBUG_KMS("PSR already in use\n");
 443                 goto unlock;
 444         }
 445
 446         if (!intel_psr_match_conditions(intel_dp))
 447                 goto unlock;
 448
 449         dev_priv->psr.busy_frontbuffer_bits = 0;
 450
 451         if (HAS_DDI(dev)) {
 452                 hsw_psr_setup_vsc(intel_dp);
 453
 454                 if (dev_priv->psr.psr2_support) {
 455                         /* PSR2 is restricted to work with panel resolutions upto 3200x2000 */
 456                         if (crtc->config->pipe_src_w > 3200 ||
 457                                 crtc->config->pipe_src_h > 2000)
 458                                 dev_priv->psr.psr2_support = false;
 459                         else
 460                                 skl_psr_setup_su_vsc(intel_dp);
 461                 }
 462
 463                 /*
 464                  * Per Spec: Avoid continuous PSR exit by masking MEMUP and HPD.
 465                  * Also mask LPSP to avoid dependency on other drivers that
 466                  * might block runtime_pm besides preventing other hw tracking
 467                  * issues now we can rely on frontbuffer tracking.
 468                  */
 469                 I915_WRITE(EDP_PSR_DEBUG_CTL, EDP_PSR_DEBUG_MASK_MEMUP |
 470                            EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
 471
 472                 /* Enable PSR on the panel */
 473                 hsw_psr_enable_sink(intel_dp);
 474
 475                 if (INTEL_INFO(dev)->gen >= 9)
 476                         intel_psr_activate(intel_dp);
 477         } else {
 478                 vlv_psr_setup_vsc(intel_dp);
 479
 480                 /* Enable PSR on the panel */
 481                 vlv_psr_enable_sink(intel_dp);
 482
 483                 /* On HSW+ enable_source also means go to PSR entry/active
 484                  * state as soon as idle_frame achieved and here would be
 485                  * to soon. However on VLV enable_source just enable PSR
 486                  * but let it on inactive state. So we might do this prior
 487                  * to active transition, i.e. here.
 488                  */
 489                 vlv_psr_enable_source(intel_dp);
 490         }
 491
 492         /*
 493          * FIXME: Activation should happen immediately since this function
 494          * is just called after pipe is fully trained and enabled.
 495          * However on every platform we face issues when first activation
 496          * follows a modeset so quickly.
 497          *     - On VLV/CHV we get bank screen on first activation
 498          *     - On HSW/BDW we get a recoverable frozen screen until next
 499          *       exit-activate sequence.
 500          */
 501         if (INTEL_INFO(dev)->gen < 9)
 502                 schedule_delayed_work(&dev_priv->psr.work,
 503                                       msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
 504
 505         dev_priv->psr.enabled = intel_dp;
 506 unlock:
 507         mutex_unlock(&dev_priv->psr.lock);
 508 }
 509
 510 static void vlv_psr_disable(struct intel_dp *intel_dp)
 511 {
 512         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 513         struct drm_device *dev = intel_dig_port->base.base.dev;
 514         struct drm_i915_private *dev_priv = dev->dev_private;
 515         struct intel_crtc *intel_crtc =
 516                 to_intel_crtc(intel_dig_port->base.base.crtc);
 517         uint32_t val;
 518
 519         if (dev_priv->psr.active) {
 520                 /* Put VLV PSR back to PSR_state 0 that is PSR Disabled. */
 521                 if (wait_for((I915_READ(VLV_PSRSTAT(intel_crtc->pipe)) &
 522                               VLV_EDP_PSR_IN_TRANS) == 0, 1))
 523                         WARN(1, "PSR transition took longer than expected\n");
 524
 525                 val = I915_READ(VLV_PSRCTL(intel_crtc->pipe));
 526                 val &= ~VLV_EDP_PSR_ACTIVE_ENTRY;
 527                 val &= ~VLV_EDP_PSR_ENABLE;
 528                 val &= ~VLV_EDP_PSR_MODE_MASK;
 529                 I915_WRITE(VLV_PSRCTL(intel_crtc->pipe), val);
 530
 531                 dev_priv->psr.active = false;
 532         } else {
 533                 WARN_ON(vlv_is_psr_active_on_pipe(dev, intel_crtc->pipe));
 534         }
 535 }
 536
 537 static void hsw_psr_disable(struct intel_dp *intel_dp)
 538 {
 539         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 540         struct drm_device *dev = intel_dig_port->base.base.dev;
 541         struct drm_i915_private *dev_priv = dev->dev_private;
 542
 543         if (dev_priv->psr.active) {
 544                 I915_WRITE(EDP_PSR_CTL,
 545                            I915_READ(EDP_PSR_CTL) & ~EDP_PSR_ENABLE);
 546
 547                 /* Wait till PSR is idle */
 548                 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL) &
 549                                EDP_PSR_STATUS_STATE_MASK) == 0,
 550                                2 * USEC_PER_SEC, 10 * USEC_PER_MSEC))
 551                         DRM_ERROR("Timed out waiting for PSR Idle State\n");
 552
 553                 dev_priv->psr.active = false;
 554         } else {
 555                 WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE);
 556         }
 557 }
 558
 559 /**
 560  * intel_psr_disable - Disable PSR
 561  * @intel_dp: Intel DP
 562  *
 563  * This function needs to be called before disabling pipe.
 564  */
 565 void intel_psr_disable(struct intel_dp *intel_dp)
 566 {
 567         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 568         struct drm_device *dev = intel_dig_port->base.base.dev;
 569         struct drm_i915_private *dev_priv = dev->dev_private;
 570
 571         mutex_lock(&dev_priv->psr.lock);
 572         if (!dev_priv->psr.enabled) {
 573                 mutex_unlock(&dev_priv->psr.lock);
 574                 return;
 575         }
 576
 577         /* Disable PSR on Source */
 578         if (HAS_DDI(dev))
 579                 hsw_psr_disable(intel_dp);
 580         else
 581                 vlv_psr_disable(intel_dp);
 582
 583         /* Disable PSR on Sink */
 584         drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0);
 585
 586         dev_priv->psr.enabled = NULL;
 587         mutex_unlock(&dev_priv->psr.lock);
 588
 589         cancel_delayed_work_sync(&dev_priv->psr.work);
 590 }
 591
 592 static void intel_psr_work(struct work_struct *work)
 593 {
 594         struct drm_i915_private *dev_priv =
 595                 container_of(work, typeof(*dev_priv), psr.work.work);
 596         struct intel_dp *intel_dp = dev_priv->psr.enabled;
 597         struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
 598         enum pipe pipe = to_intel_crtc(crtc)->pipe;
 599
 600         /* We have to make sure PSR is ready for re-enable
 601          * otherwise it keeps disabled until next full enable/disable cycle.
 602          * PSR might take some time to get fully disabled
 603          * and be ready for re-enable.
 604          */
 605         if (HAS_DDI(dev_priv)) {
 606                 if (wait_for((I915_READ(EDP_PSR_STATUS_CTL) &
 607                               EDP_PSR_STATUS_STATE_MASK) == 0, 50)) {
 608                         DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
 609                         return;
 610                 }
 611         } else {
 612                 if (wait_for((I915_READ(VLV_PSRSTAT(pipe)) &
 613                               VLV_EDP_PSR_IN_TRANS) == 0, 1)) {
 614                         DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
 615                         return;
 616                 }
 617         }
 618         mutex_lock(&dev_priv->psr.lock);
 619         intel_dp = dev_priv->psr.enabled;
 620
 621         if (!intel_dp)
 622                 goto unlock;
 623
 624         /*
 625          * The delayed work can race with an invalidate hence we need to
 626          * recheck. Since psr_flush first clears this and then reschedules we
 627          * won't ever miss a flush when bailing out here.
 628          */
 629         if (dev_priv->psr.busy_frontbuffer_bits)
 630                 goto unlock;
 631
 632         intel_psr_activate(intel_dp);
 633 unlock:
 634         mutex_unlock(&dev_priv->psr.lock);
 635 }
 636
 637 static void intel_psr_exit(struct drm_device *dev)
 638 {
 639         struct drm_i915_private *dev_priv = dev->dev_private;
 640         struct intel_dp *intel_dp = dev_priv->psr.enabled;
 641         struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
 642         enum pipe pipe = to_intel_crtc(crtc)->pipe;
 643         u32 val;
 644
 645         if (!dev_priv->psr.active)
 646                 return;
 647
 648         if (HAS_DDI(dev)) {
 649                 val = I915_READ(EDP_PSR_CTL);
 650
 651                 WARN_ON(!(val & EDP_PSR_ENABLE));
 652
 653                 I915_WRITE(EDP_PSR_CTL, val & ~EDP_PSR_ENABLE);
 654         } else {
 655                 val = I915_READ(VLV_PSRCTL(pipe));
 656
 657                 /* Here we do the transition from PSR_state 3 to PSR_state 5
 658                  * directly once PSR State 4 that is active with single frame
 659                  * update can be skipped. PSR_state 5 that is PSR exit then
 660                  * Hardware is responsible to transition back to PSR_state 1
 661                  * that is PSR inactive. Same state after
 662                  * vlv_edp_psr_enable_source.
 663                  */
 664                 val &= ~VLV_EDP_PSR_ACTIVE_ENTRY;
 665                 I915_WRITE(VLV_PSRCTL(pipe), val);
 666
 667                 /* Send AUX wake up - Spec says after transitioning to PSR
 668                  * active we have to send AUX wake up by writing 01h in DPCD
 669                  * 600h of sink device.
 670                  * XXX: This might slow down the transition, but without this
 671                  * HW doesn't complete the transition to PSR_state 1 and we
 672                  * never get the screen updated.
 673                  */
 674                 drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
 675                                    DP_SET_POWER_D0);
 676         }
 677
 678         dev_priv->psr.active = false;
 679 }
 680
 681 /**
 682  * intel_psr_single_frame_update - Single Frame Update
 683  * @dev: DRM device
 684  * @frontbuffer_bits: frontbuffer plane tracking bits
 685  *
 686  * Some platforms support a single frame update feature that is used to
 687  * send and update only one frame on Remote Frame Buffer.
 688  * So far it is only implemented for Valleyview and Cherryview because
 689  * hardware requires this to be done before a page flip.
 690  */
 691 void intel_psr_single_frame_update(struct drm_device *dev,
 692                                    unsigned frontbuffer_bits)
 693 {
 694         struct drm_i915_private *dev_priv = dev->dev_private;
 695         struct drm_crtc *crtc;
 696         enum pipe pipe;
 697         u32 val;
 698
 699         /*
 700          * Single frame update is already supported on BDW+ but it requires
 701          * many W/A and it isn't really needed.
 702          */
 703         if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev))
 704                 return;
 705
 706         mutex_lock(&dev_priv->psr.lock);
 707         if (!dev_priv->psr.enabled) {
 708                 mutex_unlock(&dev_priv->psr.lock);
 709                 return;
 710         }
 711
 712         crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
 713         pipe = to_intel_crtc(crtc)->pipe;
 714
 715         if (frontbuffer_bits & INTEL_FRONTBUFFER_ALL_MASK(pipe)) {
 716                 val = I915_READ(VLV_PSRCTL(pipe));
 717
 718                 /*
 719                  * We need to set this bit before writing registers for a flip.
 720                  * This bit will be self-clear when it gets to the PSR active state.
 721                  */
 722                 I915_WRITE(VLV_PSRCTL(pipe), val | VLV_EDP_PSR_SINGLE_FRAME_UPDATE);
 723         }
 724         mutex_unlock(&dev_priv->psr.lock);
 725 }
 726
 727 /**
 728  * intel_psr_invalidate - Invalidade PSR
 729  * @dev: DRM device
 730  * @frontbuffer_bits: frontbuffer plane tracking bits
 731  *
 732  * Since the hardware frontbuffer tracking has gaps we need to integrate
 733  * with the software frontbuffer tracking. This function gets called every
 734  * time frontbuffer rendering starts and a buffer gets dirtied. PSR must be
 735  * disabled if the frontbuffer mask contains a buffer relevant to PSR.
 736  *
 737  * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits."
 738  */
 739 void intel_psr_invalidate(struct drm_device *dev,
 740                           unsigned frontbuffer_bits)
 741 {
 742         struct drm_i915_private *dev_priv = dev->dev_private;
 743         struct drm_crtc *crtc;
 744         enum pipe pipe;
 745
 746         mutex_lock(&dev_priv->psr.lock);
 747         if (!dev_priv->psr.enabled) {
 748                 mutex_unlock(&dev_priv->psr.lock);
 749                 return;
 750         }
 751
 752         crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
 753         pipe = to_intel_crtc(crtc)->pipe;
 754
 755         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
 756         dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits;
 757
 758         if (frontbuffer_bits)
 759                 intel_psr_exit(dev);
 760
 761         mutex_unlock(&dev_priv->psr.lock);
 762 }
 763
 764 /**
 765  * intel_psr_flush - Flush PSR
 766  * @dev: DRM device
 767  * @frontbuffer_bits: frontbuffer plane tracking bits
 768  * @origin: which operation caused the flush
 769  *
 770  * Since the hardware frontbuffer tracking has gaps we need to integrate
 771  * with the software frontbuffer tracking. This function gets called every
 772  * time frontbuffer rendering has completed and flushed out to memory. PSR
 773  * can be enabled again if no other frontbuffer relevant to PSR is dirty.
 774  *
 775  * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits.
 776  */
 777 void intel_psr_flush(struct drm_device *dev,
 778                      unsigned frontbuffer_bits, enum fb_op_origin origin)
 779 {
 780         struct drm_i915_private *dev_priv = dev->dev_private;
 781         struct drm_crtc *crtc;
 782         enum pipe pipe;
 783
 784         mutex_lock(&dev_priv->psr.lock);
 785         if (!dev_priv->psr.enabled) {
 786                 mutex_unlock(&dev_priv->psr.lock);
 787                 return;
 788         }
 789
 790         crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
 791         pipe = to_intel_crtc(crtc)->pipe;
 792
 793         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
 794         dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits;
 795
 796         /* By definition flush = invalidate + flush */
 797         if (frontbuffer_bits)
 798                 intel_psr_exit(dev);
 799
 800         if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
 801                 if (!work_busy(&dev_priv->psr.work.work))
 802                         schedule_delayed_work(&dev_priv->psr.work,
 803                                               msecs_to_jiffies(100));
 804         mutex_unlock(&dev_priv->psr.lock);
 805 }
 806
 807 /**
 808  * intel_psr_init - Init basic PSR work and mutex.
 809  * @dev: DRM device
 810  *
 811  * This function is  called only once at driver load to initialize basic
 812  * PSR stuff.
 813  */
 814 void intel_psr_init(struct drm_device *dev)
 815 {
 816         struct drm_i915_private *dev_priv = dev->dev_private;
 817
 818         dev_priv->psr_mmio_base = IS_HASWELL(dev_priv) ?
 819                 HSW_EDP_PSR_BASE : BDW_EDP_PSR_BASE;
 820
 821         /* Per platform default */
 822         if (i915.enable_psr == -1) {
 823                 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
 824                         i915.enable_psr = 1;
 825                 else
 826                         i915.enable_psr = 0;
 827         }
 828
 829         /* Set link_standby x link_off defaults */
 830         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
 831                 /* HSW and BDW require workarounds that we don't implement. */
 832                 dev_priv->psr.link_standby = false;
 833         else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 834                 /* On VLV and CHV only standby mode is supported. */
 835                 dev_priv->psr.link_standby = true;
 836         else
 837                 /* For new platforms let's respect VBT back again */
 838                 dev_priv->psr.link_standby = dev_priv->vbt.psr.full_link;
 839
 840         /* Override link_standby x link_off defaults */
 841         if (i915.enable_psr == 2 && !dev_priv->psr.link_standby) {
 842                 DRM_DEBUG_KMS("PSR: Forcing link standby\n");
 843                 dev_priv->psr.link_standby = true;
 844         }
 845         if (i915.enable_psr == 3 && dev_priv->psr.link_standby) {
 846                 DRM_DEBUG_KMS("PSR: Forcing main link off\n");
 847                 dev_priv->psr.link_standby = false;
 848         }
 849
 850         INIT_DELAYED_WORK(&dev_priv->psr.work, intel_psr_work);
 851         mutex_init(&dev_priv->psr.lock);
 852 }