2 * Copyright © 2008-2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
32 #include <drm/i915_drm.h>
33 #include "i915_trace.h"
34 #include "intel_drv.h"
36 /* Early gen2 devices have a cacheline of just 32 bytes, using 64 is overkill,
37 * but keeps the logic simple. Indeed, the whole purpose of this macro is just
38 * to give some inclination as to some of the magic values used in the various
41 #define CACHELINE_BYTES 64
43 static inline int __ring_space(int head, int tail, int size)
45 int space = head - (tail + I915_RING_FREE_SPACE);
51 static inline int ring_space(struct intel_ringbuffer *ringbuf)
53 return __ring_space(ringbuf->head & HEAD_ADDR, ringbuf->tail, ringbuf->size);
56 static bool intel_ring_stopped(struct intel_engine_cs *ring)
58 struct drm_i915_private *dev_priv = ring->dev->dev_private;
59 return dev_priv->gpu_error.stop_rings & intel_ring_flag(ring);
62 void __intel_ring_advance(struct intel_engine_cs *ring)
64 struct intel_ringbuffer *ringbuf = ring->buffer;
65 ringbuf->tail &= ringbuf->size - 1;
66 if (intel_ring_stopped(ring))
68 ring->write_tail(ring, ringbuf->tail);
72 gen2_render_ring_flush(struct intel_engine_cs *ring,
73 u32 invalidate_domains,
80 if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
81 cmd |= MI_NO_WRITE_FLUSH;
83 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
86 ret = intel_ring_begin(ring, 2);
90 intel_ring_emit(ring, cmd);
91 intel_ring_emit(ring, MI_NOOP);
92 intel_ring_advance(ring);
98 gen4_render_ring_flush(struct intel_engine_cs *ring,
99 u32 invalidate_domains,
102 struct drm_device *dev = ring->dev;
109 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
110 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
111 * also flushed at 2d versus 3d pipeline switches.
115 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
116 * MI_READ_FLUSH is set, and is always flushed on 965.
118 * I915_GEM_DOMAIN_COMMAND may not exist?
120 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
121 * invalidated when MI_EXE_FLUSH is set.
123 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
124 * invalidated with every MI_FLUSH.
128 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
129 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
130 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
131 * are flushed at any MI_FLUSH.
134 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
135 if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
136 cmd &= ~MI_NO_WRITE_FLUSH;
137 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
140 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
141 (IS_G4X(dev) || IS_GEN5(dev)))
142 cmd |= MI_INVALIDATE_ISP;
144 ret = intel_ring_begin(ring, 2);
148 intel_ring_emit(ring, cmd);
149 intel_ring_emit(ring, MI_NOOP);
150 intel_ring_advance(ring);
156 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
157 * implementing two workarounds on gen6. From section 1.4.7.1
158 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
160 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
161 * produced by non-pipelined state commands), software needs to first
162 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
165 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
166 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
168 * And the workaround for these two requires this workaround first:
170 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
171 * BEFORE the pipe-control with a post-sync op and no write-cache
174 * And this last workaround is tricky because of the requirements on
175 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
178 * "1 of the following must also be set:
179 * - Render Target Cache Flush Enable ([12] of DW1)
180 * - Depth Cache Flush Enable ([0] of DW1)
181 * - Stall at Pixel Scoreboard ([1] of DW1)
182 * - Depth Stall ([13] of DW1)
183 * - Post-Sync Operation ([13] of DW1)
184 * - Notify Enable ([8] of DW1)"
186 * The cache flushes require the workaround flush that triggered this
187 * one, so we can't use it. Depth stall would trigger the same.
188 * Post-sync nonzero is what triggered this second workaround, so we
189 * can't use that one either. Notify enable is IRQs, which aren't
190 * really our business. That leaves only stall at scoreboard.
193 intel_emit_post_sync_nonzero_flush(struct intel_engine_cs *ring)
195 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
199 ret = intel_ring_begin(ring, 6);
203 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
204 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
205 PIPE_CONTROL_STALL_AT_SCOREBOARD);
206 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
207 intel_ring_emit(ring, 0); /* low dword */
208 intel_ring_emit(ring, 0); /* high dword */
209 intel_ring_emit(ring, MI_NOOP);
210 intel_ring_advance(ring);
212 ret = intel_ring_begin(ring, 6);
216 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
217 intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
218 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
219 intel_ring_emit(ring, 0);
220 intel_ring_emit(ring, 0);
221 intel_ring_emit(ring, MI_NOOP);
222 intel_ring_advance(ring);
228 gen6_render_ring_flush(struct intel_engine_cs *ring,
229 u32 invalidate_domains, u32 flush_domains)
232 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
235 /* Force SNB workarounds for PIPE_CONTROL flushes */
236 ret = intel_emit_post_sync_nonzero_flush(ring);
240 /* Just flush everything. Experiments have shown that reducing the
241 * number of bits based on the write domains has little performance
245 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
246 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
248 * Ensure that any following seqno writes only happen
249 * when the render cache is indeed flushed.
251 flags |= PIPE_CONTROL_CS_STALL;
253 if (invalidate_domains) {
254 flags |= PIPE_CONTROL_TLB_INVALIDATE;
255 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
256 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
257 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
258 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
259 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
261 * TLB invalidate requires a post-sync write.
263 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
266 ret = intel_ring_begin(ring, 4);
270 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
271 intel_ring_emit(ring, flags);
272 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
273 intel_ring_emit(ring, 0);
274 intel_ring_advance(ring);
280 gen7_render_ring_cs_stall_wa(struct intel_engine_cs *ring)
284 ret = intel_ring_begin(ring, 4);
288 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
289 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
290 PIPE_CONTROL_STALL_AT_SCOREBOARD);
291 intel_ring_emit(ring, 0);
292 intel_ring_emit(ring, 0);
293 intel_ring_advance(ring);
298 static int gen7_ring_fbc_flush(struct intel_engine_cs *ring, u32 value)
302 if (!ring->fbc_dirty)
305 ret = intel_ring_begin(ring, 6);
308 /* WaFbcNukeOn3DBlt:ivb/hsw */
309 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
310 intel_ring_emit(ring, MSG_FBC_REND_STATE);
311 intel_ring_emit(ring, value);
312 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | MI_SRM_LRM_GLOBAL_GTT);
313 intel_ring_emit(ring, MSG_FBC_REND_STATE);
314 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
315 intel_ring_advance(ring);
317 ring->fbc_dirty = false;
322 gen7_render_ring_flush(struct intel_engine_cs *ring,
323 u32 invalidate_domains, u32 flush_domains)
326 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
330 * Ensure that any following seqno writes only happen when the render
331 * cache is indeed flushed.
333 * Workaround: 4th PIPE_CONTROL command (except the ones with only
334 * read-cache invalidate bits set) must have the CS_STALL bit set. We
335 * don't try to be clever and just set it unconditionally.
337 flags |= PIPE_CONTROL_CS_STALL;
339 /* Just flush everything. Experiments have shown that reducing the
340 * number of bits based on the write domains has little performance
344 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
345 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
347 if (invalidate_domains) {
348 flags |= PIPE_CONTROL_TLB_INVALIDATE;
349 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
350 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
351 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
352 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
353 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
355 * TLB invalidate requires a post-sync write.
357 flags |= PIPE_CONTROL_QW_WRITE;
358 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
360 /* Workaround: we must issue a pipe_control with CS-stall bit
361 * set before a pipe_control command that has the state cache
362 * invalidate bit set. */
363 gen7_render_ring_cs_stall_wa(ring);
366 ret = intel_ring_begin(ring, 4);
370 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
371 intel_ring_emit(ring, flags);
372 intel_ring_emit(ring, scratch_addr);
373 intel_ring_emit(ring, 0);
374 intel_ring_advance(ring);
376 if (!invalidate_domains && flush_domains)
377 return gen7_ring_fbc_flush(ring, FBC_REND_NUKE);
383 gen8_emit_pipe_control(struct intel_engine_cs *ring,
384 u32 flags, u32 scratch_addr)
388 ret = intel_ring_begin(ring, 6);
392 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
393 intel_ring_emit(ring, flags);
394 intel_ring_emit(ring, scratch_addr);
395 intel_ring_emit(ring, 0);
396 intel_ring_emit(ring, 0);
397 intel_ring_emit(ring, 0);
398 intel_ring_advance(ring);
404 gen8_render_ring_flush(struct intel_engine_cs *ring,
405 u32 invalidate_domains, u32 flush_domains)
408 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
411 flags |= PIPE_CONTROL_CS_STALL;
414 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
415 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
417 if (invalidate_domains) {
418 flags |= PIPE_CONTROL_TLB_INVALIDATE;
419 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
420 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
421 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
422 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
423 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
424 flags |= PIPE_CONTROL_QW_WRITE;
425 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
427 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
428 ret = gen8_emit_pipe_control(ring,
429 PIPE_CONTROL_CS_STALL |
430 PIPE_CONTROL_STALL_AT_SCOREBOARD,
436 return gen8_emit_pipe_control(ring, flags, scratch_addr);
439 static void ring_write_tail(struct intel_engine_cs *ring,
442 struct drm_i915_private *dev_priv = ring->dev->dev_private;
443 I915_WRITE_TAIL(ring, value);
446 u64 intel_ring_get_active_head(struct intel_engine_cs *ring)
448 struct drm_i915_private *dev_priv = ring->dev->dev_private;
451 if (INTEL_INFO(ring->dev)->gen >= 8)
452 acthd = I915_READ64_2x32(RING_ACTHD(ring->mmio_base),
453 RING_ACTHD_UDW(ring->mmio_base));
454 else if (INTEL_INFO(ring->dev)->gen >= 4)
455 acthd = I915_READ(RING_ACTHD(ring->mmio_base));
457 acthd = I915_READ(ACTHD);
462 static void ring_setup_phys_status_page(struct intel_engine_cs *ring)
464 struct drm_i915_private *dev_priv = ring->dev->dev_private;
467 addr = dev_priv->status_page_dmah->busaddr;
468 if (INTEL_INFO(ring->dev)->gen >= 4)
469 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
470 I915_WRITE(HWS_PGA, addr);
473 static bool stop_ring(struct intel_engine_cs *ring)
475 struct drm_i915_private *dev_priv = to_i915(ring->dev);
477 if (!IS_GEN2(ring->dev)) {
478 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
479 if (wait_for_atomic((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
480 DRM_ERROR("%s :timed out trying to stop ring\n", ring->name);
485 I915_WRITE_CTL(ring, 0);
486 I915_WRITE_HEAD(ring, 0);
487 ring->write_tail(ring, 0);
489 if (!IS_GEN2(ring->dev)) {
490 (void)I915_READ_CTL(ring);
491 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
494 return (I915_READ_HEAD(ring) & HEAD_ADDR) == 0;
497 static int init_ring_common(struct intel_engine_cs *ring)
499 struct drm_device *dev = ring->dev;
500 struct drm_i915_private *dev_priv = dev->dev_private;
501 struct intel_ringbuffer *ringbuf = ring->buffer;
502 struct drm_i915_gem_object *obj = ringbuf->obj;
505 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
507 if (!stop_ring(ring)) {
508 /* G45 ring initialization often fails to reset head to zero */
509 DRM_DEBUG_KMS("%s head not reset to zero "
510 "ctl %08x head %08x tail %08x start %08x\n",
513 I915_READ_HEAD(ring),
514 I915_READ_TAIL(ring),
515 I915_READ_START(ring));
517 if (!stop_ring(ring)) {
518 DRM_ERROR("failed to set %s head to zero "
519 "ctl %08x head %08x tail %08x start %08x\n",
522 I915_READ_HEAD(ring),
523 I915_READ_TAIL(ring),
524 I915_READ_START(ring));
530 if (I915_NEED_GFX_HWS(dev))
531 intel_ring_setup_status_page(ring);
533 ring_setup_phys_status_page(ring);
535 /* Enforce ordering by reading HEAD register back */
536 I915_READ_HEAD(ring);
538 /* Initialize the ring. This must happen _after_ we've cleared the ring
539 * registers with the above sequence (the readback of the HEAD registers
540 * also enforces ordering), otherwise the hw might lose the new ring
541 * register values. */
542 I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj));
544 ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES)
547 /* If the head is still not zero, the ring is dead */
548 if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
549 I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) &&
550 (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
551 DRM_ERROR("%s initialization failed "
552 "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
554 I915_READ_CTL(ring), I915_READ_CTL(ring) & RING_VALID,
555 I915_READ_HEAD(ring), I915_READ_TAIL(ring),
556 I915_READ_START(ring), (unsigned long)i915_gem_obj_ggtt_offset(obj));
561 if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
562 i915_kernel_lost_context(ring->dev);
564 ringbuf->head = I915_READ_HEAD(ring);
565 ringbuf->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
566 ringbuf->space = ring_space(ringbuf);
567 ringbuf->last_retired_head = -1;
570 memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
573 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
579 init_pipe_control(struct intel_engine_cs *ring)
583 if (ring->scratch.obj)
586 ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096);
587 if (ring->scratch.obj == NULL) {
588 DRM_ERROR("Failed to allocate seqno page\n");
593 ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC);
597 ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0);
601 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj);
602 ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl));
603 if (ring->scratch.cpu_page == NULL) {
608 DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
609 ring->name, ring->scratch.gtt_offset);
613 i915_gem_object_ggtt_unpin(ring->scratch.obj);
615 drm_gem_object_unreference(&ring->scratch.obj->base);
620 static int init_render_ring(struct intel_engine_cs *ring)
622 struct drm_device *dev = ring->dev;
623 struct drm_i915_private *dev_priv = dev->dev_private;
624 int ret = init_ring_common(ring);
628 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
629 if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7)
630 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
632 /* We need to disable the AsyncFlip performance optimisations in order
633 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
634 * programmed to '1' on all products.
636 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
638 if (INTEL_INFO(dev)->gen >= 6)
639 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
641 /* Required for the hardware to program scanline values for waiting */
642 /* WaEnableFlushTlbInvalidationMode:snb */
643 if (INTEL_INFO(dev)->gen == 6)
645 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
647 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
649 I915_WRITE(GFX_MODE_GEN7,
650 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
651 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
653 if (INTEL_INFO(dev)->gen >= 5) {
654 ret = init_pipe_control(ring);
660 /* From the Sandybridge PRM, volume 1 part 3, page 24:
661 * "If this bit is set, STCunit will have LRA as replacement
662 * policy. [...] This bit must be reset. LRA replacement
663 * policy is not supported."
665 I915_WRITE(CACHE_MODE_0,
666 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
669 if (INTEL_INFO(dev)->gen >= 6)
670 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
673 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
678 static void render_ring_cleanup(struct intel_engine_cs *ring)
680 struct drm_device *dev = ring->dev;
681 struct drm_i915_private *dev_priv = dev->dev_private;
683 if (dev_priv->semaphore_obj) {
684 i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj);
685 drm_gem_object_unreference(&dev_priv->semaphore_obj->base);
686 dev_priv->semaphore_obj = NULL;
689 if (ring->scratch.obj == NULL)
692 if (INTEL_INFO(dev)->gen >= 5) {
693 kunmap(sg_page(ring->scratch.obj->pages->sgl));
694 i915_gem_object_ggtt_unpin(ring->scratch.obj);
697 drm_gem_object_unreference(&ring->scratch.obj->base);
698 ring->scratch.obj = NULL;
701 static int gen8_rcs_signal(struct intel_engine_cs *signaller,
702 unsigned int num_dwords)
704 #define MBOX_UPDATE_DWORDS 8
705 struct drm_device *dev = signaller->dev;
706 struct drm_i915_private *dev_priv = dev->dev_private;
707 struct intel_engine_cs *waiter;
708 int i, ret, num_rings;
710 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
711 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
712 #undef MBOX_UPDATE_DWORDS
714 ret = intel_ring_begin(signaller, num_dwords);
718 for_each_ring(waiter, dev_priv, i) {
719 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
720 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
723 intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
724 intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |
725 PIPE_CONTROL_QW_WRITE |
726 PIPE_CONTROL_FLUSH_ENABLE);
727 intel_ring_emit(signaller, lower_32_bits(gtt_offset));
728 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
729 intel_ring_emit(signaller, signaller->outstanding_lazy_seqno);
730 intel_ring_emit(signaller, 0);
731 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
732 MI_SEMAPHORE_TARGET(waiter->id));
733 intel_ring_emit(signaller, 0);
739 static int gen8_xcs_signal(struct intel_engine_cs *signaller,
740 unsigned int num_dwords)
742 #define MBOX_UPDATE_DWORDS 6
743 struct drm_device *dev = signaller->dev;
744 struct drm_i915_private *dev_priv = dev->dev_private;
745 struct intel_engine_cs *waiter;
746 int i, ret, num_rings;
748 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
749 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
750 #undef MBOX_UPDATE_DWORDS
752 ret = intel_ring_begin(signaller, num_dwords);
756 for_each_ring(waiter, dev_priv, i) {
757 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
758 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
761 intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |
762 MI_FLUSH_DW_OP_STOREDW);
763 intel_ring_emit(signaller, lower_32_bits(gtt_offset) |
764 MI_FLUSH_DW_USE_GTT);
765 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
766 intel_ring_emit(signaller, signaller->outstanding_lazy_seqno);
767 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
768 MI_SEMAPHORE_TARGET(waiter->id));
769 intel_ring_emit(signaller, 0);
775 static int gen6_signal(struct intel_engine_cs *signaller,
776 unsigned int num_dwords)
778 struct drm_device *dev = signaller->dev;
779 struct drm_i915_private *dev_priv = dev->dev_private;
780 struct intel_engine_cs *useless;
781 int i, ret, num_rings;
783 #define MBOX_UPDATE_DWORDS 3
784 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
785 num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
786 #undef MBOX_UPDATE_DWORDS
788 ret = intel_ring_begin(signaller, num_dwords);
792 for_each_ring(useless, dev_priv, i) {
793 u32 mbox_reg = signaller->semaphore.mbox.signal[i];
794 if (mbox_reg != GEN6_NOSYNC) {
795 intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
796 intel_ring_emit(signaller, mbox_reg);
797 intel_ring_emit(signaller, signaller->outstanding_lazy_seqno);
801 /* If num_dwords was rounded, make sure the tail pointer is correct */
802 if (num_rings % 2 == 0)
803 intel_ring_emit(signaller, MI_NOOP);
809 * gen6_add_request - Update the semaphore mailbox registers
811 * @ring - ring that is adding a request
812 * @seqno - return seqno stuck into the ring
814 * Update the mailbox registers in the *other* rings with the current seqno.
815 * This acts like a signal in the canonical semaphore.
818 gen6_add_request(struct intel_engine_cs *ring)
822 if (ring->semaphore.signal)
823 ret = ring->semaphore.signal(ring, 4);
825 ret = intel_ring_begin(ring, 4);
830 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
831 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
832 intel_ring_emit(ring, ring->outstanding_lazy_seqno);
833 intel_ring_emit(ring, MI_USER_INTERRUPT);
834 __intel_ring_advance(ring);
839 static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
842 struct drm_i915_private *dev_priv = dev->dev_private;
843 return dev_priv->last_seqno < seqno;
847 * intel_ring_sync - sync the waiter to the signaller on seqno
849 * @waiter - ring that is waiting
850 * @signaller - ring which has, or will signal
851 * @seqno - seqno which the waiter will block on
855 gen8_ring_sync(struct intel_engine_cs *waiter,
856 struct intel_engine_cs *signaller,
859 struct drm_i915_private *dev_priv = waiter->dev->dev_private;
862 ret = intel_ring_begin(waiter, 4);
866 intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |
867 MI_SEMAPHORE_GLOBAL_GTT |
869 MI_SEMAPHORE_SAD_GTE_SDD);
870 intel_ring_emit(waiter, seqno);
871 intel_ring_emit(waiter,
872 lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
873 intel_ring_emit(waiter,
874 upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
875 intel_ring_advance(waiter);
880 gen6_ring_sync(struct intel_engine_cs *waiter,
881 struct intel_engine_cs *signaller,
884 u32 dw1 = MI_SEMAPHORE_MBOX |
885 MI_SEMAPHORE_COMPARE |
886 MI_SEMAPHORE_REGISTER;
887 u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id];
890 /* Throughout all of the GEM code, seqno passed implies our current
891 * seqno is >= the last seqno executed. However for hardware the
892 * comparison is strictly greater than.
896 WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
898 ret = intel_ring_begin(waiter, 4);
902 /* If seqno wrap happened, omit the wait with no-ops */
903 if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
904 intel_ring_emit(waiter, dw1 | wait_mbox);
905 intel_ring_emit(waiter, seqno);
906 intel_ring_emit(waiter, 0);
907 intel_ring_emit(waiter, MI_NOOP);
909 intel_ring_emit(waiter, MI_NOOP);
910 intel_ring_emit(waiter, MI_NOOP);
911 intel_ring_emit(waiter, MI_NOOP);
912 intel_ring_emit(waiter, MI_NOOP);
914 intel_ring_advance(waiter);
919 #define PIPE_CONTROL_FLUSH(ring__, addr__) \
921 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
922 PIPE_CONTROL_DEPTH_STALL); \
923 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
924 intel_ring_emit(ring__, 0); \
925 intel_ring_emit(ring__, 0); \
929 pc_render_add_request(struct intel_engine_cs *ring)
931 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
934 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
935 * incoherent with writes to memory, i.e. completely fubar,
936 * so we need to use PIPE_NOTIFY instead.
938 * However, we also need to workaround the qword write
939 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
940 * memory before requesting an interrupt.
942 ret = intel_ring_begin(ring, 32);
946 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
947 PIPE_CONTROL_WRITE_FLUSH |
948 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
949 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
950 intel_ring_emit(ring, ring->outstanding_lazy_seqno);
951 intel_ring_emit(ring, 0);
952 PIPE_CONTROL_FLUSH(ring, scratch_addr);
953 scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
954 PIPE_CONTROL_FLUSH(ring, scratch_addr);
955 scratch_addr += 2 * CACHELINE_BYTES;
956 PIPE_CONTROL_FLUSH(ring, scratch_addr);
957 scratch_addr += 2 * CACHELINE_BYTES;
958 PIPE_CONTROL_FLUSH(ring, scratch_addr);
959 scratch_addr += 2 * CACHELINE_BYTES;
960 PIPE_CONTROL_FLUSH(ring, scratch_addr);
961 scratch_addr += 2 * CACHELINE_BYTES;
962 PIPE_CONTROL_FLUSH(ring, scratch_addr);
964 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
965 PIPE_CONTROL_WRITE_FLUSH |
966 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
967 PIPE_CONTROL_NOTIFY);
968 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
969 intel_ring_emit(ring, ring->outstanding_lazy_seqno);
970 intel_ring_emit(ring, 0);
971 __intel_ring_advance(ring);
977 gen6_ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
979 /* Workaround to force correct ordering between irq and seqno writes on
980 * ivb (and maybe also on snb) by reading from a CS register (like
981 * ACTHD) before reading the status page. */
982 if (!lazy_coherency) {
983 struct drm_i915_private *dev_priv = ring->dev->dev_private;
984 POSTING_READ(RING_ACTHD(ring->mmio_base));
987 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
991 ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
993 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
997 ring_set_seqno(struct intel_engine_cs *ring, u32 seqno)
999 intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
1003 pc_render_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1005 return ring->scratch.cpu_page[0];
1009 pc_render_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1011 ring->scratch.cpu_page[0] = seqno;
1015 gen5_ring_get_irq(struct intel_engine_cs *ring)
1017 struct drm_device *dev = ring->dev;
1018 struct drm_i915_private *dev_priv = dev->dev_private;
1019 unsigned long flags;
1021 if (!dev->irq_enabled)
1024 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1025 if (ring->irq_refcount++ == 0)
1026 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1027 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1033 gen5_ring_put_irq(struct intel_engine_cs *ring)
1035 struct drm_device *dev = ring->dev;
1036 struct drm_i915_private *dev_priv = dev->dev_private;
1037 unsigned long flags;
1039 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1040 if (--ring->irq_refcount == 0)
1041 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1042 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1046 i9xx_ring_get_irq(struct intel_engine_cs *ring)
1048 struct drm_device *dev = ring->dev;
1049 struct drm_i915_private *dev_priv = dev->dev_private;
1050 unsigned long flags;
1052 if (!dev->irq_enabled)
1055 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1056 if (ring->irq_refcount++ == 0) {
1057 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1058 I915_WRITE(IMR, dev_priv->irq_mask);
1061 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1067 i9xx_ring_put_irq(struct intel_engine_cs *ring)
1069 struct drm_device *dev = ring->dev;
1070 struct drm_i915_private *dev_priv = dev->dev_private;
1071 unsigned long flags;
1073 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1074 if (--ring->irq_refcount == 0) {
1075 dev_priv->irq_mask |= ring->irq_enable_mask;
1076 I915_WRITE(IMR, dev_priv->irq_mask);
1079 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1083 i8xx_ring_get_irq(struct intel_engine_cs *ring)
1085 struct drm_device *dev = ring->dev;
1086 struct drm_i915_private *dev_priv = dev->dev_private;
1087 unsigned long flags;
1089 if (!dev->irq_enabled)
1092 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1093 if (ring->irq_refcount++ == 0) {
1094 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1095 I915_WRITE16(IMR, dev_priv->irq_mask);
1096 POSTING_READ16(IMR);
1098 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1104 i8xx_ring_put_irq(struct intel_engine_cs *ring)
1106 struct drm_device *dev = ring->dev;
1107 struct drm_i915_private *dev_priv = dev->dev_private;
1108 unsigned long flags;
1110 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1111 if (--ring->irq_refcount == 0) {
1112 dev_priv->irq_mask |= ring->irq_enable_mask;
1113 I915_WRITE16(IMR, dev_priv->irq_mask);
1114 POSTING_READ16(IMR);
1116 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1119 void intel_ring_setup_status_page(struct intel_engine_cs *ring)
1121 struct drm_device *dev = ring->dev;
1122 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1125 /* The ring status page addresses are no longer next to the rest of
1126 * the ring registers as of gen7.
1131 mmio = RENDER_HWS_PGA_GEN7;
1134 mmio = BLT_HWS_PGA_GEN7;
1137 * VCS2 actually doesn't exist on Gen7. Only shut up
1138 * gcc switch check warning
1142 mmio = BSD_HWS_PGA_GEN7;
1145 mmio = VEBOX_HWS_PGA_GEN7;
1148 } else if (IS_GEN6(ring->dev)) {
1149 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
1151 /* XXX: gen8 returns to sanity */
1152 mmio = RING_HWS_PGA(ring->mmio_base);
1155 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
1159 * Flush the TLB for this page
1161 * FIXME: These two bits have disappeared on gen8, so a question
1162 * arises: do we still need this and if so how should we go about
1163 * invalidating the TLB?
1165 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
1166 u32 reg = RING_INSTPM(ring->mmio_base);
1168 /* ring should be idle before issuing a sync flush*/
1169 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
1172 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
1173 INSTPM_SYNC_FLUSH));
1174 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
1176 DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
1182 bsd_ring_flush(struct intel_engine_cs *ring,
1183 u32 invalidate_domains,
1188 ret = intel_ring_begin(ring, 2);
1192 intel_ring_emit(ring, MI_FLUSH);
1193 intel_ring_emit(ring, MI_NOOP);
1194 intel_ring_advance(ring);
1199 i9xx_add_request(struct intel_engine_cs *ring)
1203 ret = intel_ring_begin(ring, 4);
1207 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1208 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1209 intel_ring_emit(ring, ring->outstanding_lazy_seqno);
1210 intel_ring_emit(ring, MI_USER_INTERRUPT);
1211 __intel_ring_advance(ring);
1217 gen6_ring_get_irq(struct intel_engine_cs *ring)
1219 struct drm_device *dev = ring->dev;
1220 struct drm_i915_private *dev_priv = dev->dev_private;
1221 unsigned long flags;
1223 if (!dev->irq_enabled)
1226 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1227 if (ring->irq_refcount++ == 0) {
1228 if (HAS_L3_DPF(dev) && ring->id == RCS)
1229 I915_WRITE_IMR(ring,
1230 ~(ring->irq_enable_mask |
1231 GT_PARITY_ERROR(dev)));
1233 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1234 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1236 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1242 gen6_ring_put_irq(struct intel_engine_cs *ring)
1244 struct drm_device *dev = ring->dev;
1245 struct drm_i915_private *dev_priv = dev->dev_private;
1246 unsigned long flags;
1248 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1249 if (--ring->irq_refcount == 0) {
1250 if (HAS_L3_DPF(dev) && ring->id == RCS)
1251 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
1253 I915_WRITE_IMR(ring, ~0);
1254 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1256 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1260 hsw_vebox_get_irq(struct intel_engine_cs *ring)
1262 struct drm_device *dev = ring->dev;
1263 struct drm_i915_private *dev_priv = dev->dev_private;
1264 unsigned long flags;
1266 if (!dev->irq_enabled)
1269 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1270 if (ring->irq_refcount++ == 0) {
1271 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1272 gen6_enable_pm_irq(dev_priv, ring->irq_enable_mask);
1274 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1280 hsw_vebox_put_irq(struct intel_engine_cs *ring)
1282 struct drm_device *dev = ring->dev;
1283 struct drm_i915_private *dev_priv = dev->dev_private;
1284 unsigned long flags;
1286 if (!dev->irq_enabled)
1289 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1290 if (--ring->irq_refcount == 0) {
1291 I915_WRITE_IMR(ring, ~0);
1292 gen6_disable_pm_irq(dev_priv, ring->irq_enable_mask);
1294 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1298 gen8_ring_get_irq(struct intel_engine_cs *ring)
1300 struct drm_device *dev = ring->dev;
1301 struct drm_i915_private *dev_priv = dev->dev_private;
1302 unsigned long flags;
1304 if (!dev->irq_enabled)
1307 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1308 if (ring->irq_refcount++ == 0) {
1309 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1310 I915_WRITE_IMR(ring,
1311 ~(ring->irq_enable_mask |
1312 GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1314 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1316 POSTING_READ(RING_IMR(ring->mmio_base));
1318 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1324 gen8_ring_put_irq(struct intel_engine_cs *ring)
1326 struct drm_device *dev = ring->dev;
1327 struct drm_i915_private *dev_priv = dev->dev_private;
1328 unsigned long flags;
1330 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1331 if (--ring->irq_refcount == 0) {
1332 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1333 I915_WRITE_IMR(ring,
1334 ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1336 I915_WRITE_IMR(ring, ~0);
1338 POSTING_READ(RING_IMR(ring->mmio_base));
1340 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1344 i965_dispatch_execbuffer(struct intel_engine_cs *ring,
1345 u64 offset, u32 length,
1350 ret = intel_ring_begin(ring, 2);
1354 intel_ring_emit(ring,
1355 MI_BATCH_BUFFER_START |
1357 (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
1358 intel_ring_emit(ring, offset);
1359 intel_ring_advance(ring);
1364 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1365 #define I830_BATCH_LIMIT (256*1024)
1367 i830_dispatch_execbuffer(struct intel_engine_cs *ring,
1368 u64 offset, u32 len,
1373 if (flags & I915_DISPATCH_PINNED) {
1374 ret = intel_ring_begin(ring, 4);
1378 intel_ring_emit(ring, MI_BATCH_BUFFER);
1379 intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1380 intel_ring_emit(ring, offset + len - 8);
1381 intel_ring_emit(ring, MI_NOOP);
1382 intel_ring_advance(ring);
1384 u32 cs_offset = ring->scratch.gtt_offset;
1386 if (len > I830_BATCH_LIMIT)
1389 ret = intel_ring_begin(ring, 9+3);
1392 /* Blit the batch (which has now all relocs applied) to the stable batch
1393 * scratch bo area (so that the CS never stumbles over its tlb
1394 * invalidation bug) ... */
1395 intel_ring_emit(ring, XY_SRC_COPY_BLT_CMD |
1396 XY_SRC_COPY_BLT_WRITE_ALPHA |
1397 XY_SRC_COPY_BLT_WRITE_RGB);
1398 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_GXCOPY | 4096);
1399 intel_ring_emit(ring, 0);
1400 intel_ring_emit(ring, (DIV_ROUND_UP(len, 4096) << 16) | 1024);
1401 intel_ring_emit(ring, cs_offset);
1402 intel_ring_emit(ring, 0);
1403 intel_ring_emit(ring, 4096);
1404 intel_ring_emit(ring, offset);
1405 intel_ring_emit(ring, MI_FLUSH);
1407 /* ... and execute it. */
1408 intel_ring_emit(ring, MI_BATCH_BUFFER);
1409 intel_ring_emit(ring, cs_offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1410 intel_ring_emit(ring, cs_offset + len - 8);
1411 intel_ring_advance(ring);
1418 i915_dispatch_execbuffer(struct intel_engine_cs *ring,
1419 u64 offset, u32 len,
1424 ret = intel_ring_begin(ring, 2);
1428 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1429 intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1430 intel_ring_advance(ring);
1435 static void cleanup_status_page(struct intel_engine_cs *ring)
1437 struct drm_i915_gem_object *obj;
1439 obj = ring->status_page.obj;
1443 kunmap(sg_page(obj->pages->sgl));
1444 i915_gem_object_ggtt_unpin(obj);
1445 drm_gem_object_unreference(&obj->base);
1446 ring->status_page.obj = NULL;
1449 static int init_status_page(struct intel_engine_cs *ring)
1451 struct drm_i915_gem_object *obj;
1453 if ((obj = ring->status_page.obj) == NULL) {
1457 obj = i915_gem_alloc_object(ring->dev, 4096);
1459 DRM_ERROR("Failed to allocate status page\n");
1463 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1468 if (!HAS_LLC(ring->dev))
1469 /* On g33, we cannot place HWS above 256MiB, so
1470 * restrict its pinning to the low mappable arena.
1471 * Though this restriction is not documented for
1472 * gen4, gen5, or byt, they also behave similarly
1473 * and hang if the HWS is placed at the top of the
1474 * GTT. To generalise, it appears that all !llc
1475 * platforms have issues with us placing the HWS
1476 * above the mappable region (even though we never
1479 flags |= PIN_MAPPABLE;
1480 ret = i915_gem_obj_ggtt_pin(obj, 4096, flags);
1483 drm_gem_object_unreference(&obj->base);
1487 ring->status_page.obj = obj;
1490 ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
1491 ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
1492 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1494 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1495 ring->name, ring->status_page.gfx_addr);
1500 static int init_phys_status_page(struct intel_engine_cs *ring)
1502 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1504 if (!dev_priv->status_page_dmah) {
1505 dev_priv->status_page_dmah =
1506 drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
1507 if (!dev_priv->status_page_dmah)
1511 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1512 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1517 static void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
1522 iounmap(ringbuf->virtual_start);
1523 i915_gem_object_ggtt_unpin(ringbuf->obj);
1524 drm_gem_object_unreference(&ringbuf->obj->base);
1525 ringbuf->obj = NULL;
1528 static int intel_alloc_ringbuffer_obj(struct drm_device *dev,
1529 struct intel_ringbuffer *ringbuf)
1531 struct drm_i915_private *dev_priv = to_i915(dev);
1532 struct drm_i915_gem_object *obj;
1540 obj = i915_gem_object_create_stolen(dev, ringbuf->size);
1542 obj = i915_gem_alloc_object(dev, ringbuf->size);
1546 /* mark ring buffers as read-only from GPU side by default */
1549 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE);
1553 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1557 ringbuf->virtual_start =
1558 ioremap_wc(dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj),
1560 if (ringbuf->virtual_start == NULL) {
1569 i915_gem_object_ggtt_unpin(obj);
1571 drm_gem_object_unreference(&obj->base);
1575 static int intel_init_ring_buffer(struct drm_device *dev,
1576 struct intel_engine_cs *ring)
1578 struct intel_ringbuffer *ringbuf = ring->buffer;
1581 if (ringbuf == NULL) {
1582 ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL);
1585 ring->buffer = ringbuf;
1589 INIT_LIST_HEAD(&ring->active_list);
1590 INIT_LIST_HEAD(&ring->request_list);
1591 ringbuf->size = 32 * PAGE_SIZE;
1592 memset(ring->semaphore.sync_seqno, 0, sizeof(ring->semaphore.sync_seqno));
1594 init_waitqueue_head(&ring->irq_queue);
1596 if (I915_NEED_GFX_HWS(dev)) {
1597 ret = init_status_page(ring);
1601 BUG_ON(ring->id != RCS);
1602 ret = init_phys_status_page(ring);
1607 ret = intel_alloc_ringbuffer_obj(dev, ringbuf);
1609 DRM_ERROR("Failed to allocate ringbuffer %s: %d\n", ring->name, ret);
1613 /* Workaround an erratum on the i830 which causes a hang if
1614 * the TAIL pointer points to within the last 2 cachelines
1617 ringbuf->effective_size = ringbuf->size;
1618 if (IS_I830(dev) || IS_845G(dev))
1619 ringbuf->effective_size -= 2 * CACHELINE_BYTES;
1621 ret = i915_cmd_parser_init_ring(ring);
1625 ret = ring->init(ring);
1633 ring->buffer = NULL;
1637 void intel_cleanup_ring_buffer(struct intel_engine_cs *ring)
1639 struct drm_i915_private *dev_priv = to_i915(ring->dev);
1640 struct intel_ringbuffer *ringbuf = ring->buffer;
1642 if (!intel_ring_initialized(ring))
1645 intel_stop_ring_buffer(ring);
1646 WARN_ON(!IS_GEN2(ring->dev) && (I915_READ_MODE(ring) & MODE_IDLE) == 0);
1648 intel_destroy_ringbuffer_obj(ringbuf);
1649 ring->preallocated_lazy_request = NULL;
1650 ring->outstanding_lazy_seqno = 0;
1653 ring->cleanup(ring);
1655 cleanup_status_page(ring);
1657 i915_cmd_parser_fini_ring(ring);
1660 ring->buffer = NULL;
1663 static int intel_ring_wait_request(struct intel_engine_cs *ring, int n)
1665 struct intel_ringbuffer *ringbuf = ring->buffer;
1666 struct drm_i915_gem_request *request;
1670 if (ringbuf->last_retired_head != -1) {
1671 ringbuf->head = ringbuf->last_retired_head;
1672 ringbuf->last_retired_head = -1;
1674 ringbuf->space = ring_space(ringbuf);
1675 if (ringbuf->space >= n)
1679 list_for_each_entry(request, &ring->request_list, list) {
1680 if (__ring_space(request->tail, ringbuf->tail, ringbuf->size) >= n) {
1681 seqno = request->seqno;
1689 ret = i915_wait_seqno(ring, seqno);
1693 i915_gem_retire_requests_ring(ring);
1694 ringbuf->head = ringbuf->last_retired_head;
1695 ringbuf->last_retired_head = -1;
1697 ringbuf->space = ring_space(ringbuf);
1701 static int ring_wait_for_space(struct intel_engine_cs *ring, int n)
1703 struct drm_device *dev = ring->dev;
1704 struct drm_i915_private *dev_priv = dev->dev_private;
1705 struct intel_ringbuffer *ringbuf = ring->buffer;
1709 ret = intel_ring_wait_request(ring, n);
1713 /* force the tail write in case we have been skipping them */
1714 __intel_ring_advance(ring);
1716 /* With GEM the hangcheck timer should kick us out of the loop,
1717 * leaving it early runs the risk of corrupting GEM state (due
1718 * to running on almost untested codepaths). But on resume
1719 * timers don't work yet, so prevent a complete hang in that
1720 * case by choosing an insanely large timeout. */
1721 end = jiffies + 60 * HZ;
1723 trace_i915_ring_wait_begin(ring);
1725 ringbuf->head = I915_READ_HEAD(ring);
1726 ringbuf->space = ring_space(ringbuf);
1727 if (ringbuf->space >= n) {
1732 if (!drm_core_check_feature(dev, DRIVER_MODESET) &&
1733 dev->primary->master) {
1734 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1735 if (master_priv->sarea_priv)
1736 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1741 if (dev_priv->mm.interruptible && signal_pending(current)) {
1746 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
1747 dev_priv->mm.interruptible);
1751 if (time_after(jiffies, end)) {
1756 trace_i915_ring_wait_end(ring);
1760 static int intel_wrap_ring_buffer(struct intel_engine_cs *ring)
1762 uint32_t __iomem *virt;
1763 struct intel_ringbuffer *ringbuf = ring->buffer;
1764 int rem = ringbuf->size - ringbuf->tail;
1766 if (ringbuf->space < rem) {
1767 int ret = ring_wait_for_space(ring, rem);
1772 virt = ringbuf->virtual_start + ringbuf->tail;
1775 iowrite32(MI_NOOP, virt++);
1778 ringbuf->space = ring_space(ringbuf);
1783 int intel_ring_idle(struct intel_engine_cs *ring)
1788 /* We need to add any requests required to flush the objects and ring */
1789 if (ring->outstanding_lazy_seqno) {
1790 ret = i915_add_request(ring, NULL);
1795 /* Wait upon the last request to be completed */
1796 if (list_empty(&ring->request_list))
1799 seqno = list_entry(ring->request_list.prev,
1800 struct drm_i915_gem_request,
1803 return i915_wait_seqno(ring, seqno);
1807 intel_ring_alloc_seqno(struct intel_engine_cs *ring)
1809 if (ring->outstanding_lazy_seqno)
1812 if (ring->preallocated_lazy_request == NULL) {
1813 struct drm_i915_gem_request *request;
1815 request = kmalloc(sizeof(*request), GFP_KERNEL);
1816 if (request == NULL)
1819 ring->preallocated_lazy_request = request;
1822 return i915_gem_get_seqno(ring->dev, &ring->outstanding_lazy_seqno);
1825 static int __intel_ring_prepare(struct intel_engine_cs *ring,
1828 struct intel_ringbuffer *ringbuf = ring->buffer;
1831 if (unlikely(ringbuf->tail + bytes > ringbuf->effective_size)) {
1832 ret = intel_wrap_ring_buffer(ring);
1837 if (unlikely(ringbuf->space < bytes)) {
1838 ret = ring_wait_for_space(ring, bytes);
1846 int intel_ring_begin(struct intel_engine_cs *ring,
1849 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1852 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
1853 dev_priv->mm.interruptible);
1857 ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t));
1861 /* Preallocate the olr before touching the ring */
1862 ret = intel_ring_alloc_seqno(ring);
1866 ring->buffer->space -= num_dwords * sizeof(uint32_t);
1870 /* Align the ring tail to a cacheline boundary */
1871 int intel_ring_cacheline_align(struct intel_engine_cs *ring)
1873 int num_dwords = (ring->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
1876 if (num_dwords == 0)
1879 num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
1880 ret = intel_ring_begin(ring, num_dwords);
1884 while (num_dwords--)
1885 intel_ring_emit(ring, MI_NOOP);
1887 intel_ring_advance(ring);
1892 void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno)
1894 struct drm_device *dev = ring->dev;
1895 struct drm_i915_private *dev_priv = dev->dev_private;
1897 BUG_ON(ring->outstanding_lazy_seqno);
1899 if (INTEL_INFO(dev)->gen == 6 || INTEL_INFO(dev)->gen == 7) {
1900 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
1901 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
1903 I915_WRITE(RING_SYNC_2(ring->mmio_base), 0);
1906 ring->set_seqno(ring, seqno);
1907 ring->hangcheck.seqno = seqno;
1910 static void gen6_bsd_ring_write_tail(struct intel_engine_cs *ring,
1913 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1915 /* Every tail move must follow the sequence below */
1917 /* Disable notification that the ring is IDLE. The GT
1918 * will then assume that it is busy and bring it out of rc6.
1920 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1921 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1923 /* Clear the context id. Here be magic! */
1924 I915_WRITE64(GEN6_BSD_RNCID, 0x0);
1926 /* Wait for the ring not to be idle, i.e. for it to wake up. */
1927 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
1928 GEN6_BSD_SLEEP_INDICATOR) == 0,
1930 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
1932 /* Now that the ring is fully powered up, update the tail */
1933 I915_WRITE_TAIL(ring, value);
1934 POSTING_READ(RING_TAIL(ring->mmio_base));
1936 /* Let the ring send IDLE messages to the GT again,
1937 * and so let it sleep to conserve power when idle.
1939 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1940 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1943 static int gen6_bsd_ring_flush(struct intel_engine_cs *ring,
1944 u32 invalidate, u32 flush)
1949 ret = intel_ring_begin(ring, 4);
1954 if (INTEL_INFO(ring->dev)->gen >= 8)
1957 * Bspec vol 1c.5 - video engine command streamer:
1958 * "If ENABLED, all TLBs will be invalidated once the flush
1959 * operation is complete. This bit is only valid when the
1960 * Post-Sync Operation field is a value of 1h or 3h."
1962 if (invalidate & I915_GEM_GPU_DOMAINS)
1963 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD |
1964 MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
1965 intel_ring_emit(ring, cmd);
1966 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
1967 if (INTEL_INFO(ring->dev)->gen >= 8) {
1968 intel_ring_emit(ring, 0); /* upper addr */
1969 intel_ring_emit(ring, 0); /* value */
1971 intel_ring_emit(ring, 0);
1972 intel_ring_emit(ring, MI_NOOP);
1974 intel_ring_advance(ring);
1979 gen8_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
1980 u64 offset, u32 len,
1983 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1984 bool ppgtt = dev_priv->mm.aliasing_ppgtt != NULL &&
1985 !(flags & I915_DISPATCH_SECURE);
1988 ret = intel_ring_begin(ring, 4);
1992 /* FIXME(BDW): Address space and security selectors. */
1993 intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));
1994 intel_ring_emit(ring, lower_32_bits(offset));
1995 intel_ring_emit(ring, upper_32_bits(offset));
1996 intel_ring_emit(ring, MI_NOOP);
1997 intel_ring_advance(ring);
2003 hsw_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
2004 u64 offset, u32 len,
2009 ret = intel_ring_begin(ring, 2);
2013 intel_ring_emit(ring,
2014 MI_BATCH_BUFFER_START | MI_BATCH_PPGTT_HSW |
2015 (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_HSW));
2016 /* bit0-7 is the length on GEN6+ */
2017 intel_ring_emit(ring, offset);
2018 intel_ring_advance(ring);
2024 gen6_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
2025 u64 offset, u32 len,
2030 ret = intel_ring_begin(ring, 2);
2034 intel_ring_emit(ring,
2035 MI_BATCH_BUFFER_START |
2036 (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
2037 /* bit0-7 is the length on GEN6+ */
2038 intel_ring_emit(ring, offset);
2039 intel_ring_advance(ring);
2044 /* Blitter support (SandyBridge+) */
2046 static int gen6_ring_flush(struct intel_engine_cs *ring,
2047 u32 invalidate, u32 flush)
2049 struct drm_device *dev = ring->dev;
2053 ret = intel_ring_begin(ring, 4);
2058 if (INTEL_INFO(ring->dev)->gen >= 8)
2061 * Bspec vol 1c.3 - blitter engine command streamer:
2062 * "If ENABLED, all TLBs will be invalidated once the flush
2063 * operation is complete. This bit is only valid when the
2064 * Post-Sync Operation field is a value of 1h or 3h."
2066 if (invalidate & I915_GEM_DOMAIN_RENDER)
2067 cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX |
2068 MI_FLUSH_DW_OP_STOREDW;
2069 intel_ring_emit(ring, cmd);
2070 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2071 if (INTEL_INFO(ring->dev)->gen >= 8) {
2072 intel_ring_emit(ring, 0); /* upper addr */
2073 intel_ring_emit(ring, 0); /* value */
2075 intel_ring_emit(ring, 0);
2076 intel_ring_emit(ring, MI_NOOP);
2078 intel_ring_advance(ring);
2080 if (IS_GEN7(dev) && !invalidate && flush)
2081 return gen7_ring_fbc_flush(ring, FBC_REND_CACHE_CLEAN);
2086 int intel_init_render_ring_buffer(struct drm_device *dev)
2088 struct drm_i915_private *dev_priv = dev->dev_private;
2089 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
2090 struct drm_i915_gem_object *obj;
2093 ring->name = "render ring";
2095 ring->mmio_base = RENDER_RING_BASE;
2097 if (INTEL_INFO(dev)->gen >= 8) {
2098 if (i915_semaphore_is_enabled(dev)) {
2099 obj = i915_gem_alloc_object(dev, 4096);
2101 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2102 i915.semaphores = 0;
2104 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2105 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK);
2107 drm_gem_object_unreference(&obj->base);
2108 DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2109 i915.semaphores = 0;
2111 dev_priv->semaphore_obj = obj;
2114 ring->add_request = gen6_add_request;
2115 ring->flush = gen8_render_ring_flush;
2116 ring->irq_get = gen8_ring_get_irq;
2117 ring->irq_put = gen8_ring_put_irq;
2118 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2119 ring->get_seqno = gen6_ring_get_seqno;
2120 ring->set_seqno = ring_set_seqno;
2121 if (i915_semaphore_is_enabled(dev)) {
2122 WARN_ON(!dev_priv->semaphore_obj);
2123 ring->semaphore.sync_to = gen8_ring_sync;
2124 ring->semaphore.signal = gen8_rcs_signal;
2125 GEN8_RING_SEMAPHORE_INIT;
2127 } else if (INTEL_INFO(dev)->gen >= 6) {
2128 ring->add_request = gen6_add_request;
2129 ring->flush = gen7_render_ring_flush;
2130 if (INTEL_INFO(dev)->gen == 6)
2131 ring->flush = gen6_render_ring_flush;
2132 ring->irq_get = gen6_ring_get_irq;
2133 ring->irq_put = gen6_ring_put_irq;
2134 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2135 ring->get_seqno = gen6_ring_get_seqno;
2136 ring->set_seqno = ring_set_seqno;
2137 if (i915_semaphore_is_enabled(dev)) {
2138 ring->semaphore.sync_to = gen6_ring_sync;
2139 ring->semaphore.signal = gen6_signal;
2141 * The current semaphore is only applied on pre-gen8
2142 * platform. And there is no VCS2 ring on the pre-gen8
2143 * platform. So the semaphore between RCS and VCS2 is
2144 * initialized as INVALID. Gen8 will initialize the
2145 * sema between VCS2 and RCS later.
2147 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID;
2148 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV;
2149 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB;
2150 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE;
2151 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2152 ring->semaphore.mbox.signal[RCS] = GEN6_NOSYNC;
2153 ring->semaphore.mbox.signal[VCS] = GEN6_VRSYNC;
2154 ring->semaphore.mbox.signal[BCS] = GEN6_BRSYNC;
2155 ring->semaphore.mbox.signal[VECS] = GEN6_VERSYNC;
2156 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2158 } else if (IS_GEN5(dev)) {
2159 ring->add_request = pc_render_add_request;
2160 ring->flush = gen4_render_ring_flush;
2161 ring->get_seqno = pc_render_get_seqno;
2162 ring->set_seqno = pc_render_set_seqno;
2163 ring->irq_get = gen5_ring_get_irq;
2164 ring->irq_put = gen5_ring_put_irq;
2165 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
2166 GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
2168 ring->add_request = i9xx_add_request;
2169 if (INTEL_INFO(dev)->gen < 4)
2170 ring->flush = gen2_render_ring_flush;
2172 ring->flush = gen4_render_ring_flush;
2173 ring->get_seqno = ring_get_seqno;
2174 ring->set_seqno = ring_set_seqno;
2176 ring->irq_get = i8xx_ring_get_irq;
2177 ring->irq_put = i8xx_ring_put_irq;
2179 ring->irq_get = i9xx_ring_get_irq;
2180 ring->irq_put = i9xx_ring_put_irq;
2182 ring->irq_enable_mask = I915_USER_INTERRUPT;
2184 ring->write_tail = ring_write_tail;
2186 if (IS_HASWELL(dev))
2187 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
2188 else if (IS_GEN8(dev))
2189 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2190 else if (INTEL_INFO(dev)->gen >= 6)
2191 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2192 else if (INTEL_INFO(dev)->gen >= 4)
2193 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2194 else if (IS_I830(dev) || IS_845G(dev))
2195 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
2197 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
2198 ring->init = init_render_ring;
2199 ring->cleanup = render_ring_cleanup;
2201 /* Workaround batchbuffer to combat CS tlb bug. */
2202 if (HAS_BROKEN_CS_TLB(dev)) {
2203 obj = i915_gem_alloc_object(dev, I830_BATCH_LIMIT);
2205 DRM_ERROR("Failed to allocate batch bo\n");
2209 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
2211 drm_gem_object_unreference(&obj->base);
2212 DRM_ERROR("Failed to ping batch bo\n");
2216 ring->scratch.obj = obj;
2217 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
2220 return intel_init_ring_buffer(dev, ring);
2223 int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
2225 struct drm_i915_private *dev_priv = dev->dev_private;
2226 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
2227 struct intel_ringbuffer *ringbuf = ring->buffer;
2230 if (ringbuf == NULL) {
2231 ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL);
2234 ring->buffer = ringbuf;
2237 ring->name = "render ring";
2239 ring->mmio_base = RENDER_RING_BASE;
2241 if (INTEL_INFO(dev)->gen >= 6) {
2242 /* non-kms not supported on gen6+ */
2247 /* Note: gem is not supported on gen5/ilk without kms (the corresponding
2248 * gem_init ioctl returns with -ENODEV). Hence we do not need to set up
2249 * the special gen5 functions. */
2250 ring->add_request = i9xx_add_request;
2251 if (INTEL_INFO(dev)->gen < 4)
2252 ring->flush = gen2_render_ring_flush;
2254 ring->flush = gen4_render_ring_flush;
2255 ring->get_seqno = ring_get_seqno;
2256 ring->set_seqno = ring_set_seqno;
2258 ring->irq_get = i8xx_ring_get_irq;
2259 ring->irq_put = i8xx_ring_put_irq;
2261 ring->irq_get = i9xx_ring_get_irq;
2262 ring->irq_put = i9xx_ring_put_irq;
2264 ring->irq_enable_mask = I915_USER_INTERRUPT;
2265 ring->write_tail = ring_write_tail;
2266 if (INTEL_INFO(dev)->gen >= 4)
2267 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2268 else if (IS_I830(dev) || IS_845G(dev))
2269 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
2271 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
2272 ring->init = init_render_ring;
2273 ring->cleanup = render_ring_cleanup;
2276 INIT_LIST_HEAD(&ring->active_list);
2277 INIT_LIST_HEAD(&ring->request_list);
2279 ringbuf->size = size;
2280 ringbuf->effective_size = ringbuf->size;
2281 if (IS_I830(ring->dev) || IS_845G(ring->dev))
2282 ringbuf->effective_size -= 2 * CACHELINE_BYTES;
2284 ringbuf->virtual_start = ioremap_wc(start, size);
2285 if (ringbuf->virtual_start == NULL) {
2286 DRM_ERROR("can not ioremap virtual address for"
2292 if (!I915_NEED_GFX_HWS(dev)) {
2293 ret = init_phys_status_page(ring);
2301 iounmap(ringbuf->virtual_start);
2304 ring->buffer = NULL;
2308 int intel_init_bsd_ring_buffer(struct drm_device *dev)
2310 struct drm_i915_private *dev_priv = dev->dev_private;
2311 struct intel_engine_cs *ring = &dev_priv->ring[VCS];
2313 ring->name = "bsd ring";
2316 ring->write_tail = ring_write_tail;
2317 if (INTEL_INFO(dev)->gen >= 6) {
2318 ring->mmio_base = GEN6_BSD_RING_BASE;
2319 /* gen6 bsd needs a special wa for tail updates */
2321 ring->write_tail = gen6_bsd_ring_write_tail;
2322 ring->flush = gen6_bsd_ring_flush;
2323 ring->add_request = gen6_add_request;
2324 ring->get_seqno = gen6_ring_get_seqno;
2325 ring->set_seqno = ring_set_seqno;
2326 if (INTEL_INFO(dev)->gen >= 8) {
2327 ring->irq_enable_mask =
2328 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2329 ring->irq_get = gen8_ring_get_irq;
2330 ring->irq_put = gen8_ring_put_irq;
2331 ring->dispatch_execbuffer =
2332 gen8_ring_dispatch_execbuffer;
2333 if (i915_semaphore_is_enabled(dev)) {
2334 ring->semaphore.sync_to = gen8_ring_sync;
2335 ring->semaphore.signal = gen8_xcs_signal;
2336 GEN8_RING_SEMAPHORE_INIT;
2339 ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2340 ring->irq_get = gen6_ring_get_irq;
2341 ring->irq_put = gen6_ring_put_irq;
2342 ring->dispatch_execbuffer =
2343 gen6_ring_dispatch_execbuffer;
2344 if (i915_semaphore_is_enabled(dev)) {
2345 ring->semaphore.sync_to = gen6_ring_sync;
2346 ring->semaphore.signal = gen6_signal;
2347 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;
2348 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2349 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB;
2350 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE;
2351 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2352 ring->semaphore.mbox.signal[RCS] = GEN6_RVSYNC;
2353 ring->semaphore.mbox.signal[VCS] = GEN6_NOSYNC;
2354 ring->semaphore.mbox.signal[BCS] = GEN6_BVSYNC;
2355 ring->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC;
2356 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2360 ring->mmio_base = BSD_RING_BASE;
2361 ring->flush = bsd_ring_flush;
2362 ring->add_request = i9xx_add_request;
2363 ring->get_seqno = ring_get_seqno;
2364 ring->set_seqno = ring_set_seqno;
2366 ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
2367 ring->irq_get = gen5_ring_get_irq;
2368 ring->irq_put = gen5_ring_put_irq;
2370 ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
2371 ring->irq_get = i9xx_ring_get_irq;
2372 ring->irq_put = i9xx_ring_put_irq;
2374 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2376 ring->init = init_ring_common;
2378 return intel_init_ring_buffer(dev, ring);
2382 * Initialize the second BSD ring for Broadwell GT3.
2383 * It is noted that this only exists on Broadwell GT3.
2385 int intel_init_bsd2_ring_buffer(struct drm_device *dev)
2387 struct drm_i915_private *dev_priv = dev->dev_private;
2388 struct intel_engine_cs *ring = &dev_priv->ring[VCS2];
2390 if ((INTEL_INFO(dev)->gen != 8)) {
2391 DRM_ERROR("No dual-BSD ring on non-BDW machine\n");
2395 ring->name = "bsd2 ring";
2398 ring->write_tail = ring_write_tail;
2399 ring->mmio_base = GEN8_BSD2_RING_BASE;
2400 ring->flush = gen6_bsd_ring_flush;
2401 ring->add_request = gen6_add_request;
2402 ring->get_seqno = gen6_ring_get_seqno;
2403 ring->set_seqno = ring_set_seqno;
2404 ring->irq_enable_mask =
2405 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
2406 ring->irq_get = gen8_ring_get_irq;
2407 ring->irq_put = gen8_ring_put_irq;
2408 ring->dispatch_execbuffer =
2409 gen8_ring_dispatch_execbuffer;
2410 if (i915_semaphore_is_enabled(dev)) {
2411 ring->semaphore.sync_to = gen8_ring_sync;
2412 ring->semaphore.signal = gen8_xcs_signal;
2413 GEN8_RING_SEMAPHORE_INIT;
2415 ring->init = init_ring_common;
2417 return intel_init_ring_buffer(dev, ring);
2420 int intel_init_blt_ring_buffer(struct drm_device *dev)
2422 struct drm_i915_private *dev_priv = dev->dev_private;
2423 struct intel_engine_cs *ring = &dev_priv->ring[BCS];
2425 ring->name = "blitter ring";
2428 ring->mmio_base = BLT_RING_BASE;
2429 ring->write_tail = ring_write_tail;
2430 ring->flush = gen6_ring_flush;
2431 ring->add_request = gen6_add_request;
2432 ring->get_seqno = gen6_ring_get_seqno;
2433 ring->set_seqno = ring_set_seqno;
2434 if (INTEL_INFO(dev)->gen >= 8) {
2435 ring->irq_enable_mask =
2436 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
2437 ring->irq_get = gen8_ring_get_irq;
2438 ring->irq_put = gen8_ring_put_irq;
2439 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2440 if (i915_semaphore_is_enabled(dev)) {
2441 ring->semaphore.sync_to = gen8_ring_sync;
2442 ring->semaphore.signal = gen8_xcs_signal;
2443 GEN8_RING_SEMAPHORE_INIT;
2446 ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
2447 ring->irq_get = gen6_ring_get_irq;
2448 ring->irq_put = gen6_ring_put_irq;
2449 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2450 if (i915_semaphore_is_enabled(dev)) {
2451 ring->semaphore.signal = gen6_signal;
2452 ring->semaphore.sync_to = gen6_ring_sync;
2454 * The current semaphore is only applied on pre-gen8
2455 * platform. And there is no VCS2 ring on the pre-gen8
2456 * platform. So the semaphore between BCS and VCS2 is
2457 * initialized as INVALID. Gen8 will initialize the
2458 * sema between BCS and VCS2 later.
2460 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR;
2461 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV;
2462 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID;
2463 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE;
2464 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2465 ring->semaphore.mbox.signal[RCS] = GEN6_RBSYNC;
2466 ring->semaphore.mbox.signal[VCS] = GEN6_VBSYNC;
2467 ring->semaphore.mbox.signal[BCS] = GEN6_NOSYNC;
2468 ring->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC;
2469 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2472 ring->init = init_ring_common;
2474 return intel_init_ring_buffer(dev, ring);
2477 int intel_init_vebox_ring_buffer(struct drm_device *dev)
2479 struct drm_i915_private *dev_priv = dev->dev_private;
2480 struct intel_engine_cs *ring = &dev_priv->ring[VECS];
2482 ring->name = "video enhancement ring";
2485 ring->mmio_base = VEBOX_RING_BASE;
2486 ring->write_tail = ring_write_tail;
2487 ring->flush = gen6_ring_flush;
2488 ring->add_request = gen6_add_request;
2489 ring->get_seqno = gen6_ring_get_seqno;
2490 ring->set_seqno = ring_set_seqno;
2492 if (INTEL_INFO(dev)->gen >= 8) {
2493 ring->irq_enable_mask =
2494 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
2495 ring->irq_get = gen8_ring_get_irq;
2496 ring->irq_put = gen8_ring_put_irq;
2497 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2498 if (i915_semaphore_is_enabled(dev)) {
2499 ring->semaphore.sync_to = gen8_ring_sync;
2500 ring->semaphore.signal = gen8_xcs_signal;
2501 GEN8_RING_SEMAPHORE_INIT;
2504 ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
2505 ring->irq_get = hsw_vebox_get_irq;
2506 ring->irq_put = hsw_vebox_put_irq;
2507 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2508 if (i915_semaphore_is_enabled(dev)) {
2509 ring->semaphore.sync_to = gen6_ring_sync;
2510 ring->semaphore.signal = gen6_signal;
2511 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;
2512 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV;
2513 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB;
2514 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID;
2515 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2516 ring->semaphore.mbox.signal[RCS] = GEN6_RVESYNC;
2517 ring->semaphore.mbox.signal[VCS] = GEN6_VVESYNC;
2518 ring->semaphore.mbox.signal[BCS] = GEN6_BVESYNC;
2519 ring->semaphore.mbox.signal[VECS] = GEN6_NOSYNC;
2520 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2523 ring->init = init_ring_common;
2525 return intel_init_ring_buffer(dev, ring);
2529 intel_ring_flush_all_caches(struct intel_engine_cs *ring)
2533 if (!ring->gpu_caches_dirty)
2536 ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS);
2540 trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS);
2542 ring->gpu_caches_dirty = false;
2547 intel_ring_invalidate_all_caches(struct intel_engine_cs *ring)
2549 uint32_t flush_domains;
2553 if (ring->gpu_caches_dirty)
2554 flush_domains = I915_GEM_GPU_DOMAINS;
2556 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2560 trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2562 ring->gpu_caches_dirty = false;
2567 intel_stop_ring_buffer(struct intel_engine_cs *ring)
2571 if (!intel_ring_initialized(ring))
2574 ret = intel_ring_idle(ring);
2575 if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
2576 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",