drivers/gpu/drm/i915/intel_ringbuffer.c

   1 /*
   2  * Copyright © 2008-2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Zou Nan hai <nanhai.zou@intel.com>
  26  *    Xiang Hai hao<haihao.xiang@intel.com>
  27  *
  28  */
  29
  30 #include <linux/log2.h>
  31 #include <drm/drmP.h>
  32 #include "i915_drv.h"
  33 #include <drm/i915_drm.h>
  34 #include "i915_trace.h"
  35 #include "intel_drv.h"
  36
  37 int __intel_ring_space(int head, int tail, int size)
  38 {
  39         int space = head - tail;
  40         if (space <= 0)
  41                 space += size;
  42         return space - I915_RING_FREE_SPACE;
  43 }
  44
  45 void intel_ring_update_space(struct intel_ringbuffer *ringbuf)
  46 {
  47         if (ringbuf->last_retired_head != -1) {
  48                 ringbuf->head = ringbuf->last_retired_head;
  49                 ringbuf->last_retired_head = -1;
  50         }
  51
  52         ringbuf->space = __intel_ring_space(ringbuf->head & HEAD_ADDR,
  53                                             ringbuf->tail, ringbuf->size);
  54 }
  55
  56 bool intel_engine_stopped(struct intel_engine_cs *engine)
  57 {
  58         struct drm_i915_private *dev_priv = engine->dev->dev_private;
  59         return dev_priv->gpu_error.stop_rings & intel_engine_flag(engine);
  60 }
  61
  62 static void __intel_ring_advance(struct intel_engine_cs *engine)
  63 {
  64         struct intel_ringbuffer *ringbuf = engine->buffer;
  65         ringbuf->tail &= ringbuf->size - 1;
  66         if (intel_engine_stopped(engine))
  67                 return;
  68         engine->write_tail(engine, ringbuf->tail);
  69 }
  70
  71 static int
  72 gen2_render_ring_flush(struct drm_i915_gem_request *req,
  73                        u32      invalidate_domains,
  74                        u32      flush_domains)
  75 {
  76         struct intel_engine_cs *engine = req->engine;
  77         u32 cmd;
  78         int ret;
  79
  80         cmd = MI_FLUSH;
  81         if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
  82                 cmd |= MI_NO_WRITE_FLUSH;
  83
  84         if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
  85                 cmd |= MI_READ_FLUSH;
  86
  87         ret = intel_ring_begin(req, 2);
  88         if (ret)
  89                 return ret;
  90
  91         intel_ring_emit(engine, cmd);
  92         intel_ring_emit(engine, MI_NOOP);
  93         intel_ring_advance(engine);
  94
  95         return 0;
  96 }
  97
  98 static int
  99 gen4_render_ring_flush(struct drm_i915_gem_request *req,
 100                        u32      invalidate_domains,
 101                        u32      flush_domains)
 102 {
 103         struct intel_engine_cs *engine = req->engine;
 104         struct drm_device *dev = engine->dev;
 105         u32 cmd;
 106         int ret;
 107
 108         /*
 109          * read/write caches:
 110          *
 111          * I915_GEM_DOMAIN_RENDER is always invalidated, but is
 112          * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
 113          * also flushed at 2d versus 3d pipeline switches.
 114          *
 115          * read-only caches:
 116          *
 117          * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
 118          * MI_READ_FLUSH is set, and is always flushed on 965.
 119          *
 120          * I915_GEM_DOMAIN_COMMAND may not exist?
 121          *
 122          * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
 123          * invalidated when MI_EXE_FLUSH is set.
 124          *
 125          * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
 126          * invalidated with every MI_FLUSH.
 127          *
 128          * TLBs:
 129          *
 130          * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
 131          * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
 132          * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
 133          * are flushed at any MI_FLUSH.
 134          */
 135
 136         cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
 137         if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
 138                 cmd &= ~MI_NO_WRITE_FLUSH;
 139         if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
 140                 cmd |= MI_EXE_FLUSH;
 141
 142         if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
 143             (IS_G4X(dev) || IS_GEN5(dev)))
 144                 cmd |= MI_INVALIDATE_ISP;
 145
 146         ret = intel_ring_begin(req, 2);
 147         if (ret)
 148                 return ret;
 149
 150         intel_ring_emit(engine, cmd);
 151         intel_ring_emit(engine, MI_NOOP);
 152         intel_ring_advance(engine);
 153
 154         return 0;
 155 }
 156
 157 /**
 158  * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
 159  * implementing two workarounds on gen6.  From section 1.4.7.1
 160  * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
 161  *
 162  * [DevSNB-C+{W/A}] Before any depth stall flush (including those
 163  * produced by non-pipelined state commands), software needs to first
 164  * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
 165  * 0.
 166  *
 167  * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
 168  * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
 169  *
 170  * And the workaround for these two requires this workaround first:
 171  *
 172  * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
 173  * BEFORE the pipe-control with a post-sync op and no write-cache
 174  * flushes.
 175  *
 176  * And this last workaround is tricky because of the requirements on
 177  * that bit.  From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
 178  * volume 2 part 1:
 179  *
 180  *     "1 of the following must also be set:
 181  *      - Render Target Cache Flush Enable ([12] of DW1)
 182  *      - Depth Cache Flush Enable ([0] of DW1)
 183  *      - Stall at Pixel Scoreboard ([1] of DW1)
 184  *      - Depth Stall ([13] of DW1)
 185  *      - Post-Sync Operation ([13] of DW1)
 186  *      - Notify Enable ([8] of DW1)"
 187  *
 188  * The cache flushes require the workaround flush that triggered this
 189  * one, so we can't use it.  Depth stall would trigger the same.
 190  * Post-sync nonzero is what triggered this second workaround, so we
 191  * can't use that one either.  Notify enable is IRQs, which aren't
 192  * really our business.  That leaves only stall at scoreboard.
 193  */
 194 static int
 195 intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request *req)
 196 {
 197         struct intel_engine_cs *engine = req->engine;
 198         u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 199         int ret;
 200
 201         ret = intel_ring_begin(req, 6);
 202         if (ret)
 203                 return ret;
 204
 205         intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(5));
 206         intel_ring_emit(engine, PIPE_CONTROL_CS_STALL |
 207                         PIPE_CONTROL_STALL_AT_SCOREBOARD);
 208         intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 209         intel_ring_emit(engine, 0); /* low dword */
 210         intel_ring_emit(engine, 0); /* high dword */
 211         intel_ring_emit(engine, MI_NOOP);
 212         intel_ring_advance(engine);
 213
 214         ret = intel_ring_begin(req, 6);
 215         if (ret)
 216                 return ret;
 217
 218         intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(5));
 219         intel_ring_emit(engine, PIPE_CONTROL_QW_WRITE);
 220         intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 221         intel_ring_emit(engine, 0);
 222         intel_ring_emit(engine, 0);
 223         intel_ring_emit(engine, MI_NOOP);
 224         intel_ring_advance(engine);
 225
 226         return 0;
 227 }
 228
 229 static int
 230 gen6_render_ring_flush(struct drm_i915_gem_request *req,
 231                        u32 invalidate_domains, u32 flush_domains)
 232 {
 233         struct intel_engine_cs *engine = req->engine;
 234         u32 flags = 0;
 235         u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 236         int ret;
 237
 238         /* Force SNB workarounds for PIPE_CONTROL flushes */
 239         ret = intel_emit_post_sync_nonzero_flush(req);
 240         if (ret)
 241                 return ret;
 242
 243         /* Just flush everything.  Experiments have shown that reducing the
 244          * number of bits based on the write domains has little performance
 245          * impact.
 246          */
 247         if (flush_domains) {
 248                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 249                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 250                 /*
 251                  * Ensure that any following seqno writes only happen
 252                  * when the render cache is indeed flushed.
 253                  */
 254                 flags |= PIPE_CONTROL_CS_STALL;
 255         }
 256         if (invalidate_domains) {
 257                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 258                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 259                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 260                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 261                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 262                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 263                 /*
 264                  * TLB invalidate requires a post-sync write.
 265                  */
 266                 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
 267         }
 268
 269         ret = intel_ring_begin(req, 4);
 270         if (ret)
 271                 return ret;
 272
 273         intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4));
 274         intel_ring_emit(engine, flags);
 275         intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
 276         intel_ring_emit(engine, 0);
 277         intel_ring_advance(engine);
 278
 279         return 0;
 280 }
 281
 282 static int
 283 gen7_render_ring_cs_stall_wa(struct drm_i915_gem_request *req)
 284 {
 285         struct intel_engine_cs *engine = req->engine;
 286         int ret;
 287
 288         ret = intel_ring_begin(req, 4);
 289         if (ret)
 290                 return ret;
 291
 292         intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4));
 293         intel_ring_emit(engine, PIPE_CONTROL_CS_STALL |
 294                               PIPE_CONTROL_STALL_AT_SCOREBOARD);
 295         intel_ring_emit(engine, 0);
 296         intel_ring_emit(engine, 0);
 297         intel_ring_advance(engine);
 298
 299         return 0;
 300 }
 301
 302 static int
 303 gen7_render_ring_flush(struct drm_i915_gem_request *req,
 304                        u32 invalidate_domains, u32 flush_domains)
 305 {
 306         struct intel_engine_cs *engine = req->engine;
 307         u32 flags = 0;
 308         u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 309         int ret;
 310
 311         /*
 312          * Ensure that any following seqno writes only happen when the render
 313          * cache is indeed flushed.
 314          *
 315          * Workaround: 4th PIPE_CONTROL command (except the ones with only
 316          * read-cache invalidate bits set) must have the CS_STALL bit set. We
 317          * don't try to be clever and just set it unconditionally.
 318          */
 319         flags |= PIPE_CONTROL_CS_STALL;
 320
 321         /* Just flush everything.  Experiments have shown that reducing the
 322          * number of bits based on the write domains has little performance
 323          * impact.
 324          */
 325         if (flush_domains) {
 326                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 327                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 328                 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
 329                 flags |= PIPE_CONTROL_FLUSH_ENABLE;
 330         }
 331         if (invalidate_domains) {
 332                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 333                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 334                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 335                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 336                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 337                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 338                 flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
 339                 /*
 340                  * TLB invalidate requires a post-sync write.
 341                  */
 342                 flags |= PIPE_CONTROL_QW_WRITE;
 343                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 344
 345                 flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
 346
 347                 /* Workaround: we must issue a pipe_control with CS-stall bit
 348                  * set before a pipe_control command that has the state cache
 349                  * invalidate bit set. */
 350                 gen7_render_ring_cs_stall_wa(req);
 351         }
 352
 353         ret = intel_ring_begin(req, 4);
 354         if (ret)
 355                 return ret;
 356
 357         intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4));
 358         intel_ring_emit(engine, flags);
 359         intel_ring_emit(engine, scratch_addr);
 360         intel_ring_emit(engine, 0);
 361         intel_ring_advance(engine);
 362
 363         return 0;
 364 }
 365
 366 static int
 367 gen8_emit_pipe_control(struct drm_i915_gem_request *req,
 368                        u32 flags, u32 scratch_addr)
 369 {
 370         struct intel_engine_cs *engine = req->engine;
 371         int ret;
 372
 373         ret = intel_ring_begin(req, 6);
 374         if (ret)
 375                 return ret;
 376
 377         intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(6));
 378         intel_ring_emit(engine, flags);
 379         intel_ring_emit(engine, scratch_addr);
 380         intel_ring_emit(engine, 0);
 381         intel_ring_emit(engine, 0);
 382         intel_ring_emit(engine, 0);
 383         intel_ring_advance(engine);
 384
 385         return 0;
 386 }
 387
 388 static int
 389 gen8_render_ring_flush(struct drm_i915_gem_request *req,
 390                        u32 invalidate_domains, u32 flush_domains)
 391 {
 392         u32 flags = 0;
 393         u32 scratch_addr = req->engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 394         int ret;
 395
 396         flags |= PIPE_CONTROL_CS_STALL;
 397
 398         if (flush_domains) {
 399                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 400                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 401                 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
 402                 flags |= PIPE_CONTROL_FLUSH_ENABLE;
 403         }
 404         if (invalidate_domains) {
 405                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 406                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 407                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 408                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 409                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 410                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 411                 flags |= PIPE_CONTROL_QW_WRITE;
 412                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 413
 414                 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
 415                 ret = gen8_emit_pipe_control(req,
 416                                              PIPE_CONTROL_CS_STALL |
 417                                              PIPE_CONTROL_STALL_AT_SCOREBOARD,
 418                                              0);
 419                 if (ret)
 420                         return ret;
 421         }
 422
 423         return gen8_emit_pipe_control(req, flags, scratch_addr);
 424 }
 425
 426 static void ring_write_tail(struct intel_engine_cs *engine,
 427                             u32 value)
 428 {
 429         struct drm_i915_private *dev_priv = engine->dev->dev_private;
 430         I915_WRITE_TAIL(engine, value);
 431 }
 432
 433 u64 intel_ring_get_active_head(struct intel_engine_cs *engine)
 434 {
 435         struct drm_i915_private *dev_priv = engine->dev->dev_private;
 436         u64 acthd;
 437
 438         if (INTEL_INFO(engine->dev)->gen >= 8)
 439                 acthd = I915_READ64_2x32(RING_ACTHD(engine->mmio_base),
 440                                          RING_ACTHD_UDW(engine->mmio_base));
 441         else if (INTEL_INFO(engine->dev)->gen >= 4)
 442                 acthd = I915_READ(RING_ACTHD(engine->mmio_base));
 443         else
 444                 acthd = I915_READ(ACTHD);
 445
 446         return acthd;
 447 }
 448
 449 static void ring_setup_phys_status_page(struct intel_engine_cs *engine)
 450 {
 451         struct drm_i915_private *dev_priv = engine->dev->dev_private;
 452         u32 addr;
 453
 454         addr = dev_priv->status_page_dmah->busaddr;
 455         if (INTEL_INFO(engine->dev)->gen >= 4)
 456                 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
 457         I915_WRITE(HWS_PGA, addr);
 458 }
 459
 460 static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
 461 {
 462         struct drm_device *dev = engine->dev;
 463         struct drm_i915_private *dev_priv = engine->dev->dev_private;
 464         i915_reg_t mmio;
 465
 466         /* The ring status page addresses are no longer next to the rest of
 467          * the ring registers as of gen7.
 468          */
 469         if (IS_GEN7(dev)) {
 470                 switch (engine->id) {
 471                 case RCS:
 472                         mmio = RENDER_HWS_PGA_GEN7;
 473                         break;
 474                 case BCS:
 475                         mmio = BLT_HWS_PGA_GEN7;
 476                         break;
 477                 /*
 478                  * VCS2 actually doesn't exist on Gen7. Only shut up
 479                  * gcc switch check warning
 480                  */
 481                 case VCS2:
 482                 case VCS:
 483                         mmio = BSD_HWS_PGA_GEN7;
 484                         break;
 485                 case VECS:
 486                         mmio = VEBOX_HWS_PGA_GEN7;
 487                         break;
 488                 }
 489         } else if (IS_GEN6(engine->dev)) {
 490                 mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
 491         } else {
 492                 /* XXX: gen8 returns to sanity */
 493                 mmio = RING_HWS_PGA(engine->mmio_base);
 494         }
 495
 496         I915_WRITE(mmio, (u32)engine->status_page.gfx_addr);
 497         POSTING_READ(mmio);
 498
 499         /*
 500          * Flush the TLB for this page
 501          *
 502          * FIXME: These two bits have disappeared on gen8, so a question
 503          * arises: do we still need this and if so how should we go about
 504          * invalidating the TLB?
 505          */
 506         if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
 507                 i915_reg_t reg = RING_INSTPM(engine->mmio_base);
 508
 509                 /* ring should be idle before issuing a sync flush*/
 510                 WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0);
 511
 512                 I915_WRITE(reg,
 513                            _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
 514                                               INSTPM_SYNC_FLUSH));
 515                 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
 516                              1000))
 517                         DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
 518                                   engine->name);
 519         }
 520 }
 521
 522 static bool stop_ring(struct intel_engine_cs *engine)
 523 {
 524         struct drm_i915_private *dev_priv = to_i915(engine->dev);
 525
 526         if (!IS_GEN2(engine->dev)) {
 527                 I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING));
 528                 if (wait_for((I915_READ_MODE(engine) & MODE_IDLE) != 0, 1000)) {
 529                         DRM_ERROR("%s : timed out trying to stop ring\n",
 530                                   engine->name);
 531                         /* Sometimes we observe that the idle flag is not
 532                          * set even though the ring is empty. So double
 533                          * check before giving up.
 534                          */
 535                         if (I915_READ_HEAD(engine) != I915_READ_TAIL(engine))
 536                                 return false;
 537                 }
 538         }
 539
 540         I915_WRITE_CTL(engine, 0);
 541         I915_WRITE_HEAD(engine, 0);
 542         engine->write_tail(engine, 0);
 543
 544         if (!IS_GEN2(engine->dev)) {
 545                 (void)I915_READ_CTL(engine);
 546                 I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING));
 547         }
 548
 549         return (I915_READ_HEAD(engine) & HEAD_ADDR) == 0;
 550 }
 551
 552 void intel_engine_init_hangcheck(struct intel_engine_cs *engine)
 553 {
 554         memset(&engine->hangcheck, 0, sizeof(engine->hangcheck));
 555 }
 556
 557 static int init_ring_common(struct intel_engine_cs *engine)
 558 {
 559         struct drm_device *dev = engine->dev;
 560         struct drm_i915_private *dev_priv = dev->dev_private;
 561         struct intel_ringbuffer *ringbuf = engine->buffer;
 562         struct drm_i915_gem_object *obj = ringbuf->obj;
 563         int ret = 0;
 564
 565         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
 566
 567         if (!stop_ring(engine)) {
 568                 /* G45 ring initialization often fails to reset head to zero */
 569                 DRM_DEBUG_KMS("%s head not reset to zero "
 570                               "ctl %08x head %08x tail %08x start %08x\n",
 571                               engine->name,
 572                               I915_READ_CTL(engine),
 573                               I915_READ_HEAD(engine),
 574                               I915_READ_TAIL(engine),
 575                               I915_READ_START(engine));
 576
 577                 if (!stop_ring(engine)) {
 578                         DRM_ERROR("failed to set %s head to zero "
 579                                   "ctl %08x head %08x tail %08x start %08x\n",
 580                                   engine->name,
 581                                   I915_READ_CTL(engine),
 582                                   I915_READ_HEAD(engine),
 583                                   I915_READ_TAIL(engine),
 584                                   I915_READ_START(engine));
 585                         ret = -EIO;
 586                         goto out;
 587                 }
 588         }
 589
 590         if (I915_NEED_GFX_HWS(dev))
 591                 intel_ring_setup_status_page(engine);
 592         else
 593                 ring_setup_phys_status_page(engine);
 594
 595         /* Enforce ordering by reading HEAD register back */
 596         I915_READ_HEAD(engine);
 597
 598         /* Initialize the ring. This must happen _after_ we've cleared the ring
 599          * registers with the above sequence (the readback of the HEAD registers
 600          * also enforces ordering), otherwise the hw might lose the new ring
 601          * register values. */
 602         I915_WRITE_START(engine, i915_gem_obj_ggtt_offset(obj));
 603
 604         /* WaClearRingBufHeadRegAtInit:ctg,elk */
 605         if (I915_READ_HEAD(engine))
 606                 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
 607                           engine->name, I915_READ_HEAD(engine));
 608         I915_WRITE_HEAD(engine, 0);
 609         (void)I915_READ_HEAD(engine);
 610
 611         I915_WRITE_CTL(engine,
 612                         ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES)
 613                         | RING_VALID);
 614
 615         /* If the head is still not zero, the ring is dead */
 616         if (wait_for((I915_READ_CTL(engine) & RING_VALID) != 0 &&
 617                      I915_READ_START(engine) == i915_gem_obj_ggtt_offset(obj) &&
 618                      (I915_READ_HEAD(engine) & HEAD_ADDR) == 0, 50)) {
 619                 DRM_ERROR("%s initialization failed "
 620                           "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
 621                           engine->name,
 622                           I915_READ_CTL(engine),
 623                           I915_READ_CTL(engine) & RING_VALID,
 624                           I915_READ_HEAD(engine), I915_READ_TAIL(engine),
 625                           I915_READ_START(engine),
 626                           (unsigned long)i915_gem_obj_ggtt_offset(obj));
 627                 ret = -EIO;
 628                 goto out;
 629         }
 630
 631         ringbuf->last_retired_head = -1;
 632         ringbuf->head = I915_READ_HEAD(engine);
 633         ringbuf->tail = I915_READ_TAIL(engine) & TAIL_ADDR;
 634         intel_ring_update_space(ringbuf);
 635
 636         intel_engine_init_hangcheck(engine);
 637
 638 out:
 639         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
 640
 641         return ret;
 642 }
 643
 644 void
 645 intel_fini_pipe_control(struct intel_engine_cs *engine)
 646 {
 647         struct drm_device *dev = engine->dev;
 648
 649         if (engine->scratch.obj == NULL)
 650                 return;
 651
 652         if (INTEL_INFO(dev)->gen >= 5) {
 653                 kunmap(sg_page(engine->scratch.obj->pages->sgl));
 654                 i915_gem_object_ggtt_unpin(engine->scratch.obj);
 655         }
 656
 657         drm_gem_object_unreference(&engine->scratch.obj->base);
 658         engine->scratch.obj = NULL;
 659 }
 660
 661 int
 662 intel_init_pipe_control(struct intel_engine_cs *engine)
 663 {
 664         int ret;
 665
 666         WARN_ON(engine->scratch.obj);
 667
 668         engine->scratch.obj = i915_gem_alloc_object(engine->dev, 4096);
 669         if (engine->scratch.obj == NULL) {
 670                 DRM_ERROR("Failed to allocate seqno page\n");
 671                 ret = -ENOMEM;
 672                 goto err;
 673         }
 674
 675         ret = i915_gem_object_set_cache_level(engine->scratch.obj,
 676                                               I915_CACHE_LLC);
 677         if (ret)
 678                 goto err_unref;
 679
 680         ret = i915_gem_obj_ggtt_pin(engine->scratch.obj, 4096, 0);
 681         if (ret)
 682                 goto err_unref;
 683
 684         engine->scratch.gtt_offset = i915_gem_obj_ggtt_offset(engine->scratch.obj);
 685         engine->scratch.cpu_page = kmap(sg_page(engine->scratch.obj->pages->sgl));
 686         if (engine->scratch.cpu_page == NULL) {
 687                 ret = -ENOMEM;
 688                 goto err_unpin;
 689         }
 690
 691         DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
 692                          engine->name, engine->scratch.gtt_offset);
 693         return 0;
 694
 695 err_unpin:
 696         i915_gem_object_ggtt_unpin(engine->scratch.obj);
 697 err_unref:
 698         drm_gem_object_unreference(&engine->scratch.obj->base);
 699 err:
 700         return ret;
 701 }
 702
 703 static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req)
 704 {
 705         int ret, i;
 706         struct intel_engine_cs *engine = req->engine;
 707         struct drm_device *dev = engine->dev;
 708         struct drm_i915_private *dev_priv = dev->dev_private;
 709         struct i915_workarounds *w = &dev_priv->workarounds;
 710
 711         if (w->count == 0)
 712                 return 0;
 713
 714         engine->gpu_caches_dirty = true;
 715         ret = intel_ring_flush_all_caches(req);
 716         if (ret)
 717                 return ret;
 718
 719         ret = intel_ring_begin(req, (w->count * 2 + 2));
 720         if (ret)
 721                 return ret;
 722
 723         intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(w->count));
 724         for (i = 0; i < w->count; i++) {
 725                 intel_ring_emit_reg(engine, w->reg[i].addr);
 726                 intel_ring_emit(engine, w->reg[i].value);
 727         }
 728         intel_ring_emit(engine, MI_NOOP);
 729
 730         intel_ring_advance(engine);
 731
 732         engine->gpu_caches_dirty = true;
 733         ret = intel_ring_flush_all_caches(req);
 734         if (ret)
 735                 return ret;
 736
 737         DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count);
 738
 739         return 0;
 740 }
 741
 742 static int intel_rcs_ctx_init(struct drm_i915_gem_request *req)
 743 {
 744         int ret;
 745
 746         ret = intel_ring_workarounds_emit(req);
 747         if (ret != 0)
 748                 return ret;
 749
 750         ret = i915_gem_render_state_init(req);
 751         if (ret)
 752                 return ret;
 753
 754         return 0;
 755 }
 756
 757 static int wa_add(struct drm_i915_private *dev_priv,
 758                   i915_reg_t addr,
 759                   const u32 mask, const u32 val)
 760 {
 761         const u32 idx = dev_priv->workarounds.count;
 762
 763         if (WARN_ON(idx >= I915_MAX_WA_REGS))
 764                 return -ENOSPC;
 765
 766         dev_priv->workarounds.reg[idx].addr = addr;
 767         dev_priv->workarounds.reg[idx].value = val;
 768         dev_priv->workarounds.reg[idx].mask = mask;
 769
 770         dev_priv->workarounds.count++;
 771
 772         return 0;
 773 }
 774
 775 #define WA_REG(addr, mask, val) do { \
 776                 const int r = wa_add(dev_priv, (addr), (mask), (val)); \
 777                 if (r) \
 778                         return r; \
 779         } while (0)
 780
 781 #define WA_SET_BIT_MASKED(addr, mask) \
 782         WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
 783
 784 #define WA_CLR_BIT_MASKED(addr, mask) \
 785         WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
 786
 787 #define WA_SET_FIELD_MASKED(addr, mask, value) \
 788         WA_REG(addr, mask, _MASKED_FIELD(mask, value))
 789
 790 #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
 791 #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
 792
 793 #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
 794
 795 static int wa_ring_whitelist_reg(struct intel_engine_cs *engine,
 796                                  i915_reg_t reg)
 797 {
 798         struct drm_i915_private *dev_priv = engine->dev->dev_private;
 799         struct i915_workarounds *wa = &dev_priv->workarounds;
 800         const uint32_t index = wa->hw_whitelist_count[engine->id];
 801
 802         if (WARN_ON(index >= RING_MAX_NONPRIV_SLOTS))
 803                 return -EINVAL;
 804
 805         WA_WRITE(RING_FORCE_TO_NONPRIV(engine->mmio_base, index),
 806                  i915_mmio_reg_offset(reg));
 807         wa->hw_whitelist_count[engine->id]++;
 808
 809         return 0;
 810 }
 811
 812 static int gen8_init_workarounds(struct intel_engine_cs *engine)
 813 {
 814         struct drm_device *dev = engine->dev;
 815         struct drm_i915_private *dev_priv = dev->dev_private;
 816
 817         WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
 818
 819         /* WaDisableAsyncFlipPerfMode:bdw,chv */
 820         WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
 821
 822         /* WaDisablePartialInstShootdown:bdw,chv */
 823         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 824                           PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
 825
 826         /* Use Force Non-Coherent whenever executing a 3D context. This is a
 827          * workaround for for a possible hang in the unlikely event a TLB
 828          * invalidation occurs during a PSD flush.
 829          */
 830         /* WaForceEnableNonCoherent:bdw,chv */
 831         /* WaHdcDisableFetchWhenMasked:bdw,chv */
 832         WA_SET_BIT_MASKED(HDC_CHICKEN0,
 833                           HDC_DONOT_FETCH_MEM_WHEN_MASKED |
 834                           HDC_FORCE_NON_COHERENT);
 835
 836         /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
 837          * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
 838          *  polygons in the same 8x4 pixel/sample area to be processed without
 839          *  stalling waiting for the earlier ones to write to Hierarchical Z
 840          *  buffer."
 841          *
 842          * This optimization is off by default for BDW and CHV; turn it on.
 843          */
 844         WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
 845
 846         /* Wa4x4STCOptimizationDisable:bdw,chv */
 847         WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
 848
 849         /*
 850          * BSpec recommends 8x4 when MSAA is used,
 851          * however in practice 16x4 seems fastest.
 852          *
 853          * Note that PS/WM thread counts depend on the WIZ hashing
 854          * disable bit, which we don't touch here, but it's good
 855          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
 856          */
 857         WA_SET_FIELD_MASKED(GEN7_GT_MODE,
 858                             GEN6_WIZ_HASHING_MASK,
 859                             GEN6_WIZ_HASHING_16x4);
 860
 861         return 0;
 862 }
 863
 864 static int bdw_init_workarounds(struct intel_engine_cs *engine)
 865 {
 866         int ret;
 867         struct drm_device *dev = engine->dev;
 868         struct drm_i915_private *dev_priv = dev->dev_private;
 869
 870         ret = gen8_init_workarounds(engine);
 871         if (ret)
 872                 return ret;
 873
 874         /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
 875         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
 876
 877         /* WaDisableDopClockGating:bdw */
 878         WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
 879                           DOP_CLOCK_GATING_DISABLE);
 880
 881         WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
 882                           GEN8_SAMPLER_POWER_BYPASS_DIS);
 883
 884         WA_SET_BIT_MASKED(HDC_CHICKEN0,
 885                           /* WaForceContextSaveRestoreNonCoherent:bdw */
 886                           HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
 887                           /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
 888                           (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
 889
 890         return 0;
 891 }
 892
 893 static int chv_init_workarounds(struct intel_engine_cs *engine)
 894 {
 895         int ret;
 896         struct drm_device *dev = engine->dev;
 897         struct drm_i915_private *dev_priv = dev->dev_private;
 898
 899         ret = gen8_init_workarounds(engine);
 900         if (ret)
 901                 return ret;
 902
 903         /* WaDisableThreadStallDopClockGating:chv */
 904         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
 905
 906         /* Improve HiZ throughput on CHV. */
 907         WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
 908
 909         return 0;
 910 }
 911
 912 static int gen9_init_workarounds(struct intel_engine_cs *engine)
 913 {
 914         struct drm_device *dev = engine->dev;
 915         struct drm_i915_private *dev_priv = dev->dev_private;
 916         int ret;
 917
 918         /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl */
 919         I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
 920                    GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
 921
 922         /* WaDisableKillLogic:bxt,skl,kbl */
 923         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
 924                    ECOCHK_DIS_TLB);
 925
 926         /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl */
 927         /* WaDisablePartialInstShootdown:skl,bxt,kbl */
 928         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 929                           FLOW_CONTROL_ENABLE |
 930                           PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
 931
 932         /* Syncing dependencies between camera and graphics:skl,bxt,kbl */
 933         WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
 934                           GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
 935
 936         /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */
 937         if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
 938             IS_BXT_REVID(dev, 0, BXT_REVID_A1))
 939                 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
 940                                   GEN9_DG_MIRROR_FIX_ENABLE);
 941
 942         /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
 943         if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
 944             IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
 945                 WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
 946                                   GEN9_RHWO_OPTIMIZATION_DISABLE);
 947                 /*
 948                  * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set
 949                  * but we do that in per ctx batchbuffer as there is an issue
 950                  * with this register not getting restored on ctx restore
 951                  */
 952         }
 953
 954         /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl */
 955         /* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl */
 956         WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
 957                           GEN9_ENABLE_YV12_BUGFIX |
 958                           GEN9_ENABLE_GPGPU_PREEMPTION);
 959
 960         /* Wa4x4STCOptimizationDisable:skl,bxt,kbl */
 961         /* WaDisablePartialResolveInVc:skl,bxt,kbl */
 962         WA_SET_BIT_MASKED(CACHE_MODE_1, (GEN8_4x4_STC_OPTIMIZATION_DISABLE |
 963                                          GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE));
 964
 965         /* WaCcsTlbPrefetchDisable:skl,bxt,kbl */
 966         WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
 967                           GEN9_CCS_TLB_PREFETCH_ENABLE);
 968
 969         /* WaDisableMaskBasedCammingInRCC:skl,bxt */
 970         if (IS_SKL_REVID(dev, SKL_REVID_C0, SKL_REVID_C0) ||
 971             IS_BXT_REVID(dev, 0, BXT_REVID_A1))
 972                 WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
 973                                   PIXEL_MASK_CAMMING_DISABLE);
 974
 975         /* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl */
 976         WA_SET_BIT_MASKED(HDC_CHICKEN0,
 977                           HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
 978                           HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE);
 979
 980         /* WaForceEnableNonCoherent and WaDisableHDCInvalidation are
 981          * both tied to WaForceContextSaveRestoreNonCoherent
 982          * in some hsds for skl. We keep the tie for all gen9. The
 983          * documentation is a bit hazy and so we want to get common behaviour,
 984          * even though there is no clear evidence we would need both on kbl/bxt.
 985          * This area has been source of system hangs so we play it safe
 986          * and mimic the skl regardless of what bspec says.
 987          *
 988          * Use Force Non-Coherent whenever executing a 3D context. This
 989          * is a workaround for a possible hang in the unlikely event
 990          * a TLB invalidation occurs during a PSD flush.
 991          */
 992
 993         /* WaForceEnableNonCoherent:skl,bxt,kbl */
 994         WA_SET_BIT_MASKED(HDC_CHICKEN0,
 995                           HDC_FORCE_NON_COHERENT);
 996
 997         /* WaDisableHDCInvalidation:skl,bxt,kbl */
 998         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
 999                    BDW_DISABLE_HDC_INVALIDATION);
1000
1001         /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl */
1002         if (IS_SKYLAKE(dev_priv) ||
1003             IS_KABYLAKE(dev_priv) ||
1004             IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0))
1005                 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
1006                                   GEN8_SAMPLER_POWER_BYPASS_DIS);
1007
1008         /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl */
1009         WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
1010
1011         /* WaOCLCoherentLineFlush:skl,bxt,kbl */
1012         I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
1013                                     GEN8_LQSC_FLUSH_COHERENT_LINES));
1014
1015         /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt */
1016         ret = wa_ring_whitelist_reg(engine, GEN9_CTX_PREEMPT_REG);
1017         if (ret)
1018                 return ret;
1019
1020         /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl */
1021         ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1);
1022         if (ret)
1023                 return ret;
1024
1025         /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl */
1026         ret = wa_ring_whitelist_reg(engine, GEN8_HDC_CHICKEN1);
1027         if (ret)
1028                 return ret;
1029
1030         return 0;
1031 }
1032
1033 static int skl_tune_iz_hashing(struct intel_engine_cs *engine)
1034 {
1035         struct drm_device *dev = engine->dev;
1036         struct drm_i915_private *dev_priv = dev->dev_private;
1037         u8 vals[3] = { 0, 0, 0 };
1038         unsigned int i;
1039
1040         for (i = 0; i < 3; i++) {
1041                 u8 ss;
1042
1043                 /*
1044                  * Only consider slices where one, and only one, subslice has 7
1045                  * EUs
1046                  */
1047                 if (!is_power_of_2(dev_priv->info.subslice_7eu[i]))
1048                         continue;
1049
1050                 /*
1051                  * subslice_7eu[i] != 0 (because of the check above) and
1052                  * ss_max == 4 (maximum number of subslices possible per slice)
1053                  *
1054                  * ->    0 <= ss <= 3;
1055                  */
1056                 ss = ffs(dev_priv->info.subslice_7eu[i]) - 1;
1057                 vals[i] = 3 - ss;
1058         }
1059
1060         if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0)
1061                 return 0;
1062
1063         /* Tune IZ hashing. See intel_device_info_runtime_init() */
1064         WA_SET_FIELD_MASKED(GEN7_GT_MODE,
1065                             GEN9_IZ_HASHING_MASK(2) |
1066                             GEN9_IZ_HASHING_MASK(1) |
1067                             GEN9_IZ_HASHING_MASK(0),
1068                             GEN9_IZ_HASHING(2, vals[2]) |
1069                             GEN9_IZ_HASHING(1, vals[1]) |
1070                             GEN9_IZ_HASHING(0, vals[0]));
1071
1072         return 0;
1073 }
1074
1075 static int skl_init_workarounds(struct intel_engine_cs *engine)
1076 {
1077         int ret;
1078         struct drm_device *dev = engine->dev;
1079         struct drm_i915_private *dev_priv = dev->dev_private;
1080
1081         ret = gen9_init_workarounds(engine);
1082         if (ret)
1083                 return ret;
1084
1085         /*
1086          * Actual WA is to disable percontext preemption granularity control
1087          * until D0 which is the default case so this is equivalent to
1088          * !WaDisablePerCtxtPreemptionGranularityControl:skl
1089          */
1090         if (IS_SKL_REVID(dev, SKL_REVID_E0, REVID_FOREVER)) {
1091                 I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1,
1092                            _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL));
1093         }
1094
1095         if (IS_SKL_REVID(dev, 0, SKL_REVID_D0)) {
1096                 /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
1097                 I915_WRITE(FF_SLICE_CS_CHICKEN2,
1098                            _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE));
1099         }
1100
1101         /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes
1102          * involving this register should also be added to WA batch as required.
1103          */
1104         if (IS_SKL_REVID(dev, 0, SKL_REVID_E0))
1105                 /* WaDisableLSQCROPERFforOCL:skl */
1106                 I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
1107                            GEN8_LQSC_RO_PERF_DIS);
1108
1109         /* WaEnableGapsTsvCreditFix:skl */
1110         if (IS_SKL_REVID(dev, SKL_REVID_C0, REVID_FOREVER)) {
1111                 I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
1112                                            GEN9_GAPS_TSV_CREDIT_DISABLE));
1113         }
1114
1115         /* WaDisablePowerCompilerClockGating:skl */
1116         if (IS_SKL_REVID(dev, SKL_REVID_B0, SKL_REVID_B0))
1117                 WA_SET_BIT_MASKED(HIZ_CHICKEN,
1118                                   BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
1119
1120         /* WaBarrierPerformanceFixDisable:skl */
1121         if (IS_SKL_REVID(dev, SKL_REVID_C0, SKL_REVID_D0))
1122                 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1123                                   HDC_FENCE_DEST_SLM_DISABLE |
1124                                   HDC_BARRIER_PERFORMANCE_DISABLE);
1125
1126         /* WaDisableSbeCacheDispatchPortSharing:skl */
1127         if (IS_SKL_REVID(dev, 0, SKL_REVID_F0))
1128                 WA_SET_BIT_MASKED(
1129                         GEN7_HALF_SLICE_CHICKEN1,
1130                         GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1131
1132         /* WaDisableGafsUnitClkGating:skl */
1133         WA_SET_BIT(GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
1134
1135         /* WaDisableLSQCROPERFforOCL:skl */
1136         ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
1137         if (ret)
1138                 return ret;
1139
1140         return skl_tune_iz_hashing(engine);
1141 }
1142
1143 static int bxt_init_workarounds(struct intel_engine_cs *engine)
1144 {
1145         int ret;
1146         struct drm_device *dev = engine->dev;
1147         struct drm_i915_private *dev_priv = dev->dev_private;
1148
1149         ret = gen9_init_workarounds(engine);
1150         if (ret)
1151                 return ret;
1152
1153         /* WaStoreMultiplePTEenable:bxt */
1154         /* This is a requirement according to Hardware specification */
1155         if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
1156                 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
1157
1158         /* WaSetClckGatingDisableMedia:bxt */
1159         if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
1160                 I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) &
1161                                             ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE));
1162         }
1163
1164         /* WaDisableThreadStallDopClockGating:bxt */
1165         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
1166                           STALL_DOP_GATING_DISABLE);
1167
1168         /* WaDisableSbeCacheDispatchPortSharing:bxt */
1169         if (IS_BXT_REVID(dev, 0, BXT_REVID_B0)) {
1170                 WA_SET_BIT_MASKED(
1171                         GEN7_HALF_SLICE_CHICKEN1,
1172                         GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1173         }
1174
1175         /* WaDisableObjectLevelPreemptionForTrifanOrPolygon:bxt */
1176         /* WaDisableObjectLevelPreemptionForInstancedDraw:bxt */
1177         /* WaDisableObjectLevelPreemtionForInstanceId:bxt */
1178         /* WaDisableLSQCROPERFforOCL:bxt */
1179         if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
1180                 ret = wa_ring_whitelist_reg(engine, GEN9_CS_DEBUG_MODE1);
1181                 if (ret)
1182                         return ret;
1183
1184                 ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
1185                 if (ret)
1186                         return ret;
1187         }
1188
1189         /* WaInsertDummyPushConstPs:bxt */
1190         if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0))
1191                 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
1192                                   GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
1193
1194         return 0;
1195 }
1196
1197 static int kbl_init_workarounds(struct intel_engine_cs *engine)
1198 {
1199         struct drm_i915_private *dev_priv = engine->dev->dev_private;
1200         int ret;
1201
1202         ret = gen9_init_workarounds(engine);
1203         if (ret)
1204                 return ret;
1205
1206         /* WaEnableGapsTsvCreditFix:kbl */
1207         I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
1208                                    GEN9_GAPS_TSV_CREDIT_DISABLE));
1209
1210         /* WaDisableDynamicCreditSharing:kbl */
1211         if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
1212                 WA_SET_BIT(GAMT_CHKN_BIT_REG,
1213                            GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING);
1214
1215         /* WaDisableFenceDestinationToSLM:kbl (pre-prod) */
1216         if (IS_KBL_REVID(dev_priv, KBL_REVID_A0, KBL_REVID_A0))
1217                 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1218                                   HDC_FENCE_DEST_SLM_DISABLE);
1219
1220         /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes
1221          * involving this register should also be added to WA batch as required.
1222          */
1223         if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_E0))
1224                 /* WaDisableLSQCROPERFforOCL:kbl */
1225                 I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
1226                            GEN8_LQSC_RO_PERF_DIS);
1227
1228         /* WaInsertDummyPushConstPs:kbl */
1229         if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
1230                 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
1231                                   GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
1232
1233         /* WaDisableGafsUnitClkGating:kbl */
1234         WA_SET_BIT(GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
1235
1236         /* WaDisableSbeCacheDispatchPortSharing:kbl */
1237         WA_SET_BIT_MASKED(
1238                 GEN7_HALF_SLICE_CHICKEN1,
1239                 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1240
1241         /* WaDisableLSQCROPERFforOCL:kbl */
1242         ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
1243         if (ret)
1244                 return ret;
1245
1246         return 0;
1247 }
1248
1249 int init_workarounds_ring(struct intel_engine_cs *engine)
1250 {
1251         struct drm_device *dev = engine->dev;
1252         struct drm_i915_private *dev_priv = dev->dev_private;
1253
1254         WARN_ON(engine->id != RCS);
1255
1256         dev_priv->workarounds.count = 0;
1257         dev_priv->workarounds.hw_whitelist_count[RCS] = 0;
1258
1259         if (IS_BROADWELL(dev))
1260                 return bdw_init_workarounds(engine);
1261
1262         if (IS_CHERRYVIEW(dev))
1263                 return chv_init_workarounds(engine);
1264
1265         if (IS_SKYLAKE(dev))
1266                 return skl_init_workarounds(engine);
1267
1268         if (IS_BROXTON(dev))
1269                 return bxt_init_workarounds(engine);
1270
1271         if (IS_KABYLAKE(dev_priv))
1272                 return kbl_init_workarounds(engine);
1273
1274         return 0;
1275 }
1276
1277 static int init_render_ring(struct intel_engine_cs *engine)
1278 {
1279         struct drm_device *dev = engine->dev;
1280         struct drm_i915_private *dev_priv = dev->dev_private;
1281         int ret = init_ring_common(engine);
1282         if (ret)
1283                 return ret;
1284
1285         /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
1286         if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7)
1287                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
1288
1289         /* We need to disable the AsyncFlip performance optimisations in order
1290          * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1291          * programmed to '1' on all products.
1292          *
1293          * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
1294          */
1295         if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
1296                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1297
1298         /* Required for the hardware to program scanline values for waiting */
1299         /* WaEnableFlushTlbInvalidationMode:snb */
1300         if (INTEL_INFO(dev)->gen == 6)
1301                 I915_WRITE(GFX_MODE,
1302                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
1303
1304         /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
1305         if (IS_GEN7(dev))
1306                 I915_WRITE(GFX_MODE_GEN7,
1307                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
1308                            _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
1309
1310         if (IS_GEN6(dev)) {
1311                 /* From the Sandybridge PRM, volume 1 part 3, page 24:
1312                  * "If this bit is set, STCunit will have LRA as replacement
1313                  *  policy. [...] This bit must be reset.  LRA replacement
1314                  *  policy is not supported."
1315                  */
1316                 I915_WRITE(CACHE_MODE_0,
1317                            _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
1318         }
1319
1320         if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
1321                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
1322
1323         if (HAS_L3_DPF(dev))
1324                 I915_WRITE_IMR(engine, ~GT_PARITY_ERROR(dev));
1325
1326         return init_workarounds_ring(engine);
1327 }
1328
1329 static void render_ring_cleanup(struct intel_engine_cs *engine)
1330 {
1331         struct drm_device *dev = engine->dev;
1332         struct drm_i915_private *dev_priv = dev->dev_private;
1333
1334         if (dev_priv->semaphore_obj) {
1335                 i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj);
1336                 drm_gem_object_unreference(&dev_priv->semaphore_obj->base);
1337                 dev_priv->semaphore_obj = NULL;
1338         }
1339
1340         intel_fini_pipe_control(engine);
1341 }
1342
1343 static int gen8_rcs_signal(struct drm_i915_gem_request *signaller_req,
1344                            unsigned int num_dwords)
1345 {
1346 #define MBOX_UPDATE_DWORDS 8
1347         struct intel_engine_cs *signaller = signaller_req->engine;
1348         struct drm_device *dev = signaller->dev;
1349         struct drm_i915_private *dev_priv = dev->dev_private;
1350         struct intel_engine_cs *waiter;
1351         enum intel_engine_id id;
1352         int ret, num_rings;
1353
1354         num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1355         num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1356 #undef MBOX_UPDATE_DWORDS
1357
1358         ret = intel_ring_begin(signaller_req, num_dwords);
1359         if (ret)
1360                 return ret;
1361
1362         for_each_engine_id(waiter, dev_priv, id) {
1363                 u32 seqno;
1364                 u64 gtt_offset = signaller->semaphore.signal_ggtt[id];
1365                 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1366                         continue;
1367
1368                 seqno = i915_gem_request_get_seqno(signaller_req);
1369                 intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
1370                 intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |
1371                                            PIPE_CONTROL_QW_WRITE |
1372                                            PIPE_CONTROL_FLUSH_ENABLE);
1373                 intel_ring_emit(signaller, lower_32_bits(gtt_offset));
1374                 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
1375                 intel_ring_emit(signaller, seqno);
1376                 intel_ring_emit(signaller, 0);
1377                 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1378                                            MI_SEMAPHORE_TARGET(waiter->hw_id));
1379                 intel_ring_emit(signaller, 0);
1380         }
1381
1382         return 0;
1383 }
1384
1385 static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req,
1386                            unsigned int num_dwords)
1387 {
1388 #define MBOX_UPDATE_DWORDS 6
1389         struct intel_engine_cs *signaller = signaller_req->engine;
1390         struct drm_device *dev = signaller->dev;
1391         struct drm_i915_private *dev_priv = dev->dev_private;
1392         struct intel_engine_cs *waiter;
1393         enum intel_engine_id id;
1394         int ret, num_rings;
1395
1396         num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1397         num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1398 #undef MBOX_UPDATE_DWORDS
1399
1400         ret = intel_ring_begin(signaller_req, num_dwords);
1401         if (ret)
1402                 return ret;
1403
1404         for_each_engine_id(waiter, dev_priv, id) {
1405                 u32 seqno;
1406                 u64 gtt_offset = signaller->semaphore.signal_ggtt[id];
1407                 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1408                         continue;
1409
1410                 seqno = i915_gem_request_get_seqno(signaller_req);
1411                 intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |
1412                                            MI_FLUSH_DW_OP_STOREDW);
1413                 intel_ring_emit(signaller, lower_32_bits(gtt_offset) |
1414                                            MI_FLUSH_DW_USE_GTT);
1415                 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
1416                 intel_ring_emit(signaller, seqno);
1417                 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1418                                            MI_SEMAPHORE_TARGET(waiter->hw_id));
1419                 intel_ring_emit(signaller, 0);
1420         }
1421
1422         return 0;
1423 }
1424
1425 static int gen6_signal(struct drm_i915_gem_request *signaller_req,
1426                        unsigned int num_dwords)
1427 {
1428         struct intel_engine_cs *signaller = signaller_req->engine;
1429         struct drm_device *dev = signaller->dev;
1430         struct drm_i915_private *dev_priv = dev->dev_private;
1431         struct intel_engine_cs *useless;
1432         enum intel_engine_id id;
1433         int ret, num_rings;
1434
1435 #define MBOX_UPDATE_DWORDS 3
1436         num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1437         num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
1438 #undef MBOX_UPDATE_DWORDS
1439
1440         ret = intel_ring_begin(signaller_req, num_dwords);
1441         if (ret)
1442                 return ret;
1443
1444         for_each_engine_id(useless, dev_priv, id) {
1445                 i915_reg_t mbox_reg = signaller->semaphore.mbox.signal[id];
1446
1447                 if (i915_mmio_reg_valid(mbox_reg)) {
1448                         u32 seqno = i915_gem_request_get_seqno(signaller_req);
1449
1450                         intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
1451                         intel_ring_emit_reg(signaller, mbox_reg);
1452                         intel_ring_emit(signaller, seqno);
1453                 }
1454         }
1455
1456         /* If num_dwords was rounded, make sure the tail pointer is correct */
1457         if (num_rings % 2 == 0)
1458                 intel_ring_emit(signaller, MI_NOOP);
1459
1460         return 0;
1461 }
1462
1463 /**
1464  * gen6_add_request - Update the semaphore mailbox registers
1465  *
1466  * @request - request to write to the ring
1467  *
1468  * Update the mailbox registers in the *other* rings with the current seqno.
1469  * This acts like a signal in the canonical semaphore.
1470  */
1471 static int
1472 gen6_add_request(struct drm_i915_gem_request *req)
1473 {
1474         struct intel_engine_cs *engine = req->engine;
1475         int ret;
1476
1477         if (engine->semaphore.signal)
1478                 ret = engine->semaphore.signal(req, 4);
1479         else
1480                 ret = intel_ring_begin(req, 4);
1481
1482         if (ret)
1483                 return ret;
1484
1485         intel_ring_emit(engine, MI_STORE_DWORD_INDEX);
1486         intel_ring_emit(engine,
1487                         I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1488         intel_ring_emit(engine, i915_gem_request_get_seqno(req));
1489         intel_ring_emit(engine, MI_USER_INTERRUPT);
1490         __intel_ring_advance(engine);
1491
1492         return 0;
1493 }
1494
1495 static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
1496                                               u32 seqno)
1497 {
1498         struct drm_i915_private *dev_priv = dev->dev_private;
1499         return dev_priv->last_seqno < seqno;
1500 }
1501
1502 /**
1503  * intel_ring_sync - sync the waiter to the signaller on seqno
1504  *
1505  * @waiter - ring that is waiting
1506  * @signaller - ring which has, or will signal
1507  * @seqno - seqno which the waiter will block on
1508  */
1509
1510 static int
1511 gen8_ring_sync(struct drm_i915_gem_request *waiter_req,
1512                struct intel_engine_cs *signaller,
1513                u32 seqno)
1514 {
1515         struct intel_engine_cs *waiter = waiter_req->engine;
1516         struct drm_i915_private *dev_priv = waiter->dev->dev_private;
1517         int ret;
1518
1519         ret = intel_ring_begin(waiter_req, 4);
1520         if (ret)
1521                 return ret;
1522
1523         intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |
1524                                 MI_SEMAPHORE_GLOBAL_GTT |
1525                                 MI_SEMAPHORE_POLL |
1526                                 MI_SEMAPHORE_SAD_GTE_SDD);
1527         intel_ring_emit(waiter, seqno);
1528         intel_ring_emit(waiter,
1529                         lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1530         intel_ring_emit(waiter,
1531                         upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1532         intel_ring_advance(waiter);
1533         return 0;
1534 }
1535
1536 static int
1537 gen6_ring_sync(struct drm_i915_gem_request *waiter_req,
1538                struct intel_engine_cs *signaller,
1539                u32 seqno)
1540 {
1541         struct intel_engine_cs *waiter = waiter_req->engine;
1542         u32 dw1 = MI_SEMAPHORE_MBOX |
1543                   MI_SEMAPHORE_COMPARE |
1544                   MI_SEMAPHORE_REGISTER;
1545         u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id];
1546         int ret;
1547
1548         /* Throughout all of the GEM code, seqno passed implies our current
1549          * seqno is >= the last seqno executed. However for hardware the
1550          * comparison is strictly greater than.
1551          */
1552         seqno -= 1;
1553
1554         WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
1555
1556         ret = intel_ring_begin(waiter_req, 4);
1557         if (ret)
1558                 return ret;
1559
1560         /* If seqno wrap happened, omit the wait with no-ops */
1561         if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
1562                 intel_ring_emit(waiter, dw1 | wait_mbox);
1563                 intel_ring_emit(waiter, seqno);
1564                 intel_ring_emit(waiter, 0);
1565                 intel_ring_emit(waiter, MI_NOOP);
1566         } else {
1567                 intel_ring_emit(waiter, MI_NOOP);
1568                 intel_ring_emit(waiter, MI_NOOP);
1569                 intel_ring_emit(waiter, MI_NOOP);
1570                 intel_ring_emit(waiter, MI_NOOP);
1571         }
1572         intel_ring_advance(waiter);
1573
1574         return 0;
1575 }
1576
1577 #define PIPE_CONTROL_FLUSH(ring__, addr__)                                      \
1578 do {                                                                    \
1579         intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |                \
1580                  PIPE_CONTROL_DEPTH_STALL);                             \
1581         intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT);                    \
1582         intel_ring_emit(ring__, 0);                                                     \
1583         intel_ring_emit(ring__, 0);                                                     \
1584 } while (0)
1585
1586 static int
1587 pc_render_add_request(struct drm_i915_gem_request *req)
1588 {
1589         struct intel_engine_cs *engine = req->engine;
1590         u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
1591         int ret;
1592
1593         /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
1594          * incoherent with writes to memory, i.e. completely fubar,
1595          * so we need to use PIPE_NOTIFY instead.
1596          *
1597          * However, we also need to workaround the qword write
1598          * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
1599          * memory before requesting an interrupt.
1600          */
1601         ret = intel_ring_begin(req, 32);
1602         if (ret)
1603                 return ret;
1604
1605         intel_ring_emit(engine,
1606                         GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1607                         PIPE_CONTROL_WRITE_FLUSH |
1608                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
1609         intel_ring_emit(engine,
1610                         engine->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1611         intel_ring_emit(engine, i915_gem_request_get_seqno(req));
1612         intel_ring_emit(engine, 0);
1613         PIPE_CONTROL_FLUSH(engine, scratch_addr);
1614         scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
1615         PIPE_CONTROL_FLUSH(engine, scratch_addr);
1616         scratch_addr += 2 * CACHELINE_BYTES;
1617         PIPE_CONTROL_FLUSH(engine, scratch_addr);
1618         scratch_addr += 2 * CACHELINE_BYTES;
1619         PIPE_CONTROL_FLUSH(engine, scratch_addr);
1620         scratch_addr += 2 * CACHELINE_BYTES;
1621         PIPE_CONTROL_FLUSH(engine, scratch_addr);
1622         scratch_addr += 2 * CACHELINE_BYTES;
1623         PIPE_CONTROL_FLUSH(engine, scratch_addr);
1624
1625         intel_ring_emit(engine,
1626                         GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1627                         PIPE_CONTROL_WRITE_FLUSH |
1628                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
1629                         PIPE_CONTROL_NOTIFY);
1630         intel_ring_emit(engine,
1631                         engine->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1632         intel_ring_emit(engine, i915_gem_request_get_seqno(req));
1633         intel_ring_emit(engine, 0);
1634         __intel_ring_advance(engine);
1635
1636         return 0;
1637 }
1638
1639 static void
1640 gen6_seqno_barrier(struct intel_engine_cs *engine)
1641 {
1642         struct drm_i915_private *dev_priv = engine->dev->dev_private;
1643
1644         /* Workaround to force correct ordering between irq and seqno writes on
1645          * ivb (and maybe also on snb) by reading from a CS register (like
1646          * ACTHD) before reading the status page.
1647          *
1648          * Note that this effectively stalls the read by the time it takes to
1649          * do a memory transaction, which more or less ensures that the write
1650          * from the GPU has sufficient time to invalidate the CPU cacheline.
1651          * Alternatively we could delay the interrupt from the CS ring to give
1652          * the write time to land, but that would incur a delay after every
1653          * batch i.e. much more frequent than a delay when waiting for the
1654          * interrupt (with the same net latency).
1655          *
1656          * Also note that to prevent whole machine hangs on gen7, we have to
1657          * take the spinlock to guard against concurrent cacheline access.
1658          */
1659         spin_lock_irq(&dev_priv->uncore.lock);
1660         POSTING_READ_FW(RING_ACTHD(engine->mmio_base));
1661         spin_unlock_irq(&dev_priv->uncore.lock);
1662 }
1663
1664 static u32
1665 ring_get_seqno(struct intel_engine_cs *engine)
1666 {
1667         return intel_read_status_page(engine, I915_GEM_HWS_INDEX);
1668 }
1669
1670 static void
1671 ring_set_seqno(struct intel_engine_cs *engine, u32 seqno)
1672 {
1673         intel_write_status_page(engine, I915_GEM_HWS_INDEX, seqno);
1674 }
1675
1676 static u32
1677 pc_render_get_seqno(struct intel_engine_cs *engine)
1678 {
1679         return engine->scratch.cpu_page[0];
1680 }
1681
1682 static void
1683 pc_render_set_seqno(struct intel_engine_cs *engine, u32 seqno)
1684 {
1685         engine->scratch.cpu_page[0] = seqno;
1686 }
1687
1688 static bool
1689 gen5_ring_get_irq(struct intel_engine_cs *engine)
1690 {
1691         struct drm_device *dev = engine->dev;
1692         struct drm_i915_private *dev_priv = dev->dev_private;
1693         unsigned long flags;
1694
1695         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1696                 return false;
1697
1698         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1699         if (engine->irq_refcount++ == 0)
1700                 gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask);
1701         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1702
1703         return true;
1704 }
1705
1706 static void
1707 gen5_ring_put_irq(struct intel_engine_cs *engine)
1708 {
1709         struct drm_device *dev = engine->dev;
1710         struct drm_i915_private *dev_priv = dev->dev_private;
1711         unsigned long flags;
1712
1713         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1714         if (--engine->irq_refcount == 0)
1715                 gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask);
1716         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1717 }
1718
1719 static bool
1720 i9xx_ring_get_irq(struct intel_engine_cs *engine)
1721 {
1722         struct drm_device *dev = engine->dev;
1723         struct drm_i915_private *dev_priv = dev->dev_private;
1724         unsigned long flags;
1725
1726         if (!intel_irqs_enabled(dev_priv))
1727                 return false;
1728
1729         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1730         if (engine->irq_refcount++ == 0) {
1731                 dev_priv->irq_mask &= ~engine->irq_enable_mask;
1732                 I915_WRITE(IMR, dev_priv->irq_mask);
1733                 POSTING_READ(IMR);
1734         }
1735         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1736
1737         return true;
1738 }
1739
1740 static void
1741 i9xx_ring_put_irq(struct intel_engine_cs *engine)
1742 {
1743         struct drm_device *dev = engine->dev;
1744         struct drm_i915_private *dev_priv = dev->dev_private;
1745         unsigned long flags;
1746
1747         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1748         if (--engine->irq_refcount == 0) {
1749                 dev_priv->irq_mask |= engine->irq_enable_mask;
1750                 I915_WRITE(IMR, dev_priv->irq_mask);
1751                 POSTING_READ(IMR);
1752         }
1753         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1754 }
1755
1756 static bool
1757 i8xx_ring_get_irq(struct intel_engine_cs *engine)
1758 {
1759         struct drm_device *dev = engine->dev;
1760         struct drm_i915_private *dev_priv = dev->dev_private;
1761         unsigned long flags;
1762
1763         if (!intel_irqs_enabled(dev_priv))
1764                 return false;
1765
1766         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1767         if (engine->irq_refcount++ == 0) {
1768                 dev_priv->irq_mask &= ~engine->irq_enable_mask;
1769                 I915_WRITE16(IMR, dev_priv->irq_mask);
1770                 POSTING_READ16(IMR);
1771         }
1772         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1773
1774         return true;
1775 }
1776
1777 static void
1778 i8xx_ring_put_irq(struct intel_engine_cs *engine)
1779 {
1780         struct drm_device *dev = engine->dev;
1781         struct drm_i915_private *dev_priv = dev->dev_private;
1782         unsigned long flags;
1783
1784         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1785         if (--engine->irq_refcount == 0) {
1786                 dev_priv->irq_mask |= engine->irq_enable_mask;
1787                 I915_WRITE16(IMR, dev_priv->irq_mask);
1788                 POSTING_READ16(IMR);
1789         }
1790         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1791 }
1792
1793 static int
1794 bsd_ring_flush(struct drm_i915_gem_request *req,
1795                u32     invalidate_domains,
1796                u32     flush_domains)
1797 {
1798         struct intel_engine_cs *engine = req->engine;
1799         int ret;
1800
1801         ret = intel_ring_begin(req, 2);
1802         if (ret)
1803                 return ret;
1804
1805         intel_ring_emit(engine, MI_FLUSH);
1806         intel_ring_emit(engine, MI_NOOP);
1807         intel_ring_advance(engine);
1808         return 0;
1809 }
1810
1811 static int
1812 i9xx_add_request(struct drm_i915_gem_request *req)
1813 {
1814         struct intel_engine_cs *engine = req->engine;
1815         int ret;
1816
1817         ret = intel_ring_begin(req, 4);
1818         if (ret)
1819                 return ret;
1820
1821         intel_ring_emit(engine, MI_STORE_DWORD_INDEX);
1822         intel_ring_emit(engine,
1823                         I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1824         intel_ring_emit(engine, i915_gem_request_get_seqno(req));
1825         intel_ring_emit(engine, MI_USER_INTERRUPT);
1826         __intel_ring_advance(engine);
1827
1828         return 0;
1829 }
1830
1831 static bool
1832 gen6_ring_get_irq(struct intel_engine_cs *engine)
1833 {
1834         struct drm_device *dev = engine->dev;
1835         struct drm_i915_private *dev_priv = dev->dev_private;
1836         unsigned long flags;
1837
1838         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1839                 return false;
1840
1841         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1842         if (engine->irq_refcount++ == 0) {
1843                 if (HAS_L3_DPF(dev) && engine->id == RCS)
1844                         I915_WRITE_IMR(engine,
1845                                        ~(engine->irq_enable_mask |
1846                                          GT_PARITY_ERROR(dev)));
1847                 else
1848                         I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
1849                 gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask);
1850         }
1851         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1852
1853         return true;
1854 }
1855
1856 static void
1857 gen6_ring_put_irq(struct intel_engine_cs *engine)
1858 {
1859         struct drm_device *dev = engine->dev;
1860         struct drm_i915_private *dev_priv = dev->dev_private;
1861         unsigned long flags;
1862
1863         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1864         if (--engine->irq_refcount == 0) {
1865                 if (HAS_L3_DPF(dev) && engine->id == RCS)
1866                         I915_WRITE_IMR(engine, ~GT_PARITY_ERROR(dev));
1867                 else
1868                         I915_WRITE_IMR(engine, ~0);
1869                 gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask);
1870         }
1871         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1872 }
1873
1874 static bool
1875 hsw_vebox_get_irq(struct intel_engine_cs *engine)
1876 {
1877         struct drm_device *dev = engine->dev;
1878         struct drm_i915_private *dev_priv = dev->dev_private;
1879         unsigned long flags;
1880
1881         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1882                 return false;
1883
1884         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1885         if (engine->irq_refcount++ == 0) {
1886                 I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
1887                 gen6_enable_pm_irq(dev_priv, engine->irq_enable_mask);
1888         }
1889         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1890
1891         return true;
1892 }
1893
1894 static void
1895 hsw_vebox_put_irq(struct intel_engine_cs *engine)
1896 {
1897         struct drm_device *dev = engine->dev;
1898         struct drm_i915_private *dev_priv = dev->dev_private;
1899         unsigned long flags;
1900
1901         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1902         if (--engine->irq_refcount == 0) {
1903                 I915_WRITE_IMR(engine, ~0);
1904                 gen6_disable_pm_irq(dev_priv, engine->irq_enable_mask);
1905         }
1906         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1907 }
1908
1909 static bool
1910 gen8_ring_get_irq(struct intel_engine_cs *engine)
1911 {
1912         struct drm_device *dev = engine->dev;
1913         struct drm_i915_private *dev_priv = dev->dev_private;
1914         unsigned long flags;
1915
1916         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1917                 return false;
1918
1919         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1920         if (engine->irq_refcount++ == 0) {
1921                 if (HAS_L3_DPF(dev) && engine->id == RCS) {
1922                         I915_WRITE_IMR(engine,
1923                                        ~(engine->irq_enable_mask |
1924                                          GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1925                 } else {
1926                         I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
1927                 }
1928                 POSTING_READ(RING_IMR(engine->mmio_base));
1929         }
1930         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1931
1932         return true;
1933 }
1934
1935 static void
1936 gen8_ring_put_irq(struct intel_engine_cs *engine)
1937 {
1938         struct drm_device *dev = engine->dev;
1939         struct drm_i915_private *dev_priv = dev->dev_private;
1940         unsigned long flags;
1941
1942         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1943         if (--engine->irq_refcount == 0) {
1944                 if (HAS_L3_DPF(dev) && engine->id == RCS) {
1945                         I915_WRITE_IMR(engine,
1946                                        ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1947                 } else {
1948                         I915_WRITE_IMR(engine, ~0);
1949                 }
1950                 POSTING_READ(RING_IMR(engine->mmio_base));
1951         }
1952         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1953 }
1954
1955 static int
1956 i965_dispatch_execbuffer(struct drm_i915_gem_request *req,
1957                          u64 offset, u32 length,
1958                          unsigned dispatch_flags)
1959 {
1960         struct intel_engine_cs *engine = req->engine;
1961         int ret;
1962
1963         ret = intel_ring_begin(req, 2);
1964         if (ret)
1965                 return ret;
1966
1967         intel_ring_emit(engine,
1968                         MI_BATCH_BUFFER_START |
1969                         MI_BATCH_GTT |
1970                         (dispatch_flags & I915_DISPATCH_SECURE ?
1971                          0 : MI_BATCH_NON_SECURE_I965));
1972         intel_ring_emit(engine, offset);
1973         intel_ring_advance(engine);
1974
1975         return 0;
1976 }
1977
1978 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1979 #define I830_BATCH_LIMIT (256*1024)
1980 #define I830_TLB_ENTRIES (2)
1981 #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
1982 static int
1983 i830_dispatch_execbuffer(struct drm_i915_gem_request *req,
1984                          u64 offset, u32 len,
1985                          unsigned dispatch_flags)
1986 {
1987         struct intel_engine_cs *engine = req->engine;
1988         u32 cs_offset = engine->scratch.gtt_offset;
1989         int ret;
1990
1991         ret = intel_ring_begin(req, 6);
1992         if (ret)
1993                 return ret;
1994
1995         /* Evict the invalid PTE TLBs */
1996         intel_ring_emit(engine, COLOR_BLT_CMD | BLT_WRITE_RGBA);
1997         intel_ring_emit(engine, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096);
1998         intel_ring_emit(engine, I830_TLB_ENTRIES << 16 | 4); /* load each page */
1999         intel_ring_emit(engine, cs_offset);
2000         intel_ring_emit(engine, 0xdeadbeef);
2001         intel_ring_emit(engine, MI_NOOP);
2002         intel_ring_advance(engine);
2003
2004         if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) {
2005                 if (len > I830_BATCH_LIMIT)
2006                         return -ENOSPC;
2007
2008                 ret = intel_ring_begin(req, 6 + 2);
2009                 if (ret)
2010                         return ret;
2011
2012                 /* Blit the batch (which has now all relocs applied) to the
2013                  * stable batch scratch bo area (so that the CS never
2014                  * stumbles over its tlb invalidation bug) ...
2015                  */
2016                 intel_ring_emit(engine, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA);
2017                 intel_ring_emit(engine,
2018                                 BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096);
2019                 intel_ring_emit(engine, DIV_ROUND_UP(len, 4096) << 16 | 4096);
2020                 intel_ring_emit(engine, cs_offset);
2021                 intel_ring_emit(engine, 4096);
2022                 intel_ring_emit(engine, offset);
2023
2024                 intel_ring_emit(engine, MI_FLUSH);
2025                 intel_ring_emit(engine, MI_NOOP);
2026                 intel_ring_advance(engine);
2027
2028                 /* ... and execute it. */
2029                 offset = cs_offset;
2030         }
2031
2032         ret = intel_ring_begin(req, 2);
2033         if (ret)
2034                 return ret;
2035
2036         intel_ring_emit(engine, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
2037         intel_ring_emit(engine, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
2038                                           0 : MI_BATCH_NON_SECURE));
2039         intel_ring_advance(engine);
2040
2041         return 0;
2042 }
2043
2044 static int
2045 i915_dispatch_execbuffer(struct drm_i915_gem_request *req,
2046                          u64 offset, u32 len,
2047                          unsigned dispatch_flags)
2048 {
2049         struct intel_engine_cs *engine = req->engine;
2050         int ret;
2051
2052         ret = intel_ring_begin(req, 2);
2053         if (ret)
2054                 return ret;
2055
2056         intel_ring_emit(engine, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
2057         intel_ring_emit(engine, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
2058                                           0 : MI_BATCH_NON_SECURE));
2059         intel_ring_advance(engine);
2060
2061         return 0;
2062 }
2063
2064 static void cleanup_phys_status_page(struct intel_engine_cs *engine)
2065 {
2066         struct drm_i915_private *dev_priv = to_i915(engine->dev);
2067
2068         if (!dev_priv->status_page_dmah)
2069                 return;
2070
2071         drm_pci_free(engine->dev, dev_priv->status_page_dmah);
2072         engine->status_page.page_addr = NULL;
2073 }
2074
2075 static void cleanup_status_page(struct intel_engine_cs *engine)
2076 {
2077         struct drm_i915_gem_object *obj;
2078
2079         obj = engine->status_page.obj;
2080         if (obj == NULL)
2081                 return;
2082
2083         kunmap(sg_page(obj->pages->sgl));
2084         i915_gem_object_ggtt_unpin(obj);
2085         drm_gem_object_unreference(&obj->base);
2086         engine->status_page.obj = NULL;
2087 }
2088
2089 static int init_status_page(struct intel_engine_cs *engine)
2090 {
2091         struct drm_i915_gem_object *obj = engine->status_page.obj;
2092
2093         if (obj == NULL) {
2094                 unsigned flags;
2095                 int ret;
2096
2097                 obj = i915_gem_alloc_object(engine->dev, 4096);
2098                 if (obj == NULL) {
2099                         DRM_ERROR("Failed to allocate status page\n");
2100                         return -ENOMEM;
2101                 }
2102
2103                 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2104                 if (ret)
2105                         goto err_unref;
2106
2107                 flags = 0;
2108                 if (!HAS_LLC(engine->dev))
2109                         /* On g33, we cannot place HWS above 256MiB, so
2110                          * restrict its pinning to the low mappable arena.
2111                          * Though this restriction is not documented for
2112                          * gen4, gen5, or byt, they also behave similarly
2113                          * and hang if the HWS is placed at the top of the
2114                          * GTT. To generalise, it appears that all !llc
2115                          * platforms have issues with us placing the HWS
2116                          * above the mappable region (even though we never
2117                          * actualy map it).
2118                          */
2119                         flags |= PIN_MAPPABLE;
2120                 ret = i915_gem_obj_ggtt_pin(obj, 4096, flags);
2121                 if (ret) {
2122 err_unref:
2123                         drm_gem_object_unreference(&obj->base);
2124                         return ret;
2125                 }
2126
2127                 engine->status_page.obj = obj;
2128         }
2129
2130         engine->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
2131         engine->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
2132         memset(engine->status_page.page_addr, 0, PAGE_SIZE);
2133
2134         DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
2135                         engine->name, engine->status_page.gfx_addr);
2136
2137         return 0;
2138 }
2139
2140 static int init_phys_status_page(struct intel_engine_cs *engine)
2141 {
2142         struct drm_i915_private *dev_priv = engine->dev->dev_private;
2143
2144         if (!dev_priv->status_page_dmah) {
2145                 dev_priv->status_page_dmah =
2146                         drm_pci_alloc(engine->dev, PAGE_SIZE, PAGE_SIZE);
2147                 if (!dev_priv->status_page_dmah)
2148                         return -ENOMEM;
2149         }
2150
2151         engine->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
2152         memset(engine->status_page.page_addr, 0, PAGE_SIZE);
2153
2154         return 0;
2155 }
2156
2157 void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
2158 {
2159         if (HAS_LLC(ringbuf->obj->base.dev) && !ringbuf->obj->stolen)
2160                 i915_gem_object_unpin_map(ringbuf->obj);
2161         else
2162                 iounmap(ringbuf->virtual_start);
2163         ringbuf->virtual_start = NULL;
2164         ringbuf->vma = NULL;
2165         i915_gem_object_ggtt_unpin(ringbuf->obj);
2166 }
2167
2168 int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
2169                                      struct intel_ringbuffer *ringbuf)
2170 {
2171         struct drm_i915_private *dev_priv = to_i915(dev);
2172         struct i915_ggtt *ggtt = &dev_priv->ggtt;
2173         struct drm_i915_gem_object *obj = ringbuf->obj;
2174         /* Ring wraparound at offset 0 sometimes hangs. No idea why. */
2175         unsigned flags = PIN_OFFSET_BIAS | 4096;
2176         void *addr;
2177         int ret;
2178
2179         if (HAS_LLC(dev_priv) && !obj->stolen) {
2180                 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, flags);
2181                 if (ret)
2182                         return ret;
2183
2184                 ret = i915_gem_object_set_to_cpu_domain(obj, true);
2185                 if (ret)
2186                         goto err_unpin;
2187
2188                 addr = i915_gem_object_pin_map(obj);
2189                 if (IS_ERR(addr)) {
2190                         ret = PTR_ERR(addr);
2191                         goto err_unpin;
2192                 }
2193         } else {
2194                 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE,
2195                                             flags | PIN_MAPPABLE);
2196                 if (ret)
2197                         return ret;
2198
2199                 ret = i915_gem_object_set_to_gtt_domain(obj, true);
2200                 if (ret)
2201                         goto err_unpin;
2202
2203                 /* Access through the GTT requires the device to be awake. */
2204                 assert_rpm_wakelock_held(dev_priv);
2205
2206                 addr = ioremap_wc(ggtt->mappable_base +
2207                                   i915_gem_obj_ggtt_offset(obj), ringbuf->size);
2208                 if (addr == NULL) {
2209                         ret = -ENOMEM;
2210                         goto err_unpin;
2211                 }
2212         }
2213
2214         ringbuf->virtual_start = addr;
2215         ringbuf->vma = i915_gem_obj_to_ggtt(obj);
2216         return 0;
2217
2218 err_unpin:
2219         i915_gem_object_ggtt_unpin(obj);
2220         return ret;
2221 }
2222
2223 static void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
2224 {
2225         drm_gem_object_unreference(&ringbuf->obj->base);
2226         ringbuf->obj = NULL;
2227 }
2228
2229 static int intel_alloc_ringbuffer_obj(struct drm_device *dev,
2230                                       struct intel_ringbuffer *ringbuf)
2231 {
2232         struct drm_i915_gem_object *obj;
2233
2234         obj = NULL;
2235         if (!HAS_LLC(dev))
2236                 obj = i915_gem_object_create_stolen(dev, ringbuf->size);
2237         if (obj == NULL)
2238                 obj = i915_gem_alloc_object(dev, ringbuf->size);
2239         if (obj == NULL)
2240                 return -ENOMEM;
2241
2242         /* mark ring buffers as read-only from GPU side by default */
2243         obj->gt_ro = 1;
2244
2245         ringbuf->obj = obj;
2246
2247         return 0;
2248 }
2249
2250 struct intel_ringbuffer *
2251 intel_engine_create_ringbuffer(struct intel_engine_cs *engine, int size)
2252 {
2253         struct intel_ringbuffer *ring;
2254         int ret;
2255
2256         ring = kzalloc(sizeof(*ring), GFP_KERNEL);
2257         if (ring == NULL) {
2258                 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n",
2259                                  engine->name);
2260                 return ERR_PTR(-ENOMEM);
2261         }
2262
2263         ring->engine = engine;
2264         list_add(&ring->link, &engine->buffers);
2265
2266         ring->size = size;
2267         /* Workaround an erratum on the i830 which causes a hang if
2268          * the TAIL pointer points to within the last 2 cachelines
2269          * of the buffer.
2270          */
2271         ring->effective_size = size;
2272         if (IS_I830(engine->dev) || IS_845G(engine->dev))
2273                 ring->effective_size -= 2 * CACHELINE_BYTES;
2274
2275         ring->last_retired_head = -1;
2276         intel_ring_update_space(ring);
2277
2278         ret = intel_alloc_ringbuffer_obj(engine->dev, ring);
2279         if (ret) {
2280                 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s: %d\n",
2281                                  engine->name, ret);
2282                 list_del(&ring->link);
2283                 kfree(ring);
2284                 return ERR_PTR(ret);
2285         }
2286
2287         return ring;
2288 }
2289
2290 void
2291 intel_ringbuffer_free(struct intel_ringbuffer *ring)
2292 {
2293         intel_destroy_ringbuffer_obj(ring);
2294         list_del(&ring->link);
2295         kfree(ring);
2296 }
2297
2298 static int intel_init_ring_buffer(struct drm_device *dev,
2299                                   struct intel_engine_cs *engine)
2300 {
2301         struct intel_ringbuffer *ringbuf;
2302         int ret;
2303
2304         WARN_ON(engine->buffer);
2305
2306         engine->dev = dev;
2307         INIT_LIST_HEAD(&engine->active_list);
2308         INIT_LIST_HEAD(&engine->request_list);
2309         INIT_LIST_HEAD(&engine->execlist_queue);
2310         INIT_LIST_HEAD(&engine->buffers);
2311         i915_gem_batch_pool_init(dev, &engine->batch_pool);
2312         memset(engine->semaphore.sync_seqno, 0,
2313                sizeof(engine->semaphore.sync_seqno));
2314
2315         init_waitqueue_head(&engine->irq_queue);
2316
2317         ringbuf = intel_engine_create_ringbuffer(engine, 32 * PAGE_SIZE);
2318         if (IS_ERR(ringbuf)) {
2319                 ret = PTR_ERR(ringbuf);
2320                 goto error;
2321         }
2322         engine->buffer = ringbuf;
2323
2324         if (I915_NEED_GFX_HWS(dev)) {
2325                 ret = init_status_page(engine);
2326                 if (ret)
2327                         goto error;
2328         } else {
2329                 WARN_ON(engine->id != RCS);
2330                 ret = init_phys_status_page(engine);
2331                 if (ret)
2332                         goto error;
2333         }
2334
2335         ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
2336         if (ret) {
2337                 DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
2338                                 engine->name, ret);
2339                 intel_destroy_ringbuffer_obj(ringbuf);
2340                 goto error;
2341         }
2342
2343         ret = i915_cmd_parser_init_ring(engine);
2344         if (ret)
2345                 goto error;
2346
2347         return 0;
2348
2349 error:
2350         intel_cleanup_engine(engine);
2351         return ret;
2352 }
2353
2354 void intel_cleanup_engine(struct intel_engine_cs *engine)
2355 {
2356         struct drm_i915_private *dev_priv;
2357
2358         if (!intel_engine_initialized(engine))
2359                 return;
2360
2361         dev_priv = to_i915(engine->dev);
2362
2363         if (engine->buffer) {
2364                 intel_stop_engine(engine);
2365                 WARN_ON(!IS_GEN2(engine->dev) && (I915_READ_MODE(engine) & MODE_IDLE) == 0);
2366
2367                 intel_unpin_ringbuffer_obj(engine->buffer);
2368                 intel_ringbuffer_free(engine->buffer);
2369                 engine->buffer = NULL;
2370         }
2371
2372         if (engine->cleanup)
2373                 engine->cleanup(engine);
2374
2375         if (I915_NEED_GFX_HWS(engine->dev)) {
2376                 cleanup_status_page(engine);
2377         } else {
2378                 WARN_ON(engine->id != RCS);
2379                 cleanup_phys_status_page(engine);
2380         }
2381
2382         i915_cmd_parser_fini_ring(engine);
2383         i915_gem_batch_pool_fini(&engine->batch_pool);
2384         engine->dev = NULL;
2385 }
2386
2387 int intel_engine_idle(struct intel_engine_cs *engine)
2388 {
2389         struct drm_i915_gem_request *req;
2390
2391         /* Wait upon the last request to be completed */
2392         if (list_empty(&engine->request_list))
2393                 return 0;
2394
2395         req = list_entry(engine->request_list.prev,
2396                          struct drm_i915_gem_request,
2397                          list);
2398
2399         /* Make sure we do not trigger any retires */
2400         return __i915_wait_request(req,
2401                                    req->i915->mm.interruptible,
2402                                    NULL, NULL);
2403 }
2404
2405 int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request)
2406 {
2407         request->ringbuf = request->engine->buffer;
2408         return 0;
2409 }
2410
2411 int intel_ring_reserve_space(struct drm_i915_gem_request *request)
2412 {
2413         /*
2414          * The first call merely notes the reserve request and is common for
2415          * all back ends. The subsequent localised _begin() call actually
2416          * ensures that the reservation is available. Without the begin, if
2417          * the request creator immediately submitted the request without
2418          * adding any commands to it then there might not actually be
2419          * sufficient room for the submission commands.
2420          */
2421         intel_ring_reserved_space_reserve(request->ringbuf, MIN_SPACE_FOR_ADD_REQUEST);
2422
2423         return intel_ring_begin(request, 0);
2424 }
2425
2426 void intel_ring_reserved_space_reserve(struct intel_ringbuffer *ringbuf, int size)
2427 {
2428         GEM_BUG_ON(ringbuf->reserved_size);
2429         ringbuf->reserved_size = size;
2430 }
2431
2432 void intel_ring_reserved_space_cancel(struct intel_ringbuffer *ringbuf)
2433 {
2434         GEM_BUG_ON(!ringbuf->reserved_size);
2435         ringbuf->reserved_size   = 0;
2436 }
2437
2438 void intel_ring_reserved_space_use(struct intel_ringbuffer *ringbuf)
2439 {
2440         GEM_BUG_ON(!ringbuf->reserved_size);
2441         ringbuf->reserved_size   = 0;
2442 }
2443
2444 void intel_ring_reserved_space_end(struct intel_ringbuffer *ringbuf)
2445 {
2446         GEM_BUG_ON(ringbuf->reserved_size);
2447 }
2448
2449 static int wait_for_space(struct drm_i915_gem_request *req, int bytes)
2450 {
2451         struct intel_ringbuffer *ringbuf = req->ringbuf;
2452         struct intel_engine_cs *engine = req->engine;
2453         struct drm_i915_gem_request *target;
2454
2455         intel_ring_update_space(ringbuf);
2456         if (ringbuf->space >= bytes)
2457                 return 0;
2458
2459         /*
2460          * Space is reserved in the ringbuffer for finalising the request,
2461          * as that cannot be allowed to fail. During request finalisation,
2462          * reserved_space is set to 0 to stop the overallocation and the
2463          * assumption is that then we never need to wait (which has the
2464          * risk of failing with EINTR).
2465          *
2466          * See also i915_gem_request_alloc() and i915_add_request().
2467          */
2468         GEM_BUG_ON(!ringbuf->reserved_size);
2469
2470         list_for_each_entry(target, &engine->request_list, list) {
2471                 unsigned space;
2472
2473                 /*
2474                  * The request queue is per-engine, so can contain requests
2475                  * from multiple ringbuffers. Here, we must ignore any that
2476                  * aren't from the ringbuffer we're considering.
2477                  */
2478                 if (target->ringbuf != ringbuf)
2479                         continue;
2480
2481                 /* Would completion of this request free enough space? */
2482                 space = __intel_ring_space(target->postfix, ringbuf->tail,
2483                                            ringbuf->size);
2484                 if (space >= bytes)
2485                         break;
2486         }
2487
2488         if (WARN_ON(&target->list == &engine->request_list))
2489                 return -ENOSPC;
2490
2491         return i915_wait_request(target);
2492 }
2493
2494 int intel_ring_begin(struct drm_i915_gem_request *req, int num_dwords)
2495 {
2496         struct intel_ringbuffer *ringbuf = req->ringbuf;
2497         int remain_actual = ringbuf->size - ringbuf->tail;
2498         int remain_usable = ringbuf->effective_size - ringbuf->tail;
2499         int bytes = num_dwords * sizeof(u32);
2500         int total_bytes, wait_bytes;
2501         bool need_wrap = false;
2502
2503         total_bytes = bytes + ringbuf->reserved_size;
2504
2505         if (unlikely(bytes > remain_usable)) {
2506                 /*
2507                  * Not enough space for the basic request. So need to flush
2508                  * out the remainder and then wait for base + reserved.
2509                  */
2510                 wait_bytes = remain_actual + total_bytes;
2511                 need_wrap = true;
2512         } else if (unlikely(total_bytes > remain_usable)) {
2513                 /*
2514                  * The base request will fit but the reserved space
2515                  * falls off the end. So we don't need an immediate wrap
2516                  * and only need to effectively wait for the reserved
2517                  * size space from the start of ringbuffer.
2518                  */
2519                 wait_bytes = remain_actual + ringbuf->reserved_size;
2520         } else {
2521                 /* No wrapping required, just waiting. */
2522                 wait_bytes = total_bytes;
2523         }
2524
2525         if (wait_bytes > ringbuf->space) {
2526                 int ret = wait_for_space(req, wait_bytes);
2527                 if (unlikely(ret))
2528                         return ret;
2529
2530                 intel_ring_update_space(ringbuf);
2531                 if (unlikely(ringbuf->space < wait_bytes))
2532                         return -EAGAIN;
2533         }
2534
2535         if (unlikely(need_wrap)) {
2536                 GEM_BUG_ON(remain_actual > ringbuf->space);
2537                 GEM_BUG_ON(ringbuf->tail + remain_actual > ringbuf->size);
2538
2539                 /* Fill the tail with MI_NOOP */
2540                 memset(ringbuf->virtual_start + ringbuf->tail,
2541                        0, remain_actual);
2542                 ringbuf->tail = 0;
2543                 ringbuf->space -= remain_actual;
2544         }
2545
2546         ringbuf->space -= bytes;
2547         GEM_BUG_ON(ringbuf->space < 0);
2548         return 0;
2549 }
2550
2551 /* Align the ring tail to a cacheline boundary */
2552 int intel_ring_cacheline_align(struct drm_i915_gem_request *req)
2553 {
2554         struct intel_engine_cs *engine = req->engine;
2555         int num_dwords = (engine->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
2556         int ret;
2557
2558         if (num_dwords == 0)
2559                 return 0;
2560
2561         num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
2562         ret = intel_ring_begin(req, num_dwords);
2563         if (ret)
2564                 return ret;
2565
2566         while (num_dwords--)
2567                 intel_ring_emit(engine, MI_NOOP);
2568
2569         intel_ring_advance(engine);
2570
2571         return 0;
2572 }
2573
2574 void intel_ring_init_seqno(struct intel_engine_cs *engine, u32 seqno)
2575 {
2576         struct drm_i915_private *dev_priv = to_i915(engine->dev);
2577
2578         /* Our semaphore implementation is strictly monotonic (i.e. we proceed
2579          * so long as the semaphore value in the register/page is greater
2580          * than the sync value), so whenever we reset the seqno,
2581          * so long as we reset the tracking semaphore value to 0, it will
2582          * always be before the next request's seqno. If we don't reset
2583          * the semaphore value, then when the seqno moves backwards all
2584          * future waits will complete instantly (causing rendering corruption).
2585          */
2586         if (INTEL_INFO(dev_priv)->gen == 6 || INTEL_INFO(dev_priv)->gen == 7) {
2587                 I915_WRITE(RING_SYNC_0(engine->mmio_base), 0);
2588                 I915_WRITE(RING_SYNC_1(engine->mmio_base), 0);
2589                 if (HAS_VEBOX(dev_priv))
2590                         I915_WRITE(RING_SYNC_2(engine->mmio_base), 0);
2591         }
2592         if (dev_priv->semaphore_obj) {
2593                 struct drm_i915_gem_object *obj = dev_priv->semaphore_obj;
2594                 struct page *page = i915_gem_object_get_dirty_page(obj, 0);
2595                 void *semaphores = kmap(page);
2596                 memset(semaphores + GEN8_SEMAPHORE_OFFSET(engine->id, 0),
2597                        0, I915_NUM_ENGINES * gen8_semaphore_seqno_size);
2598                 kunmap(page);
2599         }
2600         memset(engine->semaphore.sync_seqno, 0,
2601                sizeof(engine->semaphore.sync_seqno));
2602
2603         engine->set_seqno(engine, seqno);
2604         engine->last_submitted_seqno = seqno;
2605
2606         engine->hangcheck.seqno = seqno;
2607 }
2608
2609 static void gen6_bsd_ring_write_tail(struct intel_engine_cs *engine,
2610                                      u32 value)
2611 {
2612         struct drm_i915_private *dev_priv = engine->dev->dev_private;
2613
2614        /* Every tail move must follow the sequence below */
2615
2616         /* Disable notification that the ring is IDLE. The GT
2617          * will then assume that it is busy and bring it out of rc6.
2618          */
2619         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2620                    _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2621
2622         /* Clear the context id. Here be magic! */
2623         I915_WRITE64(GEN6_BSD_RNCID, 0x0);
2624
2625         /* Wait for the ring not to be idle, i.e. for it to wake up. */
2626         if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
2627                       GEN6_BSD_SLEEP_INDICATOR) == 0,
2628                      50))
2629                 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
2630
2631         /* Now that the ring is fully powered up, update the tail */
2632         I915_WRITE_TAIL(engine, value);
2633         POSTING_READ(RING_TAIL(engine->mmio_base));
2634
2635         /* Let the ring send IDLE messages to the GT again,
2636          * and so let it sleep to conserve power when idle.
2637          */
2638         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2639                    _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2640 }
2641
2642 static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req,
2643                                u32 invalidate, u32 flush)
2644 {
2645         struct intel_engine_cs *engine = req->engine;
2646         uint32_t cmd;
2647         int ret;
2648
2649         ret = intel_ring_begin(req, 4);
2650         if (ret)
2651                 return ret;
2652
2653         cmd = MI_FLUSH_DW;
2654         if (INTEL_INFO(engine->dev)->gen >= 8)
2655                 cmd += 1;
2656
2657         /* We always require a command barrier so that subsequent
2658          * commands, such as breadcrumb interrupts, are strictly ordered
2659          * wrt the contents of the write cache being flushed to memory
2660          * (and thus being coherent from the CPU).
2661          */
2662         cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2663
2664         /*
2665          * Bspec vol 1c.5 - video engine command streamer:
2666          * "If ENABLED, all TLBs will be invalidated once the flush
2667          * operation is complete. This bit is only valid when the
2668          * Post-Sync Operation field is a value of 1h or 3h."
2669          */
2670         if (invalidate & I915_GEM_GPU_DOMAINS)
2671                 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
2672
2673         intel_ring_emit(engine, cmd);
2674         intel_ring_emit(engine,
2675                         I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2676         if (INTEL_INFO(engine->dev)->gen >= 8) {
2677                 intel_ring_emit(engine, 0); /* upper addr */
2678                 intel_ring_emit(engine, 0); /* value */
2679         } else  {
2680                 intel_ring_emit(engine, 0);
2681                 intel_ring_emit(engine, MI_NOOP);
2682         }
2683         intel_ring_advance(engine);
2684         return 0;
2685 }
2686
2687 static int
2688 gen8_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
2689                               u64 offset, u32 len,
2690                               unsigned dispatch_flags)
2691 {
2692         struct intel_engine_cs *engine = req->engine;
2693         bool ppgtt = USES_PPGTT(engine->dev) &&
2694                         !(dispatch_flags & I915_DISPATCH_SECURE);
2695         int ret;
2696
2697         ret = intel_ring_begin(req, 4);
2698         if (ret)
2699                 return ret;
2700
2701         /* FIXME(BDW): Address space and security selectors. */
2702         intel_ring_emit(engine, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8) |
2703                         (dispatch_flags & I915_DISPATCH_RS ?
2704                          MI_BATCH_RESOURCE_STREAMER : 0));
2705         intel_ring_emit(engine, lower_32_bits(offset));
2706         intel_ring_emit(engine, upper_32_bits(offset));
2707         intel_ring_emit(engine, MI_NOOP);
2708         intel_ring_advance(engine);
2709
2710         return 0;
2711 }
2712
2713 static int
2714 hsw_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
2715                              u64 offset, u32 len,
2716                              unsigned dispatch_flags)
2717 {
2718         struct intel_engine_cs *engine = req->engine;
2719         int ret;
2720
2721         ret = intel_ring_begin(req, 2);
2722         if (ret)
2723                 return ret;
2724
2725         intel_ring_emit(engine,
2726                         MI_BATCH_BUFFER_START |
2727                         (dispatch_flags & I915_DISPATCH_SECURE ?
2728                          0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW) |
2729                         (dispatch_flags & I915_DISPATCH_RS ?
2730                          MI_BATCH_RESOURCE_STREAMER : 0));
2731         /* bit0-7 is the length on GEN6+ */
2732         intel_ring_emit(engine, offset);
2733         intel_ring_advance(engine);
2734
2735         return 0;
2736 }
2737
2738 static int
2739 gen6_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
2740                               u64 offset, u32 len,
2741                               unsigned dispatch_flags)
2742 {
2743         struct intel_engine_cs *engine = req->engine;
2744         int ret;
2745
2746         ret = intel_ring_begin(req, 2);
2747         if (ret)
2748                 return ret;
2749
2750         intel_ring_emit(engine,
2751                         MI_BATCH_BUFFER_START |
2752                         (dispatch_flags & I915_DISPATCH_SECURE ?
2753                          0 : MI_BATCH_NON_SECURE_I965));
2754         /* bit0-7 is the length on GEN6+ */
2755         intel_ring_emit(engine, offset);
2756         intel_ring_advance(engine);
2757
2758         return 0;
2759 }
2760
2761 /* Blitter support (SandyBridge+) */
2762
2763 static int gen6_ring_flush(struct drm_i915_gem_request *req,
2764                            u32 invalidate, u32 flush)
2765 {
2766         struct intel_engine_cs *engine = req->engine;
2767         struct drm_device *dev = engine->dev;
2768         uint32_t cmd;
2769         int ret;
2770
2771         ret = intel_ring_begin(req, 4);
2772         if (ret)
2773                 return ret;
2774
2775         cmd = MI_FLUSH_DW;
2776         if (INTEL_INFO(dev)->gen >= 8)
2777                 cmd += 1;
2778
2779         /* We always require a command barrier so that subsequent
2780          * commands, such as breadcrumb interrupts, are strictly ordered
2781          * wrt the contents of the write cache being flushed to memory
2782          * (and thus being coherent from the CPU).
2783          */
2784         cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2785
2786         /*
2787          * Bspec vol 1c.3 - blitter engine command streamer:
2788          * "If ENABLED, all TLBs will be invalidated once the flush
2789          * operation is complete. This bit is only valid when the
2790          * Post-Sync Operation field is a value of 1h or 3h."
2791          */
2792         if (invalidate & I915_GEM_DOMAIN_RENDER)
2793                 cmd |= MI_INVALIDATE_TLB;
2794         intel_ring_emit(engine, cmd);
2795         intel_ring_emit(engine,
2796                         I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2797         if (INTEL_INFO(dev)->gen >= 8) {
2798                 intel_ring_emit(engine, 0); /* upper addr */
2799                 intel_ring_emit(engine, 0); /* value */
2800         } else  {
2801                 intel_ring_emit(engine, 0);
2802                 intel_ring_emit(engine, MI_NOOP);
2803         }
2804         intel_ring_advance(engine);
2805
2806         return 0;
2807 }
2808
2809 int intel_init_render_ring_buffer(struct drm_device *dev)
2810 {
2811         struct drm_i915_private *dev_priv = dev->dev_private;
2812         struct intel_engine_cs *engine = &dev_priv->engine[RCS];
2813         struct drm_i915_gem_object *obj;
2814         int ret;
2815
2816         engine->name = "render ring";
2817         engine->id = RCS;
2818         engine->exec_id = I915_EXEC_RENDER;
2819         engine->hw_id = 0;
2820         engine->mmio_base = RENDER_RING_BASE;
2821
2822         if (INTEL_INFO(dev)->gen >= 8) {
2823                 if (i915_semaphore_is_enabled(dev)) {
2824                         obj = i915_gem_alloc_object(dev, 4096);
2825                         if (obj == NULL) {
2826                                 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2827                                 i915.semaphores = 0;
2828                         } else {
2829                                 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2830                                 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK);
2831                                 if (ret != 0) {
2832                                         drm_gem_object_unreference(&obj->base);
2833                                         DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2834                                         i915.semaphores = 0;
2835                                 } else
2836                                         dev_priv->semaphore_obj = obj;
2837                         }
2838                 }
2839
2840                 engine->init_context = intel_rcs_ctx_init;
2841                 engine->add_request = gen6_add_request;
2842                 engine->flush = gen8_render_ring_flush;
2843                 engine->irq_get = gen8_ring_get_irq;
2844                 engine->irq_put = gen8_ring_put_irq;
2845                 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2846                 engine->irq_seqno_barrier = gen6_seqno_barrier;
2847                 engine->get_seqno = ring_get_seqno;
2848                 engine->set_seqno = ring_set_seqno;
2849                 if (i915_semaphore_is_enabled(dev)) {
2850                         WARN_ON(!dev_priv->semaphore_obj);
2851                         engine->semaphore.sync_to = gen8_ring_sync;
2852                         engine->semaphore.signal = gen8_rcs_signal;
2853                         GEN8_RING_SEMAPHORE_INIT(engine);
2854                 }
2855         } else if (INTEL_INFO(dev)->gen >= 6) {
2856                 engine->init_context = intel_rcs_ctx_init;
2857                 engine->add_request = gen6_add_request;
2858                 engine->flush = gen7_render_ring_flush;
2859                 if (INTEL_INFO(dev)->gen == 6)
2860                         engine->flush = gen6_render_ring_flush;
2861                 engine->irq_get = gen6_ring_get_irq;
2862                 engine->irq_put = gen6_ring_put_irq;
2863                 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2864                 engine->irq_seqno_barrier = gen6_seqno_barrier;
2865                 engine->get_seqno = ring_get_seqno;
2866                 engine->set_seqno = ring_set_seqno;
2867                 if (i915_semaphore_is_enabled(dev)) {
2868                         engine->semaphore.sync_to = gen6_ring_sync;
2869                         engine->semaphore.signal = gen6_signal;
2870                         /*
2871                          * The current semaphore is only applied on pre-gen8
2872                          * platform.  And there is no VCS2 ring on the pre-gen8
2873                          * platform. So the semaphore between RCS and VCS2 is
2874                          * initialized as INVALID.  Gen8 will initialize the
2875                          * sema between VCS2 and RCS later.
2876                          */
2877                         engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID;
2878                         engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV;
2879                         engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB;
2880                         engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE;
2881                         engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2882                         engine->semaphore.mbox.signal[RCS] = GEN6_NOSYNC;
2883                         engine->semaphore.mbox.signal[VCS] = GEN6_VRSYNC;
2884                         engine->semaphore.mbox.signal[BCS] = GEN6_BRSYNC;
2885                         engine->semaphore.mbox.signal[VECS] = GEN6_VERSYNC;
2886                         engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2887                 }
2888         } else if (IS_GEN5(dev)) {
2889                 engine->add_request = pc_render_add_request;
2890                 engine->flush = gen4_render_ring_flush;
2891                 engine->get_seqno = pc_render_get_seqno;
2892                 engine->set_seqno = pc_render_set_seqno;
2893                 engine->irq_get = gen5_ring_get_irq;
2894                 engine->irq_put = gen5_ring_put_irq;
2895                 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
2896                                         GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
2897         } else {
2898                 engine->add_request = i9xx_add_request;
2899                 if (INTEL_INFO(dev)->gen < 4)
2900                         engine->flush = gen2_render_ring_flush;
2901                 else
2902                         engine->flush = gen4_render_ring_flush;
2903                 engine->get_seqno = ring_get_seqno;
2904                 engine->set_seqno = ring_set_seqno;
2905                 if (IS_GEN2(dev)) {
2906                         engine->irq_get = i8xx_ring_get_irq;
2907                         engine->irq_put = i8xx_ring_put_irq;
2908                 } else {
2909                         engine->irq_get = i9xx_ring_get_irq;
2910                         engine->irq_put = i9xx_ring_put_irq;
2911                 }
2912                 engine->irq_enable_mask = I915_USER_INTERRUPT;
2913         }
2914         engine->write_tail = ring_write_tail;
2915
2916         if (IS_HASWELL(dev))
2917                 engine->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
2918         else if (IS_GEN8(dev))
2919                 engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2920         else if (INTEL_INFO(dev)->gen >= 6)
2921                 engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2922         else if (INTEL_INFO(dev)->gen >= 4)
2923                 engine->dispatch_execbuffer = i965_dispatch_execbuffer;
2924         else if (IS_I830(dev) || IS_845G(dev))
2925                 engine->dispatch_execbuffer = i830_dispatch_execbuffer;
2926         else
2927                 engine->dispatch_execbuffer = i915_dispatch_execbuffer;
2928         engine->init_hw = init_render_ring;
2929         engine->cleanup = render_ring_cleanup;
2930
2931         /* Workaround batchbuffer to combat CS tlb bug. */
2932         if (HAS_BROKEN_CS_TLB(dev)) {
2933                 obj = i915_gem_alloc_object(dev, I830_WA_SIZE);
2934                 if (obj == NULL) {
2935                         DRM_ERROR("Failed to allocate batch bo\n");
2936                         return -ENOMEM;
2937                 }
2938
2939                 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
2940                 if (ret != 0) {
2941                         drm_gem_object_unreference(&obj->base);
2942                         DRM_ERROR("Failed to ping batch bo\n");
2943                         return ret;
2944                 }
2945
2946                 engine->scratch.obj = obj;
2947                 engine->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
2948         }
2949
2950         ret = intel_init_ring_buffer(dev, engine);
2951         if (ret)
2952                 return ret;
2953
2954         if (INTEL_INFO(dev)->gen >= 5) {
2955                 ret = intel_init_pipe_control(engine);
2956                 if (ret)
2957                         return ret;
2958         }
2959
2960         return 0;
2961 }
2962
2963 int intel_init_bsd_ring_buffer(struct drm_device *dev)
2964 {
2965         struct drm_i915_private *dev_priv = dev->dev_private;
2966         struct intel_engine_cs *engine = &dev_priv->engine[VCS];
2967
2968         engine->name = "bsd ring";
2969         engine->id = VCS;
2970         engine->exec_id = I915_EXEC_BSD;
2971         engine->hw_id = 1;
2972
2973         engine->write_tail = ring_write_tail;
2974         if (INTEL_INFO(dev)->gen >= 6) {
2975                 engine->mmio_base = GEN6_BSD_RING_BASE;
2976                 /* gen6 bsd needs a special wa for tail updates */
2977                 if (IS_GEN6(dev))
2978                         engine->write_tail = gen6_bsd_ring_write_tail;
2979                 engine->flush = gen6_bsd_ring_flush;
2980                 engine->add_request = gen6_add_request;
2981                 engine->irq_seqno_barrier = gen6_seqno_barrier;
2982                 engine->get_seqno = ring_get_seqno;
2983                 engine->set_seqno = ring_set_seqno;
2984                 if (INTEL_INFO(dev)->gen >= 8) {
2985                         engine->irq_enable_mask =
2986                                 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2987                         engine->irq_get = gen8_ring_get_irq;
2988                         engine->irq_put = gen8_ring_put_irq;
2989                         engine->dispatch_execbuffer =
2990                                 gen8_ring_dispatch_execbuffer;
2991                         if (i915_semaphore_is_enabled(dev)) {
2992                                 engine->semaphore.sync_to = gen8_ring_sync;
2993                                 engine->semaphore.signal = gen8_xcs_signal;
2994                                 GEN8_RING_SEMAPHORE_INIT(engine);
2995                         }
2996                 } else {
2997                         engine->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2998                         engine->irq_get = gen6_ring_get_irq;
2999                         engine->irq_put = gen6_ring_put_irq;
3000                         engine->dispatch_execbuffer =
3001                                 gen6_ring_dispatch_execbuffer;
3002                         if (i915_semaphore_is_enabled(dev)) {
3003                                 engine->semaphore.sync_to = gen6_ring_sync;
3004                                 engine->semaphore.signal = gen6_signal;
3005                                 engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;
3006                                 engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID;
3007                                 engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB;
3008                                 engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE;
3009                                 engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
3010                                 engine->semaphore.mbox.signal[RCS] = GEN6_RVSYNC;
3011                                 engine->semaphore.mbox.signal[VCS] = GEN6_NOSYNC;
3012                                 engine->semaphore.mbox.signal[BCS] = GEN6_BVSYNC;
3013                                 engine->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC;
3014                                 engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
3015                         }
3016                 }
3017         } else {
3018                 engine->mmio_base = BSD_RING_BASE;
3019                 engine->flush = bsd_ring_flush;
3020                 engine->add_request = i9xx_add_request;
3021                 engine->get_seqno = ring_get_seqno;
3022                 engine->set_seqno = ring_set_seqno;
3023                 if (IS_GEN5(dev)) {
3024                         engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
3025                         engine->irq_get = gen5_ring_get_irq;
3026                         engine->irq_put = gen5_ring_put_irq;
3027                 } else {
3028                         engine->irq_enable_mask = I915_BSD_USER_INTERRUPT;
3029                         engine->irq_get = i9xx_ring_get_irq;
3030                         engine->irq_put = i9xx_ring_put_irq;
3031                 }
3032                 engine->dispatch_execbuffer = i965_dispatch_execbuffer;
3033         }
3034         engine->init_hw = init_ring_common;
3035
3036         return intel_init_ring_buffer(dev, engine);
3037 }
3038
3039 /**
3040  * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3)
3041  */
3042 int intel_init_bsd2_ring_buffer(struct drm_device *dev)
3043 {
3044         struct drm_i915_private *dev_priv = dev->dev_private;
3045         struct intel_engine_cs *engine = &dev_priv->engine[VCS2];
3046
3047         engine->name = "bsd2 ring";
3048         engine->id = VCS2;
3049         engine->exec_id = I915_EXEC_BSD;
3050         engine->hw_id = 4;
3051
3052         engine->write_tail = ring_write_tail;
3053         engine->mmio_base = GEN8_BSD2_RING_BASE;
3054         engine->flush = gen6_bsd_ring_flush;
3055         engine->add_request = gen6_add_request;
3056         engine->irq_seqno_barrier = gen6_seqno_barrier;
3057         engine->get_seqno = ring_get_seqno;
3058         engine->set_seqno = ring_set_seqno;
3059         engine->irq_enable_mask =
3060                         GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
3061         engine->irq_get = gen8_ring_get_irq;
3062         engine->irq_put = gen8_ring_put_irq;
3063         engine->dispatch_execbuffer =
3064                         gen8_ring_dispatch_execbuffer;
3065         if (i915_semaphore_is_enabled(dev)) {
3066                 engine->semaphore.sync_to = gen8_ring_sync;
3067                 engine->semaphore.signal = gen8_xcs_signal;
3068                 GEN8_RING_SEMAPHORE_INIT(engine);
3069         }
3070         engine->init_hw = init_ring_common;
3071
3072         return intel_init_ring_buffer(dev, engine);
3073 }
3074
3075 int intel_init_blt_ring_buffer(struct drm_device *dev)
3076 {
3077         struct drm_i915_private *dev_priv = dev->dev_private;
3078         struct intel_engine_cs *engine = &dev_priv->engine[BCS];
3079
3080         engine->name = "blitter ring";
3081         engine->id = BCS;
3082         engine->exec_id = I915_EXEC_BLT;
3083         engine->hw_id = 2;
3084
3085         engine->mmio_base = BLT_RING_BASE;
3086         engine->write_tail = ring_write_tail;
3087         engine->flush = gen6_ring_flush;
3088         engine->add_request = gen6_add_request;
3089         engine->irq_seqno_barrier = gen6_seqno_barrier;
3090         engine->get_seqno = ring_get_seqno;
3091         engine->set_seqno = ring_set_seqno;
3092         if (INTEL_INFO(dev)->gen >= 8) {
3093                 engine->irq_enable_mask =
3094                         GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
3095                 engine->irq_get = gen8_ring_get_irq;
3096                 engine->irq_put = gen8_ring_put_irq;
3097                 engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
3098                 if (i915_semaphore_is_enabled(dev)) {
3099                         engine->semaphore.sync_to = gen8_ring_sync;
3100                         engine->semaphore.signal = gen8_xcs_signal;
3101                         GEN8_RING_SEMAPHORE_INIT(engine);
3102                 }
3103         } else {
3104                 engine->irq_enable_mask = GT_BLT_USER_INTERRUPT;
3105                 engine->irq_get = gen6_ring_get_irq;
3106                 engine->irq_put = gen6_ring_put_irq;
3107                 engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
3108                 if (i915_semaphore_is_enabled(dev)) {
3109                         engine->semaphore.signal = gen6_signal;
3110                         engine->semaphore.sync_to = gen6_ring_sync;
3111                         /*
3112                          * The current semaphore is only applied on pre-gen8
3113                          * platform.  And there is no VCS2 ring on the pre-gen8
3114                          * platform. So the semaphore between BCS and VCS2 is
3115                          * initialized as INVALID.  Gen8 will initialize the
3116                          * sema between BCS and VCS2 later.
3117                          */
3118                         engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR;
3119                         engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV;
3120                         engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID;
3121                         engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE;
3122                         engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
3123                         engine->semaphore.mbox.signal[RCS] = GEN6_RBSYNC;
3124                         engine->semaphore.mbox.signal[VCS] = GEN6_VBSYNC;
3125                         engine->semaphore.mbox.signal[BCS] = GEN6_NOSYNC;
3126                         engine->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC;
3127                         engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
3128                 }
3129         }
3130         engine->init_hw = init_ring_common;
3131
3132         return intel_init_ring_buffer(dev, engine);
3133 }
3134
3135 int intel_init_vebox_ring_buffer(struct drm_device *dev)
3136 {
3137         struct drm_i915_private *dev_priv = dev->dev_private;
3138         struct intel_engine_cs *engine = &dev_priv->engine[VECS];
3139
3140         engine->name = "video enhancement ring";
3141         engine->id = VECS;
3142         engine->exec_id = I915_EXEC_VEBOX;
3143         engine->hw_id = 3;
3144
3145         engine->mmio_base = VEBOX_RING_BASE;
3146         engine->write_tail = ring_write_tail;
3147         engine->flush = gen6_ring_flush;
3148         engine->add_request = gen6_add_request;
3149         engine->irq_seqno_barrier = gen6_seqno_barrier;
3150         engine->get_seqno = ring_get_seqno;
3151         engine->set_seqno = ring_set_seqno;
3152
3153         if (INTEL_INFO(dev)->gen >= 8) {
3154                 engine->irq_enable_mask =
3155                         GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
3156                 engine->irq_get = gen8_ring_get_irq;
3157                 engine->irq_put = gen8_ring_put_irq;
3158                 engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
3159                 if (i915_semaphore_is_enabled(dev)) {
3160                         engine->semaphore.sync_to = gen8_ring_sync;
3161                         engine->semaphore.signal = gen8_xcs_signal;
3162                         GEN8_RING_SEMAPHORE_INIT(engine);
3163                 }
3164         } else {
3165                 engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
3166                 engine->irq_get = hsw_vebox_get_irq;
3167                 engine->irq_put = hsw_vebox_put_irq;
3168                 engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
3169                 if (i915_semaphore_is_enabled(dev)) {
3170                         engine->semaphore.sync_to = gen6_ring_sync;
3171                         engine->semaphore.signal = gen6_signal;
3172                         engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;
3173                         engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV;
3174                         engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB;
3175                         engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID;
3176                         engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
3177                         engine->semaphore.mbox.signal[RCS] = GEN6_RVESYNC;
3178                         engine->semaphore.mbox.signal[VCS] = GEN6_VVESYNC;
3179                         engine->semaphore.mbox.signal[BCS] = GEN6_BVESYNC;
3180                         engine->semaphore.mbox.signal[VECS] = GEN6_NOSYNC;
3181                         engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
3182                 }
3183         }
3184         engine->init_hw = init_ring_common;
3185
3186         return intel_init_ring_buffer(dev, engine);
3187 }
3188
3189 int
3190 intel_ring_flush_all_caches(struct drm_i915_gem_request *req)
3191 {
3192         struct intel_engine_cs *engine = req->engine;
3193         int ret;
3194
3195         if (!engine->gpu_caches_dirty)
3196                 return 0;
3197
3198         ret = engine->flush(req, 0, I915_GEM_GPU_DOMAINS);
3199         if (ret)
3200                 return ret;
3201
3202         trace_i915_gem_ring_flush(req, 0, I915_GEM_GPU_DOMAINS);
3203
3204         engine->gpu_caches_dirty = false;
3205         return 0;
3206 }
3207
3208 int
3209 intel_ring_invalidate_all_caches(struct drm_i915_gem_request *req)
3210 {
3211         struct intel_engine_cs *engine = req->engine;
3212         uint32_t flush_domains;
3213         int ret;
3214
3215         flush_domains = 0;
3216         if (engine->gpu_caches_dirty)
3217                 flush_domains = I915_GEM_GPU_DOMAINS;
3218
3219         ret = engine->flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
3220         if (ret)
3221                 return ret;
3222
3223         trace_i915_gem_ring_flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
3224
3225         engine->gpu_caches_dirty = false;
3226         return 0;
3227 }
3228
3229 void
3230 intel_stop_engine(struct intel_engine_cs *engine)
3231 {
3232         int ret;
3233
3234         if (!intel_engine_initialized(engine))
3235                 return;
3236
3237         ret = intel_engine_idle(engine);
3238         if (ret)
3239                 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
3240                           engine->name, ret);
3241
3242         stop_ring(engine);
3243 }