drivers/gpu/drm/i915/intel_ringbuffer.c

   1 /*
   2  * Copyright © 2008-2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Zou Nan hai <nanhai.zou@intel.com>
  26  *    Xiang Hai hao<haihao.xiang@intel.com>
  27  *
  28  */
  29
  30 #include <linux/log2.h>
  31 #include <drm/drmP.h>
  32 #include "i915_drv.h"
  33 #include <drm/i915_drm.h>
  34 #include "i915_trace.h"
  35 #include "intel_drv.h"
  36
  37 int __intel_ring_space(int head, int tail, int size)
  38 {
  39         int space = head - tail;
  40         if (space <= 0)
  41                 space += size;
  42         return space - I915_RING_FREE_SPACE;
  43 }
  44
  45 void intel_ring_update_space(struct intel_ringbuffer *ringbuf)
  46 {
  47         if (ringbuf->last_retired_head != -1) {
  48                 ringbuf->head = ringbuf->last_retired_head;
  49                 ringbuf->last_retired_head = -1;
  50         }
  51
  52         ringbuf->space = __intel_ring_space(ringbuf->head & HEAD_ADDR,
  53                                             ringbuf->tail, ringbuf->size);
  54 }
  55
  56 bool intel_engine_stopped(struct intel_engine_cs *engine)
  57 {
  58         struct drm_i915_private *dev_priv = engine->dev->dev_private;
  59         return dev_priv->gpu_error.stop_rings & intel_engine_flag(engine);
  60 }
  61
  62 static void __intel_ring_advance(struct intel_engine_cs *engine)
  63 {
  64         struct intel_ringbuffer *ringbuf = engine->buffer;
  65         ringbuf->tail &= ringbuf->size - 1;
  66         if (intel_engine_stopped(engine))
  67                 return;
  68         engine->write_tail(engine, ringbuf->tail);
  69 }
  70
  71 static int
  72 gen2_render_ring_flush(struct drm_i915_gem_request *req,
  73                        u32      invalidate_domains,
  74                        u32      flush_domains)
  75 {
  76         struct intel_engine_cs *engine = req->engine;
  77         u32 cmd;
  78         int ret;
  79
  80         cmd = MI_FLUSH;
  81         if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
  82                 cmd |= MI_NO_WRITE_FLUSH;
  83
  84         if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
  85                 cmd |= MI_READ_FLUSH;
  86
  87         ret = intel_ring_begin(req, 2);
  88         if (ret)
  89                 return ret;
  90
  91         intel_ring_emit(engine, cmd);
  92         intel_ring_emit(engine, MI_NOOP);
  93         intel_ring_advance(engine);
  94
  95         return 0;
  96 }
  97
  98 static int
  99 gen4_render_ring_flush(struct drm_i915_gem_request *req,
 100                        u32      invalidate_domains,
 101                        u32      flush_domains)
 102 {
 103         struct intel_engine_cs *engine = req->engine;
 104         struct drm_device *dev = engine->dev;
 105         u32 cmd;
 106         int ret;
 107
 108         /*
 109          * read/write caches:
 110          *
 111          * I915_GEM_DOMAIN_RENDER is always invalidated, but is
 112          * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
 113          * also flushed at 2d versus 3d pipeline switches.
 114          *
 115          * read-only caches:
 116          *
 117          * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
 118          * MI_READ_FLUSH is set, and is always flushed on 965.
 119          *
 120          * I915_GEM_DOMAIN_COMMAND may not exist?
 121          *
 122          * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
 123          * invalidated when MI_EXE_FLUSH is set.
 124          *
 125          * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
 126          * invalidated with every MI_FLUSH.
 127          *
 128          * TLBs:
 129          *
 130          * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
 131          * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
 132          * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
 133          * are flushed at any MI_FLUSH.
 134          */
 135
 136         cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
 137         if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
 138                 cmd &= ~MI_NO_WRITE_FLUSH;
 139         if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
 140                 cmd |= MI_EXE_FLUSH;
 141
 142         if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
 143             (IS_G4X(dev) || IS_GEN5(dev)))
 144                 cmd |= MI_INVALIDATE_ISP;
 145
 146         ret = intel_ring_begin(req, 2);
 147         if (ret)
 148                 return ret;
 149
 150         intel_ring_emit(engine, cmd);
 151         intel_ring_emit(engine, MI_NOOP);
 152         intel_ring_advance(engine);
 153
 154         return 0;
 155 }
 156
 157 /**
 158  * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
 159  * implementing two workarounds on gen6.  From section 1.4.7.1
 160  * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
 161  *
 162  * [DevSNB-C+{W/A}] Before any depth stall flush (including those
 163  * produced by non-pipelined state commands), software needs to first
 164  * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
 165  * 0.
 166  *
 167  * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
 168  * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
 169  *
 170  * And the workaround for these two requires this workaround first:
 171  *
 172  * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
 173  * BEFORE the pipe-control with a post-sync op and no write-cache
 174  * flushes.
 175  *
 176  * And this last workaround is tricky because of the requirements on
 177  * that bit.  From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
 178  * volume 2 part 1:
 179  *
 180  *     "1 of the following must also be set:
 181  *      - Render Target Cache Flush Enable ([12] of DW1)
 182  *      - Depth Cache Flush Enable ([0] of DW1)
 183  *      - Stall at Pixel Scoreboard ([1] of DW1)
 184  *      - Depth Stall ([13] of DW1)
 185  *      - Post-Sync Operation ([13] of DW1)
 186  *      - Notify Enable ([8] of DW1)"
 187  *
 188  * The cache flushes require the workaround flush that triggered this
 189  * one, so we can't use it.  Depth stall would trigger the same.
 190  * Post-sync nonzero is what triggered this second workaround, so we
 191  * can't use that one either.  Notify enable is IRQs, which aren't
 192  * really our business.  That leaves only stall at scoreboard.
 193  */
 194 static int
 195 intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request *req)
 196 {
 197         struct intel_engine_cs *engine = req->engine;
 198         u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 199         int ret;
 200
 201         ret = intel_ring_begin(req, 6);
 202         if (ret)
 203                 return ret;
 204
 205         intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(5));
 206         intel_ring_emit(engine, PIPE_CONTROL_CS_STALL |
 207                         PIPE_CONTROL_STALL_AT_SCOREBOARD);
 208         intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 209         intel_ring_emit(engine, 0); /* low dword */
 210         intel_ring_emit(engine, 0); /* high dword */
 211         intel_ring_emit(engine, MI_NOOP);
 212         intel_ring_advance(engine);
 213
 214         ret = intel_ring_begin(req, 6);
 215         if (ret)
 216                 return ret;
 217
 218         intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(5));
 219         intel_ring_emit(engine, PIPE_CONTROL_QW_WRITE);
 220         intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 221         intel_ring_emit(engine, 0);
 222         intel_ring_emit(engine, 0);
 223         intel_ring_emit(engine, MI_NOOP);
 224         intel_ring_advance(engine);
 225
 226         return 0;
 227 }
 228
 229 static int
 230 gen6_render_ring_flush(struct drm_i915_gem_request *req,
 231                        u32 invalidate_domains, u32 flush_domains)
 232 {
 233         struct intel_engine_cs *engine = req->engine;
 234         u32 flags = 0;
 235         u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 236         int ret;
 237
 238         /* Force SNB workarounds for PIPE_CONTROL flushes */
 239         ret = intel_emit_post_sync_nonzero_flush(req);
 240         if (ret)
 241                 return ret;
 242
 243         /* Just flush everything.  Experiments have shown that reducing the
 244          * number of bits based on the write domains has little performance
 245          * impact.
 246          */
 247         if (flush_domains) {
 248                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 249                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 250                 /*
 251                  * Ensure that any following seqno writes only happen
 252                  * when the render cache is indeed flushed.
 253                  */
 254                 flags |= PIPE_CONTROL_CS_STALL;
 255         }
 256         if (invalidate_domains) {
 257                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 258                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 259                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 260                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 261                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 262                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 263                 /*
 264                  * TLB invalidate requires a post-sync write.
 265                  */
 266                 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
 267         }
 268
 269         ret = intel_ring_begin(req, 4);
 270         if (ret)
 271                 return ret;
 272
 273         intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4));
 274         intel_ring_emit(engine, flags);
 275         intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
 276         intel_ring_emit(engine, 0);
 277         intel_ring_advance(engine);
 278
 279         return 0;
 280 }
 281
 282 static int
 283 gen7_render_ring_cs_stall_wa(struct drm_i915_gem_request *req)
 284 {
 285         struct intel_engine_cs *engine = req->engine;
 286         int ret;
 287
 288         ret = intel_ring_begin(req, 4);
 289         if (ret)
 290                 return ret;
 291
 292         intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4));
 293         intel_ring_emit(engine, PIPE_CONTROL_CS_STALL |
 294                               PIPE_CONTROL_STALL_AT_SCOREBOARD);
 295         intel_ring_emit(engine, 0);
 296         intel_ring_emit(engine, 0);
 297         intel_ring_advance(engine);
 298
 299         return 0;
 300 }
 301
 302 static int
 303 gen7_render_ring_flush(struct drm_i915_gem_request *req,
 304                        u32 invalidate_domains, u32 flush_domains)
 305 {
 306         struct intel_engine_cs *engine = req->engine;
 307         u32 flags = 0;
 308         u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 309         int ret;
 310
 311         /*
 312          * Ensure that any following seqno writes only happen when the render
 313          * cache is indeed flushed.
 314          *
 315          * Workaround: 4th PIPE_CONTROL command (except the ones with only
 316          * read-cache invalidate bits set) must have the CS_STALL bit set. We
 317          * don't try to be clever and just set it unconditionally.
 318          */
 319         flags |= PIPE_CONTROL_CS_STALL;
 320
 321         /* Just flush everything.  Experiments have shown that reducing the
 322          * number of bits based on the write domains has little performance
 323          * impact.
 324          */
 325         if (flush_domains) {
 326                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 327                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 328                 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
 329                 flags |= PIPE_CONTROL_FLUSH_ENABLE;
 330         }
 331         if (invalidate_domains) {
 332                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 333                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 334                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 335                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 336                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 337                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 338                 flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
 339                 /*
 340                  * TLB invalidate requires a post-sync write.
 341                  */
 342                 flags |= PIPE_CONTROL_QW_WRITE;
 343                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 344
 345                 flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
 346
 347                 /* Workaround: we must issue a pipe_control with CS-stall bit
 348                  * set before a pipe_control command that has the state cache
 349                  * invalidate bit set. */
 350                 gen7_render_ring_cs_stall_wa(req);
 351         }
 352
 353         ret = intel_ring_begin(req, 4);
 354         if (ret)
 355                 return ret;
 356
 357         intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4));
 358         intel_ring_emit(engine, flags);
 359         intel_ring_emit(engine, scratch_addr);
 360         intel_ring_emit(engine, 0);
 361         intel_ring_advance(engine);
 362
 363         return 0;
 364 }
 365
 366 static int
 367 gen8_emit_pipe_control(struct drm_i915_gem_request *req,
 368                        u32 flags, u32 scratch_addr)
 369 {
 370         struct intel_engine_cs *engine = req->engine;
 371         int ret;
 372
 373         ret = intel_ring_begin(req, 6);
 374         if (ret)
 375                 return ret;
 376
 377         intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(6));
 378         intel_ring_emit(engine, flags);
 379         intel_ring_emit(engine, scratch_addr);
 380         intel_ring_emit(engine, 0);
 381         intel_ring_emit(engine, 0);
 382         intel_ring_emit(engine, 0);
 383         intel_ring_advance(engine);
 384
 385         return 0;
 386 }
 387
 388 static int
 389 gen8_render_ring_flush(struct drm_i915_gem_request *req,
 390                        u32 invalidate_domains, u32 flush_domains)
 391 {
 392         u32 flags = 0;
 393         u32 scratch_addr = req->engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 394         int ret;
 395
 396         flags |= PIPE_CONTROL_CS_STALL;
 397
 398         if (flush_domains) {
 399                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 400                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 401                 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
 402                 flags |= PIPE_CONTROL_FLUSH_ENABLE;
 403         }
 404         if (invalidate_domains) {
 405                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 406                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 407                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 408                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 409                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 410                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 411                 flags |= PIPE_CONTROL_QW_WRITE;
 412                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 413
 414                 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
 415                 ret = gen8_emit_pipe_control(req,
 416                                              PIPE_CONTROL_CS_STALL |
 417                                              PIPE_CONTROL_STALL_AT_SCOREBOARD,
 418                                              0);
 419                 if (ret)
 420                         return ret;
 421         }
 422
 423         return gen8_emit_pipe_control(req, flags, scratch_addr);
 424 }
 425
 426 static void ring_write_tail(struct intel_engine_cs *engine,
 427                             u32 value)
 428 {
 429         struct drm_i915_private *dev_priv = engine->dev->dev_private;
 430         I915_WRITE_TAIL(engine, value);
 431 }
 432
 433 u64 intel_ring_get_active_head(struct intel_engine_cs *engine)
 434 {
 435         struct drm_i915_private *dev_priv = engine->dev->dev_private;
 436         u64 acthd;
 437
 438         if (INTEL_INFO(engine->dev)->gen >= 8)
 439                 acthd = I915_READ64_2x32(RING_ACTHD(engine->mmio_base),
 440                                          RING_ACTHD_UDW(engine->mmio_base));
 441         else if (INTEL_INFO(engine->dev)->gen >= 4)
 442                 acthd = I915_READ(RING_ACTHD(engine->mmio_base));
 443         else
 444                 acthd = I915_READ(ACTHD);
 445
 446         return acthd;
 447 }
 448
 449 static void ring_setup_phys_status_page(struct intel_engine_cs *engine)
 450 {
 451         struct drm_i915_private *dev_priv = engine->dev->dev_private;
 452         u32 addr;
 453
 454         addr = dev_priv->status_page_dmah->busaddr;
 455         if (INTEL_INFO(engine->dev)->gen >= 4)
 456                 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
 457         I915_WRITE(HWS_PGA, addr);
 458 }
 459
 460 static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
 461 {
 462         struct drm_device *dev = engine->dev;
 463         struct drm_i915_private *dev_priv = engine->dev->dev_private;
 464         i915_reg_t mmio;
 465
 466         /* The ring status page addresses are no longer next to the rest of
 467          * the ring registers as of gen7.
 468          */
 469         if (IS_GEN7(dev)) {
 470                 switch (engine->id) {
 471                 case RCS:
 472                         mmio = RENDER_HWS_PGA_GEN7;
 473                         break;
 474                 case BCS:
 475                         mmio = BLT_HWS_PGA_GEN7;
 476                         break;
 477                 /*
 478                  * VCS2 actually doesn't exist on Gen7. Only shut up
 479                  * gcc switch check warning
 480                  */
 481                 case VCS2:
 482                 case VCS:
 483                         mmio = BSD_HWS_PGA_GEN7;
 484                         break;
 485                 case VECS:
 486                         mmio = VEBOX_HWS_PGA_GEN7;
 487                         break;
 488                 }
 489         } else if (IS_GEN6(engine->dev)) {
 490                 mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
 491         } else {
 492                 /* XXX: gen8 returns to sanity */
 493                 mmio = RING_HWS_PGA(engine->mmio_base);
 494         }
 495
 496         I915_WRITE(mmio, (u32)engine->status_page.gfx_addr);
 497         POSTING_READ(mmio);
 498
 499         /*
 500          * Flush the TLB for this page
 501          *
 502          * FIXME: These two bits have disappeared on gen8, so a question
 503          * arises: do we still need this and if so how should we go about
 504          * invalidating the TLB?
 505          */
 506         if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
 507                 i915_reg_t reg = RING_INSTPM(engine->mmio_base);
 508
 509                 /* ring should be idle before issuing a sync flush*/
 510                 WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0);
 511
 512                 I915_WRITE(reg,
 513                            _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
 514                                               INSTPM_SYNC_FLUSH));
 515                 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
 516                              1000))
 517                         DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
 518                                   engine->name);
 519         }
 520 }
 521
 522 static bool stop_ring(struct intel_engine_cs *engine)
 523 {
 524         struct drm_i915_private *dev_priv = to_i915(engine->dev);
 525
 526         if (!IS_GEN2(engine->dev)) {
 527                 I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING));
 528                 if (wait_for((I915_READ_MODE(engine) & MODE_IDLE) != 0, 1000)) {
 529                         DRM_ERROR("%s : timed out trying to stop ring\n",
 530                                   engine->name);
 531                         /* Sometimes we observe that the idle flag is not
 532                          * set even though the ring is empty. So double
 533                          * check before giving up.
 534                          */
 535                         if (I915_READ_HEAD(engine) != I915_READ_TAIL(engine))
 536                                 return false;
 537                 }
 538         }
 539
 540         I915_WRITE_CTL(engine, 0);
 541         I915_WRITE_HEAD(engine, 0);
 542         engine->write_tail(engine, 0);
 543
 544         if (!IS_GEN2(engine->dev)) {
 545                 (void)I915_READ_CTL(engine);
 546                 I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING));
 547         }
 548
 549         return (I915_READ_HEAD(engine) & HEAD_ADDR) == 0;
 550 }
 551
 552 void intel_engine_init_hangcheck(struct intel_engine_cs *engine)
 553 {
 554         memset(&engine->hangcheck, 0, sizeof(engine->hangcheck));
 555 }
 556
 557 static int init_ring_common(struct intel_engine_cs *engine)
 558 {
 559         struct drm_device *dev = engine->dev;
 560         struct drm_i915_private *dev_priv = dev->dev_private;
 561         struct intel_ringbuffer *ringbuf = engine->buffer;
 562         struct drm_i915_gem_object *obj = ringbuf->obj;
 563         int ret = 0;
 564
 565         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
 566
 567         if (!stop_ring(engine)) {
 568                 /* G45 ring initialization often fails to reset head to zero */
 569                 DRM_DEBUG_KMS("%s head not reset to zero "
 570                               "ctl %08x head %08x tail %08x start %08x\n",
 571                               engine->name,
 572                               I915_READ_CTL(engine),
 573                               I915_READ_HEAD(engine),
 574                               I915_READ_TAIL(engine),
 575                               I915_READ_START(engine));
 576
 577                 if (!stop_ring(engine)) {
 578                         DRM_ERROR("failed to set %s head to zero "
 579                                   "ctl %08x head %08x tail %08x start %08x\n",
 580                                   engine->name,
 581                                   I915_READ_CTL(engine),
 582                                   I915_READ_HEAD(engine),
 583                                   I915_READ_TAIL(engine),
 584                                   I915_READ_START(engine));
 585                         ret = -EIO;
 586                         goto out;
 587                 }
 588         }
 589
 590         if (I915_NEED_GFX_HWS(dev))
 591                 intel_ring_setup_status_page(engine);
 592         else
 593                 ring_setup_phys_status_page(engine);
 594
 595         /* Enforce ordering by reading HEAD register back */
 596         I915_READ_HEAD(engine);
 597
 598         /* Initialize the ring. This must happen _after_ we've cleared the ring
 599          * registers with the above sequence (the readback of the HEAD registers
 600          * also enforces ordering), otherwise the hw might lose the new ring
 601          * register values. */
 602         I915_WRITE_START(engine, i915_gem_obj_ggtt_offset(obj));
 603
 604         /* WaClearRingBufHeadRegAtInit:ctg,elk */
 605         if (I915_READ_HEAD(engine))
 606                 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
 607                           engine->name, I915_READ_HEAD(engine));
 608         I915_WRITE_HEAD(engine, 0);
 609         (void)I915_READ_HEAD(engine);
 610
 611         I915_WRITE_CTL(engine,
 612                         ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES)
 613                         | RING_VALID);
 614
 615         /* If the head is still not zero, the ring is dead */
 616         if (wait_for((I915_READ_CTL(engine) & RING_VALID) != 0 &&
 617                      I915_READ_START(engine) == i915_gem_obj_ggtt_offset(obj) &&
 618                      (I915_READ_HEAD(engine) & HEAD_ADDR) == 0, 50)) {
 619                 DRM_ERROR("%s initialization failed "
 620                           "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
 621                           engine->name,
 622                           I915_READ_CTL(engine),
 623                           I915_READ_CTL(engine) & RING_VALID,
 624                           I915_READ_HEAD(engine), I915_READ_TAIL(engine),
 625                           I915_READ_START(engine),
 626                           (unsigned long)i915_gem_obj_ggtt_offset(obj));
 627                 ret = -EIO;
 628                 goto out;
 629         }
 630
 631         ringbuf->last_retired_head = -1;
 632         ringbuf->head = I915_READ_HEAD(engine);
 633         ringbuf->tail = I915_READ_TAIL(engine) & TAIL_ADDR;
 634         intel_ring_update_space(ringbuf);
 635
 636         intel_engine_init_hangcheck(engine);
 637
 638 out:
 639         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
 640
 641         return ret;
 642 }
 643
 644 void
 645 intel_fini_pipe_control(struct intel_engine_cs *engine)
 646 {
 647         struct drm_device *dev = engine->dev;
 648
 649         if (engine->scratch.obj == NULL)
 650                 return;
 651
 652         if (INTEL_INFO(dev)->gen >= 5) {
 653                 kunmap(sg_page(engine->scratch.obj->pages->sgl));
 654                 i915_gem_object_ggtt_unpin(engine->scratch.obj);
 655         }
 656
 657         drm_gem_object_unreference(&engine->scratch.obj->base);
 658         engine->scratch.obj = NULL;
 659 }
 660
 661 int
 662 intel_init_pipe_control(struct intel_engine_cs *engine)
 663 {
 664         int ret;
 665
 666         WARN_ON(engine->scratch.obj);
 667
 668         engine->scratch.obj = i915_gem_alloc_object(engine->dev, 4096);
 669         if (engine->scratch.obj == NULL) {
 670                 DRM_ERROR("Failed to allocate seqno page\n");
 671                 ret = -ENOMEM;
 672                 goto err;
 673         }
 674
 675         ret = i915_gem_object_set_cache_level(engine->scratch.obj,
 676                                               I915_CACHE_LLC);
 677         if (ret)
 678                 goto err_unref;
 679
 680         ret = i915_gem_obj_ggtt_pin(engine->scratch.obj, 4096, 0);
 681         if (ret)
 682                 goto err_unref;
 683
 684         engine->scratch.gtt_offset = i915_gem_obj_ggtt_offset(engine->scratch.obj);
 685         engine->scratch.cpu_page = kmap(sg_page(engine->scratch.obj->pages->sgl));
 686         if (engine->scratch.cpu_page == NULL) {
 687                 ret = -ENOMEM;
 688                 goto err_unpin;
 689         }
 690
 691         DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
 692                          engine->name, engine->scratch.gtt_offset);
 693         return 0;
 694
 695 err_unpin:
 696         i915_gem_object_ggtt_unpin(engine->scratch.obj);
 697 err_unref:
 698         drm_gem_object_unreference(&engine->scratch.obj->base);
 699 err:
 700         return ret;
 701 }
 702
 703 static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req)
 704 {
 705         int ret, i;
 706         struct intel_engine_cs *engine = req->engine;
 707         struct drm_device *dev = engine->dev;
 708         struct drm_i915_private *dev_priv = dev->dev_private;
 709         struct i915_workarounds *w = &dev_priv->workarounds;
 710
 711         if (w->count == 0)
 712                 return 0;
 713
 714         engine->gpu_caches_dirty = true;
 715         ret = intel_ring_flush_all_caches(req);
 716         if (ret)
 717                 return ret;
 718
 719         ret = intel_ring_begin(req, (w->count * 2 + 2));
 720         if (ret)
 721                 return ret;
 722
 723         intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(w->count));
 724         for (i = 0; i < w->count; i++) {
 725                 intel_ring_emit_reg(engine, w->reg[i].addr);
 726                 intel_ring_emit(engine, w->reg[i].value);
 727         }
 728         intel_ring_emit(engine, MI_NOOP);
 729
 730         intel_ring_advance(engine);
 731
 732         engine->gpu_caches_dirty = true;
 733         ret = intel_ring_flush_all_caches(req);
 734         if (ret)
 735                 return ret;
 736
 737         DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count);
 738
 739         return 0;
 740 }
 741
 742 static int intel_rcs_ctx_init(struct drm_i915_gem_request *req)
 743 {
 744         int ret;
 745
 746         ret = intel_ring_workarounds_emit(req);
 747         if (ret != 0)
 748                 return ret;
 749
 750         ret = i915_gem_render_state_init(req);
 751         if (ret)
 752                 return ret;
 753
 754         return 0;
 755 }
 756
 757 static int wa_add(struct drm_i915_private *dev_priv,
 758                   i915_reg_t addr,
 759                   const u32 mask, const u32 val)
 760 {
 761         const u32 idx = dev_priv->workarounds.count;
 762
 763         if (WARN_ON(idx >= I915_MAX_WA_REGS))
 764                 return -ENOSPC;
 765
 766         dev_priv->workarounds.reg[idx].addr = addr;
 767         dev_priv->workarounds.reg[idx].value = val;
 768         dev_priv->workarounds.reg[idx].mask = mask;
 769
 770         dev_priv->workarounds.count++;
 771
 772         return 0;
 773 }
 774
 775 #define WA_REG(addr, mask, val) do { \
 776                 const int r = wa_add(dev_priv, (addr), (mask), (val)); \
 777                 if (r) \
 778                         return r; \
 779         } while (0)
 780
 781 #define WA_SET_BIT_MASKED(addr, mask) \
 782         WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
 783
 784 #define WA_CLR_BIT_MASKED(addr, mask) \
 785         WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
 786
 787 #define WA_SET_FIELD_MASKED(addr, mask, value) \
 788         WA_REG(addr, mask, _MASKED_FIELD(mask, value))
 789
 790 #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
 791 #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
 792
 793 #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
 794
 795 static int wa_ring_whitelist_reg(struct intel_engine_cs *engine,
 796                                  i915_reg_t reg)
 797 {
 798         struct drm_i915_private *dev_priv = engine->dev->dev_private;
 799         struct i915_workarounds *wa = &dev_priv->workarounds;
 800         const uint32_t index = wa->hw_whitelist_count[engine->id];
 801
 802         if (WARN_ON(index >= RING_MAX_NONPRIV_SLOTS))
 803                 return -EINVAL;
 804
 805         WA_WRITE(RING_FORCE_TO_NONPRIV(engine->mmio_base, index),
 806                  i915_mmio_reg_offset(reg));
 807         wa->hw_whitelist_count[engine->id]++;
 808
 809         return 0;
 810 }
 811
 812 static int gen8_init_workarounds(struct intel_engine_cs *engine)
 813 {
 814         struct drm_device *dev = engine->dev;
 815         struct drm_i915_private *dev_priv = dev->dev_private;
 816
 817         WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
 818
 819         /* WaDisableAsyncFlipPerfMode:bdw,chv */
 820         WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
 821
 822         /* WaDisablePartialInstShootdown:bdw,chv */
 823         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 824                           PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
 825
 826         /* Use Force Non-Coherent whenever executing a 3D context. This is a
 827          * workaround for for a possible hang in the unlikely event a TLB
 828          * invalidation occurs during a PSD flush.
 829          */
 830         /* WaForceEnableNonCoherent:bdw,chv */
 831         /* WaHdcDisableFetchWhenMasked:bdw,chv */
 832         WA_SET_BIT_MASKED(HDC_CHICKEN0,
 833                           HDC_DONOT_FETCH_MEM_WHEN_MASKED |
 834                           HDC_FORCE_NON_COHERENT);
 835
 836         /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
 837          * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
 838          *  polygons in the same 8x4 pixel/sample area to be processed without
 839          *  stalling waiting for the earlier ones to write to Hierarchical Z
 840          *  buffer."
 841          *
 842          * This optimization is off by default for BDW and CHV; turn it on.
 843          */
 844         WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
 845
 846         /* Wa4x4STCOptimizationDisable:bdw,chv */
 847         WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
 848
 849         /*
 850          * BSpec recommends 8x4 when MSAA is used,
 851          * however in practice 16x4 seems fastest.
 852          *
 853          * Note that PS/WM thread counts depend on the WIZ hashing
 854          * disable bit, which we don't touch here, but it's good
 855          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
 856          */
 857         WA_SET_FIELD_MASKED(GEN7_GT_MODE,
 858                             GEN6_WIZ_HASHING_MASK,
 859                             GEN6_WIZ_HASHING_16x4);
 860
 861         return 0;
 862 }
 863
 864 static int bdw_init_workarounds(struct intel_engine_cs *engine)
 865 {
 866         int ret;
 867         struct drm_device *dev = engine->dev;
 868         struct drm_i915_private *dev_priv = dev->dev_private;
 869
 870         ret = gen8_init_workarounds(engine);
 871         if (ret)
 872                 return ret;
 873
 874         /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
 875         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
 876
 877         /* WaDisableDopClockGating:bdw */
 878         WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
 879                           DOP_CLOCK_GATING_DISABLE);
 880
 881         WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
 882                           GEN8_SAMPLER_POWER_BYPASS_DIS);
 883
 884         WA_SET_BIT_MASKED(HDC_CHICKEN0,
 885                           /* WaForceContextSaveRestoreNonCoherent:bdw */
 886                           HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
 887                           /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
 888                           (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
 889
 890         return 0;
 891 }
 892
 893 static int chv_init_workarounds(struct intel_engine_cs *engine)
 894 {
 895         int ret;
 896         struct drm_device *dev = engine->dev;
 897         struct drm_i915_private *dev_priv = dev->dev_private;
 898
 899         ret = gen8_init_workarounds(engine);
 900         if (ret)
 901                 return ret;
 902
 903         /* WaDisableThreadStallDopClockGating:chv */
 904         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
 905
 906         /* Improve HiZ throughput on CHV. */
 907         WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
 908
 909         return 0;
 910 }
 911
 912 static int gen9_init_workarounds(struct intel_engine_cs *engine)
 913 {
 914         struct drm_device *dev = engine->dev;
 915         struct drm_i915_private *dev_priv = dev->dev_private;
 916         uint32_t tmp;
 917         int ret;
 918
 919         /* WaEnableLbsSlaRetryTimerDecrement:skl */
 920         I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
 921                    GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
 922
 923         /* WaDisableKillLogic:bxt,skl */
 924         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
 925                    ECOCHK_DIS_TLB);
 926
 927         /* WaClearFlowControlGpgpuContextSave:skl,bxt */
 928         /* WaDisablePartialInstShootdown:skl,bxt */
 929         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 930                           FLOW_CONTROL_ENABLE |
 931                           PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
 932
 933         /* Syncing dependencies between camera and graphics:skl,bxt */
 934         WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
 935                           GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
 936
 937         /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */
 938         if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
 939             IS_BXT_REVID(dev, 0, BXT_REVID_A1))
 940                 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
 941                                   GEN9_DG_MIRROR_FIX_ENABLE);
 942
 943         /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
 944         if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
 945             IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
 946                 WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
 947                                   GEN9_RHWO_OPTIMIZATION_DISABLE);
 948                 /*
 949                  * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set
 950                  * but we do that in per ctx batchbuffer as there is an issue
 951                  * with this register not getting restored on ctx restore
 952                  */
 953         }
 954
 955         /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt */
 956         /* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt */
 957         WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
 958                           GEN9_ENABLE_YV12_BUGFIX |
 959                           GEN9_ENABLE_GPGPU_PREEMPTION);
 960
 961         /* Wa4x4STCOptimizationDisable:skl,bxt */
 962         /* WaDisablePartialResolveInVc:skl,bxt */
 963         WA_SET_BIT_MASKED(CACHE_MODE_1, (GEN8_4x4_STC_OPTIMIZATION_DISABLE |
 964                                          GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE));
 965
 966         /* WaCcsTlbPrefetchDisable:skl,bxt */
 967         WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
 968                           GEN9_CCS_TLB_PREFETCH_ENABLE);
 969
 970         /* WaDisableMaskBasedCammingInRCC:skl,bxt */
 971         if (IS_SKL_REVID(dev, SKL_REVID_C0, SKL_REVID_C0) ||
 972             IS_BXT_REVID(dev, 0, BXT_REVID_A1))
 973                 WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
 974                                   PIXEL_MASK_CAMMING_DISABLE);
 975
 976         /* WaForceContextSaveRestoreNonCoherent:skl,bxt */
 977         tmp = HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT;
 978         if (IS_SKL_REVID(dev, SKL_REVID_F0, REVID_FOREVER) ||
 979             IS_BXT_REVID(dev, BXT_REVID_B0, REVID_FOREVER))
 980                 tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE;
 981         WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp);
 982
 983         /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt */
 984         if (IS_SKYLAKE(dev) || IS_BXT_REVID(dev, 0, BXT_REVID_B0))
 985                 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
 986                                   GEN8_SAMPLER_POWER_BYPASS_DIS);
 987
 988         /* WaDisableSTUnitPowerOptimization:skl,bxt */
 989         WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
 990
 991         /* WaOCLCoherentLineFlush:skl,bxt */
 992         I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
 993                                     GEN8_LQSC_FLUSH_COHERENT_LINES));
 994
 995         /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt */
 996         ret = wa_ring_whitelist_reg(engine, GEN9_CTX_PREEMPT_REG);
 997         if (ret)
 998                 return ret;
 999
1000         /* WaEnablePreemptionGranularityControlByUMD:skl,bxt */
1001         ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1);
1002         if (ret)
1003                 return ret;
1004
1005         /* WaAllowUMDToModifyHDCChicken1:skl,bxt */
1006         ret = wa_ring_whitelist_reg(engine, GEN8_HDC_CHICKEN1);
1007         if (ret)
1008                 return ret;
1009
1010         return 0;
1011 }
1012
1013 static int skl_tune_iz_hashing(struct intel_engine_cs *engine)
1014 {
1015         struct drm_device *dev = engine->dev;
1016         struct drm_i915_private *dev_priv = dev->dev_private;
1017         u8 vals[3] = { 0, 0, 0 };
1018         unsigned int i;
1019
1020         for (i = 0; i < 3; i++) {
1021                 u8 ss;
1022
1023                 /*
1024                  * Only consider slices where one, and only one, subslice has 7
1025                  * EUs
1026                  */
1027                 if (!is_power_of_2(dev_priv->info.subslice_7eu[i]))
1028                         continue;
1029
1030                 /*
1031                  * subslice_7eu[i] != 0 (because of the check above) and
1032                  * ss_max == 4 (maximum number of subslices possible per slice)
1033                  *
1034                  * ->    0 <= ss <= 3;
1035                  */
1036                 ss = ffs(dev_priv->info.subslice_7eu[i]) - 1;
1037                 vals[i] = 3 - ss;
1038         }
1039
1040         if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0)
1041                 return 0;
1042
1043         /* Tune IZ hashing. See intel_device_info_runtime_init() */
1044         WA_SET_FIELD_MASKED(GEN7_GT_MODE,
1045                             GEN9_IZ_HASHING_MASK(2) |
1046                             GEN9_IZ_HASHING_MASK(1) |
1047                             GEN9_IZ_HASHING_MASK(0),
1048                             GEN9_IZ_HASHING(2, vals[2]) |
1049                             GEN9_IZ_HASHING(1, vals[1]) |
1050                             GEN9_IZ_HASHING(0, vals[0]));
1051
1052         return 0;
1053 }
1054
1055 static int skl_init_workarounds(struct intel_engine_cs *engine)
1056 {
1057         int ret;
1058         struct drm_device *dev = engine->dev;
1059         struct drm_i915_private *dev_priv = dev->dev_private;
1060
1061         ret = gen9_init_workarounds(engine);
1062         if (ret)
1063                 return ret;
1064
1065         /*
1066          * Actual WA is to disable percontext preemption granularity control
1067          * until D0 which is the default case so this is equivalent to
1068          * !WaDisablePerCtxtPreemptionGranularityControl:skl
1069          */
1070         if (IS_SKL_REVID(dev, SKL_REVID_E0, REVID_FOREVER)) {
1071                 I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1,
1072                            _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL));
1073         }
1074
1075         if (IS_SKL_REVID(dev, 0, SKL_REVID_D0)) {
1076                 /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
1077                 I915_WRITE(FF_SLICE_CS_CHICKEN2,
1078                            _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE));
1079         }
1080
1081         /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes
1082          * involving this register should also be added to WA batch as required.
1083          */
1084         if (IS_SKL_REVID(dev, 0, SKL_REVID_E0))
1085                 /* WaDisableLSQCROPERFforOCL:skl */
1086                 I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
1087                            GEN8_LQSC_RO_PERF_DIS);
1088
1089         /* WaEnableGapsTsvCreditFix:skl */
1090         if (IS_SKL_REVID(dev, SKL_REVID_C0, REVID_FOREVER)) {
1091                 I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
1092                                            GEN9_GAPS_TSV_CREDIT_DISABLE));
1093         }
1094
1095         /* WaDisablePowerCompilerClockGating:skl */
1096         if (IS_SKL_REVID(dev, SKL_REVID_B0, SKL_REVID_B0))
1097                 WA_SET_BIT_MASKED(HIZ_CHICKEN,
1098                                   BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
1099
1100         /* This is tied to WaForceContextSaveRestoreNonCoherent */
1101         if (IS_SKL_REVID(dev, 0, REVID_FOREVER)) {
1102                 /*
1103                  *Use Force Non-Coherent whenever executing a 3D context. This
1104                  * is a workaround for a possible hang in the unlikely event
1105                  * a TLB invalidation occurs during a PSD flush.
1106                  */
1107                 /* WaForceEnableNonCoherent:skl */
1108                 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1109                                   HDC_FORCE_NON_COHERENT);
1110
1111                 /* WaDisableHDCInvalidation:skl */
1112                 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
1113                            BDW_DISABLE_HDC_INVALIDATION);
1114         }
1115
1116         /* WaBarrierPerformanceFixDisable:skl */
1117         if (IS_SKL_REVID(dev, SKL_REVID_C0, SKL_REVID_D0))
1118                 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1119                                   HDC_FENCE_DEST_SLM_DISABLE |
1120                                   HDC_BARRIER_PERFORMANCE_DISABLE);
1121
1122         /* WaDisableSbeCacheDispatchPortSharing:skl */
1123         if (IS_SKL_REVID(dev, 0, SKL_REVID_F0))
1124                 WA_SET_BIT_MASKED(
1125                         GEN7_HALF_SLICE_CHICKEN1,
1126                         GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1127
1128         /* WaDisableGafsUnitClkGating:skl */
1129         WA_SET_BIT(GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
1130
1131         /* WaDisableLSQCROPERFforOCL:skl */
1132         ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
1133         if (ret)
1134                 return ret;
1135
1136         return skl_tune_iz_hashing(engine);
1137 }
1138
1139 static int bxt_init_workarounds(struct intel_engine_cs *engine)
1140 {
1141         int ret;
1142         struct drm_device *dev = engine->dev;
1143         struct drm_i915_private *dev_priv = dev->dev_private;
1144
1145         ret = gen9_init_workarounds(engine);
1146         if (ret)
1147                 return ret;
1148
1149         /* WaStoreMultiplePTEenable:bxt */
1150         /* This is a requirement according to Hardware specification */
1151         if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
1152                 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
1153
1154         /* WaSetClckGatingDisableMedia:bxt */
1155         if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
1156                 I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) &
1157                                             ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE));
1158         }
1159
1160         /* WaDisableThreadStallDopClockGating:bxt */
1161         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
1162                           STALL_DOP_GATING_DISABLE);
1163
1164         /* WaDisableSbeCacheDispatchPortSharing:bxt */
1165         if (IS_BXT_REVID(dev, 0, BXT_REVID_B0)) {
1166                 WA_SET_BIT_MASKED(
1167                         GEN7_HALF_SLICE_CHICKEN1,
1168                         GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1169         }
1170
1171         /* WaDisableObjectLevelPreemptionForTrifanOrPolygon:bxt */
1172         /* WaDisableObjectLevelPreemptionForInstancedDraw:bxt */
1173         /* WaDisableObjectLevelPreemtionForInstanceId:bxt */
1174         /* WaDisableLSQCROPERFforOCL:bxt */
1175         if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
1176                 ret = wa_ring_whitelist_reg(engine, GEN9_CS_DEBUG_MODE1);
1177                 if (ret)
1178                         return ret;
1179
1180                 ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
1181                 if (ret)
1182                         return ret;
1183         }
1184
1185         return 0;
1186 }
1187
1188 int init_workarounds_ring(struct intel_engine_cs *engine)
1189 {
1190         struct drm_device *dev = engine->dev;
1191         struct drm_i915_private *dev_priv = dev->dev_private;
1192
1193         WARN_ON(engine->id != RCS);
1194
1195         dev_priv->workarounds.count = 0;
1196         dev_priv->workarounds.hw_whitelist_count[RCS] = 0;
1197
1198         if (IS_BROADWELL(dev))
1199                 return bdw_init_workarounds(engine);
1200
1201         if (IS_CHERRYVIEW(dev))
1202                 return chv_init_workarounds(engine);
1203
1204         if (IS_SKYLAKE(dev))
1205                 return skl_init_workarounds(engine);
1206
1207         if (IS_BROXTON(dev))
1208                 return bxt_init_workarounds(engine);
1209
1210         return 0;
1211 }
1212
1213 static int init_render_ring(struct intel_engine_cs *engine)
1214 {
1215         struct drm_device *dev = engine->dev;
1216         struct drm_i915_private *dev_priv = dev->dev_private;
1217         int ret = init_ring_common(engine);
1218         if (ret)
1219                 return ret;
1220
1221         /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
1222         if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7)
1223                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
1224
1225         /* We need to disable the AsyncFlip performance optimisations in order
1226          * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1227          * programmed to '1' on all products.
1228          *
1229          * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
1230          */
1231         if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
1232                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1233
1234         /* Required for the hardware to program scanline values for waiting */
1235         /* WaEnableFlushTlbInvalidationMode:snb */
1236         if (INTEL_INFO(dev)->gen == 6)
1237                 I915_WRITE(GFX_MODE,
1238                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
1239
1240         /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
1241         if (IS_GEN7(dev))
1242                 I915_WRITE(GFX_MODE_GEN7,
1243                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
1244                            _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
1245
1246         if (IS_GEN6(dev)) {
1247                 /* From the Sandybridge PRM, volume 1 part 3, page 24:
1248                  * "If this bit is set, STCunit will have LRA as replacement
1249                  *  policy. [...] This bit must be reset.  LRA replacement
1250                  *  policy is not supported."
1251                  */
1252                 I915_WRITE(CACHE_MODE_0,
1253                            _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
1254         }
1255
1256         if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
1257                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
1258
1259         if (HAS_L3_DPF(dev))
1260                 I915_WRITE_IMR(engine, ~GT_PARITY_ERROR(dev));
1261
1262         return init_workarounds_ring(engine);
1263 }
1264
1265 static void render_ring_cleanup(struct intel_engine_cs *engine)
1266 {
1267         struct drm_device *dev = engine->dev;
1268         struct drm_i915_private *dev_priv = dev->dev_private;
1269
1270         if (dev_priv->semaphore_obj) {
1271                 i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj);
1272                 drm_gem_object_unreference(&dev_priv->semaphore_obj->base);
1273                 dev_priv->semaphore_obj = NULL;
1274         }
1275
1276         intel_fini_pipe_control(engine);
1277 }
1278
1279 static int gen8_rcs_signal(struct drm_i915_gem_request *signaller_req,
1280                            unsigned int num_dwords)
1281 {
1282 #define MBOX_UPDATE_DWORDS 8
1283         struct intel_engine_cs *signaller = signaller_req->engine;
1284         struct drm_device *dev = signaller->dev;
1285         struct drm_i915_private *dev_priv = dev->dev_private;
1286         struct intel_engine_cs *waiter;
1287         enum intel_engine_id id;
1288         int ret, num_rings;
1289
1290         num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1291         num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1292 #undef MBOX_UPDATE_DWORDS
1293
1294         ret = intel_ring_begin(signaller_req, num_dwords);
1295         if (ret)
1296                 return ret;
1297
1298         for_each_engine_id(waiter, dev_priv, id) {
1299                 u32 seqno;
1300                 u64 gtt_offset = signaller->semaphore.signal_ggtt[id];
1301                 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1302                         continue;
1303
1304                 seqno = i915_gem_request_get_seqno(signaller_req);
1305                 intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
1306                 intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |
1307                                            PIPE_CONTROL_QW_WRITE |
1308                                            PIPE_CONTROL_FLUSH_ENABLE);
1309                 intel_ring_emit(signaller, lower_32_bits(gtt_offset));
1310                 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
1311                 intel_ring_emit(signaller, seqno);
1312                 intel_ring_emit(signaller, 0);
1313                 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1314                                            MI_SEMAPHORE_TARGET(waiter->hw_id));
1315                 intel_ring_emit(signaller, 0);
1316         }
1317
1318         return 0;
1319 }
1320
1321 static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req,
1322                            unsigned int num_dwords)
1323 {
1324 #define MBOX_UPDATE_DWORDS 6
1325         struct intel_engine_cs *signaller = signaller_req->engine;
1326         struct drm_device *dev = signaller->dev;
1327         struct drm_i915_private *dev_priv = dev->dev_private;
1328         struct intel_engine_cs *waiter;
1329         enum intel_engine_id id;
1330         int ret, num_rings;
1331
1332         num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1333         num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1334 #undef MBOX_UPDATE_DWORDS
1335
1336         ret = intel_ring_begin(signaller_req, num_dwords);
1337         if (ret)
1338                 return ret;
1339
1340         for_each_engine_id(waiter, dev_priv, id) {
1341                 u32 seqno;
1342                 u64 gtt_offset = signaller->semaphore.signal_ggtt[id];
1343                 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1344                         continue;
1345
1346                 seqno = i915_gem_request_get_seqno(signaller_req);
1347                 intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |
1348                                            MI_FLUSH_DW_OP_STOREDW);
1349                 intel_ring_emit(signaller, lower_32_bits(gtt_offset) |
1350                                            MI_FLUSH_DW_USE_GTT);
1351                 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
1352                 intel_ring_emit(signaller, seqno);
1353                 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1354                                            MI_SEMAPHORE_TARGET(waiter->hw_id));
1355                 intel_ring_emit(signaller, 0);
1356         }
1357
1358         return 0;
1359 }
1360
1361 static int gen6_signal(struct drm_i915_gem_request *signaller_req,
1362                        unsigned int num_dwords)
1363 {
1364         struct intel_engine_cs *signaller = signaller_req->engine;
1365         struct drm_device *dev = signaller->dev;
1366         struct drm_i915_private *dev_priv = dev->dev_private;
1367         struct intel_engine_cs *useless;
1368         enum intel_engine_id id;
1369         int ret, num_rings;
1370
1371 #define MBOX_UPDATE_DWORDS 3
1372         num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1373         num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
1374 #undef MBOX_UPDATE_DWORDS
1375
1376         ret = intel_ring_begin(signaller_req, num_dwords);
1377         if (ret)
1378                 return ret;
1379
1380         for_each_engine_id(useless, dev_priv, id) {
1381                 i915_reg_t mbox_reg = signaller->semaphore.mbox.signal[id];
1382
1383                 if (i915_mmio_reg_valid(mbox_reg)) {
1384                         u32 seqno = i915_gem_request_get_seqno(signaller_req);
1385
1386                         intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
1387                         intel_ring_emit_reg(signaller, mbox_reg);
1388                         intel_ring_emit(signaller, seqno);
1389                 }
1390         }
1391
1392         /* If num_dwords was rounded, make sure the tail pointer is correct */
1393         if (num_rings % 2 == 0)
1394                 intel_ring_emit(signaller, MI_NOOP);
1395
1396         return 0;
1397 }
1398
1399 /**
1400  * gen6_add_request - Update the semaphore mailbox registers
1401  *
1402  * @request - request to write to the ring
1403  *
1404  * Update the mailbox registers in the *other* rings with the current seqno.
1405  * This acts like a signal in the canonical semaphore.
1406  */
1407 static int
1408 gen6_add_request(struct drm_i915_gem_request *req)
1409 {
1410         struct intel_engine_cs *engine = req->engine;
1411         int ret;
1412
1413         if (engine->semaphore.signal)
1414                 ret = engine->semaphore.signal(req, 4);
1415         else
1416                 ret = intel_ring_begin(req, 4);
1417
1418         if (ret)
1419                 return ret;
1420
1421         intel_ring_emit(engine, MI_STORE_DWORD_INDEX);
1422         intel_ring_emit(engine,
1423                         I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1424         intel_ring_emit(engine, i915_gem_request_get_seqno(req));
1425         intel_ring_emit(engine, MI_USER_INTERRUPT);
1426         __intel_ring_advance(engine);
1427
1428         return 0;
1429 }
1430
1431 static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
1432                                               u32 seqno)
1433 {
1434         struct drm_i915_private *dev_priv = dev->dev_private;
1435         return dev_priv->last_seqno < seqno;
1436 }
1437
1438 /**
1439  * intel_ring_sync - sync the waiter to the signaller on seqno
1440  *
1441  * @waiter - ring that is waiting
1442  * @signaller - ring which has, or will signal
1443  * @seqno - seqno which the waiter will block on
1444  */
1445
1446 static int
1447 gen8_ring_sync(struct drm_i915_gem_request *waiter_req,
1448                struct intel_engine_cs *signaller,
1449                u32 seqno)
1450 {
1451         struct intel_engine_cs *waiter = waiter_req->engine;
1452         struct drm_i915_private *dev_priv = waiter->dev->dev_private;
1453         int ret;
1454
1455         ret = intel_ring_begin(waiter_req, 4);
1456         if (ret)
1457                 return ret;
1458
1459         intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |
1460                                 MI_SEMAPHORE_GLOBAL_GTT |
1461                                 MI_SEMAPHORE_POLL |
1462                                 MI_SEMAPHORE_SAD_GTE_SDD);
1463         intel_ring_emit(waiter, seqno);
1464         intel_ring_emit(waiter,
1465                         lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1466         intel_ring_emit(waiter,
1467                         upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1468         intel_ring_advance(waiter);
1469         return 0;
1470 }
1471
1472 static int
1473 gen6_ring_sync(struct drm_i915_gem_request *waiter_req,
1474                struct intel_engine_cs *signaller,
1475                u32 seqno)
1476 {
1477         struct intel_engine_cs *waiter = waiter_req->engine;
1478         u32 dw1 = MI_SEMAPHORE_MBOX |
1479                   MI_SEMAPHORE_COMPARE |
1480                   MI_SEMAPHORE_REGISTER;
1481         u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id];
1482         int ret;
1483
1484         /* Throughout all of the GEM code, seqno passed implies our current
1485          * seqno is >= the last seqno executed. However for hardware the
1486          * comparison is strictly greater than.
1487          */
1488         seqno -= 1;
1489
1490         WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
1491
1492         ret = intel_ring_begin(waiter_req, 4);
1493         if (ret)
1494                 return ret;
1495
1496         /* If seqno wrap happened, omit the wait with no-ops */
1497         if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
1498                 intel_ring_emit(waiter, dw1 | wait_mbox);
1499                 intel_ring_emit(waiter, seqno);
1500                 intel_ring_emit(waiter, 0);
1501                 intel_ring_emit(waiter, MI_NOOP);
1502         } else {
1503                 intel_ring_emit(waiter, MI_NOOP);
1504                 intel_ring_emit(waiter, MI_NOOP);
1505                 intel_ring_emit(waiter, MI_NOOP);
1506                 intel_ring_emit(waiter, MI_NOOP);
1507         }
1508         intel_ring_advance(waiter);
1509
1510         return 0;
1511 }
1512
1513 #define PIPE_CONTROL_FLUSH(ring__, addr__)                                      \
1514 do {                                                                    \
1515         intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |                \
1516                  PIPE_CONTROL_DEPTH_STALL);                             \
1517         intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT);                    \
1518         intel_ring_emit(ring__, 0);                                                     \
1519         intel_ring_emit(ring__, 0);                                                     \
1520 } while (0)
1521
1522 static int
1523 pc_render_add_request(struct drm_i915_gem_request *req)
1524 {
1525         struct intel_engine_cs *engine = req->engine;
1526         u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
1527         int ret;
1528
1529         /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
1530          * incoherent with writes to memory, i.e. completely fubar,
1531          * so we need to use PIPE_NOTIFY instead.
1532          *
1533          * However, we also need to workaround the qword write
1534          * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
1535          * memory before requesting an interrupt.
1536          */
1537         ret = intel_ring_begin(req, 32);
1538         if (ret)
1539                 return ret;
1540
1541         intel_ring_emit(engine,
1542                         GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1543                         PIPE_CONTROL_WRITE_FLUSH |
1544                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
1545         intel_ring_emit(engine,
1546                         engine->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1547         intel_ring_emit(engine, i915_gem_request_get_seqno(req));
1548         intel_ring_emit(engine, 0);
1549         PIPE_CONTROL_FLUSH(engine, scratch_addr);
1550         scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
1551         PIPE_CONTROL_FLUSH(engine, scratch_addr);
1552         scratch_addr += 2 * CACHELINE_BYTES;
1553         PIPE_CONTROL_FLUSH(engine, scratch_addr);
1554         scratch_addr += 2 * CACHELINE_BYTES;
1555         PIPE_CONTROL_FLUSH(engine, scratch_addr);
1556         scratch_addr += 2 * CACHELINE_BYTES;
1557         PIPE_CONTROL_FLUSH(engine, scratch_addr);
1558         scratch_addr += 2 * CACHELINE_BYTES;
1559         PIPE_CONTROL_FLUSH(engine, scratch_addr);
1560
1561         intel_ring_emit(engine,
1562                         GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1563                         PIPE_CONTROL_WRITE_FLUSH |
1564                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
1565                         PIPE_CONTROL_NOTIFY);
1566         intel_ring_emit(engine,
1567                         engine->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1568         intel_ring_emit(engine, i915_gem_request_get_seqno(req));
1569         intel_ring_emit(engine, 0);
1570         __intel_ring_advance(engine);
1571
1572         return 0;
1573 }
1574
1575 static void
1576 gen6_seqno_barrier(struct intel_engine_cs *engine)
1577 {
1578         struct drm_i915_private *dev_priv = engine->dev->dev_private;
1579
1580         /* Workaround to force correct ordering between irq and seqno writes on
1581          * ivb (and maybe also on snb) by reading from a CS register (like
1582          * ACTHD) before reading the status page.
1583          *
1584          * Note that this effectively stalls the read by the time it takes to
1585          * do a memory transaction, which more or less ensures that the write
1586          * from the GPU has sufficient time to invalidate the CPU cacheline.
1587          * Alternatively we could delay the interrupt from the CS ring to give
1588          * the write time to land, but that would incur a delay after every
1589          * batch i.e. much more frequent than a delay when waiting for the
1590          * interrupt (with the same net latency).
1591          *
1592          * Also note that to prevent whole machine hangs on gen7, we have to
1593          * take the spinlock to guard against concurrent cacheline access.
1594          */
1595         spin_lock_irq(&dev_priv->uncore.lock);
1596         POSTING_READ_FW(RING_ACTHD(engine->mmio_base));
1597         spin_unlock_irq(&dev_priv->uncore.lock);
1598 }
1599
1600 static u32
1601 ring_get_seqno(struct intel_engine_cs *engine)
1602 {
1603         return intel_read_status_page(engine, I915_GEM_HWS_INDEX);
1604 }
1605
1606 static void
1607 ring_set_seqno(struct intel_engine_cs *engine, u32 seqno)
1608 {
1609         intel_write_status_page(engine, I915_GEM_HWS_INDEX, seqno);
1610 }
1611
1612 static u32
1613 pc_render_get_seqno(struct intel_engine_cs *engine)
1614 {
1615         return engine->scratch.cpu_page[0];
1616 }
1617
1618 static void
1619 pc_render_set_seqno(struct intel_engine_cs *engine, u32 seqno)
1620 {
1621         engine->scratch.cpu_page[0] = seqno;
1622 }
1623
1624 static bool
1625 gen5_ring_get_irq(struct intel_engine_cs *engine)
1626 {
1627         struct drm_device *dev = engine->dev;
1628         struct drm_i915_private *dev_priv = dev->dev_private;
1629         unsigned long flags;
1630
1631         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1632                 return false;
1633
1634         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1635         if (engine->irq_refcount++ == 0)
1636                 gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask);
1637         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1638
1639         return true;
1640 }
1641
1642 static void
1643 gen5_ring_put_irq(struct intel_engine_cs *engine)
1644 {
1645         struct drm_device *dev = engine->dev;
1646         struct drm_i915_private *dev_priv = dev->dev_private;
1647         unsigned long flags;
1648
1649         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1650         if (--engine->irq_refcount == 0)
1651                 gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask);
1652         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1653 }
1654
1655 static bool
1656 i9xx_ring_get_irq(struct intel_engine_cs *engine)
1657 {
1658         struct drm_device *dev = engine->dev;
1659         struct drm_i915_private *dev_priv = dev->dev_private;
1660         unsigned long flags;
1661
1662         if (!intel_irqs_enabled(dev_priv))
1663                 return false;
1664
1665         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1666         if (engine->irq_refcount++ == 0) {
1667                 dev_priv->irq_mask &= ~engine->irq_enable_mask;
1668                 I915_WRITE(IMR, dev_priv->irq_mask);
1669                 POSTING_READ(IMR);
1670         }
1671         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1672
1673         return true;
1674 }
1675
1676 static void
1677 i9xx_ring_put_irq(struct intel_engine_cs *engine)
1678 {
1679         struct drm_device *dev = engine->dev;
1680         struct drm_i915_private *dev_priv = dev->dev_private;
1681         unsigned long flags;
1682
1683         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1684         if (--engine->irq_refcount == 0) {
1685                 dev_priv->irq_mask |= engine->irq_enable_mask;
1686                 I915_WRITE(IMR, dev_priv->irq_mask);
1687                 POSTING_READ(IMR);
1688         }
1689         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1690 }
1691
1692 static bool
1693 i8xx_ring_get_irq(struct intel_engine_cs *engine)
1694 {
1695         struct drm_device *dev = engine->dev;
1696         struct drm_i915_private *dev_priv = dev->dev_private;
1697         unsigned long flags;
1698
1699         if (!intel_irqs_enabled(dev_priv))
1700                 return false;
1701
1702         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1703         if (engine->irq_refcount++ == 0) {
1704                 dev_priv->irq_mask &= ~engine->irq_enable_mask;
1705                 I915_WRITE16(IMR, dev_priv->irq_mask);
1706                 POSTING_READ16(IMR);
1707         }
1708         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1709
1710         return true;
1711 }
1712
1713 static void
1714 i8xx_ring_put_irq(struct intel_engine_cs *engine)
1715 {
1716         struct drm_device *dev = engine->dev;
1717         struct drm_i915_private *dev_priv = dev->dev_private;
1718         unsigned long flags;
1719
1720         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1721         if (--engine->irq_refcount == 0) {
1722                 dev_priv->irq_mask |= engine->irq_enable_mask;
1723                 I915_WRITE16(IMR, dev_priv->irq_mask);
1724                 POSTING_READ16(IMR);
1725         }
1726         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1727 }
1728
1729 static int
1730 bsd_ring_flush(struct drm_i915_gem_request *req,
1731                u32     invalidate_domains,
1732                u32     flush_domains)
1733 {
1734         struct intel_engine_cs *engine = req->engine;
1735         int ret;
1736
1737         ret = intel_ring_begin(req, 2);
1738         if (ret)
1739                 return ret;
1740
1741         intel_ring_emit(engine, MI_FLUSH);
1742         intel_ring_emit(engine, MI_NOOP);
1743         intel_ring_advance(engine);
1744         return 0;
1745 }
1746
1747 static int
1748 i9xx_add_request(struct drm_i915_gem_request *req)
1749 {
1750         struct intel_engine_cs *engine = req->engine;
1751         int ret;
1752
1753         ret = intel_ring_begin(req, 4);
1754         if (ret)
1755                 return ret;
1756
1757         intel_ring_emit(engine, MI_STORE_DWORD_INDEX);
1758         intel_ring_emit(engine,
1759                         I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1760         intel_ring_emit(engine, i915_gem_request_get_seqno(req));
1761         intel_ring_emit(engine, MI_USER_INTERRUPT);
1762         __intel_ring_advance(engine);
1763
1764         return 0;
1765 }
1766
1767 static bool
1768 gen6_ring_get_irq(struct intel_engine_cs *engine)
1769 {
1770         struct drm_device *dev = engine->dev;
1771         struct drm_i915_private *dev_priv = dev->dev_private;
1772         unsigned long flags;
1773
1774         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1775                 return false;
1776
1777         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1778         if (engine->irq_refcount++ == 0) {
1779                 if (HAS_L3_DPF(dev) && engine->id == RCS)
1780                         I915_WRITE_IMR(engine,
1781                                        ~(engine->irq_enable_mask |
1782                                          GT_PARITY_ERROR(dev)));
1783                 else
1784                         I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
1785                 gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask);
1786         }
1787         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1788
1789         return true;
1790 }
1791
1792 static void
1793 gen6_ring_put_irq(struct intel_engine_cs *engine)
1794 {
1795         struct drm_device *dev = engine->dev;
1796         struct drm_i915_private *dev_priv = dev->dev_private;
1797         unsigned long flags;
1798
1799         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1800         if (--engine->irq_refcount == 0) {
1801                 if (HAS_L3_DPF(dev) && engine->id == RCS)
1802                         I915_WRITE_IMR(engine, ~GT_PARITY_ERROR(dev));
1803                 else
1804                         I915_WRITE_IMR(engine, ~0);
1805                 gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask);
1806         }
1807         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1808 }
1809
1810 static bool
1811 hsw_vebox_get_irq(struct intel_engine_cs *engine)
1812 {
1813         struct drm_device *dev = engine->dev;
1814         struct drm_i915_private *dev_priv = dev->dev_private;
1815         unsigned long flags;
1816
1817         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1818                 return false;
1819
1820         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1821         if (engine->irq_refcount++ == 0) {
1822                 I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
1823                 gen6_enable_pm_irq(dev_priv, engine->irq_enable_mask);
1824         }
1825         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1826
1827         return true;
1828 }
1829
1830 static void
1831 hsw_vebox_put_irq(struct intel_engine_cs *engine)
1832 {
1833         struct drm_device *dev = engine->dev;
1834         struct drm_i915_private *dev_priv = dev->dev_private;
1835         unsigned long flags;
1836
1837         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1838         if (--engine->irq_refcount == 0) {
1839                 I915_WRITE_IMR(engine, ~0);
1840                 gen6_disable_pm_irq(dev_priv, engine->irq_enable_mask);
1841         }
1842         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1843 }
1844
1845 static bool
1846 gen8_ring_get_irq(struct intel_engine_cs *engine)
1847 {
1848         struct drm_device *dev = engine->dev;
1849         struct drm_i915_private *dev_priv = dev->dev_private;
1850         unsigned long flags;
1851
1852         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1853                 return false;
1854
1855         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1856         if (engine->irq_refcount++ == 0) {
1857                 if (HAS_L3_DPF(dev) && engine->id == RCS) {
1858                         I915_WRITE_IMR(engine,
1859                                        ~(engine->irq_enable_mask |
1860                                          GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1861                 } else {
1862                         I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
1863                 }
1864                 POSTING_READ(RING_IMR(engine->mmio_base));
1865         }
1866         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1867
1868         return true;
1869 }
1870
1871 static void
1872 gen8_ring_put_irq(struct intel_engine_cs *engine)
1873 {
1874         struct drm_device *dev = engine->dev;
1875         struct drm_i915_private *dev_priv = dev->dev_private;
1876         unsigned long flags;
1877
1878         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1879         if (--engine->irq_refcount == 0) {
1880                 if (HAS_L3_DPF(dev) && engine->id == RCS) {
1881                         I915_WRITE_IMR(engine,
1882                                        ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1883                 } else {
1884                         I915_WRITE_IMR(engine, ~0);
1885                 }
1886                 POSTING_READ(RING_IMR(engine->mmio_base));
1887         }
1888         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1889 }
1890
1891 static int
1892 i965_dispatch_execbuffer(struct drm_i915_gem_request *req,
1893                          u64 offset, u32 length,
1894                          unsigned dispatch_flags)
1895 {
1896         struct intel_engine_cs *engine = req->engine;
1897         int ret;
1898
1899         ret = intel_ring_begin(req, 2);
1900         if (ret)
1901                 return ret;
1902
1903         intel_ring_emit(engine,
1904                         MI_BATCH_BUFFER_START |
1905                         MI_BATCH_GTT |
1906                         (dispatch_flags & I915_DISPATCH_SECURE ?
1907                          0 : MI_BATCH_NON_SECURE_I965));
1908         intel_ring_emit(engine, offset);
1909         intel_ring_advance(engine);
1910
1911         return 0;
1912 }
1913
1914 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1915 #define I830_BATCH_LIMIT (256*1024)
1916 #define I830_TLB_ENTRIES (2)
1917 #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
1918 static int
1919 i830_dispatch_execbuffer(struct drm_i915_gem_request *req,
1920                          u64 offset, u32 len,
1921                          unsigned dispatch_flags)
1922 {
1923         struct intel_engine_cs *engine = req->engine;
1924         u32 cs_offset = engine->scratch.gtt_offset;
1925         int ret;
1926
1927         ret = intel_ring_begin(req, 6);
1928         if (ret)
1929                 return ret;
1930
1931         /* Evict the invalid PTE TLBs */
1932         intel_ring_emit(engine, COLOR_BLT_CMD | BLT_WRITE_RGBA);
1933         intel_ring_emit(engine, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096);
1934         intel_ring_emit(engine, I830_TLB_ENTRIES << 16 | 4); /* load each page */
1935         intel_ring_emit(engine, cs_offset);
1936         intel_ring_emit(engine, 0xdeadbeef);
1937         intel_ring_emit(engine, MI_NOOP);
1938         intel_ring_advance(engine);
1939
1940         if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) {
1941                 if (len > I830_BATCH_LIMIT)
1942                         return -ENOSPC;
1943
1944                 ret = intel_ring_begin(req, 6 + 2);
1945                 if (ret)
1946                         return ret;
1947
1948                 /* Blit the batch (which has now all relocs applied) to the
1949                  * stable batch scratch bo area (so that the CS never
1950                  * stumbles over its tlb invalidation bug) ...
1951                  */
1952                 intel_ring_emit(engine, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA);
1953                 intel_ring_emit(engine,
1954                                 BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096);
1955                 intel_ring_emit(engine, DIV_ROUND_UP(len, 4096) << 16 | 4096);
1956                 intel_ring_emit(engine, cs_offset);
1957                 intel_ring_emit(engine, 4096);
1958                 intel_ring_emit(engine, offset);
1959
1960                 intel_ring_emit(engine, MI_FLUSH);
1961                 intel_ring_emit(engine, MI_NOOP);
1962                 intel_ring_advance(engine);
1963
1964                 /* ... and execute it. */
1965                 offset = cs_offset;
1966         }
1967
1968         ret = intel_ring_begin(req, 2);
1969         if (ret)
1970                 return ret;
1971
1972         intel_ring_emit(engine, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1973         intel_ring_emit(engine, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1974                                           0 : MI_BATCH_NON_SECURE));
1975         intel_ring_advance(engine);
1976
1977         return 0;
1978 }
1979
1980 static int
1981 i915_dispatch_execbuffer(struct drm_i915_gem_request *req,
1982                          u64 offset, u32 len,
1983                          unsigned dispatch_flags)
1984 {
1985         struct intel_engine_cs *engine = req->engine;
1986         int ret;
1987
1988         ret = intel_ring_begin(req, 2);
1989         if (ret)
1990                 return ret;
1991
1992         intel_ring_emit(engine, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1993         intel_ring_emit(engine, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1994                                           0 : MI_BATCH_NON_SECURE));
1995         intel_ring_advance(engine);
1996
1997         return 0;
1998 }
1999
2000 static void cleanup_phys_status_page(struct intel_engine_cs *engine)
2001 {
2002         struct drm_i915_private *dev_priv = to_i915(engine->dev);
2003
2004         if (!dev_priv->status_page_dmah)
2005                 return;
2006
2007         drm_pci_free(engine->dev, dev_priv->status_page_dmah);
2008         engine->status_page.page_addr = NULL;
2009 }
2010
2011 static void cleanup_status_page(struct intel_engine_cs *engine)
2012 {
2013         struct drm_i915_gem_object *obj;
2014
2015         obj = engine->status_page.obj;
2016         if (obj == NULL)
2017                 return;
2018
2019         kunmap(sg_page(obj->pages->sgl));
2020         i915_gem_object_ggtt_unpin(obj);
2021         drm_gem_object_unreference(&obj->base);
2022         engine->status_page.obj = NULL;
2023 }
2024
2025 static int init_status_page(struct intel_engine_cs *engine)
2026 {
2027         struct drm_i915_gem_object *obj = engine->status_page.obj;
2028
2029         if (obj == NULL) {
2030                 unsigned flags;
2031                 int ret;
2032
2033                 obj = i915_gem_alloc_object(engine->dev, 4096);
2034                 if (obj == NULL) {
2035                         DRM_ERROR("Failed to allocate status page\n");
2036                         return -ENOMEM;
2037                 }
2038
2039                 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2040                 if (ret)
2041                         goto err_unref;
2042
2043                 flags = 0;
2044                 if (!HAS_LLC(engine->dev))
2045                         /* On g33, we cannot place HWS above 256MiB, so
2046                          * restrict its pinning to the low mappable arena.
2047                          * Though this restriction is not documented for
2048                          * gen4, gen5, or byt, they also behave similarly
2049                          * and hang if the HWS is placed at the top of the
2050                          * GTT. To generalise, it appears that all !llc
2051                          * platforms have issues with us placing the HWS
2052                          * above the mappable region (even though we never
2053                          * actualy map it).
2054                          */
2055                         flags |= PIN_MAPPABLE;
2056                 ret = i915_gem_obj_ggtt_pin(obj, 4096, flags);
2057                 if (ret) {
2058 err_unref:
2059                         drm_gem_object_unreference(&obj->base);
2060                         return ret;
2061                 }
2062
2063                 engine->status_page.obj = obj;
2064         }
2065
2066         engine->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
2067         engine->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
2068         memset(engine->status_page.page_addr, 0, PAGE_SIZE);
2069
2070         DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
2071                         engine->name, engine->status_page.gfx_addr);
2072
2073         return 0;
2074 }
2075
2076 static int init_phys_status_page(struct intel_engine_cs *engine)
2077 {
2078         struct drm_i915_private *dev_priv = engine->dev->dev_private;
2079
2080         if (!dev_priv->status_page_dmah) {
2081                 dev_priv->status_page_dmah =
2082                         drm_pci_alloc(engine->dev, PAGE_SIZE, PAGE_SIZE);
2083                 if (!dev_priv->status_page_dmah)
2084                         return -ENOMEM;
2085         }
2086
2087         engine->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
2088         memset(engine->status_page.page_addr, 0, PAGE_SIZE);
2089
2090         return 0;
2091 }
2092
2093 void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
2094 {
2095         if (HAS_LLC(ringbuf->obj->base.dev) && !ringbuf->obj->stolen)
2096                 i915_gem_object_unpin_map(ringbuf->obj);
2097         else
2098                 iounmap(ringbuf->virtual_start);
2099         ringbuf->virtual_start = NULL;
2100         ringbuf->vma = NULL;
2101         i915_gem_object_ggtt_unpin(ringbuf->obj);
2102 }
2103
2104 int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
2105                                      struct intel_ringbuffer *ringbuf)
2106 {
2107         struct drm_i915_private *dev_priv = to_i915(dev);
2108         struct i915_ggtt *ggtt = &dev_priv->ggtt;
2109         struct drm_i915_gem_object *obj = ringbuf->obj;
2110         /* Ring wraparound at offset 0 sometimes hangs. No idea why. */
2111         unsigned flags = PIN_OFFSET_BIAS | 4096;
2112         void *addr;
2113         int ret;
2114
2115         if (HAS_LLC(dev_priv) && !obj->stolen) {
2116                 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, flags);
2117                 if (ret)
2118                         return ret;
2119
2120                 ret = i915_gem_object_set_to_cpu_domain(obj, true);
2121                 if (ret)
2122                         goto err_unpin;
2123
2124                 addr = i915_gem_object_pin_map(obj);
2125                 if (IS_ERR(addr)) {
2126                         ret = PTR_ERR(addr);
2127                         goto err_unpin;
2128                 }
2129         } else {
2130                 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE,
2131                                             flags | PIN_MAPPABLE);
2132                 if (ret)
2133                         return ret;
2134
2135                 ret = i915_gem_object_set_to_gtt_domain(obj, true);
2136                 if (ret)
2137                         goto err_unpin;
2138
2139                 /* Access through the GTT requires the device to be awake. */
2140                 assert_rpm_wakelock_held(dev_priv);
2141
2142                 addr = ioremap_wc(ggtt->mappable_base +
2143                                   i915_gem_obj_ggtt_offset(obj), ringbuf->size);
2144                 if (addr == NULL) {
2145                         ret = -ENOMEM;
2146                         goto err_unpin;
2147                 }
2148         }
2149
2150         ringbuf->virtual_start = addr;
2151         ringbuf->vma = i915_gem_obj_to_ggtt(obj);
2152         return 0;
2153
2154 err_unpin:
2155         i915_gem_object_ggtt_unpin(obj);
2156         return ret;
2157 }
2158
2159 static void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
2160 {
2161         drm_gem_object_unreference(&ringbuf->obj->base);
2162         ringbuf->obj = NULL;
2163 }
2164
2165 static int intel_alloc_ringbuffer_obj(struct drm_device *dev,
2166                                       struct intel_ringbuffer *ringbuf)
2167 {
2168         struct drm_i915_gem_object *obj;
2169
2170         obj = NULL;
2171         if (!HAS_LLC(dev))
2172                 obj = i915_gem_object_create_stolen(dev, ringbuf->size);
2173         if (obj == NULL)
2174                 obj = i915_gem_alloc_object(dev, ringbuf->size);
2175         if (obj == NULL)
2176                 return -ENOMEM;
2177
2178         /* mark ring buffers as read-only from GPU side by default */
2179         obj->gt_ro = 1;
2180
2181         ringbuf->obj = obj;
2182
2183         return 0;
2184 }
2185
2186 struct intel_ringbuffer *
2187 intel_engine_create_ringbuffer(struct intel_engine_cs *engine, int size)
2188 {
2189         struct intel_ringbuffer *ring;
2190         int ret;
2191
2192         ring = kzalloc(sizeof(*ring), GFP_KERNEL);
2193         if (ring == NULL) {
2194                 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n",
2195                                  engine->name);
2196                 return ERR_PTR(-ENOMEM);
2197         }
2198
2199         ring->engine = engine;
2200         list_add(&ring->link, &engine->buffers);
2201
2202         ring->size = size;
2203         /* Workaround an erratum on the i830 which causes a hang if
2204          * the TAIL pointer points to within the last 2 cachelines
2205          * of the buffer.
2206          */
2207         ring->effective_size = size;
2208         if (IS_I830(engine->dev) || IS_845G(engine->dev))
2209                 ring->effective_size -= 2 * CACHELINE_BYTES;
2210
2211         ring->last_retired_head = -1;
2212         intel_ring_update_space(ring);
2213
2214         ret = intel_alloc_ringbuffer_obj(engine->dev, ring);
2215         if (ret) {
2216                 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s: %d\n",
2217                                  engine->name, ret);
2218                 list_del(&ring->link);
2219                 kfree(ring);
2220                 return ERR_PTR(ret);
2221         }
2222
2223         return ring;
2224 }
2225
2226 void
2227 intel_ringbuffer_free(struct intel_ringbuffer *ring)
2228 {
2229         intel_destroy_ringbuffer_obj(ring);
2230         list_del(&ring->link);
2231         kfree(ring);
2232 }
2233
2234 static int intel_init_ring_buffer(struct drm_device *dev,
2235                                   struct intel_engine_cs *engine)
2236 {
2237         struct intel_ringbuffer *ringbuf;
2238         int ret;
2239
2240         WARN_ON(engine->buffer);
2241
2242         engine->dev = dev;
2243         INIT_LIST_HEAD(&engine->active_list);
2244         INIT_LIST_HEAD(&engine->request_list);
2245         INIT_LIST_HEAD(&engine->execlist_queue);
2246         INIT_LIST_HEAD(&engine->buffers);
2247         i915_gem_batch_pool_init(dev, &engine->batch_pool);
2248         memset(engine->semaphore.sync_seqno, 0,
2249                sizeof(engine->semaphore.sync_seqno));
2250
2251         init_waitqueue_head(&engine->irq_queue);
2252
2253         ringbuf = intel_engine_create_ringbuffer(engine, 32 * PAGE_SIZE);
2254         if (IS_ERR(ringbuf)) {
2255                 ret = PTR_ERR(ringbuf);
2256                 goto error;
2257         }
2258         engine->buffer = ringbuf;
2259
2260         if (I915_NEED_GFX_HWS(dev)) {
2261                 ret = init_status_page(engine);
2262                 if (ret)
2263                         goto error;
2264         } else {
2265                 WARN_ON(engine->id != RCS);
2266                 ret = init_phys_status_page(engine);
2267                 if (ret)
2268                         goto error;
2269         }
2270
2271         ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
2272         if (ret) {
2273                 DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
2274                                 engine->name, ret);
2275                 intel_destroy_ringbuffer_obj(ringbuf);
2276                 goto error;
2277         }
2278
2279         ret = i915_cmd_parser_init_ring(engine);
2280         if (ret)
2281                 goto error;
2282
2283         return 0;
2284
2285 error:
2286         intel_cleanup_engine(engine);
2287         return ret;
2288 }
2289
2290 void intel_cleanup_engine(struct intel_engine_cs *engine)
2291 {
2292         struct drm_i915_private *dev_priv;
2293
2294         if (!intel_engine_initialized(engine))
2295                 return;
2296
2297         dev_priv = to_i915(engine->dev);
2298
2299         if (engine->buffer) {
2300                 intel_stop_engine(engine);
2301                 WARN_ON(!IS_GEN2(engine->dev) && (I915_READ_MODE(engine) & MODE_IDLE) == 0);
2302
2303                 intel_unpin_ringbuffer_obj(engine->buffer);
2304                 intel_ringbuffer_free(engine->buffer);
2305                 engine->buffer = NULL;
2306         }
2307
2308         if (engine->cleanup)
2309                 engine->cleanup(engine);
2310
2311         if (I915_NEED_GFX_HWS(engine->dev)) {
2312                 cleanup_status_page(engine);
2313         } else {
2314                 WARN_ON(engine->id != RCS);
2315                 cleanup_phys_status_page(engine);
2316         }
2317
2318         i915_cmd_parser_fini_ring(engine);
2319         i915_gem_batch_pool_fini(&engine->batch_pool);
2320         engine->dev = NULL;
2321 }
2322
2323 int intel_engine_idle(struct intel_engine_cs *engine)
2324 {
2325         struct drm_i915_gem_request *req;
2326
2327         /* Wait upon the last request to be completed */
2328         if (list_empty(&engine->request_list))
2329                 return 0;
2330
2331         req = list_entry(engine->request_list.prev,
2332                          struct drm_i915_gem_request,
2333                          list);
2334
2335         /* Make sure we do not trigger any retires */
2336         return __i915_wait_request(req,
2337                                    req->i915->mm.interruptible,
2338                                    NULL, NULL);
2339 }
2340
2341 int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request)
2342 {
2343         request->ringbuf = request->engine->buffer;
2344         return 0;
2345 }
2346
2347 int intel_ring_reserve_space(struct drm_i915_gem_request *request)
2348 {
2349         /*
2350          * The first call merely notes the reserve request and is common for
2351          * all back ends. The subsequent localised _begin() call actually
2352          * ensures that the reservation is available. Without the begin, if
2353          * the request creator immediately submitted the request without
2354          * adding any commands to it then there might not actually be
2355          * sufficient room for the submission commands.
2356          */
2357         intel_ring_reserved_space_reserve(request->ringbuf, MIN_SPACE_FOR_ADD_REQUEST);
2358
2359         return intel_ring_begin(request, 0);
2360 }
2361
2362 void intel_ring_reserved_space_reserve(struct intel_ringbuffer *ringbuf, int size)
2363 {
2364         GEM_BUG_ON(ringbuf->reserved_size);
2365         ringbuf->reserved_size = size;
2366 }
2367
2368 void intel_ring_reserved_space_cancel(struct intel_ringbuffer *ringbuf)
2369 {
2370         GEM_BUG_ON(!ringbuf->reserved_size);
2371         ringbuf->reserved_size   = 0;
2372 }
2373
2374 void intel_ring_reserved_space_use(struct intel_ringbuffer *ringbuf)
2375 {
2376         GEM_BUG_ON(!ringbuf->reserved_size);
2377         ringbuf->reserved_size   = 0;
2378 }
2379
2380 void intel_ring_reserved_space_end(struct intel_ringbuffer *ringbuf)
2381 {
2382         GEM_BUG_ON(ringbuf->reserved_size);
2383 }
2384
2385 static int wait_for_space(struct drm_i915_gem_request *req, int bytes)
2386 {
2387         struct intel_ringbuffer *ringbuf = req->ringbuf;
2388         struct intel_engine_cs *engine = req->engine;
2389         struct drm_i915_gem_request *target;
2390
2391         intel_ring_update_space(ringbuf);
2392         if (ringbuf->space >= bytes)
2393                 return 0;
2394
2395         /*
2396          * Space is reserved in the ringbuffer for finalising the request,
2397          * as that cannot be allowed to fail. During request finalisation,
2398          * reserved_space is set to 0 to stop the overallocation and the
2399          * assumption is that then we never need to wait (which has the
2400          * risk of failing with EINTR).
2401          *
2402          * See also i915_gem_request_alloc() and i915_add_request().
2403          */
2404         GEM_BUG_ON(!ringbuf->reserved_size);
2405
2406         list_for_each_entry(target, &engine->request_list, list) {
2407                 unsigned space;
2408
2409                 /*
2410                  * The request queue is per-engine, so can contain requests
2411                  * from multiple ringbuffers. Here, we must ignore any that
2412                  * aren't from the ringbuffer we're considering.
2413                  */
2414                 if (target->ringbuf != ringbuf)
2415                         continue;
2416
2417                 /* Would completion of this request free enough space? */
2418                 space = __intel_ring_space(target->postfix, ringbuf->tail,
2419                                            ringbuf->size);
2420                 if (space >= bytes)
2421                         break;
2422         }
2423
2424         if (WARN_ON(&target->list == &engine->request_list))
2425                 return -ENOSPC;
2426
2427         return i915_wait_request(target);
2428 }
2429
2430 int intel_ring_begin(struct drm_i915_gem_request *req, int num_dwords)
2431 {
2432         struct intel_ringbuffer *ringbuf = req->ringbuf;
2433         int remain_actual = ringbuf->size - ringbuf->tail;
2434         int remain_usable = ringbuf->effective_size - ringbuf->tail;
2435         int bytes = num_dwords * sizeof(u32);
2436         int total_bytes, wait_bytes;
2437         bool need_wrap = false;
2438
2439         total_bytes = bytes + ringbuf->reserved_size;
2440
2441         if (unlikely(bytes > remain_usable)) {
2442                 /*
2443                  * Not enough space for the basic request. So need to flush
2444                  * out the remainder and then wait for base + reserved.
2445                  */
2446                 wait_bytes = remain_actual + total_bytes;
2447                 need_wrap = true;
2448         } else if (unlikely(total_bytes > remain_usable)) {
2449                 /*
2450                  * The base request will fit but the reserved space
2451                  * falls off the end. So we don't need an immediate wrap
2452                  * and only need to effectively wait for the reserved
2453                  * size space from the start of ringbuffer.
2454                  */
2455                 wait_bytes = remain_actual + ringbuf->reserved_size;
2456         } else {
2457                 /* No wrapping required, just waiting. */
2458                 wait_bytes = total_bytes;
2459         }
2460
2461         if (wait_bytes > ringbuf->space) {
2462                 int ret = wait_for_space(req, wait_bytes);
2463                 if (unlikely(ret))
2464                         return ret;
2465
2466                 intel_ring_update_space(ringbuf);
2467                 if (unlikely(ringbuf->space < wait_bytes))
2468                         return -EAGAIN;
2469         }
2470
2471         if (unlikely(need_wrap)) {
2472                 GEM_BUG_ON(remain_actual > ringbuf->space);
2473                 GEM_BUG_ON(ringbuf->tail + remain_actual > ringbuf->size);
2474
2475                 /* Fill the tail with MI_NOOP */
2476                 memset(ringbuf->virtual_start + ringbuf->tail,
2477                        0, remain_actual);
2478                 ringbuf->tail = 0;
2479                 ringbuf->space -= remain_actual;
2480         }
2481
2482         ringbuf->space -= bytes;
2483         GEM_BUG_ON(ringbuf->space < 0);
2484         return 0;
2485 }
2486
2487 /* Align the ring tail to a cacheline boundary */
2488 int intel_ring_cacheline_align(struct drm_i915_gem_request *req)
2489 {
2490         struct intel_engine_cs *engine = req->engine;
2491         int num_dwords = (engine->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
2492         int ret;
2493
2494         if (num_dwords == 0)
2495                 return 0;
2496
2497         num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
2498         ret = intel_ring_begin(req, num_dwords);
2499         if (ret)
2500                 return ret;
2501
2502         while (num_dwords--)
2503                 intel_ring_emit(engine, MI_NOOP);
2504
2505         intel_ring_advance(engine);
2506
2507         return 0;
2508 }
2509
2510 void intel_ring_init_seqno(struct intel_engine_cs *engine, u32 seqno)
2511 {
2512         struct drm_i915_private *dev_priv = to_i915(engine->dev);
2513
2514         /* Our semaphore implementation is strictly monotonic (i.e. we proceed
2515          * so long as the semaphore value in the register/page is greater
2516          * than the sync value), so whenever we reset the seqno,
2517          * so long as we reset the tracking semaphore value to 0, it will
2518          * always be before the next request's seqno. If we don't reset
2519          * the semaphore value, then when the seqno moves backwards all
2520          * future waits will complete instantly (causing rendering corruption).
2521          */
2522         if (INTEL_INFO(dev_priv)->gen == 6 || INTEL_INFO(dev_priv)->gen == 7) {
2523                 I915_WRITE(RING_SYNC_0(engine->mmio_base), 0);
2524                 I915_WRITE(RING_SYNC_1(engine->mmio_base), 0);
2525                 if (HAS_VEBOX(dev_priv))
2526                         I915_WRITE(RING_SYNC_2(engine->mmio_base), 0);
2527         }
2528         if (dev_priv->semaphore_obj) {
2529                 struct drm_i915_gem_object *obj = dev_priv->semaphore_obj;
2530                 struct page *page = i915_gem_object_get_dirty_page(obj, 0);
2531                 void *semaphores = kmap(page);
2532                 memset(semaphores + GEN8_SEMAPHORE_OFFSET(engine->id, 0),
2533                        0, I915_NUM_ENGINES * gen8_semaphore_seqno_size);
2534                 kunmap(page);
2535         }
2536         memset(engine->semaphore.sync_seqno, 0,
2537                sizeof(engine->semaphore.sync_seqno));
2538
2539         engine->set_seqno(engine, seqno);
2540         engine->last_submitted_seqno = seqno;
2541
2542         engine->hangcheck.seqno = seqno;
2543 }
2544
2545 static void gen6_bsd_ring_write_tail(struct intel_engine_cs *engine,
2546                                      u32 value)
2547 {
2548         struct drm_i915_private *dev_priv = engine->dev->dev_private;
2549
2550        /* Every tail move must follow the sequence below */
2551
2552         /* Disable notification that the ring is IDLE. The GT
2553          * will then assume that it is busy and bring it out of rc6.
2554          */
2555         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2556                    _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2557
2558         /* Clear the context id. Here be magic! */
2559         I915_WRITE64(GEN6_BSD_RNCID, 0x0);
2560
2561         /* Wait for the ring not to be idle, i.e. for it to wake up. */
2562         if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
2563                       GEN6_BSD_SLEEP_INDICATOR) == 0,
2564                      50))
2565                 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
2566
2567         /* Now that the ring is fully powered up, update the tail */
2568         I915_WRITE_TAIL(engine, value);
2569         POSTING_READ(RING_TAIL(engine->mmio_base));
2570
2571         /* Let the ring send IDLE messages to the GT again,
2572          * and so let it sleep to conserve power when idle.
2573          */
2574         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2575                    _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2576 }
2577
2578 static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req,
2579                                u32 invalidate, u32 flush)
2580 {
2581         struct intel_engine_cs *engine = req->engine;
2582         uint32_t cmd;
2583         int ret;
2584
2585         ret = intel_ring_begin(req, 4);
2586         if (ret)
2587                 return ret;
2588
2589         cmd = MI_FLUSH_DW;
2590         if (INTEL_INFO(engine->dev)->gen >= 8)
2591                 cmd += 1;
2592
2593         /* We always require a command barrier so that subsequent
2594          * commands, such as breadcrumb interrupts, are strictly ordered
2595          * wrt the contents of the write cache being flushed to memory
2596          * (and thus being coherent from the CPU).
2597          */
2598         cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2599
2600         /*
2601          * Bspec vol 1c.5 - video engine command streamer:
2602          * "If ENABLED, all TLBs will be invalidated once the flush
2603          * operation is complete. This bit is only valid when the
2604          * Post-Sync Operation field is a value of 1h or 3h."
2605          */
2606         if (invalidate & I915_GEM_GPU_DOMAINS)
2607                 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
2608
2609         intel_ring_emit(engine, cmd);
2610         intel_ring_emit(engine,
2611                         I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2612         if (INTEL_INFO(engine->dev)->gen >= 8) {
2613                 intel_ring_emit(engine, 0); /* upper addr */
2614                 intel_ring_emit(engine, 0); /* value */
2615         } else  {
2616                 intel_ring_emit(engine, 0);
2617                 intel_ring_emit(engine, MI_NOOP);
2618         }
2619         intel_ring_advance(engine);
2620         return 0;
2621 }
2622
2623 static int
2624 gen8_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
2625                               u64 offset, u32 len,
2626                               unsigned dispatch_flags)
2627 {
2628         struct intel_engine_cs *engine = req->engine;
2629         bool ppgtt = USES_PPGTT(engine->dev) &&
2630                         !(dispatch_flags & I915_DISPATCH_SECURE);
2631         int ret;
2632
2633         ret = intel_ring_begin(req, 4);
2634         if (ret)
2635                 return ret;
2636
2637         /* FIXME(BDW): Address space and security selectors. */
2638         intel_ring_emit(engine, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8) |
2639                         (dispatch_flags & I915_DISPATCH_RS ?
2640                          MI_BATCH_RESOURCE_STREAMER : 0));
2641         intel_ring_emit(engine, lower_32_bits(offset));
2642         intel_ring_emit(engine, upper_32_bits(offset));
2643         intel_ring_emit(engine, MI_NOOP);
2644         intel_ring_advance(engine);
2645
2646         return 0;
2647 }
2648
2649 static int
2650 hsw_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
2651                              u64 offset, u32 len,
2652                              unsigned dispatch_flags)
2653 {
2654         struct intel_engine_cs *engine = req->engine;
2655         int ret;
2656
2657         ret = intel_ring_begin(req, 2);
2658         if (ret)
2659                 return ret;
2660
2661         intel_ring_emit(engine,
2662                         MI_BATCH_BUFFER_START |
2663                         (dispatch_flags & I915_DISPATCH_SECURE ?
2664                          0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW) |
2665                         (dispatch_flags & I915_DISPATCH_RS ?
2666                          MI_BATCH_RESOURCE_STREAMER : 0));
2667         /* bit0-7 is the length on GEN6+ */
2668         intel_ring_emit(engine, offset);
2669         intel_ring_advance(engine);
2670
2671         return 0;
2672 }
2673
2674 static int
2675 gen6_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
2676                               u64 offset, u32 len,
2677                               unsigned dispatch_flags)
2678 {
2679         struct intel_engine_cs *engine = req->engine;
2680         int ret;
2681
2682         ret = intel_ring_begin(req, 2);
2683         if (ret)
2684                 return ret;
2685
2686         intel_ring_emit(engine,
2687                         MI_BATCH_BUFFER_START |
2688                         (dispatch_flags & I915_DISPATCH_SECURE ?
2689                          0 : MI_BATCH_NON_SECURE_I965));
2690         /* bit0-7 is the length on GEN6+ */
2691         intel_ring_emit(engine, offset);
2692         intel_ring_advance(engine);
2693
2694         return 0;
2695 }
2696
2697 /* Blitter support (SandyBridge+) */
2698
2699 static int gen6_ring_flush(struct drm_i915_gem_request *req,
2700                            u32 invalidate, u32 flush)
2701 {
2702         struct intel_engine_cs *engine = req->engine;
2703         struct drm_device *dev = engine->dev;
2704         uint32_t cmd;
2705         int ret;
2706
2707         ret = intel_ring_begin(req, 4);
2708         if (ret)
2709                 return ret;
2710
2711         cmd = MI_FLUSH_DW;
2712         if (INTEL_INFO(dev)->gen >= 8)
2713                 cmd += 1;
2714
2715         /* We always require a command barrier so that subsequent
2716          * commands, such as breadcrumb interrupts, are strictly ordered
2717          * wrt the contents of the write cache being flushed to memory
2718          * (and thus being coherent from the CPU).
2719          */
2720         cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2721
2722         /*
2723          * Bspec vol 1c.3 - blitter engine command streamer:
2724          * "If ENABLED, all TLBs will be invalidated once the flush
2725          * operation is complete. This bit is only valid when the
2726          * Post-Sync Operation field is a value of 1h or 3h."
2727          */
2728         if (invalidate & I915_GEM_DOMAIN_RENDER)
2729                 cmd |= MI_INVALIDATE_TLB;
2730         intel_ring_emit(engine, cmd);
2731         intel_ring_emit(engine,
2732                         I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2733         if (INTEL_INFO(dev)->gen >= 8) {
2734                 intel_ring_emit(engine, 0); /* upper addr */
2735                 intel_ring_emit(engine, 0); /* value */
2736         } else  {
2737                 intel_ring_emit(engine, 0);
2738                 intel_ring_emit(engine, MI_NOOP);
2739         }
2740         intel_ring_advance(engine);
2741
2742         return 0;
2743 }
2744
2745 int intel_init_render_ring_buffer(struct drm_device *dev)
2746 {
2747         struct drm_i915_private *dev_priv = dev->dev_private;
2748         struct intel_engine_cs *engine = &dev_priv->engine[RCS];
2749         struct drm_i915_gem_object *obj;
2750         int ret;
2751
2752         engine->name = "render ring";
2753         engine->id = RCS;
2754         engine->exec_id = I915_EXEC_RENDER;
2755         engine->hw_id = 0;
2756         engine->mmio_base = RENDER_RING_BASE;
2757
2758         if (INTEL_INFO(dev)->gen >= 8) {
2759                 if (i915_semaphore_is_enabled(dev)) {
2760                         obj = i915_gem_alloc_object(dev, 4096);
2761                         if (obj == NULL) {
2762                                 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2763                                 i915.semaphores = 0;
2764                         } else {
2765                                 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2766                                 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK);
2767                                 if (ret != 0) {
2768                                         drm_gem_object_unreference(&obj->base);
2769                                         DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2770                                         i915.semaphores = 0;
2771                                 } else
2772                                         dev_priv->semaphore_obj = obj;
2773                         }
2774                 }
2775
2776                 engine->init_context = intel_rcs_ctx_init;
2777                 engine->add_request = gen6_add_request;
2778                 engine->flush = gen8_render_ring_flush;
2779                 engine->irq_get = gen8_ring_get_irq;
2780                 engine->irq_put = gen8_ring_put_irq;
2781                 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2782                 engine->irq_seqno_barrier = gen6_seqno_barrier;
2783                 engine->get_seqno = ring_get_seqno;
2784                 engine->set_seqno = ring_set_seqno;
2785                 if (i915_semaphore_is_enabled(dev)) {
2786                         WARN_ON(!dev_priv->semaphore_obj);
2787                         engine->semaphore.sync_to = gen8_ring_sync;
2788                         engine->semaphore.signal = gen8_rcs_signal;
2789                         GEN8_RING_SEMAPHORE_INIT(engine);
2790                 }
2791         } else if (INTEL_INFO(dev)->gen >= 6) {
2792                 engine->init_context = intel_rcs_ctx_init;
2793                 engine->add_request = gen6_add_request;
2794                 engine->flush = gen7_render_ring_flush;
2795                 if (INTEL_INFO(dev)->gen == 6)
2796                         engine->flush = gen6_render_ring_flush;
2797                 engine->irq_get = gen6_ring_get_irq;
2798                 engine->irq_put = gen6_ring_put_irq;
2799                 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2800                 engine->irq_seqno_barrier = gen6_seqno_barrier;
2801                 engine->get_seqno = ring_get_seqno;
2802                 engine->set_seqno = ring_set_seqno;
2803                 if (i915_semaphore_is_enabled(dev)) {
2804                         engine->semaphore.sync_to = gen6_ring_sync;
2805                         engine->semaphore.signal = gen6_signal;
2806                         /*
2807                          * The current semaphore is only applied on pre-gen8
2808                          * platform.  And there is no VCS2 ring on the pre-gen8
2809                          * platform. So the semaphore between RCS and VCS2 is
2810                          * initialized as INVALID.  Gen8 will initialize the
2811                          * sema between VCS2 and RCS later.
2812                          */
2813                         engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID;
2814                         engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV;
2815                         engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB;
2816                         engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE;
2817                         engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2818                         engine->semaphore.mbox.signal[RCS] = GEN6_NOSYNC;
2819                         engine->semaphore.mbox.signal[VCS] = GEN6_VRSYNC;
2820                         engine->semaphore.mbox.signal[BCS] = GEN6_BRSYNC;
2821                         engine->semaphore.mbox.signal[VECS] = GEN6_VERSYNC;
2822                         engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2823                 }
2824         } else if (IS_GEN5(dev)) {
2825                 engine->add_request = pc_render_add_request;
2826                 engine->flush = gen4_render_ring_flush;
2827                 engine->get_seqno = pc_render_get_seqno;
2828                 engine->set_seqno = pc_render_set_seqno;
2829                 engine->irq_get = gen5_ring_get_irq;
2830                 engine->irq_put = gen5_ring_put_irq;
2831                 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
2832                                         GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
2833         } else {
2834                 engine->add_request = i9xx_add_request;
2835                 if (INTEL_INFO(dev)->gen < 4)
2836                         engine->flush = gen2_render_ring_flush;
2837                 else
2838                         engine->flush = gen4_render_ring_flush;
2839                 engine->get_seqno = ring_get_seqno;
2840                 engine->set_seqno = ring_set_seqno;
2841                 if (IS_GEN2(dev)) {
2842                         engine->irq_get = i8xx_ring_get_irq;
2843                         engine->irq_put = i8xx_ring_put_irq;
2844                 } else {
2845                         engine->irq_get = i9xx_ring_get_irq;
2846                         engine->irq_put = i9xx_ring_put_irq;
2847                 }
2848                 engine->irq_enable_mask = I915_USER_INTERRUPT;
2849         }
2850         engine->write_tail = ring_write_tail;
2851
2852         if (IS_HASWELL(dev))
2853                 engine->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
2854         else if (IS_GEN8(dev))
2855                 engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2856         else if (INTEL_INFO(dev)->gen >= 6)
2857                 engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2858         else if (INTEL_INFO(dev)->gen >= 4)
2859                 engine->dispatch_execbuffer = i965_dispatch_execbuffer;
2860         else if (IS_I830(dev) || IS_845G(dev))
2861                 engine->dispatch_execbuffer = i830_dispatch_execbuffer;
2862         else
2863                 engine->dispatch_execbuffer = i915_dispatch_execbuffer;
2864         engine->init_hw = init_render_ring;
2865         engine->cleanup = render_ring_cleanup;
2866
2867         /* Workaround batchbuffer to combat CS tlb bug. */
2868         if (HAS_BROKEN_CS_TLB(dev)) {
2869                 obj = i915_gem_alloc_object(dev, I830_WA_SIZE);
2870                 if (obj == NULL) {
2871                         DRM_ERROR("Failed to allocate batch bo\n");
2872                         return -ENOMEM;
2873                 }
2874
2875                 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
2876                 if (ret != 0) {
2877                         drm_gem_object_unreference(&obj->base);
2878                         DRM_ERROR("Failed to ping batch bo\n");
2879                         return ret;
2880                 }
2881
2882                 engine->scratch.obj = obj;
2883                 engine->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
2884         }
2885
2886         ret = intel_init_ring_buffer(dev, engine);
2887         if (ret)
2888                 return ret;
2889
2890         if (INTEL_INFO(dev)->gen >= 5) {
2891                 ret = intel_init_pipe_control(engine);
2892                 if (ret)
2893                         return ret;
2894         }
2895
2896         return 0;
2897 }
2898
2899 int intel_init_bsd_ring_buffer(struct drm_device *dev)
2900 {
2901         struct drm_i915_private *dev_priv = dev->dev_private;
2902         struct intel_engine_cs *engine = &dev_priv->engine[VCS];
2903
2904         engine->name = "bsd ring";
2905         engine->id = VCS;
2906         engine->exec_id = I915_EXEC_BSD;
2907         engine->hw_id = 1;
2908
2909         engine->write_tail = ring_write_tail;
2910         if (INTEL_INFO(dev)->gen >= 6) {
2911                 engine->mmio_base = GEN6_BSD_RING_BASE;
2912                 /* gen6 bsd needs a special wa for tail updates */
2913                 if (IS_GEN6(dev))
2914                         engine->write_tail = gen6_bsd_ring_write_tail;
2915                 engine->flush = gen6_bsd_ring_flush;
2916                 engine->add_request = gen6_add_request;
2917                 engine->irq_seqno_barrier = gen6_seqno_barrier;
2918                 engine->get_seqno = ring_get_seqno;
2919                 engine->set_seqno = ring_set_seqno;
2920                 if (INTEL_INFO(dev)->gen >= 8) {
2921                         engine->irq_enable_mask =
2922                                 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2923                         engine->irq_get = gen8_ring_get_irq;
2924                         engine->irq_put = gen8_ring_put_irq;
2925                         engine->dispatch_execbuffer =
2926                                 gen8_ring_dispatch_execbuffer;
2927                         if (i915_semaphore_is_enabled(dev)) {
2928                                 engine->semaphore.sync_to = gen8_ring_sync;
2929                                 engine->semaphore.signal = gen8_xcs_signal;
2930                                 GEN8_RING_SEMAPHORE_INIT(engine);
2931                         }
2932                 } else {
2933                         engine->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2934                         engine->irq_get = gen6_ring_get_irq;
2935                         engine->irq_put = gen6_ring_put_irq;
2936                         engine->dispatch_execbuffer =
2937                                 gen6_ring_dispatch_execbuffer;
2938                         if (i915_semaphore_is_enabled(dev)) {
2939                                 engine->semaphore.sync_to = gen6_ring_sync;
2940                                 engine->semaphore.signal = gen6_signal;
2941                                 engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;
2942                                 engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2943                                 engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB;
2944                                 engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE;
2945                                 engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2946                                 engine->semaphore.mbox.signal[RCS] = GEN6_RVSYNC;
2947                                 engine->semaphore.mbox.signal[VCS] = GEN6_NOSYNC;
2948                                 engine->semaphore.mbox.signal[BCS] = GEN6_BVSYNC;
2949                                 engine->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC;
2950                                 engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2951                         }
2952                 }
2953         } else {
2954                 engine->mmio_base = BSD_RING_BASE;
2955                 engine->flush = bsd_ring_flush;
2956                 engine->add_request = i9xx_add_request;
2957                 engine->get_seqno = ring_get_seqno;
2958                 engine->set_seqno = ring_set_seqno;
2959                 if (IS_GEN5(dev)) {
2960                         engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
2961                         engine->irq_get = gen5_ring_get_irq;
2962                         engine->irq_put = gen5_ring_put_irq;
2963                 } else {
2964                         engine->irq_enable_mask = I915_BSD_USER_INTERRUPT;
2965                         engine->irq_get = i9xx_ring_get_irq;
2966                         engine->irq_put = i9xx_ring_put_irq;
2967                 }
2968                 engine->dispatch_execbuffer = i965_dispatch_execbuffer;
2969         }
2970         engine->init_hw = init_ring_common;
2971
2972         return intel_init_ring_buffer(dev, engine);
2973 }
2974
2975 /**
2976  * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3)
2977  */
2978 int intel_init_bsd2_ring_buffer(struct drm_device *dev)
2979 {
2980         struct drm_i915_private *dev_priv = dev->dev_private;
2981         struct intel_engine_cs *engine = &dev_priv->engine[VCS2];
2982
2983         engine->name = "bsd2 ring";
2984         engine->id = VCS2;
2985         engine->exec_id = I915_EXEC_BSD;
2986         engine->hw_id = 4;
2987
2988         engine->write_tail = ring_write_tail;
2989         engine->mmio_base = GEN8_BSD2_RING_BASE;
2990         engine->flush = gen6_bsd_ring_flush;
2991         engine->add_request = gen6_add_request;
2992         engine->irq_seqno_barrier = gen6_seqno_barrier;
2993         engine->get_seqno = ring_get_seqno;
2994         engine->set_seqno = ring_set_seqno;
2995         engine->irq_enable_mask =
2996                         GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
2997         engine->irq_get = gen8_ring_get_irq;
2998         engine->irq_put = gen8_ring_put_irq;
2999         engine->dispatch_execbuffer =
3000                         gen8_ring_dispatch_execbuffer;
3001         if (i915_semaphore_is_enabled(dev)) {
3002                 engine->semaphore.sync_to = gen8_ring_sync;
3003                 engine->semaphore.signal = gen8_xcs_signal;
3004                 GEN8_RING_SEMAPHORE_INIT(engine);
3005         }
3006         engine->init_hw = init_ring_common;
3007
3008         return intel_init_ring_buffer(dev, engine);
3009 }
3010
3011 int intel_init_blt_ring_buffer(struct drm_device *dev)
3012 {
3013         struct drm_i915_private *dev_priv = dev->dev_private;
3014         struct intel_engine_cs *engine = &dev_priv->engine[BCS];
3015
3016         engine->name = "blitter ring";
3017         engine->id = BCS;
3018         engine->exec_id = I915_EXEC_BLT;
3019         engine->hw_id = 2;
3020
3021         engine->mmio_base = BLT_RING_BASE;
3022         engine->write_tail = ring_write_tail;
3023         engine->flush = gen6_ring_flush;
3024         engine->add_request = gen6_add_request;
3025         engine->irq_seqno_barrier = gen6_seqno_barrier;
3026         engine->get_seqno = ring_get_seqno;
3027         engine->set_seqno = ring_set_seqno;
3028         if (INTEL_INFO(dev)->gen >= 8) {
3029                 engine->irq_enable_mask =
3030                         GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
3031                 engine->irq_get = gen8_ring_get_irq;
3032                 engine->irq_put = gen8_ring_put_irq;
3033                 engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
3034                 if (i915_semaphore_is_enabled(dev)) {
3035                         engine->semaphore.sync_to = gen8_ring_sync;
3036                         engine->semaphore.signal = gen8_xcs_signal;
3037                         GEN8_RING_SEMAPHORE_INIT(engine);
3038                 }
3039         } else {
3040                 engine->irq_enable_mask = GT_BLT_USER_INTERRUPT;
3041                 engine->irq_get = gen6_ring_get_irq;
3042                 engine->irq_put = gen6_ring_put_irq;
3043                 engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
3044                 if (i915_semaphore_is_enabled(dev)) {
3045                         engine->semaphore.signal = gen6_signal;
3046                         engine->semaphore.sync_to = gen6_ring_sync;
3047                         /*
3048                          * The current semaphore is only applied on pre-gen8
3049                          * platform.  And there is no VCS2 ring on the pre-gen8
3050                          * platform. So the semaphore between BCS and VCS2 is
3051                          * initialized as INVALID.  Gen8 will initialize the
3052                          * sema between BCS and VCS2 later.
3053                          */
3054                         engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR;
3055                         engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV;
3056                         engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID;
3057                         engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE;
3058                         engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
3059                         engine->semaphore.mbox.signal[RCS] = GEN6_RBSYNC;
3060                         engine->semaphore.mbox.signal[VCS] = GEN6_VBSYNC;
3061                         engine->semaphore.mbox.signal[BCS] = GEN6_NOSYNC;
3062                         engine->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC;
3063                         engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
3064                 }
3065         }
3066         engine->init_hw = init_ring_common;
3067
3068         return intel_init_ring_buffer(dev, engine);
3069 }
3070
3071 int intel_init_vebox_ring_buffer(struct drm_device *dev)
3072 {
3073         struct drm_i915_private *dev_priv = dev->dev_private;
3074         struct intel_engine_cs *engine = &dev_priv->engine[VECS];
3075
3076         engine->name = "video enhancement ring";
3077         engine->id = VECS;
3078         engine->exec_id = I915_EXEC_VEBOX;
3079         engine->hw_id = 3;
3080
3081         engine->mmio_base = VEBOX_RING_BASE;
3082         engine->write_tail = ring_write_tail;
3083         engine->flush = gen6_ring_flush;
3084         engine->add_request = gen6_add_request;
3085         engine->irq_seqno_barrier = gen6_seqno_barrier;
3086         engine->get_seqno = ring_get_seqno;
3087         engine->set_seqno = ring_set_seqno;
3088
3089         if (INTEL_INFO(dev)->gen >= 8) {
3090                 engine->irq_enable_mask =
3091                         GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
3092                 engine->irq_get = gen8_ring_get_irq;
3093                 engine->irq_put = gen8_ring_put_irq;
3094                 engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
3095                 if (i915_semaphore_is_enabled(dev)) {
3096                         engine->semaphore.sync_to = gen8_ring_sync;
3097                         engine->semaphore.signal = gen8_xcs_signal;
3098                         GEN8_RING_SEMAPHORE_INIT(engine);
3099                 }
3100         } else {
3101                 engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
3102                 engine->irq_get = hsw_vebox_get_irq;
3103                 engine->irq_put = hsw_vebox_put_irq;
3104                 engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
3105                 if (i915_semaphore_is_enabled(dev)) {
3106                         engine->semaphore.sync_to = gen6_ring_sync;
3107                         engine->semaphore.signal = gen6_signal;
3108                         engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;
3109                         engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV;
3110                         engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB;
3111                         engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID;
3112                         engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
3113                         engine->semaphore.mbox.signal[RCS] = GEN6_RVESYNC;
3114                         engine->semaphore.mbox.signal[VCS] = GEN6_VVESYNC;
3115                         engine->semaphore.mbox.signal[BCS] = GEN6_BVESYNC;
3116                         engine->semaphore.mbox.signal[VECS] = GEN6_NOSYNC;
3117                         engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
3118                 }
3119         }
3120         engine->init_hw = init_ring_common;
3121
3122         return intel_init_ring_buffer(dev, engine);
3123 }
3124
3125 int
3126 intel_ring_flush_all_caches(struct drm_i915_gem_request *req)
3127 {
3128         struct intel_engine_cs *engine = req->engine;
3129         int ret;
3130
3131         if (!engine->gpu_caches_dirty)
3132                 return 0;
3133
3134         ret = engine->flush(req, 0, I915_GEM_GPU_DOMAINS);
3135         if (ret)
3136                 return ret;
3137
3138         trace_i915_gem_ring_flush(req, 0, I915_GEM_GPU_DOMAINS);
3139
3140         engine->gpu_caches_dirty = false;
3141         return 0;
3142 }
3143
3144 int
3145 intel_ring_invalidate_all_caches(struct drm_i915_gem_request *req)
3146 {
3147         struct intel_engine_cs *engine = req->engine;
3148         uint32_t flush_domains;
3149         int ret;
3150
3151         flush_domains = 0;
3152         if (engine->gpu_caches_dirty)
3153                 flush_domains = I915_GEM_GPU_DOMAINS;
3154
3155         ret = engine->flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
3156         if (ret)
3157                 return ret;
3158
3159         trace_i915_gem_ring_flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
3160
3161         engine->gpu_caches_dirty = false;
3162         return 0;
3163 }
3164
3165 void
3166 intel_stop_engine(struct intel_engine_cs *engine)
3167 {
3168         int ret;
3169
3170         if (!intel_engine_initialized(engine))
3171                 return;
3172
3173         ret = intel_engine_idle(engine);
3174         if (ret)
3175                 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
3176                           engine->name, ret);
3177
3178         stop_ring(engine);
3179 }