drivers/gpu/drm/i915/intel_ringbuffer.c

   1 /*
   2  * Copyright © 2008-2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Zou Nan hai <nanhai.zou@intel.com>
  26  *    Xiang Hai hao<haihao.xiang@intel.com>
  27  *
  28  */
  29
  30 #include <linux/log2.h>
  31 #include <drm/drmP.h>
  32 #include "i915_drv.h"
  33 #include <drm/i915_drm.h>
  34 #include "i915_trace.h"
  35 #include "intel_drv.h"
  36
  37 /* Rough estimate of the typical request size, performing a flush,
  38  * set-context and then emitting the batch.
  39  */
  40 #define LEGACY_REQUEST_SIZE 200
  41
  42 int __intel_ring_space(int head, int tail, int size)
  43 {
  44         int space = head - tail;
  45         if (space <= 0)
  46                 space += size;
  47         return space - I915_RING_FREE_SPACE;
  48 }
  49
  50 void intel_ring_update_space(struct intel_ring *ring)
  51 {
  52         if (ring->last_retired_head != -1) {
  53                 ring->head = ring->last_retired_head;
  54                 ring->last_retired_head = -1;
  55         }
  56
  57         ring->space = __intel_ring_space(ring->head & HEAD_ADDR,
  58                                          ring->tail, ring->size);
  59 }
  60
  61 static int
  62 gen2_render_ring_flush(struct drm_i915_gem_request *req, u32 mode)
  63 {
  64         struct intel_ring *ring = req->ring;
  65         u32 cmd;
  66         int ret;
  67
  68         cmd = MI_FLUSH;
  69
  70         if (mode & EMIT_INVALIDATE)
  71                 cmd |= MI_READ_FLUSH;
  72
  73         ret = intel_ring_begin(req, 2);
  74         if (ret)
  75                 return ret;
  76
  77         intel_ring_emit(ring, cmd);
  78         intel_ring_emit(ring, MI_NOOP);
  79         intel_ring_advance(ring);
  80
  81         return 0;
  82 }
  83
  84 static int
  85 gen4_render_ring_flush(struct drm_i915_gem_request *req, u32 mode)
  86 {
  87         struct intel_ring *ring = req->ring;
  88         u32 cmd;
  89         int ret;
  90
  91         /*
  92          * read/write caches:
  93          *
  94          * I915_GEM_DOMAIN_RENDER is always invalidated, but is
  95          * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
  96          * also flushed at 2d versus 3d pipeline switches.
  97          *
  98          * read-only caches:
  99          *
 100          * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
 101          * MI_READ_FLUSH is set, and is always flushed on 965.
 102          *
 103          * I915_GEM_DOMAIN_COMMAND may not exist?
 104          *
 105          * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
 106          * invalidated when MI_EXE_FLUSH is set.
 107          *
 108          * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
 109          * invalidated with every MI_FLUSH.
 110          *
 111          * TLBs:
 112          *
 113          * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
 114          * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
 115          * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
 116          * are flushed at any MI_FLUSH.
 117          */
 118
 119         cmd = MI_FLUSH;
 120         if (mode & EMIT_INVALIDATE) {
 121                 cmd |= MI_EXE_FLUSH;
 122                 if (IS_G4X(req->i915) || IS_GEN5(req->i915))
 123                         cmd |= MI_INVALIDATE_ISP;
 124         }
 125
 126         ret = intel_ring_begin(req, 2);
 127         if (ret)
 128                 return ret;
 129
 130         intel_ring_emit(ring, cmd);
 131         intel_ring_emit(ring, MI_NOOP);
 132         intel_ring_advance(ring);
 133
 134         return 0;
 135 }
 136
 137 /**
 138  * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
 139  * implementing two workarounds on gen6.  From section 1.4.7.1
 140  * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
 141  *
 142  * [DevSNB-C+{W/A}] Before any depth stall flush (including those
 143  * produced by non-pipelined state commands), software needs to first
 144  * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
 145  * 0.
 146  *
 147  * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
 148  * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
 149  *
 150  * And the workaround for these two requires this workaround first:
 151  *
 152  * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
 153  * BEFORE the pipe-control with a post-sync op and no write-cache
 154  * flushes.
 155  *
 156  * And this last workaround is tricky because of the requirements on
 157  * that bit.  From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
 158  * volume 2 part 1:
 159  *
 160  *     "1 of the following must also be set:
 161  *      - Render Target Cache Flush Enable ([12] of DW1)
 162  *      - Depth Cache Flush Enable ([0] of DW1)
 163  *      - Stall at Pixel Scoreboard ([1] of DW1)
 164  *      - Depth Stall ([13] of DW1)
 165  *      - Post-Sync Operation ([13] of DW1)
 166  *      - Notify Enable ([8] of DW1)"
 167  *
 168  * The cache flushes require the workaround flush that triggered this
 169  * one, so we can't use it.  Depth stall would trigger the same.
 170  * Post-sync nonzero is what triggered this second workaround, so we
 171  * can't use that one either.  Notify enable is IRQs, which aren't
 172  * really our business.  That leaves only stall at scoreboard.
 173  */
 174 static int
 175 intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request *req)
 176 {
 177         struct intel_ring *ring = req->ring;
 178         u32 scratch_addr =
 179                 i915_ggtt_offset(req->engine->scratch) + 2 * CACHELINE_BYTES;
 180         int ret;
 181
 182         ret = intel_ring_begin(req, 6);
 183         if (ret)
 184                 return ret;
 185
 186         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 187         intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
 188                         PIPE_CONTROL_STALL_AT_SCOREBOARD);
 189         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
 190         intel_ring_emit(ring, 0); /* low dword */
 191         intel_ring_emit(ring, 0); /* high dword */
 192         intel_ring_emit(ring, MI_NOOP);
 193         intel_ring_advance(ring);
 194
 195         ret = intel_ring_begin(req, 6);
 196         if (ret)
 197                 return ret;
 198
 199         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 200         intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
 201         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
 202         intel_ring_emit(ring, 0);
 203         intel_ring_emit(ring, 0);
 204         intel_ring_emit(ring, MI_NOOP);
 205         intel_ring_advance(ring);
 206
 207         return 0;
 208 }
 209
 210 static int
 211 gen6_render_ring_flush(struct drm_i915_gem_request *req, u32 mode)
 212 {
 213         struct intel_ring *ring = req->ring;
 214         u32 scratch_addr =
 215                 i915_ggtt_offset(req->engine->scratch) + 2 * CACHELINE_BYTES;
 216         u32 flags = 0;
 217         int ret;
 218
 219         /* Force SNB workarounds for PIPE_CONTROL flushes */
 220         ret = intel_emit_post_sync_nonzero_flush(req);
 221         if (ret)
 222                 return ret;
 223
 224         /* Just flush everything.  Experiments have shown that reducing the
 225          * number of bits based on the write domains has little performance
 226          * impact.
 227          */
 228         if (mode & EMIT_FLUSH) {
 229                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 230                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 231                 /*
 232                  * Ensure that any following seqno writes only happen
 233                  * when the render cache is indeed flushed.
 234                  */
 235                 flags |= PIPE_CONTROL_CS_STALL;
 236         }
 237         if (mode & EMIT_INVALIDATE) {
 238                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 239                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 240                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 241                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 242                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 243                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 244                 /*
 245                  * TLB invalidate requires a post-sync write.
 246                  */
 247                 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
 248         }
 249
 250         ret = intel_ring_begin(req, 4);
 251         if (ret)
 252                 return ret;
 253
 254         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 255         intel_ring_emit(ring, flags);
 256         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
 257         intel_ring_emit(ring, 0);
 258         intel_ring_advance(ring);
 259
 260         return 0;
 261 }
 262
 263 static int
 264 gen7_render_ring_cs_stall_wa(struct drm_i915_gem_request *req)
 265 {
 266         struct intel_ring *ring = req->ring;
 267         int ret;
 268
 269         ret = intel_ring_begin(req, 4);
 270         if (ret)
 271                 return ret;
 272
 273         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 274         intel_ring_emit(ring,
 275                         PIPE_CONTROL_CS_STALL |
 276                         PIPE_CONTROL_STALL_AT_SCOREBOARD);
 277         intel_ring_emit(ring, 0);
 278         intel_ring_emit(ring, 0);
 279         intel_ring_advance(ring);
 280
 281         return 0;
 282 }
 283
 284 static int
 285 gen7_render_ring_flush(struct drm_i915_gem_request *req, u32 mode)
 286 {
 287         struct intel_ring *ring = req->ring;
 288         u32 scratch_addr =
 289                 i915_ggtt_offset(req->engine->scratch) + 2 * CACHELINE_BYTES;
 290         u32 flags = 0;
 291         int ret;
 292
 293         /*
 294          * Ensure that any following seqno writes only happen when the render
 295          * cache is indeed flushed.
 296          *
 297          * Workaround: 4th PIPE_CONTROL command (except the ones with only
 298          * read-cache invalidate bits set) must have the CS_STALL bit set. We
 299          * don't try to be clever and just set it unconditionally.
 300          */
 301         flags |= PIPE_CONTROL_CS_STALL;
 302
 303         /* Just flush everything.  Experiments have shown that reducing the
 304          * number of bits based on the write domains has little performance
 305          * impact.
 306          */
 307         if (mode & EMIT_FLUSH) {
 308                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 309                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 310                 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
 311                 flags |= PIPE_CONTROL_FLUSH_ENABLE;
 312         }
 313         if (mode & EMIT_INVALIDATE) {
 314                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 315                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 316                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 317                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 318                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 319                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 320                 flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
 321                 /*
 322                  * TLB invalidate requires a post-sync write.
 323                  */
 324                 flags |= PIPE_CONTROL_QW_WRITE;
 325                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 326
 327                 flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
 328
 329                 /* Workaround: we must issue a pipe_control with CS-stall bit
 330                  * set before a pipe_control command that has the state cache
 331                  * invalidate bit set. */
 332                 gen7_render_ring_cs_stall_wa(req);
 333         }
 334
 335         ret = intel_ring_begin(req, 4);
 336         if (ret)
 337                 return ret;
 338
 339         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 340         intel_ring_emit(ring, flags);
 341         intel_ring_emit(ring, scratch_addr);
 342         intel_ring_emit(ring, 0);
 343         intel_ring_advance(ring);
 344
 345         return 0;
 346 }
 347
 348 static int
 349 gen8_emit_pipe_control(struct drm_i915_gem_request *req,
 350                        u32 flags, u32 scratch_addr)
 351 {
 352         struct intel_ring *ring = req->ring;
 353         int ret;
 354
 355         ret = intel_ring_begin(req, 6);
 356         if (ret)
 357                 return ret;
 358
 359         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
 360         intel_ring_emit(ring, flags);
 361         intel_ring_emit(ring, scratch_addr);
 362         intel_ring_emit(ring, 0);
 363         intel_ring_emit(ring, 0);
 364         intel_ring_emit(ring, 0);
 365         intel_ring_advance(ring);
 366
 367         return 0;
 368 }
 369
 370 static int
 371 gen8_render_ring_flush(struct drm_i915_gem_request *req, u32 mode)
 372 {
 373         u32 scratch_addr =
 374                 i915_ggtt_offset(req->engine->scratch) + 2 * CACHELINE_BYTES;
 375         u32 flags = 0;
 376         int ret;
 377
 378         flags |= PIPE_CONTROL_CS_STALL;
 379
 380         if (mode & EMIT_FLUSH) {
 381                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 382                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 383                 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
 384                 flags |= PIPE_CONTROL_FLUSH_ENABLE;
 385         }
 386         if (mode & EMIT_INVALIDATE) {
 387                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 388                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 389                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 390                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 391                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 392                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 393                 flags |= PIPE_CONTROL_QW_WRITE;
 394                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 395
 396                 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
 397                 ret = gen8_emit_pipe_control(req,
 398                                              PIPE_CONTROL_CS_STALL |
 399                                              PIPE_CONTROL_STALL_AT_SCOREBOARD,
 400                                              0);
 401                 if (ret)
 402                         return ret;
 403         }
 404
 405         return gen8_emit_pipe_control(req, flags, scratch_addr);
 406 }
 407
 408 u64 intel_engine_get_active_head(struct intel_engine_cs *engine)
 409 {
 410         struct drm_i915_private *dev_priv = engine->i915;
 411         u64 acthd;
 412
 413         if (INTEL_GEN(dev_priv) >= 8)
 414                 acthd = I915_READ64_2x32(RING_ACTHD(engine->mmio_base),
 415                                          RING_ACTHD_UDW(engine->mmio_base));
 416         else if (INTEL_GEN(dev_priv) >= 4)
 417                 acthd = I915_READ(RING_ACTHD(engine->mmio_base));
 418         else
 419                 acthd = I915_READ(ACTHD);
 420
 421         return acthd;
 422 }
 423
 424 static void ring_setup_phys_status_page(struct intel_engine_cs *engine)
 425 {
 426         struct drm_i915_private *dev_priv = engine->i915;
 427         u32 addr;
 428
 429         addr = dev_priv->status_page_dmah->busaddr;
 430         if (INTEL_GEN(dev_priv) >= 4)
 431                 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
 432         I915_WRITE(HWS_PGA, addr);
 433 }
 434
 435 static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
 436 {
 437         struct drm_i915_private *dev_priv = engine->i915;
 438         i915_reg_t mmio;
 439
 440         /* The ring status page addresses are no longer next to the rest of
 441          * the ring registers as of gen7.
 442          */
 443         if (IS_GEN7(dev_priv)) {
 444                 switch (engine->id) {
 445                 case RCS:
 446                         mmio = RENDER_HWS_PGA_GEN7;
 447                         break;
 448                 case BCS:
 449                         mmio = BLT_HWS_PGA_GEN7;
 450                         break;
 451                 /*
 452                  * VCS2 actually doesn't exist on Gen7. Only shut up
 453                  * gcc switch check warning
 454                  */
 455                 case VCS2:
 456                 case VCS:
 457                         mmio = BSD_HWS_PGA_GEN7;
 458                         break;
 459                 case VECS:
 460                         mmio = VEBOX_HWS_PGA_GEN7;
 461                         break;
 462                 }
 463         } else if (IS_GEN6(dev_priv)) {
 464                 mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
 465         } else {
 466                 /* XXX: gen8 returns to sanity */
 467                 mmio = RING_HWS_PGA(engine->mmio_base);
 468         }
 469
 470         I915_WRITE(mmio, engine->status_page.ggtt_offset);
 471         POSTING_READ(mmio);
 472
 473         /*
 474          * Flush the TLB for this page
 475          *
 476          * FIXME: These two bits have disappeared on gen8, so a question
 477          * arises: do we still need this and if so how should we go about
 478          * invalidating the TLB?
 479          */
 480         if (IS_GEN(dev_priv, 6, 7)) {
 481                 i915_reg_t reg = RING_INSTPM(engine->mmio_base);
 482
 483                 /* ring should be idle before issuing a sync flush*/
 484                 WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0);
 485
 486                 I915_WRITE(reg,
 487                            _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
 488                                               INSTPM_SYNC_FLUSH));
 489                 if (intel_wait_for_register(dev_priv,
 490                                             reg, INSTPM_SYNC_FLUSH, 0,
 491                                             1000))
 492                         DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
 493                                   engine->name);
 494         }
 495 }
 496
 497 static bool stop_ring(struct intel_engine_cs *engine)
 498 {
 499         struct drm_i915_private *dev_priv = engine->i915;
 500
 501         if (INTEL_GEN(dev_priv) > 2) {
 502                 I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING));
 503                 if (intel_wait_for_register(dev_priv,
 504                                             RING_MI_MODE(engine->mmio_base),
 505                                             MODE_IDLE,
 506                                             MODE_IDLE,
 507                                             1000)) {
 508                         DRM_ERROR("%s : timed out trying to stop ring\n",
 509                                   engine->name);
 510                         /* Sometimes we observe that the idle flag is not
 511                          * set even though the ring is empty. So double
 512                          * check before giving up.
 513                          */
 514                         if (I915_READ_HEAD(engine) != I915_READ_TAIL(engine))
 515                                 return false;
 516                 }
 517         }
 518
 519         I915_WRITE_CTL(engine, 0);
 520         I915_WRITE_HEAD(engine, 0);
 521         I915_WRITE_TAIL(engine, 0);
 522
 523         if (INTEL_GEN(dev_priv) > 2) {
 524                 (void)I915_READ_CTL(engine);
 525                 I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING));
 526         }
 527
 528         return (I915_READ_HEAD(engine) & HEAD_ADDR) == 0;
 529 }
 530
 531 static int init_ring_common(struct intel_engine_cs *engine)
 532 {
 533         struct drm_i915_private *dev_priv = engine->i915;
 534         struct intel_ring *ring = engine->buffer;
 535         int ret = 0;
 536
 537         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
 538
 539         if (!stop_ring(engine)) {
 540                 /* G45 ring initialization often fails to reset head to zero */
 541                 DRM_DEBUG_KMS("%s head not reset to zero "
 542                               "ctl %08x head %08x tail %08x start %08x\n",
 543                               engine->name,
 544                               I915_READ_CTL(engine),
 545                               I915_READ_HEAD(engine),
 546                               I915_READ_TAIL(engine),
 547                               I915_READ_START(engine));
 548
 549                 if (!stop_ring(engine)) {
 550                         DRM_ERROR("failed to set %s head to zero "
 551                                   "ctl %08x head %08x tail %08x start %08x\n",
 552                                   engine->name,
 553                                   I915_READ_CTL(engine),
 554                                   I915_READ_HEAD(engine),
 555                                   I915_READ_TAIL(engine),
 556                                   I915_READ_START(engine));
 557                         ret = -EIO;
 558                         goto out;
 559                 }
 560         }
 561
 562         if (I915_NEED_GFX_HWS(dev_priv))
 563                 intel_ring_setup_status_page(engine);
 564         else
 565                 ring_setup_phys_status_page(engine);
 566
 567         /* Enforce ordering by reading HEAD register back */
 568         I915_READ_HEAD(engine);
 569
 570         /* Initialize the ring. This must happen _after_ we've cleared the ring
 571          * registers with the above sequence (the readback of the HEAD registers
 572          * also enforces ordering), otherwise the hw might lose the new ring
 573          * register values. */
 574         I915_WRITE_START(engine, i915_ggtt_offset(ring->vma));
 575
 576         /* WaClearRingBufHeadRegAtInit:ctg,elk */
 577         if (I915_READ_HEAD(engine))
 578                 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
 579                           engine->name, I915_READ_HEAD(engine));
 580         I915_WRITE_HEAD(engine, 0);
 581         (void)I915_READ_HEAD(engine);
 582
 583         I915_WRITE_CTL(engine,
 584                         ((ring->size - PAGE_SIZE) & RING_NR_PAGES)
 585                         | RING_VALID);
 586
 587         /* If the head is still not zero, the ring is dead */
 588         if (wait_for((I915_READ_CTL(engine) & RING_VALID) != 0 &&
 589                      I915_READ_START(engine) == i915_ggtt_offset(ring->vma) &&
 590                      (I915_READ_HEAD(engine) & HEAD_ADDR) == 0, 50)) {
 591                 DRM_ERROR("%s initialization failed "
 592                           "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08x]\n",
 593                           engine->name,
 594                           I915_READ_CTL(engine),
 595                           I915_READ_CTL(engine) & RING_VALID,
 596                           I915_READ_HEAD(engine), I915_READ_TAIL(engine),
 597                           I915_READ_START(engine),
 598                           i915_ggtt_offset(ring->vma));
 599                 ret = -EIO;
 600                 goto out;
 601         }
 602
 603         ring->last_retired_head = -1;
 604         ring->head = I915_READ_HEAD(engine);
 605         ring->tail = I915_READ_TAIL(engine) & TAIL_ADDR;
 606         intel_ring_update_space(ring);
 607
 608         intel_engine_init_hangcheck(engine);
 609
 610 out:
 611         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
 612
 613         return ret;
 614 }
 615
 616 static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req)
 617 {
 618         struct intel_ring *ring = req->ring;
 619         struct i915_workarounds *w = &req->i915->workarounds;
 620         int ret, i;
 621
 622         if (w->count == 0)
 623                 return 0;
 624
 625         ret = req->engine->emit_flush(req, EMIT_BARRIER);
 626         if (ret)
 627                 return ret;
 628
 629         ret = intel_ring_begin(req, (w->count * 2 + 2));
 630         if (ret)
 631                 return ret;
 632
 633         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count));
 634         for (i = 0; i < w->count; i++) {
 635                 intel_ring_emit_reg(ring, w->reg[i].addr);
 636                 intel_ring_emit(ring, w->reg[i].value);
 637         }
 638         intel_ring_emit(ring, MI_NOOP);
 639
 640         intel_ring_advance(ring);
 641
 642         ret = req->engine->emit_flush(req, EMIT_BARRIER);
 643         if (ret)
 644                 return ret;
 645
 646         DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count);
 647
 648         return 0;
 649 }
 650
 651 static int intel_rcs_ctx_init(struct drm_i915_gem_request *req)
 652 {
 653         int ret;
 654
 655         ret = intel_ring_workarounds_emit(req);
 656         if (ret != 0)
 657                 return ret;
 658
 659         ret = i915_gem_render_state_init(req);
 660         if (ret)
 661                 return ret;
 662
 663         return 0;
 664 }
 665
 666 static int wa_add(struct drm_i915_private *dev_priv,
 667                   i915_reg_t addr,
 668                   const u32 mask, const u32 val)
 669 {
 670         const u32 idx = dev_priv->workarounds.count;
 671
 672         if (WARN_ON(idx >= I915_MAX_WA_REGS))
 673                 return -ENOSPC;
 674
 675         dev_priv->workarounds.reg[idx].addr = addr;
 676         dev_priv->workarounds.reg[idx].value = val;
 677         dev_priv->workarounds.reg[idx].mask = mask;
 678
 679         dev_priv->workarounds.count++;
 680
 681         return 0;
 682 }
 683
 684 #define WA_REG(addr, mask, val) do { \
 685                 const int r = wa_add(dev_priv, (addr), (mask), (val)); \
 686                 if (r) \
 687                         return r; \
 688         } while (0)
 689
 690 #define WA_SET_BIT_MASKED(addr, mask) \
 691         WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
 692
 693 #define WA_CLR_BIT_MASKED(addr, mask) \
 694         WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
 695
 696 #define WA_SET_FIELD_MASKED(addr, mask, value) \
 697         WA_REG(addr, mask, _MASKED_FIELD(mask, value))
 698
 699 #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
 700 #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
 701
 702 #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
 703
 704 static int wa_ring_whitelist_reg(struct intel_engine_cs *engine,
 705                                  i915_reg_t reg)
 706 {
 707         struct drm_i915_private *dev_priv = engine->i915;
 708         struct i915_workarounds *wa = &dev_priv->workarounds;
 709         const uint32_t index = wa->hw_whitelist_count[engine->id];
 710
 711         if (WARN_ON(index >= RING_MAX_NONPRIV_SLOTS))
 712                 return -EINVAL;
 713
 714         WA_WRITE(RING_FORCE_TO_NONPRIV(engine->mmio_base, index),
 715                  i915_mmio_reg_offset(reg));
 716         wa->hw_whitelist_count[engine->id]++;
 717
 718         return 0;
 719 }
 720
 721 static int gen8_init_workarounds(struct intel_engine_cs *engine)
 722 {
 723         struct drm_i915_private *dev_priv = engine->i915;
 724
 725         WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
 726
 727         /* WaDisableAsyncFlipPerfMode:bdw,chv */
 728         WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
 729
 730         /* WaDisablePartialInstShootdown:bdw,chv */
 731         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 732                           PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
 733
 734         /* Use Force Non-Coherent whenever executing a 3D context. This is a
 735          * workaround for for a possible hang in the unlikely event a TLB
 736          * invalidation occurs during a PSD flush.
 737          */
 738         /* WaForceEnableNonCoherent:bdw,chv */
 739         /* WaHdcDisableFetchWhenMasked:bdw,chv */
 740         WA_SET_BIT_MASKED(HDC_CHICKEN0,
 741                           HDC_DONOT_FETCH_MEM_WHEN_MASKED |
 742                           HDC_FORCE_NON_COHERENT);
 743
 744         /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
 745          * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
 746          *  polygons in the same 8x4 pixel/sample area to be processed without
 747          *  stalling waiting for the earlier ones to write to Hierarchical Z
 748          *  buffer."
 749          *
 750          * This optimization is off by default for BDW and CHV; turn it on.
 751          */
 752         WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
 753
 754         /* Wa4x4STCOptimizationDisable:bdw,chv */
 755         WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
 756
 757         /*
 758          * BSpec recommends 8x4 when MSAA is used,
 759          * however in practice 16x4 seems fastest.
 760          *
 761          * Note that PS/WM thread counts depend on the WIZ hashing
 762          * disable bit, which we don't touch here, but it's good
 763          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
 764          */
 765         WA_SET_FIELD_MASKED(GEN7_GT_MODE,
 766                             GEN6_WIZ_HASHING_MASK,
 767                             GEN6_WIZ_HASHING_16x4);
 768
 769         return 0;
 770 }
 771
 772 static int bdw_init_workarounds(struct intel_engine_cs *engine)
 773 {
 774         struct drm_i915_private *dev_priv = engine->i915;
 775         int ret;
 776
 777         ret = gen8_init_workarounds(engine);
 778         if (ret)
 779                 return ret;
 780
 781         /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
 782         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
 783
 784         /* WaDisableDopClockGating:bdw */
 785         WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
 786                           DOP_CLOCK_GATING_DISABLE);
 787
 788         WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
 789                           GEN8_SAMPLER_POWER_BYPASS_DIS);
 790
 791         WA_SET_BIT_MASKED(HDC_CHICKEN0,
 792                           /* WaForceContextSaveRestoreNonCoherent:bdw */
 793                           HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
 794                           /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
 795                           (IS_BDW_GT3(dev_priv) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
 796
 797         return 0;
 798 }
 799
 800 static int chv_init_workarounds(struct intel_engine_cs *engine)
 801 {
 802         struct drm_i915_private *dev_priv = engine->i915;
 803         int ret;
 804
 805         ret = gen8_init_workarounds(engine);
 806         if (ret)
 807                 return ret;
 808
 809         /* WaDisableThreadStallDopClockGating:chv */
 810         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
 811
 812         /* Improve HiZ throughput on CHV. */
 813         WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
 814
 815         return 0;
 816 }
 817
 818 static int gen9_init_workarounds(struct intel_engine_cs *engine)
 819 {
 820         struct drm_i915_private *dev_priv = engine->i915;
 821         int ret;
 822
 823         /* WaConextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl */
 824         I915_WRITE(GEN9_CSFE_CHICKEN1_RCS, _MASKED_BIT_ENABLE(GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE));
 825
 826         /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl */
 827         I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
 828                    GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
 829
 830         /* WaDisableKillLogic:bxt,skl,kbl */
 831         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
 832                    ECOCHK_DIS_TLB);
 833
 834         /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl */
 835         /* WaDisablePartialInstShootdown:skl,bxt,kbl */
 836         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 837                           FLOW_CONTROL_ENABLE |
 838                           PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
 839
 840         /* Syncing dependencies between camera and graphics:skl,bxt,kbl */
 841         WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
 842                           GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
 843
 844         /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */
 845         if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_B0) ||
 846             IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
 847                 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
 848                                   GEN9_DG_MIRROR_FIX_ENABLE);
 849
 850         /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
 851         if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_B0) ||
 852             IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
 853                 WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
 854                                   GEN9_RHWO_OPTIMIZATION_DISABLE);
 855                 /*
 856                  * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set
 857                  * but we do that in per ctx batchbuffer as there is an issue
 858                  * with this register not getting restored on ctx restore
 859                  */
 860         }
 861
 862         /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl */
 863         /* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl */
 864         WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
 865                           GEN9_ENABLE_YV12_BUGFIX |
 866                           GEN9_ENABLE_GPGPU_PREEMPTION);
 867
 868         /* Wa4x4STCOptimizationDisable:skl,bxt,kbl */
 869         /* WaDisablePartialResolveInVc:skl,bxt,kbl */
 870         WA_SET_BIT_MASKED(CACHE_MODE_1, (GEN8_4x4_STC_OPTIMIZATION_DISABLE |
 871                                          GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE));
 872
 873         /* WaCcsTlbPrefetchDisable:skl,bxt,kbl */
 874         WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
 875                           GEN9_CCS_TLB_PREFETCH_ENABLE);
 876
 877         /* WaDisableMaskBasedCammingInRCC:skl,bxt */
 878         if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, SKL_REVID_C0) ||
 879             IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
 880                 WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
 881                                   PIXEL_MASK_CAMMING_DISABLE);
 882
 883         /* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl */
 884         WA_SET_BIT_MASKED(HDC_CHICKEN0,
 885                           HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
 886                           HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE);
 887
 888         /* WaForceEnableNonCoherent and WaDisableHDCInvalidation are
 889          * both tied to WaForceContextSaveRestoreNonCoherent
 890          * in some hsds for skl. We keep the tie for all gen9. The
 891          * documentation is a bit hazy and so we want to get common behaviour,
 892          * even though there is no clear evidence we would need both on kbl/bxt.
 893          * This area has been source of system hangs so we play it safe
 894          * and mimic the skl regardless of what bspec says.
 895          *
 896          * Use Force Non-Coherent whenever executing a 3D context. This
 897          * is a workaround for a possible hang in the unlikely event
 898          * a TLB invalidation occurs during a PSD flush.
 899          */
 900
 901         /* WaForceEnableNonCoherent:skl,bxt,kbl */
 902         WA_SET_BIT_MASKED(HDC_CHICKEN0,
 903                           HDC_FORCE_NON_COHERENT);
 904
 905         /* WaDisableHDCInvalidation:skl,bxt,kbl */
 906         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
 907                    BDW_DISABLE_HDC_INVALIDATION);
 908
 909         /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl */
 910         if (IS_SKYLAKE(dev_priv) ||
 911             IS_KABYLAKE(dev_priv) ||
 912             IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0))
 913                 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
 914                                   GEN8_SAMPLER_POWER_BYPASS_DIS);
 915
 916         /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl */
 917         WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
 918
 919         /* WaOCLCoherentLineFlush:skl,bxt,kbl */
 920         I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
 921                                     GEN8_LQSC_FLUSH_COHERENT_LINES));
 922
 923         /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt */
 924         ret = wa_ring_whitelist_reg(engine, GEN9_CTX_PREEMPT_REG);
 925         if (ret)
 926                 return ret;
 927
 928         /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl */
 929         ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1);
 930         if (ret)
 931                 return ret;
 932
 933         /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl */
 934         ret = wa_ring_whitelist_reg(engine, GEN8_HDC_CHICKEN1);
 935         if (ret)
 936                 return ret;
 937
 938         return 0;
 939 }
 940
 941 static int skl_tune_iz_hashing(struct intel_engine_cs *engine)
 942 {
 943         struct drm_i915_private *dev_priv = engine->i915;
 944         u8 vals[3] = { 0, 0, 0 };
 945         unsigned int i;
 946
 947         for (i = 0; i < 3; i++) {
 948                 u8 ss;
 949
 950                 /*
 951                  * Only consider slices where one, and only one, subslice has 7
 952                  * EUs
 953                  */
 954                 if (!is_power_of_2(dev_priv->info.subslice_7eu[i]))
 955                         continue;
 956
 957                 /*
 958                  * subslice_7eu[i] != 0 (because of the check above) and
 959                  * ss_max == 4 (maximum number of subslices possible per slice)
 960                  *
 961                  * ->    0 <= ss <= 3;
 962                  */
 963                 ss = ffs(dev_priv->info.subslice_7eu[i]) - 1;
 964                 vals[i] = 3 - ss;
 965         }
 966
 967         if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0)
 968                 return 0;
 969
 970         /* Tune IZ hashing. See intel_device_info_runtime_init() */
 971         WA_SET_FIELD_MASKED(GEN7_GT_MODE,
 972                             GEN9_IZ_HASHING_MASK(2) |
 973                             GEN9_IZ_HASHING_MASK(1) |
 974                             GEN9_IZ_HASHING_MASK(0),
 975                             GEN9_IZ_HASHING(2, vals[2]) |
 976                             GEN9_IZ_HASHING(1, vals[1]) |
 977                             GEN9_IZ_HASHING(0, vals[0]));
 978
 979         return 0;
 980 }
 981
 982 static int skl_init_workarounds(struct intel_engine_cs *engine)
 983 {
 984         struct drm_i915_private *dev_priv = engine->i915;
 985         int ret;
 986
 987         ret = gen9_init_workarounds(engine);
 988         if (ret)
 989                 return ret;
 990
 991         /*
 992          * Actual WA is to disable percontext preemption granularity control
 993          * until D0 which is the default case so this is equivalent to
 994          * !WaDisablePerCtxtPreemptionGranularityControl:skl
 995          */
 996         if (IS_SKL_REVID(dev_priv, SKL_REVID_E0, REVID_FOREVER)) {
 997                 I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1,
 998                            _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL));
 999         }
1000
1001         if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_E0)) {
1002                 /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
1003                 I915_WRITE(FF_SLICE_CS_CHICKEN2,
1004                            _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE));
1005         }
1006
1007         /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes
1008          * involving this register should also be added to WA batch as required.
1009          */
1010         if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_E0))
1011                 /* WaDisableLSQCROPERFforOCL:skl */
1012                 I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
1013                            GEN8_LQSC_RO_PERF_DIS);
1014
1015         /* WaEnableGapsTsvCreditFix:skl */
1016         if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, REVID_FOREVER)) {
1017                 I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
1018                                            GEN9_GAPS_TSV_CREDIT_DISABLE));
1019         }
1020
1021         /* WaDisablePowerCompilerClockGating:skl */
1022         if (IS_SKL_REVID(dev_priv, SKL_REVID_B0, SKL_REVID_B0))
1023                 WA_SET_BIT_MASKED(HIZ_CHICKEN,
1024                                   BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
1025
1026         /* WaBarrierPerformanceFixDisable:skl */
1027         if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, SKL_REVID_D0))
1028                 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1029                                   HDC_FENCE_DEST_SLM_DISABLE |
1030                                   HDC_BARRIER_PERFORMANCE_DISABLE);
1031
1032         /* WaDisableSbeCacheDispatchPortSharing:skl */
1033         if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0))
1034                 WA_SET_BIT_MASKED(
1035                         GEN7_HALF_SLICE_CHICKEN1,
1036                         GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1037
1038         /* WaDisableGafsUnitClkGating:skl */
1039         WA_SET_BIT(GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
1040
1041         /* WaInPlaceDecompressionHang:skl */
1042         if (IS_SKL_REVID(dev_priv, SKL_REVID_H0, REVID_FOREVER))
1043                 WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA,
1044                            GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
1045
1046         /* WaDisableLSQCROPERFforOCL:skl */
1047         ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
1048         if (ret)
1049                 return ret;
1050
1051         return skl_tune_iz_hashing(engine);
1052 }
1053
1054 static int bxt_init_workarounds(struct intel_engine_cs *engine)
1055 {
1056         struct drm_i915_private *dev_priv = engine->i915;
1057         int ret;
1058
1059         ret = gen9_init_workarounds(engine);
1060         if (ret)
1061                 return ret;
1062
1063         /* WaStoreMultiplePTEenable:bxt */
1064         /* This is a requirement according to Hardware specification */
1065         if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
1066                 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
1067
1068         /* WaSetClckGatingDisableMedia:bxt */
1069         if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
1070                 I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) &
1071                                             ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE));
1072         }
1073
1074         /* WaDisableThreadStallDopClockGating:bxt */
1075         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
1076                           STALL_DOP_GATING_DISABLE);
1077
1078         /* WaDisablePooledEuLoadBalancingFix:bxt */
1079         if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER)) {
1080                 WA_SET_BIT_MASKED(FF_SLICE_CS_CHICKEN2,
1081                                   GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE);
1082         }
1083
1084         /* WaDisableSbeCacheDispatchPortSharing:bxt */
1085         if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0)) {
1086                 WA_SET_BIT_MASKED(
1087                         GEN7_HALF_SLICE_CHICKEN1,
1088                         GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1089         }
1090
1091         /* WaDisableObjectLevelPreemptionForTrifanOrPolygon:bxt */
1092         /* WaDisableObjectLevelPreemptionForInstancedDraw:bxt */
1093         /* WaDisableObjectLevelPreemtionForInstanceId:bxt */
1094         /* WaDisableLSQCROPERFforOCL:bxt */
1095         if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
1096                 ret = wa_ring_whitelist_reg(engine, GEN9_CS_DEBUG_MODE1);
1097                 if (ret)
1098                         return ret;
1099
1100                 ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
1101                 if (ret)
1102                         return ret;
1103         }
1104
1105         /* WaProgramL3SqcReg1DefaultForPerf:bxt */
1106         if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
1107                 I915_WRITE(GEN8_L3SQCREG1, L3_GENERAL_PRIO_CREDITS(62) |
1108                                            L3_HIGH_PRIO_CREDITS(2));
1109
1110         /* WaToEnableHwFixForPushConstHWBug:bxt */
1111         if (IS_BXT_REVID(dev_priv, BXT_REVID_C0, REVID_FOREVER))
1112                 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
1113                                   GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
1114
1115         /* WaInPlaceDecompressionHang:bxt */
1116         if (IS_BXT_REVID(dev_priv, BXT_REVID_C0, REVID_FOREVER))
1117                 WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA,
1118                            GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
1119
1120         return 0;
1121 }
1122
1123 static int kbl_init_workarounds(struct intel_engine_cs *engine)
1124 {
1125         struct drm_i915_private *dev_priv = engine->i915;
1126         int ret;
1127
1128         ret = gen9_init_workarounds(engine);
1129         if (ret)
1130                 return ret;
1131
1132         /* WaEnableGapsTsvCreditFix:kbl */
1133         I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
1134                                    GEN9_GAPS_TSV_CREDIT_DISABLE));
1135
1136         /* WaDisableDynamicCreditSharing:kbl */
1137         if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
1138                 WA_SET_BIT(GAMT_CHKN_BIT_REG,
1139                            GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING);
1140
1141         /* WaDisableFenceDestinationToSLM:kbl (pre-prod) */
1142         if (IS_KBL_REVID(dev_priv, KBL_REVID_A0, KBL_REVID_A0))
1143                 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1144                                   HDC_FENCE_DEST_SLM_DISABLE);
1145
1146         /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes
1147          * involving this register should also be added to WA batch as required.
1148          */
1149         if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_E0))
1150                 /* WaDisableLSQCROPERFforOCL:kbl */
1151                 I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
1152                            GEN8_LQSC_RO_PERF_DIS);
1153
1154         /* WaToEnableHwFixForPushConstHWBug:kbl */
1155         if (IS_KBL_REVID(dev_priv, KBL_REVID_C0, REVID_FOREVER))
1156                 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
1157                                   GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
1158
1159         /* WaDisableGafsUnitClkGating:kbl */
1160         WA_SET_BIT(GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
1161
1162         /* WaDisableSbeCacheDispatchPortSharing:kbl */
1163         WA_SET_BIT_MASKED(
1164                 GEN7_HALF_SLICE_CHICKEN1,
1165                 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1166
1167         /* WaInPlaceDecompressionHang:kbl */
1168         WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA,
1169                    GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
1170
1171         /* WaDisableLSQCROPERFforOCL:kbl */
1172         ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
1173         if (ret)
1174                 return ret;
1175
1176         return 0;
1177 }
1178
1179 int init_workarounds_ring(struct intel_engine_cs *engine)
1180 {
1181         struct drm_i915_private *dev_priv = engine->i915;
1182
1183         WARN_ON(engine->id != RCS);
1184
1185         dev_priv->workarounds.count = 0;
1186         dev_priv->workarounds.hw_whitelist_count[RCS] = 0;
1187
1188         if (IS_BROADWELL(dev_priv))
1189                 return bdw_init_workarounds(engine);
1190
1191         if (IS_CHERRYVIEW(dev_priv))
1192                 return chv_init_workarounds(engine);
1193
1194         if (IS_SKYLAKE(dev_priv))
1195                 return skl_init_workarounds(engine);
1196
1197         if (IS_BROXTON(dev_priv))
1198                 return bxt_init_workarounds(engine);
1199
1200         if (IS_KABYLAKE(dev_priv))
1201                 return kbl_init_workarounds(engine);
1202
1203         return 0;
1204 }
1205
1206 static int init_render_ring(struct intel_engine_cs *engine)
1207 {
1208         struct drm_i915_private *dev_priv = engine->i915;
1209         int ret = init_ring_common(engine);
1210         if (ret)
1211                 return ret;
1212
1213         /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
1214         if (IS_GEN(dev_priv, 4, 6))
1215                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
1216
1217         /* We need to disable the AsyncFlip performance optimisations in order
1218          * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1219          * programmed to '1' on all products.
1220          *
1221          * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
1222          */
1223         if (IS_GEN(dev_priv, 6, 7))
1224                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1225
1226         /* Required for the hardware to program scanline values for waiting */
1227         /* WaEnableFlushTlbInvalidationMode:snb */
1228         if (IS_GEN6(dev_priv))
1229                 I915_WRITE(GFX_MODE,
1230                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
1231
1232         /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
1233         if (IS_GEN7(dev_priv))
1234                 I915_WRITE(GFX_MODE_GEN7,
1235                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
1236                            _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
1237
1238         if (IS_GEN6(dev_priv)) {
1239                 /* From the Sandybridge PRM, volume 1 part 3, page 24:
1240                  * "If this bit is set, STCunit will have LRA as replacement
1241                  *  policy. [...] This bit must be reset.  LRA replacement
1242                  *  policy is not supported."
1243                  */
1244                 I915_WRITE(CACHE_MODE_0,
1245                            _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
1246         }
1247
1248         if (IS_GEN(dev_priv, 6, 7))
1249                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
1250
1251         if (INTEL_INFO(dev_priv)->gen >= 6)
1252                 I915_WRITE_IMR(engine, ~engine->irq_keep_mask);
1253
1254         return init_workarounds_ring(engine);
1255 }
1256
1257 static void render_ring_cleanup(struct intel_engine_cs *engine)
1258 {
1259         struct drm_i915_private *dev_priv = engine->i915;
1260
1261         i915_vma_unpin_and_release(&dev_priv->semaphore);
1262 }
1263
1264 static int gen8_rcs_signal(struct drm_i915_gem_request *req)
1265 {
1266         struct intel_ring *ring = req->ring;
1267         struct drm_i915_private *dev_priv = req->i915;
1268         struct intel_engine_cs *waiter;
1269         enum intel_engine_id id;
1270         int ret, num_rings;
1271
1272         num_rings = INTEL_INFO(dev_priv)->num_rings;
1273         ret = intel_ring_begin(req, (num_rings-1) * 8);
1274         if (ret)
1275                 return ret;
1276
1277         for_each_engine_id(waiter, dev_priv, id) {
1278                 u64 gtt_offset = req->engine->semaphore.signal_ggtt[id];
1279                 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1280                         continue;
1281
1282                 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
1283                 intel_ring_emit(ring,
1284                                 PIPE_CONTROL_GLOBAL_GTT_IVB |
1285                                 PIPE_CONTROL_QW_WRITE |
1286                                 PIPE_CONTROL_CS_STALL);
1287                 intel_ring_emit(ring, lower_32_bits(gtt_offset));
1288                 intel_ring_emit(ring, upper_32_bits(gtt_offset));
1289                 intel_ring_emit(ring, req->fence.seqno);
1290                 intel_ring_emit(ring, 0);
1291                 intel_ring_emit(ring,
1292                                 MI_SEMAPHORE_SIGNAL |
1293                                 MI_SEMAPHORE_TARGET(waiter->hw_id));
1294                 intel_ring_emit(ring, 0);
1295         }
1296         intel_ring_advance(ring);
1297
1298         return 0;
1299 }
1300
1301 static int gen8_xcs_signal(struct drm_i915_gem_request *req)
1302 {
1303         struct intel_ring *ring = req->ring;
1304         struct drm_i915_private *dev_priv = req->i915;
1305         struct intel_engine_cs *waiter;
1306         enum intel_engine_id id;
1307         int ret, num_rings;
1308
1309         num_rings = INTEL_INFO(dev_priv)->num_rings;
1310         ret = intel_ring_begin(req, (num_rings-1) * 6);
1311         if (ret)
1312                 return ret;
1313
1314         for_each_engine_id(waiter, dev_priv, id) {
1315                 u64 gtt_offset = req->engine->semaphore.signal_ggtt[id];
1316                 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1317                         continue;
1318
1319                 intel_ring_emit(ring,
1320                                 (MI_FLUSH_DW + 1) | MI_FLUSH_DW_OP_STOREDW);
1321                 intel_ring_emit(ring,
1322                                 lower_32_bits(gtt_offset) |
1323                                 MI_FLUSH_DW_USE_GTT);
1324                 intel_ring_emit(ring, upper_32_bits(gtt_offset));
1325                 intel_ring_emit(ring, req->fence.seqno);
1326                 intel_ring_emit(ring,
1327                                 MI_SEMAPHORE_SIGNAL |
1328                                 MI_SEMAPHORE_TARGET(waiter->hw_id));
1329                 intel_ring_emit(ring, 0);
1330         }
1331         intel_ring_advance(ring);
1332
1333         return 0;
1334 }
1335
1336 static int gen6_signal(struct drm_i915_gem_request *req)
1337 {
1338         struct intel_ring *ring = req->ring;
1339         struct drm_i915_private *dev_priv = req->i915;
1340         struct intel_engine_cs *engine;
1341         int ret, num_rings;
1342
1343         num_rings = INTEL_INFO(dev_priv)->num_rings;
1344         ret = intel_ring_begin(req, round_up((num_rings-1) * 3, 2));
1345         if (ret)
1346                 return ret;
1347
1348         for_each_engine(engine, dev_priv) {
1349                 i915_reg_t mbox_reg;
1350
1351                 if (!(BIT(engine->hw_id) & GEN6_SEMAPHORES_MASK))
1352                         continue;
1353
1354                 mbox_reg = req->engine->semaphore.mbox.signal[engine->hw_id];
1355                 if (i915_mmio_reg_valid(mbox_reg)) {
1356                         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
1357                         intel_ring_emit_reg(ring, mbox_reg);
1358                         intel_ring_emit(ring, req->fence.seqno);
1359                 }
1360         }
1361
1362         /* If num_dwords was rounded, make sure the tail pointer is correct */
1363         if (num_rings % 2 == 0)
1364                 intel_ring_emit(ring, MI_NOOP);
1365         intel_ring_advance(ring);
1366
1367         return 0;
1368 }
1369
1370 static void i9xx_submit_request(struct drm_i915_gem_request *request)
1371 {
1372         struct drm_i915_private *dev_priv = request->i915;
1373
1374         I915_WRITE_TAIL(request->engine,
1375                         intel_ring_offset(request->ring, request->tail));
1376 }
1377
1378 static int i9xx_emit_request(struct drm_i915_gem_request *req)
1379 {
1380         struct intel_ring *ring = req->ring;
1381         int ret;
1382
1383         ret = intel_ring_begin(req, 4);
1384         if (ret)
1385                 return ret;
1386
1387         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1388         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1389         intel_ring_emit(ring, req->fence.seqno);
1390         intel_ring_emit(ring, MI_USER_INTERRUPT);
1391         intel_ring_advance(ring);
1392
1393         req->tail = ring->tail;
1394
1395         return 0;
1396 }
1397
1398 /**
1399  * gen6_sema_emit_request - Update the semaphore mailbox registers
1400  *
1401  * @request - request to write to the ring
1402  *
1403  * Update the mailbox registers in the *other* rings with the current seqno.
1404  * This acts like a signal in the canonical semaphore.
1405  */
1406 static int gen6_sema_emit_request(struct drm_i915_gem_request *req)
1407 {
1408         int ret;
1409
1410         ret = req->engine->semaphore.signal(req);
1411         if (ret)
1412                 return ret;
1413
1414         return i9xx_emit_request(req);
1415 }
1416
1417 static int gen8_render_emit_request(struct drm_i915_gem_request *req)
1418 {
1419         struct intel_engine_cs *engine = req->engine;
1420         struct intel_ring *ring = req->ring;
1421         int ret;
1422
1423         if (engine->semaphore.signal) {
1424                 ret = engine->semaphore.signal(req);
1425                 if (ret)
1426                         return ret;
1427         }
1428
1429         ret = intel_ring_begin(req, 8);
1430         if (ret)
1431                 return ret;
1432
1433         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
1434         intel_ring_emit(ring, (PIPE_CONTROL_GLOBAL_GTT_IVB |
1435                                PIPE_CONTROL_CS_STALL |
1436                                PIPE_CONTROL_QW_WRITE));
1437         intel_ring_emit(ring, intel_hws_seqno_address(engine));
1438         intel_ring_emit(ring, 0);
1439         intel_ring_emit(ring, i915_gem_request_get_seqno(req));
1440         /* We're thrashing one dword of HWS. */
1441         intel_ring_emit(ring, 0);
1442         intel_ring_emit(ring, MI_USER_INTERRUPT);
1443         intel_ring_emit(ring, MI_NOOP);
1444         intel_ring_advance(ring);
1445
1446         req->tail = ring->tail;
1447
1448         return 0;
1449 }
1450
1451 /**
1452  * intel_ring_sync - sync the waiter to the signaller on seqno
1453  *
1454  * @waiter - ring that is waiting
1455  * @signaller - ring which has, or will signal
1456  * @seqno - seqno which the waiter will block on
1457  */
1458
1459 static int
1460 gen8_ring_sync_to(struct drm_i915_gem_request *req,
1461                   struct drm_i915_gem_request *signal)
1462 {
1463         struct intel_ring *ring = req->ring;
1464         struct drm_i915_private *dev_priv = req->i915;
1465         u64 offset = GEN8_WAIT_OFFSET(req->engine, signal->engine->id);
1466         struct i915_hw_ppgtt *ppgtt;
1467         int ret;
1468
1469         ret = intel_ring_begin(req, 4);
1470         if (ret)
1471                 return ret;
1472
1473         intel_ring_emit(ring,
1474                         MI_SEMAPHORE_WAIT |
1475                         MI_SEMAPHORE_GLOBAL_GTT |
1476                         MI_SEMAPHORE_SAD_GTE_SDD);
1477         intel_ring_emit(ring, signal->fence.seqno);
1478         intel_ring_emit(ring, lower_32_bits(offset));
1479         intel_ring_emit(ring, upper_32_bits(offset));
1480         intel_ring_advance(ring);
1481
1482         /* When the !RCS engines idle waiting upon a semaphore, they lose their
1483          * pagetables and we must reload them before executing the batch.
1484          * We do this on the i915_switch_context() following the wait and
1485          * before the dispatch.
1486          */
1487         ppgtt = req->ctx->ppgtt;
1488         if (ppgtt && req->engine->id != RCS)
1489                 ppgtt->pd_dirty_rings |= intel_engine_flag(req->engine);
1490         return 0;
1491 }
1492
1493 static int
1494 gen6_ring_sync_to(struct drm_i915_gem_request *req,
1495                   struct drm_i915_gem_request *signal)
1496 {
1497         struct intel_ring *ring = req->ring;
1498         u32 dw1 = MI_SEMAPHORE_MBOX |
1499                   MI_SEMAPHORE_COMPARE |
1500                   MI_SEMAPHORE_REGISTER;
1501         u32 wait_mbox = signal->engine->semaphore.mbox.wait[req->engine->hw_id];
1502         int ret;
1503
1504         WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
1505
1506         ret = intel_ring_begin(req, 4);
1507         if (ret)
1508                 return ret;
1509
1510         intel_ring_emit(ring, dw1 | wait_mbox);
1511         /* Throughout all of the GEM code, seqno passed implies our current
1512          * seqno is >= the last seqno executed. However for hardware the
1513          * comparison is strictly greater than.
1514          */
1515         intel_ring_emit(ring, signal->fence.seqno - 1);
1516         intel_ring_emit(ring, 0);
1517         intel_ring_emit(ring, MI_NOOP);
1518         intel_ring_advance(ring);
1519
1520         return 0;
1521 }
1522
1523 static void
1524 gen5_seqno_barrier(struct intel_engine_cs *engine)
1525 {
1526         /* MI_STORE are internally buffered by the GPU and not flushed
1527          * either by MI_FLUSH or SyncFlush or any other combination of
1528          * MI commands.
1529          *
1530          * "Only the submission of the store operation is guaranteed.
1531          * The write result will be complete (coherent) some time later
1532          * (this is practically a finite period but there is no guaranteed
1533          * latency)."
1534          *
1535          * Empirically, we observe that we need a delay of at least 75us to
1536          * be sure that the seqno write is visible by the CPU.
1537          */
1538         usleep_range(125, 250);
1539 }
1540
1541 static void
1542 gen6_seqno_barrier(struct intel_engine_cs *engine)
1543 {
1544         struct drm_i915_private *dev_priv = engine->i915;
1545
1546         /* Workaround to force correct ordering between irq and seqno writes on
1547          * ivb (and maybe also on snb) by reading from a CS register (like
1548          * ACTHD) before reading the status page.
1549          *
1550          * Note that this effectively stalls the read by the time it takes to
1551          * do a memory transaction, which more or less ensures that the write
1552          * from the GPU has sufficient time to invalidate the CPU cacheline.
1553          * Alternatively we could delay the interrupt from the CS ring to give
1554          * the write time to land, but that would incur a delay after every
1555          * batch i.e. much more frequent than a delay when waiting for the
1556          * interrupt (with the same net latency).
1557          *
1558          * Also note that to prevent whole machine hangs on gen7, we have to
1559          * take the spinlock to guard against concurrent cacheline access.
1560          */
1561         spin_lock_irq(&dev_priv->uncore.lock);
1562         POSTING_READ_FW(RING_ACTHD(engine->mmio_base));
1563         spin_unlock_irq(&dev_priv->uncore.lock);
1564 }
1565
1566 static void
1567 gen5_irq_enable(struct intel_engine_cs *engine)
1568 {
1569         gen5_enable_gt_irq(engine->i915, engine->irq_enable_mask);
1570 }
1571
1572 static void
1573 gen5_irq_disable(struct intel_engine_cs *engine)
1574 {
1575         gen5_disable_gt_irq(engine->i915, engine->irq_enable_mask);
1576 }
1577
1578 static void
1579 i9xx_irq_enable(struct intel_engine_cs *engine)
1580 {
1581         struct drm_i915_private *dev_priv = engine->i915;
1582
1583         dev_priv->irq_mask &= ~engine->irq_enable_mask;
1584         I915_WRITE(IMR, dev_priv->irq_mask);
1585         POSTING_READ_FW(RING_IMR(engine->mmio_base));
1586 }
1587
1588 static void
1589 i9xx_irq_disable(struct intel_engine_cs *engine)
1590 {
1591         struct drm_i915_private *dev_priv = engine->i915;
1592
1593         dev_priv->irq_mask |= engine->irq_enable_mask;
1594         I915_WRITE(IMR, dev_priv->irq_mask);
1595 }
1596
1597 static void
1598 i8xx_irq_enable(struct intel_engine_cs *engine)
1599 {
1600         struct drm_i915_private *dev_priv = engine->i915;
1601
1602         dev_priv->irq_mask &= ~engine->irq_enable_mask;
1603         I915_WRITE16(IMR, dev_priv->irq_mask);
1604         POSTING_READ16(RING_IMR(engine->mmio_base));
1605 }
1606
1607 static void
1608 i8xx_irq_disable(struct intel_engine_cs *engine)
1609 {
1610         struct drm_i915_private *dev_priv = engine->i915;
1611
1612         dev_priv->irq_mask |= engine->irq_enable_mask;
1613         I915_WRITE16(IMR, dev_priv->irq_mask);
1614 }
1615
1616 static int
1617 bsd_ring_flush(struct drm_i915_gem_request *req, u32 mode)
1618 {
1619         struct intel_ring *ring = req->ring;
1620         int ret;
1621
1622         ret = intel_ring_begin(req, 2);
1623         if (ret)
1624                 return ret;
1625
1626         intel_ring_emit(ring, MI_FLUSH);
1627         intel_ring_emit(ring, MI_NOOP);
1628         intel_ring_advance(ring);
1629         return 0;
1630 }
1631
1632 static void
1633 gen6_irq_enable(struct intel_engine_cs *engine)
1634 {
1635         struct drm_i915_private *dev_priv = engine->i915;
1636
1637         I915_WRITE_IMR(engine,
1638                        ~(engine->irq_enable_mask |
1639                          engine->irq_keep_mask));
1640         gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask);
1641 }
1642
1643 static void
1644 gen6_irq_disable(struct intel_engine_cs *engine)
1645 {
1646         struct drm_i915_private *dev_priv = engine->i915;
1647
1648         I915_WRITE_IMR(engine, ~engine->irq_keep_mask);
1649         gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask);
1650 }
1651
1652 static void
1653 hsw_vebox_irq_enable(struct intel_engine_cs *engine)
1654 {
1655         struct drm_i915_private *dev_priv = engine->i915;
1656
1657         I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
1658         gen6_enable_pm_irq(dev_priv, engine->irq_enable_mask);
1659 }
1660
1661 static void
1662 hsw_vebox_irq_disable(struct intel_engine_cs *engine)
1663 {
1664         struct drm_i915_private *dev_priv = engine->i915;
1665
1666         I915_WRITE_IMR(engine, ~0);
1667         gen6_disable_pm_irq(dev_priv, engine->irq_enable_mask);
1668 }
1669
1670 static void
1671 gen8_irq_enable(struct intel_engine_cs *engine)
1672 {
1673         struct drm_i915_private *dev_priv = engine->i915;
1674
1675         I915_WRITE_IMR(engine,
1676                        ~(engine->irq_enable_mask |
1677                          engine->irq_keep_mask));
1678         POSTING_READ_FW(RING_IMR(engine->mmio_base));
1679 }
1680
1681 static void
1682 gen8_irq_disable(struct intel_engine_cs *engine)
1683 {
1684         struct drm_i915_private *dev_priv = engine->i915;
1685
1686         I915_WRITE_IMR(engine, ~engine->irq_keep_mask);
1687 }
1688
1689 static int
1690 i965_emit_bb_start(struct drm_i915_gem_request *req,
1691                    u64 offset, u32 length,
1692                    unsigned int dispatch_flags)
1693 {
1694         struct intel_ring *ring = req->ring;
1695         int ret;
1696
1697         ret = intel_ring_begin(req, 2);
1698         if (ret)
1699                 return ret;
1700
1701         intel_ring_emit(ring,
1702                         MI_BATCH_BUFFER_START |
1703                         MI_BATCH_GTT |
1704                         (dispatch_flags & I915_DISPATCH_SECURE ?
1705                          0 : MI_BATCH_NON_SECURE_I965));
1706         intel_ring_emit(ring, offset);
1707         intel_ring_advance(ring);
1708
1709         return 0;
1710 }
1711
1712 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1713 #define I830_BATCH_LIMIT (256*1024)
1714 #define I830_TLB_ENTRIES (2)
1715 #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
1716 static int
1717 i830_emit_bb_start(struct drm_i915_gem_request *req,
1718                    u64 offset, u32 len,
1719                    unsigned int dispatch_flags)
1720 {
1721         struct intel_ring *ring = req->ring;
1722         u32 cs_offset = i915_ggtt_offset(req->engine->scratch);
1723         int ret;
1724
1725         ret = intel_ring_begin(req, 6);
1726         if (ret)
1727                 return ret;
1728
1729         /* Evict the invalid PTE TLBs */
1730         intel_ring_emit(ring, COLOR_BLT_CMD | BLT_WRITE_RGBA);
1731         intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096);
1732         intel_ring_emit(ring, I830_TLB_ENTRIES << 16 | 4); /* load each page */
1733         intel_ring_emit(ring, cs_offset);
1734         intel_ring_emit(ring, 0xdeadbeef);
1735         intel_ring_emit(ring, MI_NOOP);
1736         intel_ring_advance(ring);
1737
1738         if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) {
1739                 if (len > I830_BATCH_LIMIT)
1740                         return -ENOSPC;
1741
1742                 ret = intel_ring_begin(req, 6 + 2);
1743                 if (ret)
1744                         return ret;
1745
1746                 /* Blit the batch (which has now all relocs applied) to the
1747                  * stable batch scratch bo area (so that the CS never
1748                  * stumbles over its tlb invalidation bug) ...
1749                  */
1750                 intel_ring_emit(ring, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA);
1751                 intel_ring_emit(ring,
1752                                 BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096);
1753                 intel_ring_emit(ring, DIV_ROUND_UP(len, 4096) << 16 | 4096);
1754                 intel_ring_emit(ring, cs_offset);
1755                 intel_ring_emit(ring, 4096);
1756                 intel_ring_emit(ring, offset);
1757
1758                 intel_ring_emit(ring, MI_FLUSH);
1759                 intel_ring_emit(ring, MI_NOOP);
1760                 intel_ring_advance(ring);
1761
1762                 /* ... and execute it. */
1763                 offset = cs_offset;
1764         }
1765
1766         ret = intel_ring_begin(req, 2);
1767         if (ret)
1768                 return ret;
1769
1770         intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1771         intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1772                                         0 : MI_BATCH_NON_SECURE));
1773         intel_ring_advance(ring);
1774
1775         return 0;
1776 }
1777
1778 static int
1779 i915_emit_bb_start(struct drm_i915_gem_request *req,
1780                    u64 offset, u32 len,
1781                    unsigned int dispatch_flags)
1782 {
1783         struct intel_ring *ring = req->ring;
1784         int ret;
1785
1786         ret = intel_ring_begin(req, 2);
1787         if (ret)
1788                 return ret;
1789
1790         intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1791         intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1792                                         0 : MI_BATCH_NON_SECURE));
1793         intel_ring_advance(ring);
1794
1795         return 0;
1796 }
1797
1798 static void cleanup_phys_status_page(struct intel_engine_cs *engine)
1799 {
1800         struct drm_i915_private *dev_priv = engine->i915;
1801
1802         if (!dev_priv->status_page_dmah)
1803                 return;
1804
1805         drm_pci_free(&dev_priv->drm, dev_priv->status_page_dmah);
1806         engine->status_page.page_addr = NULL;
1807 }
1808
1809 static void cleanup_status_page(struct intel_engine_cs *engine)
1810 {
1811         struct i915_vma *vma;
1812
1813         vma = fetch_and_zero(&engine->status_page.vma);
1814         if (!vma)
1815                 return;
1816
1817         i915_vma_unpin(vma);
1818         i915_gem_object_unpin_map(vma->obj);
1819         i915_vma_put(vma);
1820 }
1821
1822 static int init_status_page(struct intel_engine_cs *engine)
1823 {
1824         struct drm_i915_gem_object *obj;
1825         struct i915_vma *vma;
1826         unsigned int flags;
1827         int ret;
1828
1829         obj = i915_gem_object_create(&engine->i915->drm, 4096);
1830         if (IS_ERR(obj)) {
1831                 DRM_ERROR("Failed to allocate status page\n");
1832                 return PTR_ERR(obj);
1833         }
1834
1835         ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1836         if (ret)
1837                 goto err;
1838
1839         vma = i915_vma_create(obj, &engine->i915->ggtt.base, NULL);
1840         if (IS_ERR(vma)) {
1841                 ret = PTR_ERR(vma);
1842                 goto err;
1843         }
1844
1845         flags = PIN_GLOBAL;
1846         if (!HAS_LLC(engine->i915))
1847                 /* On g33, we cannot place HWS above 256MiB, so
1848                  * restrict its pinning to the low mappable arena.
1849                  * Though this restriction is not documented for
1850                  * gen4, gen5, or byt, they also behave similarly
1851                  * and hang if the HWS is placed at the top of the
1852                  * GTT. To generalise, it appears that all !llc
1853                  * platforms have issues with us placing the HWS
1854                  * above the mappable region (even though we never
1855                  * actualy map it).
1856                  */
1857                 flags |= PIN_MAPPABLE;
1858         ret = i915_vma_pin(vma, 0, 4096, flags);
1859         if (ret)
1860                 goto err;
1861
1862         engine->status_page.vma = vma;
1863         engine->status_page.ggtt_offset = i915_ggtt_offset(vma);
1864         engine->status_page.page_addr =
1865                 i915_gem_object_pin_map(obj, I915_MAP_WB);
1866
1867         DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1868                          engine->name, i915_ggtt_offset(vma));
1869         return 0;
1870
1871 err:
1872         i915_gem_object_put(obj);
1873         return ret;
1874 }
1875
1876 static int init_phys_status_page(struct intel_engine_cs *engine)
1877 {
1878         struct drm_i915_private *dev_priv = engine->i915;
1879
1880         dev_priv->status_page_dmah =
1881                 drm_pci_alloc(&dev_priv->drm, PAGE_SIZE, PAGE_SIZE);
1882         if (!dev_priv->status_page_dmah)
1883                 return -ENOMEM;
1884
1885         engine->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1886         memset(engine->status_page.page_addr, 0, PAGE_SIZE);
1887
1888         return 0;
1889 }
1890
1891 int intel_ring_pin(struct intel_ring *ring)
1892 {
1893         /* Ring wraparound at offset 0 sometimes hangs. No idea why. */
1894         unsigned int flags = PIN_GLOBAL | PIN_OFFSET_BIAS | 4096;
1895         enum i915_map_type map;
1896         struct i915_vma *vma = ring->vma;
1897         void *addr;
1898         int ret;
1899
1900         GEM_BUG_ON(ring->vaddr);
1901
1902         map = HAS_LLC(ring->engine->i915) ? I915_MAP_WB : I915_MAP_WC;
1903
1904         if (vma->obj->stolen)
1905                 flags |= PIN_MAPPABLE;
1906
1907         if (!(vma->flags & I915_VMA_GLOBAL_BIND)) {
1908                 if (flags & PIN_MAPPABLE || map == I915_MAP_WC)
1909                         ret = i915_gem_object_set_to_gtt_domain(vma->obj, true);
1910                 else
1911                         ret = i915_gem_object_set_to_cpu_domain(vma->obj, true);
1912                 if (unlikely(ret))
1913                         return ret;
1914         }
1915
1916         ret = i915_vma_pin(vma, 0, PAGE_SIZE, flags);
1917         if (unlikely(ret))
1918                 return ret;
1919
1920         if (i915_vma_is_map_and_fenceable(vma))
1921                 addr = (void __force *)i915_vma_pin_iomap(vma);
1922         else
1923                 addr = i915_gem_object_pin_map(vma->obj, map);
1924         if (IS_ERR(addr))
1925                 goto err;
1926
1927         ring->vaddr = addr;
1928         return 0;
1929
1930 err:
1931         i915_vma_unpin(vma);
1932         return PTR_ERR(addr);
1933 }
1934
1935 void intel_ring_unpin(struct intel_ring *ring)
1936 {
1937         GEM_BUG_ON(!ring->vma);
1938         GEM_BUG_ON(!ring->vaddr);
1939
1940         if (i915_vma_is_map_and_fenceable(ring->vma))
1941                 i915_vma_unpin_iomap(ring->vma);
1942         else
1943                 i915_gem_object_unpin_map(ring->vma->obj);
1944         ring->vaddr = NULL;
1945
1946         i915_vma_unpin(ring->vma);
1947 }
1948
1949 static struct i915_vma *
1950 intel_ring_create_vma(struct drm_i915_private *dev_priv, int size)
1951 {
1952         struct drm_i915_gem_object *obj;
1953         struct i915_vma *vma;
1954
1955         obj = i915_gem_object_create_stolen(&dev_priv->drm, size);
1956         if (!obj)
1957                 obj = i915_gem_object_create(&dev_priv->drm, size);
1958         if (IS_ERR(obj))
1959                 return ERR_CAST(obj);
1960
1961         /* mark ring buffers as read-only from GPU side by default */
1962         obj->gt_ro = 1;
1963
1964         vma = i915_vma_create(obj, &dev_priv->ggtt.base, NULL);
1965         if (IS_ERR(vma))
1966                 goto err;
1967
1968         return vma;
1969
1970 err:
1971         i915_gem_object_put(obj);
1972         return vma;
1973 }
1974
1975 struct intel_ring *
1976 intel_engine_create_ring(struct intel_engine_cs *engine, int size)
1977 {
1978         struct intel_ring *ring;
1979         struct i915_vma *vma;
1980
1981         GEM_BUG_ON(!is_power_of_2(size));
1982
1983         ring = kzalloc(sizeof(*ring), GFP_KERNEL);
1984         if (!ring)
1985                 return ERR_PTR(-ENOMEM);
1986
1987         ring->engine = engine;
1988
1989         INIT_LIST_HEAD(&ring->request_list);
1990
1991         ring->size = size;
1992         /* Workaround an erratum on the i830 which causes a hang if
1993          * the TAIL pointer points to within the last 2 cachelines
1994          * of the buffer.
1995          */
1996         ring->effective_size = size;
1997         if (IS_I830(engine->i915) || IS_845G(engine->i915))
1998                 ring->effective_size -= 2 * CACHELINE_BYTES;
1999
2000         ring->last_retired_head = -1;
2001         intel_ring_update_space(ring);
2002
2003         vma = intel_ring_create_vma(engine->i915, size);
2004         if (IS_ERR(vma)) {
2005                 kfree(ring);
2006                 return ERR_CAST(vma);
2007         }
2008         ring->vma = vma;
2009
2010         list_add(&ring->link, &engine->buffers);
2011         return ring;
2012 }
2013
2014 void
2015 intel_ring_free(struct intel_ring *ring)
2016 {
2017         i915_vma_put(ring->vma);
2018         list_del(&ring->link);
2019         kfree(ring);
2020 }
2021
2022 static int intel_ring_context_pin(struct i915_gem_context *ctx,
2023                                   struct intel_engine_cs *engine)
2024 {
2025         struct intel_context *ce = &ctx->engine[engine->id];
2026         int ret;
2027
2028         lockdep_assert_held(&ctx->i915->drm.struct_mutex);
2029
2030         if (ce->pin_count++)
2031                 return 0;
2032
2033         if (ce->state) {
2034                 ret = i915_gem_object_set_to_gtt_domain(ce->state->obj, false);
2035                 if (ret)
2036                         goto error;
2037
2038                 ret = i915_vma_pin(ce->state, 0, ctx->ggtt_alignment,
2039                                    PIN_GLOBAL | PIN_HIGH);
2040                 if (ret)
2041                         goto error;
2042         }
2043
2044         /* The kernel context is only used as a placeholder for flushing the
2045          * active context. It is never used for submitting user rendering and
2046          * as such never requires the golden render context, and so we can skip
2047          * emitting it when we switch to the kernel context. This is required
2048          * as during eviction we cannot allocate and pin the renderstate in
2049          * order to initialise the context.
2050          */
2051         if (ctx == ctx->i915->kernel_context)
2052                 ce->initialised = true;
2053
2054         i915_gem_context_get(ctx);
2055         return 0;
2056
2057 error:
2058         ce->pin_count = 0;
2059         return ret;
2060 }
2061
2062 static void intel_ring_context_unpin(struct i915_gem_context *ctx,
2063                                      struct intel_engine_cs *engine)
2064 {
2065         struct intel_context *ce = &ctx->engine[engine->id];
2066
2067         lockdep_assert_held(&ctx->i915->drm.struct_mutex);
2068
2069         if (--ce->pin_count)
2070                 return;
2071
2072         if (ce->state)
2073                 i915_vma_unpin(ce->state);
2074
2075         i915_gem_context_put(ctx);
2076 }
2077
2078 static int intel_init_ring_buffer(struct intel_engine_cs *engine)
2079 {
2080         struct drm_i915_private *dev_priv = engine->i915;
2081         struct intel_ring *ring;
2082         int ret;
2083
2084         WARN_ON(engine->buffer);
2085
2086         intel_engine_setup_common(engine);
2087
2088         memset(engine->semaphore.sync_seqno, 0,
2089                sizeof(engine->semaphore.sync_seqno));
2090
2091         ret = intel_engine_init_common(engine);
2092         if (ret)
2093                 goto error;
2094
2095         /* We may need to do things with the shrinker which
2096          * require us to immediately switch back to the default
2097          * context. This can cause a problem as pinning the
2098          * default context also requires GTT space which may not
2099          * be available. To avoid this we always pin the default
2100          * context.
2101          */
2102         ret = intel_ring_context_pin(dev_priv->kernel_context, engine);
2103         if (ret)
2104                 goto error;
2105
2106         ring = intel_engine_create_ring(engine, 32 * PAGE_SIZE);
2107         if (IS_ERR(ring)) {
2108                 ret = PTR_ERR(ring);
2109                 goto error;
2110         }
2111
2112         if (I915_NEED_GFX_HWS(dev_priv)) {
2113                 ret = init_status_page(engine);
2114                 if (ret)
2115                         goto error;
2116         } else {
2117                 WARN_ON(engine->id != RCS);
2118                 ret = init_phys_status_page(engine);
2119                 if (ret)
2120                         goto error;
2121         }
2122
2123         ret = intel_ring_pin(ring);
2124         if (ret) {
2125                 intel_ring_free(ring);
2126                 goto error;
2127         }
2128         engine->buffer = ring;
2129
2130         return 0;
2131
2132 error:
2133         intel_engine_cleanup(engine);
2134         return ret;
2135 }
2136
2137 void intel_engine_cleanup(struct intel_engine_cs *engine)
2138 {
2139         struct drm_i915_private *dev_priv;
2140
2141         if (!intel_engine_initialized(engine))
2142                 return;
2143
2144         dev_priv = engine->i915;
2145
2146         if (engine->buffer) {
2147                 WARN_ON(INTEL_GEN(dev_priv) > 2 &&
2148                         (I915_READ_MODE(engine) & MODE_IDLE) == 0);
2149
2150                 intel_ring_unpin(engine->buffer);
2151                 intel_ring_free(engine->buffer);
2152                 engine->buffer = NULL;
2153         }
2154
2155         if (engine->cleanup)
2156                 engine->cleanup(engine);
2157
2158         if (I915_NEED_GFX_HWS(dev_priv)) {
2159                 cleanup_status_page(engine);
2160         } else {
2161                 WARN_ON(engine->id != RCS);
2162                 cleanup_phys_status_page(engine);
2163         }
2164
2165         intel_engine_cleanup_common(engine);
2166
2167         intel_ring_context_unpin(dev_priv->kernel_context, engine);
2168
2169         engine->i915 = NULL;
2170 }
2171
2172 int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request)
2173 {
2174         int ret;
2175
2176         /* Flush enough space to reduce the likelihood of waiting after
2177          * we start building the request - in which case we will just
2178          * have to repeat work.
2179          */
2180         request->reserved_space += LEGACY_REQUEST_SIZE;
2181
2182         request->ring = request->engine->buffer;
2183
2184         ret = intel_ring_begin(request, 0);
2185         if (ret)
2186                 return ret;
2187
2188         request->reserved_space -= LEGACY_REQUEST_SIZE;
2189         return 0;
2190 }
2191
2192 static int wait_for_space(struct drm_i915_gem_request *req, int bytes)
2193 {
2194         struct intel_ring *ring = req->ring;
2195         struct drm_i915_gem_request *target;
2196         int ret;
2197
2198         intel_ring_update_space(ring);
2199         if (ring->space >= bytes)
2200                 return 0;
2201
2202         /*
2203          * Space is reserved in the ringbuffer for finalising the request,
2204          * as that cannot be allowed to fail. During request finalisation,
2205          * reserved_space is set to 0 to stop the overallocation and the
2206          * assumption is that then we never need to wait (which has the
2207          * risk of failing with EINTR).
2208          *
2209          * See also i915_gem_request_alloc() and i915_add_request().
2210          */
2211         GEM_BUG_ON(!req->reserved_space);
2212
2213         list_for_each_entry(target, &ring->request_list, ring_link) {
2214                 unsigned space;
2215
2216                 /* Would completion of this request free enough space? */
2217                 space = __intel_ring_space(target->postfix, ring->tail,
2218                                            ring->size);
2219                 if (space >= bytes)
2220                         break;
2221         }
2222
2223         if (WARN_ON(&target->ring_link == &ring->request_list))
2224                 return -ENOSPC;
2225
2226         ret = i915_wait_request(target, true, NULL, NO_WAITBOOST);
2227         if (ret)
2228                 return ret;
2229
2230         if (i915_reset_in_progress(&target->i915->gpu_error))
2231                 return -EAGAIN;
2232
2233         i915_gem_request_retire_upto(target);
2234
2235         intel_ring_update_space(ring);
2236         GEM_BUG_ON(ring->space < bytes);
2237         return 0;
2238 }
2239
2240 int intel_ring_begin(struct drm_i915_gem_request *req, int num_dwords)
2241 {
2242         struct intel_ring *ring = req->ring;
2243         int remain_actual = ring->size - ring->tail;
2244         int remain_usable = ring->effective_size - ring->tail;
2245         int bytes = num_dwords * sizeof(u32);
2246         int total_bytes, wait_bytes;
2247         bool need_wrap = false;
2248
2249         total_bytes = bytes + req->reserved_space;
2250
2251         if (unlikely(bytes > remain_usable)) {
2252                 /*
2253                  * Not enough space for the basic request. So need to flush
2254                  * out the remainder and then wait for base + reserved.
2255                  */
2256                 wait_bytes = remain_actual + total_bytes;
2257                 need_wrap = true;
2258         } else if (unlikely(total_bytes > remain_usable)) {
2259                 /*
2260                  * The base request will fit but the reserved space
2261                  * falls off the end. So we don't need an immediate wrap
2262                  * and only need to effectively wait for the reserved
2263                  * size space from the start of ringbuffer.
2264                  */
2265                 wait_bytes = remain_actual + req->reserved_space;
2266         } else {
2267                 /* No wrapping required, just waiting. */
2268                 wait_bytes = total_bytes;
2269         }
2270
2271         if (wait_bytes > ring->space) {
2272                 int ret = wait_for_space(req, wait_bytes);
2273                 if (unlikely(ret))
2274                         return ret;
2275         }
2276
2277         if (unlikely(need_wrap)) {
2278                 GEM_BUG_ON(remain_actual > ring->space);
2279                 GEM_BUG_ON(ring->tail + remain_actual > ring->size);
2280
2281                 /* Fill the tail with MI_NOOP */
2282                 memset(ring->vaddr + ring->tail, 0, remain_actual);
2283                 ring->tail = 0;
2284                 ring->space -= remain_actual;
2285         }
2286
2287         ring->space -= bytes;
2288         GEM_BUG_ON(ring->space < 0);
2289         return 0;
2290 }
2291
2292 /* Align the ring tail to a cacheline boundary */
2293 int intel_ring_cacheline_align(struct drm_i915_gem_request *req)
2294 {
2295         struct intel_ring *ring = req->ring;
2296         int num_dwords =
2297                 (ring->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
2298         int ret;
2299
2300         if (num_dwords == 0)
2301                 return 0;
2302
2303         num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
2304         ret = intel_ring_begin(req, num_dwords);
2305         if (ret)
2306                 return ret;
2307
2308         while (num_dwords--)
2309                 intel_ring_emit(ring, MI_NOOP);
2310
2311         intel_ring_advance(ring);
2312
2313         return 0;
2314 }
2315
2316 static void gen6_bsd_submit_request(struct drm_i915_gem_request *request)
2317 {
2318         struct drm_i915_private *dev_priv = request->i915;
2319
2320         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
2321
2322        /* Every tail move must follow the sequence below */
2323
2324         /* Disable notification that the ring is IDLE. The GT
2325          * will then assume that it is busy and bring it out of rc6.
2326          */
2327         I915_WRITE_FW(GEN6_BSD_SLEEP_PSMI_CONTROL,
2328                       _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2329
2330         /* Clear the context id. Here be magic! */
2331         I915_WRITE64_FW(GEN6_BSD_RNCID, 0x0);
2332
2333         /* Wait for the ring not to be idle, i.e. for it to wake up. */
2334         if (intel_wait_for_register_fw(dev_priv,
2335                                        GEN6_BSD_SLEEP_PSMI_CONTROL,
2336                                        GEN6_BSD_SLEEP_INDICATOR,
2337                                        0,
2338                                        50))
2339                 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
2340
2341         /* Now that the ring is fully powered up, update the tail */
2342         i9xx_submit_request(request);
2343
2344         /* Let the ring send IDLE messages to the GT again,
2345          * and so let it sleep to conserve power when idle.
2346          */
2347         I915_WRITE_FW(GEN6_BSD_SLEEP_PSMI_CONTROL,
2348                       _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2349
2350         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
2351 }
2352
2353 static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req, u32 mode)
2354 {
2355         struct intel_ring *ring = req->ring;
2356         uint32_t cmd;
2357         int ret;
2358
2359         ret = intel_ring_begin(req, 4);
2360         if (ret)
2361                 return ret;
2362
2363         cmd = MI_FLUSH_DW;
2364         if (INTEL_GEN(req->i915) >= 8)
2365                 cmd += 1;
2366
2367         /* We always require a command barrier so that subsequent
2368          * commands, such as breadcrumb interrupts, are strictly ordered
2369          * wrt the contents of the write cache being flushed to memory
2370          * (and thus being coherent from the CPU).
2371          */
2372         cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2373
2374         /*
2375          * Bspec vol 1c.5 - video engine command streamer:
2376          * "If ENABLED, all TLBs will be invalidated once the flush
2377          * operation is complete. This bit is only valid when the
2378          * Post-Sync Operation field is a value of 1h or 3h."
2379          */
2380         if (mode & EMIT_INVALIDATE)
2381                 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
2382
2383         intel_ring_emit(ring, cmd);
2384         intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2385         if (INTEL_GEN(req->i915) >= 8) {
2386                 intel_ring_emit(ring, 0); /* upper addr */
2387                 intel_ring_emit(ring, 0); /* value */
2388         } else  {
2389                 intel_ring_emit(ring, 0);
2390                 intel_ring_emit(ring, MI_NOOP);
2391         }
2392         intel_ring_advance(ring);
2393         return 0;
2394 }
2395
2396 static int
2397 gen8_emit_bb_start(struct drm_i915_gem_request *req,
2398                    u64 offset, u32 len,
2399                    unsigned int dispatch_flags)
2400 {
2401         struct intel_ring *ring = req->ring;
2402         bool ppgtt = USES_PPGTT(req->i915) &&
2403                         !(dispatch_flags & I915_DISPATCH_SECURE);
2404         int ret;
2405
2406         ret = intel_ring_begin(req, 4);
2407         if (ret)
2408                 return ret;
2409
2410         /* FIXME(BDW): Address space and security selectors. */
2411         intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8) |
2412                         (dispatch_flags & I915_DISPATCH_RS ?
2413                          MI_BATCH_RESOURCE_STREAMER : 0));
2414         intel_ring_emit(ring, lower_32_bits(offset));
2415         intel_ring_emit(ring, upper_32_bits(offset));
2416         intel_ring_emit(ring, MI_NOOP);
2417         intel_ring_advance(ring);
2418
2419         return 0;
2420 }
2421
2422 static int
2423 hsw_emit_bb_start(struct drm_i915_gem_request *req,
2424                   u64 offset, u32 len,
2425                   unsigned int dispatch_flags)
2426 {
2427         struct intel_ring *ring = req->ring;
2428         int ret;
2429
2430         ret = intel_ring_begin(req, 2);
2431         if (ret)
2432                 return ret;
2433
2434         intel_ring_emit(ring,
2435                         MI_BATCH_BUFFER_START |
2436                         (dispatch_flags & I915_DISPATCH_SECURE ?
2437                          0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW) |
2438                         (dispatch_flags & I915_DISPATCH_RS ?
2439                          MI_BATCH_RESOURCE_STREAMER : 0));
2440         /* bit0-7 is the length on GEN6+ */
2441         intel_ring_emit(ring, offset);
2442         intel_ring_advance(ring);
2443
2444         return 0;
2445 }
2446
2447 static int
2448 gen6_emit_bb_start(struct drm_i915_gem_request *req,
2449                    u64 offset, u32 len,
2450                    unsigned int dispatch_flags)
2451 {
2452         struct intel_ring *ring = req->ring;
2453         int ret;
2454
2455         ret = intel_ring_begin(req, 2);
2456         if (ret)
2457                 return ret;
2458
2459         intel_ring_emit(ring,
2460                         MI_BATCH_BUFFER_START |
2461                         (dispatch_flags & I915_DISPATCH_SECURE ?
2462                          0 : MI_BATCH_NON_SECURE_I965));
2463         /* bit0-7 is the length on GEN6+ */
2464         intel_ring_emit(ring, offset);
2465         intel_ring_advance(ring);
2466
2467         return 0;
2468 }
2469
2470 /* Blitter support (SandyBridge+) */
2471
2472 static int gen6_ring_flush(struct drm_i915_gem_request *req, u32 mode)
2473 {
2474         struct intel_ring *ring = req->ring;
2475         uint32_t cmd;
2476         int ret;
2477
2478         ret = intel_ring_begin(req, 4);
2479         if (ret)
2480                 return ret;
2481
2482         cmd = MI_FLUSH_DW;
2483         if (INTEL_GEN(req->i915) >= 8)
2484                 cmd += 1;
2485
2486         /* We always require a command barrier so that subsequent
2487          * commands, such as breadcrumb interrupts, are strictly ordered
2488          * wrt the contents of the write cache being flushed to memory
2489          * (and thus being coherent from the CPU).
2490          */
2491         cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2492
2493         /*
2494          * Bspec vol 1c.3 - blitter engine command streamer:
2495          * "If ENABLED, all TLBs will be invalidated once the flush
2496          * operation is complete. This bit is only valid when the
2497          * Post-Sync Operation field is a value of 1h or 3h."
2498          */
2499         if (mode & EMIT_INVALIDATE)
2500                 cmd |= MI_INVALIDATE_TLB;
2501         intel_ring_emit(ring, cmd);
2502         intel_ring_emit(ring,
2503                         I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2504         if (INTEL_GEN(req->i915) >= 8) {
2505                 intel_ring_emit(ring, 0); /* upper addr */
2506                 intel_ring_emit(ring, 0); /* value */
2507         } else  {
2508                 intel_ring_emit(ring, 0);
2509                 intel_ring_emit(ring, MI_NOOP);
2510         }
2511         intel_ring_advance(ring);
2512
2513         return 0;
2514 }
2515
2516 static void intel_ring_init_semaphores(struct drm_i915_private *dev_priv,
2517                                        struct intel_engine_cs *engine)
2518 {
2519         struct drm_i915_gem_object *obj;
2520         int ret, i;
2521
2522         if (!i915.semaphores)
2523                 return;
2524
2525         if (INTEL_GEN(dev_priv) >= 8 && !dev_priv->semaphore) {
2526                 struct i915_vma *vma;
2527
2528                 obj = i915_gem_object_create(&dev_priv->drm, 4096);
2529                 if (IS_ERR(obj))
2530                         goto err;
2531
2532                 vma = i915_vma_create(obj, &dev_priv->ggtt.base, NULL);
2533                 if (IS_ERR(vma))
2534                         goto err_obj;
2535
2536                 ret = i915_gem_object_set_to_gtt_domain(obj, false);
2537                 if (ret)
2538                         goto err_obj;
2539
2540                 ret = i915_vma_pin(vma, 0, 0, PIN_GLOBAL | PIN_HIGH);
2541                 if (ret)
2542                         goto err_obj;
2543
2544                 dev_priv->semaphore = vma;
2545         }
2546
2547         if (INTEL_GEN(dev_priv) >= 8) {
2548                 u32 offset = i915_ggtt_offset(dev_priv->semaphore);
2549
2550                 engine->semaphore.sync_to = gen8_ring_sync_to;
2551                 engine->semaphore.signal = gen8_xcs_signal;
2552
2553                 for (i = 0; i < I915_NUM_ENGINES; i++) {
2554                         u32 ring_offset;
2555
2556                         if (i != engine->id)
2557                                 ring_offset = offset + GEN8_SEMAPHORE_OFFSET(engine->id, i);
2558                         else
2559                                 ring_offset = MI_SEMAPHORE_SYNC_INVALID;
2560
2561                         engine->semaphore.signal_ggtt[i] = ring_offset;
2562                 }
2563         } else if (INTEL_GEN(dev_priv) >= 6) {
2564                 engine->semaphore.sync_to = gen6_ring_sync_to;
2565                 engine->semaphore.signal = gen6_signal;
2566
2567                 /*
2568                  * The current semaphore is only applied on pre-gen8
2569                  * platform.  And there is no VCS2 ring on the pre-gen8
2570                  * platform. So the semaphore between RCS and VCS2 is
2571                  * initialized as INVALID.  Gen8 will initialize the
2572                  * sema between VCS2 and RCS later.
2573                  */
2574                 for (i = 0; i < GEN6_NUM_SEMAPHORES; i++) {
2575                         static const struct {
2576                                 u32 wait_mbox;
2577                                 i915_reg_t mbox_reg;
2578                         } sem_data[GEN6_NUM_SEMAPHORES][GEN6_NUM_SEMAPHORES] = {
2579                                 [RCS_HW] = {
2580                                         [VCS_HW] =  { .wait_mbox = MI_SEMAPHORE_SYNC_RV,  .mbox_reg = GEN6_VRSYNC },
2581                                         [BCS_HW] =  { .wait_mbox = MI_SEMAPHORE_SYNC_RB,  .mbox_reg = GEN6_BRSYNC },
2582                                         [VECS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_RVE, .mbox_reg = GEN6_VERSYNC },
2583                                 },
2584                                 [VCS_HW] = {
2585                                         [RCS_HW] =  { .wait_mbox = MI_SEMAPHORE_SYNC_VR,  .mbox_reg = GEN6_RVSYNC },
2586                                         [BCS_HW] =  { .wait_mbox = MI_SEMAPHORE_SYNC_VB,  .mbox_reg = GEN6_BVSYNC },
2587                                         [VECS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VVE, .mbox_reg = GEN6_VEVSYNC },
2588                                 },
2589                                 [BCS_HW] = {
2590                                         [RCS_HW] =  { .wait_mbox = MI_SEMAPHORE_SYNC_BR,  .mbox_reg = GEN6_RBSYNC },
2591                                         [VCS_HW] =  { .wait_mbox = MI_SEMAPHORE_SYNC_BV,  .mbox_reg = GEN6_VBSYNC },
2592                                         [VECS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_BVE, .mbox_reg = GEN6_VEBSYNC },
2593                                 },
2594                                 [VECS_HW] = {
2595                                         [RCS_HW] =  { .wait_mbox = MI_SEMAPHORE_SYNC_VER, .mbox_reg = GEN6_RVESYNC },
2596                                         [VCS_HW] =  { .wait_mbox = MI_SEMAPHORE_SYNC_VEV, .mbox_reg = GEN6_VVESYNC },
2597                                         [BCS_HW] =  { .wait_mbox = MI_SEMAPHORE_SYNC_VEB, .mbox_reg = GEN6_BVESYNC },
2598                                 },
2599                         };
2600                         u32 wait_mbox;
2601                         i915_reg_t mbox_reg;
2602
2603                         if (i == engine->hw_id) {
2604                                 wait_mbox = MI_SEMAPHORE_SYNC_INVALID;
2605                                 mbox_reg = GEN6_NOSYNC;
2606                         } else {
2607                                 wait_mbox = sem_data[engine->hw_id][i].wait_mbox;
2608                                 mbox_reg = sem_data[engine->hw_id][i].mbox_reg;
2609                         }
2610
2611                         engine->semaphore.mbox.wait[i] = wait_mbox;
2612                         engine->semaphore.mbox.signal[i] = mbox_reg;
2613                 }
2614         }
2615
2616         return;
2617
2618 err_obj:
2619         i915_gem_object_put(obj);
2620 err:
2621         DRM_DEBUG_DRIVER("Failed to allocate space for semaphores, disabling\n");
2622         i915.semaphores = 0;
2623 }
2624
2625 static void intel_ring_init_irq(struct drm_i915_private *dev_priv,
2626                                 struct intel_engine_cs *engine)
2627 {
2628         engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << engine->irq_shift;
2629
2630         if (INTEL_GEN(dev_priv) >= 8) {
2631                 engine->irq_enable = gen8_irq_enable;
2632                 engine->irq_disable = gen8_irq_disable;
2633                 engine->irq_seqno_barrier = gen6_seqno_barrier;
2634         } else if (INTEL_GEN(dev_priv) >= 6) {
2635                 engine->irq_enable = gen6_irq_enable;
2636                 engine->irq_disable = gen6_irq_disable;
2637                 engine->irq_seqno_barrier = gen6_seqno_barrier;
2638         } else if (INTEL_GEN(dev_priv) >= 5) {
2639                 engine->irq_enable = gen5_irq_enable;
2640                 engine->irq_disable = gen5_irq_disable;
2641                 engine->irq_seqno_barrier = gen5_seqno_barrier;
2642         } else if (INTEL_GEN(dev_priv) >= 3) {
2643                 engine->irq_enable = i9xx_irq_enable;
2644                 engine->irq_disable = i9xx_irq_disable;
2645         } else {
2646                 engine->irq_enable = i8xx_irq_enable;
2647                 engine->irq_disable = i8xx_irq_disable;
2648         }
2649 }
2650
2651 static void intel_ring_default_vfuncs(struct drm_i915_private *dev_priv,
2652                                       struct intel_engine_cs *engine)
2653 {
2654         intel_ring_init_irq(dev_priv, engine);
2655         intel_ring_init_semaphores(dev_priv, engine);
2656
2657         engine->init_hw = init_ring_common;
2658
2659         engine->emit_request = i9xx_emit_request;
2660         if (i915.semaphores)
2661                 engine->emit_request = gen6_sema_emit_request;
2662         engine->submit_request = i9xx_submit_request;
2663
2664         if (INTEL_GEN(dev_priv) >= 8)
2665                 engine->emit_bb_start = gen8_emit_bb_start;
2666         else if (INTEL_GEN(dev_priv) >= 6)
2667                 engine->emit_bb_start = gen6_emit_bb_start;
2668         else if (INTEL_GEN(dev_priv) >= 4)
2669                 engine->emit_bb_start = i965_emit_bb_start;
2670         else if (IS_I830(dev_priv) || IS_845G(dev_priv))
2671                 engine->emit_bb_start = i830_emit_bb_start;
2672         else
2673                 engine->emit_bb_start = i915_emit_bb_start;
2674 }
2675
2676 int intel_init_render_ring_buffer(struct intel_engine_cs *engine)
2677 {
2678         struct drm_i915_private *dev_priv = engine->i915;
2679         int ret;
2680
2681         intel_ring_default_vfuncs(dev_priv, engine);
2682
2683         if (HAS_L3_DPF(dev_priv))
2684                 engine->irq_keep_mask = GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
2685
2686         if (INTEL_GEN(dev_priv) >= 8) {
2687                 engine->init_context = intel_rcs_ctx_init;
2688                 engine->emit_request = gen8_render_emit_request;
2689                 engine->emit_flush = gen8_render_ring_flush;
2690                 if (i915.semaphores)
2691                         engine->semaphore.signal = gen8_rcs_signal;
2692         } else if (INTEL_GEN(dev_priv) >= 6) {
2693                 engine->init_context = intel_rcs_ctx_init;
2694                 engine->emit_flush = gen7_render_ring_flush;
2695                 if (IS_GEN6(dev_priv))
2696                         engine->emit_flush = gen6_render_ring_flush;
2697         } else if (IS_GEN5(dev_priv)) {
2698                 engine->emit_flush = gen4_render_ring_flush;
2699         } else {
2700                 if (INTEL_GEN(dev_priv) < 4)
2701                         engine->emit_flush = gen2_render_ring_flush;
2702                 else
2703                         engine->emit_flush = gen4_render_ring_flush;
2704                 engine->irq_enable_mask = I915_USER_INTERRUPT;
2705         }
2706
2707         if (IS_HASWELL(dev_priv))
2708                 engine->emit_bb_start = hsw_emit_bb_start;
2709
2710         engine->init_hw = init_render_ring;
2711         engine->cleanup = render_ring_cleanup;
2712
2713         ret = intel_init_ring_buffer(engine);
2714         if (ret)
2715                 return ret;
2716
2717         if (INTEL_GEN(dev_priv) >= 6) {
2718                 ret = intel_engine_create_scratch(engine, 4096);
2719                 if (ret)
2720                         return ret;
2721         } else if (HAS_BROKEN_CS_TLB(dev_priv)) {
2722                 ret = intel_engine_create_scratch(engine, I830_WA_SIZE);
2723                 if (ret)
2724                         return ret;
2725         }
2726
2727         return 0;
2728 }
2729
2730 int intel_init_bsd_ring_buffer(struct intel_engine_cs *engine)
2731 {
2732         struct drm_i915_private *dev_priv = engine->i915;
2733
2734         intel_ring_default_vfuncs(dev_priv, engine);
2735
2736         if (INTEL_GEN(dev_priv) >= 6) {
2737                 /* gen6 bsd needs a special wa for tail updates */
2738                 if (IS_GEN6(dev_priv))
2739                         engine->submit_request = gen6_bsd_submit_request;
2740                 engine->emit_flush = gen6_bsd_ring_flush;
2741                 if (INTEL_GEN(dev_priv) < 8)
2742                         engine->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2743         } else {
2744                 engine->mmio_base = BSD_RING_BASE;
2745                 engine->emit_flush = bsd_ring_flush;
2746                 if (IS_GEN5(dev_priv))
2747                         engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
2748                 else
2749                         engine->irq_enable_mask = I915_BSD_USER_INTERRUPT;
2750         }
2751
2752         return intel_init_ring_buffer(engine);
2753 }
2754
2755 /**
2756  * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3)
2757  */
2758 int intel_init_bsd2_ring_buffer(struct intel_engine_cs *engine)
2759 {
2760         struct drm_i915_private *dev_priv = engine->i915;
2761
2762         intel_ring_default_vfuncs(dev_priv, engine);
2763
2764         engine->emit_flush = gen6_bsd_ring_flush;
2765
2766         return intel_init_ring_buffer(engine);
2767 }
2768
2769 int intel_init_blt_ring_buffer(struct intel_engine_cs *engine)
2770 {
2771         struct drm_i915_private *dev_priv = engine->i915;
2772
2773         intel_ring_default_vfuncs(dev_priv, engine);
2774
2775         engine->emit_flush = gen6_ring_flush;
2776         if (INTEL_GEN(dev_priv) < 8)
2777                 engine->irq_enable_mask = GT_BLT_USER_INTERRUPT;
2778
2779         return intel_init_ring_buffer(engine);
2780 }
2781
2782 int intel_init_vebox_ring_buffer(struct intel_engine_cs *engine)
2783 {
2784         struct drm_i915_private *dev_priv = engine->i915;
2785
2786         intel_ring_default_vfuncs(dev_priv, engine);
2787
2788         engine->emit_flush = gen6_ring_flush;
2789
2790         if (INTEL_GEN(dev_priv) < 8) {
2791                 engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
2792                 engine->irq_enable = hsw_vebox_irq_enable;
2793                 engine->irq_disable = hsw_vebox_irq_disable;
2794         }
2795
2796         return intel_init_ring_buffer(engine);
2797 }