drivers/gpu/drm/i915/intel_ringbuffer.c

   1 /*
   2  * Copyright © 2008-2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Zou Nan hai <nanhai.zou@intel.com>
  26  *    Xiang Hai hao<haihao.xiang@intel.com>
  27  *
  28  */
  29
  30 #include <linux/log2.h>
  31 #include <drm/drmP.h>
  32 #include "i915_drv.h"
  33 #include <drm/i915_drm.h>
  34 #include "i915_trace.h"
  35 #include "intel_drv.h"
  36
  37 int __intel_ring_space(int head, int tail, int size)
  38 {
  39         int space = head - tail;
  40         if (space <= 0)
  41                 space += size;
  42         return space - I915_RING_FREE_SPACE;
  43 }
  44
  45 void intel_ring_update_space(struct intel_ringbuffer *ringbuf)
  46 {
  47         if (ringbuf->last_retired_head != -1) {
  48                 ringbuf->head = ringbuf->last_retired_head;
  49                 ringbuf->last_retired_head = -1;
  50         }
  51
  52         ringbuf->space = __intel_ring_space(ringbuf->head & HEAD_ADDR,
  53                                             ringbuf->tail, ringbuf->size);
  54 }
  55
  56 bool intel_engine_stopped(struct intel_engine_cs *engine)
  57 {
  58         struct drm_i915_private *dev_priv = engine->dev->dev_private;
  59         return dev_priv->gpu_error.stop_rings & intel_engine_flag(engine);
  60 }
  61
  62 static void __intel_ring_advance(struct intel_engine_cs *engine)
  63 {
  64         struct intel_ringbuffer *ringbuf = engine->buffer;
  65         ringbuf->tail &= ringbuf->size - 1;
  66         if (intel_engine_stopped(engine))
  67                 return;
  68         engine->write_tail(engine, ringbuf->tail);
  69 }
  70
  71 static int
  72 gen2_render_ring_flush(struct drm_i915_gem_request *req,
  73                        u32      invalidate_domains,
  74                        u32      flush_domains)
  75 {
  76         struct intel_engine_cs *engine = req->engine;
  77         u32 cmd;
  78         int ret;
  79
  80         cmd = MI_FLUSH;
  81         if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
  82                 cmd |= MI_NO_WRITE_FLUSH;
  83
  84         if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
  85                 cmd |= MI_READ_FLUSH;
  86
  87         ret = intel_ring_begin(req, 2);
  88         if (ret)
  89                 return ret;
  90
  91         intel_ring_emit(engine, cmd);
  92         intel_ring_emit(engine, MI_NOOP);
  93         intel_ring_advance(engine);
  94
  95         return 0;
  96 }
  97
  98 static int
  99 gen4_render_ring_flush(struct drm_i915_gem_request *req,
 100                        u32      invalidate_domains,
 101                        u32      flush_domains)
 102 {
 103         struct intel_engine_cs *engine = req->engine;
 104         struct drm_device *dev = engine->dev;
 105         u32 cmd;
 106         int ret;
 107
 108         /*
 109          * read/write caches:
 110          *
 111          * I915_GEM_DOMAIN_RENDER is always invalidated, but is
 112          * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
 113          * also flushed at 2d versus 3d pipeline switches.
 114          *
 115          * read-only caches:
 116          *
 117          * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
 118          * MI_READ_FLUSH is set, and is always flushed on 965.
 119          *
 120          * I915_GEM_DOMAIN_COMMAND may not exist?
 121          *
 122          * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
 123          * invalidated when MI_EXE_FLUSH is set.
 124          *
 125          * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
 126          * invalidated with every MI_FLUSH.
 127          *
 128          * TLBs:
 129          *
 130          * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
 131          * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
 132          * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
 133          * are flushed at any MI_FLUSH.
 134          */
 135
 136         cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
 137         if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
 138                 cmd &= ~MI_NO_WRITE_FLUSH;
 139         if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
 140                 cmd |= MI_EXE_FLUSH;
 141
 142         if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
 143             (IS_G4X(dev) || IS_GEN5(dev)))
 144                 cmd |= MI_INVALIDATE_ISP;
 145
 146         ret = intel_ring_begin(req, 2);
 147         if (ret)
 148                 return ret;
 149
 150         intel_ring_emit(engine, cmd);
 151         intel_ring_emit(engine, MI_NOOP);
 152         intel_ring_advance(engine);
 153
 154         return 0;
 155 }
 156
 157 /**
 158  * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
 159  * implementing two workarounds on gen6.  From section 1.4.7.1
 160  * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
 161  *
 162  * [DevSNB-C+{W/A}] Before any depth stall flush (including those
 163  * produced by non-pipelined state commands), software needs to first
 164  * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
 165  * 0.
 166  *
 167  * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
 168  * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
 169  *
 170  * And the workaround for these two requires this workaround first:
 171  *
 172  * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
 173  * BEFORE the pipe-control with a post-sync op and no write-cache
 174  * flushes.
 175  *
 176  * And this last workaround is tricky because of the requirements on
 177  * that bit.  From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
 178  * volume 2 part 1:
 179  *
 180  *     "1 of the following must also be set:
 181  *      - Render Target Cache Flush Enable ([12] of DW1)
 182  *      - Depth Cache Flush Enable ([0] of DW1)
 183  *      - Stall at Pixel Scoreboard ([1] of DW1)
 184  *      - Depth Stall ([13] of DW1)
 185  *      - Post-Sync Operation ([13] of DW1)
 186  *      - Notify Enable ([8] of DW1)"
 187  *
 188  * The cache flushes require the workaround flush that triggered this
 189  * one, so we can't use it.  Depth stall would trigger the same.
 190  * Post-sync nonzero is what triggered this second workaround, so we
 191  * can't use that one either.  Notify enable is IRQs, which aren't
 192  * really our business.  That leaves only stall at scoreboard.
 193  */
 194 static int
 195 intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request *req)
 196 {
 197         struct intel_engine_cs *engine = req->engine;
 198         u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 199         int ret;
 200
 201         ret = intel_ring_begin(req, 6);
 202         if (ret)
 203                 return ret;
 204
 205         intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(5));
 206         intel_ring_emit(engine, PIPE_CONTROL_CS_STALL |
 207                         PIPE_CONTROL_STALL_AT_SCOREBOARD);
 208         intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 209         intel_ring_emit(engine, 0); /* low dword */
 210         intel_ring_emit(engine, 0); /* high dword */
 211         intel_ring_emit(engine, MI_NOOP);
 212         intel_ring_advance(engine);
 213
 214         ret = intel_ring_begin(req, 6);
 215         if (ret)
 216                 return ret;
 217
 218         intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(5));
 219         intel_ring_emit(engine, PIPE_CONTROL_QW_WRITE);
 220         intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 221         intel_ring_emit(engine, 0);
 222         intel_ring_emit(engine, 0);
 223         intel_ring_emit(engine, MI_NOOP);
 224         intel_ring_advance(engine);
 225
 226         return 0;
 227 }
 228
 229 static int
 230 gen6_render_ring_flush(struct drm_i915_gem_request *req,
 231                        u32 invalidate_domains, u32 flush_domains)
 232 {
 233         struct intel_engine_cs *engine = req->engine;
 234         u32 flags = 0;
 235         u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 236         int ret;
 237
 238         /* Force SNB workarounds for PIPE_CONTROL flushes */
 239         ret = intel_emit_post_sync_nonzero_flush(req);
 240         if (ret)
 241                 return ret;
 242
 243         /* Just flush everything.  Experiments have shown that reducing the
 244          * number of bits based on the write domains has little performance
 245          * impact.
 246          */
 247         if (flush_domains) {
 248                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 249                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 250                 /*
 251                  * Ensure that any following seqno writes only happen
 252                  * when the render cache is indeed flushed.
 253                  */
 254                 flags |= PIPE_CONTROL_CS_STALL;
 255         }
 256         if (invalidate_domains) {
 257                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 258                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 259                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 260                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 261                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 262                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 263                 /*
 264                  * TLB invalidate requires a post-sync write.
 265                  */
 266                 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
 267         }
 268
 269         ret = intel_ring_begin(req, 4);
 270         if (ret)
 271                 return ret;
 272
 273         intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4));
 274         intel_ring_emit(engine, flags);
 275         intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
 276         intel_ring_emit(engine, 0);
 277         intel_ring_advance(engine);
 278
 279         return 0;
 280 }
 281
 282 static int
 283 gen7_render_ring_cs_stall_wa(struct drm_i915_gem_request *req)
 284 {
 285         struct intel_engine_cs *engine = req->engine;
 286         int ret;
 287
 288         ret = intel_ring_begin(req, 4);
 289         if (ret)
 290                 return ret;
 291
 292         intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4));
 293         intel_ring_emit(engine, PIPE_CONTROL_CS_STALL |
 294                               PIPE_CONTROL_STALL_AT_SCOREBOARD);
 295         intel_ring_emit(engine, 0);
 296         intel_ring_emit(engine, 0);
 297         intel_ring_advance(engine);
 298
 299         return 0;
 300 }
 301
 302 static int
 303 gen7_render_ring_flush(struct drm_i915_gem_request *req,
 304                        u32 invalidate_domains, u32 flush_domains)
 305 {
 306         struct intel_engine_cs *engine = req->engine;
 307         u32 flags = 0;
 308         u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 309         int ret;
 310
 311         /*
 312          * Ensure that any following seqno writes only happen when the render
 313          * cache is indeed flushed.
 314          *
 315          * Workaround: 4th PIPE_CONTROL command (except the ones with only
 316          * read-cache invalidate bits set) must have the CS_STALL bit set. We
 317          * don't try to be clever and just set it unconditionally.
 318          */
 319         flags |= PIPE_CONTROL_CS_STALL;
 320
 321         /* Just flush everything.  Experiments have shown that reducing the
 322          * number of bits based on the write domains has little performance
 323          * impact.
 324          */
 325         if (flush_domains) {
 326                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 327                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 328                 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
 329                 flags |= PIPE_CONTROL_FLUSH_ENABLE;
 330         }
 331         if (invalidate_domains) {
 332                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 333                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 334                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 335                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 336                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 337                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 338                 flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
 339                 /*
 340                  * TLB invalidate requires a post-sync write.
 341                  */
 342                 flags |= PIPE_CONTROL_QW_WRITE;
 343                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 344
 345                 flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
 346
 347                 /* Workaround: we must issue a pipe_control with CS-stall bit
 348                  * set before a pipe_control command that has the state cache
 349                  * invalidate bit set. */
 350                 gen7_render_ring_cs_stall_wa(req);
 351         }
 352
 353         ret = intel_ring_begin(req, 4);
 354         if (ret)
 355                 return ret;
 356
 357         intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4));
 358         intel_ring_emit(engine, flags);
 359         intel_ring_emit(engine, scratch_addr);
 360         intel_ring_emit(engine, 0);
 361         intel_ring_advance(engine);
 362
 363         return 0;
 364 }
 365
 366 static int
 367 gen8_emit_pipe_control(struct drm_i915_gem_request *req,
 368                        u32 flags, u32 scratch_addr)
 369 {
 370         struct intel_engine_cs *engine = req->engine;
 371         int ret;
 372
 373         ret = intel_ring_begin(req, 6);
 374         if (ret)
 375                 return ret;
 376
 377         intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(6));
 378         intel_ring_emit(engine, flags);
 379         intel_ring_emit(engine, scratch_addr);
 380         intel_ring_emit(engine, 0);
 381         intel_ring_emit(engine, 0);
 382         intel_ring_emit(engine, 0);
 383         intel_ring_advance(engine);
 384
 385         return 0;
 386 }
 387
 388 static int
 389 gen8_render_ring_flush(struct drm_i915_gem_request *req,
 390                        u32 invalidate_domains, u32 flush_domains)
 391 {
 392         u32 flags = 0;
 393         u32 scratch_addr = req->engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 394         int ret;
 395
 396         flags |= PIPE_CONTROL_CS_STALL;
 397
 398         if (flush_domains) {
 399                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 400                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 401                 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
 402                 flags |= PIPE_CONTROL_FLUSH_ENABLE;
 403         }
 404         if (invalidate_domains) {
 405                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 406                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 407                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 408                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 409                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 410                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 411                 flags |= PIPE_CONTROL_QW_WRITE;
 412                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 413
 414                 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
 415                 ret = gen8_emit_pipe_control(req,
 416                                              PIPE_CONTROL_CS_STALL |
 417                                              PIPE_CONTROL_STALL_AT_SCOREBOARD,
 418                                              0);
 419                 if (ret)
 420                         return ret;
 421         }
 422
 423         return gen8_emit_pipe_control(req, flags, scratch_addr);
 424 }
 425
 426 static void ring_write_tail(struct intel_engine_cs *engine,
 427                             u32 value)
 428 {
 429         struct drm_i915_private *dev_priv = engine->dev->dev_private;
 430         I915_WRITE_TAIL(engine, value);
 431 }
 432
 433 u64 intel_ring_get_active_head(struct intel_engine_cs *engine)
 434 {
 435         struct drm_i915_private *dev_priv = engine->dev->dev_private;
 436         u64 acthd;
 437
 438         if (INTEL_INFO(engine->dev)->gen >= 8)
 439                 acthd = I915_READ64_2x32(RING_ACTHD(engine->mmio_base),
 440                                          RING_ACTHD_UDW(engine->mmio_base));
 441         else if (INTEL_INFO(engine->dev)->gen >= 4)
 442                 acthd = I915_READ(RING_ACTHD(engine->mmio_base));
 443         else
 444                 acthd = I915_READ(ACTHD);
 445
 446         return acthd;
 447 }
 448
 449 static void ring_setup_phys_status_page(struct intel_engine_cs *engine)
 450 {
 451         struct drm_i915_private *dev_priv = engine->dev->dev_private;
 452         u32 addr;
 453
 454         addr = dev_priv->status_page_dmah->busaddr;
 455         if (INTEL_INFO(engine->dev)->gen >= 4)
 456                 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
 457         I915_WRITE(HWS_PGA, addr);
 458 }
 459
 460 static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
 461 {
 462         struct drm_device *dev = engine->dev;
 463         struct drm_i915_private *dev_priv = engine->dev->dev_private;
 464         i915_reg_t mmio;
 465
 466         /* The ring status page addresses are no longer next to the rest of
 467          * the ring registers as of gen7.
 468          */
 469         if (IS_GEN7(dev)) {
 470                 switch (engine->id) {
 471                 case RCS:
 472                         mmio = RENDER_HWS_PGA_GEN7;
 473                         break;
 474                 case BCS:
 475                         mmio = BLT_HWS_PGA_GEN7;
 476                         break;
 477                 /*
 478                  * VCS2 actually doesn't exist on Gen7. Only shut up
 479                  * gcc switch check warning
 480                  */
 481                 case VCS2:
 482                 case VCS:
 483                         mmio = BSD_HWS_PGA_GEN7;
 484                         break;
 485                 case VECS:
 486                         mmio = VEBOX_HWS_PGA_GEN7;
 487                         break;
 488                 }
 489         } else if (IS_GEN6(engine->dev)) {
 490                 mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
 491         } else {
 492                 /* XXX: gen8 returns to sanity */
 493                 mmio = RING_HWS_PGA(engine->mmio_base);
 494         }
 495
 496         I915_WRITE(mmio, (u32)engine->status_page.gfx_addr);
 497         POSTING_READ(mmio);
 498
 499         /*
 500          * Flush the TLB for this page
 501          *
 502          * FIXME: These two bits have disappeared on gen8, so a question
 503          * arises: do we still need this and if so how should we go about
 504          * invalidating the TLB?
 505          */
 506         if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
 507                 i915_reg_t reg = RING_INSTPM(engine->mmio_base);
 508
 509                 /* ring should be idle before issuing a sync flush*/
 510                 WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0);
 511
 512                 I915_WRITE(reg,
 513                            _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
 514                                               INSTPM_SYNC_FLUSH));
 515                 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
 516                              1000))
 517                         DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
 518                                   engine->name);
 519         }
 520 }
 521
 522 static bool stop_ring(struct intel_engine_cs *engine)
 523 {
 524         struct drm_i915_private *dev_priv = to_i915(engine->dev);
 525
 526         if (!IS_GEN2(engine->dev)) {
 527                 I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING));
 528                 if (wait_for((I915_READ_MODE(engine) & MODE_IDLE) != 0, 1000)) {
 529                         DRM_ERROR("%s : timed out trying to stop ring\n",
 530                                   engine->name);
 531                         /* Sometimes we observe that the idle flag is not
 532                          * set even though the ring is empty. So double
 533                          * check before giving up.
 534                          */
 535                         if (I915_READ_HEAD(engine) != I915_READ_TAIL(engine))
 536                                 return false;
 537                 }
 538         }
 539
 540         I915_WRITE_CTL(engine, 0);
 541         I915_WRITE_HEAD(engine, 0);
 542         engine->write_tail(engine, 0);
 543
 544         if (!IS_GEN2(engine->dev)) {
 545                 (void)I915_READ_CTL(engine);
 546                 I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING));
 547         }
 548
 549         return (I915_READ_HEAD(engine) & HEAD_ADDR) == 0;
 550 }
 551
 552 void intel_engine_init_hangcheck(struct intel_engine_cs *engine)
 553 {
 554         memset(&engine->hangcheck, 0, sizeof(engine->hangcheck));
 555 }
 556
 557 static int init_ring_common(struct intel_engine_cs *engine)
 558 {
 559         struct drm_device *dev = engine->dev;
 560         struct drm_i915_private *dev_priv = dev->dev_private;
 561         struct intel_ringbuffer *ringbuf = engine->buffer;
 562         struct drm_i915_gem_object *obj = ringbuf->obj;
 563         int ret = 0;
 564
 565         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
 566
 567         if (!stop_ring(engine)) {
 568                 /* G45 ring initialization often fails to reset head to zero */
 569                 DRM_DEBUG_KMS("%s head not reset to zero "
 570                               "ctl %08x head %08x tail %08x start %08x\n",
 571                               engine->name,
 572                               I915_READ_CTL(engine),
 573                               I915_READ_HEAD(engine),
 574                               I915_READ_TAIL(engine),
 575                               I915_READ_START(engine));
 576
 577                 if (!stop_ring(engine)) {
 578                         DRM_ERROR("failed to set %s head to zero "
 579                                   "ctl %08x head %08x tail %08x start %08x\n",
 580                                   engine->name,
 581                                   I915_READ_CTL(engine),
 582                                   I915_READ_HEAD(engine),
 583                                   I915_READ_TAIL(engine),
 584                                   I915_READ_START(engine));
 585                         ret = -EIO;
 586                         goto out;
 587                 }
 588         }
 589
 590         if (I915_NEED_GFX_HWS(dev))
 591                 intel_ring_setup_status_page(engine);
 592         else
 593                 ring_setup_phys_status_page(engine);
 594
 595         /* Enforce ordering by reading HEAD register back */
 596         I915_READ_HEAD(engine);
 597
 598         /* Initialize the ring. This must happen _after_ we've cleared the ring
 599          * registers with the above sequence (the readback of the HEAD registers
 600          * also enforces ordering), otherwise the hw might lose the new ring
 601          * register values. */
 602         I915_WRITE_START(engine, i915_gem_obj_ggtt_offset(obj));
 603
 604         /* WaClearRingBufHeadRegAtInit:ctg,elk */
 605         if (I915_READ_HEAD(engine))
 606                 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
 607                           engine->name, I915_READ_HEAD(engine));
 608         I915_WRITE_HEAD(engine, 0);
 609         (void)I915_READ_HEAD(engine);
 610
 611         I915_WRITE_CTL(engine,
 612                         ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES)
 613                         | RING_VALID);
 614
 615         /* If the head is still not zero, the ring is dead */
 616         if (wait_for((I915_READ_CTL(engine) & RING_VALID) != 0 &&
 617                      I915_READ_START(engine) == i915_gem_obj_ggtt_offset(obj) &&
 618                      (I915_READ_HEAD(engine) & HEAD_ADDR) == 0, 50)) {
 619                 DRM_ERROR("%s initialization failed "
 620                           "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
 621                           engine->name,
 622                           I915_READ_CTL(engine),
 623                           I915_READ_CTL(engine) & RING_VALID,
 624                           I915_READ_HEAD(engine), I915_READ_TAIL(engine),
 625                           I915_READ_START(engine),
 626                           (unsigned long)i915_gem_obj_ggtt_offset(obj));
 627                 ret = -EIO;
 628                 goto out;
 629         }
 630
 631         ringbuf->last_retired_head = -1;
 632         ringbuf->head = I915_READ_HEAD(engine);
 633         ringbuf->tail = I915_READ_TAIL(engine) & TAIL_ADDR;
 634         intel_ring_update_space(ringbuf);
 635
 636         intel_engine_init_hangcheck(engine);
 637
 638 out:
 639         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
 640
 641         return ret;
 642 }
 643
 644 void
 645 intel_fini_pipe_control(struct intel_engine_cs *engine)
 646 {
 647         struct drm_device *dev = engine->dev;
 648
 649         if (engine->scratch.obj == NULL)
 650                 return;
 651
 652         if (INTEL_INFO(dev)->gen >= 5) {
 653                 kunmap(sg_page(engine->scratch.obj->pages->sgl));
 654                 i915_gem_object_ggtt_unpin(engine->scratch.obj);
 655         }
 656
 657         drm_gem_object_unreference(&engine->scratch.obj->base);
 658         engine->scratch.obj = NULL;
 659 }
 660
 661 int
 662 intel_init_pipe_control(struct intel_engine_cs *engine)
 663 {
 664         int ret;
 665
 666         WARN_ON(engine->scratch.obj);
 667
 668         engine->scratch.obj = i915_gem_alloc_object(engine->dev, 4096);
 669         if (engine->scratch.obj == NULL) {
 670                 DRM_ERROR("Failed to allocate seqno page\n");
 671                 ret = -ENOMEM;
 672                 goto err;
 673         }
 674
 675         ret = i915_gem_object_set_cache_level(engine->scratch.obj,
 676                                               I915_CACHE_LLC);
 677         if (ret)
 678                 goto err_unref;
 679
 680         ret = i915_gem_obj_ggtt_pin(engine->scratch.obj, 4096, 0);
 681         if (ret)
 682                 goto err_unref;
 683
 684         engine->scratch.gtt_offset = i915_gem_obj_ggtt_offset(engine->scratch.obj);
 685         engine->scratch.cpu_page = kmap(sg_page(engine->scratch.obj->pages->sgl));
 686         if (engine->scratch.cpu_page == NULL) {
 687                 ret = -ENOMEM;
 688                 goto err_unpin;
 689         }
 690
 691         DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
 692                          engine->name, engine->scratch.gtt_offset);
 693         return 0;
 694
 695 err_unpin:
 696         i915_gem_object_ggtt_unpin(engine->scratch.obj);
 697 err_unref:
 698         drm_gem_object_unreference(&engine->scratch.obj->base);
 699 err:
 700         return ret;
 701 }
 702
 703 static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req)
 704 {
 705         int ret, i;
 706         struct intel_engine_cs *engine = req->engine;
 707         struct drm_device *dev = engine->dev;
 708         struct drm_i915_private *dev_priv = dev->dev_private;
 709         struct i915_workarounds *w = &dev_priv->workarounds;
 710
 711         if (w->count == 0)
 712                 return 0;
 713
 714         engine->gpu_caches_dirty = true;
 715         ret = intel_ring_flush_all_caches(req);
 716         if (ret)
 717                 return ret;
 718
 719         ret = intel_ring_begin(req, (w->count * 2 + 2));
 720         if (ret)
 721                 return ret;
 722
 723         intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(w->count));
 724         for (i = 0; i < w->count; i++) {
 725                 intel_ring_emit_reg(engine, w->reg[i].addr);
 726                 intel_ring_emit(engine, w->reg[i].value);
 727         }
 728         intel_ring_emit(engine, MI_NOOP);
 729
 730         intel_ring_advance(engine);
 731
 732         engine->gpu_caches_dirty = true;
 733         ret = intel_ring_flush_all_caches(req);
 734         if (ret)
 735                 return ret;
 736
 737         DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count);
 738
 739         return 0;
 740 }
 741
 742 static int intel_rcs_ctx_init(struct drm_i915_gem_request *req)
 743 {
 744         int ret;
 745
 746         ret = intel_ring_workarounds_emit(req);
 747         if (ret != 0)
 748                 return ret;
 749
 750         ret = i915_gem_render_state_init(req);
 751         if (ret)
 752                 return ret;
 753
 754         return 0;
 755 }
 756
 757 static int wa_add(struct drm_i915_private *dev_priv,
 758                   i915_reg_t addr,
 759                   const u32 mask, const u32 val)
 760 {
 761         const u32 idx = dev_priv->workarounds.count;
 762
 763         if (WARN_ON(idx >= I915_MAX_WA_REGS))
 764                 return -ENOSPC;
 765
 766         dev_priv->workarounds.reg[idx].addr = addr;
 767         dev_priv->workarounds.reg[idx].value = val;
 768         dev_priv->workarounds.reg[idx].mask = mask;
 769
 770         dev_priv->workarounds.count++;
 771
 772         return 0;
 773 }
 774
 775 #define WA_REG(addr, mask, val) do { \
 776                 const int r = wa_add(dev_priv, (addr), (mask), (val)); \
 777                 if (r) \
 778                         return r; \
 779         } while (0)
 780
 781 #define WA_SET_BIT_MASKED(addr, mask) \
 782         WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
 783
 784 #define WA_CLR_BIT_MASKED(addr, mask) \
 785         WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
 786
 787 #define WA_SET_FIELD_MASKED(addr, mask, value) \
 788         WA_REG(addr, mask, _MASKED_FIELD(mask, value))
 789
 790 #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
 791 #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
 792
 793 #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
 794
 795 static int wa_ring_whitelist_reg(struct intel_engine_cs *engine,
 796                                  i915_reg_t reg)
 797 {
 798         struct drm_i915_private *dev_priv = engine->dev->dev_private;
 799         struct i915_workarounds *wa = &dev_priv->workarounds;
 800         const uint32_t index = wa->hw_whitelist_count[engine->id];
 801
 802         if (WARN_ON(index >= RING_MAX_NONPRIV_SLOTS))
 803                 return -EINVAL;
 804
 805         WA_WRITE(RING_FORCE_TO_NONPRIV(engine->mmio_base, index),
 806                  i915_mmio_reg_offset(reg));
 807         wa->hw_whitelist_count[engine->id]++;
 808
 809         return 0;
 810 }
 811
 812 static int gen8_init_workarounds(struct intel_engine_cs *engine)
 813 {
 814         struct drm_device *dev = engine->dev;
 815         struct drm_i915_private *dev_priv = dev->dev_private;
 816
 817         WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
 818
 819         /* WaDisableAsyncFlipPerfMode:bdw,chv */
 820         WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
 821
 822         /* WaDisablePartialInstShootdown:bdw,chv */
 823         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 824                           PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
 825
 826         /* Use Force Non-Coherent whenever executing a 3D context. This is a
 827          * workaround for for a possible hang in the unlikely event a TLB
 828          * invalidation occurs during a PSD flush.
 829          */
 830         /* WaForceEnableNonCoherent:bdw,chv */
 831         /* WaHdcDisableFetchWhenMasked:bdw,chv */
 832         WA_SET_BIT_MASKED(HDC_CHICKEN0,
 833                           HDC_DONOT_FETCH_MEM_WHEN_MASKED |
 834                           HDC_FORCE_NON_COHERENT);
 835
 836         /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
 837          * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
 838          *  polygons in the same 8x4 pixel/sample area to be processed without
 839          *  stalling waiting for the earlier ones to write to Hierarchical Z
 840          *  buffer."
 841          *
 842          * This optimization is off by default for BDW and CHV; turn it on.
 843          */
 844         WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
 845
 846         /* Wa4x4STCOptimizationDisable:bdw,chv */
 847         WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
 848
 849         /*
 850          * BSpec recommends 8x4 when MSAA is used,
 851          * however in practice 16x4 seems fastest.
 852          *
 853          * Note that PS/WM thread counts depend on the WIZ hashing
 854          * disable bit, which we don't touch here, but it's good
 855          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
 856          */
 857         WA_SET_FIELD_MASKED(GEN7_GT_MODE,
 858                             GEN6_WIZ_HASHING_MASK,
 859                             GEN6_WIZ_HASHING_16x4);
 860
 861         return 0;
 862 }
 863
 864 static int bdw_init_workarounds(struct intel_engine_cs *engine)
 865 {
 866         int ret;
 867         struct drm_device *dev = engine->dev;
 868         struct drm_i915_private *dev_priv = dev->dev_private;
 869
 870         ret = gen8_init_workarounds(engine);
 871         if (ret)
 872                 return ret;
 873
 874         /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
 875         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
 876
 877         /* WaDisableDopClockGating:bdw */
 878         WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
 879                           DOP_CLOCK_GATING_DISABLE);
 880
 881         WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
 882                           GEN8_SAMPLER_POWER_BYPASS_DIS);
 883
 884         WA_SET_BIT_MASKED(HDC_CHICKEN0,
 885                           /* WaForceContextSaveRestoreNonCoherent:bdw */
 886                           HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
 887                           /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
 888                           (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
 889
 890         return 0;
 891 }
 892
 893 static int chv_init_workarounds(struct intel_engine_cs *engine)
 894 {
 895         int ret;
 896         struct drm_device *dev = engine->dev;
 897         struct drm_i915_private *dev_priv = dev->dev_private;
 898
 899         ret = gen8_init_workarounds(engine);
 900         if (ret)
 901                 return ret;
 902
 903         /* WaDisableThreadStallDopClockGating:chv */
 904         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
 905
 906         /* Improve HiZ throughput on CHV. */
 907         WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
 908
 909         return 0;
 910 }
 911
 912 static int gen9_init_workarounds(struct intel_engine_cs *engine)
 913 {
 914         struct drm_device *dev = engine->dev;
 915         struct drm_i915_private *dev_priv = dev->dev_private;
 916         uint32_t tmp;
 917         int ret;
 918
 919         /* WaEnableLbsSlaRetryTimerDecrement:skl */
 920         I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
 921                    GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
 922
 923         /* WaDisableKillLogic:bxt,skl */
 924         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
 925                    ECOCHK_DIS_TLB);
 926
 927         /* WaClearFlowControlGpgpuContextSave:skl,bxt */
 928         /* WaDisablePartialInstShootdown:skl,bxt */
 929         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 930                           FLOW_CONTROL_ENABLE |
 931                           PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
 932
 933         /* Syncing dependencies between camera and graphics:skl,bxt */
 934         WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
 935                           GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
 936
 937         /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */
 938         if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
 939             IS_BXT_REVID(dev, 0, BXT_REVID_A1))
 940                 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
 941                                   GEN9_DG_MIRROR_FIX_ENABLE);
 942
 943         /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
 944         if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
 945             IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
 946                 WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
 947                                   GEN9_RHWO_OPTIMIZATION_DISABLE);
 948                 /*
 949                  * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set
 950                  * but we do that in per ctx batchbuffer as there is an issue
 951                  * with this register not getting restored on ctx restore
 952                  */
 953         }
 954
 955         /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt */
 956         /* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt */
 957         WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
 958                           GEN9_ENABLE_YV12_BUGFIX |
 959                           GEN9_ENABLE_GPGPU_PREEMPTION);
 960
 961         /* Wa4x4STCOptimizationDisable:skl,bxt */
 962         /* WaDisablePartialResolveInVc:skl,bxt */
 963         WA_SET_BIT_MASKED(CACHE_MODE_1, (GEN8_4x4_STC_OPTIMIZATION_DISABLE |
 964                                          GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE));
 965
 966         /* WaCcsTlbPrefetchDisable:skl,bxt */
 967         WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
 968                           GEN9_CCS_TLB_PREFETCH_ENABLE);
 969
 970         /* WaDisableMaskBasedCammingInRCC:skl,bxt */
 971         if (IS_SKL_REVID(dev, SKL_REVID_C0, SKL_REVID_C0) ||
 972             IS_BXT_REVID(dev, 0, BXT_REVID_A1))
 973                 WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
 974                                   PIXEL_MASK_CAMMING_DISABLE);
 975
 976         /* WaForceContextSaveRestoreNonCoherent:skl,bxt */
 977         tmp = HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT;
 978         if (IS_SKL_REVID(dev, SKL_REVID_F0, REVID_FOREVER) ||
 979             IS_BXT_REVID(dev, BXT_REVID_B0, REVID_FOREVER))
 980                 tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE;
 981         WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp);
 982
 983         /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt */
 984         if (IS_SKYLAKE(dev) || IS_BXT_REVID(dev, 0, BXT_REVID_B0))
 985                 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
 986                                   GEN8_SAMPLER_POWER_BYPASS_DIS);
 987
 988         /* WaDisableSTUnitPowerOptimization:skl,bxt */
 989         WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
 990
 991         /* WaOCLCoherentLineFlush:skl,bxt */
 992         I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
 993                                     GEN8_LQSC_FLUSH_COHERENT_LINES));
 994
 995         /* WaEnablePreemptionGranularityControlByUMD:skl,bxt */
 996         ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1);
 997         if (ret)
 998                 return ret;
 999
1000         /* WaAllowUMDToModifyHDCChicken1:skl,bxt */
1001         ret = wa_ring_whitelist_reg(engine, GEN8_HDC_CHICKEN1);
1002         if (ret)
1003                 return ret;
1004
1005         return 0;
1006 }
1007
1008 static int skl_tune_iz_hashing(struct intel_engine_cs *engine)
1009 {
1010         struct drm_device *dev = engine->dev;
1011         struct drm_i915_private *dev_priv = dev->dev_private;
1012         u8 vals[3] = { 0, 0, 0 };
1013         unsigned int i;
1014
1015         for (i = 0; i < 3; i++) {
1016                 u8 ss;
1017
1018                 /*
1019                  * Only consider slices where one, and only one, subslice has 7
1020                  * EUs
1021                  */
1022                 if (!is_power_of_2(dev_priv->info.subslice_7eu[i]))
1023                         continue;
1024
1025                 /*
1026                  * subslice_7eu[i] != 0 (because of the check above) and
1027                  * ss_max == 4 (maximum number of subslices possible per slice)
1028                  *
1029                  * ->    0 <= ss <= 3;
1030                  */
1031                 ss = ffs(dev_priv->info.subslice_7eu[i]) - 1;
1032                 vals[i] = 3 - ss;
1033         }
1034
1035         if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0)
1036                 return 0;
1037
1038         /* Tune IZ hashing. See intel_device_info_runtime_init() */
1039         WA_SET_FIELD_MASKED(GEN7_GT_MODE,
1040                             GEN9_IZ_HASHING_MASK(2) |
1041                             GEN9_IZ_HASHING_MASK(1) |
1042                             GEN9_IZ_HASHING_MASK(0),
1043                             GEN9_IZ_HASHING(2, vals[2]) |
1044                             GEN9_IZ_HASHING(1, vals[1]) |
1045                             GEN9_IZ_HASHING(0, vals[0]));
1046
1047         return 0;
1048 }
1049
1050 static int skl_init_workarounds(struct intel_engine_cs *engine)
1051 {
1052         int ret;
1053         struct drm_device *dev = engine->dev;
1054         struct drm_i915_private *dev_priv = dev->dev_private;
1055
1056         ret = gen9_init_workarounds(engine);
1057         if (ret)
1058                 return ret;
1059
1060         /*
1061          * Actual WA is to disable percontext preemption granularity control
1062          * until D0 which is the default case so this is equivalent to
1063          * !WaDisablePerCtxtPreemptionGranularityControl:skl
1064          */
1065         if (IS_SKL_REVID(dev, SKL_REVID_E0, REVID_FOREVER)) {
1066                 I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1,
1067                            _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL));
1068         }
1069
1070         if (IS_SKL_REVID(dev, 0, SKL_REVID_D0)) {
1071                 /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
1072                 I915_WRITE(FF_SLICE_CS_CHICKEN2,
1073                            _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE));
1074         }
1075
1076         /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes
1077          * involving this register should also be added to WA batch as required.
1078          */
1079         if (IS_SKL_REVID(dev, 0, SKL_REVID_E0))
1080                 /* WaDisableLSQCROPERFforOCL:skl */
1081                 I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
1082                            GEN8_LQSC_RO_PERF_DIS);
1083
1084         /* WaEnableGapsTsvCreditFix:skl */
1085         if (IS_SKL_REVID(dev, SKL_REVID_C0, REVID_FOREVER)) {
1086                 I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
1087                                            GEN9_GAPS_TSV_CREDIT_DISABLE));
1088         }
1089
1090         /* WaDisablePowerCompilerClockGating:skl */
1091         if (IS_SKL_REVID(dev, SKL_REVID_B0, SKL_REVID_B0))
1092                 WA_SET_BIT_MASKED(HIZ_CHICKEN,
1093                                   BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
1094
1095         /* This is tied to WaForceContextSaveRestoreNonCoherent */
1096         if (IS_SKL_REVID(dev, 0, REVID_FOREVER)) {
1097                 /*
1098                  *Use Force Non-Coherent whenever executing a 3D context. This
1099                  * is a workaround for a possible hang in the unlikely event
1100                  * a TLB invalidation occurs during a PSD flush.
1101                  */
1102                 /* WaForceEnableNonCoherent:skl */
1103                 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1104                                   HDC_FORCE_NON_COHERENT);
1105
1106                 /* WaDisableHDCInvalidation:skl */
1107                 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
1108                            BDW_DISABLE_HDC_INVALIDATION);
1109         }
1110
1111         /* WaBarrierPerformanceFixDisable:skl */
1112         if (IS_SKL_REVID(dev, SKL_REVID_C0, SKL_REVID_D0))
1113                 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1114                                   HDC_FENCE_DEST_SLM_DISABLE |
1115                                   HDC_BARRIER_PERFORMANCE_DISABLE);
1116
1117         /* WaDisableSbeCacheDispatchPortSharing:skl */
1118         if (IS_SKL_REVID(dev, 0, SKL_REVID_F0))
1119                 WA_SET_BIT_MASKED(
1120                         GEN7_HALF_SLICE_CHICKEN1,
1121                         GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1122
1123         /* WaDisableLSQCROPERFforOCL:skl */
1124         ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
1125         if (ret)
1126                 return ret;
1127
1128         return skl_tune_iz_hashing(engine);
1129 }
1130
1131 static int bxt_init_workarounds(struct intel_engine_cs *engine)
1132 {
1133         int ret;
1134         struct drm_device *dev = engine->dev;
1135         struct drm_i915_private *dev_priv = dev->dev_private;
1136
1137         ret = gen9_init_workarounds(engine);
1138         if (ret)
1139                 return ret;
1140
1141         /* WaStoreMultiplePTEenable:bxt */
1142         /* This is a requirement according to Hardware specification */
1143         if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
1144                 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
1145
1146         /* WaSetClckGatingDisableMedia:bxt */
1147         if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
1148                 I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) &
1149                                             ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE));
1150         }
1151
1152         /* WaDisableThreadStallDopClockGating:bxt */
1153         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
1154                           STALL_DOP_GATING_DISABLE);
1155
1156         /* WaDisableSbeCacheDispatchPortSharing:bxt */
1157         if (IS_BXT_REVID(dev, 0, BXT_REVID_B0)) {
1158                 WA_SET_BIT_MASKED(
1159                         GEN7_HALF_SLICE_CHICKEN1,
1160                         GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1161         }
1162
1163         /* WaDisableObjectLevelPreemptionForTrifanOrPolygon:bxt */
1164         /* WaDisableObjectLevelPreemptionForInstancedDraw:bxt */
1165         /* WaDisableObjectLevelPreemtionForInstanceId:bxt */
1166         /* WaDisableLSQCROPERFforOCL:bxt */
1167         if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
1168                 ret = wa_ring_whitelist_reg(engine, GEN9_CS_DEBUG_MODE1);
1169                 if (ret)
1170                         return ret;
1171
1172                 ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
1173                 if (ret)
1174                         return ret;
1175         }
1176
1177         return 0;
1178 }
1179
1180 int init_workarounds_ring(struct intel_engine_cs *engine)
1181 {
1182         struct drm_device *dev = engine->dev;
1183         struct drm_i915_private *dev_priv = dev->dev_private;
1184
1185         WARN_ON(engine->id != RCS);
1186
1187         dev_priv->workarounds.count = 0;
1188         dev_priv->workarounds.hw_whitelist_count[RCS] = 0;
1189
1190         if (IS_BROADWELL(dev))
1191                 return bdw_init_workarounds(engine);
1192
1193         if (IS_CHERRYVIEW(dev))
1194                 return chv_init_workarounds(engine);
1195
1196         if (IS_SKYLAKE(dev))
1197                 return skl_init_workarounds(engine);
1198
1199         if (IS_BROXTON(dev))
1200                 return bxt_init_workarounds(engine);
1201
1202         return 0;
1203 }
1204
1205 static int init_render_ring(struct intel_engine_cs *engine)
1206 {
1207         struct drm_device *dev = engine->dev;
1208         struct drm_i915_private *dev_priv = dev->dev_private;
1209         int ret = init_ring_common(engine);
1210         if (ret)
1211                 return ret;
1212
1213         /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
1214         if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7)
1215                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
1216
1217         /* We need to disable the AsyncFlip performance optimisations in order
1218          * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1219          * programmed to '1' on all products.
1220          *
1221          * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
1222          */
1223         if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
1224                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1225
1226         /* Required for the hardware to program scanline values for waiting */
1227         /* WaEnableFlushTlbInvalidationMode:snb */
1228         if (INTEL_INFO(dev)->gen == 6)
1229                 I915_WRITE(GFX_MODE,
1230                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
1231
1232         /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
1233         if (IS_GEN7(dev))
1234                 I915_WRITE(GFX_MODE_GEN7,
1235                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
1236                            _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
1237
1238         if (IS_GEN6(dev)) {
1239                 /* From the Sandybridge PRM, volume 1 part 3, page 24:
1240                  * "If this bit is set, STCunit will have LRA as replacement
1241                  *  policy. [...] This bit must be reset.  LRA replacement
1242                  *  policy is not supported."
1243                  */
1244                 I915_WRITE(CACHE_MODE_0,
1245                            _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
1246         }
1247
1248         if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
1249                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
1250
1251         if (HAS_L3_DPF(dev))
1252                 I915_WRITE_IMR(engine, ~GT_PARITY_ERROR(dev));
1253
1254         return init_workarounds_ring(engine);
1255 }
1256
1257 static void render_ring_cleanup(struct intel_engine_cs *engine)
1258 {
1259         struct drm_device *dev = engine->dev;
1260         struct drm_i915_private *dev_priv = dev->dev_private;
1261
1262         if (dev_priv->semaphore_obj) {
1263                 i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj);
1264                 drm_gem_object_unreference(&dev_priv->semaphore_obj->base);
1265                 dev_priv->semaphore_obj = NULL;
1266         }
1267
1268         intel_fini_pipe_control(engine);
1269 }
1270
1271 static int gen8_rcs_signal(struct drm_i915_gem_request *signaller_req,
1272                            unsigned int num_dwords)
1273 {
1274 #define MBOX_UPDATE_DWORDS 8
1275         struct intel_engine_cs *signaller = signaller_req->engine;
1276         struct drm_device *dev = signaller->dev;
1277         struct drm_i915_private *dev_priv = dev->dev_private;
1278         struct intel_engine_cs *waiter;
1279         enum intel_engine_id id;
1280         int ret, num_rings;
1281
1282         num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1283         num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1284 #undef MBOX_UPDATE_DWORDS
1285
1286         ret = intel_ring_begin(signaller_req, num_dwords);
1287         if (ret)
1288                 return ret;
1289
1290         for_each_engine_id(waiter, dev_priv, id) {
1291                 u32 seqno;
1292                 u64 gtt_offset = signaller->semaphore.signal_ggtt[id];
1293                 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1294                         continue;
1295
1296                 seqno = i915_gem_request_get_seqno(signaller_req);
1297                 intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
1298                 intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |
1299                                            PIPE_CONTROL_QW_WRITE |
1300                                            PIPE_CONTROL_FLUSH_ENABLE);
1301                 intel_ring_emit(signaller, lower_32_bits(gtt_offset));
1302                 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
1303                 intel_ring_emit(signaller, seqno);
1304                 intel_ring_emit(signaller, 0);
1305                 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1306                                            MI_SEMAPHORE_TARGET(waiter->hw_id));
1307                 intel_ring_emit(signaller, 0);
1308         }
1309
1310         return 0;
1311 }
1312
1313 static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req,
1314                            unsigned int num_dwords)
1315 {
1316 #define MBOX_UPDATE_DWORDS 6
1317         struct intel_engine_cs *signaller = signaller_req->engine;
1318         struct drm_device *dev = signaller->dev;
1319         struct drm_i915_private *dev_priv = dev->dev_private;
1320         struct intel_engine_cs *waiter;
1321         enum intel_engine_id id;
1322         int ret, num_rings;
1323
1324         num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1325         num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1326 #undef MBOX_UPDATE_DWORDS
1327
1328         ret = intel_ring_begin(signaller_req, num_dwords);
1329         if (ret)
1330                 return ret;
1331
1332         for_each_engine_id(waiter, dev_priv, id) {
1333                 u32 seqno;
1334                 u64 gtt_offset = signaller->semaphore.signal_ggtt[id];
1335                 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1336                         continue;
1337
1338                 seqno = i915_gem_request_get_seqno(signaller_req);
1339                 intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |
1340                                            MI_FLUSH_DW_OP_STOREDW);
1341                 intel_ring_emit(signaller, lower_32_bits(gtt_offset) |
1342                                            MI_FLUSH_DW_USE_GTT);
1343                 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
1344                 intel_ring_emit(signaller, seqno);
1345                 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1346                                            MI_SEMAPHORE_TARGET(waiter->hw_id));
1347                 intel_ring_emit(signaller, 0);
1348         }
1349
1350         return 0;
1351 }
1352
1353 static int gen6_signal(struct drm_i915_gem_request *signaller_req,
1354                        unsigned int num_dwords)
1355 {
1356         struct intel_engine_cs *signaller = signaller_req->engine;
1357         struct drm_device *dev = signaller->dev;
1358         struct drm_i915_private *dev_priv = dev->dev_private;
1359         struct intel_engine_cs *useless;
1360         enum intel_engine_id id;
1361         int ret, num_rings;
1362
1363 #define MBOX_UPDATE_DWORDS 3
1364         num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1365         num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
1366 #undef MBOX_UPDATE_DWORDS
1367
1368         ret = intel_ring_begin(signaller_req, num_dwords);
1369         if (ret)
1370                 return ret;
1371
1372         for_each_engine_id(useless, dev_priv, id) {
1373                 i915_reg_t mbox_reg = signaller->semaphore.mbox.signal[id];
1374
1375                 if (i915_mmio_reg_valid(mbox_reg)) {
1376                         u32 seqno = i915_gem_request_get_seqno(signaller_req);
1377
1378                         intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
1379                         intel_ring_emit_reg(signaller, mbox_reg);
1380                         intel_ring_emit(signaller, seqno);
1381                 }
1382         }
1383
1384         /* If num_dwords was rounded, make sure the tail pointer is correct */
1385         if (num_rings % 2 == 0)
1386                 intel_ring_emit(signaller, MI_NOOP);
1387
1388         return 0;
1389 }
1390
1391 /**
1392  * gen6_add_request - Update the semaphore mailbox registers
1393  *
1394  * @request - request to write to the ring
1395  *
1396  * Update the mailbox registers in the *other* rings with the current seqno.
1397  * This acts like a signal in the canonical semaphore.
1398  */
1399 static int
1400 gen6_add_request(struct drm_i915_gem_request *req)
1401 {
1402         struct intel_engine_cs *engine = req->engine;
1403         int ret;
1404
1405         if (engine->semaphore.signal)
1406                 ret = engine->semaphore.signal(req, 4);
1407         else
1408                 ret = intel_ring_begin(req, 4);
1409
1410         if (ret)
1411                 return ret;
1412
1413         intel_ring_emit(engine, MI_STORE_DWORD_INDEX);
1414         intel_ring_emit(engine,
1415                         I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1416         intel_ring_emit(engine, i915_gem_request_get_seqno(req));
1417         intel_ring_emit(engine, MI_USER_INTERRUPT);
1418         __intel_ring_advance(engine);
1419
1420         return 0;
1421 }
1422
1423 static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
1424                                               u32 seqno)
1425 {
1426         struct drm_i915_private *dev_priv = dev->dev_private;
1427         return dev_priv->last_seqno < seqno;
1428 }
1429
1430 /**
1431  * intel_ring_sync - sync the waiter to the signaller on seqno
1432  *
1433  * @waiter - ring that is waiting
1434  * @signaller - ring which has, or will signal
1435  * @seqno - seqno which the waiter will block on
1436  */
1437
1438 static int
1439 gen8_ring_sync(struct drm_i915_gem_request *waiter_req,
1440                struct intel_engine_cs *signaller,
1441                u32 seqno)
1442 {
1443         struct intel_engine_cs *waiter = waiter_req->engine;
1444         struct drm_i915_private *dev_priv = waiter->dev->dev_private;
1445         int ret;
1446
1447         ret = intel_ring_begin(waiter_req, 4);
1448         if (ret)
1449                 return ret;
1450
1451         intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |
1452                                 MI_SEMAPHORE_GLOBAL_GTT |
1453                                 MI_SEMAPHORE_POLL |
1454                                 MI_SEMAPHORE_SAD_GTE_SDD);
1455         intel_ring_emit(waiter, seqno);
1456         intel_ring_emit(waiter,
1457                         lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1458         intel_ring_emit(waiter,
1459                         upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1460         intel_ring_advance(waiter);
1461         return 0;
1462 }
1463
1464 static int
1465 gen6_ring_sync(struct drm_i915_gem_request *waiter_req,
1466                struct intel_engine_cs *signaller,
1467                u32 seqno)
1468 {
1469         struct intel_engine_cs *waiter = waiter_req->engine;
1470         u32 dw1 = MI_SEMAPHORE_MBOX |
1471                   MI_SEMAPHORE_COMPARE |
1472                   MI_SEMAPHORE_REGISTER;
1473         u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id];
1474         int ret;
1475
1476         /* Throughout all of the GEM code, seqno passed implies our current
1477          * seqno is >= the last seqno executed. However for hardware the
1478          * comparison is strictly greater than.
1479          */
1480         seqno -= 1;
1481
1482         WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
1483
1484         ret = intel_ring_begin(waiter_req, 4);
1485         if (ret)
1486                 return ret;
1487
1488         /* If seqno wrap happened, omit the wait with no-ops */
1489         if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
1490                 intel_ring_emit(waiter, dw1 | wait_mbox);
1491                 intel_ring_emit(waiter, seqno);
1492                 intel_ring_emit(waiter, 0);
1493                 intel_ring_emit(waiter, MI_NOOP);
1494         } else {
1495                 intel_ring_emit(waiter, MI_NOOP);
1496                 intel_ring_emit(waiter, MI_NOOP);
1497                 intel_ring_emit(waiter, MI_NOOP);
1498                 intel_ring_emit(waiter, MI_NOOP);
1499         }
1500         intel_ring_advance(waiter);
1501
1502         return 0;
1503 }
1504
1505 #define PIPE_CONTROL_FLUSH(ring__, addr__)                                      \
1506 do {                                                                    \
1507         intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |                \
1508                  PIPE_CONTROL_DEPTH_STALL);                             \
1509         intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT);                    \
1510         intel_ring_emit(ring__, 0);                                                     \
1511         intel_ring_emit(ring__, 0);                                                     \
1512 } while (0)
1513
1514 static int
1515 pc_render_add_request(struct drm_i915_gem_request *req)
1516 {
1517         struct intel_engine_cs *engine = req->engine;
1518         u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
1519         int ret;
1520
1521         /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
1522          * incoherent with writes to memory, i.e. completely fubar,
1523          * so we need to use PIPE_NOTIFY instead.
1524          *
1525          * However, we also need to workaround the qword write
1526          * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
1527          * memory before requesting an interrupt.
1528          */
1529         ret = intel_ring_begin(req, 32);
1530         if (ret)
1531                 return ret;
1532
1533         intel_ring_emit(engine,
1534                         GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1535                         PIPE_CONTROL_WRITE_FLUSH |
1536                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
1537         intel_ring_emit(engine,
1538                         engine->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1539         intel_ring_emit(engine, i915_gem_request_get_seqno(req));
1540         intel_ring_emit(engine, 0);
1541         PIPE_CONTROL_FLUSH(engine, scratch_addr);
1542         scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
1543         PIPE_CONTROL_FLUSH(engine, scratch_addr);
1544         scratch_addr += 2 * CACHELINE_BYTES;
1545         PIPE_CONTROL_FLUSH(engine, scratch_addr);
1546         scratch_addr += 2 * CACHELINE_BYTES;
1547         PIPE_CONTROL_FLUSH(engine, scratch_addr);
1548         scratch_addr += 2 * CACHELINE_BYTES;
1549         PIPE_CONTROL_FLUSH(engine, scratch_addr);
1550         scratch_addr += 2 * CACHELINE_BYTES;
1551         PIPE_CONTROL_FLUSH(engine, scratch_addr);
1552
1553         intel_ring_emit(engine,
1554                         GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1555                         PIPE_CONTROL_WRITE_FLUSH |
1556                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
1557                         PIPE_CONTROL_NOTIFY);
1558         intel_ring_emit(engine,
1559                         engine->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1560         intel_ring_emit(engine, i915_gem_request_get_seqno(req));
1561         intel_ring_emit(engine, 0);
1562         __intel_ring_advance(engine);
1563
1564         return 0;
1565 }
1566
1567 static void
1568 gen6_seqno_barrier(struct intel_engine_cs *engine)
1569 {
1570         struct drm_i915_private *dev_priv = engine->dev->dev_private;
1571
1572         /* Workaround to force correct ordering between irq and seqno writes on
1573          * ivb (and maybe also on snb) by reading from a CS register (like
1574          * ACTHD) before reading the status page.
1575          *
1576          * Note that this effectively stalls the read by the time it takes to
1577          * do a memory transaction, which more or less ensures that the write
1578          * from the GPU has sufficient time to invalidate the CPU cacheline.
1579          * Alternatively we could delay the interrupt from the CS ring to give
1580          * the write time to land, but that would incur a delay after every
1581          * batch i.e. much more frequent than a delay when waiting for the
1582          * interrupt (with the same net latency).
1583          *
1584          * Also note that to prevent whole machine hangs on gen7, we have to
1585          * take the spinlock to guard against concurrent cacheline access.
1586          */
1587         spin_lock_irq(&dev_priv->uncore.lock);
1588         POSTING_READ_FW(RING_ACTHD(engine->mmio_base));
1589         spin_unlock_irq(&dev_priv->uncore.lock);
1590 }
1591
1592 static u32
1593 ring_get_seqno(struct intel_engine_cs *engine)
1594 {
1595         return intel_read_status_page(engine, I915_GEM_HWS_INDEX);
1596 }
1597
1598 static void
1599 ring_set_seqno(struct intel_engine_cs *engine, u32 seqno)
1600 {
1601         intel_write_status_page(engine, I915_GEM_HWS_INDEX, seqno);
1602 }
1603
1604 static u32
1605 pc_render_get_seqno(struct intel_engine_cs *engine)
1606 {
1607         return engine->scratch.cpu_page[0];
1608 }
1609
1610 static void
1611 pc_render_set_seqno(struct intel_engine_cs *engine, u32 seqno)
1612 {
1613         engine->scratch.cpu_page[0] = seqno;
1614 }
1615
1616 static bool
1617 gen5_ring_get_irq(struct intel_engine_cs *engine)
1618 {
1619         struct drm_device *dev = engine->dev;
1620         struct drm_i915_private *dev_priv = dev->dev_private;
1621         unsigned long flags;
1622
1623         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1624                 return false;
1625
1626         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1627         if (engine->irq_refcount++ == 0)
1628                 gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask);
1629         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1630
1631         return true;
1632 }
1633
1634 static void
1635 gen5_ring_put_irq(struct intel_engine_cs *engine)
1636 {
1637         struct drm_device *dev = engine->dev;
1638         struct drm_i915_private *dev_priv = dev->dev_private;
1639         unsigned long flags;
1640
1641         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1642         if (--engine->irq_refcount == 0)
1643                 gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask);
1644         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1645 }
1646
1647 static bool
1648 i9xx_ring_get_irq(struct intel_engine_cs *engine)
1649 {
1650         struct drm_device *dev = engine->dev;
1651         struct drm_i915_private *dev_priv = dev->dev_private;
1652         unsigned long flags;
1653
1654         if (!intel_irqs_enabled(dev_priv))
1655                 return false;
1656
1657         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1658         if (engine->irq_refcount++ == 0) {
1659                 dev_priv->irq_mask &= ~engine->irq_enable_mask;
1660                 I915_WRITE(IMR, dev_priv->irq_mask);
1661                 POSTING_READ(IMR);
1662         }
1663         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1664
1665         return true;
1666 }
1667
1668 static void
1669 i9xx_ring_put_irq(struct intel_engine_cs *engine)
1670 {
1671         struct drm_device *dev = engine->dev;
1672         struct drm_i915_private *dev_priv = dev->dev_private;
1673         unsigned long flags;
1674
1675         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1676         if (--engine->irq_refcount == 0) {
1677                 dev_priv->irq_mask |= engine->irq_enable_mask;
1678                 I915_WRITE(IMR, dev_priv->irq_mask);
1679                 POSTING_READ(IMR);
1680         }
1681         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1682 }
1683
1684 static bool
1685 i8xx_ring_get_irq(struct intel_engine_cs *engine)
1686 {
1687         struct drm_device *dev = engine->dev;
1688         struct drm_i915_private *dev_priv = dev->dev_private;
1689         unsigned long flags;
1690
1691         if (!intel_irqs_enabled(dev_priv))
1692                 return false;
1693
1694         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1695         if (engine->irq_refcount++ == 0) {
1696                 dev_priv->irq_mask &= ~engine->irq_enable_mask;
1697                 I915_WRITE16(IMR, dev_priv->irq_mask);
1698                 POSTING_READ16(IMR);
1699         }
1700         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1701
1702         return true;
1703 }
1704
1705 static void
1706 i8xx_ring_put_irq(struct intel_engine_cs *engine)
1707 {
1708         struct drm_device *dev = engine->dev;
1709         struct drm_i915_private *dev_priv = dev->dev_private;
1710         unsigned long flags;
1711
1712         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1713         if (--engine->irq_refcount == 0) {
1714                 dev_priv->irq_mask |= engine->irq_enable_mask;
1715                 I915_WRITE16(IMR, dev_priv->irq_mask);
1716                 POSTING_READ16(IMR);
1717         }
1718         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1719 }
1720
1721 static int
1722 bsd_ring_flush(struct drm_i915_gem_request *req,
1723                u32     invalidate_domains,
1724                u32     flush_domains)
1725 {
1726         struct intel_engine_cs *engine = req->engine;
1727         int ret;
1728
1729         ret = intel_ring_begin(req, 2);
1730         if (ret)
1731                 return ret;
1732
1733         intel_ring_emit(engine, MI_FLUSH);
1734         intel_ring_emit(engine, MI_NOOP);
1735         intel_ring_advance(engine);
1736         return 0;
1737 }
1738
1739 static int
1740 i9xx_add_request(struct drm_i915_gem_request *req)
1741 {
1742         struct intel_engine_cs *engine = req->engine;
1743         int ret;
1744
1745         ret = intel_ring_begin(req, 4);
1746         if (ret)
1747                 return ret;
1748
1749         intel_ring_emit(engine, MI_STORE_DWORD_INDEX);
1750         intel_ring_emit(engine,
1751                         I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1752         intel_ring_emit(engine, i915_gem_request_get_seqno(req));
1753         intel_ring_emit(engine, MI_USER_INTERRUPT);
1754         __intel_ring_advance(engine);
1755
1756         return 0;
1757 }
1758
1759 static bool
1760 gen6_ring_get_irq(struct intel_engine_cs *engine)
1761 {
1762         struct drm_device *dev = engine->dev;
1763         struct drm_i915_private *dev_priv = dev->dev_private;
1764         unsigned long flags;
1765
1766         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1767                 return false;
1768
1769         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1770         if (engine->irq_refcount++ == 0) {
1771                 if (HAS_L3_DPF(dev) && engine->id == RCS)
1772                         I915_WRITE_IMR(engine,
1773                                        ~(engine->irq_enable_mask |
1774                                          GT_PARITY_ERROR(dev)));
1775                 else
1776                         I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
1777                 gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask);
1778         }
1779         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1780
1781         return true;
1782 }
1783
1784 static void
1785 gen6_ring_put_irq(struct intel_engine_cs *engine)
1786 {
1787         struct drm_device *dev = engine->dev;
1788         struct drm_i915_private *dev_priv = dev->dev_private;
1789         unsigned long flags;
1790
1791         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1792         if (--engine->irq_refcount == 0) {
1793                 if (HAS_L3_DPF(dev) && engine->id == RCS)
1794                         I915_WRITE_IMR(engine, ~GT_PARITY_ERROR(dev));
1795                 else
1796                         I915_WRITE_IMR(engine, ~0);
1797                 gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask);
1798         }
1799         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1800 }
1801
1802 static bool
1803 hsw_vebox_get_irq(struct intel_engine_cs *engine)
1804 {
1805         struct drm_device *dev = engine->dev;
1806         struct drm_i915_private *dev_priv = dev->dev_private;
1807         unsigned long flags;
1808
1809         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1810                 return false;
1811
1812         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1813         if (engine->irq_refcount++ == 0) {
1814                 I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
1815                 gen6_enable_pm_irq(dev_priv, engine->irq_enable_mask);
1816         }
1817         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1818
1819         return true;
1820 }
1821
1822 static void
1823 hsw_vebox_put_irq(struct intel_engine_cs *engine)
1824 {
1825         struct drm_device *dev = engine->dev;
1826         struct drm_i915_private *dev_priv = dev->dev_private;
1827         unsigned long flags;
1828
1829         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1830         if (--engine->irq_refcount == 0) {
1831                 I915_WRITE_IMR(engine, ~0);
1832                 gen6_disable_pm_irq(dev_priv, engine->irq_enable_mask);
1833         }
1834         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1835 }
1836
1837 static bool
1838 gen8_ring_get_irq(struct intel_engine_cs *engine)
1839 {
1840         struct drm_device *dev = engine->dev;
1841         struct drm_i915_private *dev_priv = dev->dev_private;
1842         unsigned long flags;
1843
1844         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1845                 return false;
1846
1847         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1848         if (engine->irq_refcount++ == 0) {
1849                 if (HAS_L3_DPF(dev) && engine->id == RCS) {
1850                         I915_WRITE_IMR(engine,
1851                                        ~(engine->irq_enable_mask |
1852                                          GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1853                 } else {
1854                         I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
1855                 }
1856                 POSTING_READ(RING_IMR(engine->mmio_base));
1857         }
1858         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1859
1860         return true;
1861 }
1862
1863 static void
1864 gen8_ring_put_irq(struct intel_engine_cs *engine)
1865 {
1866         struct drm_device *dev = engine->dev;
1867         struct drm_i915_private *dev_priv = dev->dev_private;
1868         unsigned long flags;
1869
1870         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1871         if (--engine->irq_refcount == 0) {
1872                 if (HAS_L3_DPF(dev) && engine->id == RCS) {
1873                         I915_WRITE_IMR(engine,
1874                                        ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1875                 } else {
1876                         I915_WRITE_IMR(engine, ~0);
1877                 }
1878                 POSTING_READ(RING_IMR(engine->mmio_base));
1879         }
1880         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1881 }
1882
1883 static int
1884 i965_dispatch_execbuffer(struct drm_i915_gem_request *req,
1885                          u64 offset, u32 length,
1886                          unsigned dispatch_flags)
1887 {
1888         struct intel_engine_cs *engine = req->engine;
1889         int ret;
1890
1891         ret = intel_ring_begin(req, 2);
1892         if (ret)
1893                 return ret;
1894
1895         intel_ring_emit(engine,
1896                         MI_BATCH_BUFFER_START |
1897                         MI_BATCH_GTT |
1898                         (dispatch_flags & I915_DISPATCH_SECURE ?
1899                          0 : MI_BATCH_NON_SECURE_I965));
1900         intel_ring_emit(engine, offset);
1901         intel_ring_advance(engine);
1902
1903         return 0;
1904 }
1905
1906 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1907 #define I830_BATCH_LIMIT (256*1024)
1908 #define I830_TLB_ENTRIES (2)
1909 #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
1910 static int
1911 i830_dispatch_execbuffer(struct drm_i915_gem_request *req,
1912                          u64 offset, u32 len,
1913                          unsigned dispatch_flags)
1914 {
1915         struct intel_engine_cs *engine = req->engine;
1916         u32 cs_offset = engine->scratch.gtt_offset;
1917         int ret;
1918
1919         ret = intel_ring_begin(req, 6);
1920         if (ret)
1921                 return ret;
1922
1923         /* Evict the invalid PTE TLBs */
1924         intel_ring_emit(engine, COLOR_BLT_CMD | BLT_WRITE_RGBA);
1925         intel_ring_emit(engine, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096);
1926         intel_ring_emit(engine, I830_TLB_ENTRIES << 16 | 4); /* load each page */
1927         intel_ring_emit(engine, cs_offset);
1928         intel_ring_emit(engine, 0xdeadbeef);
1929         intel_ring_emit(engine, MI_NOOP);
1930         intel_ring_advance(engine);
1931
1932         if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) {
1933                 if (len > I830_BATCH_LIMIT)
1934                         return -ENOSPC;
1935
1936                 ret = intel_ring_begin(req, 6 + 2);
1937                 if (ret)
1938                         return ret;
1939
1940                 /* Blit the batch (which has now all relocs applied) to the
1941                  * stable batch scratch bo area (so that the CS never
1942                  * stumbles over its tlb invalidation bug) ...
1943                  */
1944                 intel_ring_emit(engine, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA);
1945                 intel_ring_emit(engine,
1946                                 BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096);
1947                 intel_ring_emit(engine, DIV_ROUND_UP(len, 4096) << 16 | 4096);
1948                 intel_ring_emit(engine, cs_offset);
1949                 intel_ring_emit(engine, 4096);
1950                 intel_ring_emit(engine, offset);
1951
1952                 intel_ring_emit(engine, MI_FLUSH);
1953                 intel_ring_emit(engine, MI_NOOP);
1954                 intel_ring_advance(engine);
1955
1956                 /* ... and execute it. */
1957                 offset = cs_offset;
1958         }
1959
1960         ret = intel_ring_begin(req, 2);
1961         if (ret)
1962                 return ret;
1963
1964         intel_ring_emit(engine, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1965         intel_ring_emit(engine, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1966                                           0 : MI_BATCH_NON_SECURE));
1967         intel_ring_advance(engine);
1968
1969         return 0;
1970 }
1971
1972 static int
1973 i915_dispatch_execbuffer(struct drm_i915_gem_request *req,
1974                          u64 offset, u32 len,
1975                          unsigned dispatch_flags)
1976 {
1977         struct intel_engine_cs *engine = req->engine;
1978         int ret;
1979
1980         ret = intel_ring_begin(req, 2);
1981         if (ret)
1982                 return ret;
1983
1984         intel_ring_emit(engine, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1985         intel_ring_emit(engine, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1986                                           0 : MI_BATCH_NON_SECURE));
1987         intel_ring_advance(engine);
1988
1989         return 0;
1990 }
1991
1992 static void cleanup_phys_status_page(struct intel_engine_cs *engine)
1993 {
1994         struct drm_i915_private *dev_priv = to_i915(engine->dev);
1995
1996         if (!dev_priv->status_page_dmah)
1997                 return;
1998
1999         drm_pci_free(engine->dev, dev_priv->status_page_dmah);
2000         engine->status_page.page_addr = NULL;
2001 }
2002
2003 static void cleanup_status_page(struct intel_engine_cs *engine)
2004 {
2005         struct drm_i915_gem_object *obj;
2006
2007         obj = engine->status_page.obj;
2008         if (obj == NULL)
2009                 return;
2010
2011         kunmap(sg_page(obj->pages->sgl));
2012         i915_gem_object_ggtt_unpin(obj);
2013         drm_gem_object_unreference(&obj->base);
2014         engine->status_page.obj = NULL;
2015 }
2016
2017 static int init_status_page(struct intel_engine_cs *engine)
2018 {
2019         struct drm_i915_gem_object *obj = engine->status_page.obj;
2020
2021         if (obj == NULL) {
2022                 unsigned flags;
2023                 int ret;
2024
2025                 obj = i915_gem_alloc_object(engine->dev, 4096);
2026                 if (obj == NULL) {
2027                         DRM_ERROR("Failed to allocate status page\n");
2028                         return -ENOMEM;
2029                 }
2030
2031                 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2032                 if (ret)
2033                         goto err_unref;
2034
2035                 flags = 0;
2036                 if (!HAS_LLC(engine->dev))
2037                         /* On g33, we cannot place HWS above 256MiB, so
2038                          * restrict its pinning to the low mappable arena.
2039                          * Though this restriction is not documented for
2040                          * gen4, gen5, or byt, they also behave similarly
2041                          * and hang if the HWS is placed at the top of the
2042                          * GTT. To generalise, it appears that all !llc
2043                          * platforms have issues with us placing the HWS
2044                          * above the mappable region (even though we never
2045                          * actualy map it).
2046                          */
2047                         flags |= PIN_MAPPABLE;
2048                 ret = i915_gem_obj_ggtt_pin(obj, 4096, flags);
2049                 if (ret) {
2050 err_unref:
2051                         drm_gem_object_unreference(&obj->base);
2052                         return ret;
2053                 }
2054
2055                 engine->status_page.obj = obj;
2056         }
2057
2058         engine->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
2059         engine->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
2060         memset(engine->status_page.page_addr, 0, PAGE_SIZE);
2061
2062         DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
2063                         engine->name, engine->status_page.gfx_addr);
2064
2065         return 0;
2066 }
2067
2068 static int init_phys_status_page(struct intel_engine_cs *engine)
2069 {
2070         struct drm_i915_private *dev_priv = engine->dev->dev_private;
2071
2072         if (!dev_priv->status_page_dmah) {
2073                 dev_priv->status_page_dmah =
2074                         drm_pci_alloc(engine->dev, PAGE_SIZE, PAGE_SIZE);
2075                 if (!dev_priv->status_page_dmah)
2076                         return -ENOMEM;
2077         }
2078
2079         engine->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
2080         memset(engine->status_page.page_addr, 0, PAGE_SIZE);
2081
2082         return 0;
2083 }
2084
2085 void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
2086 {
2087         if (HAS_LLC(ringbuf->obj->base.dev) && !ringbuf->obj->stolen)
2088                 i915_gem_object_unpin_map(ringbuf->obj);
2089         else
2090                 iounmap(ringbuf->virtual_start);
2091         ringbuf->virtual_start = NULL;
2092         ringbuf->vma = NULL;
2093         i915_gem_object_ggtt_unpin(ringbuf->obj);
2094 }
2095
2096 int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
2097                                      struct intel_ringbuffer *ringbuf)
2098 {
2099         struct drm_i915_private *dev_priv = to_i915(dev);
2100         struct i915_ggtt *ggtt = &dev_priv->ggtt;
2101         struct drm_i915_gem_object *obj = ringbuf->obj;
2102         /* Ring wraparound at offset 0 sometimes hangs. No idea why. */
2103         unsigned flags = PIN_OFFSET_BIAS | 4096;
2104         void *addr;
2105         int ret;
2106
2107         if (HAS_LLC(dev_priv) && !obj->stolen) {
2108                 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, flags);
2109                 if (ret)
2110                         return ret;
2111
2112                 ret = i915_gem_object_set_to_cpu_domain(obj, true);
2113                 if (ret)
2114                         goto err_unpin;
2115
2116                 addr = i915_gem_object_pin_map(obj);
2117                 if (IS_ERR(addr)) {
2118                         ret = PTR_ERR(addr);
2119                         goto err_unpin;
2120                 }
2121         } else {
2122                 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE,
2123                                             flags | PIN_MAPPABLE);
2124                 if (ret)
2125                         return ret;
2126
2127                 ret = i915_gem_object_set_to_gtt_domain(obj, true);
2128                 if (ret)
2129                         goto err_unpin;
2130
2131                 /* Access through the GTT requires the device to be awake. */
2132                 assert_rpm_wakelock_held(dev_priv);
2133
2134                 addr = ioremap_wc(ggtt->mappable_base +
2135                                   i915_gem_obj_ggtt_offset(obj), ringbuf->size);
2136                 if (addr == NULL) {
2137                         ret = -ENOMEM;
2138                         goto err_unpin;
2139                 }
2140         }
2141
2142         ringbuf->virtual_start = addr;
2143         ringbuf->vma = i915_gem_obj_to_ggtt(obj);
2144         return 0;
2145
2146 err_unpin:
2147         i915_gem_object_ggtt_unpin(obj);
2148         return ret;
2149 }
2150
2151 static void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
2152 {
2153         drm_gem_object_unreference(&ringbuf->obj->base);
2154         ringbuf->obj = NULL;
2155 }
2156
2157 static int intel_alloc_ringbuffer_obj(struct drm_device *dev,
2158                                       struct intel_ringbuffer *ringbuf)
2159 {
2160         struct drm_i915_gem_object *obj;
2161
2162         obj = NULL;
2163         if (!HAS_LLC(dev))
2164                 obj = i915_gem_object_create_stolen(dev, ringbuf->size);
2165         if (obj == NULL)
2166                 obj = i915_gem_alloc_object(dev, ringbuf->size);
2167         if (obj == NULL)
2168                 return -ENOMEM;
2169
2170         /* mark ring buffers as read-only from GPU side by default */
2171         obj->gt_ro = 1;
2172
2173         ringbuf->obj = obj;
2174
2175         return 0;
2176 }
2177
2178 struct intel_ringbuffer *
2179 intel_engine_create_ringbuffer(struct intel_engine_cs *engine, int size)
2180 {
2181         struct intel_ringbuffer *ring;
2182         int ret;
2183
2184         ring = kzalloc(sizeof(*ring), GFP_KERNEL);
2185         if (ring == NULL) {
2186                 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n",
2187                                  engine->name);
2188                 return ERR_PTR(-ENOMEM);
2189         }
2190
2191         ring->engine = engine;
2192         list_add(&ring->link, &engine->buffers);
2193
2194         ring->size = size;
2195         /* Workaround an erratum on the i830 which causes a hang if
2196          * the TAIL pointer points to within the last 2 cachelines
2197          * of the buffer.
2198          */
2199         ring->effective_size = size;
2200         if (IS_I830(engine->dev) || IS_845G(engine->dev))
2201                 ring->effective_size -= 2 * CACHELINE_BYTES;
2202
2203         ring->last_retired_head = -1;
2204         intel_ring_update_space(ring);
2205
2206         ret = intel_alloc_ringbuffer_obj(engine->dev, ring);
2207         if (ret) {
2208                 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s: %d\n",
2209                                  engine->name, ret);
2210                 list_del(&ring->link);
2211                 kfree(ring);
2212                 return ERR_PTR(ret);
2213         }
2214
2215         return ring;
2216 }
2217
2218 void
2219 intel_ringbuffer_free(struct intel_ringbuffer *ring)
2220 {
2221         intel_destroy_ringbuffer_obj(ring);
2222         list_del(&ring->link);
2223         kfree(ring);
2224 }
2225
2226 static int intel_init_ring_buffer(struct drm_device *dev,
2227                                   struct intel_engine_cs *engine)
2228 {
2229         struct intel_ringbuffer *ringbuf;
2230         int ret;
2231
2232         WARN_ON(engine->buffer);
2233
2234         engine->dev = dev;
2235         INIT_LIST_HEAD(&engine->active_list);
2236         INIT_LIST_HEAD(&engine->request_list);
2237         INIT_LIST_HEAD(&engine->execlist_queue);
2238         INIT_LIST_HEAD(&engine->buffers);
2239         i915_gem_batch_pool_init(dev, &engine->batch_pool);
2240         memset(engine->semaphore.sync_seqno, 0,
2241                sizeof(engine->semaphore.sync_seqno));
2242
2243         init_waitqueue_head(&engine->irq_queue);
2244
2245         ringbuf = intel_engine_create_ringbuffer(engine, 32 * PAGE_SIZE);
2246         if (IS_ERR(ringbuf)) {
2247                 ret = PTR_ERR(ringbuf);
2248                 goto error;
2249         }
2250         engine->buffer = ringbuf;
2251
2252         if (I915_NEED_GFX_HWS(dev)) {
2253                 ret = init_status_page(engine);
2254                 if (ret)
2255                         goto error;
2256         } else {
2257                 WARN_ON(engine->id != RCS);
2258                 ret = init_phys_status_page(engine);
2259                 if (ret)
2260                         goto error;
2261         }
2262
2263         ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
2264         if (ret) {
2265                 DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
2266                                 engine->name, ret);
2267                 intel_destroy_ringbuffer_obj(ringbuf);
2268                 goto error;
2269         }
2270
2271         ret = i915_cmd_parser_init_ring(engine);
2272         if (ret)
2273                 goto error;
2274
2275         return 0;
2276
2277 error:
2278         intel_cleanup_engine(engine);
2279         return ret;
2280 }
2281
2282 void intel_cleanup_engine(struct intel_engine_cs *engine)
2283 {
2284         struct drm_i915_private *dev_priv;
2285
2286         if (!intel_engine_initialized(engine))
2287                 return;
2288
2289         dev_priv = to_i915(engine->dev);
2290
2291         if (engine->buffer) {
2292                 intel_stop_engine(engine);
2293                 WARN_ON(!IS_GEN2(engine->dev) && (I915_READ_MODE(engine) & MODE_IDLE) == 0);
2294
2295                 intel_unpin_ringbuffer_obj(engine->buffer);
2296                 intel_ringbuffer_free(engine->buffer);
2297                 engine->buffer = NULL;
2298         }
2299
2300         if (engine->cleanup)
2301                 engine->cleanup(engine);
2302
2303         if (I915_NEED_GFX_HWS(engine->dev)) {
2304                 cleanup_status_page(engine);
2305         } else {
2306                 WARN_ON(engine->id != RCS);
2307                 cleanup_phys_status_page(engine);
2308         }
2309
2310         i915_cmd_parser_fini_ring(engine);
2311         i915_gem_batch_pool_fini(&engine->batch_pool);
2312         engine->dev = NULL;
2313 }
2314
2315 int intel_engine_idle(struct intel_engine_cs *engine)
2316 {
2317         struct drm_i915_gem_request *req;
2318
2319         /* Wait upon the last request to be completed */
2320         if (list_empty(&engine->request_list))
2321                 return 0;
2322
2323         req = list_entry(engine->request_list.prev,
2324                          struct drm_i915_gem_request,
2325                          list);
2326
2327         /* Make sure we do not trigger any retires */
2328         return __i915_wait_request(req,
2329                                    req->i915->mm.interruptible,
2330                                    NULL, NULL);
2331 }
2332
2333 int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request)
2334 {
2335         request->ringbuf = request->engine->buffer;
2336         return 0;
2337 }
2338
2339 int intel_ring_reserve_space(struct drm_i915_gem_request *request)
2340 {
2341         /*
2342          * The first call merely notes the reserve request and is common for
2343          * all back ends. The subsequent localised _begin() call actually
2344          * ensures that the reservation is available. Without the begin, if
2345          * the request creator immediately submitted the request without
2346          * adding any commands to it then there might not actually be
2347          * sufficient room for the submission commands.
2348          */
2349         intel_ring_reserved_space_reserve(request->ringbuf, MIN_SPACE_FOR_ADD_REQUEST);
2350
2351         return intel_ring_begin(request, 0);
2352 }
2353
2354 void intel_ring_reserved_space_reserve(struct intel_ringbuffer *ringbuf, int size)
2355 {
2356         GEM_BUG_ON(ringbuf->reserved_size);
2357         ringbuf->reserved_size = size;
2358 }
2359
2360 void intel_ring_reserved_space_cancel(struct intel_ringbuffer *ringbuf)
2361 {
2362         GEM_BUG_ON(!ringbuf->reserved_size);
2363         ringbuf->reserved_size   = 0;
2364 }
2365
2366 void intel_ring_reserved_space_use(struct intel_ringbuffer *ringbuf)
2367 {
2368         GEM_BUG_ON(!ringbuf->reserved_size);
2369         ringbuf->reserved_size   = 0;
2370 }
2371
2372 void intel_ring_reserved_space_end(struct intel_ringbuffer *ringbuf)
2373 {
2374         GEM_BUG_ON(ringbuf->reserved_size);
2375 }
2376
2377 static int wait_for_space(struct drm_i915_gem_request *req, int bytes)
2378 {
2379         struct intel_ringbuffer *ringbuf = req->ringbuf;
2380         struct intel_engine_cs *engine = req->engine;
2381         struct drm_i915_gem_request *target;
2382
2383         intel_ring_update_space(ringbuf);
2384         if (ringbuf->space >= bytes)
2385                 return 0;
2386
2387         /*
2388          * Space is reserved in the ringbuffer for finalising the request,
2389          * as that cannot be allowed to fail. During request finalisation,
2390          * reserved_space is set to 0 to stop the overallocation and the
2391          * assumption is that then we never need to wait (which has the
2392          * risk of failing with EINTR).
2393          *
2394          * See also i915_gem_request_alloc() and i915_add_request().
2395          */
2396         GEM_BUG_ON(!ringbuf->reserved_size);
2397
2398         list_for_each_entry(target, &engine->request_list, list) {
2399                 unsigned space;
2400
2401                 /*
2402                  * The request queue is per-engine, so can contain requests
2403                  * from multiple ringbuffers. Here, we must ignore any that
2404                  * aren't from the ringbuffer we're considering.
2405                  */
2406                 if (target->ringbuf != ringbuf)
2407                         continue;
2408
2409                 /* Would completion of this request free enough space? */
2410                 space = __intel_ring_space(target->postfix, ringbuf->tail,
2411                                            ringbuf->size);
2412                 if (space >= bytes)
2413                         break;
2414         }
2415
2416         if (WARN_ON(&target->list == &engine->request_list))
2417                 return -ENOSPC;
2418
2419         return i915_wait_request(target);
2420 }
2421
2422 int intel_ring_begin(struct drm_i915_gem_request *req, int num_dwords)
2423 {
2424         struct intel_ringbuffer *ringbuf = req->ringbuf;
2425         int remain_actual = ringbuf->size - ringbuf->tail;
2426         int remain_usable = ringbuf->effective_size - ringbuf->tail;
2427         int bytes = num_dwords * sizeof(u32);
2428         int total_bytes, wait_bytes;
2429         bool need_wrap = false;
2430
2431         total_bytes = bytes + ringbuf->reserved_size;
2432
2433         if (unlikely(bytes > remain_usable)) {
2434                 /*
2435                  * Not enough space for the basic request. So need to flush
2436                  * out the remainder and then wait for base + reserved.
2437                  */
2438                 wait_bytes = remain_actual + total_bytes;
2439                 need_wrap = true;
2440         } else if (unlikely(total_bytes > remain_usable)) {
2441                 /*
2442                  * The base request will fit but the reserved space
2443                  * falls off the end. So we don't need an immediate wrap
2444                  * and only need to effectively wait for the reserved
2445                  * size space from the start of ringbuffer.
2446                  */
2447                 wait_bytes = remain_actual + ringbuf->reserved_size;
2448         } else {
2449                 /* No wrapping required, just waiting. */
2450                 wait_bytes = total_bytes;
2451         }
2452
2453         if (wait_bytes > ringbuf->space) {
2454                 int ret = wait_for_space(req, wait_bytes);
2455                 if (unlikely(ret))
2456                         return ret;
2457
2458                 intel_ring_update_space(ringbuf);
2459                 if (unlikely(ringbuf->space < wait_bytes))
2460                         return -EAGAIN;
2461         }
2462
2463         if (unlikely(need_wrap)) {
2464                 GEM_BUG_ON(remain_actual > ringbuf->space);
2465                 GEM_BUG_ON(ringbuf->tail + remain_actual > ringbuf->size);
2466
2467                 /* Fill the tail with MI_NOOP */
2468                 memset(ringbuf->virtual_start + ringbuf->tail,
2469                        0, remain_actual);
2470                 ringbuf->tail = 0;
2471                 ringbuf->space -= remain_actual;
2472         }
2473
2474         ringbuf->space -= bytes;
2475         GEM_BUG_ON(ringbuf->space < 0);
2476         return 0;
2477 }
2478
2479 /* Align the ring tail to a cacheline boundary */
2480 int intel_ring_cacheline_align(struct drm_i915_gem_request *req)
2481 {
2482         struct intel_engine_cs *engine = req->engine;
2483         int num_dwords = (engine->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
2484         int ret;
2485
2486         if (num_dwords == 0)
2487                 return 0;
2488
2489         num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
2490         ret = intel_ring_begin(req, num_dwords);
2491         if (ret)
2492                 return ret;
2493
2494         while (num_dwords--)
2495                 intel_ring_emit(engine, MI_NOOP);
2496
2497         intel_ring_advance(engine);
2498
2499         return 0;
2500 }
2501
2502 void intel_ring_init_seqno(struct intel_engine_cs *engine, u32 seqno)
2503 {
2504         struct drm_i915_private *dev_priv = to_i915(engine->dev);
2505
2506         /* Our semaphore implementation is strictly monotonic (i.e. we proceed
2507          * so long as the semaphore value in the register/page is greater
2508          * than the sync value), so whenever we reset the seqno,
2509          * so long as we reset the tracking semaphore value to 0, it will
2510          * always be before the next request's seqno. If we don't reset
2511          * the semaphore value, then when the seqno moves backwards all
2512          * future waits will complete instantly (causing rendering corruption).
2513          */
2514         if (INTEL_INFO(dev_priv)->gen == 6 || INTEL_INFO(dev_priv)->gen == 7) {
2515                 I915_WRITE(RING_SYNC_0(engine->mmio_base), 0);
2516                 I915_WRITE(RING_SYNC_1(engine->mmio_base), 0);
2517                 if (HAS_VEBOX(dev_priv))
2518                         I915_WRITE(RING_SYNC_2(engine->mmio_base), 0);
2519         }
2520         if (dev_priv->semaphore_obj) {
2521                 struct drm_i915_gem_object *obj = dev_priv->semaphore_obj;
2522                 struct page *page = i915_gem_object_get_dirty_page(obj, 0);
2523                 void *semaphores = kmap(page);
2524                 memset(semaphores + GEN8_SEMAPHORE_OFFSET(engine->id, 0),
2525                        0, I915_NUM_ENGINES * gen8_semaphore_seqno_size);
2526                 kunmap(page);
2527         }
2528         memset(engine->semaphore.sync_seqno, 0,
2529                sizeof(engine->semaphore.sync_seqno));
2530
2531         engine->set_seqno(engine, seqno);
2532         engine->last_submitted_seqno = seqno;
2533
2534         engine->hangcheck.seqno = seqno;
2535 }
2536
2537 static void gen6_bsd_ring_write_tail(struct intel_engine_cs *engine,
2538                                      u32 value)
2539 {
2540         struct drm_i915_private *dev_priv = engine->dev->dev_private;
2541
2542        /* Every tail move must follow the sequence below */
2543
2544         /* Disable notification that the ring is IDLE. The GT
2545          * will then assume that it is busy and bring it out of rc6.
2546          */
2547         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2548                    _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2549
2550         /* Clear the context id. Here be magic! */
2551         I915_WRITE64(GEN6_BSD_RNCID, 0x0);
2552
2553         /* Wait for the ring not to be idle, i.e. for it to wake up. */
2554         if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
2555                       GEN6_BSD_SLEEP_INDICATOR) == 0,
2556                      50))
2557                 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
2558
2559         /* Now that the ring is fully powered up, update the tail */
2560         I915_WRITE_TAIL(engine, value);
2561         POSTING_READ(RING_TAIL(engine->mmio_base));
2562
2563         /* Let the ring send IDLE messages to the GT again,
2564          * and so let it sleep to conserve power when idle.
2565          */
2566         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2567                    _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2568 }
2569
2570 static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req,
2571                                u32 invalidate, u32 flush)
2572 {
2573         struct intel_engine_cs *engine = req->engine;
2574         uint32_t cmd;
2575         int ret;
2576
2577         ret = intel_ring_begin(req, 4);
2578         if (ret)
2579                 return ret;
2580
2581         cmd = MI_FLUSH_DW;
2582         if (INTEL_INFO(engine->dev)->gen >= 8)
2583                 cmd += 1;
2584
2585         /* We always require a command barrier so that subsequent
2586          * commands, such as breadcrumb interrupts, are strictly ordered
2587          * wrt the contents of the write cache being flushed to memory
2588          * (and thus being coherent from the CPU).
2589          */
2590         cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2591
2592         /*
2593          * Bspec vol 1c.5 - video engine command streamer:
2594          * "If ENABLED, all TLBs will be invalidated once the flush
2595          * operation is complete. This bit is only valid when the
2596          * Post-Sync Operation field is a value of 1h or 3h."
2597          */
2598         if (invalidate & I915_GEM_GPU_DOMAINS)
2599                 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
2600
2601         intel_ring_emit(engine, cmd);
2602         intel_ring_emit(engine,
2603                         I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2604         if (INTEL_INFO(engine->dev)->gen >= 8) {
2605                 intel_ring_emit(engine, 0); /* upper addr */
2606                 intel_ring_emit(engine, 0); /* value */
2607         } else  {
2608                 intel_ring_emit(engine, 0);
2609                 intel_ring_emit(engine, MI_NOOP);
2610         }
2611         intel_ring_advance(engine);
2612         return 0;
2613 }
2614
2615 static int
2616 gen8_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
2617                               u64 offset, u32 len,
2618                               unsigned dispatch_flags)
2619 {
2620         struct intel_engine_cs *engine = req->engine;
2621         bool ppgtt = USES_PPGTT(engine->dev) &&
2622                         !(dispatch_flags & I915_DISPATCH_SECURE);
2623         int ret;
2624
2625         ret = intel_ring_begin(req, 4);
2626         if (ret)
2627                 return ret;
2628
2629         /* FIXME(BDW): Address space and security selectors. */
2630         intel_ring_emit(engine, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8) |
2631                         (dispatch_flags & I915_DISPATCH_RS ?
2632                          MI_BATCH_RESOURCE_STREAMER : 0));
2633         intel_ring_emit(engine, lower_32_bits(offset));
2634         intel_ring_emit(engine, upper_32_bits(offset));
2635         intel_ring_emit(engine, MI_NOOP);
2636         intel_ring_advance(engine);
2637
2638         return 0;
2639 }
2640
2641 static int
2642 hsw_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
2643                              u64 offset, u32 len,
2644                              unsigned dispatch_flags)
2645 {
2646         struct intel_engine_cs *engine = req->engine;
2647         int ret;
2648
2649         ret = intel_ring_begin(req, 2);
2650         if (ret)
2651                 return ret;
2652
2653         intel_ring_emit(engine,
2654                         MI_BATCH_BUFFER_START |
2655                         (dispatch_flags & I915_DISPATCH_SECURE ?
2656                          0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW) |
2657                         (dispatch_flags & I915_DISPATCH_RS ?
2658                          MI_BATCH_RESOURCE_STREAMER : 0));
2659         /* bit0-7 is the length on GEN6+ */
2660         intel_ring_emit(engine, offset);
2661         intel_ring_advance(engine);
2662
2663         return 0;
2664 }
2665
2666 static int
2667 gen6_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
2668                               u64 offset, u32 len,
2669                               unsigned dispatch_flags)
2670 {
2671         struct intel_engine_cs *engine = req->engine;
2672         int ret;
2673
2674         ret = intel_ring_begin(req, 2);
2675         if (ret)
2676                 return ret;
2677
2678         intel_ring_emit(engine,
2679                         MI_BATCH_BUFFER_START |
2680                         (dispatch_flags & I915_DISPATCH_SECURE ?
2681                          0 : MI_BATCH_NON_SECURE_I965));
2682         /* bit0-7 is the length on GEN6+ */
2683         intel_ring_emit(engine, offset);
2684         intel_ring_advance(engine);
2685
2686         return 0;
2687 }
2688
2689 /* Blitter support (SandyBridge+) */
2690
2691 static int gen6_ring_flush(struct drm_i915_gem_request *req,
2692                            u32 invalidate, u32 flush)
2693 {
2694         struct intel_engine_cs *engine = req->engine;
2695         struct drm_device *dev = engine->dev;
2696         uint32_t cmd;
2697         int ret;
2698
2699         ret = intel_ring_begin(req, 4);
2700         if (ret)
2701                 return ret;
2702
2703         cmd = MI_FLUSH_DW;
2704         if (INTEL_INFO(dev)->gen >= 8)
2705                 cmd += 1;
2706
2707         /* We always require a command barrier so that subsequent
2708          * commands, such as breadcrumb interrupts, are strictly ordered
2709          * wrt the contents of the write cache being flushed to memory
2710          * (and thus being coherent from the CPU).
2711          */
2712         cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2713
2714         /*
2715          * Bspec vol 1c.3 - blitter engine command streamer:
2716          * "If ENABLED, all TLBs will be invalidated once the flush
2717          * operation is complete. This bit is only valid when the
2718          * Post-Sync Operation field is a value of 1h or 3h."
2719          */
2720         if (invalidate & I915_GEM_DOMAIN_RENDER)
2721                 cmd |= MI_INVALIDATE_TLB;
2722         intel_ring_emit(engine, cmd);
2723         intel_ring_emit(engine,
2724                         I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2725         if (INTEL_INFO(dev)->gen >= 8) {
2726                 intel_ring_emit(engine, 0); /* upper addr */
2727                 intel_ring_emit(engine, 0); /* value */
2728         } else  {
2729                 intel_ring_emit(engine, 0);
2730                 intel_ring_emit(engine, MI_NOOP);
2731         }
2732         intel_ring_advance(engine);
2733
2734         return 0;
2735 }
2736
2737 int intel_init_render_ring_buffer(struct drm_device *dev)
2738 {
2739         struct drm_i915_private *dev_priv = dev->dev_private;
2740         struct intel_engine_cs *engine = &dev_priv->engine[RCS];
2741         struct drm_i915_gem_object *obj;
2742         int ret;
2743
2744         engine->name = "render ring";
2745         engine->id = RCS;
2746         engine->exec_id = I915_EXEC_RENDER;
2747         engine->hw_id = 0;
2748         engine->mmio_base = RENDER_RING_BASE;
2749
2750         if (INTEL_INFO(dev)->gen >= 8) {
2751                 if (i915_semaphore_is_enabled(dev)) {
2752                         obj = i915_gem_alloc_object(dev, 4096);
2753                         if (obj == NULL) {
2754                                 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2755                                 i915.semaphores = 0;
2756                         } else {
2757                                 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2758                                 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK);
2759                                 if (ret != 0) {
2760                                         drm_gem_object_unreference(&obj->base);
2761                                         DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2762                                         i915.semaphores = 0;
2763                                 } else
2764                                         dev_priv->semaphore_obj = obj;
2765                         }
2766                 }
2767
2768                 engine->init_context = intel_rcs_ctx_init;
2769                 engine->add_request = gen6_add_request;
2770                 engine->flush = gen8_render_ring_flush;
2771                 engine->irq_get = gen8_ring_get_irq;
2772                 engine->irq_put = gen8_ring_put_irq;
2773                 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2774                 engine->irq_seqno_barrier = gen6_seqno_barrier;
2775                 engine->get_seqno = ring_get_seqno;
2776                 engine->set_seqno = ring_set_seqno;
2777                 if (i915_semaphore_is_enabled(dev)) {
2778                         WARN_ON(!dev_priv->semaphore_obj);
2779                         engine->semaphore.sync_to = gen8_ring_sync;
2780                         engine->semaphore.signal = gen8_rcs_signal;
2781                         GEN8_RING_SEMAPHORE_INIT(engine);
2782                 }
2783         } else if (INTEL_INFO(dev)->gen >= 6) {
2784                 engine->init_context = intel_rcs_ctx_init;
2785                 engine->add_request = gen6_add_request;
2786                 engine->flush = gen7_render_ring_flush;
2787                 if (INTEL_INFO(dev)->gen == 6)
2788                         engine->flush = gen6_render_ring_flush;
2789                 engine->irq_get = gen6_ring_get_irq;
2790                 engine->irq_put = gen6_ring_put_irq;
2791                 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2792                 engine->irq_seqno_barrier = gen6_seqno_barrier;
2793                 engine->get_seqno = ring_get_seqno;
2794                 engine->set_seqno = ring_set_seqno;
2795                 if (i915_semaphore_is_enabled(dev)) {
2796                         engine->semaphore.sync_to = gen6_ring_sync;
2797                         engine->semaphore.signal = gen6_signal;
2798                         /*
2799                          * The current semaphore is only applied on pre-gen8
2800                          * platform.  And there is no VCS2 ring on the pre-gen8
2801                          * platform. So the semaphore between RCS and VCS2 is
2802                          * initialized as INVALID.  Gen8 will initialize the
2803                          * sema between VCS2 and RCS later.
2804                          */
2805                         engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID;
2806                         engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV;
2807                         engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB;
2808                         engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE;
2809                         engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2810                         engine->semaphore.mbox.signal[RCS] = GEN6_NOSYNC;
2811                         engine->semaphore.mbox.signal[VCS] = GEN6_VRSYNC;
2812                         engine->semaphore.mbox.signal[BCS] = GEN6_BRSYNC;
2813                         engine->semaphore.mbox.signal[VECS] = GEN6_VERSYNC;
2814                         engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2815                 }
2816         } else if (IS_GEN5(dev)) {
2817                 engine->add_request = pc_render_add_request;
2818                 engine->flush = gen4_render_ring_flush;
2819                 engine->get_seqno = pc_render_get_seqno;
2820                 engine->set_seqno = pc_render_set_seqno;
2821                 engine->irq_get = gen5_ring_get_irq;
2822                 engine->irq_put = gen5_ring_put_irq;
2823                 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
2824                                         GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
2825         } else {
2826                 engine->add_request = i9xx_add_request;
2827                 if (INTEL_INFO(dev)->gen < 4)
2828                         engine->flush = gen2_render_ring_flush;
2829                 else
2830                         engine->flush = gen4_render_ring_flush;
2831                 engine->get_seqno = ring_get_seqno;
2832                 engine->set_seqno = ring_set_seqno;
2833                 if (IS_GEN2(dev)) {
2834                         engine->irq_get = i8xx_ring_get_irq;
2835                         engine->irq_put = i8xx_ring_put_irq;
2836                 } else {
2837                         engine->irq_get = i9xx_ring_get_irq;
2838                         engine->irq_put = i9xx_ring_put_irq;
2839                 }
2840                 engine->irq_enable_mask = I915_USER_INTERRUPT;
2841         }
2842         engine->write_tail = ring_write_tail;
2843
2844         if (IS_HASWELL(dev))
2845                 engine->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
2846         else if (IS_GEN8(dev))
2847                 engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2848         else if (INTEL_INFO(dev)->gen >= 6)
2849                 engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2850         else if (INTEL_INFO(dev)->gen >= 4)
2851                 engine->dispatch_execbuffer = i965_dispatch_execbuffer;
2852         else if (IS_I830(dev) || IS_845G(dev))
2853                 engine->dispatch_execbuffer = i830_dispatch_execbuffer;
2854         else
2855                 engine->dispatch_execbuffer = i915_dispatch_execbuffer;
2856         engine->init_hw = init_render_ring;
2857         engine->cleanup = render_ring_cleanup;
2858
2859         /* Workaround batchbuffer to combat CS tlb bug. */
2860         if (HAS_BROKEN_CS_TLB(dev)) {
2861                 obj = i915_gem_alloc_object(dev, I830_WA_SIZE);
2862                 if (obj == NULL) {
2863                         DRM_ERROR("Failed to allocate batch bo\n");
2864                         return -ENOMEM;
2865                 }
2866
2867                 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
2868                 if (ret != 0) {
2869                         drm_gem_object_unreference(&obj->base);
2870                         DRM_ERROR("Failed to ping batch bo\n");
2871                         return ret;
2872                 }
2873
2874                 engine->scratch.obj = obj;
2875                 engine->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
2876         }
2877
2878         ret = intel_init_ring_buffer(dev, engine);
2879         if (ret)
2880                 return ret;
2881
2882         if (INTEL_INFO(dev)->gen >= 5) {
2883                 ret = intel_init_pipe_control(engine);
2884                 if (ret)
2885                         return ret;
2886         }
2887
2888         return 0;
2889 }
2890
2891 int intel_init_bsd_ring_buffer(struct drm_device *dev)
2892 {
2893         struct drm_i915_private *dev_priv = dev->dev_private;
2894         struct intel_engine_cs *engine = &dev_priv->engine[VCS];
2895
2896         engine->name = "bsd ring";
2897         engine->id = VCS;
2898         engine->exec_id = I915_EXEC_BSD;
2899         engine->hw_id = 1;
2900
2901         engine->write_tail = ring_write_tail;
2902         if (INTEL_INFO(dev)->gen >= 6) {
2903                 engine->mmio_base = GEN6_BSD_RING_BASE;
2904                 /* gen6 bsd needs a special wa for tail updates */
2905                 if (IS_GEN6(dev))
2906                         engine->write_tail = gen6_bsd_ring_write_tail;
2907                 engine->flush = gen6_bsd_ring_flush;
2908                 engine->add_request = gen6_add_request;
2909                 engine->irq_seqno_barrier = gen6_seqno_barrier;
2910                 engine->get_seqno = ring_get_seqno;
2911                 engine->set_seqno = ring_set_seqno;
2912                 if (INTEL_INFO(dev)->gen >= 8) {
2913                         engine->irq_enable_mask =
2914                                 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2915                         engine->irq_get = gen8_ring_get_irq;
2916                         engine->irq_put = gen8_ring_put_irq;
2917                         engine->dispatch_execbuffer =
2918                                 gen8_ring_dispatch_execbuffer;
2919                         if (i915_semaphore_is_enabled(dev)) {
2920                                 engine->semaphore.sync_to = gen8_ring_sync;
2921                                 engine->semaphore.signal = gen8_xcs_signal;
2922                                 GEN8_RING_SEMAPHORE_INIT(engine);
2923                         }
2924                 } else {
2925                         engine->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2926                         engine->irq_get = gen6_ring_get_irq;
2927                         engine->irq_put = gen6_ring_put_irq;
2928                         engine->dispatch_execbuffer =
2929                                 gen6_ring_dispatch_execbuffer;
2930                         if (i915_semaphore_is_enabled(dev)) {
2931                                 engine->semaphore.sync_to = gen6_ring_sync;
2932                                 engine->semaphore.signal = gen6_signal;
2933                                 engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;
2934                                 engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2935                                 engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB;
2936                                 engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE;
2937                                 engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2938                                 engine->semaphore.mbox.signal[RCS] = GEN6_RVSYNC;
2939                                 engine->semaphore.mbox.signal[VCS] = GEN6_NOSYNC;
2940                                 engine->semaphore.mbox.signal[BCS] = GEN6_BVSYNC;
2941                                 engine->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC;
2942                                 engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2943                         }
2944                 }
2945         } else {
2946                 engine->mmio_base = BSD_RING_BASE;
2947                 engine->flush = bsd_ring_flush;
2948                 engine->add_request = i9xx_add_request;
2949                 engine->get_seqno = ring_get_seqno;
2950                 engine->set_seqno = ring_set_seqno;
2951                 if (IS_GEN5(dev)) {
2952                         engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
2953                         engine->irq_get = gen5_ring_get_irq;
2954                         engine->irq_put = gen5_ring_put_irq;
2955                 } else {
2956                         engine->irq_enable_mask = I915_BSD_USER_INTERRUPT;
2957                         engine->irq_get = i9xx_ring_get_irq;
2958                         engine->irq_put = i9xx_ring_put_irq;
2959                 }
2960                 engine->dispatch_execbuffer = i965_dispatch_execbuffer;
2961         }
2962         engine->init_hw = init_ring_common;
2963
2964         return intel_init_ring_buffer(dev, engine);
2965 }
2966
2967 /**
2968  * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3)
2969  */
2970 int intel_init_bsd2_ring_buffer(struct drm_device *dev)
2971 {
2972         struct drm_i915_private *dev_priv = dev->dev_private;
2973         struct intel_engine_cs *engine = &dev_priv->engine[VCS2];
2974
2975         engine->name = "bsd2 ring";
2976         engine->id = VCS2;
2977         engine->exec_id = I915_EXEC_BSD;
2978         engine->hw_id = 4;
2979
2980         engine->write_tail = ring_write_tail;
2981         engine->mmio_base = GEN8_BSD2_RING_BASE;
2982         engine->flush = gen6_bsd_ring_flush;
2983         engine->add_request = gen6_add_request;
2984         engine->irq_seqno_barrier = gen6_seqno_barrier;
2985         engine->get_seqno = ring_get_seqno;
2986         engine->set_seqno = ring_set_seqno;
2987         engine->irq_enable_mask =
2988                         GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
2989         engine->irq_get = gen8_ring_get_irq;
2990         engine->irq_put = gen8_ring_put_irq;
2991         engine->dispatch_execbuffer =
2992                         gen8_ring_dispatch_execbuffer;
2993         if (i915_semaphore_is_enabled(dev)) {
2994                 engine->semaphore.sync_to = gen8_ring_sync;
2995                 engine->semaphore.signal = gen8_xcs_signal;
2996                 GEN8_RING_SEMAPHORE_INIT(engine);
2997         }
2998         engine->init_hw = init_ring_common;
2999
3000         return intel_init_ring_buffer(dev, engine);
3001 }
3002
3003 int intel_init_blt_ring_buffer(struct drm_device *dev)
3004 {
3005         struct drm_i915_private *dev_priv = dev->dev_private;
3006         struct intel_engine_cs *engine = &dev_priv->engine[BCS];
3007
3008         engine->name = "blitter ring";
3009         engine->id = BCS;
3010         engine->exec_id = I915_EXEC_BLT;
3011         engine->hw_id = 2;
3012
3013         engine->mmio_base = BLT_RING_BASE;
3014         engine->write_tail = ring_write_tail;
3015         engine->flush = gen6_ring_flush;
3016         engine->add_request = gen6_add_request;
3017         engine->irq_seqno_barrier = gen6_seqno_barrier;
3018         engine->get_seqno = ring_get_seqno;
3019         engine->set_seqno = ring_set_seqno;
3020         if (INTEL_INFO(dev)->gen >= 8) {
3021                 engine->irq_enable_mask =
3022                         GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
3023                 engine->irq_get = gen8_ring_get_irq;
3024                 engine->irq_put = gen8_ring_put_irq;
3025                 engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
3026                 if (i915_semaphore_is_enabled(dev)) {
3027                         engine->semaphore.sync_to = gen8_ring_sync;
3028                         engine->semaphore.signal = gen8_xcs_signal;
3029                         GEN8_RING_SEMAPHORE_INIT(engine);
3030                 }
3031         } else {
3032                 engine->irq_enable_mask = GT_BLT_USER_INTERRUPT;
3033                 engine->irq_get = gen6_ring_get_irq;
3034                 engine->irq_put = gen6_ring_put_irq;
3035                 engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
3036                 if (i915_semaphore_is_enabled(dev)) {
3037                         engine->semaphore.signal = gen6_signal;
3038                         engine->semaphore.sync_to = gen6_ring_sync;
3039                         /*
3040                          * The current semaphore is only applied on pre-gen8
3041                          * platform.  And there is no VCS2 ring on the pre-gen8
3042                          * platform. So the semaphore between BCS and VCS2 is
3043                          * initialized as INVALID.  Gen8 will initialize the
3044                          * sema between BCS and VCS2 later.
3045                          */
3046                         engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR;
3047                         engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV;
3048                         engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID;
3049                         engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE;
3050                         engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
3051                         engine->semaphore.mbox.signal[RCS] = GEN6_RBSYNC;
3052                         engine->semaphore.mbox.signal[VCS] = GEN6_VBSYNC;
3053                         engine->semaphore.mbox.signal[BCS] = GEN6_NOSYNC;
3054                         engine->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC;
3055                         engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
3056                 }
3057         }
3058         engine->init_hw = init_ring_common;
3059
3060         return intel_init_ring_buffer(dev, engine);
3061 }
3062
3063 int intel_init_vebox_ring_buffer(struct drm_device *dev)
3064 {
3065         struct drm_i915_private *dev_priv = dev->dev_private;
3066         struct intel_engine_cs *engine = &dev_priv->engine[VECS];
3067
3068         engine->name = "video enhancement ring";
3069         engine->id = VECS;
3070         engine->exec_id = I915_EXEC_VEBOX;
3071         engine->hw_id = 3;
3072
3073         engine->mmio_base = VEBOX_RING_BASE;
3074         engine->write_tail = ring_write_tail;
3075         engine->flush = gen6_ring_flush;
3076         engine->add_request = gen6_add_request;
3077         engine->irq_seqno_barrier = gen6_seqno_barrier;
3078         engine->get_seqno = ring_get_seqno;
3079         engine->set_seqno = ring_set_seqno;
3080
3081         if (INTEL_INFO(dev)->gen >= 8) {
3082                 engine->irq_enable_mask =
3083                         GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
3084                 engine->irq_get = gen8_ring_get_irq;
3085                 engine->irq_put = gen8_ring_put_irq;
3086                 engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
3087                 if (i915_semaphore_is_enabled(dev)) {
3088                         engine->semaphore.sync_to = gen8_ring_sync;
3089                         engine->semaphore.signal = gen8_xcs_signal;
3090                         GEN8_RING_SEMAPHORE_INIT(engine);
3091                 }
3092         } else {
3093                 engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
3094                 engine->irq_get = hsw_vebox_get_irq;
3095                 engine->irq_put = hsw_vebox_put_irq;
3096                 engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
3097                 if (i915_semaphore_is_enabled(dev)) {
3098                         engine->semaphore.sync_to = gen6_ring_sync;
3099                         engine->semaphore.signal = gen6_signal;
3100                         engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;
3101                         engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV;
3102                         engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB;
3103                         engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID;
3104                         engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
3105                         engine->semaphore.mbox.signal[RCS] = GEN6_RVESYNC;
3106                         engine->semaphore.mbox.signal[VCS] = GEN6_VVESYNC;
3107                         engine->semaphore.mbox.signal[BCS] = GEN6_BVESYNC;
3108                         engine->semaphore.mbox.signal[VECS] = GEN6_NOSYNC;
3109                         engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
3110                 }
3111         }
3112         engine->init_hw = init_ring_common;
3113
3114         return intel_init_ring_buffer(dev, engine);
3115 }
3116
3117 int
3118 intel_ring_flush_all_caches(struct drm_i915_gem_request *req)
3119 {
3120         struct intel_engine_cs *engine = req->engine;
3121         int ret;
3122
3123         if (!engine->gpu_caches_dirty)
3124                 return 0;
3125
3126         ret = engine->flush(req, 0, I915_GEM_GPU_DOMAINS);
3127         if (ret)
3128                 return ret;
3129
3130         trace_i915_gem_ring_flush(req, 0, I915_GEM_GPU_DOMAINS);
3131
3132         engine->gpu_caches_dirty = false;
3133         return 0;
3134 }
3135
3136 int
3137 intel_ring_invalidate_all_caches(struct drm_i915_gem_request *req)
3138 {
3139         struct intel_engine_cs *engine = req->engine;
3140         uint32_t flush_domains;
3141         int ret;
3142
3143         flush_domains = 0;
3144         if (engine->gpu_caches_dirty)
3145                 flush_domains = I915_GEM_GPU_DOMAINS;
3146
3147         ret = engine->flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
3148         if (ret)
3149                 return ret;
3150
3151         trace_i915_gem_ring_flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
3152
3153         engine->gpu_caches_dirty = false;
3154         return 0;
3155 }
3156
3157 void
3158 intel_stop_engine(struct intel_engine_cs *engine)
3159 {
3160         int ret;
3161
3162         if (!intel_engine_initialized(engine))
3163                 return;
3164
3165         ret = intel_engine_idle(engine);
3166         if (ret)
3167                 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
3168                           engine->name, ret);
3169
3170         stop_ring(engine);
3171 }