drivers/gpu/drm/i915/intel_ringbuffer.c

   1 /*
   2  * Copyright © 2008-2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Zou Nan hai <nanhai.zou@intel.com>
  26  *    Xiang Hai hao<haihao.xiang@intel.com>
  27  *
  28  */
  29
  30 #include <linux/log2.h>
  31 #include <drm/drmP.h>
  32 #include "i915_drv.h"
  33 #include <drm/i915_drm.h>
  34 #include "i915_trace.h"
  35 #include "intel_drv.h"
  36
  37 int __intel_ring_space(int head, int tail, int size)
  38 {
  39         int space = head - tail;
  40         if (space <= 0)
  41                 space += size;
  42         return space - I915_RING_FREE_SPACE;
  43 }
  44
  45 void intel_ring_update_space(struct intel_ringbuffer *ringbuf)
  46 {
  47         if (ringbuf->last_retired_head != -1) {
  48                 ringbuf->head = ringbuf->last_retired_head;
  49                 ringbuf->last_retired_head = -1;
  50         }
  51
  52         ringbuf->space = __intel_ring_space(ringbuf->head & HEAD_ADDR,
  53                                             ringbuf->tail, ringbuf->size);
  54 }
  55
  56 bool intel_engine_stopped(struct intel_engine_cs *engine)
  57 {
  58         struct drm_i915_private *dev_priv = engine->dev->dev_private;
  59         return dev_priv->gpu_error.stop_rings & intel_engine_flag(engine);
  60 }
  61
  62 static void __intel_ring_advance(struct intel_engine_cs *engine)
  63 {
  64         struct intel_ringbuffer *ringbuf = engine->buffer;
  65         ringbuf->tail &= ringbuf->size - 1;
  66         if (intel_engine_stopped(engine))
  67                 return;
  68         engine->write_tail(engine, ringbuf->tail);
  69 }
  70
  71 static int
  72 gen2_render_ring_flush(struct drm_i915_gem_request *req,
  73                        u32      invalidate_domains,
  74                        u32      flush_domains)
  75 {
  76         struct intel_engine_cs *engine = req->engine;
  77         u32 cmd;
  78         int ret;
  79
  80         cmd = MI_FLUSH;
  81         if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
  82                 cmd |= MI_NO_WRITE_FLUSH;
  83
  84         if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
  85                 cmd |= MI_READ_FLUSH;
  86
  87         ret = intel_ring_begin(req, 2);
  88         if (ret)
  89                 return ret;
  90
  91         intel_ring_emit(engine, cmd);
  92         intel_ring_emit(engine, MI_NOOP);
  93         intel_ring_advance(engine);
  94
  95         return 0;
  96 }
  97
  98 static int
  99 gen4_render_ring_flush(struct drm_i915_gem_request *req,
 100                        u32      invalidate_domains,
 101                        u32      flush_domains)
 102 {
 103         struct intel_engine_cs *engine = req->engine;
 104         struct drm_device *dev = engine->dev;
 105         u32 cmd;
 106         int ret;
 107
 108         /*
 109          * read/write caches:
 110          *
 111          * I915_GEM_DOMAIN_RENDER is always invalidated, but is
 112          * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
 113          * also flushed at 2d versus 3d pipeline switches.
 114          *
 115          * read-only caches:
 116          *
 117          * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
 118          * MI_READ_FLUSH is set, and is always flushed on 965.
 119          *
 120          * I915_GEM_DOMAIN_COMMAND may not exist?
 121          *
 122          * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
 123          * invalidated when MI_EXE_FLUSH is set.
 124          *
 125          * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
 126          * invalidated with every MI_FLUSH.
 127          *
 128          * TLBs:
 129          *
 130          * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
 131          * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
 132          * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
 133          * are flushed at any MI_FLUSH.
 134          */
 135
 136         cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
 137         if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
 138                 cmd &= ~MI_NO_WRITE_FLUSH;
 139         if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
 140                 cmd |= MI_EXE_FLUSH;
 141
 142         if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
 143             (IS_G4X(dev) || IS_GEN5(dev)))
 144                 cmd |= MI_INVALIDATE_ISP;
 145
 146         ret = intel_ring_begin(req, 2);
 147         if (ret)
 148                 return ret;
 149
 150         intel_ring_emit(engine, cmd);
 151         intel_ring_emit(engine, MI_NOOP);
 152         intel_ring_advance(engine);
 153
 154         return 0;
 155 }
 156
 157 /**
 158  * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
 159  * implementing two workarounds on gen6.  From section 1.4.7.1
 160  * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
 161  *
 162  * [DevSNB-C+{W/A}] Before any depth stall flush (including those
 163  * produced by non-pipelined state commands), software needs to first
 164  * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
 165  * 0.
 166  *
 167  * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
 168  * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
 169  *
 170  * And the workaround for these two requires this workaround first:
 171  *
 172  * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
 173  * BEFORE the pipe-control with a post-sync op and no write-cache
 174  * flushes.
 175  *
 176  * And this last workaround is tricky because of the requirements on
 177  * that bit.  From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
 178  * volume 2 part 1:
 179  *
 180  *     "1 of the following must also be set:
 181  *      - Render Target Cache Flush Enable ([12] of DW1)
 182  *      - Depth Cache Flush Enable ([0] of DW1)
 183  *      - Stall at Pixel Scoreboard ([1] of DW1)
 184  *      - Depth Stall ([13] of DW1)
 185  *      - Post-Sync Operation ([13] of DW1)
 186  *      - Notify Enable ([8] of DW1)"
 187  *
 188  * The cache flushes require the workaround flush that triggered this
 189  * one, so we can't use it.  Depth stall would trigger the same.
 190  * Post-sync nonzero is what triggered this second workaround, so we
 191  * can't use that one either.  Notify enable is IRQs, which aren't
 192  * really our business.  That leaves only stall at scoreboard.
 193  */
 194 static int
 195 intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request *req)
 196 {
 197         struct intel_engine_cs *engine = req->engine;
 198         u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 199         int ret;
 200
 201         ret = intel_ring_begin(req, 6);
 202         if (ret)
 203                 return ret;
 204
 205         intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(5));
 206         intel_ring_emit(engine, PIPE_CONTROL_CS_STALL |
 207                         PIPE_CONTROL_STALL_AT_SCOREBOARD);
 208         intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 209         intel_ring_emit(engine, 0); /* low dword */
 210         intel_ring_emit(engine, 0); /* high dword */
 211         intel_ring_emit(engine, MI_NOOP);
 212         intel_ring_advance(engine);
 213
 214         ret = intel_ring_begin(req, 6);
 215         if (ret)
 216                 return ret;
 217
 218         intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(5));
 219         intel_ring_emit(engine, PIPE_CONTROL_QW_WRITE);
 220         intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 221         intel_ring_emit(engine, 0);
 222         intel_ring_emit(engine, 0);
 223         intel_ring_emit(engine, MI_NOOP);
 224         intel_ring_advance(engine);
 225
 226         return 0;
 227 }
 228
 229 static int
 230 gen6_render_ring_flush(struct drm_i915_gem_request *req,
 231                        u32 invalidate_domains, u32 flush_domains)
 232 {
 233         struct intel_engine_cs *engine = req->engine;
 234         u32 flags = 0;
 235         u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 236         int ret;
 237
 238         /* Force SNB workarounds for PIPE_CONTROL flushes */
 239         ret = intel_emit_post_sync_nonzero_flush(req);
 240         if (ret)
 241                 return ret;
 242
 243         /* Just flush everything.  Experiments have shown that reducing the
 244          * number of bits based on the write domains has little performance
 245          * impact.
 246          */
 247         if (flush_domains) {
 248                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 249                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 250                 /*
 251                  * Ensure that any following seqno writes only happen
 252                  * when the render cache is indeed flushed.
 253                  */
 254                 flags |= PIPE_CONTROL_CS_STALL;
 255         }
 256         if (invalidate_domains) {
 257                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 258                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 259                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 260                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 261                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 262                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 263                 /*
 264                  * TLB invalidate requires a post-sync write.
 265                  */
 266                 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
 267         }
 268
 269         ret = intel_ring_begin(req, 4);
 270         if (ret)
 271                 return ret;
 272
 273         intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4));
 274         intel_ring_emit(engine, flags);
 275         intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
 276         intel_ring_emit(engine, 0);
 277         intel_ring_advance(engine);
 278
 279         return 0;
 280 }
 281
 282 static int
 283 gen7_render_ring_cs_stall_wa(struct drm_i915_gem_request *req)
 284 {
 285         struct intel_engine_cs *engine = req->engine;
 286         int ret;
 287
 288         ret = intel_ring_begin(req, 4);
 289         if (ret)
 290                 return ret;
 291
 292         intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4));
 293         intel_ring_emit(engine, PIPE_CONTROL_CS_STALL |
 294                               PIPE_CONTROL_STALL_AT_SCOREBOARD);
 295         intel_ring_emit(engine, 0);
 296         intel_ring_emit(engine, 0);
 297         intel_ring_advance(engine);
 298
 299         return 0;
 300 }
 301
 302 static int
 303 gen7_render_ring_flush(struct drm_i915_gem_request *req,
 304                        u32 invalidate_domains, u32 flush_domains)
 305 {
 306         struct intel_engine_cs *engine = req->engine;
 307         u32 flags = 0;
 308         u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 309         int ret;
 310
 311         /*
 312          * Ensure that any following seqno writes only happen when the render
 313          * cache is indeed flushed.
 314          *
 315          * Workaround: 4th PIPE_CONTROL command (except the ones with only
 316          * read-cache invalidate bits set) must have the CS_STALL bit set. We
 317          * don't try to be clever and just set it unconditionally.
 318          */
 319         flags |= PIPE_CONTROL_CS_STALL;
 320
 321         /* Just flush everything.  Experiments have shown that reducing the
 322          * number of bits based on the write domains has little performance
 323          * impact.
 324          */
 325         if (flush_domains) {
 326                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 327                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 328                 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
 329                 flags |= PIPE_CONTROL_FLUSH_ENABLE;
 330         }
 331         if (invalidate_domains) {
 332                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 333                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 334                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 335                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 336                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 337                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 338                 flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
 339                 /*
 340                  * TLB invalidate requires a post-sync write.
 341                  */
 342                 flags |= PIPE_CONTROL_QW_WRITE;
 343                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 344
 345                 flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
 346
 347                 /* Workaround: we must issue a pipe_control with CS-stall bit
 348                  * set before a pipe_control command that has the state cache
 349                  * invalidate bit set. */
 350                 gen7_render_ring_cs_stall_wa(req);
 351         }
 352
 353         ret = intel_ring_begin(req, 4);
 354         if (ret)
 355                 return ret;
 356
 357         intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4));
 358         intel_ring_emit(engine, flags);
 359         intel_ring_emit(engine, scratch_addr);
 360         intel_ring_emit(engine, 0);
 361         intel_ring_advance(engine);
 362
 363         return 0;
 364 }
 365
 366 static int
 367 gen8_emit_pipe_control(struct drm_i915_gem_request *req,
 368                        u32 flags, u32 scratch_addr)
 369 {
 370         struct intel_engine_cs *engine = req->engine;
 371         int ret;
 372
 373         ret = intel_ring_begin(req, 6);
 374         if (ret)
 375                 return ret;
 376
 377         intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(6));
 378         intel_ring_emit(engine, flags);
 379         intel_ring_emit(engine, scratch_addr);
 380         intel_ring_emit(engine, 0);
 381         intel_ring_emit(engine, 0);
 382         intel_ring_emit(engine, 0);
 383         intel_ring_advance(engine);
 384
 385         return 0;
 386 }
 387
 388 static int
 389 gen8_render_ring_flush(struct drm_i915_gem_request *req,
 390                        u32 invalidate_domains, u32 flush_domains)
 391 {
 392         u32 flags = 0;
 393         u32 scratch_addr = req->engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 394         int ret;
 395
 396         flags |= PIPE_CONTROL_CS_STALL;
 397
 398         if (flush_domains) {
 399                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 400                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 401                 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
 402                 flags |= PIPE_CONTROL_FLUSH_ENABLE;
 403         }
 404         if (invalidate_domains) {
 405                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 406                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 407                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 408                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 409                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 410                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 411                 flags |= PIPE_CONTROL_QW_WRITE;
 412                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 413
 414                 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
 415                 ret = gen8_emit_pipe_control(req,
 416                                              PIPE_CONTROL_CS_STALL |
 417                                              PIPE_CONTROL_STALL_AT_SCOREBOARD,
 418                                              0);
 419                 if (ret)
 420                         return ret;
 421         }
 422
 423         return gen8_emit_pipe_control(req, flags, scratch_addr);
 424 }
 425
 426 static void ring_write_tail(struct intel_engine_cs *engine,
 427                             u32 value)
 428 {
 429         struct drm_i915_private *dev_priv = engine->dev->dev_private;
 430         I915_WRITE_TAIL(engine, value);
 431 }
 432
 433 u64 intel_ring_get_active_head(struct intel_engine_cs *engine)
 434 {
 435         struct drm_i915_private *dev_priv = engine->dev->dev_private;
 436         u64 acthd;
 437
 438         if (INTEL_INFO(engine->dev)->gen >= 8)
 439                 acthd = I915_READ64_2x32(RING_ACTHD(engine->mmio_base),
 440                                          RING_ACTHD_UDW(engine->mmio_base));
 441         else if (INTEL_INFO(engine->dev)->gen >= 4)
 442                 acthd = I915_READ(RING_ACTHD(engine->mmio_base));
 443         else
 444                 acthd = I915_READ(ACTHD);
 445
 446         return acthd;
 447 }
 448
 449 static void ring_setup_phys_status_page(struct intel_engine_cs *engine)
 450 {
 451         struct drm_i915_private *dev_priv = engine->dev->dev_private;
 452         u32 addr;
 453
 454         addr = dev_priv->status_page_dmah->busaddr;
 455         if (INTEL_INFO(engine->dev)->gen >= 4)
 456                 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
 457         I915_WRITE(HWS_PGA, addr);
 458 }
 459
 460 static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
 461 {
 462         struct drm_device *dev = engine->dev;
 463         struct drm_i915_private *dev_priv = engine->dev->dev_private;
 464         i915_reg_t mmio;
 465
 466         /* The ring status page addresses are no longer next to the rest of
 467          * the ring registers as of gen7.
 468          */
 469         if (IS_GEN7(dev)) {
 470                 switch (engine->id) {
 471                 case RCS:
 472                         mmio = RENDER_HWS_PGA_GEN7;
 473                         break;
 474                 case BCS:
 475                         mmio = BLT_HWS_PGA_GEN7;
 476                         break;
 477                 /*
 478                  * VCS2 actually doesn't exist on Gen7. Only shut up
 479                  * gcc switch check warning
 480                  */
 481                 case VCS2:
 482                 case VCS:
 483                         mmio = BSD_HWS_PGA_GEN7;
 484                         break;
 485                 case VECS:
 486                         mmio = VEBOX_HWS_PGA_GEN7;
 487                         break;
 488                 }
 489         } else if (IS_GEN6(engine->dev)) {
 490                 mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
 491         } else {
 492                 /* XXX: gen8 returns to sanity */
 493                 mmio = RING_HWS_PGA(engine->mmio_base);
 494         }
 495
 496         I915_WRITE(mmio, (u32)engine->status_page.gfx_addr);
 497         POSTING_READ(mmio);
 498
 499         /*
 500          * Flush the TLB for this page
 501          *
 502          * FIXME: These two bits have disappeared on gen8, so a question
 503          * arises: do we still need this and if so how should we go about
 504          * invalidating the TLB?
 505          */
 506         if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
 507                 i915_reg_t reg = RING_INSTPM(engine->mmio_base);
 508
 509                 /* ring should be idle before issuing a sync flush*/
 510                 WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0);
 511
 512                 I915_WRITE(reg,
 513                            _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
 514                                               INSTPM_SYNC_FLUSH));
 515                 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
 516                              1000))
 517                         DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
 518                                   engine->name);
 519         }
 520 }
 521
 522 static bool stop_ring(struct intel_engine_cs *engine)
 523 {
 524         struct drm_i915_private *dev_priv = to_i915(engine->dev);
 525
 526         if (!IS_GEN2(engine->dev)) {
 527                 I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING));
 528                 if (wait_for((I915_READ_MODE(engine) & MODE_IDLE) != 0, 1000)) {
 529                         DRM_ERROR("%s : timed out trying to stop ring\n",
 530                                   engine->name);
 531                         /* Sometimes we observe that the idle flag is not
 532                          * set even though the ring is empty. So double
 533                          * check before giving up.
 534                          */
 535                         if (I915_READ_HEAD(engine) != I915_READ_TAIL(engine))
 536                                 return false;
 537                 }
 538         }
 539
 540         I915_WRITE_CTL(engine, 0);
 541         I915_WRITE_HEAD(engine, 0);
 542         engine->write_tail(engine, 0);
 543
 544         if (!IS_GEN2(engine->dev)) {
 545                 (void)I915_READ_CTL(engine);
 546                 I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING));
 547         }
 548
 549         return (I915_READ_HEAD(engine) & HEAD_ADDR) == 0;
 550 }
 551
 552 void intel_engine_init_hangcheck(struct intel_engine_cs *engine)
 553 {
 554         memset(&engine->hangcheck, 0, sizeof(engine->hangcheck));
 555 }
 556
 557 static int init_ring_common(struct intel_engine_cs *engine)
 558 {
 559         struct drm_device *dev = engine->dev;
 560         struct drm_i915_private *dev_priv = dev->dev_private;
 561         struct intel_ringbuffer *ringbuf = engine->buffer;
 562         struct drm_i915_gem_object *obj = ringbuf->obj;
 563         int ret = 0;
 564
 565         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
 566
 567         if (!stop_ring(engine)) {
 568                 /* G45 ring initialization often fails to reset head to zero */
 569                 DRM_DEBUG_KMS("%s head not reset to zero "
 570                               "ctl %08x head %08x tail %08x start %08x\n",
 571                               engine->name,
 572                               I915_READ_CTL(engine),
 573                               I915_READ_HEAD(engine),
 574                               I915_READ_TAIL(engine),
 575                               I915_READ_START(engine));
 576
 577                 if (!stop_ring(engine)) {
 578                         DRM_ERROR("failed to set %s head to zero "
 579                                   "ctl %08x head %08x tail %08x start %08x\n",
 580                                   engine->name,
 581                                   I915_READ_CTL(engine),
 582                                   I915_READ_HEAD(engine),
 583                                   I915_READ_TAIL(engine),
 584                                   I915_READ_START(engine));
 585                         ret = -EIO;
 586                         goto out;
 587                 }
 588         }
 589
 590         if (I915_NEED_GFX_HWS(dev))
 591                 intel_ring_setup_status_page(engine);
 592         else
 593                 ring_setup_phys_status_page(engine);
 594
 595         /* Enforce ordering by reading HEAD register back */
 596         I915_READ_HEAD(engine);
 597
 598         /* Initialize the ring. This must happen _after_ we've cleared the ring
 599          * registers with the above sequence (the readback of the HEAD registers
 600          * also enforces ordering), otherwise the hw might lose the new ring
 601          * register values. */
 602         I915_WRITE_START(engine, i915_gem_obj_ggtt_offset(obj));
 603
 604         /* WaClearRingBufHeadRegAtInit:ctg,elk */
 605         if (I915_READ_HEAD(engine))
 606                 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
 607                           engine->name, I915_READ_HEAD(engine));
 608         I915_WRITE_HEAD(engine, 0);
 609         (void)I915_READ_HEAD(engine);
 610
 611         I915_WRITE_CTL(engine,
 612                         ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES)
 613                         | RING_VALID);
 614
 615         /* If the head is still not zero, the ring is dead */
 616         if (wait_for((I915_READ_CTL(engine) & RING_VALID) != 0 &&
 617                      I915_READ_START(engine) == i915_gem_obj_ggtt_offset(obj) &&
 618                      (I915_READ_HEAD(engine) & HEAD_ADDR) == 0, 50)) {
 619                 DRM_ERROR("%s initialization failed "
 620                           "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
 621                           engine->name,
 622                           I915_READ_CTL(engine),
 623                           I915_READ_CTL(engine) & RING_VALID,
 624                           I915_READ_HEAD(engine), I915_READ_TAIL(engine),
 625                           I915_READ_START(engine),
 626                           (unsigned long)i915_gem_obj_ggtt_offset(obj));
 627                 ret = -EIO;
 628                 goto out;
 629         }
 630
 631         ringbuf->last_retired_head = -1;
 632         ringbuf->head = I915_READ_HEAD(engine);
 633         ringbuf->tail = I915_READ_TAIL(engine) & TAIL_ADDR;
 634         intel_ring_update_space(ringbuf);
 635
 636         intel_engine_init_hangcheck(engine);
 637
 638 out:
 639         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
 640
 641         return ret;
 642 }
 643
 644 void
 645 intel_fini_pipe_control(struct intel_engine_cs *engine)
 646 {
 647         struct drm_device *dev = engine->dev;
 648
 649         if (engine->scratch.obj == NULL)
 650                 return;
 651
 652         if (INTEL_INFO(dev)->gen >= 5) {
 653                 kunmap(sg_page(engine->scratch.obj->pages->sgl));
 654                 i915_gem_object_ggtt_unpin(engine->scratch.obj);
 655         }
 656
 657         drm_gem_object_unreference(&engine->scratch.obj->base);
 658         engine->scratch.obj = NULL;
 659 }
 660
 661 int
 662 intel_init_pipe_control(struct intel_engine_cs *engine)
 663 {
 664         int ret;
 665
 666         WARN_ON(engine->scratch.obj);
 667
 668         engine->scratch.obj = i915_gem_alloc_object(engine->dev, 4096);
 669         if (engine->scratch.obj == NULL) {
 670                 DRM_ERROR("Failed to allocate seqno page\n");
 671                 ret = -ENOMEM;
 672                 goto err;
 673         }
 674
 675         ret = i915_gem_object_set_cache_level(engine->scratch.obj,
 676                                               I915_CACHE_LLC);
 677         if (ret)
 678                 goto err_unref;
 679
 680         ret = i915_gem_obj_ggtt_pin(engine->scratch.obj, 4096, 0);
 681         if (ret)
 682                 goto err_unref;
 683
 684         engine->scratch.gtt_offset = i915_gem_obj_ggtt_offset(engine->scratch.obj);
 685         engine->scratch.cpu_page = kmap(sg_page(engine->scratch.obj->pages->sgl));
 686         if (engine->scratch.cpu_page == NULL) {
 687                 ret = -ENOMEM;
 688                 goto err_unpin;
 689         }
 690
 691         DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
 692                          engine->name, engine->scratch.gtt_offset);
 693         return 0;
 694
 695 err_unpin:
 696         i915_gem_object_ggtt_unpin(engine->scratch.obj);
 697 err_unref:
 698         drm_gem_object_unreference(&engine->scratch.obj->base);
 699 err:
 700         return ret;
 701 }
 702
 703 static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req)
 704 {
 705         int ret, i;
 706         struct intel_engine_cs *engine = req->engine;
 707         struct drm_device *dev = engine->dev;
 708         struct drm_i915_private *dev_priv = dev->dev_private;
 709         struct i915_workarounds *w = &dev_priv->workarounds;
 710
 711         if (w->count == 0)
 712                 return 0;
 713
 714         engine->gpu_caches_dirty = true;
 715         ret = intel_ring_flush_all_caches(req);
 716         if (ret)
 717                 return ret;
 718
 719         ret = intel_ring_begin(req, (w->count * 2 + 2));
 720         if (ret)
 721                 return ret;
 722
 723         intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(w->count));
 724         for (i = 0; i < w->count; i++) {
 725                 intel_ring_emit_reg(engine, w->reg[i].addr);
 726                 intel_ring_emit(engine, w->reg[i].value);
 727         }
 728         intel_ring_emit(engine, MI_NOOP);
 729
 730         intel_ring_advance(engine);
 731
 732         engine->gpu_caches_dirty = true;
 733         ret = intel_ring_flush_all_caches(req);
 734         if (ret)
 735                 return ret;
 736
 737         DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count);
 738
 739         return 0;
 740 }
 741
 742 static int intel_rcs_ctx_init(struct drm_i915_gem_request *req)
 743 {
 744         int ret;
 745
 746         ret = intel_ring_workarounds_emit(req);
 747         if (ret != 0)
 748                 return ret;
 749
 750         ret = i915_gem_render_state_init(req);
 751         if (ret)
 752                 return ret;
 753
 754         return 0;
 755 }
 756
 757 static int wa_add(struct drm_i915_private *dev_priv,
 758                   i915_reg_t addr,
 759                   const u32 mask, const u32 val)
 760 {
 761         const u32 idx = dev_priv->workarounds.count;
 762
 763         if (WARN_ON(idx >= I915_MAX_WA_REGS))
 764                 return -ENOSPC;
 765
 766         dev_priv->workarounds.reg[idx].addr = addr;
 767         dev_priv->workarounds.reg[idx].value = val;
 768         dev_priv->workarounds.reg[idx].mask = mask;
 769
 770         dev_priv->workarounds.count++;
 771
 772         return 0;
 773 }
 774
 775 #define WA_REG(addr, mask, val) do { \
 776                 const int r = wa_add(dev_priv, (addr), (mask), (val)); \
 777                 if (r) \
 778                         return r; \
 779         } while (0)
 780
 781 #define WA_SET_BIT_MASKED(addr, mask) \
 782         WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
 783
 784 #define WA_CLR_BIT_MASKED(addr, mask) \
 785         WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
 786
 787 #define WA_SET_FIELD_MASKED(addr, mask, value) \
 788         WA_REG(addr, mask, _MASKED_FIELD(mask, value))
 789
 790 #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
 791 #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
 792
 793 #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
 794
 795 static int wa_ring_whitelist_reg(struct intel_engine_cs *engine,
 796                                  i915_reg_t reg)
 797 {
 798         struct drm_i915_private *dev_priv = engine->dev->dev_private;
 799         struct i915_workarounds *wa = &dev_priv->workarounds;
 800         const uint32_t index = wa->hw_whitelist_count[engine->id];
 801
 802         if (WARN_ON(index >= RING_MAX_NONPRIV_SLOTS))
 803                 return -EINVAL;
 804
 805         WA_WRITE(RING_FORCE_TO_NONPRIV(engine->mmio_base, index),
 806                  i915_mmio_reg_offset(reg));
 807         wa->hw_whitelist_count[engine->id]++;
 808
 809         return 0;
 810 }
 811
 812 static int gen8_init_workarounds(struct intel_engine_cs *engine)
 813 {
 814         struct drm_device *dev = engine->dev;
 815         struct drm_i915_private *dev_priv = dev->dev_private;
 816
 817         WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
 818
 819         /* WaDisableAsyncFlipPerfMode:bdw,chv */
 820         WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
 821
 822         /* WaDisablePartialInstShootdown:bdw,chv */
 823         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 824                           PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
 825
 826         /* Use Force Non-Coherent whenever executing a 3D context. This is a
 827          * workaround for for a possible hang in the unlikely event a TLB
 828          * invalidation occurs during a PSD flush.
 829          */
 830         /* WaForceEnableNonCoherent:bdw,chv */
 831         /* WaHdcDisableFetchWhenMasked:bdw,chv */
 832         WA_SET_BIT_MASKED(HDC_CHICKEN0,
 833                           HDC_DONOT_FETCH_MEM_WHEN_MASKED |
 834                           HDC_FORCE_NON_COHERENT);
 835
 836         /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
 837          * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
 838          *  polygons in the same 8x4 pixel/sample area to be processed without
 839          *  stalling waiting for the earlier ones to write to Hierarchical Z
 840          *  buffer."
 841          *
 842          * This optimization is off by default for BDW and CHV; turn it on.
 843          */
 844         WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
 845
 846         /* Wa4x4STCOptimizationDisable:bdw,chv */
 847         WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
 848
 849         /*
 850          * BSpec recommends 8x4 when MSAA is used,
 851          * however in practice 16x4 seems fastest.
 852          *
 853          * Note that PS/WM thread counts depend on the WIZ hashing
 854          * disable bit, which we don't touch here, but it's good
 855          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
 856          */
 857         WA_SET_FIELD_MASKED(GEN7_GT_MODE,
 858                             GEN6_WIZ_HASHING_MASK,
 859                             GEN6_WIZ_HASHING_16x4);
 860
 861         return 0;
 862 }
 863
 864 static int bdw_init_workarounds(struct intel_engine_cs *engine)
 865 {
 866         int ret;
 867         struct drm_device *dev = engine->dev;
 868         struct drm_i915_private *dev_priv = dev->dev_private;
 869
 870         ret = gen8_init_workarounds(engine);
 871         if (ret)
 872                 return ret;
 873
 874         /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
 875         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
 876
 877         /* WaDisableDopClockGating:bdw */
 878         WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
 879                           DOP_CLOCK_GATING_DISABLE);
 880
 881         WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
 882                           GEN8_SAMPLER_POWER_BYPASS_DIS);
 883
 884         WA_SET_BIT_MASKED(HDC_CHICKEN0,
 885                           /* WaForceContextSaveRestoreNonCoherent:bdw */
 886                           HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
 887                           /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
 888                           (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
 889
 890         return 0;
 891 }
 892
 893 static int chv_init_workarounds(struct intel_engine_cs *engine)
 894 {
 895         int ret;
 896         struct drm_device *dev = engine->dev;
 897         struct drm_i915_private *dev_priv = dev->dev_private;
 898
 899         ret = gen8_init_workarounds(engine);
 900         if (ret)
 901                 return ret;
 902
 903         /* WaDisableThreadStallDopClockGating:chv */
 904         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
 905
 906         /* Improve HiZ throughput on CHV. */
 907         WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
 908
 909         return 0;
 910 }
 911
 912 static int gen9_init_workarounds(struct intel_engine_cs *engine)
 913 {
 914         struct drm_device *dev = engine->dev;
 915         struct drm_i915_private *dev_priv = dev->dev_private;
 916         int ret;
 917
 918         /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl */
 919         I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
 920                    GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
 921
 922         /* WaDisableKillLogic:bxt,skl,kbl */
 923         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
 924                    ECOCHK_DIS_TLB);
 925
 926         /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl */
 927         /* WaDisablePartialInstShootdown:skl,bxt,kbl */
 928         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 929                           FLOW_CONTROL_ENABLE |
 930                           PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
 931
 932         /* Syncing dependencies between camera and graphics:skl,bxt,kbl */
 933         WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
 934                           GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
 935
 936         /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */
 937         if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
 938             IS_BXT_REVID(dev, 0, BXT_REVID_A1))
 939                 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
 940                                   GEN9_DG_MIRROR_FIX_ENABLE);
 941
 942         /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
 943         if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
 944             IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
 945                 WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
 946                                   GEN9_RHWO_OPTIMIZATION_DISABLE);
 947                 /*
 948                  * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set
 949                  * but we do that in per ctx batchbuffer as there is an issue
 950                  * with this register not getting restored on ctx restore
 951                  */
 952         }
 953
 954         /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl */
 955         /* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl */
 956         WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
 957                           GEN9_ENABLE_YV12_BUGFIX |
 958                           GEN9_ENABLE_GPGPU_PREEMPTION);
 959
 960         /* Wa4x4STCOptimizationDisable:skl,bxt,kbl */
 961         /* WaDisablePartialResolveInVc:skl,bxt,kbl */
 962         WA_SET_BIT_MASKED(CACHE_MODE_1, (GEN8_4x4_STC_OPTIMIZATION_DISABLE |
 963                                          GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE));
 964
 965         /* WaCcsTlbPrefetchDisable:skl,bxt,kbl */
 966         WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
 967                           GEN9_CCS_TLB_PREFETCH_ENABLE);
 968
 969         /* WaDisableMaskBasedCammingInRCC:skl,bxt */
 970         if (IS_SKL_REVID(dev, SKL_REVID_C0, SKL_REVID_C0) ||
 971             IS_BXT_REVID(dev, 0, BXT_REVID_A1))
 972                 WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
 973                                   PIXEL_MASK_CAMMING_DISABLE);
 974
 975         /* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl */
 976         WA_SET_BIT_MASKED(HDC_CHICKEN0,
 977                           HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
 978                           HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE);
 979
 980         /* WaForceEnableNonCoherent and WaDisableHDCInvalidation are
 981          * both tied to WaForceContextSaveRestoreNonCoherent
 982          * in some hsds for skl. We keep the tie for all gen9. The
 983          * documentation is a bit hazy and so we want to get common behaviour,
 984          * even though there is no clear evidence we would need both on kbl/bxt.
 985          * This area has been source of system hangs so we play it safe
 986          * and mimic the skl regardless of what bspec says.
 987          *
 988          * Use Force Non-Coherent whenever executing a 3D context. This
 989          * is a workaround for a possible hang in the unlikely event
 990          * a TLB invalidation occurs during a PSD flush.
 991          */
 992
 993         /* WaForceEnableNonCoherent:skl,bxt,kbl */
 994         WA_SET_BIT_MASKED(HDC_CHICKEN0,
 995                           HDC_FORCE_NON_COHERENT);
 996
 997         /* WaDisableHDCInvalidation:skl,bxt,kbl */
 998         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
 999                    BDW_DISABLE_HDC_INVALIDATION);
1000
1001         /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl */
1002         if (IS_SKYLAKE(dev_priv) ||
1003             IS_KABYLAKE(dev_priv) ||
1004             IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0))
1005                 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
1006                                   GEN8_SAMPLER_POWER_BYPASS_DIS);
1007
1008         /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl */
1009         WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
1010
1011         /* WaOCLCoherentLineFlush:skl,bxt,kbl */
1012         I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
1013                                     GEN8_LQSC_FLUSH_COHERENT_LINES));
1014
1015         /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt */
1016         ret = wa_ring_whitelist_reg(engine, GEN9_CTX_PREEMPT_REG);
1017         if (ret)
1018                 return ret;
1019
1020         /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl */
1021         ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1);
1022         if (ret)
1023                 return ret;
1024
1025         /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl */
1026         ret = wa_ring_whitelist_reg(engine, GEN8_HDC_CHICKEN1);
1027         if (ret)
1028                 return ret;
1029
1030         return 0;
1031 }
1032
1033 static int skl_tune_iz_hashing(struct intel_engine_cs *engine)
1034 {
1035         struct drm_device *dev = engine->dev;
1036         struct drm_i915_private *dev_priv = dev->dev_private;
1037         u8 vals[3] = { 0, 0, 0 };
1038         unsigned int i;
1039
1040         for (i = 0; i < 3; i++) {
1041                 u8 ss;
1042
1043                 /*
1044                  * Only consider slices where one, and only one, subslice has 7
1045                  * EUs
1046                  */
1047                 if (!is_power_of_2(dev_priv->info.subslice_7eu[i]))
1048                         continue;
1049
1050                 /*
1051                  * subslice_7eu[i] != 0 (because of the check above) and
1052                  * ss_max == 4 (maximum number of subslices possible per slice)
1053                  *
1054                  * ->    0 <= ss <= 3;
1055                  */
1056                 ss = ffs(dev_priv->info.subslice_7eu[i]) - 1;
1057                 vals[i] = 3 - ss;
1058         }
1059
1060         if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0)
1061                 return 0;
1062
1063         /* Tune IZ hashing. See intel_device_info_runtime_init() */
1064         WA_SET_FIELD_MASKED(GEN7_GT_MODE,
1065                             GEN9_IZ_HASHING_MASK(2) |
1066                             GEN9_IZ_HASHING_MASK(1) |
1067                             GEN9_IZ_HASHING_MASK(0),
1068                             GEN9_IZ_HASHING(2, vals[2]) |
1069                             GEN9_IZ_HASHING(1, vals[1]) |
1070                             GEN9_IZ_HASHING(0, vals[0]));
1071
1072         return 0;
1073 }
1074
1075 static int skl_init_workarounds(struct intel_engine_cs *engine)
1076 {
1077         int ret;
1078         struct drm_device *dev = engine->dev;
1079         struct drm_i915_private *dev_priv = dev->dev_private;
1080
1081         ret = gen9_init_workarounds(engine);
1082         if (ret)
1083                 return ret;
1084
1085         /*
1086          * Actual WA is to disable percontext preemption granularity control
1087          * until D0 which is the default case so this is equivalent to
1088          * !WaDisablePerCtxtPreemptionGranularityControl:skl
1089          */
1090         if (IS_SKL_REVID(dev, SKL_REVID_E0, REVID_FOREVER)) {
1091                 I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1,
1092                            _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL));
1093         }
1094
1095         if (IS_SKL_REVID(dev, 0, SKL_REVID_D0)) {
1096                 /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
1097                 I915_WRITE(FF_SLICE_CS_CHICKEN2,
1098                            _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE));
1099         }
1100
1101         /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes
1102          * involving this register should also be added to WA batch as required.
1103          */
1104         if (IS_SKL_REVID(dev, 0, SKL_REVID_E0))
1105                 /* WaDisableLSQCROPERFforOCL:skl */
1106                 I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
1107                            GEN8_LQSC_RO_PERF_DIS);
1108
1109         /* WaEnableGapsTsvCreditFix:skl */
1110         if (IS_SKL_REVID(dev, SKL_REVID_C0, REVID_FOREVER)) {
1111                 I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
1112                                            GEN9_GAPS_TSV_CREDIT_DISABLE));
1113         }
1114
1115         /* WaDisablePowerCompilerClockGating:skl */
1116         if (IS_SKL_REVID(dev, SKL_REVID_B0, SKL_REVID_B0))
1117                 WA_SET_BIT_MASKED(HIZ_CHICKEN,
1118                                   BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
1119
1120         /* WaBarrierPerformanceFixDisable:skl */
1121         if (IS_SKL_REVID(dev, SKL_REVID_C0, SKL_REVID_D0))
1122                 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1123                                   HDC_FENCE_DEST_SLM_DISABLE |
1124                                   HDC_BARRIER_PERFORMANCE_DISABLE);
1125
1126         /* WaDisableSbeCacheDispatchPortSharing:skl */
1127         if (IS_SKL_REVID(dev, 0, SKL_REVID_F0))
1128                 WA_SET_BIT_MASKED(
1129                         GEN7_HALF_SLICE_CHICKEN1,
1130                         GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1131
1132         /* WaDisableGafsUnitClkGating:skl */
1133         WA_SET_BIT(GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
1134
1135         /* WaDisableLSQCROPERFforOCL:skl */
1136         ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
1137         if (ret)
1138                 return ret;
1139
1140         return skl_tune_iz_hashing(engine);
1141 }
1142
1143 static int bxt_init_workarounds(struct intel_engine_cs *engine)
1144 {
1145         int ret;
1146         struct drm_device *dev = engine->dev;
1147         struct drm_i915_private *dev_priv = dev->dev_private;
1148
1149         ret = gen9_init_workarounds(engine);
1150         if (ret)
1151                 return ret;
1152
1153         /* WaStoreMultiplePTEenable:bxt */
1154         /* This is a requirement according to Hardware specification */
1155         if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
1156                 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
1157
1158         /* WaSetClckGatingDisableMedia:bxt */
1159         if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
1160                 I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) &
1161                                             ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE));
1162         }
1163
1164         /* WaDisableThreadStallDopClockGating:bxt */
1165         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
1166                           STALL_DOP_GATING_DISABLE);
1167
1168         /* WaDisableSbeCacheDispatchPortSharing:bxt */
1169         if (IS_BXT_REVID(dev, 0, BXT_REVID_B0)) {
1170                 WA_SET_BIT_MASKED(
1171                         GEN7_HALF_SLICE_CHICKEN1,
1172                         GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1173         }
1174
1175         /* WaDisableObjectLevelPreemptionForTrifanOrPolygon:bxt */
1176         /* WaDisableObjectLevelPreemptionForInstancedDraw:bxt */
1177         /* WaDisableObjectLevelPreemtionForInstanceId:bxt */
1178         /* WaDisableLSQCROPERFforOCL:bxt */
1179         if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
1180                 ret = wa_ring_whitelist_reg(engine, GEN9_CS_DEBUG_MODE1);
1181                 if (ret)
1182                         return ret;
1183
1184                 ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
1185                 if (ret)
1186                         return ret;
1187         }
1188
1189         /* WaInsertDummyPushConstPs:bxt */
1190         if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0))
1191                 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
1192                                   GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
1193
1194         return 0;
1195 }
1196
1197 static int kbl_init_workarounds(struct intel_engine_cs *engine)
1198 {
1199         struct drm_i915_private *dev_priv = engine->dev->dev_private;
1200         int ret;
1201
1202         ret = gen9_init_workarounds(engine);
1203         if (ret)
1204                 return ret;
1205
1206         /* WaEnableGapsTsvCreditFix:kbl */
1207         I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
1208                                    GEN9_GAPS_TSV_CREDIT_DISABLE));
1209
1210         /* WaDisableDynamicCreditSharing:kbl */
1211         if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
1212                 WA_SET_BIT(GAMT_CHKN_BIT_REG,
1213                            GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING);
1214
1215         /* WaDisableFenceDestinationToSLM:kbl (pre-prod) */
1216         if (IS_KBL_REVID(dev_priv, KBL_REVID_A0, KBL_REVID_A0))
1217                 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1218                                   HDC_FENCE_DEST_SLM_DISABLE);
1219
1220         /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes
1221          * involving this register should also be added to WA batch as required.
1222          */
1223         if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_E0))
1224                 /* WaDisableLSQCROPERFforOCL:kbl */
1225                 I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
1226                            GEN8_LQSC_RO_PERF_DIS);
1227
1228         /* WaInsertDummyPushConstPs:kbl */
1229         if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
1230                 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
1231                                   GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
1232
1233         /* WaDisableLSQCROPERFforOCL:kbl */
1234         ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
1235         if (ret)
1236                 return ret;
1237
1238         return 0;
1239 }
1240
1241 int init_workarounds_ring(struct intel_engine_cs *engine)
1242 {
1243         struct drm_device *dev = engine->dev;
1244         struct drm_i915_private *dev_priv = dev->dev_private;
1245
1246         WARN_ON(engine->id != RCS);
1247
1248         dev_priv->workarounds.count = 0;
1249         dev_priv->workarounds.hw_whitelist_count[RCS] = 0;
1250
1251         if (IS_BROADWELL(dev))
1252                 return bdw_init_workarounds(engine);
1253
1254         if (IS_CHERRYVIEW(dev))
1255                 return chv_init_workarounds(engine);
1256
1257         if (IS_SKYLAKE(dev))
1258                 return skl_init_workarounds(engine);
1259
1260         if (IS_BROXTON(dev))
1261                 return bxt_init_workarounds(engine);
1262
1263         if (IS_KABYLAKE(dev_priv))
1264                 return kbl_init_workarounds(engine);
1265
1266         return 0;
1267 }
1268
1269 static int init_render_ring(struct intel_engine_cs *engine)
1270 {
1271         struct drm_device *dev = engine->dev;
1272         struct drm_i915_private *dev_priv = dev->dev_private;
1273         int ret = init_ring_common(engine);
1274         if (ret)
1275                 return ret;
1276
1277         /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
1278         if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7)
1279                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
1280
1281         /* We need to disable the AsyncFlip performance optimisations in order
1282          * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1283          * programmed to '1' on all products.
1284          *
1285          * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
1286          */
1287         if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
1288                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1289
1290         /* Required for the hardware to program scanline values for waiting */
1291         /* WaEnableFlushTlbInvalidationMode:snb */
1292         if (INTEL_INFO(dev)->gen == 6)
1293                 I915_WRITE(GFX_MODE,
1294                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
1295
1296         /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
1297         if (IS_GEN7(dev))
1298                 I915_WRITE(GFX_MODE_GEN7,
1299                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
1300                            _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
1301
1302         if (IS_GEN6(dev)) {
1303                 /* From the Sandybridge PRM, volume 1 part 3, page 24:
1304                  * "If this bit is set, STCunit will have LRA as replacement
1305                  *  policy. [...] This bit must be reset.  LRA replacement
1306                  *  policy is not supported."
1307                  */
1308                 I915_WRITE(CACHE_MODE_0,
1309                            _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
1310         }
1311
1312         if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
1313                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
1314
1315         if (HAS_L3_DPF(dev))
1316                 I915_WRITE_IMR(engine, ~GT_PARITY_ERROR(dev));
1317
1318         return init_workarounds_ring(engine);
1319 }
1320
1321 static void render_ring_cleanup(struct intel_engine_cs *engine)
1322 {
1323         struct drm_device *dev = engine->dev;
1324         struct drm_i915_private *dev_priv = dev->dev_private;
1325
1326         if (dev_priv->semaphore_obj) {
1327                 i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj);
1328                 drm_gem_object_unreference(&dev_priv->semaphore_obj->base);
1329                 dev_priv->semaphore_obj = NULL;
1330         }
1331
1332         intel_fini_pipe_control(engine);
1333 }
1334
1335 static int gen8_rcs_signal(struct drm_i915_gem_request *signaller_req,
1336                            unsigned int num_dwords)
1337 {
1338 #define MBOX_UPDATE_DWORDS 8
1339         struct intel_engine_cs *signaller = signaller_req->engine;
1340         struct drm_device *dev = signaller->dev;
1341         struct drm_i915_private *dev_priv = dev->dev_private;
1342         struct intel_engine_cs *waiter;
1343         enum intel_engine_id id;
1344         int ret, num_rings;
1345
1346         num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1347         num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1348 #undef MBOX_UPDATE_DWORDS
1349
1350         ret = intel_ring_begin(signaller_req, num_dwords);
1351         if (ret)
1352                 return ret;
1353
1354         for_each_engine_id(waiter, dev_priv, id) {
1355                 u32 seqno;
1356                 u64 gtt_offset = signaller->semaphore.signal_ggtt[id];
1357                 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1358                         continue;
1359
1360                 seqno = i915_gem_request_get_seqno(signaller_req);
1361                 intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
1362                 intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |
1363                                            PIPE_CONTROL_QW_WRITE |
1364                                            PIPE_CONTROL_FLUSH_ENABLE);
1365                 intel_ring_emit(signaller, lower_32_bits(gtt_offset));
1366                 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
1367                 intel_ring_emit(signaller, seqno);
1368                 intel_ring_emit(signaller, 0);
1369                 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1370                                            MI_SEMAPHORE_TARGET(waiter->hw_id));
1371                 intel_ring_emit(signaller, 0);
1372         }
1373
1374         return 0;
1375 }
1376
1377 static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req,
1378                            unsigned int num_dwords)
1379 {
1380 #define MBOX_UPDATE_DWORDS 6
1381         struct intel_engine_cs *signaller = signaller_req->engine;
1382         struct drm_device *dev = signaller->dev;
1383         struct drm_i915_private *dev_priv = dev->dev_private;
1384         struct intel_engine_cs *waiter;
1385         enum intel_engine_id id;
1386         int ret, num_rings;
1387
1388         num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1389         num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1390 #undef MBOX_UPDATE_DWORDS
1391
1392         ret = intel_ring_begin(signaller_req, num_dwords);
1393         if (ret)
1394                 return ret;
1395
1396         for_each_engine_id(waiter, dev_priv, id) {
1397                 u32 seqno;
1398                 u64 gtt_offset = signaller->semaphore.signal_ggtt[id];
1399                 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1400                         continue;
1401
1402                 seqno = i915_gem_request_get_seqno(signaller_req);
1403                 intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |
1404                                            MI_FLUSH_DW_OP_STOREDW);
1405                 intel_ring_emit(signaller, lower_32_bits(gtt_offset) |
1406                                            MI_FLUSH_DW_USE_GTT);
1407                 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
1408                 intel_ring_emit(signaller, seqno);
1409                 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1410                                            MI_SEMAPHORE_TARGET(waiter->hw_id));
1411                 intel_ring_emit(signaller, 0);
1412         }
1413
1414         return 0;
1415 }
1416
1417 static int gen6_signal(struct drm_i915_gem_request *signaller_req,
1418                        unsigned int num_dwords)
1419 {
1420         struct intel_engine_cs *signaller = signaller_req->engine;
1421         struct drm_device *dev = signaller->dev;
1422         struct drm_i915_private *dev_priv = dev->dev_private;
1423         struct intel_engine_cs *useless;
1424         enum intel_engine_id id;
1425         int ret, num_rings;
1426
1427 #define MBOX_UPDATE_DWORDS 3
1428         num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1429         num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
1430 #undef MBOX_UPDATE_DWORDS
1431
1432         ret = intel_ring_begin(signaller_req, num_dwords);
1433         if (ret)
1434                 return ret;
1435
1436         for_each_engine_id(useless, dev_priv, id) {
1437                 i915_reg_t mbox_reg = signaller->semaphore.mbox.signal[id];
1438
1439                 if (i915_mmio_reg_valid(mbox_reg)) {
1440                         u32 seqno = i915_gem_request_get_seqno(signaller_req);
1441
1442                         intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
1443                         intel_ring_emit_reg(signaller, mbox_reg);
1444                         intel_ring_emit(signaller, seqno);
1445                 }
1446         }
1447
1448         /* If num_dwords was rounded, make sure the tail pointer is correct */
1449         if (num_rings % 2 == 0)
1450                 intel_ring_emit(signaller, MI_NOOP);
1451
1452         return 0;
1453 }
1454
1455 /**
1456  * gen6_add_request - Update the semaphore mailbox registers
1457  *
1458  * @request - request to write to the ring
1459  *
1460  * Update the mailbox registers in the *other* rings with the current seqno.
1461  * This acts like a signal in the canonical semaphore.
1462  */
1463 static int
1464 gen6_add_request(struct drm_i915_gem_request *req)
1465 {
1466         struct intel_engine_cs *engine = req->engine;
1467         int ret;
1468
1469         if (engine->semaphore.signal)
1470                 ret = engine->semaphore.signal(req, 4);
1471         else
1472                 ret = intel_ring_begin(req, 4);
1473
1474         if (ret)
1475                 return ret;
1476
1477         intel_ring_emit(engine, MI_STORE_DWORD_INDEX);
1478         intel_ring_emit(engine,
1479                         I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1480         intel_ring_emit(engine, i915_gem_request_get_seqno(req));
1481         intel_ring_emit(engine, MI_USER_INTERRUPT);
1482         __intel_ring_advance(engine);
1483
1484         return 0;
1485 }
1486
1487 static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
1488                                               u32 seqno)
1489 {
1490         struct drm_i915_private *dev_priv = dev->dev_private;
1491         return dev_priv->last_seqno < seqno;
1492 }
1493
1494 /**
1495  * intel_ring_sync - sync the waiter to the signaller on seqno
1496  *
1497  * @waiter - ring that is waiting
1498  * @signaller - ring which has, or will signal
1499  * @seqno - seqno which the waiter will block on
1500  */
1501
1502 static int
1503 gen8_ring_sync(struct drm_i915_gem_request *waiter_req,
1504                struct intel_engine_cs *signaller,
1505                u32 seqno)
1506 {
1507         struct intel_engine_cs *waiter = waiter_req->engine;
1508         struct drm_i915_private *dev_priv = waiter->dev->dev_private;
1509         int ret;
1510
1511         ret = intel_ring_begin(waiter_req, 4);
1512         if (ret)
1513                 return ret;
1514
1515         intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |
1516                                 MI_SEMAPHORE_GLOBAL_GTT |
1517                                 MI_SEMAPHORE_POLL |
1518                                 MI_SEMAPHORE_SAD_GTE_SDD);
1519         intel_ring_emit(waiter, seqno);
1520         intel_ring_emit(waiter,
1521                         lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1522         intel_ring_emit(waiter,
1523                         upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1524         intel_ring_advance(waiter);
1525         return 0;
1526 }
1527
1528 static int
1529 gen6_ring_sync(struct drm_i915_gem_request *waiter_req,
1530                struct intel_engine_cs *signaller,
1531                u32 seqno)
1532 {
1533         struct intel_engine_cs *waiter = waiter_req->engine;
1534         u32 dw1 = MI_SEMAPHORE_MBOX |
1535                   MI_SEMAPHORE_COMPARE |
1536                   MI_SEMAPHORE_REGISTER;
1537         u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id];
1538         int ret;
1539
1540         /* Throughout all of the GEM code, seqno passed implies our current
1541          * seqno is >= the last seqno executed. However for hardware the
1542          * comparison is strictly greater than.
1543          */
1544         seqno -= 1;
1545
1546         WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
1547
1548         ret = intel_ring_begin(waiter_req, 4);
1549         if (ret)
1550                 return ret;
1551
1552         /* If seqno wrap happened, omit the wait with no-ops */
1553         if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
1554                 intel_ring_emit(waiter, dw1 | wait_mbox);
1555                 intel_ring_emit(waiter, seqno);
1556                 intel_ring_emit(waiter, 0);
1557                 intel_ring_emit(waiter, MI_NOOP);
1558         } else {
1559                 intel_ring_emit(waiter, MI_NOOP);
1560                 intel_ring_emit(waiter, MI_NOOP);
1561                 intel_ring_emit(waiter, MI_NOOP);
1562                 intel_ring_emit(waiter, MI_NOOP);
1563         }
1564         intel_ring_advance(waiter);
1565
1566         return 0;
1567 }
1568
1569 #define PIPE_CONTROL_FLUSH(ring__, addr__)                                      \
1570 do {                                                                    \
1571         intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |                \
1572                  PIPE_CONTROL_DEPTH_STALL);                             \
1573         intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT);                    \
1574         intel_ring_emit(ring__, 0);                                                     \
1575         intel_ring_emit(ring__, 0);                                                     \
1576 } while (0)
1577
1578 static int
1579 pc_render_add_request(struct drm_i915_gem_request *req)
1580 {
1581         struct intel_engine_cs *engine = req->engine;
1582         u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
1583         int ret;
1584
1585         /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
1586          * incoherent with writes to memory, i.e. completely fubar,
1587          * so we need to use PIPE_NOTIFY instead.
1588          *
1589          * However, we also need to workaround the qword write
1590          * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
1591          * memory before requesting an interrupt.
1592          */
1593         ret = intel_ring_begin(req, 32);
1594         if (ret)
1595                 return ret;
1596
1597         intel_ring_emit(engine,
1598                         GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1599                         PIPE_CONTROL_WRITE_FLUSH |
1600                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
1601         intel_ring_emit(engine,
1602                         engine->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1603         intel_ring_emit(engine, i915_gem_request_get_seqno(req));
1604         intel_ring_emit(engine, 0);
1605         PIPE_CONTROL_FLUSH(engine, scratch_addr);
1606         scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
1607         PIPE_CONTROL_FLUSH(engine, scratch_addr);
1608         scratch_addr += 2 * CACHELINE_BYTES;
1609         PIPE_CONTROL_FLUSH(engine, scratch_addr);
1610         scratch_addr += 2 * CACHELINE_BYTES;
1611         PIPE_CONTROL_FLUSH(engine, scratch_addr);
1612         scratch_addr += 2 * CACHELINE_BYTES;
1613         PIPE_CONTROL_FLUSH(engine, scratch_addr);
1614         scratch_addr += 2 * CACHELINE_BYTES;
1615         PIPE_CONTROL_FLUSH(engine, scratch_addr);
1616
1617         intel_ring_emit(engine,
1618                         GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1619                         PIPE_CONTROL_WRITE_FLUSH |
1620                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
1621                         PIPE_CONTROL_NOTIFY);
1622         intel_ring_emit(engine,
1623                         engine->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1624         intel_ring_emit(engine, i915_gem_request_get_seqno(req));
1625         intel_ring_emit(engine, 0);
1626         __intel_ring_advance(engine);
1627
1628         return 0;
1629 }
1630
1631 static void
1632 gen6_seqno_barrier(struct intel_engine_cs *engine)
1633 {
1634         struct drm_i915_private *dev_priv = engine->dev->dev_private;
1635
1636         /* Workaround to force correct ordering between irq and seqno writes on
1637          * ivb (and maybe also on snb) by reading from a CS register (like
1638          * ACTHD) before reading the status page.
1639          *
1640          * Note that this effectively stalls the read by the time it takes to
1641          * do a memory transaction, which more or less ensures that the write
1642          * from the GPU has sufficient time to invalidate the CPU cacheline.
1643          * Alternatively we could delay the interrupt from the CS ring to give
1644          * the write time to land, but that would incur a delay after every
1645          * batch i.e. much more frequent than a delay when waiting for the
1646          * interrupt (with the same net latency).
1647          *
1648          * Also note that to prevent whole machine hangs on gen7, we have to
1649          * take the spinlock to guard against concurrent cacheline access.
1650          */
1651         spin_lock_irq(&dev_priv->uncore.lock);
1652         POSTING_READ_FW(RING_ACTHD(engine->mmio_base));
1653         spin_unlock_irq(&dev_priv->uncore.lock);
1654 }
1655
1656 static u32
1657 ring_get_seqno(struct intel_engine_cs *engine)
1658 {
1659         return intel_read_status_page(engine, I915_GEM_HWS_INDEX);
1660 }
1661
1662 static void
1663 ring_set_seqno(struct intel_engine_cs *engine, u32 seqno)
1664 {
1665         intel_write_status_page(engine, I915_GEM_HWS_INDEX, seqno);
1666 }
1667
1668 static u32
1669 pc_render_get_seqno(struct intel_engine_cs *engine)
1670 {
1671         return engine->scratch.cpu_page[0];
1672 }
1673
1674 static void
1675 pc_render_set_seqno(struct intel_engine_cs *engine, u32 seqno)
1676 {
1677         engine->scratch.cpu_page[0] = seqno;
1678 }
1679
1680 static bool
1681 gen5_ring_get_irq(struct intel_engine_cs *engine)
1682 {
1683         struct drm_device *dev = engine->dev;
1684         struct drm_i915_private *dev_priv = dev->dev_private;
1685         unsigned long flags;
1686
1687         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1688                 return false;
1689
1690         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1691         if (engine->irq_refcount++ == 0)
1692                 gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask);
1693         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1694
1695         return true;
1696 }
1697
1698 static void
1699 gen5_ring_put_irq(struct intel_engine_cs *engine)
1700 {
1701         struct drm_device *dev = engine->dev;
1702         struct drm_i915_private *dev_priv = dev->dev_private;
1703         unsigned long flags;
1704
1705         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1706         if (--engine->irq_refcount == 0)
1707                 gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask);
1708         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1709 }
1710
1711 static bool
1712 i9xx_ring_get_irq(struct intel_engine_cs *engine)
1713 {
1714         struct drm_device *dev = engine->dev;
1715         struct drm_i915_private *dev_priv = dev->dev_private;
1716         unsigned long flags;
1717
1718         if (!intel_irqs_enabled(dev_priv))
1719                 return false;
1720
1721         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1722         if (engine->irq_refcount++ == 0) {
1723                 dev_priv->irq_mask &= ~engine->irq_enable_mask;
1724                 I915_WRITE(IMR, dev_priv->irq_mask);
1725                 POSTING_READ(IMR);
1726         }
1727         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1728
1729         return true;
1730 }
1731
1732 static void
1733 i9xx_ring_put_irq(struct intel_engine_cs *engine)
1734 {
1735         struct drm_device *dev = engine->dev;
1736         struct drm_i915_private *dev_priv = dev->dev_private;
1737         unsigned long flags;
1738
1739         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1740         if (--engine->irq_refcount == 0) {
1741                 dev_priv->irq_mask |= engine->irq_enable_mask;
1742                 I915_WRITE(IMR, dev_priv->irq_mask);
1743                 POSTING_READ(IMR);
1744         }
1745         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1746 }
1747
1748 static bool
1749 i8xx_ring_get_irq(struct intel_engine_cs *engine)
1750 {
1751         struct drm_device *dev = engine->dev;
1752         struct drm_i915_private *dev_priv = dev->dev_private;
1753         unsigned long flags;
1754
1755         if (!intel_irqs_enabled(dev_priv))
1756                 return false;
1757
1758         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1759         if (engine->irq_refcount++ == 0) {
1760                 dev_priv->irq_mask &= ~engine->irq_enable_mask;
1761                 I915_WRITE16(IMR, dev_priv->irq_mask);
1762                 POSTING_READ16(IMR);
1763         }
1764         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1765
1766         return true;
1767 }
1768
1769 static void
1770 i8xx_ring_put_irq(struct intel_engine_cs *engine)
1771 {
1772         struct drm_device *dev = engine->dev;
1773         struct drm_i915_private *dev_priv = dev->dev_private;
1774         unsigned long flags;
1775
1776         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1777         if (--engine->irq_refcount == 0) {
1778                 dev_priv->irq_mask |= engine->irq_enable_mask;
1779                 I915_WRITE16(IMR, dev_priv->irq_mask);
1780                 POSTING_READ16(IMR);
1781         }
1782         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1783 }
1784
1785 static int
1786 bsd_ring_flush(struct drm_i915_gem_request *req,
1787                u32     invalidate_domains,
1788                u32     flush_domains)
1789 {
1790         struct intel_engine_cs *engine = req->engine;
1791         int ret;
1792
1793         ret = intel_ring_begin(req, 2);
1794         if (ret)
1795                 return ret;
1796
1797         intel_ring_emit(engine, MI_FLUSH);
1798         intel_ring_emit(engine, MI_NOOP);
1799         intel_ring_advance(engine);
1800         return 0;
1801 }
1802
1803 static int
1804 i9xx_add_request(struct drm_i915_gem_request *req)
1805 {
1806         struct intel_engine_cs *engine = req->engine;
1807         int ret;
1808
1809         ret = intel_ring_begin(req, 4);
1810         if (ret)
1811                 return ret;
1812
1813         intel_ring_emit(engine, MI_STORE_DWORD_INDEX);
1814         intel_ring_emit(engine,
1815                         I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1816         intel_ring_emit(engine, i915_gem_request_get_seqno(req));
1817         intel_ring_emit(engine, MI_USER_INTERRUPT);
1818         __intel_ring_advance(engine);
1819
1820         return 0;
1821 }
1822
1823 static bool
1824 gen6_ring_get_irq(struct intel_engine_cs *engine)
1825 {
1826         struct drm_device *dev = engine->dev;
1827         struct drm_i915_private *dev_priv = dev->dev_private;
1828         unsigned long flags;
1829
1830         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1831                 return false;
1832
1833         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1834         if (engine->irq_refcount++ == 0) {
1835                 if (HAS_L3_DPF(dev) && engine->id == RCS)
1836                         I915_WRITE_IMR(engine,
1837                                        ~(engine->irq_enable_mask |
1838                                          GT_PARITY_ERROR(dev)));
1839                 else
1840                         I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
1841                 gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask);
1842         }
1843         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1844
1845         return true;
1846 }
1847
1848 static void
1849 gen6_ring_put_irq(struct intel_engine_cs *engine)
1850 {
1851         struct drm_device *dev = engine->dev;
1852         struct drm_i915_private *dev_priv = dev->dev_private;
1853         unsigned long flags;
1854
1855         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1856         if (--engine->irq_refcount == 0) {
1857                 if (HAS_L3_DPF(dev) && engine->id == RCS)
1858                         I915_WRITE_IMR(engine, ~GT_PARITY_ERROR(dev));
1859                 else
1860                         I915_WRITE_IMR(engine, ~0);
1861                 gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask);
1862         }
1863         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1864 }
1865
1866 static bool
1867 hsw_vebox_get_irq(struct intel_engine_cs *engine)
1868 {
1869         struct drm_device *dev = engine->dev;
1870         struct drm_i915_private *dev_priv = dev->dev_private;
1871         unsigned long flags;
1872
1873         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1874                 return false;
1875
1876         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1877         if (engine->irq_refcount++ == 0) {
1878                 I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
1879                 gen6_enable_pm_irq(dev_priv, engine->irq_enable_mask);
1880         }
1881         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1882
1883         return true;
1884 }
1885
1886 static void
1887 hsw_vebox_put_irq(struct intel_engine_cs *engine)
1888 {
1889         struct drm_device *dev = engine->dev;
1890         struct drm_i915_private *dev_priv = dev->dev_private;
1891         unsigned long flags;
1892
1893         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1894         if (--engine->irq_refcount == 0) {
1895                 I915_WRITE_IMR(engine, ~0);
1896                 gen6_disable_pm_irq(dev_priv, engine->irq_enable_mask);
1897         }
1898         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1899 }
1900
1901 static bool
1902 gen8_ring_get_irq(struct intel_engine_cs *engine)
1903 {
1904         struct drm_device *dev = engine->dev;
1905         struct drm_i915_private *dev_priv = dev->dev_private;
1906         unsigned long flags;
1907
1908         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1909                 return false;
1910
1911         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1912         if (engine->irq_refcount++ == 0) {
1913                 if (HAS_L3_DPF(dev) && engine->id == RCS) {
1914                         I915_WRITE_IMR(engine,
1915                                        ~(engine->irq_enable_mask |
1916                                          GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1917                 } else {
1918                         I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
1919                 }
1920                 POSTING_READ(RING_IMR(engine->mmio_base));
1921         }
1922         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1923
1924         return true;
1925 }
1926
1927 static void
1928 gen8_ring_put_irq(struct intel_engine_cs *engine)
1929 {
1930         struct drm_device *dev = engine->dev;
1931         struct drm_i915_private *dev_priv = dev->dev_private;
1932         unsigned long flags;
1933
1934         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1935         if (--engine->irq_refcount == 0) {
1936                 if (HAS_L3_DPF(dev) && engine->id == RCS) {
1937                         I915_WRITE_IMR(engine,
1938                                        ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1939                 } else {
1940                         I915_WRITE_IMR(engine, ~0);
1941                 }
1942                 POSTING_READ(RING_IMR(engine->mmio_base));
1943         }
1944         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1945 }
1946
1947 static int
1948 i965_dispatch_execbuffer(struct drm_i915_gem_request *req,
1949                          u64 offset, u32 length,
1950                          unsigned dispatch_flags)
1951 {
1952         struct intel_engine_cs *engine = req->engine;
1953         int ret;
1954
1955         ret = intel_ring_begin(req, 2);
1956         if (ret)
1957                 return ret;
1958
1959         intel_ring_emit(engine,
1960                         MI_BATCH_BUFFER_START |
1961                         MI_BATCH_GTT |
1962                         (dispatch_flags & I915_DISPATCH_SECURE ?
1963                          0 : MI_BATCH_NON_SECURE_I965));
1964         intel_ring_emit(engine, offset);
1965         intel_ring_advance(engine);
1966
1967         return 0;
1968 }
1969
1970 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1971 #define I830_BATCH_LIMIT (256*1024)
1972 #define I830_TLB_ENTRIES (2)
1973 #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
1974 static int
1975 i830_dispatch_execbuffer(struct drm_i915_gem_request *req,
1976                          u64 offset, u32 len,
1977                          unsigned dispatch_flags)
1978 {
1979         struct intel_engine_cs *engine = req->engine;
1980         u32 cs_offset = engine->scratch.gtt_offset;
1981         int ret;
1982
1983         ret = intel_ring_begin(req, 6);
1984         if (ret)
1985                 return ret;
1986
1987         /* Evict the invalid PTE TLBs */
1988         intel_ring_emit(engine, COLOR_BLT_CMD | BLT_WRITE_RGBA);
1989         intel_ring_emit(engine, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096);
1990         intel_ring_emit(engine, I830_TLB_ENTRIES << 16 | 4); /* load each page */
1991         intel_ring_emit(engine, cs_offset);
1992         intel_ring_emit(engine, 0xdeadbeef);
1993         intel_ring_emit(engine, MI_NOOP);
1994         intel_ring_advance(engine);
1995
1996         if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) {
1997                 if (len > I830_BATCH_LIMIT)
1998                         return -ENOSPC;
1999
2000                 ret = intel_ring_begin(req, 6 + 2);
2001                 if (ret)
2002                         return ret;
2003
2004                 /* Blit the batch (which has now all relocs applied) to the
2005                  * stable batch scratch bo area (so that the CS never
2006                  * stumbles over its tlb invalidation bug) ...
2007                  */
2008                 intel_ring_emit(engine, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA);
2009                 intel_ring_emit(engine,
2010                                 BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096);
2011                 intel_ring_emit(engine, DIV_ROUND_UP(len, 4096) << 16 | 4096);
2012                 intel_ring_emit(engine, cs_offset);
2013                 intel_ring_emit(engine, 4096);
2014                 intel_ring_emit(engine, offset);
2015
2016                 intel_ring_emit(engine, MI_FLUSH);
2017                 intel_ring_emit(engine, MI_NOOP);
2018                 intel_ring_advance(engine);
2019
2020                 /* ... and execute it. */
2021                 offset = cs_offset;
2022         }
2023
2024         ret = intel_ring_begin(req, 2);
2025         if (ret)
2026                 return ret;
2027
2028         intel_ring_emit(engine, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
2029         intel_ring_emit(engine, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
2030                                           0 : MI_BATCH_NON_SECURE));
2031         intel_ring_advance(engine);
2032
2033         return 0;
2034 }
2035
2036 static int
2037 i915_dispatch_execbuffer(struct drm_i915_gem_request *req,
2038                          u64 offset, u32 len,
2039                          unsigned dispatch_flags)
2040 {
2041         struct intel_engine_cs *engine = req->engine;
2042         int ret;
2043
2044         ret = intel_ring_begin(req, 2);
2045         if (ret)
2046                 return ret;
2047
2048         intel_ring_emit(engine, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
2049         intel_ring_emit(engine, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
2050                                           0 : MI_BATCH_NON_SECURE));
2051         intel_ring_advance(engine);
2052
2053         return 0;
2054 }
2055
2056 static void cleanup_phys_status_page(struct intel_engine_cs *engine)
2057 {
2058         struct drm_i915_private *dev_priv = to_i915(engine->dev);
2059
2060         if (!dev_priv->status_page_dmah)
2061                 return;
2062
2063         drm_pci_free(engine->dev, dev_priv->status_page_dmah);
2064         engine->status_page.page_addr = NULL;
2065 }
2066
2067 static void cleanup_status_page(struct intel_engine_cs *engine)
2068 {
2069         struct drm_i915_gem_object *obj;
2070
2071         obj = engine->status_page.obj;
2072         if (obj == NULL)
2073                 return;
2074
2075         kunmap(sg_page(obj->pages->sgl));
2076         i915_gem_object_ggtt_unpin(obj);
2077         drm_gem_object_unreference(&obj->base);
2078         engine->status_page.obj = NULL;
2079 }
2080
2081 static int init_status_page(struct intel_engine_cs *engine)
2082 {
2083         struct drm_i915_gem_object *obj = engine->status_page.obj;
2084
2085         if (obj == NULL) {
2086                 unsigned flags;
2087                 int ret;
2088
2089                 obj = i915_gem_alloc_object(engine->dev, 4096);
2090                 if (obj == NULL) {
2091                         DRM_ERROR("Failed to allocate status page\n");
2092                         return -ENOMEM;
2093                 }
2094
2095                 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2096                 if (ret)
2097                         goto err_unref;
2098
2099                 flags = 0;
2100                 if (!HAS_LLC(engine->dev))
2101                         /* On g33, we cannot place HWS above 256MiB, so
2102                          * restrict its pinning to the low mappable arena.
2103                          * Though this restriction is not documented for
2104                          * gen4, gen5, or byt, they also behave similarly
2105                          * and hang if the HWS is placed at the top of the
2106                          * GTT. To generalise, it appears that all !llc
2107                          * platforms have issues with us placing the HWS
2108                          * above the mappable region (even though we never
2109                          * actualy map it).
2110                          */
2111                         flags |= PIN_MAPPABLE;
2112                 ret = i915_gem_obj_ggtt_pin(obj, 4096, flags);
2113                 if (ret) {
2114 err_unref:
2115                         drm_gem_object_unreference(&obj->base);
2116                         return ret;
2117                 }
2118
2119                 engine->status_page.obj = obj;
2120         }
2121
2122         engine->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
2123         engine->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
2124         memset(engine->status_page.page_addr, 0, PAGE_SIZE);
2125
2126         DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
2127                         engine->name, engine->status_page.gfx_addr);
2128
2129         return 0;
2130 }
2131
2132 static int init_phys_status_page(struct intel_engine_cs *engine)
2133 {
2134         struct drm_i915_private *dev_priv = engine->dev->dev_private;
2135
2136         if (!dev_priv->status_page_dmah) {
2137                 dev_priv->status_page_dmah =
2138                         drm_pci_alloc(engine->dev, PAGE_SIZE, PAGE_SIZE);
2139                 if (!dev_priv->status_page_dmah)
2140                         return -ENOMEM;
2141         }
2142
2143         engine->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
2144         memset(engine->status_page.page_addr, 0, PAGE_SIZE);
2145
2146         return 0;
2147 }
2148
2149 void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
2150 {
2151         if (HAS_LLC(ringbuf->obj->base.dev) && !ringbuf->obj->stolen)
2152                 i915_gem_object_unpin_map(ringbuf->obj);
2153         else
2154                 iounmap(ringbuf->virtual_start);
2155         ringbuf->virtual_start = NULL;
2156         ringbuf->vma = NULL;
2157         i915_gem_object_ggtt_unpin(ringbuf->obj);
2158 }
2159
2160 int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
2161                                      struct intel_ringbuffer *ringbuf)
2162 {
2163         struct drm_i915_private *dev_priv = to_i915(dev);
2164         struct i915_ggtt *ggtt = &dev_priv->ggtt;
2165         struct drm_i915_gem_object *obj = ringbuf->obj;
2166         /* Ring wraparound at offset 0 sometimes hangs. No idea why. */
2167         unsigned flags = PIN_OFFSET_BIAS | 4096;
2168         void *addr;
2169         int ret;
2170
2171         if (HAS_LLC(dev_priv) && !obj->stolen) {
2172                 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, flags);
2173                 if (ret)
2174                         return ret;
2175
2176                 ret = i915_gem_object_set_to_cpu_domain(obj, true);
2177                 if (ret)
2178                         goto err_unpin;
2179
2180                 addr = i915_gem_object_pin_map(obj);
2181                 if (IS_ERR(addr)) {
2182                         ret = PTR_ERR(addr);
2183                         goto err_unpin;
2184                 }
2185         } else {
2186                 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE,
2187                                             flags | PIN_MAPPABLE);
2188                 if (ret)
2189                         return ret;
2190
2191                 ret = i915_gem_object_set_to_gtt_domain(obj, true);
2192                 if (ret)
2193                         goto err_unpin;
2194
2195                 /* Access through the GTT requires the device to be awake. */
2196                 assert_rpm_wakelock_held(dev_priv);
2197
2198                 addr = ioremap_wc(ggtt->mappable_base +
2199                                   i915_gem_obj_ggtt_offset(obj), ringbuf->size);
2200                 if (addr == NULL) {
2201                         ret = -ENOMEM;
2202                         goto err_unpin;
2203                 }
2204         }
2205
2206         ringbuf->virtual_start = addr;
2207         ringbuf->vma = i915_gem_obj_to_ggtt(obj);
2208         return 0;
2209
2210 err_unpin:
2211         i915_gem_object_ggtt_unpin(obj);
2212         return ret;
2213 }
2214
2215 static void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
2216 {
2217         drm_gem_object_unreference(&ringbuf->obj->base);
2218         ringbuf->obj = NULL;
2219 }
2220
2221 static int intel_alloc_ringbuffer_obj(struct drm_device *dev,
2222                                       struct intel_ringbuffer *ringbuf)
2223 {
2224         struct drm_i915_gem_object *obj;
2225
2226         obj = NULL;
2227         if (!HAS_LLC(dev))
2228                 obj = i915_gem_object_create_stolen(dev, ringbuf->size);
2229         if (obj == NULL)
2230                 obj = i915_gem_alloc_object(dev, ringbuf->size);
2231         if (obj == NULL)
2232                 return -ENOMEM;
2233
2234         /* mark ring buffers as read-only from GPU side by default */
2235         obj->gt_ro = 1;
2236
2237         ringbuf->obj = obj;
2238
2239         return 0;
2240 }
2241
2242 struct intel_ringbuffer *
2243 intel_engine_create_ringbuffer(struct intel_engine_cs *engine, int size)
2244 {
2245         struct intel_ringbuffer *ring;
2246         int ret;
2247
2248         ring = kzalloc(sizeof(*ring), GFP_KERNEL);
2249         if (ring == NULL) {
2250                 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n",
2251                                  engine->name);
2252                 return ERR_PTR(-ENOMEM);
2253         }
2254
2255         ring->engine = engine;
2256         list_add(&ring->link, &engine->buffers);
2257
2258         ring->size = size;
2259         /* Workaround an erratum on the i830 which causes a hang if
2260          * the TAIL pointer points to within the last 2 cachelines
2261          * of the buffer.
2262          */
2263         ring->effective_size = size;
2264         if (IS_I830(engine->dev) || IS_845G(engine->dev))
2265                 ring->effective_size -= 2 * CACHELINE_BYTES;
2266
2267         ring->last_retired_head = -1;
2268         intel_ring_update_space(ring);
2269
2270         ret = intel_alloc_ringbuffer_obj(engine->dev, ring);
2271         if (ret) {
2272                 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s: %d\n",
2273                                  engine->name, ret);
2274                 list_del(&ring->link);
2275                 kfree(ring);
2276                 return ERR_PTR(ret);
2277         }
2278
2279         return ring;
2280 }
2281
2282 void
2283 intel_ringbuffer_free(struct intel_ringbuffer *ring)
2284 {
2285         intel_destroy_ringbuffer_obj(ring);
2286         list_del(&ring->link);
2287         kfree(ring);
2288 }
2289
2290 static int intel_init_ring_buffer(struct drm_device *dev,
2291                                   struct intel_engine_cs *engine)
2292 {
2293         struct intel_ringbuffer *ringbuf;
2294         int ret;
2295
2296         WARN_ON(engine->buffer);
2297
2298         engine->dev = dev;
2299         INIT_LIST_HEAD(&engine->active_list);
2300         INIT_LIST_HEAD(&engine->request_list);
2301         INIT_LIST_HEAD(&engine->execlist_queue);
2302         INIT_LIST_HEAD(&engine->buffers);
2303         i915_gem_batch_pool_init(dev, &engine->batch_pool);
2304         memset(engine->semaphore.sync_seqno, 0,
2305                sizeof(engine->semaphore.sync_seqno));
2306
2307         init_waitqueue_head(&engine->irq_queue);
2308
2309         ringbuf = intel_engine_create_ringbuffer(engine, 32 * PAGE_SIZE);
2310         if (IS_ERR(ringbuf)) {
2311                 ret = PTR_ERR(ringbuf);
2312                 goto error;
2313         }
2314         engine->buffer = ringbuf;
2315
2316         if (I915_NEED_GFX_HWS(dev)) {
2317                 ret = init_status_page(engine);
2318                 if (ret)
2319                         goto error;
2320         } else {
2321                 WARN_ON(engine->id != RCS);
2322                 ret = init_phys_status_page(engine);
2323                 if (ret)
2324                         goto error;
2325         }
2326
2327         ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
2328         if (ret) {
2329                 DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
2330                                 engine->name, ret);
2331                 intel_destroy_ringbuffer_obj(ringbuf);
2332                 goto error;
2333         }
2334
2335         ret = i915_cmd_parser_init_ring(engine);
2336         if (ret)
2337                 goto error;
2338
2339         return 0;
2340
2341 error:
2342         intel_cleanup_engine(engine);
2343         return ret;
2344 }
2345
2346 void intel_cleanup_engine(struct intel_engine_cs *engine)
2347 {
2348         struct drm_i915_private *dev_priv;
2349
2350         if (!intel_engine_initialized(engine))
2351                 return;
2352
2353         dev_priv = to_i915(engine->dev);
2354
2355         if (engine->buffer) {
2356                 intel_stop_engine(engine);
2357                 WARN_ON(!IS_GEN2(engine->dev) && (I915_READ_MODE(engine) & MODE_IDLE) == 0);
2358
2359                 intel_unpin_ringbuffer_obj(engine->buffer);
2360                 intel_ringbuffer_free(engine->buffer);
2361                 engine->buffer = NULL;
2362         }
2363
2364         if (engine->cleanup)
2365                 engine->cleanup(engine);
2366
2367         if (I915_NEED_GFX_HWS(engine->dev)) {
2368                 cleanup_status_page(engine);
2369         } else {
2370                 WARN_ON(engine->id != RCS);
2371                 cleanup_phys_status_page(engine);
2372         }
2373
2374         i915_cmd_parser_fini_ring(engine);
2375         i915_gem_batch_pool_fini(&engine->batch_pool);
2376         engine->dev = NULL;
2377 }
2378
2379 int intel_engine_idle(struct intel_engine_cs *engine)
2380 {
2381         struct drm_i915_gem_request *req;
2382
2383         /* Wait upon the last request to be completed */
2384         if (list_empty(&engine->request_list))
2385                 return 0;
2386
2387         req = list_entry(engine->request_list.prev,
2388                          struct drm_i915_gem_request,
2389                          list);
2390
2391         /* Make sure we do not trigger any retires */
2392         return __i915_wait_request(req,
2393                                    req->i915->mm.interruptible,
2394                                    NULL, NULL);
2395 }
2396
2397 int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request)
2398 {
2399         request->ringbuf = request->engine->buffer;
2400         return 0;
2401 }
2402
2403 int intel_ring_reserve_space(struct drm_i915_gem_request *request)
2404 {
2405         /*
2406          * The first call merely notes the reserve request and is common for
2407          * all back ends. The subsequent localised _begin() call actually
2408          * ensures that the reservation is available. Without the begin, if
2409          * the request creator immediately submitted the request without
2410          * adding any commands to it then there might not actually be
2411          * sufficient room for the submission commands.
2412          */
2413         intel_ring_reserved_space_reserve(request->ringbuf, MIN_SPACE_FOR_ADD_REQUEST);
2414
2415         return intel_ring_begin(request, 0);
2416 }
2417
2418 void intel_ring_reserved_space_reserve(struct intel_ringbuffer *ringbuf, int size)
2419 {
2420         GEM_BUG_ON(ringbuf->reserved_size);
2421         ringbuf->reserved_size = size;
2422 }
2423
2424 void intel_ring_reserved_space_cancel(struct intel_ringbuffer *ringbuf)
2425 {
2426         GEM_BUG_ON(!ringbuf->reserved_size);
2427         ringbuf->reserved_size   = 0;
2428 }
2429
2430 void intel_ring_reserved_space_use(struct intel_ringbuffer *ringbuf)
2431 {
2432         GEM_BUG_ON(!ringbuf->reserved_size);
2433         ringbuf->reserved_size   = 0;
2434 }
2435
2436 void intel_ring_reserved_space_end(struct intel_ringbuffer *ringbuf)
2437 {
2438         GEM_BUG_ON(ringbuf->reserved_size);
2439 }
2440
2441 static int wait_for_space(struct drm_i915_gem_request *req, int bytes)
2442 {
2443         struct intel_ringbuffer *ringbuf = req->ringbuf;
2444         struct intel_engine_cs *engine = req->engine;
2445         struct drm_i915_gem_request *target;
2446
2447         intel_ring_update_space(ringbuf);
2448         if (ringbuf->space >= bytes)
2449                 return 0;
2450
2451         /*
2452          * Space is reserved in the ringbuffer for finalising the request,
2453          * as that cannot be allowed to fail. During request finalisation,
2454          * reserved_space is set to 0 to stop the overallocation and the
2455          * assumption is that then we never need to wait (which has the
2456          * risk of failing with EINTR).
2457          *
2458          * See also i915_gem_request_alloc() and i915_add_request().
2459          */
2460         GEM_BUG_ON(!ringbuf->reserved_size);
2461
2462         list_for_each_entry(target, &engine->request_list, list) {
2463                 unsigned space;
2464
2465                 /*
2466                  * The request queue is per-engine, so can contain requests
2467                  * from multiple ringbuffers. Here, we must ignore any that
2468                  * aren't from the ringbuffer we're considering.
2469                  */
2470                 if (target->ringbuf != ringbuf)
2471                         continue;
2472
2473                 /* Would completion of this request free enough space? */
2474                 space = __intel_ring_space(target->postfix, ringbuf->tail,
2475                                            ringbuf->size);
2476                 if (space >= bytes)
2477                         break;
2478         }
2479
2480         if (WARN_ON(&target->list == &engine->request_list))
2481                 return -ENOSPC;
2482
2483         return i915_wait_request(target);
2484 }
2485
2486 int intel_ring_begin(struct drm_i915_gem_request *req, int num_dwords)
2487 {
2488         struct intel_ringbuffer *ringbuf = req->ringbuf;
2489         int remain_actual = ringbuf->size - ringbuf->tail;
2490         int remain_usable = ringbuf->effective_size - ringbuf->tail;
2491         int bytes = num_dwords * sizeof(u32);
2492         int total_bytes, wait_bytes;
2493         bool need_wrap = false;
2494
2495         total_bytes = bytes + ringbuf->reserved_size;
2496
2497         if (unlikely(bytes > remain_usable)) {
2498                 /*
2499                  * Not enough space for the basic request. So need to flush
2500                  * out the remainder and then wait for base + reserved.
2501                  */
2502                 wait_bytes = remain_actual + total_bytes;
2503                 need_wrap = true;
2504         } else if (unlikely(total_bytes > remain_usable)) {
2505                 /*
2506                  * The base request will fit but the reserved space
2507                  * falls off the end. So we don't need an immediate wrap
2508                  * and only need to effectively wait for the reserved
2509                  * size space from the start of ringbuffer.
2510                  */
2511                 wait_bytes = remain_actual + ringbuf->reserved_size;
2512         } else {
2513                 /* No wrapping required, just waiting. */
2514                 wait_bytes = total_bytes;
2515         }
2516
2517         if (wait_bytes > ringbuf->space) {
2518                 int ret = wait_for_space(req, wait_bytes);
2519                 if (unlikely(ret))
2520                         return ret;
2521
2522                 intel_ring_update_space(ringbuf);
2523                 if (unlikely(ringbuf->space < wait_bytes))
2524                         return -EAGAIN;
2525         }
2526
2527         if (unlikely(need_wrap)) {
2528                 GEM_BUG_ON(remain_actual > ringbuf->space);
2529                 GEM_BUG_ON(ringbuf->tail + remain_actual > ringbuf->size);
2530
2531                 /* Fill the tail with MI_NOOP */
2532                 memset(ringbuf->virtual_start + ringbuf->tail,
2533                        0, remain_actual);
2534                 ringbuf->tail = 0;
2535                 ringbuf->space -= remain_actual;
2536         }
2537
2538         ringbuf->space -= bytes;
2539         GEM_BUG_ON(ringbuf->space < 0);
2540         return 0;
2541 }
2542
2543 /* Align the ring tail to a cacheline boundary */
2544 int intel_ring_cacheline_align(struct drm_i915_gem_request *req)
2545 {
2546         struct intel_engine_cs *engine = req->engine;
2547         int num_dwords = (engine->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
2548         int ret;
2549
2550         if (num_dwords == 0)
2551                 return 0;
2552
2553         num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
2554         ret = intel_ring_begin(req, num_dwords);
2555         if (ret)
2556                 return ret;
2557
2558         while (num_dwords--)
2559                 intel_ring_emit(engine, MI_NOOP);
2560
2561         intel_ring_advance(engine);
2562
2563         return 0;
2564 }
2565
2566 void intel_ring_init_seqno(struct intel_engine_cs *engine, u32 seqno)
2567 {
2568         struct drm_i915_private *dev_priv = to_i915(engine->dev);
2569
2570         /* Our semaphore implementation is strictly monotonic (i.e. we proceed
2571          * so long as the semaphore value in the register/page is greater
2572          * than the sync value), so whenever we reset the seqno,
2573          * so long as we reset the tracking semaphore value to 0, it will
2574          * always be before the next request's seqno. If we don't reset
2575          * the semaphore value, then when the seqno moves backwards all
2576          * future waits will complete instantly (causing rendering corruption).
2577          */
2578         if (INTEL_INFO(dev_priv)->gen == 6 || INTEL_INFO(dev_priv)->gen == 7) {
2579                 I915_WRITE(RING_SYNC_0(engine->mmio_base), 0);
2580                 I915_WRITE(RING_SYNC_1(engine->mmio_base), 0);
2581                 if (HAS_VEBOX(dev_priv))
2582                         I915_WRITE(RING_SYNC_2(engine->mmio_base), 0);
2583         }
2584         if (dev_priv->semaphore_obj) {
2585                 struct drm_i915_gem_object *obj = dev_priv->semaphore_obj;
2586                 struct page *page = i915_gem_object_get_dirty_page(obj, 0);
2587                 void *semaphores = kmap(page);
2588                 memset(semaphores + GEN8_SEMAPHORE_OFFSET(engine->id, 0),
2589                        0, I915_NUM_ENGINES * gen8_semaphore_seqno_size);
2590                 kunmap(page);
2591         }
2592         memset(engine->semaphore.sync_seqno, 0,
2593                sizeof(engine->semaphore.sync_seqno));
2594
2595         engine->set_seqno(engine, seqno);
2596         engine->last_submitted_seqno = seqno;
2597
2598         engine->hangcheck.seqno = seqno;
2599 }
2600
2601 static void gen6_bsd_ring_write_tail(struct intel_engine_cs *engine,
2602                                      u32 value)
2603 {
2604         struct drm_i915_private *dev_priv = engine->dev->dev_private;
2605
2606        /* Every tail move must follow the sequence below */
2607
2608         /* Disable notification that the ring is IDLE. The GT
2609          * will then assume that it is busy and bring it out of rc6.
2610          */
2611         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2612                    _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2613
2614         /* Clear the context id. Here be magic! */
2615         I915_WRITE64(GEN6_BSD_RNCID, 0x0);
2616
2617         /* Wait for the ring not to be idle, i.e. for it to wake up. */
2618         if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
2619                       GEN6_BSD_SLEEP_INDICATOR) == 0,
2620                      50))
2621                 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
2622
2623         /* Now that the ring is fully powered up, update the tail */
2624         I915_WRITE_TAIL(engine, value);
2625         POSTING_READ(RING_TAIL(engine->mmio_base));
2626
2627         /* Let the ring send IDLE messages to the GT again,
2628          * and so let it sleep to conserve power when idle.
2629          */
2630         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2631                    _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2632 }
2633
2634 static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req,
2635                                u32 invalidate, u32 flush)
2636 {
2637         struct intel_engine_cs *engine = req->engine;
2638         uint32_t cmd;
2639         int ret;
2640
2641         ret = intel_ring_begin(req, 4);
2642         if (ret)
2643                 return ret;
2644
2645         cmd = MI_FLUSH_DW;
2646         if (INTEL_INFO(engine->dev)->gen >= 8)
2647                 cmd += 1;
2648
2649         /* We always require a command barrier so that subsequent
2650          * commands, such as breadcrumb interrupts, are strictly ordered
2651          * wrt the contents of the write cache being flushed to memory
2652          * (and thus being coherent from the CPU).
2653          */
2654         cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2655
2656         /*
2657          * Bspec vol 1c.5 - video engine command streamer:
2658          * "If ENABLED, all TLBs will be invalidated once the flush
2659          * operation is complete. This bit is only valid when the
2660          * Post-Sync Operation field is a value of 1h or 3h."
2661          */
2662         if (invalidate & I915_GEM_GPU_DOMAINS)
2663                 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
2664
2665         intel_ring_emit(engine, cmd);
2666         intel_ring_emit(engine,
2667                         I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2668         if (INTEL_INFO(engine->dev)->gen >= 8) {
2669                 intel_ring_emit(engine, 0); /* upper addr */
2670                 intel_ring_emit(engine, 0); /* value */
2671         } else  {
2672                 intel_ring_emit(engine, 0);
2673                 intel_ring_emit(engine, MI_NOOP);
2674         }
2675         intel_ring_advance(engine);
2676         return 0;
2677 }
2678
2679 static int
2680 gen8_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
2681                               u64 offset, u32 len,
2682                               unsigned dispatch_flags)
2683 {
2684         struct intel_engine_cs *engine = req->engine;
2685         bool ppgtt = USES_PPGTT(engine->dev) &&
2686                         !(dispatch_flags & I915_DISPATCH_SECURE);
2687         int ret;
2688
2689         ret = intel_ring_begin(req, 4);
2690         if (ret)
2691                 return ret;
2692
2693         /* FIXME(BDW): Address space and security selectors. */
2694         intel_ring_emit(engine, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8) |
2695                         (dispatch_flags & I915_DISPATCH_RS ?
2696                          MI_BATCH_RESOURCE_STREAMER : 0));
2697         intel_ring_emit(engine, lower_32_bits(offset));
2698         intel_ring_emit(engine, upper_32_bits(offset));
2699         intel_ring_emit(engine, MI_NOOP);
2700         intel_ring_advance(engine);
2701
2702         return 0;
2703 }
2704
2705 static int
2706 hsw_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
2707                              u64 offset, u32 len,
2708                              unsigned dispatch_flags)
2709 {
2710         struct intel_engine_cs *engine = req->engine;
2711         int ret;
2712
2713         ret = intel_ring_begin(req, 2);
2714         if (ret)
2715                 return ret;
2716
2717         intel_ring_emit(engine,
2718                         MI_BATCH_BUFFER_START |
2719                         (dispatch_flags & I915_DISPATCH_SECURE ?
2720                          0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW) |
2721                         (dispatch_flags & I915_DISPATCH_RS ?
2722                          MI_BATCH_RESOURCE_STREAMER : 0));
2723         /* bit0-7 is the length on GEN6+ */
2724         intel_ring_emit(engine, offset);
2725         intel_ring_advance(engine);
2726
2727         return 0;
2728 }
2729
2730 static int
2731 gen6_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
2732                               u64 offset, u32 len,
2733                               unsigned dispatch_flags)
2734 {
2735         struct intel_engine_cs *engine = req->engine;
2736         int ret;
2737
2738         ret = intel_ring_begin(req, 2);
2739         if (ret)
2740                 return ret;
2741
2742         intel_ring_emit(engine,
2743                         MI_BATCH_BUFFER_START |
2744                         (dispatch_flags & I915_DISPATCH_SECURE ?
2745                          0 : MI_BATCH_NON_SECURE_I965));
2746         /* bit0-7 is the length on GEN6+ */
2747         intel_ring_emit(engine, offset);
2748         intel_ring_advance(engine);
2749
2750         return 0;
2751 }
2752
2753 /* Blitter support (SandyBridge+) */
2754
2755 static int gen6_ring_flush(struct drm_i915_gem_request *req,
2756                            u32 invalidate, u32 flush)
2757 {
2758         struct intel_engine_cs *engine = req->engine;
2759         struct drm_device *dev = engine->dev;
2760         uint32_t cmd;
2761         int ret;
2762
2763         ret = intel_ring_begin(req, 4);
2764         if (ret)
2765                 return ret;
2766
2767         cmd = MI_FLUSH_DW;
2768         if (INTEL_INFO(dev)->gen >= 8)
2769                 cmd += 1;
2770
2771         /* We always require a command barrier so that subsequent
2772          * commands, such as breadcrumb interrupts, are strictly ordered
2773          * wrt the contents of the write cache being flushed to memory
2774          * (and thus being coherent from the CPU).
2775          */
2776         cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2777
2778         /*
2779          * Bspec vol 1c.3 - blitter engine command streamer:
2780          * "If ENABLED, all TLBs will be invalidated once the flush
2781          * operation is complete. This bit is only valid when the
2782          * Post-Sync Operation field is a value of 1h or 3h."
2783          */
2784         if (invalidate & I915_GEM_DOMAIN_RENDER)
2785                 cmd |= MI_INVALIDATE_TLB;
2786         intel_ring_emit(engine, cmd);
2787         intel_ring_emit(engine,
2788                         I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2789         if (INTEL_INFO(dev)->gen >= 8) {
2790                 intel_ring_emit(engine, 0); /* upper addr */
2791                 intel_ring_emit(engine, 0); /* value */
2792         } else  {
2793                 intel_ring_emit(engine, 0);
2794                 intel_ring_emit(engine, MI_NOOP);
2795         }
2796         intel_ring_advance(engine);
2797
2798         return 0;
2799 }
2800
2801 int intel_init_render_ring_buffer(struct drm_device *dev)
2802 {
2803         struct drm_i915_private *dev_priv = dev->dev_private;
2804         struct intel_engine_cs *engine = &dev_priv->engine[RCS];
2805         struct drm_i915_gem_object *obj;
2806         int ret;
2807
2808         engine->name = "render ring";
2809         engine->id = RCS;
2810         engine->exec_id = I915_EXEC_RENDER;
2811         engine->hw_id = 0;
2812         engine->mmio_base = RENDER_RING_BASE;
2813
2814         if (INTEL_INFO(dev)->gen >= 8) {
2815                 if (i915_semaphore_is_enabled(dev)) {
2816                         obj = i915_gem_alloc_object(dev, 4096);
2817                         if (obj == NULL) {
2818                                 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2819                                 i915.semaphores = 0;
2820                         } else {
2821                                 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2822                                 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK);
2823                                 if (ret != 0) {
2824                                         drm_gem_object_unreference(&obj->base);
2825                                         DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2826                                         i915.semaphores = 0;
2827                                 } else
2828                                         dev_priv->semaphore_obj = obj;
2829                         }
2830                 }
2831
2832                 engine->init_context = intel_rcs_ctx_init;
2833                 engine->add_request = gen6_add_request;
2834                 engine->flush = gen8_render_ring_flush;
2835                 engine->irq_get = gen8_ring_get_irq;
2836                 engine->irq_put = gen8_ring_put_irq;
2837                 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2838                 engine->irq_seqno_barrier = gen6_seqno_barrier;
2839                 engine->get_seqno = ring_get_seqno;
2840                 engine->set_seqno = ring_set_seqno;
2841                 if (i915_semaphore_is_enabled(dev)) {
2842                         WARN_ON(!dev_priv->semaphore_obj);
2843                         engine->semaphore.sync_to = gen8_ring_sync;
2844                         engine->semaphore.signal = gen8_rcs_signal;
2845                         GEN8_RING_SEMAPHORE_INIT(engine);
2846                 }
2847         } else if (INTEL_INFO(dev)->gen >= 6) {
2848                 engine->init_context = intel_rcs_ctx_init;
2849                 engine->add_request = gen6_add_request;
2850                 engine->flush = gen7_render_ring_flush;
2851                 if (INTEL_INFO(dev)->gen == 6)
2852                         engine->flush = gen6_render_ring_flush;
2853                 engine->irq_get = gen6_ring_get_irq;
2854                 engine->irq_put = gen6_ring_put_irq;
2855                 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2856                 engine->irq_seqno_barrier = gen6_seqno_barrier;
2857                 engine->get_seqno = ring_get_seqno;
2858                 engine->set_seqno = ring_set_seqno;
2859                 if (i915_semaphore_is_enabled(dev)) {
2860                         engine->semaphore.sync_to = gen6_ring_sync;
2861                         engine->semaphore.signal = gen6_signal;
2862                         /*
2863                          * The current semaphore is only applied on pre-gen8
2864                          * platform.  And there is no VCS2 ring on the pre-gen8
2865                          * platform. So the semaphore between RCS and VCS2 is
2866                          * initialized as INVALID.  Gen8 will initialize the
2867                          * sema between VCS2 and RCS later.
2868                          */
2869                         engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID;
2870                         engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV;
2871                         engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB;
2872                         engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE;
2873                         engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2874                         engine->semaphore.mbox.signal[RCS] = GEN6_NOSYNC;
2875                         engine->semaphore.mbox.signal[VCS] = GEN6_VRSYNC;
2876                         engine->semaphore.mbox.signal[BCS] = GEN6_BRSYNC;
2877                         engine->semaphore.mbox.signal[VECS] = GEN6_VERSYNC;
2878                         engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2879                 }
2880         } else if (IS_GEN5(dev)) {
2881                 engine->add_request = pc_render_add_request;
2882                 engine->flush = gen4_render_ring_flush;
2883                 engine->get_seqno = pc_render_get_seqno;
2884                 engine->set_seqno = pc_render_set_seqno;
2885                 engine->irq_get = gen5_ring_get_irq;
2886                 engine->irq_put = gen5_ring_put_irq;
2887                 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
2888                                         GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
2889         } else {
2890                 engine->add_request = i9xx_add_request;
2891                 if (INTEL_INFO(dev)->gen < 4)
2892                         engine->flush = gen2_render_ring_flush;
2893                 else
2894                         engine->flush = gen4_render_ring_flush;
2895                 engine->get_seqno = ring_get_seqno;
2896                 engine->set_seqno = ring_set_seqno;
2897                 if (IS_GEN2(dev)) {
2898                         engine->irq_get = i8xx_ring_get_irq;
2899                         engine->irq_put = i8xx_ring_put_irq;
2900                 } else {
2901                         engine->irq_get = i9xx_ring_get_irq;
2902                         engine->irq_put = i9xx_ring_put_irq;
2903                 }
2904                 engine->irq_enable_mask = I915_USER_INTERRUPT;
2905         }
2906         engine->write_tail = ring_write_tail;
2907
2908         if (IS_HASWELL(dev))
2909                 engine->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
2910         else if (IS_GEN8(dev))
2911                 engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2912         else if (INTEL_INFO(dev)->gen >= 6)
2913                 engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2914         else if (INTEL_INFO(dev)->gen >= 4)
2915                 engine->dispatch_execbuffer = i965_dispatch_execbuffer;
2916         else if (IS_I830(dev) || IS_845G(dev))
2917                 engine->dispatch_execbuffer = i830_dispatch_execbuffer;
2918         else
2919                 engine->dispatch_execbuffer = i915_dispatch_execbuffer;
2920         engine->init_hw = init_render_ring;
2921         engine->cleanup = render_ring_cleanup;
2922
2923         /* Workaround batchbuffer to combat CS tlb bug. */
2924         if (HAS_BROKEN_CS_TLB(dev)) {
2925                 obj = i915_gem_alloc_object(dev, I830_WA_SIZE);
2926                 if (obj == NULL) {
2927                         DRM_ERROR("Failed to allocate batch bo\n");
2928                         return -ENOMEM;
2929                 }
2930
2931                 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
2932                 if (ret != 0) {
2933                         drm_gem_object_unreference(&obj->base);
2934                         DRM_ERROR("Failed to ping batch bo\n");
2935                         return ret;
2936                 }
2937
2938                 engine->scratch.obj = obj;
2939                 engine->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
2940         }
2941
2942         ret = intel_init_ring_buffer(dev, engine);
2943         if (ret)
2944                 return ret;
2945
2946         if (INTEL_INFO(dev)->gen >= 5) {
2947                 ret = intel_init_pipe_control(engine);
2948                 if (ret)
2949                         return ret;
2950         }
2951
2952         return 0;
2953 }
2954
2955 int intel_init_bsd_ring_buffer(struct drm_device *dev)
2956 {
2957         struct drm_i915_private *dev_priv = dev->dev_private;
2958         struct intel_engine_cs *engine = &dev_priv->engine[VCS];
2959
2960         engine->name = "bsd ring";
2961         engine->id = VCS;
2962         engine->exec_id = I915_EXEC_BSD;
2963         engine->hw_id = 1;
2964
2965         engine->write_tail = ring_write_tail;
2966         if (INTEL_INFO(dev)->gen >= 6) {
2967                 engine->mmio_base = GEN6_BSD_RING_BASE;
2968                 /* gen6 bsd needs a special wa for tail updates */
2969                 if (IS_GEN6(dev))
2970                         engine->write_tail = gen6_bsd_ring_write_tail;
2971                 engine->flush = gen6_bsd_ring_flush;
2972                 engine->add_request = gen6_add_request;
2973                 engine->irq_seqno_barrier = gen6_seqno_barrier;
2974                 engine->get_seqno = ring_get_seqno;
2975                 engine->set_seqno = ring_set_seqno;
2976                 if (INTEL_INFO(dev)->gen >= 8) {
2977                         engine->irq_enable_mask =
2978                                 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2979                         engine->irq_get = gen8_ring_get_irq;
2980                         engine->irq_put = gen8_ring_put_irq;
2981                         engine->dispatch_execbuffer =
2982                                 gen8_ring_dispatch_execbuffer;
2983                         if (i915_semaphore_is_enabled(dev)) {
2984                                 engine->semaphore.sync_to = gen8_ring_sync;
2985                                 engine->semaphore.signal = gen8_xcs_signal;
2986                                 GEN8_RING_SEMAPHORE_INIT(engine);
2987                         }
2988                 } else {
2989                         engine->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2990                         engine->irq_get = gen6_ring_get_irq;
2991                         engine->irq_put = gen6_ring_put_irq;
2992                         engine->dispatch_execbuffer =
2993                                 gen6_ring_dispatch_execbuffer;
2994                         if (i915_semaphore_is_enabled(dev)) {
2995                                 engine->semaphore.sync_to = gen6_ring_sync;
2996                                 engine->semaphore.signal = gen6_signal;
2997                                 engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;
2998                                 engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2999                                 engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB;
3000                                 engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE;
3001                                 engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
3002                                 engine->semaphore.mbox.signal[RCS] = GEN6_RVSYNC;
3003                                 engine->semaphore.mbox.signal[VCS] = GEN6_NOSYNC;
3004                                 engine->semaphore.mbox.signal[BCS] = GEN6_BVSYNC;
3005                                 engine->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC;
3006                                 engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
3007                         }
3008                 }
3009         } else {
3010                 engine->mmio_base = BSD_RING_BASE;
3011                 engine->flush = bsd_ring_flush;
3012                 engine->add_request = i9xx_add_request;
3013                 engine->get_seqno = ring_get_seqno;
3014                 engine->set_seqno = ring_set_seqno;
3015                 if (IS_GEN5(dev)) {
3016                         engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
3017                         engine->irq_get = gen5_ring_get_irq;
3018                         engine->irq_put = gen5_ring_put_irq;
3019                 } else {
3020                         engine->irq_enable_mask = I915_BSD_USER_INTERRUPT;
3021                         engine->irq_get = i9xx_ring_get_irq;
3022                         engine->irq_put = i9xx_ring_put_irq;
3023                 }
3024                 engine->dispatch_execbuffer = i965_dispatch_execbuffer;
3025         }
3026         engine->init_hw = init_ring_common;
3027
3028         return intel_init_ring_buffer(dev, engine);
3029 }
3030
3031 /**
3032  * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3)
3033  */
3034 int intel_init_bsd2_ring_buffer(struct drm_device *dev)
3035 {
3036         struct drm_i915_private *dev_priv = dev->dev_private;
3037         struct intel_engine_cs *engine = &dev_priv->engine[VCS2];
3038
3039         engine->name = "bsd2 ring";
3040         engine->id = VCS2;
3041         engine->exec_id = I915_EXEC_BSD;
3042         engine->hw_id = 4;
3043
3044         engine->write_tail = ring_write_tail;
3045         engine->mmio_base = GEN8_BSD2_RING_BASE;
3046         engine->flush = gen6_bsd_ring_flush;
3047         engine->add_request = gen6_add_request;
3048         engine->irq_seqno_barrier = gen6_seqno_barrier;
3049         engine->get_seqno = ring_get_seqno;
3050         engine->set_seqno = ring_set_seqno;
3051         engine->irq_enable_mask =
3052                         GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
3053         engine->irq_get = gen8_ring_get_irq;
3054         engine->irq_put = gen8_ring_put_irq;
3055         engine->dispatch_execbuffer =
3056                         gen8_ring_dispatch_execbuffer;
3057         if (i915_semaphore_is_enabled(dev)) {
3058                 engine->semaphore.sync_to = gen8_ring_sync;
3059                 engine->semaphore.signal = gen8_xcs_signal;
3060                 GEN8_RING_SEMAPHORE_INIT(engine);
3061         }
3062         engine->init_hw = init_ring_common;
3063
3064         return intel_init_ring_buffer(dev, engine);
3065 }
3066
3067 int intel_init_blt_ring_buffer(struct drm_device *dev)
3068 {
3069         struct drm_i915_private *dev_priv = dev->dev_private;
3070         struct intel_engine_cs *engine = &dev_priv->engine[BCS];
3071
3072         engine->name = "blitter ring";
3073         engine->id = BCS;
3074         engine->exec_id = I915_EXEC_BLT;
3075         engine->hw_id = 2;
3076
3077         engine->mmio_base = BLT_RING_BASE;
3078         engine->write_tail = ring_write_tail;
3079         engine->flush = gen6_ring_flush;
3080         engine->add_request = gen6_add_request;
3081         engine->irq_seqno_barrier = gen6_seqno_barrier;
3082         engine->get_seqno = ring_get_seqno;
3083         engine->set_seqno = ring_set_seqno;
3084         if (INTEL_INFO(dev)->gen >= 8) {
3085                 engine->irq_enable_mask =
3086                         GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
3087                 engine->irq_get = gen8_ring_get_irq;
3088                 engine->irq_put = gen8_ring_put_irq;
3089                 engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
3090                 if (i915_semaphore_is_enabled(dev)) {
3091                         engine->semaphore.sync_to = gen8_ring_sync;
3092                         engine->semaphore.signal = gen8_xcs_signal;
3093                         GEN8_RING_SEMAPHORE_INIT(engine);
3094                 }
3095         } else {
3096                 engine->irq_enable_mask = GT_BLT_USER_INTERRUPT;
3097                 engine->irq_get = gen6_ring_get_irq;
3098                 engine->irq_put = gen6_ring_put_irq;
3099                 engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
3100                 if (i915_semaphore_is_enabled(dev)) {
3101                         engine->semaphore.signal = gen6_signal;
3102                         engine->semaphore.sync_to = gen6_ring_sync;
3103                         /*
3104                          * The current semaphore is only applied on pre-gen8
3105                          * platform.  And there is no VCS2 ring on the pre-gen8
3106                          * platform. So the semaphore between BCS and VCS2 is
3107                          * initialized as INVALID.  Gen8 will initialize the
3108                          * sema between BCS and VCS2 later.
3109                          */
3110                         engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR;
3111                         engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV;
3112                         engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID;
3113                         engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE;
3114                         engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
3115                         engine->semaphore.mbox.signal[RCS] = GEN6_RBSYNC;
3116                         engine->semaphore.mbox.signal[VCS] = GEN6_VBSYNC;
3117                         engine->semaphore.mbox.signal[BCS] = GEN6_NOSYNC;
3118                         engine->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC;
3119                         engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
3120                 }
3121         }
3122         engine->init_hw = init_ring_common;
3123
3124         return intel_init_ring_buffer(dev, engine);
3125 }
3126
3127 int intel_init_vebox_ring_buffer(struct drm_device *dev)
3128 {
3129         struct drm_i915_private *dev_priv = dev->dev_private;
3130         struct intel_engine_cs *engine = &dev_priv->engine[VECS];
3131
3132         engine->name = "video enhancement ring";
3133         engine->id = VECS;
3134         engine->exec_id = I915_EXEC_VEBOX;
3135         engine->hw_id = 3;
3136
3137         engine->mmio_base = VEBOX_RING_BASE;
3138         engine->write_tail = ring_write_tail;
3139         engine->flush = gen6_ring_flush;
3140         engine->add_request = gen6_add_request;
3141         engine->irq_seqno_barrier = gen6_seqno_barrier;
3142         engine->get_seqno = ring_get_seqno;
3143         engine->set_seqno = ring_set_seqno;
3144
3145         if (INTEL_INFO(dev)->gen >= 8) {
3146                 engine->irq_enable_mask =
3147                         GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
3148                 engine->irq_get = gen8_ring_get_irq;
3149                 engine->irq_put = gen8_ring_put_irq;
3150                 engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
3151                 if (i915_semaphore_is_enabled(dev)) {
3152                         engine->semaphore.sync_to = gen8_ring_sync;
3153                         engine->semaphore.signal = gen8_xcs_signal;
3154                         GEN8_RING_SEMAPHORE_INIT(engine);
3155                 }
3156         } else {
3157                 engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
3158                 engine->irq_get = hsw_vebox_get_irq;
3159                 engine->irq_put = hsw_vebox_put_irq;
3160                 engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
3161                 if (i915_semaphore_is_enabled(dev)) {
3162                         engine->semaphore.sync_to = gen6_ring_sync;
3163                         engine->semaphore.signal = gen6_signal;
3164                         engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;
3165                         engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV;
3166                         engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB;
3167                         engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID;
3168                         engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
3169                         engine->semaphore.mbox.signal[RCS] = GEN6_RVESYNC;
3170                         engine->semaphore.mbox.signal[VCS] = GEN6_VVESYNC;
3171                         engine->semaphore.mbox.signal[BCS] = GEN6_BVESYNC;
3172                         engine->semaphore.mbox.signal[VECS] = GEN6_NOSYNC;
3173                         engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
3174                 }
3175         }
3176         engine->init_hw = init_ring_common;
3177
3178         return intel_init_ring_buffer(dev, engine);
3179 }
3180
3181 int
3182 intel_ring_flush_all_caches(struct drm_i915_gem_request *req)
3183 {
3184         struct intel_engine_cs *engine = req->engine;
3185         int ret;
3186
3187         if (!engine->gpu_caches_dirty)
3188                 return 0;
3189
3190         ret = engine->flush(req, 0, I915_GEM_GPU_DOMAINS);
3191         if (ret)
3192                 return ret;
3193
3194         trace_i915_gem_ring_flush(req, 0, I915_GEM_GPU_DOMAINS);
3195
3196         engine->gpu_caches_dirty = false;
3197         return 0;
3198 }
3199
3200 int
3201 intel_ring_invalidate_all_caches(struct drm_i915_gem_request *req)
3202 {
3203         struct intel_engine_cs *engine = req->engine;
3204         uint32_t flush_domains;
3205         int ret;
3206
3207         flush_domains = 0;
3208         if (engine->gpu_caches_dirty)
3209                 flush_domains = I915_GEM_GPU_DOMAINS;
3210
3211         ret = engine->flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
3212         if (ret)
3213                 return ret;
3214
3215         trace_i915_gem_ring_flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
3216
3217         engine->gpu_caches_dirty = false;
3218         return 0;
3219 }
3220
3221 void
3222 intel_stop_engine(struct intel_engine_cs *engine)
3223 {
3224         int ret;
3225
3226         if (!intel_engine_initialized(engine))
3227                 return;
3228
3229         ret = intel_engine_idle(engine);
3230         if (ret)
3231                 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
3232                           engine->name, ret);
3233
3234         stop_ring(engine);
3235 }