drivers/gpu/drm/i915/intel_runtime_pm.c

   1 /*
   2  * Copyright © 2012-2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *    Daniel Vetter <daniel.vetter@ffwll.ch>
  26  *
  27  */
  28
  29 #include <linux/pm_runtime.h>
  30 #include <linux/vgaarb.h>
  31
  32 #include "i915_drv.h"
  33 #include "intel_drv.h"
  34
  35 /**
  36  * DOC: runtime pm
  37  *
  38  * The i915 driver supports dynamic enabling and disabling of entire hardware
  39  * blocks at runtime. This is especially important on the display side where
  40  * software is supposed to control many power gates manually on recent hardware,
  41  * since on the GT side a lot of the power management is done by the hardware.
  42  * But even there some manual control at the device level is required.
  43  *
  44  * Since i915 supports a diverse set of platforms with a unified codebase and
  45  * hardware engineers just love to shuffle functionality around between power
  46  * domains there's a sizeable amount of indirection required. This file provides
  47  * generic functions to the driver for grabbing and releasing references for
  48  * abstract power domains. It then maps those to the actual power wells
  49  * present for a given platform.
  50  */
  51
  52 #define for_each_power_well(i, power_well, domain_mask, power_domains)  \
  53         for (i = 0;                                                     \
  54              i < (power_domains)->power_well_count &&                   \
  55                  ((power_well) = &(power_domains)->power_wells[i]);     \
  56              i++)                                                       \
  57                 for_each_if ((power_well)->domains & (domain_mask))
  58
  59 #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
  60         for (i = (power_domains)->power_well_count - 1;                  \
  61              i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
  62              i--)                                                        \
  63                 for_each_if ((power_well)->domains & (domain_mask))
  64
  65 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
  66                                     int power_well_id);
  67
  68 static struct i915_power_well *
  69 lookup_power_well(struct drm_i915_private *dev_priv, int power_well_id);
  70
  71 const char *
  72 intel_display_power_domain_str(enum intel_display_power_domain domain)
  73 {
  74         switch (domain) {
  75         case POWER_DOMAIN_PIPE_A:
  76                 return "PIPE_A";
  77         case POWER_DOMAIN_PIPE_B:
  78                 return "PIPE_B";
  79         case POWER_DOMAIN_PIPE_C:
  80                 return "PIPE_C";
  81         case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
  82                 return "PIPE_A_PANEL_FITTER";
  83         case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
  84                 return "PIPE_B_PANEL_FITTER";
  85         case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
  86                 return "PIPE_C_PANEL_FITTER";
  87         case POWER_DOMAIN_TRANSCODER_A:
  88                 return "TRANSCODER_A";
  89         case POWER_DOMAIN_TRANSCODER_B:
  90                 return "TRANSCODER_B";
  91         case POWER_DOMAIN_TRANSCODER_C:
  92                 return "TRANSCODER_C";
  93         case POWER_DOMAIN_TRANSCODER_EDP:
  94                 return "TRANSCODER_EDP";
  95         case POWER_DOMAIN_TRANSCODER_DSI_A:
  96                 return "TRANSCODER_DSI_A";
  97         case POWER_DOMAIN_TRANSCODER_DSI_C:
  98                 return "TRANSCODER_DSI_C";
  99         case POWER_DOMAIN_PORT_DDI_A_LANES:
 100                 return "PORT_DDI_A_LANES";
 101         case POWER_DOMAIN_PORT_DDI_B_LANES:
 102                 return "PORT_DDI_B_LANES";
 103         case POWER_DOMAIN_PORT_DDI_C_LANES:
 104                 return "PORT_DDI_C_LANES";
 105         case POWER_DOMAIN_PORT_DDI_D_LANES:
 106                 return "PORT_DDI_D_LANES";
 107         case POWER_DOMAIN_PORT_DDI_E_LANES:
 108                 return "PORT_DDI_E_LANES";
 109         case POWER_DOMAIN_PORT_DSI:
 110                 return "PORT_DSI";
 111         case POWER_DOMAIN_PORT_CRT:
 112                 return "PORT_CRT";
 113         case POWER_DOMAIN_PORT_OTHER:
 114                 return "PORT_OTHER";
 115         case POWER_DOMAIN_VGA:
 116                 return "VGA";
 117         case POWER_DOMAIN_AUDIO:
 118                 return "AUDIO";
 119         case POWER_DOMAIN_PLLS:
 120                 return "PLLS";
 121         case POWER_DOMAIN_AUX_A:
 122                 return "AUX_A";
 123         case POWER_DOMAIN_AUX_B:
 124                 return "AUX_B";
 125         case POWER_DOMAIN_AUX_C:
 126                 return "AUX_C";
 127         case POWER_DOMAIN_AUX_D:
 128                 return "AUX_D";
 129         case POWER_DOMAIN_GMBUS:
 130                 return "GMBUS";
 131         case POWER_DOMAIN_INIT:
 132                 return "INIT";
 133         case POWER_DOMAIN_MODESET:
 134                 return "MODESET";
 135         default:
 136                 MISSING_CASE(domain);
 137                 return "?";
 138         }
 139 }
 140
 141 static void intel_power_well_enable(struct drm_i915_private *dev_priv,
 142                                     struct i915_power_well *power_well)
 143 {
 144         DRM_DEBUG_KMS("enabling %s\n", power_well->name);
 145         power_well->ops->enable(dev_priv, power_well);
 146         power_well->hw_enabled = true;
 147 }
 148
 149 static void intel_power_well_disable(struct drm_i915_private *dev_priv,
 150                                      struct i915_power_well *power_well)
 151 {
 152         DRM_DEBUG_KMS("disabling %s\n", power_well->name);
 153         power_well->hw_enabled = false;
 154         power_well->ops->disable(dev_priv, power_well);
 155 }
 156
 157 static void intel_power_well_get(struct drm_i915_private *dev_priv,
 158                                  struct i915_power_well *power_well)
 159 {
 160         if (!power_well->count++)
 161                 intel_power_well_enable(dev_priv, power_well);
 162 }
 163
 164 static void intel_power_well_put(struct drm_i915_private *dev_priv,
 165                                  struct i915_power_well *power_well)
 166 {
 167         WARN(!power_well->count, "Use count on power well %s is already zero",
 168              power_well->name);
 169
 170         if (!--power_well->count)
 171                 intel_power_well_disable(dev_priv, power_well);
 172 }
 173
 174 /*
 175  * We should only use the power well if we explicitly asked the hardware to
 176  * enable it, so check if it's enabled and also check if we've requested it to
 177  * be enabled.
 178  */
 179 static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
 180                                    struct i915_power_well *power_well)
 181 {
 182         return I915_READ(HSW_PWR_WELL_DRIVER) ==
 183                      (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
 184 }
 185
 186 /**
 187  * __intel_display_power_is_enabled - unlocked check for a power domain
 188  * @dev_priv: i915 device instance
 189  * @domain: power domain to check
 190  *
 191  * This is the unlocked version of intel_display_power_is_enabled() and should
 192  * only be used from error capture and recovery code where deadlocks are
 193  * possible.
 194  *
 195  * Returns:
 196  * True when the power domain is enabled, false otherwise.
 197  */
 198 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
 199                                       enum intel_display_power_domain domain)
 200 {
 201         struct i915_power_domains *power_domains;
 202         struct i915_power_well *power_well;
 203         bool is_enabled;
 204         int i;
 205
 206         if (dev_priv->pm.suspended)
 207                 return false;
 208
 209         power_domains = &dev_priv->power_domains;
 210
 211         is_enabled = true;
 212
 213         for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
 214                 if (power_well->always_on)
 215                         continue;
 216
 217                 if (!power_well->hw_enabled) {
 218                         is_enabled = false;
 219                         break;
 220                 }
 221         }
 222
 223         return is_enabled;
 224 }
 225
 226 /**
 227  * intel_display_power_is_enabled - check for a power domain
 228  * @dev_priv: i915 device instance
 229  * @domain: power domain to check
 230  *
 231  * This function can be used to check the hw power domain state. It is mostly
 232  * used in hardware state readout functions. Everywhere else code should rely
 233  * upon explicit power domain reference counting to ensure that the hardware
 234  * block is powered up before accessing it.
 235  *
 236  * Callers must hold the relevant modesetting locks to ensure that concurrent
 237  * threads can't disable the power well while the caller tries to read a few
 238  * registers.
 239  *
 240  * Returns:
 241  * True when the power domain is enabled, false otherwise.
 242  */
 243 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
 244                                     enum intel_display_power_domain domain)
 245 {
 246         struct i915_power_domains *power_domains;
 247         bool ret;
 248
 249         power_domains = &dev_priv->power_domains;
 250
 251         mutex_lock(&power_domains->lock);
 252         ret = __intel_display_power_is_enabled(dev_priv, domain);
 253         mutex_unlock(&power_domains->lock);
 254
 255         return ret;
 256 }
 257
 258 /**
 259  * intel_display_set_init_power - set the initial power domain state
 260  * @dev_priv: i915 device instance
 261  * @enable: whether to enable or disable the initial power domain state
 262  *
 263  * For simplicity our driver load/unload and system suspend/resume code assumes
 264  * that all power domains are always enabled. This functions controls the state
 265  * of this little hack. While the initial power domain state is enabled runtime
 266  * pm is effectively disabled.
 267  */
 268 void intel_display_set_init_power(struct drm_i915_private *dev_priv,
 269                                   bool enable)
 270 {
 271         if (dev_priv->power_domains.init_power_on == enable)
 272                 return;
 273
 274         if (enable)
 275                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
 276         else
 277                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
 278
 279         dev_priv->power_domains.init_power_on = enable;
 280 }
 281
 282 /*
 283  * Starting with Haswell, we have a "Power Down Well" that can be turned off
 284  * when not needed anymore. We have 4 registers that can request the power well
 285  * to be enabled, and it will only be disabled if none of the registers is
 286  * requesting it to be enabled.
 287  */
 288 static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
 289 {
 290         struct drm_device *dev = &dev_priv->drm;
 291
 292         /*
 293          * After we re-enable the power well, if we touch VGA register 0x3d5
 294          * we'll get unclaimed register interrupts. This stops after we write
 295          * anything to the VGA MSR register. The vgacon module uses this
 296          * register all the time, so if we unbind our driver and, as a
 297          * consequence, bind vgacon, we'll get stuck in an infinite loop at
 298          * console_unlock(). So make here we touch the VGA MSR register, making
 299          * sure vgacon can keep working normally without triggering interrupts
 300          * and error messages.
 301          */
 302         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
 303         outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
 304         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
 305
 306         if (IS_BROADWELL(dev))
 307                 gen8_irq_power_well_post_enable(dev_priv,
 308                                                 1 << PIPE_C | 1 << PIPE_B);
 309 }
 310
 311 static void hsw_power_well_pre_disable(struct drm_i915_private *dev_priv)
 312 {
 313         if (IS_BROADWELL(dev_priv))
 314                 gen8_irq_power_well_pre_disable(dev_priv,
 315                                                 1 << PIPE_C | 1 << PIPE_B);
 316 }
 317
 318 static void skl_power_well_post_enable(struct drm_i915_private *dev_priv,
 319                                        struct i915_power_well *power_well)
 320 {
 321         struct drm_device *dev = &dev_priv->drm;
 322
 323         /*
 324          * After we re-enable the power well, if we touch VGA register 0x3d5
 325          * we'll get unclaimed register interrupts. This stops after we write
 326          * anything to the VGA MSR register. The vgacon module uses this
 327          * register all the time, so if we unbind our driver and, as a
 328          * consequence, bind vgacon, we'll get stuck in an infinite loop at
 329          * console_unlock(). So make here we touch the VGA MSR register, making
 330          * sure vgacon can keep working normally without triggering interrupts
 331          * and error messages.
 332          */
 333         if (power_well->data == SKL_DISP_PW_2) {
 334                 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
 335                 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
 336                 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
 337
 338                 gen8_irq_power_well_post_enable(dev_priv,
 339                                                 1 << PIPE_C | 1 << PIPE_B);
 340         }
 341 }
 342
 343 static void skl_power_well_pre_disable(struct drm_i915_private *dev_priv,
 344                                        struct i915_power_well *power_well)
 345 {
 346         if (power_well->data == SKL_DISP_PW_2)
 347                 gen8_irq_power_well_pre_disable(dev_priv,
 348                                                 1 << PIPE_C | 1 << PIPE_B);
 349 }
 350
 351 static void hsw_set_power_well(struct drm_i915_private *dev_priv,
 352                                struct i915_power_well *power_well, bool enable)
 353 {
 354         bool is_enabled, enable_requested;
 355         uint32_t tmp;
 356
 357         tmp = I915_READ(HSW_PWR_WELL_DRIVER);
 358         is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
 359         enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
 360
 361         if (enable) {
 362                 if (!enable_requested)
 363                         I915_WRITE(HSW_PWR_WELL_DRIVER,
 364                                    HSW_PWR_WELL_ENABLE_REQUEST);
 365
 366                 if (!is_enabled) {
 367                         DRM_DEBUG_KMS("Enabling power well\n");
 368                         if (intel_wait_for_register(dev_priv,
 369                                                     HSW_PWR_WELL_DRIVER,
 370                                                     HSW_PWR_WELL_STATE_ENABLED,
 371                                                     HSW_PWR_WELL_STATE_ENABLED,
 372                                                     20))
 373                                 DRM_ERROR("Timeout enabling power well\n");
 374                         hsw_power_well_post_enable(dev_priv);
 375                 }
 376
 377         } else {
 378                 if (enable_requested) {
 379                         hsw_power_well_pre_disable(dev_priv);
 380                         I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
 381                         POSTING_READ(HSW_PWR_WELL_DRIVER);
 382                         DRM_DEBUG_KMS("Requesting to disable the power well\n");
 383                 }
 384         }
 385 }
 386
 387 #define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS (         \
 388         BIT(POWER_DOMAIN_TRANSCODER_A) |                \
 389         BIT(POWER_DOMAIN_PIPE_B) |                      \
 390         BIT(POWER_DOMAIN_TRANSCODER_B) |                \
 391         BIT(POWER_DOMAIN_PIPE_C) |                      \
 392         BIT(POWER_DOMAIN_TRANSCODER_C) |                \
 393         BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |         \
 394         BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |         \
 395         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |            \
 396         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |            \
 397         BIT(POWER_DOMAIN_PORT_DDI_D_LANES) |            \
 398         BIT(POWER_DOMAIN_PORT_DDI_E_LANES) |            \
 399         BIT(POWER_DOMAIN_AUX_B) |                       \
 400         BIT(POWER_DOMAIN_AUX_C) |                       \
 401         BIT(POWER_DOMAIN_AUX_D) |                       \
 402         BIT(POWER_DOMAIN_AUDIO) |                       \
 403         BIT(POWER_DOMAIN_VGA) |                         \
 404         BIT(POWER_DOMAIN_INIT))
 405 #define SKL_DISPLAY_DDI_A_E_POWER_DOMAINS (             \
 406         BIT(POWER_DOMAIN_PORT_DDI_A_LANES) |            \
 407         BIT(POWER_DOMAIN_PORT_DDI_E_LANES) |            \
 408         BIT(POWER_DOMAIN_INIT))
 409 #define SKL_DISPLAY_DDI_B_POWER_DOMAINS (               \
 410         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |            \
 411         BIT(POWER_DOMAIN_INIT))
 412 #define SKL_DISPLAY_DDI_C_POWER_DOMAINS (               \
 413         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |            \
 414         BIT(POWER_DOMAIN_INIT))
 415 #define SKL_DISPLAY_DDI_D_POWER_DOMAINS (               \
 416         BIT(POWER_DOMAIN_PORT_DDI_D_LANES) |            \
 417         BIT(POWER_DOMAIN_INIT))
 418 #define SKL_DISPLAY_DC_OFF_POWER_DOMAINS (              \
 419         SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS |         \
 420         BIT(POWER_DOMAIN_MODESET) |                     \
 421         BIT(POWER_DOMAIN_AUX_A) |                       \
 422         BIT(POWER_DOMAIN_INIT))
 423
 424 #define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS (         \
 425         BIT(POWER_DOMAIN_TRANSCODER_A) |                \
 426         BIT(POWER_DOMAIN_PIPE_B) |                      \
 427         BIT(POWER_DOMAIN_TRANSCODER_B) |                \
 428         BIT(POWER_DOMAIN_PIPE_C) |                      \
 429         BIT(POWER_DOMAIN_TRANSCODER_C) |                \
 430         BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |         \
 431         BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |         \
 432         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |            \
 433         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |            \
 434         BIT(POWER_DOMAIN_AUX_B) |                       \
 435         BIT(POWER_DOMAIN_AUX_C) |                       \
 436         BIT(POWER_DOMAIN_AUDIO) |                       \
 437         BIT(POWER_DOMAIN_VGA) |                         \
 438         BIT(POWER_DOMAIN_GMBUS) |                       \
 439         BIT(POWER_DOMAIN_INIT))
 440 #define BXT_DISPLAY_DC_OFF_POWER_DOMAINS (              \
 441         BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS |         \
 442         BIT(POWER_DOMAIN_MODESET) |                     \
 443         BIT(POWER_DOMAIN_AUX_A) |                       \
 444         BIT(POWER_DOMAIN_INIT))
 445 #define BXT_DPIO_CMN_A_POWER_DOMAINS (                  \
 446         BIT(POWER_DOMAIN_PORT_DDI_A_LANES) |            \
 447         BIT(POWER_DOMAIN_AUX_A) |                       \
 448         BIT(POWER_DOMAIN_INIT))
 449 #define BXT_DPIO_CMN_BC_POWER_DOMAINS (                 \
 450         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |            \
 451         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |            \
 452         BIT(POWER_DOMAIN_AUX_B) |                       \
 453         BIT(POWER_DOMAIN_AUX_C) |                       \
 454         BIT(POWER_DOMAIN_INIT))
 455
 456 static void assert_can_enable_dc9(struct drm_i915_private *dev_priv)
 457 {
 458         WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9),
 459                   "DC9 already programmed to be enabled.\n");
 460         WARN_ONCE(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
 461                   "DC5 still not disabled to enable DC9.\n");
 462         WARN_ONCE(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on.\n");
 463         WARN_ONCE(intel_irqs_enabled(dev_priv),
 464                   "Interrupts not disabled yet.\n");
 465
 466          /*
 467           * TODO: check for the following to verify the conditions to enter DC9
 468           * state are satisfied:
 469           * 1] Check relevant display engine registers to verify if mode set
 470           * disable sequence was followed.
 471           * 2] Check if display uninitialize sequence is initialized.
 472           */
 473 }
 474
 475 static void assert_can_disable_dc9(struct drm_i915_private *dev_priv)
 476 {
 477         WARN_ONCE(intel_irqs_enabled(dev_priv),
 478                   "Interrupts not disabled yet.\n");
 479         WARN_ONCE(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
 480                   "DC5 still not disabled.\n");
 481
 482          /*
 483           * TODO: check for the following to verify DC9 state was indeed
 484           * entered before programming to disable it:
 485           * 1] Check relevant display engine registers to verify if mode
 486           *  set disable sequence was followed.
 487           * 2] Check if display uninitialize sequence is initialized.
 488           */
 489 }
 490
 491 static void gen9_write_dc_state(struct drm_i915_private *dev_priv,
 492                                 u32 state)
 493 {
 494         int rewrites = 0;
 495         int rereads = 0;
 496         u32 v;
 497
 498         I915_WRITE(DC_STATE_EN, state);
 499
 500         /* It has been observed that disabling the dc6 state sometimes
 501          * doesn't stick and dmc keeps returning old value. Make sure
 502          * the write really sticks enough times and also force rewrite until
 503          * we are confident that state is exactly what we want.
 504          */
 505         do  {
 506                 v = I915_READ(DC_STATE_EN);
 507
 508                 if (v != state) {
 509                         I915_WRITE(DC_STATE_EN, state);
 510                         rewrites++;
 511                         rereads = 0;
 512                 } else if (rereads++ > 5) {
 513                         break;
 514                 }
 515
 516         } while (rewrites < 100);
 517
 518         if (v != state)
 519                 DRM_ERROR("Writing dc state to 0x%x failed, now 0x%x\n",
 520                           state, v);
 521
 522         /* Most of the times we need one retry, avoid spam */
 523         if (rewrites > 1)
 524                 DRM_DEBUG_KMS("Rewrote dc state to 0x%x %d times\n",
 525                               state, rewrites);
 526 }
 527
 528 static u32 gen9_dc_mask(struct drm_i915_private *dev_priv)
 529 {
 530         u32 mask;
 531
 532         mask = DC_STATE_EN_UPTO_DC5;
 533         if (IS_BROXTON(dev_priv))
 534                 mask |= DC_STATE_EN_DC9;
 535         else
 536                 mask |= DC_STATE_EN_UPTO_DC6;
 537
 538         return mask;
 539 }
 540
 541 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv)
 542 {
 543         u32 val;
 544
 545         val = I915_READ(DC_STATE_EN) & gen9_dc_mask(dev_priv);
 546
 547         DRM_DEBUG_KMS("Resetting DC state tracking from %02x to %02x\n",
 548                       dev_priv->csr.dc_state, val);
 549         dev_priv->csr.dc_state = val;
 550 }
 551
 552 static void gen9_set_dc_state(struct drm_i915_private *dev_priv, uint32_t state)
 553 {
 554         uint32_t val;
 555         uint32_t mask;
 556
 557         if (WARN_ON_ONCE(state & ~dev_priv->csr.allowed_dc_mask))
 558                 state &= dev_priv->csr.allowed_dc_mask;
 559
 560         val = I915_READ(DC_STATE_EN);
 561         mask = gen9_dc_mask(dev_priv);
 562         DRM_DEBUG_KMS("Setting DC state from %02x to %02x\n",
 563                       val & mask, state);
 564
 565         /* Check if DMC is ignoring our DC state requests */
 566         if ((val & mask) != dev_priv->csr.dc_state)
 567                 DRM_ERROR("DC state mismatch (0x%x -> 0x%x)\n",
 568                           dev_priv->csr.dc_state, val & mask);
 569
 570         val &= ~mask;
 571         val |= state;
 572
 573         gen9_write_dc_state(dev_priv, val);
 574
 575         dev_priv->csr.dc_state = val & mask;
 576 }
 577
 578 void bxt_enable_dc9(struct drm_i915_private *dev_priv)
 579 {
 580         assert_can_enable_dc9(dev_priv);
 581
 582         DRM_DEBUG_KMS("Enabling DC9\n");
 583
 584         intel_power_sequencer_reset(dev_priv);
 585         gen9_set_dc_state(dev_priv, DC_STATE_EN_DC9);
 586 }
 587
 588 void bxt_disable_dc9(struct drm_i915_private *dev_priv)
 589 {
 590         assert_can_disable_dc9(dev_priv);
 591
 592         DRM_DEBUG_KMS("Disabling DC9\n");
 593
 594         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 595 }
 596
 597 static void assert_csr_loaded(struct drm_i915_private *dev_priv)
 598 {
 599         WARN_ONCE(!I915_READ(CSR_PROGRAM(0)),
 600                   "CSR program storage start is NULL\n");
 601         WARN_ONCE(!I915_READ(CSR_SSP_BASE), "CSR SSP Base Not fine\n");
 602         WARN_ONCE(!I915_READ(CSR_HTP_SKL), "CSR HTP Not fine\n");
 603 }
 604
 605 static void assert_can_enable_dc5(struct drm_i915_private *dev_priv)
 606 {
 607         bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv,
 608                                         SKL_DISP_PW_2);
 609
 610         WARN_ONCE(pg2_enabled, "PG2 not disabled to enable DC5.\n");
 611
 612         WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5),
 613                   "DC5 already programmed to be enabled.\n");
 614         assert_rpm_wakelock_held(dev_priv);
 615
 616         assert_csr_loaded(dev_priv);
 617 }
 618
 619 void gen9_enable_dc5(struct drm_i915_private *dev_priv)
 620 {
 621         assert_can_enable_dc5(dev_priv);
 622
 623         DRM_DEBUG_KMS("Enabling DC5\n");
 624
 625         gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5);
 626 }
 627
 628 static void assert_can_enable_dc6(struct drm_i915_private *dev_priv)
 629 {
 630         WARN_ONCE(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
 631                   "Backlight is not disabled.\n");
 632         WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6),
 633                   "DC6 already programmed to be enabled.\n");
 634
 635         assert_csr_loaded(dev_priv);
 636 }
 637
 638 void skl_enable_dc6(struct drm_i915_private *dev_priv)
 639 {
 640         assert_can_enable_dc6(dev_priv);
 641
 642         DRM_DEBUG_KMS("Enabling DC6\n");
 643
 644         gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
 645
 646 }
 647
 648 void skl_disable_dc6(struct drm_i915_private *dev_priv)
 649 {
 650         DRM_DEBUG_KMS("Disabling DC6\n");
 651
 652         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 653 }
 654
 655 static void
 656 gen9_sanitize_power_well_requests(struct drm_i915_private *dev_priv,
 657                                   struct i915_power_well *power_well)
 658 {
 659         enum skl_disp_power_wells power_well_id = power_well->data;
 660         u32 val;
 661         u32 mask;
 662
 663         mask = SKL_POWER_WELL_REQ(power_well_id);
 664
 665         val = I915_READ(HSW_PWR_WELL_KVMR);
 666         if (WARN_ONCE(val & mask, "Clearing unexpected KVMR request for %s\n",
 667                       power_well->name))
 668                 I915_WRITE(HSW_PWR_WELL_KVMR, val & ~mask);
 669
 670         val = I915_READ(HSW_PWR_WELL_BIOS);
 671         val |= I915_READ(HSW_PWR_WELL_DEBUG);
 672
 673         if (!(val & mask))
 674                 return;
 675
 676         /*
 677          * DMC is known to force on the request bits for power well 1 on SKL
 678          * and BXT and the misc IO power well on SKL but we don't expect any
 679          * other request bits to be set, so WARN for those.
 680          */
 681         if (power_well_id == SKL_DISP_PW_1 ||
 682             ((IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) &&
 683              power_well_id == SKL_DISP_PW_MISC_IO))
 684                 DRM_DEBUG_DRIVER("Clearing auxiliary requests for %s forced on "
 685                                  "by DMC\n", power_well->name);
 686         else
 687                 WARN_ONCE(1, "Clearing unexpected auxiliary requests for %s\n",
 688                           power_well->name);
 689
 690         I915_WRITE(HSW_PWR_WELL_BIOS, val & ~mask);
 691         I915_WRITE(HSW_PWR_WELL_DEBUG, val & ~mask);
 692 }
 693
 694 static void skl_set_power_well(struct drm_i915_private *dev_priv,
 695                         struct i915_power_well *power_well, bool enable)
 696 {
 697         uint32_t tmp, fuse_status;
 698         uint32_t req_mask, state_mask;
 699         bool is_enabled, enable_requested, check_fuse_status = false;
 700
 701         tmp = I915_READ(HSW_PWR_WELL_DRIVER);
 702         fuse_status = I915_READ(SKL_FUSE_STATUS);
 703
 704         switch (power_well->data) {
 705         case SKL_DISP_PW_1:
 706                 if (intel_wait_for_register(dev_priv,
 707                                             SKL_FUSE_STATUS,
 708                                             SKL_FUSE_PG0_DIST_STATUS,
 709                                             SKL_FUSE_PG0_DIST_STATUS,
 710                                             1)) {
 711                         DRM_ERROR("PG0 not enabled\n");
 712                         return;
 713                 }
 714                 break;
 715         case SKL_DISP_PW_2:
 716                 if (!(fuse_status & SKL_FUSE_PG1_DIST_STATUS)) {
 717                         DRM_ERROR("PG1 in disabled state\n");
 718                         return;
 719                 }
 720                 break;
 721         case SKL_DISP_PW_DDI_A_E:
 722         case SKL_DISP_PW_DDI_B:
 723         case SKL_DISP_PW_DDI_C:
 724         case SKL_DISP_PW_DDI_D:
 725         case SKL_DISP_PW_MISC_IO:
 726                 break;
 727         default:
 728                 WARN(1, "Unknown power well %lu\n", power_well->data);
 729                 return;
 730         }
 731
 732         req_mask = SKL_POWER_WELL_REQ(power_well->data);
 733         enable_requested = tmp & req_mask;
 734         state_mask = SKL_POWER_WELL_STATE(power_well->data);
 735         is_enabled = tmp & state_mask;
 736
 737         if (!enable && enable_requested)
 738                 skl_power_well_pre_disable(dev_priv, power_well);
 739
 740         if (enable) {
 741                 if (!enable_requested) {
 742                         WARN((tmp & state_mask) &&
 743                                 !I915_READ(HSW_PWR_WELL_BIOS),
 744                                 "Invalid for power well status to be enabled, unless done by the BIOS, \
 745                                 when request is to disable!\n");
 746                         I915_WRITE(HSW_PWR_WELL_DRIVER, tmp | req_mask);
 747                 }
 748
 749                 if (!is_enabled) {
 750                         DRM_DEBUG_KMS("Enabling %s\n", power_well->name);
 751                         check_fuse_status = true;
 752                 }
 753         } else {
 754                 if (enable_requested) {
 755                         I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask);
 756                         POSTING_READ(HSW_PWR_WELL_DRIVER);
 757                         DRM_DEBUG_KMS("Disabling %s\n", power_well->name);
 758                 }
 759
 760                 if (IS_GEN9(dev_priv))
 761                         gen9_sanitize_power_well_requests(dev_priv, power_well);
 762         }
 763
 764         if (wait_for(!!(I915_READ(HSW_PWR_WELL_DRIVER) & state_mask) == enable,
 765                      1))
 766                 DRM_ERROR("%s %s timeout\n",
 767                           power_well->name, enable ? "enable" : "disable");
 768
 769         if (check_fuse_status) {
 770                 if (power_well->data == SKL_DISP_PW_1) {
 771                         if (intel_wait_for_register(dev_priv,
 772                                                     SKL_FUSE_STATUS,
 773                                                     SKL_FUSE_PG1_DIST_STATUS,
 774                                                     SKL_FUSE_PG1_DIST_STATUS,
 775                                                     1))
 776                                 DRM_ERROR("PG1 distributing status timeout\n");
 777                 } else if (power_well->data == SKL_DISP_PW_2) {
 778                         if (intel_wait_for_register(dev_priv,
 779                                                     SKL_FUSE_STATUS,
 780                                                     SKL_FUSE_PG2_DIST_STATUS,
 781                                                     SKL_FUSE_PG2_DIST_STATUS,
 782                                                     1))
 783                                 DRM_ERROR("PG2 distributing status timeout\n");
 784                 }
 785         }
 786
 787         if (enable && !is_enabled)
 788                 skl_power_well_post_enable(dev_priv, power_well);
 789 }
 790
 791 static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
 792                                    struct i915_power_well *power_well)
 793 {
 794         hsw_set_power_well(dev_priv, power_well, power_well->count > 0);
 795
 796         /*
 797          * We're taking over the BIOS, so clear any requests made by it since
 798          * the driver is in charge now.
 799          */
 800         if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
 801                 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
 802 }
 803
 804 static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
 805                                   struct i915_power_well *power_well)
 806 {
 807         hsw_set_power_well(dev_priv, power_well, true);
 808 }
 809
 810 static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
 811                                    struct i915_power_well *power_well)
 812 {
 813         hsw_set_power_well(dev_priv, power_well, false);
 814 }
 815
 816 static bool skl_power_well_enabled(struct drm_i915_private *dev_priv,
 817                                         struct i915_power_well *power_well)
 818 {
 819         uint32_t mask = SKL_POWER_WELL_REQ(power_well->data) |
 820                 SKL_POWER_WELL_STATE(power_well->data);
 821
 822         return (I915_READ(HSW_PWR_WELL_DRIVER) & mask) == mask;
 823 }
 824
 825 static void skl_power_well_sync_hw(struct drm_i915_private *dev_priv,
 826                                 struct i915_power_well *power_well)
 827 {
 828         skl_set_power_well(dev_priv, power_well, power_well->count > 0);
 829
 830         /* Clear any request made by BIOS as driver is taking over */
 831         I915_WRITE(HSW_PWR_WELL_BIOS, 0);
 832 }
 833
 834 static void skl_power_well_enable(struct drm_i915_private *dev_priv,
 835                                 struct i915_power_well *power_well)
 836 {
 837         skl_set_power_well(dev_priv, power_well, true);
 838 }
 839
 840 static void skl_power_well_disable(struct drm_i915_private *dev_priv,
 841                                 struct i915_power_well *power_well)
 842 {
 843         skl_set_power_well(dev_priv, power_well, false);
 844 }
 845
 846 static enum dpio_phy bxt_power_well_to_phy(struct i915_power_well *power_well)
 847 {
 848         enum skl_disp_power_wells power_well_id = power_well->data;
 849
 850         return power_well_id == BXT_DPIO_CMN_A ? DPIO_PHY1 : DPIO_PHY0;
 851 }
 852
 853 static void bxt_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
 854                                            struct i915_power_well *power_well)
 855 {
 856         enum skl_disp_power_wells power_well_id = power_well->data;
 857         struct i915_power_well *cmn_a_well;
 858
 859         if (power_well_id == BXT_DPIO_CMN_BC) {
 860                 /*
 861                  * We need to copy the GRC calibration value from the eDP PHY,
 862                  * so make sure it's powered up.
 863                  */
 864                 cmn_a_well = lookup_power_well(dev_priv, BXT_DPIO_CMN_A);
 865                 intel_power_well_get(dev_priv, cmn_a_well);
 866         }
 867
 868         bxt_ddi_phy_init(dev_priv, bxt_power_well_to_phy(power_well));
 869
 870         if (power_well_id == BXT_DPIO_CMN_BC)
 871                 intel_power_well_put(dev_priv, cmn_a_well);
 872 }
 873
 874 static void bxt_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
 875                                             struct i915_power_well *power_well)
 876 {
 877         bxt_ddi_phy_uninit(dev_priv, bxt_power_well_to_phy(power_well));
 878 }
 879
 880 static bool bxt_dpio_cmn_power_well_enabled(struct drm_i915_private *dev_priv,
 881                                             struct i915_power_well *power_well)
 882 {
 883         return bxt_ddi_phy_is_enabled(dev_priv,
 884                                       bxt_power_well_to_phy(power_well));
 885 }
 886
 887 static void bxt_dpio_cmn_power_well_sync_hw(struct drm_i915_private *dev_priv,
 888                                             struct i915_power_well *power_well)
 889 {
 890         if (power_well->count > 0)
 891                 bxt_dpio_cmn_power_well_enable(dev_priv, power_well);
 892         else
 893                 bxt_dpio_cmn_power_well_disable(dev_priv, power_well);
 894 }
 895
 896
 897 static void bxt_verify_ddi_phy_power_wells(struct drm_i915_private *dev_priv)
 898 {
 899         struct i915_power_well *power_well;
 900
 901         power_well = lookup_power_well(dev_priv, BXT_DPIO_CMN_A);
 902         if (power_well->count > 0)
 903                 bxt_ddi_phy_verify_state(dev_priv,
 904                                          bxt_power_well_to_phy(power_well));
 905
 906         power_well = lookup_power_well(dev_priv, BXT_DPIO_CMN_BC);
 907         if (power_well->count > 0)
 908                 bxt_ddi_phy_verify_state(dev_priv,
 909                                          bxt_power_well_to_phy(power_well));
 910 }
 911
 912 static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv,
 913                                            struct i915_power_well *power_well)
 914 {
 915         return (I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0;
 916 }
 917
 918 static void gen9_assert_dbuf_enabled(struct drm_i915_private *dev_priv)
 919 {
 920         u32 tmp = I915_READ(DBUF_CTL);
 921
 922         WARN((tmp & (DBUF_POWER_STATE | DBUF_POWER_REQUEST)) !=
 923              (DBUF_POWER_STATE | DBUF_POWER_REQUEST),
 924              "Unexpected DBuf power power state (0x%08x)\n", tmp);
 925 }
 926
 927 static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
 928                                           struct i915_power_well *power_well)
 929 {
 930         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 931
 932         WARN_ON(dev_priv->cdclk_freq !=
 933                 dev_priv->display.get_display_clock_speed(&dev_priv->drm));
 934
 935         gen9_assert_dbuf_enabled(dev_priv);
 936
 937         if (IS_BROXTON(dev_priv))
 938                 bxt_verify_ddi_phy_power_wells(dev_priv);
 939 }
 940
 941 static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
 942                                            struct i915_power_well *power_well)
 943 {
 944         if (!dev_priv->csr.dmc_payload)
 945                 return;
 946
 947         if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC6)
 948                 skl_enable_dc6(dev_priv);
 949         else if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5)
 950                 gen9_enable_dc5(dev_priv);
 951 }
 952
 953 static void gen9_dc_off_power_well_sync_hw(struct drm_i915_private *dev_priv,
 954                                            struct i915_power_well *power_well)
 955 {
 956         if (power_well->count > 0)
 957                 gen9_dc_off_power_well_enable(dev_priv, power_well);
 958         else
 959                 gen9_dc_off_power_well_disable(dev_priv, power_well);
 960 }
 961
 962 static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,
 963                                            struct i915_power_well *power_well)
 964 {
 965 }
 966
 967 static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,
 968                                              struct i915_power_well *power_well)
 969 {
 970         return true;
 971 }
 972
 973 static void vlv_set_power_well(struct drm_i915_private *dev_priv,
 974                                struct i915_power_well *power_well, bool enable)
 975 {
 976         enum punit_power_well power_well_id = power_well->data;
 977         u32 mask;
 978         u32 state;
 979         u32 ctrl;
 980
 981         mask = PUNIT_PWRGT_MASK(power_well_id);
 982         state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) :
 983                          PUNIT_PWRGT_PWR_GATE(power_well_id);
 984
 985         mutex_lock(&dev_priv->rps.hw_lock);
 986
 987 #define COND \
 988         ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)
 989
 990         if (COND)
 991                 goto out;
 992
 993         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL);
 994         ctrl &= ~mask;
 995         ctrl |= state;
 996         vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl);
 997
 998         if (wait_for(COND, 100))
 999                 DRM_ERROR("timeout setting power well state %08x (%08x)\n",
1000                           state,
1001                           vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL));
1002
1003 #undef COND
1004
1005 out:
1006         mutex_unlock(&dev_priv->rps.hw_lock);
1007 }
1008
1009 static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv,
1010                                    struct i915_power_well *power_well)
1011 {
1012         vlv_set_power_well(dev_priv, power_well, power_well->count > 0);
1013 }
1014
1015 static void vlv_power_well_enable(struct drm_i915_private *dev_priv,
1016                                   struct i915_power_well *power_well)
1017 {
1018         vlv_set_power_well(dev_priv, power_well, true);
1019 }
1020
1021 static void vlv_power_well_disable(struct drm_i915_private *dev_priv,
1022                                    struct i915_power_well *power_well)
1023 {
1024         vlv_set_power_well(dev_priv, power_well, false);
1025 }
1026
1027 static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
1028                                    struct i915_power_well *power_well)
1029 {
1030         int power_well_id = power_well->data;
1031         bool enabled = false;
1032         u32 mask;
1033         u32 state;
1034         u32 ctrl;
1035
1036         mask = PUNIT_PWRGT_MASK(power_well_id);
1037         ctrl = PUNIT_PWRGT_PWR_ON(power_well_id);
1038
1039         mutex_lock(&dev_priv->rps.hw_lock);
1040
1041         state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask;
1042         /*
1043          * We only ever set the power-on and power-gate states, anything
1044          * else is unexpected.
1045          */
1046         WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) &&
1047                 state != PUNIT_PWRGT_PWR_GATE(power_well_id));
1048         if (state == ctrl)
1049                 enabled = true;
1050
1051         /*
1052          * A transient state at this point would mean some unexpected party
1053          * is poking at the power controls too.
1054          */
1055         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask;
1056         WARN_ON(ctrl != state);
1057
1058         mutex_unlock(&dev_priv->rps.hw_lock);
1059
1060         return enabled;
1061 }
1062
1063 static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
1064 {
1065         I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
1066
1067         /*
1068          * Disable trickle feed and enable pnd deadline calculation
1069          */
1070         I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
1071         I915_WRITE(CBR1_VLV, 0);
1072
1073         WARN_ON(dev_priv->rawclk_freq == 0);
1074
1075         I915_WRITE(RAWCLK_FREQ_VLV,
1076                    DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 1000));
1077 }
1078
1079 static void vlv_display_power_well_init(struct drm_i915_private *dev_priv)
1080 {
1081         struct intel_encoder *encoder;
1082         enum pipe pipe;
1083
1084         /*
1085          * Enable the CRI clock source so we can get at the
1086          * display and the reference clock for VGA
1087          * hotplug / manual detection. Supposedly DSI also
1088          * needs the ref clock up and running.
1089          *
1090          * CHV DPLL B/C have some issues if VGA mode is enabled.
1091          */
1092         for_each_pipe(&dev_priv->drm, pipe) {
1093                 u32 val = I915_READ(DPLL(pipe));
1094
1095                 val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1096                 if (pipe != PIPE_A)
1097                         val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1098
1099                 I915_WRITE(DPLL(pipe), val);
1100         }
1101
1102         vlv_init_display_clock_gating(dev_priv);
1103
1104         spin_lock_irq(&dev_priv->irq_lock);
1105         valleyview_enable_display_irqs(dev_priv);
1106         spin_unlock_irq(&dev_priv->irq_lock);
1107
1108         /*
1109          * During driver initialization/resume we can avoid restoring the
1110          * part of the HW/SW state that will be inited anyway explicitly.
1111          */
1112         if (dev_priv->power_domains.initializing)
1113                 return;
1114
1115         intel_hpd_init(dev_priv);
1116
1117         /* Re-enable the ADPA, if we have one */
1118         for_each_intel_encoder(&dev_priv->drm, encoder) {
1119                 if (encoder->type == INTEL_OUTPUT_ANALOG)
1120                         intel_crt_reset(&encoder->base);
1121         }
1122
1123         i915_redisable_vga_power_on(&dev_priv->drm);
1124 }
1125
1126 static void vlv_display_power_well_deinit(struct drm_i915_private *dev_priv)
1127 {
1128         spin_lock_irq(&dev_priv->irq_lock);
1129         valleyview_disable_display_irqs(dev_priv);
1130         spin_unlock_irq(&dev_priv->irq_lock);
1131
1132         /* make sure we're done processing display irqs */
1133         synchronize_irq(dev_priv->drm.irq);
1134
1135         intel_power_sequencer_reset(dev_priv);
1136
1137         intel_hpd_poll_init(dev_priv);
1138 }
1139
1140 static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv,
1141                                           struct i915_power_well *power_well)
1142 {
1143         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
1144
1145         vlv_set_power_well(dev_priv, power_well, true);
1146
1147         vlv_display_power_well_init(dev_priv);
1148 }
1149
1150 static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv,
1151                                            struct i915_power_well *power_well)
1152 {
1153         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
1154
1155         vlv_display_power_well_deinit(dev_priv);
1156
1157         vlv_set_power_well(dev_priv, power_well, false);
1158 }
1159
1160 static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
1161                                            struct i915_power_well *power_well)
1162 {
1163         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
1164
1165         /* since ref/cri clock was enabled */
1166         udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
1167
1168         vlv_set_power_well(dev_priv, power_well, true);
1169
1170         /*
1171          * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1172          *  6.  De-assert cmn_reset/side_reset. Same as VLV X0.
1173          *   a. GUnit 0x2110 bit[0] set to 1 (def 0)
1174          *   b. The other bits such as sfr settings / modesel may all
1175          *      be set to 0.
1176          *
1177          * This should only be done on init and resume from S3 with
1178          * both PLLs disabled, or we risk losing DPIO and PLL
1179          * synchronization.
1180          */
1181         I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
1182 }
1183
1184 static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
1185                                             struct i915_power_well *power_well)
1186 {
1187         enum pipe pipe;
1188
1189         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
1190
1191         for_each_pipe(dev_priv, pipe)
1192                 assert_pll_disabled(dev_priv, pipe);
1193
1194         /* Assert common reset */
1195         I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST);
1196
1197         vlv_set_power_well(dev_priv, power_well, false);
1198 }
1199
1200 #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
1201
1202 static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv,
1203                                                  int power_well_id)
1204 {
1205         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1206         int i;
1207
1208         for (i = 0; i < power_domains->power_well_count; i++) {
1209                 struct i915_power_well *power_well;
1210
1211                 power_well = &power_domains->power_wells[i];
1212                 if (power_well->data == power_well_id)
1213                         return power_well;
1214         }
1215
1216         return NULL;
1217 }
1218
1219 #define BITS_SET(val, bits) (((val) & (bits)) == (bits))
1220
1221 static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
1222 {
1223         struct i915_power_well *cmn_bc =
1224                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
1225         struct i915_power_well *cmn_d =
1226                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D);
1227         u32 phy_control = dev_priv->chv_phy_control;
1228         u32 phy_status = 0;
1229         u32 phy_status_mask = 0xffffffff;
1230
1231         /*
1232          * The BIOS can leave the PHY is some weird state
1233          * where it doesn't fully power down some parts.
1234          * Disable the asserts until the PHY has been fully
1235          * reset (ie. the power well has been disabled at
1236          * least once).
1237          */
1238         if (!dev_priv->chv_phy_assert[DPIO_PHY0])
1239                 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0) |
1240                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0) |
1241                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1) |
1242                                      PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1) |
1243                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0) |
1244                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1));
1245
1246         if (!dev_priv->chv_phy_assert[DPIO_PHY1])
1247                 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0) |
1248                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0) |
1249                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1));
1250
1251         if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) {
1252                 phy_status |= PHY_POWERGOOD(DPIO_PHY0);
1253
1254                 /* this assumes override is only used to enable lanes */
1255                 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0)) == 0)
1256                         phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0);
1257
1258                 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1)) == 0)
1259                         phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1);
1260
1261                 /* CL1 is on whenever anything is on in either channel */
1262                 if (BITS_SET(phy_control,
1263                              PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0) |
1264                              PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)))
1265                         phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0);
1266
1267                 /*
1268                  * The DPLLB check accounts for the pipe B + port A usage
1269                  * with CL2 powered up but all the lanes in the second channel
1270                  * powered down.
1271                  */
1272                 if (BITS_SET(phy_control,
1273                              PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)) &&
1274                     (I915_READ(DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0)
1275                         phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1);
1276
1277                 if (BITS_SET(phy_control,
1278                              PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH0)))
1279                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0);
1280                 if (BITS_SET(phy_control,
1281                              PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH0)))
1282                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1);
1283
1284                 if (BITS_SET(phy_control,
1285                              PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH1)))
1286                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0);
1287                 if (BITS_SET(phy_control,
1288                              PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH1)))
1289                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1);
1290         }
1291
1292         if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) {
1293                 phy_status |= PHY_POWERGOOD(DPIO_PHY1);
1294
1295                 /* this assumes override is only used to enable lanes */
1296                 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0)) == 0)
1297                         phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0);
1298
1299                 if (BITS_SET(phy_control,
1300                              PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0)))
1301                         phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0);
1302
1303                 if (BITS_SET(phy_control,
1304                              PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY1, DPIO_CH0)))
1305                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0);
1306                 if (BITS_SET(phy_control,
1307                              PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY1, DPIO_CH0)))
1308                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1);
1309         }
1310
1311         phy_status &= phy_status_mask;
1312
1313         /*
1314          * The PHY may be busy with some initial calibration and whatnot,
1315          * so the power state can take a while to actually change.
1316          */
1317         if (intel_wait_for_register(dev_priv,
1318                                     DISPLAY_PHY_STATUS,
1319                                     phy_status_mask,
1320                                     phy_status,
1321                                     10))
1322                 DRM_ERROR("Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n",
1323                           I915_READ(DISPLAY_PHY_STATUS) & phy_status_mask,
1324                            phy_status, dev_priv->chv_phy_control);
1325 }
1326
1327 #undef BITS_SET
1328
1329 static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
1330                                            struct i915_power_well *power_well)
1331 {
1332         enum dpio_phy phy;
1333         enum pipe pipe;
1334         uint32_t tmp;
1335
1336         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
1337                      power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
1338
1339         if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
1340                 pipe = PIPE_A;
1341                 phy = DPIO_PHY0;
1342         } else {
1343                 pipe = PIPE_C;
1344                 phy = DPIO_PHY1;
1345         }
1346
1347         /* since ref/cri clock was enabled */
1348         udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
1349         vlv_set_power_well(dev_priv, power_well, true);
1350
1351         /* Poll for phypwrgood signal */
1352         if (intel_wait_for_register(dev_priv,
1353                                     DISPLAY_PHY_STATUS,
1354                                     PHY_POWERGOOD(phy),
1355                                     PHY_POWERGOOD(phy),
1356                                     1))
1357                 DRM_ERROR("Display PHY %d is not power up\n", phy);
1358
1359         mutex_lock(&dev_priv->sb_lock);
1360
1361         /* Enable dynamic power down */
1362         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW28);
1363         tmp |= DPIO_DYNPWRDOWNEN_CH0 | DPIO_CL1POWERDOWNEN |
1364                 DPIO_SUS_CLK_CONFIG_GATE_CLKREQ;
1365         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW28, tmp);
1366
1367         if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
1368                 tmp = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW6_CH1);
1369                 tmp |= DPIO_DYNPWRDOWNEN_CH1;
1370                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW6_CH1, tmp);
1371         } else {
1372                 /*
1373                  * Force the non-existing CL2 off. BXT does this
1374                  * too, so maybe it saves some power even though
1375                  * CL2 doesn't exist?
1376                  */
1377                 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
1378                 tmp |= DPIO_CL2_LDOFUSE_PWRENB;
1379                 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, tmp);
1380         }
1381
1382         mutex_unlock(&dev_priv->sb_lock);
1383
1384         dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy);
1385         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1386
1387         DRM_DEBUG_KMS("Enabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
1388                       phy, dev_priv->chv_phy_control);
1389
1390         assert_chv_phy_status(dev_priv);
1391 }
1392
1393 static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
1394                                             struct i915_power_well *power_well)
1395 {
1396         enum dpio_phy phy;
1397
1398         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
1399                      power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
1400
1401         if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
1402                 phy = DPIO_PHY0;
1403                 assert_pll_disabled(dev_priv, PIPE_A);
1404                 assert_pll_disabled(dev_priv, PIPE_B);
1405         } else {
1406                 phy = DPIO_PHY1;
1407                 assert_pll_disabled(dev_priv, PIPE_C);
1408         }
1409
1410         dev_priv->chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy);
1411         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1412
1413         vlv_set_power_well(dev_priv, power_well, false);
1414
1415         DRM_DEBUG_KMS("Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
1416                       phy, dev_priv->chv_phy_control);
1417
1418         /* PHY is fully reset now, so we can enable the PHY state asserts */
1419         dev_priv->chv_phy_assert[phy] = true;
1420
1421         assert_chv_phy_status(dev_priv);
1422 }
1423
1424 static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1425                                      enum dpio_channel ch, bool override, unsigned int mask)
1426 {
1427         enum pipe pipe = phy == DPIO_PHY0 ? PIPE_A : PIPE_C;
1428         u32 reg, val, expected, actual;
1429
1430         /*
1431          * The BIOS can leave the PHY is some weird state
1432          * where it doesn't fully power down some parts.
1433          * Disable the asserts until the PHY has been fully
1434          * reset (ie. the power well has been disabled at
1435          * least once).
1436          */
1437         if (!dev_priv->chv_phy_assert[phy])
1438                 return;
1439
1440         if (ch == DPIO_CH0)
1441                 reg = _CHV_CMN_DW0_CH0;
1442         else
1443                 reg = _CHV_CMN_DW6_CH1;
1444
1445         mutex_lock(&dev_priv->sb_lock);
1446         val = vlv_dpio_read(dev_priv, pipe, reg);
1447         mutex_unlock(&dev_priv->sb_lock);
1448
1449         /*
1450          * This assumes !override is only used when the port is disabled.
1451          * All lanes should power down even without the override when
1452          * the port is disabled.
1453          */
1454         if (!override || mask == 0xf) {
1455                 expected = DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN;
1456                 /*
1457                  * If CH1 common lane is not active anymore
1458                  * (eg. for pipe B DPLL) the entire channel will
1459                  * shut down, which causes the common lane registers
1460                  * to read as 0. That means we can't actually check
1461                  * the lane power down status bits, but as the entire
1462                  * register reads as 0 it's a good indication that the
1463                  * channel is indeed entirely powered down.
1464                  */
1465                 if (ch == DPIO_CH1 && val == 0)
1466                         expected = 0;
1467         } else if (mask != 0x0) {
1468                 expected = DPIO_ANYDL_POWERDOWN;
1469         } else {
1470                 expected = 0;
1471         }
1472
1473         if (ch == DPIO_CH0)
1474                 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH0;
1475         else
1476                 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH1;
1477         actual &= DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN;
1478
1479         WARN(actual != expected,
1480              "Unexpected DPIO lane power down: all %d, any %d. Expected: all %d, any %d. (0x%x = 0x%08x)\n",
1481              !!(actual & DPIO_ALLDL_POWERDOWN), !!(actual & DPIO_ANYDL_POWERDOWN),
1482              !!(expected & DPIO_ALLDL_POWERDOWN), !!(expected & DPIO_ANYDL_POWERDOWN),
1483              reg, val);
1484 }
1485
1486 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1487                           enum dpio_channel ch, bool override)
1488 {
1489         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1490         bool was_override;
1491
1492         mutex_lock(&power_domains->lock);
1493
1494         was_override = dev_priv->chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1495
1496         if (override == was_override)
1497                 goto out;
1498
1499         if (override)
1500                 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1501         else
1502                 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1503
1504         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1505
1506         DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d (DPIO_PHY_CONTROL=0x%08x)\n",
1507                       phy, ch, dev_priv->chv_phy_control);
1508
1509         assert_chv_phy_status(dev_priv);
1510
1511 out:
1512         mutex_unlock(&power_domains->lock);
1513
1514         return was_override;
1515 }
1516
1517 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1518                              bool override, unsigned int mask)
1519 {
1520         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1521         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1522         enum dpio_phy phy = vlv_dport_to_phy(enc_to_dig_port(&encoder->base));
1523         enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
1524
1525         mutex_lock(&power_domains->lock);
1526
1527         dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch);
1528         dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch);
1529
1530         if (override)
1531                 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1532         else
1533                 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1534
1535         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1536
1537         DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d lanes 0x%x (PHY_CONTROL=0x%08x)\n",
1538                       phy, ch, mask, dev_priv->chv_phy_control);
1539
1540         assert_chv_phy_status(dev_priv);
1541
1542         assert_chv_phy_powergate(dev_priv, phy, ch, override, mask);
1543
1544         mutex_unlock(&power_domains->lock);
1545 }
1546
1547 static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv,
1548                                         struct i915_power_well *power_well)
1549 {
1550         enum pipe pipe = power_well->data;
1551         bool enabled;
1552         u32 state, ctrl;
1553
1554         mutex_lock(&dev_priv->rps.hw_lock);
1555
1556         state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe);
1557         /*
1558          * We only ever set the power-on and power-gate states, anything
1559          * else is unexpected.
1560          */
1561         WARN_ON(state != DP_SSS_PWR_ON(pipe) && state != DP_SSS_PWR_GATE(pipe));
1562         enabled = state == DP_SSS_PWR_ON(pipe);
1563
1564         /*
1565          * A transient state at this point would mean some unexpected party
1566          * is poking at the power controls too.
1567          */
1568         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe);
1569         WARN_ON(ctrl << 16 != state);
1570
1571         mutex_unlock(&dev_priv->rps.hw_lock);
1572
1573         return enabled;
1574 }
1575
1576 static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv,
1577                                     struct i915_power_well *power_well,
1578                                     bool enable)
1579 {
1580         enum pipe pipe = power_well->data;
1581         u32 state;
1582         u32 ctrl;
1583
1584         state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe);
1585
1586         mutex_lock(&dev_priv->rps.hw_lock);
1587
1588 #define COND \
1589         ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state)
1590
1591         if (COND)
1592                 goto out;
1593
1594         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
1595         ctrl &= ~DP_SSC_MASK(pipe);
1596         ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe);
1597         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl);
1598
1599         if (wait_for(COND, 100))
1600                 DRM_ERROR("timeout setting power well state %08x (%08x)\n",
1601                           state,
1602                           vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ));
1603
1604 #undef COND
1605
1606 out:
1607         mutex_unlock(&dev_priv->rps.hw_lock);
1608 }
1609
1610 static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv,
1611                                         struct i915_power_well *power_well)
1612 {
1613         WARN_ON_ONCE(power_well->data != PIPE_A);
1614
1615         chv_set_pipe_power_well(dev_priv, power_well, power_well->count > 0);
1616 }
1617
1618 static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv,
1619                                        struct i915_power_well *power_well)
1620 {
1621         WARN_ON_ONCE(power_well->data != PIPE_A);
1622
1623         chv_set_pipe_power_well(dev_priv, power_well, true);
1624
1625         vlv_display_power_well_init(dev_priv);
1626 }
1627
1628 static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv,
1629                                         struct i915_power_well *power_well)
1630 {
1631         WARN_ON_ONCE(power_well->data != PIPE_A);
1632
1633         vlv_display_power_well_deinit(dev_priv);
1634
1635         chv_set_pipe_power_well(dev_priv, power_well, false);
1636 }
1637
1638 static void
1639 __intel_display_power_get_domain(struct drm_i915_private *dev_priv,
1640                                  enum intel_display_power_domain domain)
1641 {
1642         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1643         struct i915_power_well *power_well;
1644         int i;
1645
1646         for_each_power_well(i, power_well, BIT(domain), power_domains)
1647                 intel_power_well_get(dev_priv, power_well);
1648
1649         power_domains->domain_use_count[domain]++;
1650 }
1651
1652 /**
1653  * intel_display_power_get - grab a power domain reference
1654  * @dev_priv: i915 device instance
1655  * @domain: power domain to reference
1656  *
1657  * This function grabs a power domain reference for @domain and ensures that the
1658  * power domain and all its parents are powered up. Therefore users should only
1659  * grab a reference to the innermost power domain they need.
1660  *
1661  * Any power domain reference obtained by this function must have a symmetric
1662  * call to intel_display_power_put() to release the reference again.
1663  */
1664 void intel_display_power_get(struct drm_i915_private *dev_priv,
1665                              enum intel_display_power_domain domain)
1666 {
1667         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1668
1669         intel_runtime_pm_get(dev_priv);
1670
1671         mutex_lock(&power_domains->lock);
1672
1673         __intel_display_power_get_domain(dev_priv, domain);
1674
1675         mutex_unlock(&power_domains->lock);
1676 }
1677
1678 /**
1679  * intel_display_power_get_if_enabled - grab a reference for an enabled display power domain
1680  * @dev_priv: i915 device instance
1681  * @domain: power domain to reference
1682  *
1683  * This function grabs a power domain reference for @domain and ensures that the
1684  * power domain and all its parents are powered up. Therefore users should only
1685  * grab a reference to the innermost power domain they need.
1686  *
1687  * Any power domain reference obtained by this function must have a symmetric
1688  * call to intel_display_power_put() to release the reference again.
1689  */
1690 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
1691                                         enum intel_display_power_domain domain)
1692 {
1693         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1694         bool is_enabled;
1695
1696         if (!intel_runtime_pm_get_if_in_use(dev_priv))
1697                 return false;
1698
1699         mutex_lock(&power_domains->lock);
1700
1701         if (__intel_display_power_is_enabled(dev_priv, domain)) {
1702                 __intel_display_power_get_domain(dev_priv, domain);
1703                 is_enabled = true;
1704         } else {
1705                 is_enabled = false;
1706         }
1707
1708         mutex_unlock(&power_domains->lock);
1709
1710         if (!is_enabled)
1711                 intel_runtime_pm_put(dev_priv);
1712
1713         return is_enabled;
1714 }
1715
1716 /**
1717  * intel_display_power_put - release a power domain reference
1718  * @dev_priv: i915 device instance
1719  * @domain: power domain to reference
1720  *
1721  * This function drops the power domain reference obtained by
1722  * intel_display_power_get() and might power down the corresponding hardware
1723  * block right away if this is the last reference.
1724  */
1725 void intel_display_power_put(struct drm_i915_private *dev_priv,
1726                              enum intel_display_power_domain domain)
1727 {
1728         struct i915_power_domains *power_domains;
1729         struct i915_power_well *power_well;
1730         int i;
1731
1732         power_domains = &dev_priv->power_domains;
1733
1734         mutex_lock(&power_domains->lock);
1735
1736         WARN(!power_domains->domain_use_count[domain],
1737              "Use count on domain %s is already zero\n",
1738              intel_display_power_domain_str(domain));
1739         power_domains->domain_use_count[domain]--;
1740
1741         for_each_power_well_rev(i, power_well, BIT(domain), power_domains)
1742                 intel_power_well_put(dev_priv, power_well);
1743
1744         mutex_unlock(&power_domains->lock);
1745
1746         intel_runtime_pm_put(dev_priv);
1747 }
1748
1749 #define HSW_DISPLAY_POWER_DOMAINS (                     \
1750         BIT(POWER_DOMAIN_PIPE_B) |                      \
1751         BIT(POWER_DOMAIN_PIPE_C) |                      \
1752         BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) |         \
1753         BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |         \
1754         BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |         \
1755         BIT(POWER_DOMAIN_TRANSCODER_A) |                \
1756         BIT(POWER_DOMAIN_TRANSCODER_B) |                \
1757         BIT(POWER_DOMAIN_TRANSCODER_C) |                \
1758         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |            \
1759         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |            \
1760         BIT(POWER_DOMAIN_PORT_DDI_D_LANES) |            \
1761         BIT(POWER_DOMAIN_PORT_CRT) | /* DDI E */        \
1762         BIT(POWER_DOMAIN_VGA) |                         \
1763         BIT(POWER_DOMAIN_AUDIO) |                       \
1764         BIT(POWER_DOMAIN_INIT))
1765
1766 #define BDW_DISPLAY_POWER_DOMAINS (                     \
1767         BIT(POWER_DOMAIN_PIPE_B) |                      \
1768         BIT(POWER_DOMAIN_PIPE_C) |                      \
1769         BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |         \
1770         BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |         \
1771         BIT(POWER_DOMAIN_TRANSCODER_A) |                \
1772         BIT(POWER_DOMAIN_TRANSCODER_B) |                \
1773         BIT(POWER_DOMAIN_TRANSCODER_C) |                \
1774         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |            \
1775         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |            \
1776         BIT(POWER_DOMAIN_PORT_DDI_D_LANES) |            \
1777         BIT(POWER_DOMAIN_PORT_CRT) | /* DDI E */        \
1778         BIT(POWER_DOMAIN_VGA) |                         \
1779         BIT(POWER_DOMAIN_AUDIO) |                       \
1780         BIT(POWER_DOMAIN_INIT))
1781
1782 #define VLV_DISPLAY_POWER_DOMAINS (             \
1783         BIT(POWER_DOMAIN_PIPE_A) |              \
1784         BIT(POWER_DOMAIN_PIPE_B) |              \
1785         BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
1786         BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
1787         BIT(POWER_DOMAIN_TRANSCODER_A) |        \
1788         BIT(POWER_DOMAIN_TRANSCODER_B) |        \
1789         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |    \
1790         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |    \
1791         BIT(POWER_DOMAIN_PORT_DSI) |            \
1792         BIT(POWER_DOMAIN_PORT_CRT) |            \
1793         BIT(POWER_DOMAIN_VGA) |                 \
1794         BIT(POWER_DOMAIN_AUDIO) |               \
1795         BIT(POWER_DOMAIN_AUX_B) |               \
1796         BIT(POWER_DOMAIN_AUX_C) |               \
1797         BIT(POWER_DOMAIN_GMBUS) |               \
1798         BIT(POWER_DOMAIN_INIT))
1799
1800 #define VLV_DPIO_CMN_BC_POWER_DOMAINS (         \
1801         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |    \
1802         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |    \
1803         BIT(POWER_DOMAIN_PORT_CRT) |            \
1804         BIT(POWER_DOMAIN_AUX_B) |               \
1805         BIT(POWER_DOMAIN_AUX_C) |               \
1806         BIT(POWER_DOMAIN_INIT))
1807
1808 #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS (  \
1809         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |    \
1810         BIT(POWER_DOMAIN_AUX_B) |               \
1811         BIT(POWER_DOMAIN_INIT))
1812
1813 #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS (  \
1814         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |    \
1815         BIT(POWER_DOMAIN_AUX_B) |               \
1816         BIT(POWER_DOMAIN_INIT))
1817
1818 #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS (  \
1819         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |    \
1820         BIT(POWER_DOMAIN_AUX_C) |               \
1821         BIT(POWER_DOMAIN_INIT))
1822
1823 #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS (  \
1824         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |    \
1825         BIT(POWER_DOMAIN_AUX_C) |               \
1826         BIT(POWER_DOMAIN_INIT))
1827
1828 #define CHV_DISPLAY_POWER_DOMAINS (             \
1829         BIT(POWER_DOMAIN_PIPE_A) |              \
1830         BIT(POWER_DOMAIN_PIPE_B) |              \
1831         BIT(POWER_DOMAIN_PIPE_C) |              \
1832         BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
1833         BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
1834         BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
1835         BIT(POWER_DOMAIN_TRANSCODER_A) |        \
1836         BIT(POWER_DOMAIN_TRANSCODER_B) |        \
1837         BIT(POWER_DOMAIN_TRANSCODER_C) |        \
1838         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |    \
1839         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |    \
1840         BIT(POWER_DOMAIN_PORT_DDI_D_LANES) |    \
1841         BIT(POWER_DOMAIN_PORT_DSI) |            \
1842         BIT(POWER_DOMAIN_VGA) |                 \
1843         BIT(POWER_DOMAIN_AUDIO) |               \
1844         BIT(POWER_DOMAIN_AUX_B) |               \
1845         BIT(POWER_DOMAIN_AUX_C) |               \
1846         BIT(POWER_DOMAIN_AUX_D) |               \
1847         BIT(POWER_DOMAIN_GMBUS) |               \
1848         BIT(POWER_DOMAIN_INIT))
1849
1850 #define CHV_DPIO_CMN_BC_POWER_DOMAINS (         \
1851         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |    \
1852         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |    \
1853         BIT(POWER_DOMAIN_AUX_B) |               \
1854         BIT(POWER_DOMAIN_AUX_C) |               \
1855         BIT(POWER_DOMAIN_INIT))
1856
1857 #define CHV_DPIO_CMN_D_POWER_DOMAINS (          \
1858         BIT(POWER_DOMAIN_PORT_DDI_D_LANES) |    \
1859         BIT(POWER_DOMAIN_AUX_D) |               \
1860         BIT(POWER_DOMAIN_INIT))
1861
1862 static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
1863         .sync_hw = i9xx_always_on_power_well_noop,
1864         .enable = i9xx_always_on_power_well_noop,
1865         .disable = i9xx_always_on_power_well_noop,
1866         .is_enabled = i9xx_always_on_power_well_enabled,
1867 };
1868
1869 static const struct i915_power_well_ops chv_pipe_power_well_ops = {
1870         .sync_hw = chv_pipe_power_well_sync_hw,
1871         .enable = chv_pipe_power_well_enable,
1872         .disable = chv_pipe_power_well_disable,
1873         .is_enabled = chv_pipe_power_well_enabled,
1874 };
1875
1876 static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = {
1877         .sync_hw = vlv_power_well_sync_hw,
1878         .enable = chv_dpio_cmn_power_well_enable,
1879         .disable = chv_dpio_cmn_power_well_disable,
1880         .is_enabled = vlv_power_well_enabled,
1881 };
1882
1883 static struct i915_power_well i9xx_always_on_power_well[] = {
1884         {
1885                 .name = "always-on",
1886                 .always_on = 1,
1887                 .domains = POWER_DOMAIN_MASK,
1888                 .ops = &i9xx_always_on_power_well_ops,
1889         },
1890 };
1891
1892 static const struct i915_power_well_ops hsw_power_well_ops = {
1893         .sync_hw = hsw_power_well_sync_hw,
1894         .enable = hsw_power_well_enable,
1895         .disable = hsw_power_well_disable,
1896         .is_enabled = hsw_power_well_enabled,
1897 };
1898
1899 static const struct i915_power_well_ops skl_power_well_ops = {
1900         .sync_hw = skl_power_well_sync_hw,
1901         .enable = skl_power_well_enable,
1902         .disable = skl_power_well_disable,
1903         .is_enabled = skl_power_well_enabled,
1904 };
1905
1906 static const struct i915_power_well_ops gen9_dc_off_power_well_ops = {
1907         .sync_hw = gen9_dc_off_power_well_sync_hw,
1908         .enable = gen9_dc_off_power_well_enable,
1909         .disable = gen9_dc_off_power_well_disable,
1910         .is_enabled = gen9_dc_off_power_well_enabled,
1911 };
1912
1913 static const struct i915_power_well_ops bxt_dpio_cmn_power_well_ops = {
1914         .sync_hw = bxt_dpio_cmn_power_well_sync_hw,
1915         .enable = bxt_dpio_cmn_power_well_enable,
1916         .disable = bxt_dpio_cmn_power_well_disable,
1917         .is_enabled = bxt_dpio_cmn_power_well_enabled,
1918 };
1919
1920 static struct i915_power_well hsw_power_wells[] = {
1921         {
1922                 .name = "always-on",
1923                 .always_on = 1,
1924                 .domains = POWER_DOMAIN_MASK,
1925                 .ops = &i9xx_always_on_power_well_ops,
1926         },
1927         {
1928                 .name = "display",
1929                 .domains = HSW_DISPLAY_POWER_DOMAINS,
1930                 .ops = &hsw_power_well_ops,
1931         },
1932 };
1933
1934 static struct i915_power_well bdw_power_wells[] = {
1935         {
1936                 .name = "always-on",
1937                 .always_on = 1,
1938                 .domains = POWER_DOMAIN_MASK,
1939                 .ops = &i9xx_always_on_power_well_ops,
1940         },
1941         {
1942                 .name = "display",
1943                 .domains = BDW_DISPLAY_POWER_DOMAINS,
1944                 .ops = &hsw_power_well_ops,
1945         },
1946 };
1947
1948 static const struct i915_power_well_ops vlv_display_power_well_ops = {
1949         .sync_hw = vlv_power_well_sync_hw,
1950         .enable = vlv_display_power_well_enable,
1951         .disable = vlv_display_power_well_disable,
1952         .is_enabled = vlv_power_well_enabled,
1953 };
1954
1955 static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = {
1956         .sync_hw = vlv_power_well_sync_hw,
1957         .enable = vlv_dpio_cmn_power_well_enable,
1958         .disable = vlv_dpio_cmn_power_well_disable,
1959         .is_enabled = vlv_power_well_enabled,
1960 };
1961
1962 static const struct i915_power_well_ops vlv_dpio_power_well_ops = {
1963         .sync_hw = vlv_power_well_sync_hw,
1964         .enable = vlv_power_well_enable,
1965         .disable = vlv_power_well_disable,
1966         .is_enabled = vlv_power_well_enabled,
1967 };
1968
1969 static struct i915_power_well vlv_power_wells[] = {
1970         {
1971                 .name = "always-on",
1972                 .always_on = 1,
1973                 .domains = POWER_DOMAIN_MASK,
1974                 .ops = &i9xx_always_on_power_well_ops,
1975                 .data = PUNIT_POWER_WELL_ALWAYS_ON,
1976         },
1977         {
1978                 .name = "display",
1979                 .domains = VLV_DISPLAY_POWER_DOMAINS,
1980                 .data = PUNIT_POWER_WELL_DISP2D,
1981                 .ops = &vlv_display_power_well_ops,
1982         },
1983         {
1984                 .name = "dpio-tx-b-01",
1985                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1986                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1987                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1988                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1989                 .ops = &vlv_dpio_power_well_ops,
1990                 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
1991         },
1992         {
1993                 .name = "dpio-tx-b-23",
1994                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1995                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1996                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1997                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1998                 .ops = &vlv_dpio_power_well_ops,
1999                 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
2000         },
2001         {
2002                 .name = "dpio-tx-c-01",
2003                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
2004                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
2005                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
2006                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
2007                 .ops = &vlv_dpio_power_well_ops,
2008                 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
2009         },
2010         {
2011                 .name = "dpio-tx-c-23",
2012                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
2013                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
2014                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
2015                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
2016                 .ops = &vlv_dpio_power_well_ops,
2017                 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
2018         },
2019         {
2020                 .name = "dpio-common",
2021                 .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,
2022                 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
2023                 .ops = &vlv_dpio_cmn_power_well_ops,
2024         },
2025 };
2026
2027 static struct i915_power_well chv_power_wells[] = {
2028         {
2029                 .name = "always-on",
2030                 .always_on = 1,
2031                 .domains = POWER_DOMAIN_MASK,
2032                 .ops = &i9xx_always_on_power_well_ops,
2033         },
2034         {
2035                 .name = "display",
2036                 /*
2037                  * Pipe A power well is the new disp2d well. Pipe B and C
2038                  * power wells don't actually exist. Pipe A power well is
2039                  * required for any pipe to work.
2040                  */
2041                 .domains = CHV_DISPLAY_POWER_DOMAINS,
2042                 .data = PIPE_A,
2043                 .ops = &chv_pipe_power_well_ops,
2044         },
2045         {
2046                 .name = "dpio-common-bc",
2047                 .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS,
2048                 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
2049                 .ops = &chv_dpio_cmn_power_well_ops,
2050         },
2051         {
2052                 .name = "dpio-common-d",
2053                 .domains = CHV_DPIO_CMN_D_POWER_DOMAINS,
2054                 .data = PUNIT_POWER_WELL_DPIO_CMN_D,
2055                 .ops = &chv_dpio_cmn_power_well_ops,
2056         },
2057 };
2058
2059 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
2060                                     int power_well_id)
2061 {
2062         struct i915_power_well *power_well;
2063         bool ret;
2064
2065         power_well = lookup_power_well(dev_priv, power_well_id);
2066         ret = power_well->ops->is_enabled(dev_priv, power_well);
2067
2068         return ret;
2069 }
2070
2071 static struct i915_power_well skl_power_wells[] = {
2072         {
2073                 .name = "always-on",
2074                 .always_on = 1,
2075                 .domains = POWER_DOMAIN_MASK,
2076                 .ops = &i9xx_always_on_power_well_ops,
2077                 .data = SKL_DISP_PW_ALWAYS_ON,
2078         },
2079         {
2080                 .name = "power well 1",
2081                 /* Handled by the DMC firmware */
2082                 .domains = 0,
2083                 .ops = &skl_power_well_ops,
2084                 .data = SKL_DISP_PW_1,
2085         },
2086         {
2087                 .name = "MISC IO power well",
2088                 /* Handled by the DMC firmware */
2089                 .domains = 0,
2090                 .ops = &skl_power_well_ops,
2091                 .data = SKL_DISP_PW_MISC_IO,
2092         },
2093         {
2094                 .name = "DC off",
2095                 .domains = SKL_DISPLAY_DC_OFF_POWER_DOMAINS,
2096                 .ops = &gen9_dc_off_power_well_ops,
2097                 .data = SKL_DISP_PW_DC_OFF,
2098         },
2099         {
2100                 .name = "power well 2",
2101                 .domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS,
2102                 .ops = &skl_power_well_ops,
2103                 .data = SKL_DISP_PW_2,
2104         },
2105         {
2106                 .name = "DDI A/E power well",
2107                 .domains = SKL_DISPLAY_DDI_A_E_POWER_DOMAINS,
2108                 .ops = &skl_power_well_ops,
2109                 .data = SKL_DISP_PW_DDI_A_E,
2110         },
2111         {
2112                 .name = "DDI B power well",
2113                 .domains = SKL_DISPLAY_DDI_B_POWER_DOMAINS,
2114                 .ops = &skl_power_well_ops,
2115                 .data = SKL_DISP_PW_DDI_B,
2116         },
2117         {
2118                 .name = "DDI C power well",
2119                 .domains = SKL_DISPLAY_DDI_C_POWER_DOMAINS,
2120                 .ops = &skl_power_well_ops,
2121                 .data = SKL_DISP_PW_DDI_C,
2122         },
2123         {
2124                 .name = "DDI D power well",
2125                 .domains = SKL_DISPLAY_DDI_D_POWER_DOMAINS,
2126                 .ops = &skl_power_well_ops,
2127                 .data = SKL_DISP_PW_DDI_D,
2128         },
2129 };
2130
2131 static struct i915_power_well bxt_power_wells[] = {
2132         {
2133                 .name = "always-on",
2134                 .always_on = 1,
2135                 .domains = POWER_DOMAIN_MASK,
2136                 .ops = &i9xx_always_on_power_well_ops,
2137         },
2138         {
2139                 .name = "power well 1",
2140                 .domains = 0,
2141                 .ops = &skl_power_well_ops,
2142                 .data = SKL_DISP_PW_1,
2143         },
2144         {
2145                 .name = "DC off",
2146                 .domains = BXT_DISPLAY_DC_OFF_POWER_DOMAINS,
2147                 .ops = &gen9_dc_off_power_well_ops,
2148                 .data = SKL_DISP_PW_DC_OFF,
2149         },
2150         {
2151                 .name = "power well 2",
2152                 .domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS,
2153                 .ops = &skl_power_well_ops,
2154                 .data = SKL_DISP_PW_2,
2155         },
2156         {
2157                 .name = "dpio-common-a",
2158                 .domains = BXT_DPIO_CMN_A_POWER_DOMAINS,
2159                 .ops = &bxt_dpio_cmn_power_well_ops,
2160                 .data = BXT_DPIO_CMN_A,
2161         },
2162         {
2163                 .name = "dpio-common-bc",
2164                 .domains = BXT_DPIO_CMN_BC_POWER_DOMAINS,
2165                 .ops = &bxt_dpio_cmn_power_well_ops,
2166                 .data = BXT_DPIO_CMN_BC,
2167         },
2168 };
2169
2170 static int
2171 sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv,
2172                                    int disable_power_well)
2173 {
2174         if (disable_power_well >= 0)
2175                 return !!disable_power_well;
2176
2177         return 1;
2178 }
2179
2180 static uint32_t get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
2181                                     int enable_dc)
2182 {
2183         uint32_t mask;
2184         int requested_dc;
2185         int max_dc;
2186
2187         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
2188                 max_dc = 2;
2189                 mask = 0;
2190         } else if (IS_BROXTON(dev_priv)) {
2191                 max_dc = 1;
2192                 /*
2193                  * DC9 has a separate HW flow from the rest of the DC states,
2194                  * not depending on the DMC firmware. It's needed by system
2195                  * suspend/resume, so allow it unconditionally.
2196                  */
2197                 mask = DC_STATE_EN_DC9;
2198         } else {
2199                 max_dc = 0;
2200                 mask = 0;
2201         }
2202
2203         if (!i915.disable_power_well)
2204                 max_dc = 0;
2205
2206         if (enable_dc >= 0 && enable_dc <= max_dc) {
2207                 requested_dc = enable_dc;
2208         } else if (enable_dc == -1) {
2209                 requested_dc = max_dc;
2210         } else if (enable_dc > max_dc && enable_dc <= 2) {
2211                 DRM_DEBUG_KMS("Adjusting requested max DC state (%d->%d)\n",
2212                               enable_dc, max_dc);
2213                 requested_dc = max_dc;
2214         } else {
2215                 DRM_ERROR("Unexpected value for enable_dc (%d)\n", enable_dc);
2216                 requested_dc = max_dc;
2217         }
2218
2219         if (requested_dc > 1)
2220                 mask |= DC_STATE_EN_UPTO_DC6;
2221         if (requested_dc > 0)
2222                 mask |= DC_STATE_EN_UPTO_DC5;
2223
2224         DRM_DEBUG_KMS("Allowed DC state mask %02x\n", mask);
2225
2226         return mask;
2227 }
2228
2229 #define set_power_wells(power_domains, __power_wells) ({                \
2230         (power_domains)->power_wells = (__power_wells);                 \
2231         (power_domains)->power_well_count = ARRAY_SIZE(__power_wells);  \
2232 })
2233
2234 /**
2235  * intel_power_domains_init - initializes the power domain structures
2236  * @dev_priv: i915 device instance
2237  *
2238  * Initializes the power domain structures for @dev_priv depending upon the
2239  * supported platform.
2240  */
2241 int intel_power_domains_init(struct drm_i915_private *dev_priv)
2242 {
2243         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2244
2245         i915.disable_power_well = sanitize_disable_power_well_option(dev_priv,
2246                                                      i915.disable_power_well);
2247         dev_priv->csr.allowed_dc_mask = get_allowed_dc_mask(dev_priv,
2248                                                             i915.enable_dc);
2249
2250         BUILD_BUG_ON(POWER_DOMAIN_NUM > 31);
2251
2252         mutex_init(&power_domains->lock);
2253
2254         /*
2255          * The enabling order will be from lower to higher indexed wells,
2256          * the disabling order is reversed.
2257          */
2258         if (IS_HASWELL(dev_priv)) {
2259                 set_power_wells(power_domains, hsw_power_wells);
2260         } else if (IS_BROADWELL(dev_priv)) {
2261                 set_power_wells(power_domains, bdw_power_wells);
2262         } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
2263                 set_power_wells(power_domains, skl_power_wells);
2264         } else if (IS_BROXTON(dev_priv)) {
2265                 set_power_wells(power_domains, bxt_power_wells);
2266         } else if (IS_CHERRYVIEW(dev_priv)) {
2267                 set_power_wells(power_domains, chv_power_wells);
2268         } else if (IS_VALLEYVIEW(dev_priv)) {
2269                 set_power_wells(power_domains, vlv_power_wells);
2270         } else {
2271                 set_power_wells(power_domains, i9xx_always_on_power_well);
2272         }
2273
2274         return 0;
2275 }
2276
2277 /**
2278  * intel_power_domains_fini - finalizes the power domain structures
2279  * @dev_priv: i915 device instance
2280  *
2281  * Finalizes the power domain structures for @dev_priv depending upon the
2282  * supported platform. This function also disables runtime pm and ensures that
2283  * the device stays powered up so that the driver can be reloaded.
2284  */
2285 void intel_power_domains_fini(struct drm_i915_private *dev_priv)
2286 {
2287         struct device *device = &dev_priv->drm.pdev->dev;
2288
2289         /*
2290          * The i915.ko module is still not prepared to be loaded when
2291          * the power well is not enabled, so just enable it in case
2292          * we're going to unload/reload.
2293          * The following also reacquires the RPM reference the core passed
2294          * to the driver during loading, which is dropped in
2295          * intel_runtime_pm_enable(). We have to hand back the control of the
2296          * device to the core with this reference held.
2297          */
2298         intel_display_set_init_power(dev_priv, true);
2299
2300         /* Remove the refcount we took to keep power well support disabled. */
2301         if (!i915.disable_power_well)
2302                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
2303
2304         /*
2305          * Remove the refcount we took in intel_runtime_pm_enable() in case
2306          * the platform doesn't support runtime PM.
2307          */
2308         if (!HAS_RUNTIME_PM(dev_priv))
2309                 pm_runtime_put(device);
2310 }
2311
2312 static void intel_power_domains_sync_hw(struct drm_i915_private *dev_priv)
2313 {
2314         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2315         struct i915_power_well *power_well;
2316         int i;
2317
2318         mutex_lock(&power_domains->lock);
2319         for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
2320                 power_well->ops->sync_hw(dev_priv, power_well);
2321                 power_well->hw_enabled = power_well->ops->is_enabled(dev_priv,
2322                                                                      power_well);
2323         }
2324         mutex_unlock(&power_domains->lock);
2325 }
2326
2327 static void gen9_dbuf_enable(struct drm_i915_private *dev_priv)
2328 {
2329         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
2330         POSTING_READ(DBUF_CTL);
2331
2332         udelay(10);
2333
2334         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
2335                 DRM_ERROR("DBuf power enable timeout\n");
2336 }
2337
2338 static void gen9_dbuf_disable(struct drm_i915_private *dev_priv)
2339 {
2340         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
2341         POSTING_READ(DBUF_CTL);
2342
2343         udelay(10);
2344
2345         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
2346                 DRM_ERROR("DBuf power disable timeout!\n");
2347 }
2348
2349 static void skl_display_core_init(struct drm_i915_private *dev_priv,
2350                                    bool resume)
2351 {
2352         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2353         struct i915_power_well *well;
2354         uint32_t val;
2355
2356         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
2357
2358         /* enable PCH reset handshake */
2359         val = I915_READ(HSW_NDE_RSTWRN_OPT);
2360         I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
2361
2362         /* enable PG1 and Misc I/O */
2363         mutex_lock(&power_domains->lock);
2364
2365         well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
2366         intel_power_well_enable(dev_priv, well);
2367
2368         well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);
2369         intel_power_well_enable(dev_priv, well);
2370
2371         mutex_unlock(&power_domains->lock);
2372
2373         skl_init_cdclk(dev_priv);
2374
2375         gen9_dbuf_enable(dev_priv);
2376
2377         if (resume && dev_priv->csr.dmc_payload)
2378                 intel_csr_load_program(dev_priv);
2379 }
2380
2381 static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
2382 {
2383         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2384         struct i915_power_well *well;
2385
2386         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
2387
2388         gen9_dbuf_disable(dev_priv);
2389
2390         skl_uninit_cdclk(dev_priv);
2391
2392         /* The spec doesn't call for removing the reset handshake flag */
2393         /* disable PG1 and Misc I/O */
2394
2395         mutex_lock(&power_domains->lock);
2396
2397         well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);
2398         intel_power_well_disable(dev_priv, well);
2399
2400         well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
2401         intel_power_well_disable(dev_priv, well);
2402
2403         mutex_unlock(&power_domains->lock);
2404 }
2405
2406 void bxt_display_core_init(struct drm_i915_private *dev_priv,
2407                            bool resume)
2408 {
2409         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2410         struct i915_power_well *well;
2411         uint32_t val;
2412
2413         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
2414
2415         /*
2416          * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
2417          * or else the reset will hang because there is no PCH to respond.
2418          * Move the handshake programming to initialization sequence.
2419          * Previously was left up to BIOS.
2420          */
2421         val = I915_READ(HSW_NDE_RSTWRN_OPT);
2422         val &= ~RESET_PCH_HANDSHAKE_ENABLE;
2423         I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
2424
2425         /* Enable PG1 */
2426         mutex_lock(&power_domains->lock);
2427
2428         well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
2429         intel_power_well_enable(dev_priv, well);
2430
2431         mutex_unlock(&power_domains->lock);
2432
2433         bxt_init_cdclk(dev_priv);
2434
2435         gen9_dbuf_enable(dev_priv);
2436
2437         if (resume && dev_priv->csr.dmc_payload)
2438                 intel_csr_load_program(dev_priv);
2439 }
2440
2441 void bxt_display_core_uninit(struct drm_i915_private *dev_priv)
2442 {
2443         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2444         struct i915_power_well *well;
2445
2446         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
2447
2448         gen9_dbuf_disable(dev_priv);
2449
2450         bxt_uninit_cdclk(dev_priv);
2451
2452         /* The spec doesn't call for removing the reset handshake flag */
2453
2454         /* Disable PG1 */
2455         mutex_lock(&power_domains->lock);
2456
2457         well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
2458         intel_power_well_disable(dev_priv, well);
2459
2460         mutex_unlock(&power_domains->lock);
2461 }
2462
2463 static void chv_phy_control_init(struct drm_i915_private *dev_priv)
2464 {
2465         struct i915_power_well *cmn_bc =
2466                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
2467         struct i915_power_well *cmn_d =
2468                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D);
2469
2470         /*
2471          * DISPLAY_PHY_CONTROL can get corrupted if read. As a
2472          * workaround never ever read DISPLAY_PHY_CONTROL, and
2473          * instead maintain a shadow copy ourselves. Use the actual
2474          * power well state and lane status to reconstruct the
2475          * expected initial value.
2476          */
2477         dev_priv->chv_phy_control =
2478                 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY0) |
2479                 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY1) |
2480                 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH0) |
2481                 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH1) |
2482                 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY1, DPIO_CH0);
2483
2484         /*
2485          * If all lanes are disabled we leave the override disabled
2486          * with all power down bits cleared to match the state we
2487          * would use after disabling the port. Otherwise enable the
2488          * override and set the lane powerdown bits accding to the
2489          * current lane status.
2490          */
2491         if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) {
2492                 uint32_t status = I915_READ(DPLL(PIPE_A));
2493                 unsigned int mask;
2494
2495                 mask = status & DPLL_PORTB_READY_MASK;
2496                 if (mask == 0xf)
2497                         mask = 0x0;
2498                 else
2499                         dev_priv->chv_phy_control |=
2500                                 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0);
2501
2502                 dev_priv->chv_phy_control |=
2503                         PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH0);
2504
2505                 mask = (status & DPLL_PORTC_READY_MASK) >> 4;
2506                 if (mask == 0xf)
2507                         mask = 0x0;
2508                 else
2509                         dev_priv->chv_phy_control |=
2510                                 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1);
2511
2512                 dev_priv->chv_phy_control |=
2513                         PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH1);
2514
2515                 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0);
2516
2517                 dev_priv->chv_phy_assert[DPIO_PHY0] = false;
2518         } else {
2519                 dev_priv->chv_phy_assert[DPIO_PHY0] = true;
2520         }
2521
2522         if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) {
2523                 uint32_t status = I915_READ(DPIO_PHY_STATUS);
2524                 unsigned int mask;
2525
2526                 mask = status & DPLL_PORTD_READY_MASK;
2527
2528                 if (mask == 0xf)
2529                         mask = 0x0;
2530                 else
2531                         dev_priv->chv_phy_control |=
2532                                 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0);
2533
2534                 dev_priv->chv_phy_control |=
2535                         PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY1, DPIO_CH0);
2536
2537                 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1);
2538
2539                 dev_priv->chv_phy_assert[DPIO_PHY1] = false;
2540         } else {
2541                 dev_priv->chv_phy_assert[DPIO_PHY1] = true;
2542         }
2543
2544         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
2545
2546         DRM_DEBUG_KMS("Initial PHY_CONTROL=0x%08x\n",
2547                       dev_priv->chv_phy_control);
2548 }
2549
2550 static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv)
2551 {
2552         struct i915_power_well *cmn =
2553                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
2554         struct i915_power_well *disp2d =
2555                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D);
2556
2557         /* If the display might be already active skip this */
2558         if (cmn->ops->is_enabled(dev_priv, cmn) &&
2559             disp2d->ops->is_enabled(dev_priv, disp2d) &&
2560             I915_READ(DPIO_CTL) & DPIO_CMNRST)
2561                 return;
2562
2563         DRM_DEBUG_KMS("toggling display PHY side reset\n");
2564
2565         /* cmnlane needs DPLL registers */
2566         disp2d->ops->enable(dev_priv, disp2d);
2567
2568         /*
2569          * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx:
2570          * Need to assert and de-assert PHY SB reset by gating the
2571          * common lane power, then un-gating it.
2572          * Simply ungating isn't enough to reset the PHY enough to get
2573          * ports and lanes running.
2574          */
2575         cmn->ops->disable(dev_priv, cmn);
2576 }
2577
2578 /**
2579  * intel_power_domains_init_hw - initialize hardware power domain state
2580  * @dev_priv: i915 device instance
2581  * @resume: Called from resume code paths or not
2582  *
2583  * This function initializes the hardware power domain state and enables all
2584  * power domains using intel_display_set_init_power().
2585  */
2586 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume)
2587 {
2588         struct drm_device *dev = &dev_priv->drm;
2589         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2590
2591         power_domains->initializing = true;
2592
2593         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
2594                 skl_display_core_init(dev_priv, resume);
2595         } else if (IS_BROXTON(dev)) {
2596                 bxt_display_core_init(dev_priv, resume);
2597         } else if (IS_CHERRYVIEW(dev)) {
2598                 mutex_lock(&power_domains->lock);
2599                 chv_phy_control_init(dev_priv);
2600                 mutex_unlock(&power_domains->lock);
2601         } else if (IS_VALLEYVIEW(dev)) {
2602                 mutex_lock(&power_domains->lock);
2603                 vlv_cmnlane_wa(dev_priv);
2604                 mutex_unlock(&power_domains->lock);
2605         }
2606
2607         /* For now, we need the power well to be always enabled. */
2608         intel_display_set_init_power(dev_priv, true);
2609         /* Disable power support if the user asked so. */
2610         if (!i915.disable_power_well)
2611                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
2612         intel_power_domains_sync_hw(dev_priv);
2613         power_domains->initializing = false;
2614 }
2615
2616 /**
2617  * intel_power_domains_suspend - suspend power domain state
2618  * @dev_priv: i915 device instance
2619  *
2620  * This function prepares the hardware power domain state before entering
2621  * system suspend. It must be paired with intel_power_domains_init_hw().
2622  */
2623 void intel_power_domains_suspend(struct drm_i915_private *dev_priv)
2624 {
2625         /*
2626          * Even if power well support was disabled we still want to disable
2627          * power wells while we are system suspended.
2628          */
2629         if (!i915.disable_power_well)
2630                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
2631
2632         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
2633                 skl_display_core_uninit(dev_priv);
2634         else if (IS_BROXTON(dev_priv))
2635                 bxt_display_core_uninit(dev_priv);
2636 }
2637
2638 /**
2639  * intel_runtime_pm_get - grab a runtime pm reference
2640  * @dev_priv: i915 device instance
2641  *
2642  * This function grabs a device-level runtime pm reference (mostly used for GEM
2643  * code to ensure the GTT or GT is on) and ensures that it is powered up.
2644  *
2645  * Any runtime pm reference obtained by this function must have a symmetric
2646  * call to intel_runtime_pm_put() to release the reference again.
2647  */
2648 void intel_runtime_pm_get(struct drm_i915_private *dev_priv)
2649 {
2650         struct drm_device *dev = &dev_priv->drm;
2651         struct device *device = &dev->pdev->dev;
2652
2653         pm_runtime_get_sync(device);
2654
2655         atomic_inc(&dev_priv->pm.wakeref_count);
2656         assert_rpm_wakelock_held(dev_priv);
2657 }
2658
2659 /**
2660  * intel_runtime_pm_get_if_in_use - grab a runtime pm reference if device in use
2661  * @dev_priv: i915 device instance
2662  *
2663  * This function grabs a device-level runtime pm reference if the device is
2664  * already in use and ensures that it is powered up.
2665  *
2666  * Any runtime pm reference obtained by this function must have a symmetric
2667  * call to intel_runtime_pm_put() to release the reference again.
2668  */
2669 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv)
2670 {
2671         struct drm_device *dev = &dev_priv->drm;
2672         struct device *device = &dev->pdev->dev;
2673
2674         if (IS_ENABLED(CONFIG_PM)) {
2675                 int ret = pm_runtime_get_if_in_use(device);
2676
2677                 /*
2678                  * In cases runtime PM is disabled by the RPM core and we get
2679                  * an -EINVAL return value we are not supposed to call this
2680                  * function, since the power state is undefined. This applies
2681                  * atm to the late/early system suspend/resume handlers.
2682                  */
2683                 WARN_ON_ONCE(ret < 0);
2684                 if (ret <= 0)
2685                         return false;
2686         }
2687
2688         atomic_inc(&dev_priv->pm.wakeref_count);
2689         assert_rpm_wakelock_held(dev_priv);
2690
2691         return true;
2692 }
2693
2694 /**
2695  * intel_runtime_pm_get_noresume - grab a runtime pm reference
2696  * @dev_priv: i915 device instance
2697  *
2698  * This function grabs a device-level runtime pm reference (mostly used for GEM
2699  * code to ensure the GTT or GT is on).
2700  *
2701  * It will _not_ power up the device but instead only check that it's powered
2702  * on.  Therefore it is only valid to call this functions from contexts where
2703  * the device is known to be powered up and where trying to power it up would
2704  * result in hilarity and deadlocks. That pretty much means only the system
2705  * suspend/resume code where this is used to grab runtime pm references for
2706  * delayed setup down in work items.
2707  *
2708  * Any runtime pm reference obtained by this function must have a symmetric
2709  * call to intel_runtime_pm_put() to release the reference again.
2710  */
2711 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv)
2712 {
2713         struct drm_device *dev = &dev_priv->drm;
2714         struct device *device = &dev->pdev->dev;
2715
2716         assert_rpm_wakelock_held(dev_priv);
2717         pm_runtime_get_noresume(device);
2718
2719         atomic_inc(&dev_priv->pm.wakeref_count);
2720 }
2721
2722 /**
2723  * intel_runtime_pm_put - release a runtime pm reference
2724  * @dev_priv: i915 device instance
2725  *
2726  * This function drops the device-level runtime pm reference obtained by
2727  * intel_runtime_pm_get() and might power down the corresponding
2728  * hardware block right away if this is the last reference.
2729  */
2730 void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
2731 {
2732         struct drm_device *dev = &dev_priv->drm;
2733         struct device *device = &dev->pdev->dev;
2734
2735         assert_rpm_wakelock_held(dev_priv);
2736         if (atomic_dec_and_test(&dev_priv->pm.wakeref_count))
2737                 atomic_inc(&dev_priv->pm.atomic_seq);
2738
2739         pm_runtime_mark_last_busy(device);
2740         pm_runtime_put_autosuspend(device);
2741 }
2742
2743 /**
2744  * intel_runtime_pm_enable - enable runtime pm
2745  * @dev_priv: i915 device instance
2746  *
2747  * This function enables runtime pm at the end of the driver load sequence.
2748  *
2749  * Note that this function does currently not enable runtime pm for the
2750  * subordinate display power domains. That is only done on the first modeset
2751  * using intel_display_set_init_power().
2752  */
2753 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv)
2754 {
2755         struct drm_device *dev = &dev_priv->drm;
2756         struct device *device = &dev->pdev->dev;
2757
2758         pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */
2759         pm_runtime_mark_last_busy(device);
2760
2761         /*
2762          * Take a permanent reference to disable the RPM functionality and drop
2763          * it only when unloading the driver. Use the low level get/put helpers,
2764          * so the driver's own RPM reference tracking asserts also work on
2765          * platforms without RPM support.
2766          */
2767         if (!HAS_RUNTIME_PM(dev)) {
2768                 pm_runtime_dont_use_autosuspend(device);
2769                 pm_runtime_get_sync(device);
2770         } else {
2771                 pm_runtime_use_autosuspend(device);
2772         }
2773
2774         /*
2775          * The core calls the driver load handler with an RPM reference held.
2776          * We drop that here and will reacquire it during unloading in
2777          * intel_power_domains_fini().
2778          */
2779         pm_runtime_put_autosuspend(device);
2780 }
2781