drivers/gpu/drm/i915/intel_runtime_pm.c

   1 /*
   2  * Copyright © 2012-2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *    Daniel Vetter <daniel.vetter@ffwll.ch>
  26  *
  27  */
  28
  29 #include <linux/pm_runtime.h>
  30 #include <linux/vgaarb.h>
  31
  32 #include "i915_drv.h"
  33 #include "intel_drv.h"
  34
  35 /**
  36  * DOC: runtime pm
  37  *
  38  * The i915 driver supports dynamic enabling and disabling of entire hardware
  39  * blocks at runtime. This is especially important on the display side where
  40  * software is supposed to control many power gates manually on recent hardware,
  41  * since on the GT side a lot of the power management is done by the hardware.
  42  * But even there some manual control at the device level is required.
  43  *
  44  * Since i915 supports a diverse set of platforms with a unified codebase and
  45  * hardware engineers just love to shuffle functionality around between power
  46  * domains there's a sizeable amount of indirection required. This file provides
  47  * generic functions to the driver for grabbing and releasing references for
  48  * abstract power domains. It then maps those to the actual power wells
  49  * present for a given platform.
  50  */
  51
  52 #define for_each_power_well(i, power_well, domain_mask, power_domains)  \
  53         for (i = 0;                                                     \
  54              i < (power_domains)->power_well_count &&                   \
  55                  ((power_well) = &(power_domains)->power_wells[i]);     \
  56              i++)                                                       \
  57                 for_each_if ((power_well)->domains & (domain_mask))
  58
  59 #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
  60         for (i = (power_domains)->power_well_count - 1;                  \
  61              i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
  62              i--)                                                        \
  63                 for_each_if ((power_well)->domains & (domain_mask))
  64
  65 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
  66                                     int power_well_id);
  67
  68 static struct i915_power_well *
  69 lookup_power_well(struct drm_i915_private *dev_priv, int power_well_id);
  70
  71 const char *
  72 intel_display_power_domain_str(enum intel_display_power_domain domain)
  73 {
  74         switch (domain) {
  75         case POWER_DOMAIN_PIPE_A:
  76                 return "PIPE_A";
  77         case POWER_DOMAIN_PIPE_B:
  78                 return "PIPE_B";
  79         case POWER_DOMAIN_PIPE_C:
  80                 return "PIPE_C";
  81         case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
  82                 return "PIPE_A_PANEL_FITTER";
  83         case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
  84                 return "PIPE_B_PANEL_FITTER";
  85         case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
  86                 return "PIPE_C_PANEL_FITTER";
  87         case POWER_DOMAIN_TRANSCODER_A:
  88                 return "TRANSCODER_A";
  89         case POWER_DOMAIN_TRANSCODER_B:
  90                 return "TRANSCODER_B";
  91         case POWER_DOMAIN_TRANSCODER_C:
  92                 return "TRANSCODER_C";
  93         case POWER_DOMAIN_TRANSCODER_EDP:
  94                 return "TRANSCODER_EDP";
  95         case POWER_DOMAIN_TRANSCODER_DSI_A:
  96                 return "TRANSCODER_DSI_A";
  97         case POWER_DOMAIN_TRANSCODER_DSI_C:
  98                 return "TRANSCODER_DSI_C";
  99         case POWER_DOMAIN_PORT_DDI_A_LANES:
 100                 return "PORT_DDI_A_LANES";
 101         case POWER_DOMAIN_PORT_DDI_B_LANES:
 102                 return "PORT_DDI_B_LANES";
 103         case POWER_DOMAIN_PORT_DDI_C_LANES:
 104                 return "PORT_DDI_C_LANES";
 105         case POWER_DOMAIN_PORT_DDI_D_LANES:
 106                 return "PORT_DDI_D_LANES";
 107         case POWER_DOMAIN_PORT_DDI_E_LANES:
 108                 return "PORT_DDI_E_LANES";
 109         case POWER_DOMAIN_PORT_DSI:
 110                 return "PORT_DSI";
 111         case POWER_DOMAIN_PORT_CRT:
 112                 return "PORT_CRT";
 113         case POWER_DOMAIN_PORT_OTHER:
 114                 return "PORT_OTHER";
 115         case POWER_DOMAIN_VGA:
 116                 return "VGA";
 117         case POWER_DOMAIN_AUDIO:
 118                 return "AUDIO";
 119         case POWER_DOMAIN_PLLS:
 120                 return "PLLS";
 121         case POWER_DOMAIN_AUX_A:
 122                 return "AUX_A";
 123         case POWER_DOMAIN_AUX_B:
 124                 return "AUX_B";
 125         case POWER_DOMAIN_AUX_C:
 126                 return "AUX_C";
 127         case POWER_DOMAIN_AUX_D:
 128                 return "AUX_D";
 129         case POWER_DOMAIN_GMBUS:
 130                 return "GMBUS";
 131         case POWER_DOMAIN_INIT:
 132                 return "INIT";
 133         case POWER_DOMAIN_MODESET:
 134                 return "MODESET";
 135         default:
 136                 MISSING_CASE(domain);
 137                 return "?";
 138         }
 139 }
 140
 141 static void intel_power_well_enable(struct drm_i915_private *dev_priv,
 142                                     struct i915_power_well *power_well)
 143 {
 144         DRM_DEBUG_KMS("enabling %s\n", power_well->name);
 145         power_well->ops->enable(dev_priv, power_well);
 146         power_well->hw_enabled = true;
 147 }
 148
 149 static void intel_power_well_disable(struct drm_i915_private *dev_priv,
 150                                      struct i915_power_well *power_well)
 151 {
 152         DRM_DEBUG_KMS("disabling %s\n", power_well->name);
 153         power_well->hw_enabled = false;
 154         power_well->ops->disable(dev_priv, power_well);
 155 }
 156
 157 static void intel_power_well_get(struct drm_i915_private *dev_priv,
 158                                  struct i915_power_well *power_well)
 159 {
 160         if (!power_well->count++)
 161                 intel_power_well_enable(dev_priv, power_well);
 162 }
 163
 164 static void intel_power_well_put(struct drm_i915_private *dev_priv,
 165                                  struct i915_power_well *power_well)
 166 {
 167         WARN(!power_well->count, "Use count on power well %s is already zero",
 168              power_well->name);
 169
 170         if (!--power_well->count)
 171                 intel_power_well_disable(dev_priv, power_well);
 172 }
 173
 174 /*
 175  * We should only use the power well if we explicitly asked the hardware to
 176  * enable it, so check if it's enabled and also check if we've requested it to
 177  * be enabled.
 178  */
 179 static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
 180                                    struct i915_power_well *power_well)
 181 {
 182         return I915_READ(HSW_PWR_WELL_DRIVER) ==
 183                      (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
 184 }
 185
 186 /**
 187  * __intel_display_power_is_enabled - unlocked check for a power domain
 188  * @dev_priv: i915 device instance
 189  * @domain: power domain to check
 190  *
 191  * This is the unlocked version of intel_display_power_is_enabled() and should
 192  * only be used from error capture and recovery code where deadlocks are
 193  * possible.
 194  *
 195  * Returns:
 196  * True when the power domain is enabled, false otherwise.
 197  */
 198 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
 199                                       enum intel_display_power_domain domain)
 200 {
 201         struct i915_power_domains *power_domains;
 202         struct i915_power_well *power_well;
 203         bool is_enabled;
 204         int i;
 205
 206         if (dev_priv->pm.suspended)
 207                 return false;
 208
 209         power_domains = &dev_priv->power_domains;
 210
 211         is_enabled = true;
 212
 213         for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
 214                 if (power_well->always_on)
 215                         continue;
 216
 217                 if (!power_well->hw_enabled) {
 218                         is_enabled = false;
 219                         break;
 220                 }
 221         }
 222
 223         return is_enabled;
 224 }
 225
 226 /**
 227  * intel_display_power_is_enabled - check for a power domain
 228  * @dev_priv: i915 device instance
 229  * @domain: power domain to check
 230  *
 231  * This function can be used to check the hw power domain state. It is mostly
 232  * used in hardware state readout functions. Everywhere else code should rely
 233  * upon explicit power domain reference counting to ensure that the hardware
 234  * block is powered up before accessing it.
 235  *
 236  * Callers must hold the relevant modesetting locks to ensure that concurrent
 237  * threads can't disable the power well while the caller tries to read a few
 238  * registers.
 239  *
 240  * Returns:
 241  * True when the power domain is enabled, false otherwise.
 242  */
 243 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
 244                                     enum intel_display_power_domain domain)
 245 {
 246         struct i915_power_domains *power_domains;
 247         bool ret;
 248
 249         power_domains = &dev_priv->power_domains;
 250
 251         mutex_lock(&power_domains->lock);
 252         ret = __intel_display_power_is_enabled(dev_priv, domain);
 253         mutex_unlock(&power_domains->lock);
 254
 255         return ret;
 256 }
 257
 258 /**
 259  * intel_display_set_init_power - set the initial power domain state
 260  * @dev_priv: i915 device instance
 261  * @enable: whether to enable or disable the initial power domain state
 262  *
 263  * For simplicity our driver load/unload and system suspend/resume code assumes
 264  * that all power domains are always enabled. This functions controls the state
 265  * of this little hack. While the initial power domain state is enabled runtime
 266  * pm is effectively disabled.
 267  */
 268 void intel_display_set_init_power(struct drm_i915_private *dev_priv,
 269                                   bool enable)
 270 {
 271         if (dev_priv->power_domains.init_power_on == enable)
 272                 return;
 273
 274         if (enable)
 275                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
 276         else
 277                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
 278
 279         dev_priv->power_domains.init_power_on = enable;
 280 }
 281
 282 /*
 283  * Starting with Haswell, we have a "Power Down Well" that can be turned off
 284  * when not needed anymore. We have 4 registers that can request the power well
 285  * to be enabled, and it will only be disabled if none of the registers is
 286  * requesting it to be enabled.
 287  */
 288 static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
 289 {
 290         struct drm_device *dev = dev_priv->dev;
 291
 292         /*
 293          * After we re-enable the power well, if we touch VGA register 0x3d5
 294          * we'll get unclaimed register interrupts. This stops after we write
 295          * anything to the VGA MSR register. The vgacon module uses this
 296          * register all the time, so if we unbind our driver and, as a
 297          * consequence, bind vgacon, we'll get stuck in an infinite loop at
 298          * console_unlock(). So make here we touch the VGA MSR register, making
 299          * sure vgacon can keep working normally without triggering interrupts
 300          * and error messages.
 301          */
 302         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
 303         outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
 304         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
 305
 306         if (IS_BROADWELL(dev))
 307                 gen8_irq_power_well_post_enable(dev_priv,
 308                                                 1 << PIPE_C | 1 << PIPE_B);
 309 }
 310
 311 static void hsw_power_well_pre_disable(struct drm_i915_private *dev_priv)
 312 {
 313         if (IS_BROADWELL(dev_priv))
 314                 gen8_irq_power_well_pre_disable(dev_priv,
 315                                                 1 << PIPE_C | 1 << PIPE_B);
 316 }
 317
 318 static void skl_power_well_post_enable(struct drm_i915_private *dev_priv,
 319                                        struct i915_power_well *power_well)
 320 {
 321         struct drm_device *dev = dev_priv->dev;
 322
 323         /*
 324          * After we re-enable the power well, if we touch VGA register 0x3d5
 325          * we'll get unclaimed register interrupts. This stops after we write
 326          * anything to the VGA MSR register. The vgacon module uses this
 327          * register all the time, so if we unbind our driver and, as a
 328          * consequence, bind vgacon, we'll get stuck in an infinite loop at
 329          * console_unlock(). So make here we touch the VGA MSR register, making
 330          * sure vgacon can keep working normally without triggering interrupts
 331          * and error messages.
 332          */
 333         if (power_well->data == SKL_DISP_PW_2) {
 334                 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
 335                 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
 336                 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
 337
 338                 gen8_irq_power_well_post_enable(dev_priv,
 339                                                 1 << PIPE_C | 1 << PIPE_B);
 340         }
 341 }
 342
 343 static void skl_power_well_pre_disable(struct drm_i915_private *dev_priv,
 344                                        struct i915_power_well *power_well)
 345 {
 346         if (power_well->data == SKL_DISP_PW_2)
 347                 gen8_irq_power_well_pre_disable(dev_priv,
 348                                                 1 << PIPE_C | 1 << PIPE_B);
 349 }
 350
 351 static void hsw_set_power_well(struct drm_i915_private *dev_priv,
 352                                struct i915_power_well *power_well, bool enable)
 353 {
 354         bool is_enabled, enable_requested;
 355         uint32_t tmp;
 356
 357         tmp = I915_READ(HSW_PWR_WELL_DRIVER);
 358         is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
 359         enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
 360
 361         if (enable) {
 362                 if (!enable_requested)
 363                         I915_WRITE(HSW_PWR_WELL_DRIVER,
 364                                    HSW_PWR_WELL_ENABLE_REQUEST);
 365
 366                 if (!is_enabled) {
 367                         DRM_DEBUG_KMS("Enabling power well\n");
 368                         if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
 369                                       HSW_PWR_WELL_STATE_ENABLED), 20))
 370                                 DRM_ERROR("Timeout enabling power well\n");
 371                         hsw_power_well_post_enable(dev_priv);
 372                 }
 373
 374         } else {
 375                 if (enable_requested) {
 376                         hsw_power_well_pre_disable(dev_priv);
 377                         I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
 378                         POSTING_READ(HSW_PWR_WELL_DRIVER);
 379                         DRM_DEBUG_KMS("Requesting to disable the power well\n");
 380                 }
 381         }
 382 }
 383
 384 #define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS (         \
 385         BIT(POWER_DOMAIN_TRANSCODER_A) |                \
 386         BIT(POWER_DOMAIN_PIPE_B) |                      \
 387         BIT(POWER_DOMAIN_TRANSCODER_B) |                \
 388         BIT(POWER_DOMAIN_PIPE_C) |                      \
 389         BIT(POWER_DOMAIN_TRANSCODER_C) |                \
 390         BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |         \
 391         BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |         \
 392         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |            \
 393         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |            \
 394         BIT(POWER_DOMAIN_PORT_DDI_D_LANES) |            \
 395         BIT(POWER_DOMAIN_PORT_DDI_E_LANES) |            \
 396         BIT(POWER_DOMAIN_AUX_B) |                       \
 397         BIT(POWER_DOMAIN_AUX_C) |                       \
 398         BIT(POWER_DOMAIN_AUX_D) |                       \
 399         BIT(POWER_DOMAIN_AUDIO) |                       \
 400         BIT(POWER_DOMAIN_VGA) |                         \
 401         BIT(POWER_DOMAIN_INIT))
 402 #define SKL_DISPLAY_DDI_A_E_POWER_DOMAINS (             \
 403         BIT(POWER_DOMAIN_PORT_DDI_A_LANES) |            \
 404         BIT(POWER_DOMAIN_PORT_DDI_E_LANES) |            \
 405         BIT(POWER_DOMAIN_INIT))
 406 #define SKL_DISPLAY_DDI_B_POWER_DOMAINS (               \
 407         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |            \
 408         BIT(POWER_DOMAIN_INIT))
 409 #define SKL_DISPLAY_DDI_C_POWER_DOMAINS (               \
 410         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |            \
 411         BIT(POWER_DOMAIN_INIT))
 412 #define SKL_DISPLAY_DDI_D_POWER_DOMAINS (               \
 413         BIT(POWER_DOMAIN_PORT_DDI_D_LANES) |            \
 414         BIT(POWER_DOMAIN_INIT))
 415 #define SKL_DISPLAY_DC_OFF_POWER_DOMAINS (              \
 416         SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS |         \
 417         BIT(POWER_DOMAIN_MODESET) |                     \
 418         BIT(POWER_DOMAIN_AUX_A) |                       \
 419         BIT(POWER_DOMAIN_INIT))
 420
 421 #define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS (         \
 422         BIT(POWER_DOMAIN_TRANSCODER_A) |                \
 423         BIT(POWER_DOMAIN_PIPE_B) |                      \
 424         BIT(POWER_DOMAIN_TRANSCODER_B) |                \
 425         BIT(POWER_DOMAIN_PIPE_C) |                      \
 426         BIT(POWER_DOMAIN_TRANSCODER_C) |                \
 427         BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |         \
 428         BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |         \
 429         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |            \
 430         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |            \
 431         BIT(POWER_DOMAIN_AUX_B) |                       \
 432         BIT(POWER_DOMAIN_AUX_C) |                       \
 433         BIT(POWER_DOMAIN_AUDIO) |                       \
 434         BIT(POWER_DOMAIN_VGA) |                         \
 435         BIT(POWER_DOMAIN_GMBUS) |                       \
 436         BIT(POWER_DOMAIN_INIT))
 437 #define BXT_DISPLAY_DC_OFF_POWER_DOMAINS (              \
 438         BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS |         \
 439         BIT(POWER_DOMAIN_MODESET) |                     \
 440         BIT(POWER_DOMAIN_AUX_A) |                       \
 441         BIT(POWER_DOMAIN_INIT))
 442 #define BXT_DPIO_CMN_A_POWER_DOMAINS (                  \
 443         BIT(POWER_DOMAIN_PORT_DDI_A_LANES) |            \
 444         BIT(POWER_DOMAIN_AUX_A) |                       \
 445         BIT(POWER_DOMAIN_INIT))
 446 #define BXT_DPIO_CMN_BC_POWER_DOMAINS (                 \
 447         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |            \
 448         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |            \
 449         BIT(POWER_DOMAIN_AUX_B) |                       \
 450         BIT(POWER_DOMAIN_AUX_C) |                       \
 451         BIT(POWER_DOMAIN_INIT))
 452
 453 static void assert_can_enable_dc9(struct drm_i915_private *dev_priv)
 454 {
 455         WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9),
 456                   "DC9 already programmed to be enabled.\n");
 457         WARN_ONCE(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
 458                   "DC5 still not disabled to enable DC9.\n");
 459         WARN_ONCE(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on.\n");
 460         WARN_ONCE(intel_irqs_enabled(dev_priv),
 461                   "Interrupts not disabled yet.\n");
 462
 463          /*
 464           * TODO: check for the following to verify the conditions to enter DC9
 465           * state are satisfied:
 466           * 1] Check relevant display engine registers to verify if mode set
 467           * disable sequence was followed.
 468           * 2] Check if display uninitialize sequence is initialized.
 469           */
 470 }
 471
 472 static void assert_can_disable_dc9(struct drm_i915_private *dev_priv)
 473 {
 474         WARN_ONCE(intel_irqs_enabled(dev_priv),
 475                   "Interrupts not disabled yet.\n");
 476         WARN_ONCE(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
 477                   "DC5 still not disabled.\n");
 478
 479          /*
 480           * TODO: check for the following to verify DC9 state was indeed
 481           * entered before programming to disable it:
 482           * 1] Check relevant display engine registers to verify if mode
 483           *  set disable sequence was followed.
 484           * 2] Check if display uninitialize sequence is initialized.
 485           */
 486 }
 487
 488 static void gen9_write_dc_state(struct drm_i915_private *dev_priv,
 489                                 u32 state)
 490 {
 491         int rewrites = 0;
 492         int rereads = 0;
 493         u32 v;
 494
 495         I915_WRITE(DC_STATE_EN, state);
 496
 497         /* It has been observed that disabling the dc6 state sometimes
 498          * doesn't stick and dmc keeps returning old value. Make sure
 499          * the write really sticks enough times and also force rewrite until
 500          * we are confident that state is exactly what we want.
 501          */
 502         do  {
 503                 v = I915_READ(DC_STATE_EN);
 504
 505                 if (v != state) {
 506                         I915_WRITE(DC_STATE_EN, state);
 507                         rewrites++;
 508                         rereads = 0;
 509                 } else if (rereads++ > 5) {
 510                         break;
 511                 }
 512
 513         } while (rewrites < 100);
 514
 515         if (v != state)
 516                 DRM_ERROR("Writing dc state to 0x%x failed, now 0x%x\n",
 517                           state, v);
 518
 519         /* Most of the times we need one retry, avoid spam */
 520         if (rewrites > 1)
 521                 DRM_DEBUG_KMS("Rewrote dc state to 0x%x %d times\n",
 522                               state, rewrites);
 523 }
 524
 525 static u32 gen9_dc_mask(struct drm_i915_private *dev_priv)
 526 {
 527         u32 mask;
 528
 529         mask = DC_STATE_EN_UPTO_DC5;
 530         if (IS_BROXTON(dev_priv))
 531                 mask |= DC_STATE_EN_DC9;
 532         else
 533                 mask |= DC_STATE_EN_UPTO_DC6;
 534
 535         return mask;
 536 }
 537
 538 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv)
 539 {
 540         u32 val;
 541
 542         val = I915_READ(DC_STATE_EN) & gen9_dc_mask(dev_priv);
 543
 544         DRM_DEBUG_KMS("Resetting DC state tracking from %02x to %02x\n",
 545                       dev_priv->csr.dc_state, val);
 546         dev_priv->csr.dc_state = val;
 547 }
 548
 549 static void gen9_set_dc_state(struct drm_i915_private *dev_priv, uint32_t state)
 550 {
 551         uint32_t val;
 552         uint32_t mask;
 553
 554         if (WARN_ON_ONCE(state & ~dev_priv->csr.allowed_dc_mask))
 555                 state &= dev_priv->csr.allowed_dc_mask;
 556
 557         val = I915_READ(DC_STATE_EN);
 558         mask = gen9_dc_mask(dev_priv);
 559         DRM_DEBUG_KMS("Setting DC state from %02x to %02x\n",
 560                       val & mask, state);
 561
 562         /* Check if DMC is ignoring our DC state requests */
 563         if ((val & mask) != dev_priv->csr.dc_state)
 564                 DRM_ERROR("DC state mismatch (0x%x -> 0x%x)\n",
 565                           dev_priv->csr.dc_state, val & mask);
 566
 567         val &= ~mask;
 568         val |= state;
 569
 570         gen9_write_dc_state(dev_priv, val);
 571
 572         dev_priv->csr.dc_state = val & mask;
 573 }
 574
 575 void bxt_enable_dc9(struct drm_i915_private *dev_priv)
 576 {
 577         assert_can_enable_dc9(dev_priv);
 578
 579         DRM_DEBUG_KMS("Enabling DC9\n");
 580
 581         intel_power_sequencer_reset(dev_priv);
 582         gen9_set_dc_state(dev_priv, DC_STATE_EN_DC9);
 583 }
 584
 585 void bxt_disable_dc9(struct drm_i915_private *dev_priv)
 586 {
 587         assert_can_disable_dc9(dev_priv);
 588
 589         DRM_DEBUG_KMS("Disabling DC9\n");
 590
 591         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 592 }
 593
 594 static void assert_csr_loaded(struct drm_i915_private *dev_priv)
 595 {
 596         WARN_ONCE(!I915_READ(CSR_PROGRAM(0)),
 597                   "CSR program storage start is NULL\n");
 598         WARN_ONCE(!I915_READ(CSR_SSP_BASE), "CSR SSP Base Not fine\n");
 599         WARN_ONCE(!I915_READ(CSR_HTP_SKL), "CSR HTP Not fine\n");
 600 }
 601
 602 static void assert_can_enable_dc5(struct drm_i915_private *dev_priv)
 603 {
 604         bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv,
 605                                         SKL_DISP_PW_2);
 606
 607         WARN_ONCE(pg2_enabled, "PG2 not disabled to enable DC5.\n");
 608
 609         WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5),
 610                   "DC5 already programmed to be enabled.\n");
 611         assert_rpm_wakelock_held(dev_priv);
 612
 613         assert_csr_loaded(dev_priv);
 614 }
 615
 616 void gen9_enable_dc5(struct drm_i915_private *dev_priv)
 617 {
 618         assert_can_enable_dc5(dev_priv);
 619
 620         DRM_DEBUG_KMS("Enabling DC5\n");
 621
 622         gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5);
 623 }
 624
 625 static void assert_can_enable_dc6(struct drm_i915_private *dev_priv)
 626 {
 627         WARN_ONCE(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
 628                   "Backlight is not disabled.\n");
 629         WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6),
 630                   "DC6 already programmed to be enabled.\n");
 631
 632         assert_csr_loaded(dev_priv);
 633 }
 634
 635 void skl_enable_dc6(struct drm_i915_private *dev_priv)
 636 {
 637         assert_can_enable_dc6(dev_priv);
 638
 639         DRM_DEBUG_KMS("Enabling DC6\n");
 640
 641         gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
 642
 643 }
 644
 645 void skl_disable_dc6(struct drm_i915_private *dev_priv)
 646 {
 647         DRM_DEBUG_KMS("Disabling DC6\n");
 648
 649         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 650 }
 651
 652 static void
 653 gen9_sanitize_power_well_requests(struct drm_i915_private *dev_priv,
 654                                   struct i915_power_well *power_well)
 655 {
 656         enum skl_disp_power_wells power_well_id = power_well->data;
 657         u32 val;
 658         u32 mask;
 659
 660         mask = SKL_POWER_WELL_REQ(power_well_id);
 661
 662         val = I915_READ(HSW_PWR_WELL_KVMR);
 663         if (WARN_ONCE(val & mask, "Clearing unexpected KVMR request for %s\n",
 664                       power_well->name))
 665                 I915_WRITE(HSW_PWR_WELL_KVMR, val & ~mask);
 666
 667         val = I915_READ(HSW_PWR_WELL_BIOS);
 668         val |= I915_READ(HSW_PWR_WELL_DEBUG);
 669
 670         if (!(val & mask))
 671                 return;
 672
 673         /*
 674          * DMC is known to force on the request bits for power well 1 on SKL
 675          * and BXT and the misc IO power well on SKL but we don't expect any
 676          * other request bits to be set, so WARN for those.
 677          */
 678         if (power_well_id == SKL_DISP_PW_1 ||
 679             ((IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) &&
 680              power_well_id == SKL_DISP_PW_MISC_IO))
 681                 DRM_DEBUG_DRIVER("Clearing auxiliary requests for %s forced on "
 682                                  "by DMC\n", power_well->name);
 683         else
 684                 WARN_ONCE(1, "Clearing unexpected auxiliary requests for %s\n",
 685                           power_well->name);
 686
 687         I915_WRITE(HSW_PWR_WELL_BIOS, val & ~mask);
 688         I915_WRITE(HSW_PWR_WELL_DEBUG, val & ~mask);
 689 }
 690
 691 static void skl_set_power_well(struct drm_i915_private *dev_priv,
 692                         struct i915_power_well *power_well, bool enable)
 693 {
 694         uint32_t tmp, fuse_status;
 695         uint32_t req_mask, state_mask;
 696         bool is_enabled, enable_requested, check_fuse_status = false;
 697
 698         tmp = I915_READ(HSW_PWR_WELL_DRIVER);
 699         fuse_status = I915_READ(SKL_FUSE_STATUS);
 700
 701         switch (power_well->data) {
 702         case SKL_DISP_PW_1:
 703                 if (wait_for((I915_READ(SKL_FUSE_STATUS) &
 704                         SKL_FUSE_PG0_DIST_STATUS), 1)) {
 705                         DRM_ERROR("PG0 not enabled\n");
 706                         return;
 707                 }
 708                 break;
 709         case SKL_DISP_PW_2:
 710                 if (!(fuse_status & SKL_FUSE_PG1_DIST_STATUS)) {
 711                         DRM_ERROR("PG1 in disabled state\n");
 712                         return;
 713                 }
 714                 break;
 715         case SKL_DISP_PW_DDI_A_E:
 716         case SKL_DISP_PW_DDI_B:
 717         case SKL_DISP_PW_DDI_C:
 718         case SKL_DISP_PW_DDI_D:
 719         case SKL_DISP_PW_MISC_IO:
 720                 break;
 721         default:
 722                 WARN(1, "Unknown power well %lu\n", power_well->data);
 723                 return;
 724         }
 725
 726         req_mask = SKL_POWER_WELL_REQ(power_well->data);
 727         enable_requested = tmp & req_mask;
 728         state_mask = SKL_POWER_WELL_STATE(power_well->data);
 729         is_enabled = tmp & state_mask;
 730
 731         if (!enable && enable_requested)
 732                 skl_power_well_pre_disable(dev_priv, power_well);
 733
 734         if (enable) {
 735                 if (!enable_requested) {
 736                         WARN((tmp & state_mask) &&
 737                                 !I915_READ(HSW_PWR_WELL_BIOS),
 738                                 "Invalid for power well status to be enabled, unless done by the BIOS, \
 739                                 when request is to disable!\n");
 740                         I915_WRITE(HSW_PWR_WELL_DRIVER, tmp | req_mask);
 741                 }
 742
 743                 if (!is_enabled) {
 744                         DRM_DEBUG_KMS("Enabling %s\n", power_well->name);
 745                         check_fuse_status = true;
 746                 }
 747         } else {
 748                 if (enable_requested) {
 749                         I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask);
 750                         POSTING_READ(HSW_PWR_WELL_DRIVER);
 751                         DRM_DEBUG_KMS("Disabling %s\n", power_well->name);
 752                 }
 753
 754                 if (IS_GEN9(dev_priv))
 755                         gen9_sanitize_power_well_requests(dev_priv, power_well);
 756         }
 757
 758         if (wait_for(!!(I915_READ(HSW_PWR_WELL_DRIVER) & state_mask) == enable,
 759                      1))
 760                 DRM_ERROR("%s %s timeout\n",
 761                           power_well->name, enable ? "enable" : "disable");
 762
 763         if (check_fuse_status) {
 764                 if (power_well->data == SKL_DISP_PW_1) {
 765                         if (wait_for((I915_READ(SKL_FUSE_STATUS) &
 766                                 SKL_FUSE_PG1_DIST_STATUS), 1))
 767                                 DRM_ERROR("PG1 distributing status timeout\n");
 768                 } else if (power_well->data == SKL_DISP_PW_2) {
 769                         if (wait_for((I915_READ(SKL_FUSE_STATUS) &
 770                                 SKL_FUSE_PG2_DIST_STATUS), 1))
 771                                 DRM_ERROR("PG2 distributing status timeout\n");
 772                 }
 773         }
 774
 775         if (enable && !is_enabled)
 776                 skl_power_well_post_enable(dev_priv, power_well);
 777 }
 778
 779 static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
 780                                    struct i915_power_well *power_well)
 781 {
 782         hsw_set_power_well(dev_priv, power_well, power_well->count > 0);
 783
 784         /*
 785          * We're taking over the BIOS, so clear any requests made by it since
 786          * the driver is in charge now.
 787          */
 788         if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
 789                 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
 790 }
 791
 792 static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
 793                                   struct i915_power_well *power_well)
 794 {
 795         hsw_set_power_well(dev_priv, power_well, true);
 796 }
 797
 798 static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
 799                                    struct i915_power_well *power_well)
 800 {
 801         hsw_set_power_well(dev_priv, power_well, false);
 802 }
 803
 804 static bool skl_power_well_enabled(struct drm_i915_private *dev_priv,
 805                                         struct i915_power_well *power_well)
 806 {
 807         uint32_t mask = SKL_POWER_WELL_REQ(power_well->data) |
 808                 SKL_POWER_WELL_STATE(power_well->data);
 809
 810         return (I915_READ(HSW_PWR_WELL_DRIVER) & mask) == mask;
 811 }
 812
 813 static void skl_power_well_sync_hw(struct drm_i915_private *dev_priv,
 814                                 struct i915_power_well *power_well)
 815 {
 816         skl_set_power_well(dev_priv, power_well, power_well->count > 0);
 817
 818         /* Clear any request made by BIOS as driver is taking over */
 819         I915_WRITE(HSW_PWR_WELL_BIOS, 0);
 820 }
 821
 822 static void skl_power_well_enable(struct drm_i915_private *dev_priv,
 823                                 struct i915_power_well *power_well)
 824 {
 825         skl_set_power_well(dev_priv, power_well, true);
 826 }
 827
 828 static void skl_power_well_disable(struct drm_i915_private *dev_priv,
 829                                 struct i915_power_well *power_well)
 830 {
 831         skl_set_power_well(dev_priv, power_well, false);
 832 }
 833
 834 static enum dpio_phy bxt_power_well_to_phy(struct i915_power_well *power_well)
 835 {
 836         enum skl_disp_power_wells power_well_id = power_well->data;
 837
 838         return power_well_id == BXT_DPIO_CMN_A ? DPIO_PHY1 : DPIO_PHY0;
 839 }
 840
 841 static void bxt_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
 842                                            struct i915_power_well *power_well)
 843 {
 844         enum skl_disp_power_wells power_well_id = power_well->data;
 845         struct i915_power_well *cmn_a_well;
 846
 847         if (power_well_id == BXT_DPIO_CMN_BC) {
 848                 /*
 849                  * We need to copy the GRC calibration value from the eDP PHY,
 850                  * so make sure it's powered up.
 851                  */
 852                 cmn_a_well = lookup_power_well(dev_priv, BXT_DPIO_CMN_A);
 853                 intel_power_well_get(dev_priv, cmn_a_well);
 854         }
 855
 856         bxt_ddi_phy_init(dev_priv, bxt_power_well_to_phy(power_well));
 857
 858         if (power_well_id == BXT_DPIO_CMN_BC)
 859                 intel_power_well_put(dev_priv, cmn_a_well);
 860 }
 861
 862 static void bxt_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
 863                                             struct i915_power_well *power_well)
 864 {
 865         bxt_ddi_phy_uninit(dev_priv, bxt_power_well_to_phy(power_well));
 866 }
 867
 868 static bool bxt_dpio_cmn_power_well_enabled(struct drm_i915_private *dev_priv,
 869                                             struct i915_power_well *power_well)
 870 {
 871         return bxt_ddi_phy_is_enabled(dev_priv,
 872                                       bxt_power_well_to_phy(power_well));
 873 }
 874
 875 static void bxt_dpio_cmn_power_well_sync_hw(struct drm_i915_private *dev_priv,
 876                                             struct i915_power_well *power_well)
 877 {
 878         if (power_well->count > 0)
 879                 bxt_dpio_cmn_power_well_enable(dev_priv, power_well);
 880         else
 881                 bxt_dpio_cmn_power_well_disable(dev_priv, power_well);
 882 }
 883
 884
 885 static void bxt_verify_ddi_phy_power_wells(struct drm_i915_private *dev_priv)
 886 {
 887         struct i915_power_well *power_well;
 888
 889         power_well = lookup_power_well(dev_priv, BXT_DPIO_CMN_A);
 890         if (power_well->count > 0)
 891                 bxt_ddi_phy_verify_state(dev_priv,
 892                                          bxt_power_well_to_phy(power_well));
 893
 894         power_well = lookup_power_well(dev_priv, BXT_DPIO_CMN_BC);
 895         if (power_well->count > 0)
 896                 bxt_ddi_phy_verify_state(dev_priv,
 897                                          bxt_power_well_to_phy(power_well));
 898 }
 899
 900 static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv,
 901                                            struct i915_power_well *power_well)
 902 {
 903         return (I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0;
 904 }
 905
 906 static void gen9_assert_dbuf_enabled(struct drm_i915_private *dev_priv)
 907 {
 908         u32 tmp = I915_READ(DBUF_CTL);
 909
 910         WARN((tmp & (DBUF_POWER_STATE | DBUF_POWER_REQUEST)) !=
 911              (DBUF_POWER_STATE | DBUF_POWER_REQUEST),
 912              "Unexpected DBuf power power state (0x%08x)\n", tmp);
 913 }
 914
 915 static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
 916                                           struct i915_power_well *power_well)
 917 {
 918         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 919
 920         WARN_ON(dev_priv->cdclk_freq !=
 921                 dev_priv->display.get_display_clock_speed(dev_priv->dev));
 922
 923         gen9_assert_dbuf_enabled(dev_priv);
 924
 925         if (IS_BROXTON(dev_priv))
 926                 bxt_verify_ddi_phy_power_wells(dev_priv);
 927 }
 928
 929 static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
 930                                            struct i915_power_well *power_well)
 931 {
 932         if (!dev_priv->csr.dmc_payload)
 933                 return;
 934
 935         if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC6)
 936                 skl_enable_dc6(dev_priv);
 937         else if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5)
 938                 gen9_enable_dc5(dev_priv);
 939 }
 940
 941 static void gen9_dc_off_power_well_sync_hw(struct drm_i915_private *dev_priv,
 942                                            struct i915_power_well *power_well)
 943 {
 944         if (power_well->count > 0)
 945                 gen9_dc_off_power_well_enable(dev_priv, power_well);
 946         else
 947                 gen9_dc_off_power_well_disable(dev_priv, power_well);
 948 }
 949
 950 static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,
 951                                            struct i915_power_well *power_well)
 952 {
 953 }
 954
 955 static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,
 956                                              struct i915_power_well *power_well)
 957 {
 958         return true;
 959 }
 960
 961 static void vlv_set_power_well(struct drm_i915_private *dev_priv,
 962                                struct i915_power_well *power_well, bool enable)
 963 {
 964         enum punit_power_well power_well_id = power_well->data;
 965         u32 mask;
 966         u32 state;
 967         u32 ctrl;
 968
 969         mask = PUNIT_PWRGT_MASK(power_well_id);
 970         state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) :
 971                          PUNIT_PWRGT_PWR_GATE(power_well_id);
 972
 973         mutex_lock(&dev_priv->rps.hw_lock);
 974
 975 #define COND \
 976         ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)
 977
 978         if (COND)
 979                 goto out;
 980
 981         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL);
 982         ctrl &= ~mask;
 983         ctrl |= state;
 984         vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl);
 985
 986         if (wait_for(COND, 100))
 987                 DRM_ERROR("timeout setting power well state %08x (%08x)\n",
 988                           state,
 989                           vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL));
 990
 991 #undef COND
 992
 993 out:
 994         mutex_unlock(&dev_priv->rps.hw_lock);
 995 }
 996
 997 static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv,
 998                                    struct i915_power_well *power_well)
 999 {
1000         vlv_set_power_well(dev_priv, power_well, power_well->count > 0);
1001 }
1002
1003 static void vlv_power_well_enable(struct drm_i915_private *dev_priv,
1004                                   struct i915_power_well *power_well)
1005 {
1006         vlv_set_power_well(dev_priv, power_well, true);
1007 }
1008
1009 static void vlv_power_well_disable(struct drm_i915_private *dev_priv,
1010                                    struct i915_power_well *power_well)
1011 {
1012         vlv_set_power_well(dev_priv, power_well, false);
1013 }
1014
1015 static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
1016                                    struct i915_power_well *power_well)
1017 {
1018         int power_well_id = power_well->data;
1019         bool enabled = false;
1020         u32 mask;
1021         u32 state;
1022         u32 ctrl;
1023
1024         mask = PUNIT_PWRGT_MASK(power_well_id);
1025         ctrl = PUNIT_PWRGT_PWR_ON(power_well_id);
1026
1027         mutex_lock(&dev_priv->rps.hw_lock);
1028
1029         state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask;
1030         /*
1031          * We only ever set the power-on and power-gate states, anything
1032          * else is unexpected.
1033          */
1034         WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) &&
1035                 state != PUNIT_PWRGT_PWR_GATE(power_well_id));
1036         if (state == ctrl)
1037                 enabled = true;
1038
1039         /*
1040          * A transient state at this point would mean some unexpected party
1041          * is poking at the power controls too.
1042          */
1043         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask;
1044         WARN_ON(ctrl != state);
1045
1046         mutex_unlock(&dev_priv->rps.hw_lock);
1047
1048         return enabled;
1049 }
1050
1051 static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
1052 {
1053         I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
1054
1055         /*
1056          * Disable trickle feed and enable pnd deadline calculation
1057          */
1058         I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
1059         I915_WRITE(CBR1_VLV, 0);
1060
1061         WARN_ON(dev_priv->rawclk_freq == 0);
1062
1063         I915_WRITE(RAWCLK_FREQ_VLV,
1064                    DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 1000));
1065 }
1066
1067 static void vlv_display_power_well_init(struct drm_i915_private *dev_priv)
1068 {
1069         enum pipe pipe;
1070
1071         /*
1072          * Enable the CRI clock source so we can get at the
1073          * display and the reference clock for VGA
1074          * hotplug / manual detection. Supposedly DSI also
1075          * needs the ref clock up and running.
1076          *
1077          * CHV DPLL B/C have some issues if VGA mode is enabled.
1078          */
1079         for_each_pipe(dev_priv->dev, pipe) {
1080                 u32 val = I915_READ(DPLL(pipe));
1081
1082                 val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1083                 if (pipe != PIPE_A)
1084                         val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1085
1086                 I915_WRITE(DPLL(pipe), val);
1087         }
1088
1089         vlv_init_display_clock_gating(dev_priv);
1090
1091         spin_lock_irq(&dev_priv->irq_lock);
1092         valleyview_enable_display_irqs(dev_priv);
1093         spin_unlock_irq(&dev_priv->irq_lock);
1094
1095         /*
1096          * During driver initialization/resume we can avoid restoring the
1097          * part of the HW/SW state that will be inited anyway explicitly.
1098          */
1099         if (dev_priv->power_domains.initializing)
1100                 return;
1101
1102         intel_hpd_init(dev_priv);
1103
1104         i915_redisable_vga_power_on(dev_priv->dev);
1105 }
1106
1107 static void vlv_display_power_well_deinit(struct drm_i915_private *dev_priv)
1108 {
1109         spin_lock_irq(&dev_priv->irq_lock);
1110         valleyview_disable_display_irqs(dev_priv);
1111         spin_unlock_irq(&dev_priv->irq_lock);
1112
1113         /* make sure we're done processing display irqs */
1114         synchronize_irq(dev_priv->dev->irq);
1115
1116         intel_power_sequencer_reset(dev_priv);
1117 }
1118
1119 static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv,
1120                                           struct i915_power_well *power_well)
1121 {
1122         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
1123
1124         vlv_set_power_well(dev_priv, power_well, true);
1125
1126         vlv_display_power_well_init(dev_priv);
1127 }
1128
1129 static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv,
1130                                            struct i915_power_well *power_well)
1131 {
1132         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
1133
1134         vlv_display_power_well_deinit(dev_priv);
1135
1136         vlv_set_power_well(dev_priv, power_well, false);
1137 }
1138
1139 static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
1140                                            struct i915_power_well *power_well)
1141 {
1142         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
1143
1144         /* since ref/cri clock was enabled */
1145         udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
1146
1147         vlv_set_power_well(dev_priv, power_well, true);
1148
1149         /*
1150          * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1151          *  6.  De-assert cmn_reset/side_reset. Same as VLV X0.
1152          *   a. GUnit 0x2110 bit[0] set to 1 (def 0)
1153          *   b. The other bits such as sfr settings / modesel may all
1154          *      be set to 0.
1155          *
1156          * This should only be done on init and resume from S3 with
1157          * both PLLs disabled, or we risk losing DPIO and PLL
1158          * synchronization.
1159          */
1160         I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
1161 }
1162
1163 static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
1164                                             struct i915_power_well *power_well)
1165 {
1166         enum pipe pipe;
1167
1168         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
1169
1170         for_each_pipe(dev_priv, pipe)
1171                 assert_pll_disabled(dev_priv, pipe);
1172
1173         /* Assert common reset */
1174         I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST);
1175
1176         vlv_set_power_well(dev_priv, power_well, false);
1177 }
1178
1179 #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
1180
1181 static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv,
1182                                                  int power_well_id)
1183 {
1184         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1185         int i;
1186
1187         for (i = 0; i < power_domains->power_well_count; i++) {
1188                 struct i915_power_well *power_well;
1189
1190                 power_well = &power_domains->power_wells[i];
1191                 if (power_well->data == power_well_id)
1192                         return power_well;
1193         }
1194
1195         return NULL;
1196 }
1197
1198 #define BITS_SET(val, bits) (((val) & (bits)) == (bits))
1199
1200 static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
1201 {
1202         struct i915_power_well *cmn_bc =
1203                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
1204         struct i915_power_well *cmn_d =
1205                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D);
1206         u32 phy_control = dev_priv->chv_phy_control;
1207         u32 phy_status = 0;
1208         u32 phy_status_mask = 0xffffffff;
1209         u32 tmp;
1210
1211         /*
1212          * The BIOS can leave the PHY is some weird state
1213          * where it doesn't fully power down some parts.
1214          * Disable the asserts until the PHY has been fully
1215          * reset (ie. the power well has been disabled at
1216          * least once).
1217          */
1218         if (!dev_priv->chv_phy_assert[DPIO_PHY0])
1219                 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0) |
1220                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0) |
1221                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1) |
1222                                      PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1) |
1223                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0) |
1224                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1));
1225
1226         if (!dev_priv->chv_phy_assert[DPIO_PHY1])
1227                 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0) |
1228                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0) |
1229                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1));
1230
1231         if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) {
1232                 phy_status |= PHY_POWERGOOD(DPIO_PHY0);
1233
1234                 /* this assumes override is only used to enable lanes */
1235                 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0)) == 0)
1236                         phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0);
1237
1238                 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1)) == 0)
1239                         phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1);
1240
1241                 /* CL1 is on whenever anything is on in either channel */
1242                 if (BITS_SET(phy_control,
1243                              PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0) |
1244                              PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)))
1245                         phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0);
1246
1247                 /*
1248                  * The DPLLB check accounts for the pipe B + port A usage
1249                  * with CL2 powered up but all the lanes in the second channel
1250                  * powered down.
1251                  */
1252                 if (BITS_SET(phy_control,
1253                              PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)) &&
1254                     (I915_READ(DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0)
1255                         phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1);
1256
1257                 if (BITS_SET(phy_control,
1258                              PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH0)))
1259                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0);
1260                 if (BITS_SET(phy_control,
1261                              PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH0)))
1262                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1);
1263
1264                 if (BITS_SET(phy_control,
1265                              PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH1)))
1266                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0);
1267                 if (BITS_SET(phy_control,
1268                              PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH1)))
1269                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1);
1270         }
1271
1272         if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) {
1273                 phy_status |= PHY_POWERGOOD(DPIO_PHY1);
1274
1275                 /* this assumes override is only used to enable lanes */
1276                 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0)) == 0)
1277                         phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0);
1278
1279                 if (BITS_SET(phy_control,
1280                              PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0)))
1281                         phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0);
1282
1283                 if (BITS_SET(phy_control,
1284                              PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY1, DPIO_CH0)))
1285                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0);
1286                 if (BITS_SET(phy_control,
1287                              PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY1, DPIO_CH0)))
1288                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1);
1289         }
1290
1291         phy_status &= phy_status_mask;
1292
1293         /*
1294          * The PHY may be busy with some initial calibration and whatnot,
1295          * so the power state can take a while to actually change.
1296          */
1297         if (wait_for((tmp = I915_READ(DISPLAY_PHY_STATUS) & phy_status_mask) == phy_status, 10))
1298                 WARN(phy_status != tmp,
1299                      "Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n",
1300                      tmp, phy_status, dev_priv->chv_phy_control);
1301 }
1302
1303 #undef BITS_SET
1304
1305 static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
1306                                            struct i915_power_well *power_well)
1307 {
1308         enum dpio_phy phy;
1309         enum pipe pipe;
1310         uint32_t tmp;
1311
1312         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
1313                      power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
1314
1315         if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
1316                 pipe = PIPE_A;
1317                 phy = DPIO_PHY0;
1318         } else {
1319                 pipe = PIPE_C;
1320                 phy = DPIO_PHY1;
1321         }
1322
1323         /* since ref/cri clock was enabled */
1324         udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
1325         vlv_set_power_well(dev_priv, power_well, true);
1326
1327         /* Poll for phypwrgood signal */
1328         if (wait_for(I915_READ(DISPLAY_PHY_STATUS) & PHY_POWERGOOD(phy), 1))
1329                 DRM_ERROR("Display PHY %d is not power up\n", phy);
1330
1331         mutex_lock(&dev_priv->sb_lock);
1332
1333         /* Enable dynamic power down */
1334         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW28);
1335         tmp |= DPIO_DYNPWRDOWNEN_CH0 | DPIO_CL1POWERDOWNEN |
1336                 DPIO_SUS_CLK_CONFIG_GATE_CLKREQ;
1337         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW28, tmp);
1338
1339         if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
1340                 tmp = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW6_CH1);
1341                 tmp |= DPIO_DYNPWRDOWNEN_CH1;
1342                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW6_CH1, tmp);
1343         } else {
1344                 /*
1345                  * Force the non-existing CL2 off. BXT does this
1346                  * too, so maybe it saves some power even though
1347                  * CL2 doesn't exist?
1348                  */
1349                 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
1350                 tmp |= DPIO_CL2_LDOFUSE_PWRENB;
1351                 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, tmp);
1352         }
1353
1354         mutex_unlock(&dev_priv->sb_lock);
1355
1356         dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy);
1357         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1358
1359         DRM_DEBUG_KMS("Enabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
1360                       phy, dev_priv->chv_phy_control);
1361
1362         assert_chv_phy_status(dev_priv);
1363 }
1364
1365 static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
1366                                             struct i915_power_well *power_well)
1367 {
1368         enum dpio_phy phy;
1369
1370         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
1371                      power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
1372
1373         if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
1374                 phy = DPIO_PHY0;
1375                 assert_pll_disabled(dev_priv, PIPE_A);
1376                 assert_pll_disabled(dev_priv, PIPE_B);
1377         } else {
1378                 phy = DPIO_PHY1;
1379                 assert_pll_disabled(dev_priv, PIPE_C);
1380         }
1381
1382         dev_priv->chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy);
1383         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1384
1385         vlv_set_power_well(dev_priv, power_well, false);
1386
1387         DRM_DEBUG_KMS("Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
1388                       phy, dev_priv->chv_phy_control);
1389
1390         /* PHY is fully reset now, so we can enable the PHY state asserts */
1391         dev_priv->chv_phy_assert[phy] = true;
1392
1393         assert_chv_phy_status(dev_priv);
1394 }
1395
1396 static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1397                                      enum dpio_channel ch, bool override, unsigned int mask)
1398 {
1399         enum pipe pipe = phy == DPIO_PHY0 ? PIPE_A : PIPE_C;
1400         u32 reg, val, expected, actual;
1401
1402         /*
1403          * The BIOS can leave the PHY is some weird state
1404          * where it doesn't fully power down some parts.
1405          * Disable the asserts until the PHY has been fully
1406          * reset (ie. the power well has been disabled at
1407          * least once).
1408          */
1409         if (!dev_priv->chv_phy_assert[phy])
1410                 return;
1411
1412         if (ch == DPIO_CH0)
1413                 reg = _CHV_CMN_DW0_CH0;
1414         else
1415                 reg = _CHV_CMN_DW6_CH1;
1416
1417         mutex_lock(&dev_priv->sb_lock);
1418         val = vlv_dpio_read(dev_priv, pipe, reg);
1419         mutex_unlock(&dev_priv->sb_lock);
1420
1421         /*
1422          * This assumes !override is only used when the port is disabled.
1423          * All lanes should power down even without the override when
1424          * the port is disabled.
1425          */
1426         if (!override || mask == 0xf) {
1427                 expected = DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN;
1428                 /*
1429                  * If CH1 common lane is not active anymore
1430                  * (eg. for pipe B DPLL) the entire channel will
1431                  * shut down, which causes the common lane registers
1432                  * to read as 0. That means we can't actually check
1433                  * the lane power down status bits, but as the entire
1434                  * register reads as 0 it's a good indication that the
1435                  * channel is indeed entirely powered down.
1436                  */
1437                 if (ch == DPIO_CH1 && val == 0)
1438                         expected = 0;
1439         } else if (mask != 0x0) {
1440                 expected = DPIO_ANYDL_POWERDOWN;
1441         } else {
1442                 expected = 0;
1443         }
1444
1445         if (ch == DPIO_CH0)
1446                 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH0;
1447         else
1448                 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH1;
1449         actual &= DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN;
1450
1451         WARN(actual != expected,
1452              "Unexpected DPIO lane power down: all %d, any %d. Expected: all %d, any %d. (0x%x = 0x%08x)\n",
1453              !!(actual & DPIO_ALLDL_POWERDOWN), !!(actual & DPIO_ANYDL_POWERDOWN),
1454              !!(expected & DPIO_ALLDL_POWERDOWN), !!(expected & DPIO_ANYDL_POWERDOWN),
1455              reg, val);
1456 }
1457
1458 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1459                           enum dpio_channel ch, bool override)
1460 {
1461         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1462         bool was_override;
1463
1464         mutex_lock(&power_domains->lock);
1465
1466         was_override = dev_priv->chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1467
1468         if (override == was_override)
1469                 goto out;
1470
1471         if (override)
1472                 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1473         else
1474                 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1475
1476         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1477
1478         DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d (DPIO_PHY_CONTROL=0x%08x)\n",
1479                       phy, ch, dev_priv->chv_phy_control);
1480
1481         assert_chv_phy_status(dev_priv);
1482
1483 out:
1484         mutex_unlock(&power_domains->lock);
1485
1486         return was_override;
1487 }
1488
1489 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1490                              bool override, unsigned int mask)
1491 {
1492         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1493         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1494         enum dpio_phy phy = vlv_dport_to_phy(enc_to_dig_port(&encoder->base));
1495         enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
1496
1497         mutex_lock(&power_domains->lock);
1498
1499         dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch);
1500         dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch);
1501
1502         if (override)
1503                 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1504         else
1505                 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1506
1507         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1508
1509         DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d lanes 0x%x (PHY_CONTROL=0x%08x)\n",
1510                       phy, ch, mask, dev_priv->chv_phy_control);
1511
1512         assert_chv_phy_status(dev_priv);
1513
1514         assert_chv_phy_powergate(dev_priv, phy, ch, override, mask);
1515
1516         mutex_unlock(&power_domains->lock);
1517 }
1518
1519 static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv,
1520                                         struct i915_power_well *power_well)
1521 {
1522         enum pipe pipe = power_well->data;
1523         bool enabled;
1524         u32 state, ctrl;
1525
1526         mutex_lock(&dev_priv->rps.hw_lock);
1527
1528         state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe);
1529         /*
1530          * We only ever set the power-on and power-gate states, anything
1531          * else is unexpected.
1532          */
1533         WARN_ON(state != DP_SSS_PWR_ON(pipe) && state != DP_SSS_PWR_GATE(pipe));
1534         enabled = state == DP_SSS_PWR_ON(pipe);
1535
1536         /*
1537          * A transient state at this point would mean some unexpected party
1538          * is poking at the power controls too.
1539          */
1540         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe);
1541         WARN_ON(ctrl << 16 != state);
1542
1543         mutex_unlock(&dev_priv->rps.hw_lock);
1544
1545         return enabled;
1546 }
1547
1548 static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv,
1549                                     struct i915_power_well *power_well,
1550                                     bool enable)
1551 {
1552         enum pipe pipe = power_well->data;
1553         u32 state;
1554         u32 ctrl;
1555
1556         state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe);
1557
1558         mutex_lock(&dev_priv->rps.hw_lock);
1559
1560 #define COND \
1561         ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state)
1562
1563         if (COND)
1564                 goto out;
1565
1566         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
1567         ctrl &= ~DP_SSC_MASK(pipe);
1568         ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe);
1569         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl);
1570
1571         if (wait_for(COND, 100))
1572                 DRM_ERROR("timeout setting power well state %08x (%08x)\n",
1573                           state,
1574                           vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ));
1575
1576 #undef COND
1577
1578 out:
1579         mutex_unlock(&dev_priv->rps.hw_lock);
1580 }
1581
1582 static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv,
1583                                         struct i915_power_well *power_well)
1584 {
1585         WARN_ON_ONCE(power_well->data != PIPE_A);
1586
1587         chv_set_pipe_power_well(dev_priv, power_well, power_well->count > 0);
1588 }
1589
1590 static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv,
1591                                        struct i915_power_well *power_well)
1592 {
1593         WARN_ON_ONCE(power_well->data != PIPE_A);
1594
1595         chv_set_pipe_power_well(dev_priv, power_well, true);
1596
1597         vlv_display_power_well_init(dev_priv);
1598 }
1599
1600 static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv,
1601                                         struct i915_power_well *power_well)
1602 {
1603         WARN_ON_ONCE(power_well->data != PIPE_A);
1604
1605         vlv_display_power_well_deinit(dev_priv);
1606
1607         chv_set_pipe_power_well(dev_priv, power_well, false);
1608 }
1609
1610 static void
1611 __intel_display_power_get_domain(struct drm_i915_private *dev_priv,
1612                                  enum intel_display_power_domain domain)
1613 {
1614         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1615         struct i915_power_well *power_well;
1616         int i;
1617
1618         for_each_power_well(i, power_well, BIT(domain), power_domains)
1619                 intel_power_well_get(dev_priv, power_well);
1620
1621         power_domains->domain_use_count[domain]++;
1622 }
1623
1624 /**
1625  * intel_display_power_get - grab a power domain reference
1626  * @dev_priv: i915 device instance
1627  * @domain: power domain to reference
1628  *
1629  * This function grabs a power domain reference for @domain and ensures that the
1630  * power domain and all its parents are powered up. Therefore users should only
1631  * grab a reference to the innermost power domain they need.
1632  *
1633  * Any power domain reference obtained by this function must have a symmetric
1634  * call to intel_display_power_put() to release the reference again.
1635  */
1636 void intel_display_power_get(struct drm_i915_private *dev_priv,
1637                              enum intel_display_power_domain domain)
1638 {
1639         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1640
1641         intel_runtime_pm_get(dev_priv);
1642
1643         mutex_lock(&power_domains->lock);
1644
1645         __intel_display_power_get_domain(dev_priv, domain);
1646
1647         mutex_unlock(&power_domains->lock);
1648 }
1649
1650 /**
1651  * intel_display_power_get_if_enabled - grab a reference for an enabled display power domain
1652  * @dev_priv: i915 device instance
1653  * @domain: power domain to reference
1654  *
1655  * This function grabs a power domain reference for @domain and ensures that the
1656  * power domain and all its parents are powered up. Therefore users should only
1657  * grab a reference to the innermost power domain they need.
1658  *
1659  * Any power domain reference obtained by this function must have a symmetric
1660  * call to intel_display_power_put() to release the reference again.
1661  */
1662 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
1663                                         enum intel_display_power_domain domain)
1664 {
1665         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1666         bool is_enabled;
1667
1668         if (!intel_runtime_pm_get_if_in_use(dev_priv))
1669                 return false;
1670
1671         mutex_lock(&power_domains->lock);
1672
1673         if (__intel_display_power_is_enabled(dev_priv, domain)) {
1674                 __intel_display_power_get_domain(dev_priv, domain);
1675                 is_enabled = true;
1676         } else {
1677                 is_enabled = false;
1678         }
1679
1680         mutex_unlock(&power_domains->lock);
1681
1682         if (!is_enabled)
1683                 intel_runtime_pm_put(dev_priv);
1684
1685         return is_enabled;
1686 }
1687
1688 /**
1689  * intel_display_power_put - release a power domain reference
1690  * @dev_priv: i915 device instance
1691  * @domain: power domain to reference
1692  *
1693  * This function drops the power domain reference obtained by
1694  * intel_display_power_get() and might power down the corresponding hardware
1695  * block right away if this is the last reference.
1696  */
1697 void intel_display_power_put(struct drm_i915_private *dev_priv,
1698                              enum intel_display_power_domain domain)
1699 {
1700         struct i915_power_domains *power_domains;
1701         struct i915_power_well *power_well;
1702         int i;
1703
1704         power_domains = &dev_priv->power_domains;
1705
1706         mutex_lock(&power_domains->lock);
1707
1708         WARN(!power_domains->domain_use_count[domain],
1709              "Use count on domain %s is already zero\n",
1710              intel_display_power_domain_str(domain));
1711         power_domains->domain_use_count[domain]--;
1712
1713         for_each_power_well_rev(i, power_well, BIT(domain), power_domains)
1714                 intel_power_well_put(dev_priv, power_well);
1715
1716         mutex_unlock(&power_domains->lock);
1717
1718         intel_runtime_pm_put(dev_priv);
1719 }
1720
1721 #define HSW_DISPLAY_POWER_DOMAINS (                     \
1722         BIT(POWER_DOMAIN_PIPE_B) |                      \
1723         BIT(POWER_DOMAIN_PIPE_C) |                      \
1724         BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) |         \
1725         BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |         \
1726         BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |         \
1727         BIT(POWER_DOMAIN_TRANSCODER_A) |                \
1728         BIT(POWER_DOMAIN_TRANSCODER_B) |                \
1729         BIT(POWER_DOMAIN_TRANSCODER_C) |                \
1730         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |            \
1731         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |            \
1732         BIT(POWER_DOMAIN_PORT_DDI_D_LANES) |            \
1733         BIT(POWER_DOMAIN_PORT_CRT) | /* DDI E */        \
1734         BIT(POWER_DOMAIN_VGA) |                         \
1735         BIT(POWER_DOMAIN_AUDIO) |                       \
1736         BIT(POWER_DOMAIN_INIT))
1737
1738 #define BDW_DISPLAY_POWER_DOMAINS (                     \
1739         BIT(POWER_DOMAIN_PIPE_B) |                      \
1740         BIT(POWER_DOMAIN_PIPE_C) |                      \
1741         BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |         \
1742         BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |         \
1743         BIT(POWER_DOMAIN_TRANSCODER_A) |                \
1744         BIT(POWER_DOMAIN_TRANSCODER_B) |                \
1745         BIT(POWER_DOMAIN_TRANSCODER_C) |                \
1746         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |            \
1747         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |            \
1748         BIT(POWER_DOMAIN_PORT_DDI_D_LANES) |            \
1749         BIT(POWER_DOMAIN_PORT_CRT) | /* DDI E */        \
1750         BIT(POWER_DOMAIN_VGA) |                         \
1751         BIT(POWER_DOMAIN_AUDIO) |                       \
1752         BIT(POWER_DOMAIN_INIT))
1753
1754 #define VLV_DISPLAY_POWER_DOMAINS (             \
1755         BIT(POWER_DOMAIN_PIPE_A) |              \
1756         BIT(POWER_DOMAIN_PIPE_B) |              \
1757         BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
1758         BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
1759         BIT(POWER_DOMAIN_TRANSCODER_A) |        \
1760         BIT(POWER_DOMAIN_TRANSCODER_B) |        \
1761         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |    \
1762         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |    \
1763         BIT(POWER_DOMAIN_PORT_DSI) |            \
1764         BIT(POWER_DOMAIN_PORT_CRT) |            \
1765         BIT(POWER_DOMAIN_VGA) |                 \
1766         BIT(POWER_DOMAIN_AUDIO) |               \
1767         BIT(POWER_DOMAIN_AUX_B) |               \
1768         BIT(POWER_DOMAIN_AUX_C) |               \
1769         BIT(POWER_DOMAIN_GMBUS) |               \
1770         BIT(POWER_DOMAIN_INIT))
1771
1772 #define VLV_DPIO_CMN_BC_POWER_DOMAINS (         \
1773         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |    \
1774         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |    \
1775         BIT(POWER_DOMAIN_PORT_CRT) |            \
1776         BIT(POWER_DOMAIN_AUX_B) |               \
1777         BIT(POWER_DOMAIN_AUX_C) |               \
1778         BIT(POWER_DOMAIN_INIT))
1779
1780 #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS (  \
1781         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |    \
1782         BIT(POWER_DOMAIN_AUX_B) |               \
1783         BIT(POWER_DOMAIN_INIT))
1784
1785 #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS (  \
1786         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |    \
1787         BIT(POWER_DOMAIN_AUX_B) |               \
1788         BIT(POWER_DOMAIN_INIT))
1789
1790 #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS (  \
1791         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |    \
1792         BIT(POWER_DOMAIN_AUX_C) |               \
1793         BIT(POWER_DOMAIN_INIT))
1794
1795 #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS (  \
1796         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |    \
1797         BIT(POWER_DOMAIN_AUX_C) |               \
1798         BIT(POWER_DOMAIN_INIT))
1799
1800 #define CHV_DISPLAY_POWER_DOMAINS (             \
1801         BIT(POWER_DOMAIN_PIPE_A) |              \
1802         BIT(POWER_DOMAIN_PIPE_B) |              \
1803         BIT(POWER_DOMAIN_PIPE_C) |              \
1804         BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
1805         BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
1806         BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
1807         BIT(POWER_DOMAIN_TRANSCODER_A) |        \
1808         BIT(POWER_DOMAIN_TRANSCODER_B) |        \
1809         BIT(POWER_DOMAIN_TRANSCODER_C) |        \
1810         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |    \
1811         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |    \
1812         BIT(POWER_DOMAIN_PORT_DDI_D_LANES) |    \
1813         BIT(POWER_DOMAIN_PORT_DSI) |            \
1814         BIT(POWER_DOMAIN_VGA) |                 \
1815         BIT(POWER_DOMAIN_AUDIO) |               \
1816         BIT(POWER_DOMAIN_AUX_B) |               \
1817         BIT(POWER_DOMAIN_AUX_C) |               \
1818         BIT(POWER_DOMAIN_AUX_D) |               \
1819         BIT(POWER_DOMAIN_GMBUS) |               \
1820         BIT(POWER_DOMAIN_INIT))
1821
1822 #define CHV_DPIO_CMN_BC_POWER_DOMAINS (         \
1823         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |    \
1824         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |    \
1825         BIT(POWER_DOMAIN_AUX_B) |               \
1826         BIT(POWER_DOMAIN_AUX_C) |               \
1827         BIT(POWER_DOMAIN_INIT))
1828
1829 #define CHV_DPIO_CMN_D_POWER_DOMAINS (          \
1830         BIT(POWER_DOMAIN_PORT_DDI_D_LANES) |    \
1831         BIT(POWER_DOMAIN_AUX_D) |               \
1832         BIT(POWER_DOMAIN_INIT))
1833
1834 static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
1835         .sync_hw = i9xx_always_on_power_well_noop,
1836         .enable = i9xx_always_on_power_well_noop,
1837         .disable = i9xx_always_on_power_well_noop,
1838         .is_enabled = i9xx_always_on_power_well_enabled,
1839 };
1840
1841 static const struct i915_power_well_ops chv_pipe_power_well_ops = {
1842         .sync_hw = chv_pipe_power_well_sync_hw,
1843         .enable = chv_pipe_power_well_enable,
1844         .disable = chv_pipe_power_well_disable,
1845         .is_enabled = chv_pipe_power_well_enabled,
1846 };
1847
1848 static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = {
1849         .sync_hw = vlv_power_well_sync_hw,
1850         .enable = chv_dpio_cmn_power_well_enable,
1851         .disable = chv_dpio_cmn_power_well_disable,
1852         .is_enabled = vlv_power_well_enabled,
1853 };
1854
1855 static struct i915_power_well i9xx_always_on_power_well[] = {
1856         {
1857                 .name = "always-on",
1858                 .always_on = 1,
1859                 .domains = POWER_DOMAIN_MASK,
1860                 .ops = &i9xx_always_on_power_well_ops,
1861         },
1862 };
1863
1864 static const struct i915_power_well_ops hsw_power_well_ops = {
1865         .sync_hw = hsw_power_well_sync_hw,
1866         .enable = hsw_power_well_enable,
1867         .disable = hsw_power_well_disable,
1868         .is_enabled = hsw_power_well_enabled,
1869 };
1870
1871 static const struct i915_power_well_ops skl_power_well_ops = {
1872         .sync_hw = skl_power_well_sync_hw,
1873         .enable = skl_power_well_enable,
1874         .disable = skl_power_well_disable,
1875         .is_enabled = skl_power_well_enabled,
1876 };
1877
1878 static const struct i915_power_well_ops gen9_dc_off_power_well_ops = {
1879         .sync_hw = gen9_dc_off_power_well_sync_hw,
1880         .enable = gen9_dc_off_power_well_enable,
1881         .disable = gen9_dc_off_power_well_disable,
1882         .is_enabled = gen9_dc_off_power_well_enabled,
1883 };
1884
1885 static const struct i915_power_well_ops bxt_dpio_cmn_power_well_ops = {
1886         .sync_hw = bxt_dpio_cmn_power_well_sync_hw,
1887         .enable = bxt_dpio_cmn_power_well_enable,
1888         .disable = bxt_dpio_cmn_power_well_disable,
1889         .is_enabled = bxt_dpio_cmn_power_well_enabled,
1890 };
1891
1892 static struct i915_power_well hsw_power_wells[] = {
1893         {
1894                 .name = "always-on",
1895                 .always_on = 1,
1896                 .domains = POWER_DOMAIN_MASK,
1897                 .ops = &i9xx_always_on_power_well_ops,
1898         },
1899         {
1900                 .name = "display",
1901                 .domains = HSW_DISPLAY_POWER_DOMAINS,
1902                 .ops = &hsw_power_well_ops,
1903         },
1904 };
1905
1906 static struct i915_power_well bdw_power_wells[] = {
1907         {
1908                 .name = "always-on",
1909                 .always_on = 1,
1910                 .domains = POWER_DOMAIN_MASK,
1911                 .ops = &i9xx_always_on_power_well_ops,
1912         },
1913         {
1914                 .name = "display",
1915                 .domains = BDW_DISPLAY_POWER_DOMAINS,
1916                 .ops = &hsw_power_well_ops,
1917         },
1918 };
1919
1920 static const struct i915_power_well_ops vlv_display_power_well_ops = {
1921         .sync_hw = vlv_power_well_sync_hw,
1922         .enable = vlv_display_power_well_enable,
1923         .disable = vlv_display_power_well_disable,
1924         .is_enabled = vlv_power_well_enabled,
1925 };
1926
1927 static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = {
1928         .sync_hw = vlv_power_well_sync_hw,
1929         .enable = vlv_dpio_cmn_power_well_enable,
1930         .disable = vlv_dpio_cmn_power_well_disable,
1931         .is_enabled = vlv_power_well_enabled,
1932 };
1933
1934 static const struct i915_power_well_ops vlv_dpio_power_well_ops = {
1935         .sync_hw = vlv_power_well_sync_hw,
1936         .enable = vlv_power_well_enable,
1937         .disable = vlv_power_well_disable,
1938         .is_enabled = vlv_power_well_enabled,
1939 };
1940
1941 static struct i915_power_well vlv_power_wells[] = {
1942         {
1943                 .name = "always-on",
1944                 .always_on = 1,
1945                 .domains = POWER_DOMAIN_MASK,
1946                 .ops = &i9xx_always_on_power_well_ops,
1947                 .data = PUNIT_POWER_WELL_ALWAYS_ON,
1948         },
1949         {
1950                 .name = "display",
1951                 .domains = VLV_DISPLAY_POWER_DOMAINS,
1952                 .data = PUNIT_POWER_WELL_DISP2D,
1953                 .ops = &vlv_display_power_well_ops,
1954         },
1955         {
1956                 .name = "dpio-tx-b-01",
1957                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1958                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1959                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1960                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1961                 .ops = &vlv_dpio_power_well_ops,
1962                 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
1963         },
1964         {
1965                 .name = "dpio-tx-b-23",
1966                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1967                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1968                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1969                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1970                 .ops = &vlv_dpio_power_well_ops,
1971                 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
1972         },
1973         {
1974                 .name = "dpio-tx-c-01",
1975                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1976                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1977                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1978                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1979                 .ops = &vlv_dpio_power_well_ops,
1980                 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
1981         },
1982         {
1983                 .name = "dpio-tx-c-23",
1984                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1985                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1986                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1987                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1988                 .ops = &vlv_dpio_power_well_ops,
1989                 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
1990         },
1991         {
1992                 .name = "dpio-common",
1993                 .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,
1994                 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
1995                 .ops = &vlv_dpio_cmn_power_well_ops,
1996         },
1997 };
1998
1999 static struct i915_power_well chv_power_wells[] = {
2000         {
2001                 .name = "always-on",
2002                 .always_on = 1,
2003                 .domains = POWER_DOMAIN_MASK,
2004                 .ops = &i9xx_always_on_power_well_ops,
2005         },
2006         {
2007                 .name = "display",
2008                 /*
2009                  * Pipe A power well is the new disp2d well. Pipe B and C
2010                  * power wells don't actually exist. Pipe A power well is
2011                  * required for any pipe to work.
2012                  */
2013                 .domains = CHV_DISPLAY_POWER_DOMAINS,
2014                 .data = PIPE_A,
2015                 .ops = &chv_pipe_power_well_ops,
2016         },
2017         {
2018                 .name = "dpio-common-bc",
2019                 .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS,
2020                 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
2021                 .ops = &chv_dpio_cmn_power_well_ops,
2022         },
2023         {
2024                 .name = "dpio-common-d",
2025                 .domains = CHV_DPIO_CMN_D_POWER_DOMAINS,
2026                 .data = PUNIT_POWER_WELL_DPIO_CMN_D,
2027                 .ops = &chv_dpio_cmn_power_well_ops,
2028         },
2029 };
2030
2031 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
2032                                     int power_well_id)
2033 {
2034         struct i915_power_well *power_well;
2035         bool ret;
2036
2037         power_well = lookup_power_well(dev_priv, power_well_id);
2038         ret = power_well->ops->is_enabled(dev_priv, power_well);
2039
2040         return ret;
2041 }
2042
2043 static struct i915_power_well skl_power_wells[] = {
2044         {
2045                 .name = "always-on",
2046                 .always_on = 1,
2047                 .domains = POWER_DOMAIN_MASK,
2048                 .ops = &i9xx_always_on_power_well_ops,
2049                 .data = SKL_DISP_PW_ALWAYS_ON,
2050         },
2051         {
2052                 .name = "power well 1",
2053                 /* Handled by the DMC firmware */
2054                 .domains = 0,
2055                 .ops = &skl_power_well_ops,
2056                 .data = SKL_DISP_PW_1,
2057         },
2058         {
2059                 .name = "MISC IO power well",
2060                 /* Handled by the DMC firmware */
2061                 .domains = 0,
2062                 .ops = &skl_power_well_ops,
2063                 .data = SKL_DISP_PW_MISC_IO,
2064         },
2065         {
2066                 .name = "DC off",
2067                 .domains = SKL_DISPLAY_DC_OFF_POWER_DOMAINS,
2068                 .ops = &gen9_dc_off_power_well_ops,
2069                 .data = SKL_DISP_PW_DC_OFF,
2070         },
2071         {
2072                 .name = "power well 2",
2073                 .domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS,
2074                 .ops = &skl_power_well_ops,
2075                 .data = SKL_DISP_PW_2,
2076         },
2077         {
2078                 .name = "DDI A/E power well",
2079                 .domains = SKL_DISPLAY_DDI_A_E_POWER_DOMAINS,
2080                 .ops = &skl_power_well_ops,
2081                 .data = SKL_DISP_PW_DDI_A_E,
2082         },
2083         {
2084                 .name = "DDI B power well",
2085                 .domains = SKL_DISPLAY_DDI_B_POWER_DOMAINS,
2086                 .ops = &skl_power_well_ops,
2087                 .data = SKL_DISP_PW_DDI_B,
2088         },
2089         {
2090                 .name = "DDI C power well",
2091                 .domains = SKL_DISPLAY_DDI_C_POWER_DOMAINS,
2092                 .ops = &skl_power_well_ops,
2093                 .data = SKL_DISP_PW_DDI_C,
2094         },
2095         {
2096                 .name = "DDI D power well",
2097                 .domains = SKL_DISPLAY_DDI_D_POWER_DOMAINS,
2098                 .ops = &skl_power_well_ops,
2099                 .data = SKL_DISP_PW_DDI_D,
2100         },
2101 };
2102
2103 static struct i915_power_well bxt_power_wells[] = {
2104         {
2105                 .name = "always-on",
2106                 .always_on = 1,
2107                 .domains = POWER_DOMAIN_MASK,
2108                 .ops = &i9xx_always_on_power_well_ops,
2109         },
2110         {
2111                 .name = "power well 1",
2112                 .domains = 0,
2113                 .ops = &skl_power_well_ops,
2114                 .data = SKL_DISP_PW_1,
2115         },
2116         {
2117                 .name = "DC off",
2118                 .domains = BXT_DISPLAY_DC_OFF_POWER_DOMAINS,
2119                 .ops = &gen9_dc_off_power_well_ops,
2120                 .data = SKL_DISP_PW_DC_OFF,
2121         },
2122         {
2123                 .name = "power well 2",
2124                 .domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS,
2125                 .ops = &skl_power_well_ops,
2126                 .data = SKL_DISP_PW_2,
2127         },
2128         {
2129                 .name = "dpio-common-a",
2130                 .domains = BXT_DPIO_CMN_A_POWER_DOMAINS,
2131                 .ops = &bxt_dpio_cmn_power_well_ops,
2132                 .data = BXT_DPIO_CMN_A,
2133         },
2134         {
2135                 .name = "dpio-common-bc",
2136                 .domains = BXT_DPIO_CMN_BC_POWER_DOMAINS,
2137                 .ops = &bxt_dpio_cmn_power_well_ops,
2138                 .data = BXT_DPIO_CMN_BC,
2139         },
2140 };
2141
2142 static int
2143 sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv,
2144                                    int disable_power_well)
2145 {
2146         if (disable_power_well >= 0)
2147                 return !!disable_power_well;
2148
2149         return 1;
2150 }
2151
2152 static uint32_t get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
2153                                     int enable_dc)
2154 {
2155         uint32_t mask;
2156         int requested_dc;
2157         int max_dc;
2158
2159         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
2160                 max_dc = 2;
2161                 mask = 0;
2162         } else if (IS_BROXTON(dev_priv)) {
2163                 max_dc = 1;
2164                 /*
2165                  * DC9 has a separate HW flow from the rest of the DC states,
2166                  * not depending on the DMC firmware. It's needed by system
2167                  * suspend/resume, so allow it unconditionally.
2168                  */
2169                 mask = DC_STATE_EN_DC9;
2170         } else {
2171                 max_dc = 0;
2172                 mask = 0;
2173         }
2174
2175         if (!i915.disable_power_well)
2176                 max_dc = 0;
2177
2178         if (enable_dc >= 0 && enable_dc <= max_dc) {
2179                 requested_dc = enable_dc;
2180         } else if (enable_dc == -1) {
2181                 requested_dc = max_dc;
2182         } else if (enable_dc > max_dc && enable_dc <= 2) {
2183                 DRM_DEBUG_KMS("Adjusting requested max DC state (%d->%d)\n",
2184                               enable_dc, max_dc);
2185                 requested_dc = max_dc;
2186         } else {
2187                 DRM_ERROR("Unexpected value for enable_dc (%d)\n", enable_dc);
2188                 requested_dc = max_dc;
2189         }
2190
2191         if (requested_dc > 1)
2192                 mask |= DC_STATE_EN_UPTO_DC6;
2193         if (requested_dc > 0)
2194                 mask |= DC_STATE_EN_UPTO_DC5;
2195
2196         DRM_DEBUG_KMS("Allowed DC state mask %02x\n", mask);
2197
2198         return mask;
2199 }
2200
2201 #define set_power_wells(power_domains, __power_wells) ({                \
2202         (power_domains)->power_wells = (__power_wells);                 \
2203         (power_domains)->power_well_count = ARRAY_SIZE(__power_wells);  \
2204 })
2205
2206 /**
2207  * intel_power_domains_init - initializes the power domain structures
2208  * @dev_priv: i915 device instance
2209  *
2210  * Initializes the power domain structures for @dev_priv depending upon the
2211  * supported platform.
2212  */
2213 int intel_power_domains_init(struct drm_i915_private *dev_priv)
2214 {
2215         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2216
2217         i915.disable_power_well = sanitize_disable_power_well_option(dev_priv,
2218                                                      i915.disable_power_well);
2219         dev_priv->csr.allowed_dc_mask = get_allowed_dc_mask(dev_priv,
2220                                                             i915.enable_dc);
2221
2222         BUILD_BUG_ON(POWER_DOMAIN_NUM > 31);
2223
2224         mutex_init(&power_domains->lock);
2225
2226         /*
2227          * The enabling order will be from lower to higher indexed wells,
2228          * the disabling order is reversed.
2229          */
2230         if (IS_HASWELL(dev_priv)) {
2231                 set_power_wells(power_domains, hsw_power_wells);
2232         } else if (IS_BROADWELL(dev_priv)) {
2233                 set_power_wells(power_domains, bdw_power_wells);
2234         } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
2235                 set_power_wells(power_domains, skl_power_wells);
2236         } else if (IS_BROXTON(dev_priv)) {
2237                 set_power_wells(power_domains, bxt_power_wells);
2238         } else if (IS_CHERRYVIEW(dev_priv)) {
2239                 set_power_wells(power_domains, chv_power_wells);
2240         } else if (IS_VALLEYVIEW(dev_priv)) {
2241                 set_power_wells(power_domains, vlv_power_wells);
2242         } else {
2243                 set_power_wells(power_domains, i9xx_always_on_power_well);
2244         }
2245
2246         return 0;
2247 }
2248
2249 /**
2250  * intel_power_domains_fini - finalizes the power domain structures
2251  * @dev_priv: i915 device instance
2252  *
2253  * Finalizes the power domain structures for @dev_priv depending upon the
2254  * supported platform. This function also disables runtime pm and ensures that
2255  * the device stays powered up so that the driver can be reloaded.
2256  */
2257 void intel_power_domains_fini(struct drm_i915_private *dev_priv)
2258 {
2259         struct device *device = &dev_priv->dev->pdev->dev;
2260
2261         /*
2262          * The i915.ko module is still not prepared to be loaded when
2263          * the power well is not enabled, so just enable it in case
2264          * we're going to unload/reload.
2265          * The following also reacquires the RPM reference the core passed
2266          * to the driver during loading, which is dropped in
2267          * intel_runtime_pm_enable(). We have to hand back the control of the
2268          * device to the core with this reference held.
2269          */
2270         intel_display_set_init_power(dev_priv, true);
2271
2272         /* Remove the refcount we took to keep power well support disabled. */
2273         if (!i915.disable_power_well)
2274                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
2275
2276         /*
2277          * Remove the refcount we took in intel_runtime_pm_enable() in case
2278          * the platform doesn't support runtime PM.
2279          */
2280         if (!HAS_RUNTIME_PM(dev_priv))
2281                 pm_runtime_put(device);
2282 }
2283
2284 static void intel_power_domains_sync_hw(struct drm_i915_private *dev_priv)
2285 {
2286         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2287         struct i915_power_well *power_well;
2288         int i;
2289
2290         mutex_lock(&power_domains->lock);
2291         for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
2292                 power_well->ops->sync_hw(dev_priv, power_well);
2293                 power_well->hw_enabled = power_well->ops->is_enabled(dev_priv,
2294                                                                      power_well);
2295         }
2296         mutex_unlock(&power_domains->lock);
2297 }
2298
2299 static void gen9_dbuf_enable(struct drm_i915_private *dev_priv)
2300 {
2301         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
2302         POSTING_READ(DBUF_CTL);
2303
2304         udelay(10);
2305
2306         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
2307                 DRM_ERROR("DBuf power enable timeout\n");
2308 }
2309
2310 static void gen9_dbuf_disable(struct drm_i915_private *dev_priv)
2311 {
2312         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
2313         POSTING_READ(DBUF_CTL);
2314
2315         udelay(10);
2316
2317         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
2318                 DRM_ERROR("DBuf power disable timeout!\n");
2319 }
2320
2321 static void skl_display_core_init(struct drm_i915_private *dev_priv,
2322                                    bool resume)
2323 {
2324         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2325         struct i915_power_well *well;
2326         uint32_t val;
2327
2328         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
2329
2330         /* enable PCH reset handshake */
2331         val = I915_READ(HSW_NDE_RSTWRN_OPT);
2332         I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
2333
2334         /* enable PG1 and Misc I/O */
2335         mutex_lock(&power_domains->lock);
2336
2337         well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
2338         intel_power_well_enable(dev_priv, well);
2339
2340         well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);
2341         intel_power_well_enable(dev_priv, well);
2342
2343         mutex_unlock(&power_domains->lock);
2344
2345         skl_init_cdclk(dev_priv);
2346
2347         gen9_dbuf_enable(dev_priv);
2348
2349         if (resume && dev_priv->csr.dmc_payload)
2350                 intel_csr_load_program(dev_priv);
2351 }
2352
2353 static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
2354 {
2355         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2356         struct i915_power_well *well;
2357
2358         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
2359
2360         gen9_dbuf_disable(dev_priv);
2361
2362         skl_uninit_cdclk(dev_priv);
2363
2364         /* The spec doesn't call for removing the reset handshake flag */
2365         /* disable PG1 and Misc I/O */
2366
2367         mutex_lock(&power_domains->lock);
2368
2369         well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);
2370         intel_power_well_disable(dev_priv, well);
2371
2372         well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
2373         intel_power_well_disable(dev_priv, well);
2374
2375         mutex_unlock(&power_domains->lock);
2376 }
2377
2378 void bxt_display_core_init(struct drm_i915_private *dev_priv,
2379                            bool resume)
2380 {
2381         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2382         struct i915_power_well *well;
2383         uint32_t val;
2384
2385         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
2386
2387         /*
2388          * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
2389          * or else the reset will hang because there is no PCH to respond.
2390          * Move the handshake programming to initialization sequence.
2391          * Previously was left up to BIOS.
2392          */
2393         val = I915_READ(HSW_NDE_RSTWRN_OPT);
2394         val &= ~RESET_PCH_HANDSHAKE_ENABLE;
2395         I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
2396
2397         /* Enable PG1 */
2398         mutex_lock(&power_domains->lock);
2399
2400         well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
2401         intel_power_well_enable(dev_priv, well);
2402
2403         mutex_unlock(&power_domains->lock);
2404
2405         bxt_init_cdclk(dev_priv);
2406
2407         gen9_dbuf_enable(dev_priv);
2408
2409         if (resume && dev_priv->csr.dmc_payload)
2410                 intel_csr_load_program(dev_priv);
2411 }
2412
2413 void bxt_display_core_uninit(struct drm_i915_private *dev_priv)
2414 {
2415         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2416         struct i915_power_well *well;
2417
2418         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
2419
2420         gen9_dbuf_disable(dev_priv);
2421
2422         bxt_uninit_cdclk(dev_priv);
2423
2424         /* The spec doesn't call for removing the reset handshake flag */
2425
2426         /* Disable PG1 */
2427         mutex_lock(&power_domains->lock);
2428
2429         well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
2430         intel_power_well_disable(dev_priv, well);
2431
2432         mutex_unlock(&power_domains->lock);
2433 }
2434
2435 static void chv_phy_control_init(struct drm_i915_private *dev_priv)
2436 {
2437         struct i915_power_well *cmn_bc =
2438                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
2439         struct i915_power_well *cmn_d =
2440                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D);
2441
2442         /*
2443          * DISPLAY_PHY_CONTROL can get corrupted if read. As a
2444          * workaround never ever read DISPLAY_PHY_CONTROL, and
2445          * instead maintain a shadow copy ourselves. Use the actual
2446          * power well state and lane status to reconstruct the
2447          * expected initial value.
2448          */
2449         dev_priv->chv_phy_control =
2450                 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY0) |
2451                 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY1) |
2452                 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH0) |
2453                 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH1) |
2454                 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY1, DPIO_CH0);
2455
2456         /*
2457          * If all lanes are disabled we leave the override disabled
2458          * with all power down bits cleared to match the state we
2459          * would use after disabling the port. Otherwise enable the
2460          * override and set the lane powerdown bits accding to the
2461          * current lane status.
2462          */
2463         if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) {
2464                 uint32_t status = I915_READ(DPLL(PIPE_A));
2465                 unsigned int mask;
2466
2467                 mask = status & DPLL_PORTB_READY_MASK;
2468                 if (mask == 0xf)
2469                         mask = 0x0;
2470                 else
2471                         dev_priv->chv_phy_control |=
2472                                 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0);
2473
2474                 dev_priv->chv_phy_control |=
2475                         PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH0);
2476
2477                 mask = (status & DPLL_PORTC_READY_MASK) >> 4;
2478                 if (mask == 0xf)
2479                         mask = 0x0;
2480                 else
2481                         dev_priv->chv_phy_control |=
2482                                 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1);
2483
2484                 dev_priv->chv_phy_control |=
2485                         PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH1);
2486
2487                 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0);
2488
2489                 dev_priv->chv_phy_assert[DPIO_PHY0] = false;
2490         } else {
2491                 dev_priv->chv_phy_assert[DPIO_PHY0] = true;
2492         }
2493
2494         if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) {
2495                 uint32_t status = I915_READ(DPIO_PHY_STATUS);
2496                 unsigned int mask;
2497
2498                 mask = status & DPLL_PORTD_READY_MASK;
2499
2500                 if (mask == 0xf)
2501                         mask = 0x0;
2502                 else
2503                         dev_priv->chv_phy_control |=
2504                                 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0);
2505
2506                 dev_priv->chv_phy_control |=
2507                         PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY1, DPIO_CH0);
2508
2509                 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1);
2510
2511                 dev_priv->chv_phy_assert[DPIO_PHY1] = false;
2512         } else {
2513                 dev_priv->chv_phy_assert[DPIO_PHY1] = true;
2514         }
2515
2516         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
2517
2518         DRM_DEBUG_KMS("Initial PHY_CONTROL=0x%08x\n",
2519                       dev_priv->chv_phy_control);
2520 }
2521
2522 static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv)
2523 {
2524         struct i915_power_well *cmn =
2525                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
2526         struct i915_power_well *disp2d =
2527                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D);
2528
2529         /* If the display might be already active skip this */
2530         if (cmn->ops->is_enabled(dev_priv, cmn) &&
2531             disp2d->ops->is_enabled(dev_priv, disp2d) &&
2532             I915_READ(DPIO_CTL) & DPIO_CMNRST)
2533                 return;
2534
2535         DRM_DEBUG_KMS("toggling display PHY side reset\n");
2536
2537         /* cmnlane needs DPLL registers */
2538         disp2d->ops->enable(dev_priv, disp2d);
2539
2540         /*
2541          * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx:
2542          * Need to assert and de-assert PHY SB reset by gating the
2543          * common lane power, then un-gating it.
2544          * Simply ungating isn't enough to reset the PHY enough to get
2545          * ports and lanes running.
2546          */
2547         cmn->ops->disable(dev_priv, cmn);
2548 }
2549
2550 /**
2551  * intel_power_domains_init_hw - initialize hardware power domain state
2552  * @dev_priv: i915 device instance
2553  * @resume: Called from resume code paths or not
2554  *
2555  * This function initializes the hardware power domain state and enables all
2556  * power domains using intel_display_set_init_power().
2557  */
2558 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume)
2559 {
2560         struct drm_device *dev = dev_priv->dev;
2561         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2562
2563         power_domains->initializing = true;
2564
2565         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
2566                 skl_display_core_init(dev_priv, resume);
2567         } else if (IS_BROXTON(dev)) {
2568                 bxt_display_core_init(dev_priv, resume);
2569         } else if (IS_CHERRYVIEW(dev)) {
2570                 mutex_lock(&power_domains->lock);
2571                 chv_phy_control_init(dev_priv);
2572                 mutex_unlock(&power_domains->lock);
2573         } else if (IS_VALLEYVIEW(dev)) {
2574                 mutex_lock(&power_domains->lock);
2575                 vlv_cmnlane_wa(dev_priv);
2576                 mutex_unlock(&power_domains->lock);
2577         }
2578
2579         /* For now, we need the power well to be always enabled. */
2580         intel_display_set_init_power(dev_priv, true);
2581         /* Disable power support if the user asked so. */
2582         if (!i915.disable_power_well)
2583                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
2584         intel_power_domains_sync_hw(dev_priv);
2585         power_domains->initializing = false;
2586 }
2587
2588 /**
2589  * intel_power_domains_suspend - suspend power domain state
2590  * @dev_priv: i915 device instance
2591  *
2592  * This function prepares the hardware power domain state before entering
2593  * system suspend. It must be paired with intel_power_domains_init_hw().
2594  */
2595 void intel_power_domains_suspend(struct drm_i915_private *dev_priv)
2596 {
2597         /*
2598          * Even if power well support was disabled we still want to disable
2599          * power wells while we are system suspended.
2600          */
2601         if (!i915.disable_power_well)
2602                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
2603
2604         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
2605                 skl_display_core_uninit(dev_priv);
2606         else if (IS_BROXTON(dev_priv))
2607                 bxt_display_core_uninit(dev_priv);
2608 }
2609
2610 /**
2611  * intel_runtime_pm_get - grab a runtime pm reference
2612  * @dev_priv: i915 device instance
2613  *
2614  * This function grabs a device-level runtime pm reference (mostly used for GEM
2615  * code to ensure the GTT or GT is on) and ensures that it is powered up.
2616  *
2617  * Any runtime pm reference obtained by this function must have a symmetric
2618  * call to intel_runtime_pm_put() to release the reference again.
2619  */
2620 void intel_runtime_pm_get(struct drm_i915_private *dev_priv)
2621 {
2622         struct drm_device *dev = dev_priv->dev;
2623         struct device *device = &dev->pdev->dev;
2624
2625         pm_runtime_get_sync(device);
2626
2627         atomic_inc(&dev_priv->pm.wakeref_count);
2628         assert_rpm_wakelock_held(dev_priv);
2629 }
2630
2631 /**
2632  * intel_runtime_pm_get_if_in_use - grab a runtime pm reference if device in use
2633  * @dev_priv: i915 device instance
2634  *
2635  * This function grabs a device-level runtime pm reference if the device is
2636  * already in use and ensures that it is powered up.
2637  *
2638  * Any runtime pm reference obtained by this function must have a symmetric
2639  * call to intel_runtime_pm_put() to release the reference again.
2640  */
2641 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv)
2642 {
2643         struct drm_device *dev = dev_priv->dev;
2644         struct device *device = &dev->pdev->dev;
2645
2646         if (IS_ENABLED(CONFIG_PM)) {
2647                 int ret = pm_runtime_get_if_in_use(device);
2648
2649                 /*
2650                  * In cases runtime PM is disabled by the RPM core and we get
2651                  * an -EINVAL return value we are not supposed to call this
2652                  * function, since the power state is undefined. This applies
2653                  * atm to the late/early system suspend/resume handlers.
2654                  */
2655                 WARN_ON_ONCE(ret < 0);
2656                 if (ret <= 0)
2657                         return false;
2658         }
2659
2660         atomic_inc(&dev_priv->pm.wakeref_count);
2661         assert_rpm_wakelock_held(dev_priv);
2662
2663         return true;
2664 }
2665
2666 /**
2667  * intel_runtime_pm_get_noresume - grab a runtime pm reference
2668  * @dev_priv: i915 device instance
2669  *
2670  * This function grabs a device-level runtime pm reference (mostly used for GEM
2671  * code to ensure the GTT or GT is on).
2672  *
2673  * It will _not_ power up the device but instead only check that it's powered
2674  * on.  Therefore it is only valid to call this functions from contexts where
2675  * the device is known to be powered up and where trying to power it up would
2676  * result in hilarity and deadlocks. That pretty much means only the system
2677  * suspend/resume code where this is used to grab runtime pm references for
2678  * delayed setup down in work items.
2679  *
2680  * Any runtime pm reference obtained by this function must have a symmetric
2681  * call to intel_runtime_pm_put() to release the reference again.
2682  */
2683 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv)
2684 {
2685         struct drm_device *dev = dev_priv->dev;
2686         struct device *device = &dev->pdev->dev;
2687
2688         assert_rpm_wakelock_held(dev_priv);
2689         pm_runtime_get_noresume(device);
2690
2691         atomic_inc(&dev_priv->pm.wakeref_count);
2692 }
2693
2694 /**
2695  * intel_runtime_pm_put - release a runtime pm reference
2696  * @dev_priv: i915 device instance
2697  *
2698  * This function drops the device-level runtime pm reference obtained by
2699  * intel_runtime_pm_get() and might power down the corresponding
2700  * hardware block right away if this is the last reference.
2701  */
2702 void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
2703 {
2704         struct drm_device *dev = dev_priv->dev;
2705         struct device *device = &dev->pdev->dev;
2706
2707         assert_rpm_wakelock_held(dev_priv);
2708         if (atomic_dec_and_test(&dev_priv->pm.wakeref_count))
2709                 atomic_inc(&dev_priv->pm.atomic_seq);
2710
2711         pm_runtime_mark_last_busy(device);
2712         pm_runtime_put_autosuspend(device);
2713 }
2714
2715 /**
2716  * intel_runtime_pm_enable - enable runtime pm
2717  * @dev_priv: i915 device instance
2718  *
2719  * This function enables runtime pm at the end of the driver load sequence.
2720  *
2721  * Note that this function does currently not enable runtime pm for the
2722  * subordinate display power domains. That is only done on the first modeset
2723  * using intel_display_set_init_power().
2724  */
2725 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv)
2726 {
2727         struct drm_device *dev = dev_priv->dev;
2728         struct device *device = &dev->pdev->dev;
2729
2730         pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */
2731         pm_runtime_mark_last_busy(device);
2732
2733         /*
2734          * Take a permanent reference to disable the RPM functionality and drop
2735          * it only when unloading the driver. Use the low level get/put helpers,
2736          * so the driver's own RPM reference tracking asserts also work on
2737          * platforms without RPM support.
2738          */
2739         if (!HAS_RUNTIME_PM(dev)) {
2740                 pm_runtime_dont_use_autosuspend(device);
2741                 pm_runtime_get_sync(device);
2742         } else {
2743                 pm_runtime_use_autosuspend(device);
2744         }
2745
2746         /*
2747          * The core calls the driver load handler with an RPM reference held.
2748          * We drop that here and will reacquire it during unloading in
2749          * intel_power_domains_fini().
2750          */
2751         pm_runtime_put_autosuspend(device);
2752 }
2753