drivers/gpu/drm/i915/intel_runtime_pm.c

   1 /*
   2  * Copyright © 2012-2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *    Daniel Vetter <daniel.vetter@ffwll.ch>
  26  *
  27  */
  28
  29 #include <linux/pm_runtime.h>
  30 #include <linux/vgaarb.h>
  31
  32 #include "i915_drv.h"
  33 #include "intel_drv.h"
  34
  35 /**
  36  * DOC: runtime pm
  37  *
  38  * The i915 driver supports dynamic enabling and disabling of entire hardware
  39  * blocks at runtime. This is especially important on the display side where
  40  * software is supposed to control many power gates manually on recent hardware,
  41  * since on the GT side a lot of the power management is done by the hardware.
  42  * But even there some manual control at the device level is required.
  43  *
  44  * Since i915 supports a diverse set of platforms with a unified codebase and
  45  * hardware engineers just love to shuffle functionality around between power
  46  * domains there's a sizeable amount of indirection required. This file provides
  47  * generic functions to the driver for grabbing and releasing references for
  48  * abstract power domains. It then maps those to the actual power wells
  49  * present for a given platform.
  50  */
  51
  52 #define for_each_power_well(i, power_well, domain_mask, power_domains)  \
  53         for (i = 0;                                                     \
  54              i < (power_domains)->power_well_count &&                   \
  55                  ((power_well) = &(power_domains)->power_wells[i]);     \
  56              i++)                                                       \
  57                 for_each_if ((power_well)->domains & (domain_mask))
  58
  59 #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
  60         for (i = (power_domains)->power_well_count - 1;                  \
  61              i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
  62              i--)                                                        \
  63                 for_each_if ((power_well)->domains & (domain_mask))
  64
  65 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
  66                                     int power_well_id);
  67
  68 static struct i915_power_well *
  69 lookup_power_well(struct drm_i915_private *dev_priv, int power_well_id);
  70
  71 const char *
  72 intel_display_power_domain_str(enum intel_display_power_domain domain)
  73 {
  74         switch (domain) {
  75         case POWER_DOMAIN_PIPE_A:
  76                 return "PIPE_A";
  77         case POWER_DOMAIN_PIPE_B:
  78                 return "PIPE_B";
  79         case POWER_DOMAIN_PIPE_C:
  80                 return "PIPE_C";
  81         case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
  82                 return "PIPE_A_PANEL_FITTER";
  83         case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
  84                 return "PIPE_B_PANEL_FITTER";
  85         case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
  86                 return "PIPE_C_PANEL_FITTER";
  87         case POWER_DOMAIN_TRANSCODER_A:
  88                 return "TRANSCODER_A";
  89         case POWER_DOMAIN_TRANSCODER_B:
  90                 return "TRANSCODER_B";
  91         case POWER_DOMAIN_TRANSCODER_C:
  92                 return "TRANSCODER_C";
  93         case POWER_DOMAIN_TRANSCODER_EDP:
  94                 return "TRANSCODER_EDP";
  95         case POWER_DOMAIN_TRANSCODER_DSI_A:
  96                 return "TRANSCODER_DSI_A";
  97         case POWER_DOMAIN_TRANSCODER_DSI_C:
  98                 return "TRANSCODER_DSI_C";
  99         case POWER_DOMAIN_PORT_DDI_A_LANES:
 100                 return "PORT_DDI_A_LANES";
 101         case POWER_DOMAIN_PORT_DDI_B_LANES:
 102                 return "PORT_DDI_B_LANES";
 103         case POWER_DOMAIN_PORT_DDI_C_LANES:
 104                 return "PORT_DDI_C_LANES";
 105         case POWER_DOMAIN_PORT_DDI_D_LANES:
 106                 return "PORT_DDI_D_LANES";
 107         case POWER_DOMAIN_PORT_DDI_E_LANES:
 108                 return "PORT_DDI_E_LANES";
 109         case POWER_DOMAIN_PORT_DSI:
 110                 return "PORT_DSI";
 111         case POWER_DOMAIN_PORT_CRT:
 112                 return "PORT_CRT";
 113         case POWER_DOMAIN_PORT_OTHER:
 114                 return "PORT_OTHER";
 115         case POWER_DOMAIN_VGA:
 116                 return "VGA";
 117         case POWER_DOMAIN_AUDIO:
 118                 return "AUDIO";
 119         case POWER_DOMAIN_PLLS:
 120                 return "PLLS";
 121         case POWER_DOMAIN_AUX_A:
 122                 return "AUX_A";
 123         case POWER_DOMAIN_AUX_B:
 124                 return "AUX_B";
 125         case POWER_DOMAIN_AUX_C:
 126                 return "AUX_C";
 127         case POWER_DOMAIN_AUX_D:
 128                 return "AUX_D";
 129         case POWER_DOMAIN_GMBUS:
 130                 return "GMBUS";
 131         case POWER_DOMAIN_INIT:
 132                 return "INIT";
 133         case POWER_DOMAIN_MODESET:
 134                 return "MODESET";
 135         default:
 136                 MISSING_CASE(domain);
 137                 return "?";
 138         }
 139 }
 140
 141 static void intel_power_well_enable(struct drm_i915_private *dev_priv,
 142                                     struct i915_power_well *power_well)
 143 {
 144         DRM_DEBUG_KMS("enabling %s\n", power_well->name);
 145         power_well->ops->enable(dev_priv, power_well);
 146         power_well->hw_enabled = true;
 147 }
 148
 149 static void intel_power_well_disable(struct drm_i915_private *dev_priv,
 150                                      struct i915_power_well *power_well)
 151 {
 152         DRM_DEBUG_KMS("disabling %s\n", power_well->name);
 153         power_well->hw_enabled = false;
 154         power_well->ops->disable(dev_priv, power_well);
 155 }
 156
 157 static void intel_power_well_get(struct drm_i915_private *dev_priv,
 158                                  struct i915_power_well *power_well)
 159 {
 160         if (!power_well->count++)
 161                 intel_power_well_enable(dev_priv, power_well);
 162 }
 163
 164 static void intel_power_well_put(struct drm_i915_private *dev_priv,
 165                                  struct i915_power_well *power_well)
 166 {
 167         WARN(!power_well->count, "Use count on power well %s is already zero",
 168              power_well->name);
 169
 170         if (!--power_well->count)
 171                 intel_power_well_disable(dev_priv, power_well);
 172 }
 173
 174 /*
 175  * We should only use the power well if we explicitly asked the hardware to
 176  * enable it, so check if it's enabled and also check if we've requested it to
 177  * be enabled.
 178  */
 179 static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
 180                                    struct i915_power_well *power_well)
 181 {
 182         return I915_READ(HSW_PWR_WELL_DRIVER) ==
 183                      (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
 184 }
 185
 186 /**
 187  * __intel_display_power_is_enabled - unlocked check for a power domain
 188  * @dev_priv: i915 device instance
 189  * @domain: power domain to check
 190  *
 191  * This is the unlocked version of intel_display_power_is_enabled() and should
 192  * only be used from error capture and recovery code where deadlocks are
 193  * possible.
 194  *
 195  * Returns:
 196  * True when the power domain is enabled, false otherwise.
 197  */
 198 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
 199                                       enum intel_display_power_domain domain)
 200 {
 201         struct i915_power_domains *power_domains;
 202         struct i915_power_well *power_well;
 203         bool is_enabled;
 204         int i;
 205
 206         if (dev_priv->pm.suspended)
 207                 return false;
 208
 209         power_domains = &dev_priv->power_domains;
 210
 211         is_enabled = true;
 212
 213         for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
 214                 if (power_well->always_on)
 215                         continue;
 216
 217                 if (!power_well->hw_enabled) {
 218                         is_enabled = false;
 219                         break;
 220                 }
 221         }
 222
 223         return is_enabled;
 224 }
 225
 226 /**
 227  * intel_display_power_is_enabled - check for a power domain
 228  * @dev_priv: i915 device instance
 229  * @domain: power domain to check
 230  *
 231  * This function can be used to check the hw power domain state. It is mostly
 232  * used in hardware state readout functions. Everywhere else code should rely
 233  * upon explicit power domain reference counting to ensure that the hardware
 234  * block is powered up before accessing it.
 235  *
 236  * Callers must hold the relevant modesetting locks to ensure that concurrent
 237  * threads can't disable the power well while the caller tries to read a few
 238  * registers.
 239  *
 240  * Returns:
 241  * True when the power domain is enabled, false otherwise.
 242  */
 243 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
 244                                     enum intel_display_power_domain domain)
 245 {
 246         struct i915_power_domains *power_domains;
 247         bool ret;
 248
 249         power_domains = &dev_priv->power_domains;
 250
 251         mutex_lock(&power_domains->lock);
 252         ret = __intel_display_power_is_enabled(dev_priv, domain);
 253         mutex_unlock(&power_domains->lock);
 254
 255         return ret;
 256 }
 257
 258 /**
 259  * intel_display_set_init_power - set the initial power domain state
 260  * @dev_priv: i915 device instance
 261  * @enable: whether to enable or disable the initial power domain state
 262  *
 263  * For simplicity our driver load/unload and system suspend/resume code assumes
 264  * that all power domains are always enabled. This functions controls the state
 265  * of this little hack. While the initial power domain state is enabled runtime
 266  * pm is effectively disabled.
 267  */
 268 void intel_display_set_init_power(struct drm_i915_private *dev_priv,
 269                                   bool enable)
 270 {
 271         if (dev_priv->power_domains.init_power_on == enable)
 272                 return;
 273
 274         if (enable)
 275                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
 276         else
 277                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
 278
 279         dev_priv->power_domains.init_power_on = enable;
 280 }
 281
 282 /*
 283  * Starting with Haswell, we have a "Power Down Well" that can be turned off
 284  * when not needed anymore. We have 4 registers that can request the power well
 285  * to be enabled, and it will only be disabled if none of the registers is
 286  * requesting it to be enabled.
 287  */
 288 static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
 289 {
 290         struct drm_device *dev = dev_priv->dev;
 291
 292         /*
 293          * After we re-enable the power well, if we touch VGA register 0x3d5
 294          * we'll get unclaimed register interrupts. This stops after we write
 295          * anything to the VGA MSR register. The vgacon module uses this
 296          * register all the time, so if we unbind our driver and, as a
 297          * consequence, bind vgacon, we'll get stuck in an infinite loop at
 298          * console_unlock(). So make here we touch the VGA MSR register, making
 299          * sure vgacon can keep working normally without triggering interrupts
 300          * and error messages.
 301          */
 302         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
 303         outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
 304         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
 305
 306         if (IS_BROADWELL(dev))
 307                 gen8_irq_power_well_post_enable(dev_priv,
 308                                                 1 << PIPE_C | 1 << PIPE_B);
 309 }
 310
 311 static void hsw_power_well_pre_disable(struct drm_i915_private *dev_priv)
 312 {
 313         if (IS_BROADWELL(dev_priv))
 314                 gen8_irq_power_well_pre_disable(dev_priv,
 315                                                 1 << PIPE_C | 1 << PIPE_B);
 316 }
 317
 318 static void skl_power_well_post_enable(struct drm_i915_private *dev_priv,
 319                                        struct i915_power_well *power_well)
 320 {
 321         struct drm_device *dev = dev_priv->dev;
 322
 323         /*
 324          * After we re-enable the power well, if we touch VGA register 0x3d5
 325          * we'll get unclaimed register interrupts. This stops after we write
 326          * anything to the VGA MSR register. The vgacon module uses this
 327          * register all the time, so if we unbind our driver and, as a
 328          * consequence, bind vgacon, we'll get stuck in an infinite loop at
 329          * console_unlock(). So make here we touch the VGA MSR register, making
 330          * sure vgacon can keep working normally without triggering interrupts
 331          * and error messages.
 332          */
 333         if (power_well->data == SKL_DISP_PW_2) {
 334                 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
 335                 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
 336                 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
 337
 338                 gen8_irq_power_well_post_enable(dev_priv,
 339                                                 1 << PIPE_C | 1 << PIPE_B);
 340         }
 341 }
 342
 343 static void skl_power_well_pre_disable(struct drm_i915_private *dev_priv,
 344                                        struct i915_power_well *power_well)
 345 {
 346         if (power_well->data == SKL_DISP_PW_2)
 347                 gen8_irq_power_well_pre_disable(dev_priv,
 348                                                 1 << PIPE_C | 1 << PIPE_B);
 349 }
 350
 351 static void hsw_set_power_well(struct drm_i915_private *dev_priv,
 352                                struct i915_power_well *power_well, bool enable)
 353 {
 354         bool is_enabled, enable_requested;
 355         uint32_t tmp;
 356
 357         tmp = I915_READ(HSW_PWR_WELL_DRIVER);
 358         is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
 359         enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
 360
 361         if (enable) {
 362                 if (!enable_requested)
 363                         I915_WRITE(HSW_PWR_WELL_DRIVER,
 364                                    HSW_PWR_WELL_ENABLE_REQUEST);
 365
 366                 if (!is_enabled) {
 367                         DRM_DEBUG_KMS("Enabling power well\n");
 368                         if (intel_wait_for_register(dev_priv,
 369                                                     HSW_PWR_WELL_DRIVER,
 370                                                     HSW_PWR_WELL_STATE_ENABLED,
 371                                                     HSW_PWR_WELL_STATE_ENABLED,
 372                                                     20))
 373                                 DRM_ERROR("Timeout enabling power well\n");
 374                         hsw_power_well_post_enable(dev_priv);
 375                 }
 376
 377         } else {
 378                 if (enable_requested) {
 379                         hsw_power_well_pre_disable(dev_priv);
 380                         I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
 381                         POSTING_READ(HSW_PWR_WELL_DRIVER);
 382                         DRM_DEBUG_KMS("Requesting to disable the power well\n");
 383                 }
 384         }
 385 }
 386
 387 #define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS (         \
 388         BIT(POWER_DOMAIN_TRANSCODER_A) |                \
 389         BIT(POWER_DOMAIN_PIPE_B) |                      \
 390         BIT(POWER_DOMAIN_TRANSCODER_B) |                \
 391         BIT(POWER_DOMAIN_PIPE_C) |                      \
 392         BIT(POWER_DOMAIN_TRANSCODER_C) |                \
 393         BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |         \
 394         BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |         \
 395         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |            \
 396         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |            \
 397         BIT(POWER_DOMAIN_PORT_DDI_D_LANES) |            \
 398         BIT(POWER_DOMAIN_PORT_DDI_E_LANES) |            \
 399         BIT(POWER_DOMAIN_AUX_B) |                       \
 400         BIT(POWER_DOMAIN_AUX_C) |                       \
 401         BIT(POWER_DOMAIN_AUX_D) |                       \
 402         BIT(POWER_DOMAIN_AUDIO) |                       \
 403         BIT(POWER_DOMAIN_VGA) |                         \
 404         BIT(POWER_DOMAIN_INIT))
 405 #define SKL_DISPLAY_DDI_A_E_POWER_DOMAINS (             \
 406         BIT(POWER_DOMAIN_PORT_DDI_A_LANES) |            \
 407         BIT(POWER_DOMAIN_PORT_DDI_E_LANES) |            \
 408         BIT(POWER_DOMAIN_INIT))
 409 #define SKL_DISPLAY_DDI_B_POWER_DOMAINS (               \
 410         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |            \
 411         BIT(POWER_DOMAIN_INIT))
 412 #define SKL_DISPLAY_DDI_C_POWER_DOMAINS (               \
 413         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |            \
 414         BIT(POWER_DOMAIN_INIT))
 415 #define SKL_DISPLAY_DDI_D_POWER_DOMAINS (               \
 416         BIT(POWER_DOMAIN_PORT_DDI_D_LANES) |            \
 417         BIT(POWER_DOMAIN_INIT))
 418 #define SKL_DISPLAY_DC_OFF_POWER_DOMAINS (              \
 419         SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS |         \
 420         BIT(POWER_DOMAIN_MODESET) |                     \
 421         BIT(POWER_DOMAIN_AUX_A) |                       \
 422         BIT(POWER_DOMAIN_INIT))
 423
 424 #define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS (         \
 425         BIT(POWER_DOMAIN_TRANSCODER_A) |                \
 426         BIT(POWER_DOMAIN_PIPE_B) |                      \
 427         BIT(POWER_DOMAIN_TRANSCODER_B) |                \
 428         BIT(POWER_DOMAIN_PIPE_C) |                      \
 429         BIT(POWER_DOMAIN_TRANSCODER_C) |                \
 430         BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |         \
 431         BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |         \
 432         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |            \
 433         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |            \
 434         BIT(POWER_DOMAIN_AUX_B) |                       \
 435         BIT(POWER_DOMAIN_AUX_C) |                       \
 436         BIT(POWER_DOMAIN_AUDIO) |                       \
 437         BIT(POWER_DOMAIN_VGA) |                         \
 438         BIT(POWER_DOMAIN_GMBUS) |                       \
 439         BIT(POWER_DOMAIN_INIT))
 440 #define BXT_DISPLAY_DC_OFF_POWER_DOMAINS (              \
 441         BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS |         \
 442         BIT(POWER_DOMAIN_MODESET) |                     \
 443         BIT(POWER_DOMAIN_AUX_A) |                       \
 444         BIT(POWER_DOMAIN_INIT))
 445 #define BXT_DPIO_CMN_A_POWER_DOMAINS (                  \
 446         BIT(POWER_DOMAIN_PORT_DDI_A_LANES) |            \
 447         BIT(POWER_DOMAIN_AUX_A) |                       \
 448         BIT(POWER_DOMAIN_INIT))
 449 #define BXT_DPIO_CMN_BC_POWER_DOMAINS (                 \
 450         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |            \
 451         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |            \
 452         BIT(POWER_DOMAIN_AUX_B) |                       \
 453         BIT(POWER_DOMAIN_AUX_C) |                       \
 454         BIT(POWER_DOMAIN_INIT))
 455
 456 static void assert_can_enable_dc9(struct drm_i915_private *dev_priv)
 457 {
 458         WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9),
 459                   "DC9 already programmed to be enabled.\n");
 460         WARN_ONCE(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
 461                   "DC5 still not disabled to enable DC9.\n");
 462         WARN_ONCE(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on.\n");
 463         WARN_ONCE(intel_irqs_enabled(dev_priv),
 464                   "Interrupts not disabled yet.\n");
 465
 466          /*
 467           * TODO: check for the following to verify the conditions to enter DC9
 468           * state are satisfied:
 469           * 1] Check relevant display engine registers to verify if mode set
 470           * disable sequence was followed.
 471           * 2] Check if display uninitialize sequence is initialized.
 472           */
 473 }
 474
 475 static void assert_can_disable_dc9(struct drm_i915_private *dev_priv)
 476 {
 477         WARN_ONCE(intel_irqs_enabled(dev_priv),
 478                   "Interrupts not disabled yet.\n");
 479         WARN_ONCE(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
 480                   "DC5 still not disabled.\n");
 481
 482          /*
 483           * TODO: check for the following to verify DC9 state was indeed
 484           * entered before programming to disable it:
 485           * 1] Check relevant display engine registers to verify if mode
 486           *  set disable sequence was followed.
 487           * 2] Check if display uninitialize sequence is initialized.
 488           */
 489 }
 490
 491 static void gen9_write_dc_state(struct drm_i915_private *dev_priv,
 492                                 u32 state)
 493 {
 494         int rewrites = 0;
 495         int rereads = 0;
 496         u32 v;
 497
 498         I915_WRITE(DC_STATE_EN, state);
 499
 500         /* It has been observed that disabling the dc6 state sometimes
 501          * doesn't stick and dmc keeps returning old value. Make sure
 502          * the write really sticks enough times and also force rewrite until
 503          * we are confident that state is exactly what we want.
 504          */
 505         do  {
 506                 v = I915_READ(DC_STATE_EN);
 507
 508                 if (v != state) {
 509                         I915_WRITE(DC_STATE_EN, state);
 510                         rewrites++;
 511                         rereads = 0;
 512                 } else if (rereads++ > 5) {
 513                         break;
 514                 }
 515
 516         } while (rewrites < 100);
 517
 518         if (v != state)
 519                 DRM_ERROR("Writing dc state to 0x%x failed, now 0x%x\n",
 520                           state, v);
 521
 522         /* Most of the times we need one retry, avoid spam */
 523         if (rewrites > 1)
 524                 DRM_DEBUG_KMS("Rewrote dc state to 0x%x %d times\n",
 525                               state, rewrites);
 526 }
 527
 528 static u32 gen9_dc_mask(struct drm_i915_private *dev_priv)
 529 {
 530         u32 mask;
 531
 532         mask = DC_STATE_EN_UPTO_DC5;
 533         if (IS_BROXTON(dev_priv))
 534                 mask |= DC_STATE_EN_DC9;
 535         else
 536                 mask |= DC_STATE_EN_UPTO_DC6;
 537
 538         return mask;
 539 }
 540
 541 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv)
 542 {
 543         u32 val;
 544
 545         val = I915_READ(DC_STATE_EN) & gen9_dc_mask(dev_priv);
 546
 547         DRM_DEBUG_KMS("Resetting DC state tracking from %02x to %02x\n",
 548                       dev_priv->csr.dc_state, val);
 549         dev_priv->csr.dc_state = val;
 550 }
 551
 552 static void gen9_set_dc_state(struct drm_i915_private *dev_priv, uint32_t state)
 553 {
 554         uint32_t val;
 555         uint32_t mask;
 556
 557         if (WARN_ON_ONCE(state & ~dev_priv->csr.allowed_dc_mask))
 558                 state &= dev_priv->csr.allowed_dc_mask;
 559
 560         val = I915_READ(DC_STATE_EN);
 561         mask = gen9_dc_mask(dev_priv);
 562         DRM_DEBUG_KMS("Setting DC state from %02x to %02x\n",
 563                       val & mask, state);
 564
 565         /* Check if DMC is ignoring our DC state requests */
 566         if ((val & mask) != dev_priv->csr.dc_state)
 567                 DRM_ERROR("DC state mismatch (0x%x -> 0x%x)\n",
 568                           dev_priv->csr.dc_state, val & mask);
 569
 570         val &= ~mask;
 571         val |= state;
 572
 573         gen9_write_dc_state(dev_priv, val);
 574
 575         dev_priv->csr.dc_state = val & mask;
 576 }
 577
 578 void bxt_enable_dc9(struct drm_i915_private *dev_priv)
 579 {
 580         assert_can_enable_dc9(dev_priv);
 581
 582         DRM_DEBUG_KMS("Enabling DC9\n");
 583
 584         intel_power_sequencer_reset(dev_priv);
 585         gen9_set_dc_state(dev_priv, DC_STATE_EN_DC9);
 586 }
 587
 588 void bxt_disable_dc9(struct drm_i915_private *dev_priv)
 589 {
 590         assert_can_disable_dc9(dev_priv);
 591
 592         DRM_DEBUG_KMS("Disabling DC9\n");
 593
 594         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 595 }
 596
 597 static void assert_csr_loaded(struct drm_i915_private *dev_priv)
 598 {
 599         WARN_ONCE(!I915_READ(CSR_PROGRAM(0)),
 600                   "CSR program storage start is NULL\n");
 601         WARN_ONCE(!I915_READ(CSR_SSP_BASE), "CSR SSP Base Not fine\n");
 602         WARN_ONCE(!I915_READ(CSR_HTP_SKL), "CSR HTP Not fine\n");
 603 }
 604
 605 static void assert_can_enable_dc5(struct drm_i915_private *dev_priv)
 606 {
 607         bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv,
 608                                         SKL_DISP_PW_2);
 609
 610         WARN_ONCE(pg2_enabled, "PG2 not disabled to enable DC5.\n");
 611
 612         WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5),
 613                   "DC5 already programmed to be enabled.\n");
 614         assert_rpm_wakelock_held(dev_priv);
 615
 616         assert_csr_loaded(dev_priv);
 617 }
 618
 619 void gen9_enable_dc5(struct drm_i915_private *dev_priv)
 620 {
 621         assert_can_enable_dc5(dev_priv);
 622
 623         DRM_DEBUG_KMS("Enabling DC5\n");
 624
 625         gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5);
 626 }
 627
 628 static void assert_can_enable_dc6(struct drm_i915_private *dev_priv)
 629 {
 630         WARN_ONCE(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
 631                   "Backlight is not disabled.\n");
 632         WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6),
 633                   "DC6 already programmed to be enabled.\n");
 634
 635         assert_csr_loaded(dev_priv);
 636 }
 637
 638 void skl_enable_dc6(struct drm_i915_private *dev_priv)
 639 {
 640         assert_can_enable_dc6(dev_priv);
 641
 642         DRM_DEBUG_KMS("Enabling DC6\n");
 643
 644         gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
 645
 646 }
 647
 648 void skl_disable_dc6(struct drm_i915_private *dev_priv)
 649 {
 650         DRM_DEBUG_KMS("Disabling DC6\n");
 651
 652         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 653 }
 654
 655 static void
 656 gen9_sanitize_power_well_requests(struct drm_i915_private *dev_priv,
 657                                   struct i915_power_well *power_well)
 658 {
 659         enum skl_disp_power_wells power_well_id = power_well->data;
 660         u32 val;
 661         u32 mask;
 662
 663         mask = SKL_POWER_WELL_REQ(power_well_id);
 664
 665         val = I915_READ(HSW_PWR_WELL_KVMR);
 666         if (WARN_ONCE(val & mask, "Clearing unexpected KVMR request for %s\n",
 667                       power_well->name))
 668                 I915_WRITE(HSW_PWR_WELL_KVMR, val & ~mask);
 669
 670         val = I915_READ(HSW_PWR_WELL_BIOS);
 671         val |= I915_READ(HSW_PWR_WELL_DEBUG);
 672
 673         if (!(val & mask))
 674                 return;
 675
 676         /*
 677          * DMC is known to force on the request bits for power well 1 on SKL
 678          * and BXT and the misc IO power well on SKL but we don't expect any
 679          * other request bits to be set, so WARN for those.
 680          */
 681         if (power_well_id == SKL_DISP_PW_1 ||
 682             ((IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) &&
 683              power_well_id == SKL_DISP_PW_MISC_IO))
 684                 DRM_DEBUG_DRIVER("Clearing auxiliary requests for %s forced on "
 685                                  "by DMC\n", power_well->name);
 686         else
 687                 WARN_ONCE(1, "Clearing unexpected auxiliary requests for %s\n",
 688                           power_well->name);
 689
 690         I915_WRITE(HSW_PWR_WELL_BIOS, val & ~mask);
 691         I915_WRITE(HSW_PWR_WELL_DEBUG, val & ~mask);
 692 }
 693
 694 static void skl_set_power_well(struct drm_i915_private *dev_priv,
 695                         struct i915_power_well *power_well, bool enable)
 696 {
 697         uint32_t tmp, fuse_status;
 698         uint32_t req_mask, state_mask;
 699         bool is_enabled, enable_requested, check_fuse_status = false;
 700
 701         tmp = I915_READ(HSW_PWR_WELL_DRIVER);
 702         fuse_status = I915_READ(SKL_FUSE_STATUS);
 703
 704         switch (power_well->data) {
 705         case SKL_DISP_PW_1:
 706                 if (intel_wait_for_register(dev_priv,
 707                                             SKL_FUSE_STATUS,
 708                                             SKL_FUSE_PG0_DIST_STATUS,
 709                                             SKL_FUSE_PG0_DIST_STATUS,
 710                                             1)) {
 711                         DRM_ERROR("PG0 not enabled\n");
 712                         return;
 713                 }
 714                 break;
 715         case SKL_DISP_PW_2:
 716                 if (!(fuse_status & SKL_FUSE_PG1_DIST_STATUS)) {
 717                         DRM_ERROR("PG1 in disabled state\n");
 718                         return;
 719                 }
 720                 break;
 721         case SKL_DISP_PW_DDI_A_E:
 722         case SKL_DISP_PW_DDI_B:
 723         case SKL_DISP_PW_DDI_C:
 724         case SKL_DISP_PW_DDI_D:
 725         case SKL_DISP_PW_MISC_IO:
 726                 break;
 727         default:
 728                 WARN(1, "Unknown power well %lu\n", power_well->data);
 729                 return;
 730         }
 731
 732         req_mask = SKL_POWER_WELL_REQ(power_well->data);
 733         enable_requested = tmp & req_mask;
 734         state_mask = SKL_POWER_WELL_STATE(power_well->data);
 735         is_enabled = tmp & state_mask;
 736
 737         if (!enable && enable_requested)
 738                 skl_power_well_pre_disable(dev_priv, power_well);
 739
 740         if (enable) {
 741                 if (!enable_requested) {
 742                         WARN((tmp & state_mask) &&
 743                                 !I915_READ(HSW_PWR_WELL_BIOS),
 744                                 "Invalid for power well status to be enabled, unless done by the BIOS, \
 745                                 when request is to disable!\n");
 746                         I915_WRITE(HSW_PWR_WELL_DRIVER, tmp | req_mask);
 747                 }
 748
 749                 if (!is_enabled) {
 750                         DRM_DEBUG_KMS("Enabling %s\n", power_well->name);
 751                         check_fuse_status = true;
 752                 }
 753         } else {
 754                 if (enable_requested) {
 755                         I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask);
 756                         POSTING_READ(HSW_PWR_WELL_DRIVER);
 757                         DRM_DEBUG_KMS("Disabling %s\n", power_well->name);
 758                 }
 759
 760                 if (IS_GEN9(dev_priv))
 761                         gen9_sanitize_power_well_requests(dev_priv, power_well);
 762         }
 763
 764         if (wait_for(!!(I915_READ(HSW_PWR_WELL_DRIVER) & state_mask) == enable,
 765                      1))
 766                 DRM_ERROR("%s %s timeout\n",
 767                           power_well->name, enable ? "enable" : "disable");
 768
 769         if (check_fuse_status) {
 770                 if (power_well->data == SKL_DISP_PW_1) {
 771                         if (intel_wait_for_register(dev_priv,
 772                                                     SKL_FUSE_STATUS,
 773                                                     SKL_FUSE_PG1_DIST_STATUS,
 774                                                     SKL_FUSE_PG1_DIST_STATUS,
 775                                                     1))
 776                                 DRM_ERROR("PG1 distributing status timeout\n");
 777                 } else if (power_well->data == SKL_DISP_PW_2) {
 778                         if (intel_wait_for_register(dev_priv,
 779                                                     SKL_FUSE_STATUS,
 780                                                     SKL_FUSE_PG2_DIST_STATUS,
 781                                                     SKL_FUSE_PG2_DIST_STATUS,
 782                                                     1))
 783                                 DRM_ERROR("PG2 distributing status timeout\n");
 784                 }
 785         }
 786
 787         if (enable && !is_enabled)
 788                 skl_power_well_post_enable(dev_priv, power_well);
 789 }
 790
 791 static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
 792                                    struct i915_power_well *power_well)
 793 {
 794         hsw_set_power_well(dev_priv, power_well, power_well->count > 0);
 795
 796         /*
 797          * We're taking over the BIOS, so clear any requests made by it since
 798          * the driver is in charge now.
 799          */
 800         if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
 801                 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
 802 }
 803
 804 static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
 805                                   struct i915_power_well *power_well)
 806 {
 807         hsw_set_power_well(dev_priv, power_well, true);
 808 }
 809
 810 static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
 811                                    struct i915_power_well *power_well)
 812 {
 813         hsw_set_power_well(dev_priv, power_well, false);
 814 }
 815
 816 static bool skl_power_well_enabled(struct drm_i915_private *dev_priv,
 817                                         struct i915_power_well *power_well)
 818 {
 819         uint32_t mask = SKL_POWER_WELL_REQ(power_well->data) |
 820                 SKL_POWER_WELL_STATE(power_well->data);
 821
 822         return (I915_READ(HSW_PWR_WELL_DRIVER) & mask) == mask;
 823 }
 824
 825 static void skl_power_well_sync_hw(struct drm_i915_private *dev_priv,
 826                                 struct i915_power_well *power_well)
 827 {
 828         skl_set_power_well(dev_priv, power_well, power_well->count > 0);
 829
 830         /* Clear any request made by BIOS as driver is taking over */
 831         I915_WRITE(HSW_PWR_WELL_BIOS, 0);
 832 }
 833
 834 static void skl_power_well_enable(struct drm_i915_private *dev_priv,
 835                                 struct i915_power_well *power_well)
 836 {
 837         skl_set_power_well(dev_priv, power_well, true);
 838 }
 839
 840 static void skl_power_well_disable(struct drm_i915_private *dev_priv,
 841                                 struct i915_power_well *power_well)
 842 {
 843         skl_set_power_well(dev_priv, power_well, false);
 844 }
 845
 846 static enum dpio_phy bxt_power_well_to_phy(struct i915_power_well *power_well)
 847 {
 848         enum skl_disp_power_wells power_well_id = power_well->data;
 849
 850         return power_well_id == BXT_DPIO_CMN_A ? DPIO_PHY1 : DPIO_PHY0;
 851 }
 852
 853 static void bxt_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
 854                                            struct i915_power_well *power_well)
 855 {
 856         enum skl_disp_power_wells power_well_id = power_well->data;
 857         struct i915_power_well *cmn_a_well;
 858
 859         if (power_well_id == BXT_DPIO_CMN_BC) {
 860                 /*
 861                  * We need to copy the GRC calibration value from the eDP PHY,
 862                  * so make sure it's powered up.
 863                  */
 864                 cmn_a_well = lookup_power_well(dev_priv, BXT_DPIO_CMN_A);
 865                 intel_power_well_get(dev_priv, cmn_a_well);
 866         }
 867
 868         bxt_ddi_phy_init(dev_priv, bxt_power_well_to_phy(power_well));
 869
 870         if (power_well_id == BXT_DPIO_CMN_BC)
 871                 intel_power_well_put(dev_priv, cmn_a_well);
 872 }
 873
 874 static void bxt_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
 875                                             struct i915_power_well *power_well)
 876 {
 877         bxt_ddi_phy_uninit(dev_priv, bxt_power_well_to_phy(power_well));
 878 }
 879
 880 static bool bxt_dpio_cmn_power_well_enabled(struct drm_i915_private *dev_priv,
 881                                             struct i915_power_well *power_well)
 882 {
 883         return bxt_ddi_phy_is_enabled(dev_priv,
 884                                       bxt_power_well_to_phy(power_well));
 885 }
 886
 887 static void bxt_dpio_cmn_power_well_sync_hw(struct drm_i915_private *dev_priv,
 888                                             struct i915_power_well *power_well)
 889 {
 890         if (power_well->count > 0)
 891                 bxt_dpio_cmn_power_well_enable(dev_priv, power_well);
 892         else
 893                 bxt_dpio_cmn_power_well_disable(dev_priv, power_well);
 894 }
 895
 896
 897 static void bxt_verify_ddi_phy_power_wells(struct drm_i915_private *dev_priv)
 898 {
 899         struct i915_power_well *power_well;
 900
 901         power_well = lookup_power_well(dev_priv, BXT_DPIO_CMN_A);
 902         if (power_well->count > 0)
 903                 bxt_ddi_phy_verify_state(dev_priv,
 904                                          bxt_power_well_to_phy(power_well));
 905
 906         power_well = lookup_power_well(dev_priv, BXT_DPIO_CMN_BC);
 907         if (power_well->count > 0)
 908                 bxt_ddi_phy_verify_state(dev_priv,
 909                                          bxt_power_well_to_phy(power_well));
 910 }
 911
 912 static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv,
 913                                            struct i915_power_well *power_well)
 914 {
 915         return (I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0;
 916 }
 917
 918 static void gen9_assert_dbuf_enabled(struct drm_i915_private *dev_priv)
 919 {
 920         u32 tmp = I915_READ(DBUF_CTL);
 921
 922         WARN((tmp & (DBUF_POWER_STATE | DBUF_POWER_REQUEST)) !=
 923              (DBUF_POWER_STATE | DBUF_POWER_REQUEST),
 924              "Unexpected DBuf power power state (0x%08x)\n", tmp);
 925 }
 926
 927 static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
 928                                           struct i915_power_well *power_well)
 929 {
 930         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 931
 932         WARN_ON(dev_priv->cdclk_freq !=
 933                 dev_priv->display.get_display_clock_speed(dev_priv->dev));
 934
 935         gen9_assert_dbuf_enabled(dev_priv);
 936
 937         if (IS_BROXTON(dev_priv))
 938                 bxt_verify_ddi_phy_power_wells(dev_priv);
 939 }
 940
 941 static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
 942                                            struct i915_power_well *power_well)
 943 {
 944         if (!dev_priv->csr.dmc_payload)
 945                 return;
 946
 947         if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC6)
 948                 skl_enable_dc6(dev_priv);
 949         else if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5)
 950                 gen9_enable_dc5(dev_priv);
 951 }
 952
 953 static void gen9_dc_off_power_well_sync_hw(struct drm_i915_private *dev_priv,
 954                                            struct i915_power_well *power_well)
 955 {
 956         if (power_well->count > 0)
 957                 gen9_dc_off_power_well_enable(dev_priv, power_well);
 958         else
 959                 gen9_dc_off_power_well_disable(dev_priv, power_well);
 960 }
 961
 962 static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,
 963                                            struct i915_power_well *power_well)
 964 {
 965 }
 966
 967 static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,
 968                                              struct i915_power_well *power_well)
 969 {
 970         return true;
 971 }
 972
 973 static void vlv_set_power_well(struct drm_i915_private *dev_priv,
 974                                struct i915_power_well *power_well, bool enable)
 975 {
 976         enum punit_power_well power_well_id = power_well->data;
 977         u32 mask;
 978         u32 state;
 979         u32 ctrl;
 980
 981         mask = PUNIT_PWRGT_MASK(power_well_id);
 982         state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) :
 983                          PUNIT_PWRGT_PWR_GATE(power_well_id);
 984
 985         mutex_lock(&dev_priv->rps.hw_lock);
 986
 987 #define COND \
 988         ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)
 989
 990         if (COND)
 991                 goto out;
 992
 993         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL);
 994         ctrl &= ~mask;
 995         ctrl |= state;
 996         vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl);
 997
 998         if (wait_for(COND, 100))
 999                 DRM_ERROR("timeout setting power well state %08x (%08x)\n",
1000                           state,
1001                           vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL));
1002
1003 #undef COND
1004
1005 out:
1006         mutex_unlock(&dev_priv->rps.hw_lock);
1007 }
1008
1009 static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv,
1010                                    struct i915_power_well *power_well)
1011 {
1012         vlv_set_power_well(dev_priv, power_well, power_well->count > 0);
1013 }
1014
1015 static void vlv_power_well_enable(struct drm_i915_private *dev_priv,
1016                                   struct i915_power_well *power_well)
1017 {
1018         vlv_set_power_well(dev_priv, power_well, true);
1019 }
1020
1021 static void vlv_power_well_disable(struct drm_i915_private *dev_priv,
1022                                    struct i915_power_well *power_well)
1023 {
1024         vlv_set_power_well(dev_priv, power_well, false);
1025 }
1026
1027 static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
1028                                    struct i915_power_well *power_well)
1029 {
1030         int power_well_id = power_well->data;
1031         bool enabled = false;
1032         u32 mask;
1033         u32 state;
1034         u32 ctrl;
1035
1036         mask = PUNIT_PWRGT_MASK(power_well_id);
1037         ctrl = PUNIT_PWRGT_PWR_ON(power_well_id);
1038
1039         mutex_lock(&dev_priv->rps.hw_lock);
1040
1041         state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask;
1042         /*
1043          * We only ever set the power-on and power-gate states, anything
1044          * else is unexpected.
1045          */
1046         WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) &&
1047                 state != PUNIT_PWRGT_PWR_GATE(power_well_id));
1048         if (state == ctrl)
1049                 enabled = true;
1050
1051         /*
1052          * A transient state at this point would mean some unexpected party
1053          * is poking at the power controls too.
1054          */
1055         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask;
1056         WARN_ON(ctrl != state);
1057
1058         mutex_unlock(&dev_priv->rps.hw_lock);
1059
1060         return enabled;
1061 }
1062
1063 static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
1064 {
1065         I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
1066
1067         /*
1068          * Disable trickle feed and enable pnd deadline calculation
1069          */
1070         I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
1071         I915_WRITE(CBR1_VLV, 0);
1072
1073         WARN_ON(dev_priv->rawclk_freq == 0);
1074
1075         I915_WRITE(RAWCLK_FREQ_VLV,
1076                    DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 1000));
1077 }
1078
1079 static void vlv_display_power_well_init(struct drm_i915_private *dev_priv)
1080 {
1081         enum pipe pipe;
1082
1083         /*
1084          * Enable the CRI clock source so we can get at the
1085          * display and the reference clock for VGA
1086          * hotplug / manual detection. Supposedly DSI also
1087          * needs the ref clock up and running.
1088          *
1089          * CHV DPLL B/C have some issues if VGA mode is enabled.
1090          */
1091         for_each_pipe(dev_priv->dev, pipe) {
1092                 u32 val = I915_READ(DPLL(pipe));
1093
1094                 val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1095                 if (pipe != PIPE_A)
1096                         val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1097
1098                 I915_WRITE(DPLL(pipe), val);
1099         }
1100
1101         vlv_init_display_clock_gating(dev_priv);
1102
1103         spin_lock_irq(&dev_priv->irq_lock);
1104         valleyview_enable_display_irqs(dev_priv);
1105         spin_unlock_irq(&dev_priv->irq_lock);
1106
1107         /*
1108          * During driver initialization/resume we can avoid restoring the
1109          * part of the HW/SW state that will be inited anyway explicitly.
1110          */
1111         if (dev_priv->power_domains.initializing)
1112                 return;
1113
1114         intel_hpd_init(dev_priv);
1115
1116         i915_redisable_vga_power_on(dev_priv->dev);
1117 }
1118
1119 static void vlv_display_power_well_deinit(struct drm_i915_private *dev_priv)
1120 {
1121         spin_lock_irq(&dev_priv->irq_lock);
1122         valleyview_disable_display_irqs(dev_priv);
1123         spin_unlock_irq(&dev_priv->irq_lock);
1124
1125         /* make sure we're done processing display irqs */
1126         synchronize_irq(dev_priv->dev->irq);
1127
1128         intel_power_sequencer_reset(dev_priv);
1129 }
1130
1131 static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv,
1132                                           struct i915_power_well *power_well)
1133 {
1134         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
1135
1136         vlv_set_power_well(dev_priv, power_well, true);
1137
1138         vlv_display_power_well_init(dev_priv);
1139 }
1140
1141 static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv,
1142                                            struct i915_power_well *power_well)
1143 {
1144         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
1145
1146         vlv_display_power_well_deinit(dev_priv);
1147
1148         vlv_set_power_well(dev_priv, power_well, false);
1149 }
1150
1151 static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
1152                                            struct i915_power_well *power_well)
1153 {
1154         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
1155
1156         /* since ref/cri clock was enabled */
1157         udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
1158
1159         vlv_set_power_well(dev_priv, power_well, true);
1160
1161         /*
1162          * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1163          *  6.  De-assert cmn_reset/side_reset. Same as VLV X0.
1164          *   a. GUnit 0x2110 bit[0] set to 1 (def 0)
1165          *   b. The other bits such as sfr settings / modesel may all
1166          *      be set to 0.
1167          *
1168          * This should only be done on init and resume from S3 with
1169          * both PLLs disabled, or we risk losing DPIO and PLL
1170          * synchronization.
1171          */
1172         I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
1173 }
1174
1175 static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
1176                                             struct i915_power_well *power_well)
1177 {
1178         enum pipe pipe;
1179
1180         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
1181
1182         for_each_pipe(dev_priv, pipe)
1183                 assert_pll_disabled(dev_priv, pipe);
1184
1185         /* Assert common reset */
1186         I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST);
1187
1188         vlv_set_power_well(dev_priv, power_well, false);
1189 }
1190
1191 #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
1192
1193 static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv,
1194                                                  int power_well_id)
1195 {
1196         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1197         int i;
1198
1199         for (i = 0; i < power_domains->power_well_count; i++) {
1200                 struct i915_power_well *power_well;
1201
1202                 power_well = &power_domains->power_wells[i];
1203                 if (power_well->data == power_well_id)
1204                         return power_well;
1205         }
1206
1207         return NULL;
1208 }
1209
1210 #define BITS_SET(val, bits) (((val) & (bits)) == (bits))
1211
1212 static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
1213 {
1214         struct i915_power_well *cmn_bc =
1215                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
1216         struct i915_power_well *cmn_d =
1217                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D);
1218         u32 phy_control = dev_priv->chv_phy_control;
1219         u32 phy_status = 0;
1220         u32 phy_status_mask = 0xffffffff;
1221
1222         /*
1223          * The BIOS can leave the PHY is some weird state
1224          * where it doesn't fully power down some parts.
1225          * Disable the asserts until the PHY has been fully
1226          * reset (ie. the power well has been disabled at
1227          * least once).
1228          */
1229         if (!dev_priv->chv_phy_assert[DPIO_PHY0])
1230                 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0) |
1231                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0) |
1232                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1) |
1233                                      PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1) |
1234                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0) |
1235                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1));
1236
1237         if (!dev_priv->chv_phy_assert[DPIO_PHY1])
1238                 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0) |
1239                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0) |
1240                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1));
1241
1242         if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) {
1243                 phy_status |= PHY_POWERGOOD(DPIO_PHY0);
1244
1245                 /* this assumes override is only used to enable lanes */
1246                 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0)) == 0)
1247                         phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0);
1248
1249                 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1)) == 0)
1250                         phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1);
1251
1252                 /* CL1 is on whenever anything is on in either channel */
1253                 if (BITS_SET(phy_control,
1254                              PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0) |
1255                              PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)))
1256                         phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0);
1257
1258                 /*
1259                  * The DPLLB check accounts for the pipe B + port A usage
1260                  * with CL2 powered up but all the lanes in the second channel
1261                  * powered down.
1262                  */
1263                 if (BITS_SET(phy_control,
1264                              PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)) &&
1265                     (I915_READ(DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0)
1266                         phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1);
1267
1268                 if (BITS_SET(phy_control,
1269                              PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH0)))
1270                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0);
1271                 if (BITS_SET(phy_control,
1272                              PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH0)))
1273                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1);
1274
1275                 if (BITS_SET(phy_control,
1276                              PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH1)))
1277                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0);
1278                 if (BITS_SET(phy_control,
1279                              PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH1)))
1280                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1);
1281         }
1282
1283         if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) {
1284                 phy_status |= PHY_POWERGOOD(DPIO_PHY1);
1285
1286                 /* this assumes override is only used to enable lanes */
1287                 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0)) == 0)
1288                         phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0);
1289
1290                 if (BITS_SET(phy_control,
1291                              PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0)))
1292                         phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0);
1293
1294                 if (BITS_SET(phy_control,
1295                              PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY1, DPIO_CH0)))
1296                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0);
1297                 if (BITS_SET(phy_control,
1298                              PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY1, DPIO_CH0)))
1299                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1);
1300         }
1301
1302         phy_status &= phy_status_mask;
1303
1304         /*
1305          * The PHY may be busy with some initial calibration and whatnot,
1306          * so the power state can take a while to actually change.
1307          */
1308         if (intel_wait_for_register(dev_priv,
1309                                     DISPLAY_PHY_STATUS,
1310                                     phy_status_mask,
1311                                     phy_status,
1312                                     10))
1313                 DRM_ERROR("Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n",
1314                           I915_READ(DISPLAY_PHY_STATUS) & phy_status_mask,
1315                            phy_status, dev_priv->chv_phy_control);
1316 }
1317
1318 #undef BITS_SET
1319
1320 static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
1321                                            struct i915_power_well *power_well)
1322 {
1323         enum dpio_phy phy;
1324         enum pipe pipe;
1325         uint32_t tmp;
1326
1327         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
1328                      power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
1329
1330         if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
1331                 pipe = PIPE_A;
1332                 phy = DPIO_PHY0;
1333         } else {
1334                 pipe = PIPE_C;
1335                 phy = DPIO_PHY1;
1336         }
1337
1338         /* since ref/cri clock was enabled */
1339         udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
1340         vlv_set_power_well(dev_priv, power_well, true);
1341
1342         /* Poll for phypwrgood signal */
1343         if (intel_wait_for_register(dev_priv,
1344                                     DISPLAY_PHY_STATUS,
1345                                     PHY_POWERGOOD(phy),
1346                                     PHY_POWERGOOD(phy),
1347                                     1))
1348                 DRM_ERROR("Display PHY %d is not power up\n", phy);
1349
1350         mutex_lock(&dev_priv->sb_lock);
1351
1352         /* Enable dynamic power down */
1353         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW28);
1354         tmp |= DPIO_DYNPWRDOWNEN_CH0 | DPIO_CL1POWERDOWNEN |
1355                 DPIO_SUS_CLK_CONFIG_GATE_CLKREQ;
1356         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW28, tmp);
1357
1358         if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
1359                 tmp = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW6_CH1);
1360                 tmp |= DPIO_DYNPWRDOWNEN_CH1;
1361                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW6_CH1, tmp);
1362         } else {
1363                 /*
1364                  * Force the non-existing CL2 off. BXT does this
1365                  * too, so maybe it saves some power even though
1366                  * CL2 doesn't exist?
1367                  */
1368                 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
1369                 tmp |= DPIO_CL2_LDOFUSE_PWRENB;
1370                 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, tmp);
1371         }
1372
1373         mutex_unlock(&dev_priv->sb_lock);
1374
1375         dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy);
1376         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1377
1378         DRM_DEBUG_KMS("Enabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
1379                       phy, dev_priv->chv_phy_control);
1380
1381         assert_chv_phy_status(dev_priv);
1382 }
1383
1384 static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
1385                                             struct i915_power_well *power_well)
1386 {
1387         enum dpio_phy phy;
1388
1389         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
1390                      power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
1391
1392         if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
1393                 phy = DPIO_PHY0;
1394                 assert_pll_disabled(dev_priv, PIPE_A);
1395                 assert_pll_disabled(dev_priv, PIPE_B);
1396         } else {
1397                 phy = DPIO_PHY1;
1398                 assert_pll_disabled(dev_priv, PIPE_C);
1399         }
1400
1401         dev_priv->chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy);
1402         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1403
1404         vlv_set_power_well(dev_priv, power_well, false);
1405
1406         DRM_DEBUG_KMS("Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
1407                       phy, dev_priv->chv_phy_control);
1408
1409         /* PHY is fully reset now, so we can enable the PHY state asserts */
1410         dev_priv->chv_phy_assert[phy] = true;
1411
1412         assert_chv_phy_status(dev_priv);
1413 }
1414
1415 static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1416                                      enum dpio_channel ch, bool override, unsigned int mask)
1417 {
1418         enum pipe pipe = phy == DPIO_PHY0 ? PIPE_A : PIPE_C;
1419         u32 reg, val, expected, actual;
1420
1421         /*
1422          * The BIOS can leave the PHY is some weird state
1423          * where it doesn't fully power down some parts.
1424          * Disable the asserts until the PHY has been fully
1425          * reset (ie. the power well has been disabled at
1426          * least once).
1427          */
1428         if (!dev_priv->chv_phy_assert[phy])
1429                 return;
1430
1431         if (ch == DPIO_CH0)
1432                 reg = _CHV_CMN_DW0_CH0;
1433         else
1434                 reg = _CHV_CMN_DW6_CH1;
1435
1436         mutex_lock(&dev_priv->sb_lock);
1437         val = vlv_dpio_read(dev_priv, pipe, reg);
1438         mutex_unlock(&dev_priv->sb_lock);
1439
1440         /*
1441          * This assumes !override is only used when the port is disabled.
1442          * All lanes should power down even without the override when
1443          * the port is disabled.
1444          */
1445         if (!override || mask == 0xf) {
1446                 expected = DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN;
1447                 /*
1448                  * If CH1 common lane is not active anymore
1449                  * (eg. for pipe B DPLL) the entire channel will
1450                  * shut down, which causes the common lane registers
1451                  * to read as 0. That means we can't actually check
1452                  * the lane power down status bits, but as the entire
1453                  * register reads as 0 it's a good indication that the
1454                  * channel is indeed entirely powered down.
1455                  */
1456                 if (ch == DPIO_CH1 && val == 0)
1457                         expected = 0;
1458         } else if (mask != 0x0) {
1459                 expected = DPIO_ANYDL_POWERDOWN;
1460         } else {
1461                 expected = 0;
1462         }
1463
1464         if (ch == DPIO_CH0)
1465                 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH0;
1466         else
1467                 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH1;
1468         actual &= DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN;
1469
1470         WARN(actual != expected,
1471              "Unexpected DPIO lane power down: all %d, any %d. Expected: all %d, any %d. (0x%x = 0x%08x)\n",
1472              !!(actual & DPIO_ALLDL_POWERDOWN), !!(actual & DPIO_ANYDL_POWERDOWN),
1473              !!(expected & DPIO_ALLDL_POWERDOWN), !!(expected & DPIO_ANYDL_POWERDOWN),
1474              reg, val);
1475 }
1476
1477 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1478                           enum dpio_channel ch, bool override)
1479 {
1480         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1481         bool was_override;
1482
1483         mutex_lock(&power_domains->lock);
1484
1485         was_override = dev_priv->chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1486
1487         if (override == was_override)
1488                 goto out;
1489
1490         if (override)
1491                 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1492         else
1493                 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1494
1495         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1496
1497         DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d (DPIO_PHY_CONTROL=0x%08x)\n",
1498                       phy, ch, dev_priv->chv_phy_control);
1499
1500         assert_chv_phy_status(dev_priv);
1501
1502 out:
1503         mutex_unlock(&power_domains->lock);
1504
1505         return was_override;
1506 }
1507
1508 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1509                              bool override, unsigned int mask)
1510 {
1511         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1512         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1513         enum dpio_phy phy = vlv_dport_to_phy(enc_to_dig_port(&encoder->base));
1514         enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
1515
1516         mutex_lock(&power_domains->lock);
1517
1518         dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch);
1519         dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch);
1520
1521         if (override)
1522                 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1523         else
1524                 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1525
1526         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1527
1528         DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d lanes 0x%x (PHY_CONTROL=0x%08x)\n",
1529                       phy, ch, mask, dev_priv->chv_phy_control);
1530
1531         assert_chv_phy_status(dev_priv);
1532
1533         assert_chv_phy_powergate(dev_priv, phy, ch, override, mask);
1534
1535         mutex_unlock(&power_domains->lock);
1536 }
1537
1538 static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv,
1539                                         struct i915_power_well *power_well)
1540 {
1541         enum pipe pipe = power_well->data;
1542         bool enabled;
1543         u32 state, ctrl;
1544
1545         mutex_lock(&dev_priv->rps.hw_lock);
1546
1547         state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe);
1548         /*
1549          * We only ever set the power-on and power-gate states, anything
1550          * else is unexpected.
1551          */
1552         WARN_ON(state != DP_SSS_PWR_ON(pipe) && state != DP_SSS_PWR_GATE(pipe));
1553         enabled = state == DP_SSS_PWR_ON(pipe);
1554
1555         /*
1556          * A transient state at this point would mean some unexpected party
1557          * is poking at the power controls too.
1558          */
1559         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe);
1560         WARN_ON(ctrl << 16 != state);
1561
1562         mutex_unlock(&dev_priv->rps.hw_lock);
1563
1564         return enabled;
1565 }
1566
1567 static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv,
1568                                     struct i915_power_well *power_well,
1569                                     bool enable)
1570 {
1571         enum pipe pipe = power_well->data;
1572         u32 state;
1573         u32 ctrl;
1574
1575         state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe);
1576
1577         mutex_lock(&dev_priv->rps.hw_lock);
1578
1579 #define COND \
1580         ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state)
1581
1582         if (COND)
1583                 goto out;
1584
1585         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
1586         ctrl &= ~DP_SSC_MASK(pipe);
1587         ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe);
1588         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl);
1589
1590         if (wait_for(COND, 100))
1591                 DRM_ERROR("timeout setting power well state %08x (%08x)\n",
1592                           state,
1593                           vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ));
1594
1595 #undef COND
1596
1597 out:
1598         mutex_unlock(&dev_priv->rps.hw_lock);
1599 }
1600
1601 static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv,
1602                                         struct i915_power_well *power_well)
1603 {
1604         WARN_ON_ONCE(power_well->data != PIPE_A);
1605
1606         chv_set_pipe_power_well(dev_priv, power_well, power_well->count > 0);
1607 }
1608
1609 static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv,
1610                                        struct i915_power_well *power_well)
1611 {
1612         WARN_ON_ONCE(power_well->data != PIPE_A);
1613
1614         chv_set_pipe_power_well(dev_priv, power_well, true);
1615
1616         vlv_display_power_well_init(dev_priv);
1617 }
1618
1619 static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv,
1620                                         struct i915_power_well *power_well)
1621 {
1622         WARN_ON_ONCE(power_well->data != PIPE_A);
1623
1624         vlv_display_power_well_deinit(dev_priv);
1625
1626         chv_set_pipe_power_well(dev_priv, power_well, false);
1627 }
1628
1629 static void
1630 __intel_display_power_get_domain(struct drm_i915_private *dev_priv,
1631                                  enum intel_display_power_domain domain)
1632 {
1633         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1634         struct i915_power_well *power_well;
1635         int i;
1636
1637         for_each_power_well(i, power_well, BIT(domain), power_domains)
1638                 intel_power_well_get(dev_priv, power_well);
1639
1640         power_domains->domain_use_count[domain]++;
1641 }
1642
1643 /**
1644  * intel_display_power_get - grab a power domain reference
1645  * @dev_priv: i915 device instance
1646  * @domain: power domain to reference
1647  *
1648  * This function grabs a power domain reference for @domain and ensures that the
1649  * power domain and all its parents are powered up. Therefore users should only
1650  * grab a reference to the innermost power domain they need.
1651  *
1652  * Any power domain reference obtained by this function must have a symmetric
1653  * call to intel_display_power_put() to release the reference again.
1654  */
1655 void intel_display_power_get(struct drm_i915_private *dev_priv,
1656                              enum intel_display_power_domain domain)
1657 {
1658         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1659
1660         intel_runtime_pm_get(dev_priv);
1661
1662         mutex_lock(&power_domains->lock);
1663
1664         __intel_display_power_get_domain(dev_priv, domain);
1665
1666         mutex_unlock(&power_domains->lock);
1667 }
1668
1669 /**
1670  * intel_display_power_get_if_enabled - grab a reference for an enabled display power domain
1671  * @dev_priv: i915 device instance
1672  * @domain: power domain to reference
1673  *
1674  * This function grabs a power domain reference for @domain and ensures that the
1675  * power domain and all its parents are powered up. Therefore users should only
1676  * grab a reference to the innermost power domain they need.
1677  *
1678  * Any power domain reference obtained by this function must have a symmetric
1679  * call to intel_display_power_put() to release the reference again.
1680  */
1681 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
1682                                         enum intel_display_power_domain domain)
1683 {
1684         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1685         bool is_enabled;
1686
1687         if (!intel_runtime_pm_get_if_in_use(dev_priv))
1688                 return false;
1689
1690         mutex_lock(&power_domains->lock);
1691
1692         if (__intel_display_power_is_enabled(dev_priv, domain)) {
1693                 __intel_display_power_get_domain(dev_priv, domain);
1694                 is_enabled = true;
1695         } else {
1696                 is_enabled = false;
1697         }
1698
1699         mutex_unlock(&power_domains->lock);
1700
1701         if (!is_enabled)
1702                 intel_runtime_pm_put(dev_priv);
1703
1704         return is_enabled;
1705 }
1706
1707 /**
1708  * intel_display_power_put - release a power domain reference
1709  * @dev_priv: i915 device instance
1710  * @domain: power domain to reference
1711  *
1712  * This function drops the power domain reference obtained by
1713  * intel_display_power_get() and might power down the corresponding hardware
1714  * block right away if this is the last reference.
1715  */
1716 void intel_display_power_put(struct drm_i915_private *dev_priv,
1717                              enum intel_display_power_domain domain)
1718 {
1719         struct i915_power_domains *power_domains;
1720         struct i915_power_well *power_well;
1721         int i;
1722
1723         power_domains = &dev_priv->power_domains;
1724
1725         mutex_lock(&power_domains->lock);
1726
1727         WARN(!power_domains->domain_use_count[domain],
1728              "Use count on domain %s is already zero\n",
1729              intel_display_power_domain_str(domain));
1730         power_domains->domain_use_count[domain]--;
1731
1732         for_each_power_well_rev(i, power_well, BIT(domain), power_domains)
1733                 intel_power_well_put(dev_priv, power_well);
1734
1735         mutex_unlock(&power_domains->lock);
1736
1737         intel_runtime_pm_put(dev_priv);
1738 }
1739
1740 #define HSW_DISPLAY_POWER_DOMAINS (                     \
1741         BIT(POWER_DOMAIN_PIPE_B) |                      \
1742         BIT(POWER_DOMAIN_PIPE_C) |                      \
1743         BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) |         \
1744         BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |         \
1745         BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |         \
1746         BIT(POWER_DOMAIN_TRANSCODER_A) |                \
1747         BIT(POWER_DOMAIN_TRANSCODER_B) |                \
1748         BIT(POWER_DOMAIN_TRANSCODER_C) |                \
1749         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |            \
1750         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |            \
1751         BIT(POWER_DOMAIN_PORT_DDI_D_LANES) |            \
1752         BIT(POWER_DOMAIN_PORT_CRT) | /* DDI E */        \
1753         BIT(POWER_DOMAIN_VGA) |                         \
1754         BIT(POWER_DOMAIN_AUDIO) |                       \
1755         BIT(POWER_DOMAIN_INIT))
1756
1757 #define BDW_DISPLAY_POWER_DOMAINS (                     \
1758         BIT(POWER_DOMAIN_PIPE_B) |                      \
1759         BIT(POWER_DOMAIN_PIPE_C) |                      \
1760         BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |         \
1761         BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |         \
1762         BIT(POWER_DOMAIN_TRANSCODER_A) |                \
1763         BIT(POWER_DOMAIN_TRANSCODER_B) |                \
1764         BIT(POWER_DOMAIN_TRANSCODER_C) |                \
1765         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |            \
1766         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |            \
1767         BIT(POWER_DOMAIN_PORT_DDI_D_LANES) |            \
1768         BIT(POWER_DOMAIN_PORT_CRT) | /* DDI E */        \
1769         BIT(POWER_DOMAIN_VGA) |                         \
1770         BIT(POWER_DOMAIN_AUDIO) |                       \
1771         BIT(POWER_DOMAIN_INIT))
1772
1773 #define VLV_DISPLAY_POWER_DOMAINS (             \
1774         BIT(POWER_DOMAIN_PIPE_A) |              \
1775         BIT(POWER_DOMAIN_PIPE_B) |              \
1776         BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
1777         BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
1778         BIT(POWER_DOMAIN_TRANSCODER_A) |        \
1779         BIT(POWER_DOMAIN_TRANSCODER_B) |        \
1780         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |    \
1781         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |    \
1782         BIT(POWER_DOMAIN_PORT_DSI) |            \
1783         BIT(POWER_DOMAIN_PORT_CRT) |            \
1784         BIT(POWER_DOMAIN_VGA) |                 \
1785         BIT(POWER_DOMAIN_AUDIO) |               \
1786         BIT(POWER_DOMAIN_AUX_B) |               \
1787         BIT(POWER_DOMAIN_AUX_C) |               \
1788         BIT(POWER_DOMAIN_GMBUS) |               \
1789         BIT(POWER_DOMAIN_INIT))
1790
1791 #define VLV_DPIO_CMN_BC_POWER_DOMAINS (         \
1792         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |    \
1793         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |    \
1794         BIT(POWER_DOMAIN_PORT_CRT) |            \
1795         BIT(POWER_DOMAIN_AUX_B) |               \
1796         BIT(POWER_DOMAIN_AUX_C) |               \
1797         BIT(POWER_DOMAIN_INIT))
1798
1799 #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS (  \
1800         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |    \
1801         BIT(POWER_DOMAIN_AUX_B) |               \
1802         BIT(POWER_DOMAIN_INIT))
1803
1804 #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS (  \
1805         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |    \
1806         BIT(POWER_DOMAIN_AUX_B) |               \
1807         BIT(POWER_DOMAIN_INIT))
1808
1809 #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS (  \
1810         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |    \
1811         BIT(POWER_DOMAIN_AUX_C) |               \
1812         BIT(POWER_DOMAIN_INIT))
1813
1814 #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS (  \
1815         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |    \
1816         BIT(POWER_DOMAIN_AUX_C) |               \
1817         BIT(POWER_DOMAIN_INIT))
1818
1819 #define CHV_DISPLAY_POWER_DOMAINS (             \
1820         BIT(POWER_DOMAIN_PIPE_A) |              \
1821         BIT(POWER_DOMAIN_PIPE_B) |              \
1822         BIT(POWER_DOMAIN_PIPE_C) |              \
1823         BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
1824         BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
1825         BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
1826         BIT(POWER_DOMAIN_TRANSCODER_A) |        \
1827         BIT(POWER_DOMAIN_TRANSCODER_B) |        \
1828         BIT(POWER_DOMAIN_TRANSCODER_C) |        \
1829         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |    \
1830         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |    \
1831         BIT(POWER_DOMAIN_PORT_DDI_D_LANES) |    \
1832         BIT(POWER_DOMAIN_PORT_DSI) |            \
1833         BIT(POWER_DOMAIN_VGA) |                 \
1834         BIT(POWER_DOMAIN_AUDIO) |               \
1835         BIT(POWER_DOMAIN_AUX_B) |               \
1836         BIT(POWER_DOMAIN_AUX_C) |               \
1837         BIT(POWER_DOMAIN_AUX_D) |               \
1838         BIT(POWER_DOMAIN_GMBUS) |               \
1839         BIT(POWER_DOMAIN_INIT))
1840
1841 #define CHV_DPIO_CMN_BC_POWER_DOMAINS (         \
1842         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |    \
1843         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |    \
1844         BIT(POWER_DOMAIN_AUX_B) |               \
1845         BIT(POWER_DOMAIN_AUX_C) |               \
1846         BIT(POWER_DOMAIN_INIT))
1847
1848 #define CHV_DPIO_CMN_D_POWER_DOMAINS (          \
1849         BIT(POWER_DOMAIN_PORT_DDI_D_LANES) |    \
1850         BIT(POWER_DOMAIN_AUX_D) |               \
1851         BIT(POWER_DOMAIN_INIT))
1852
1853 static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
1854         .sync_hw = i9xx_always_on_power_well_noop,
1855         .enable = i9xx_always_on_power_well_noop,
1856         .disable = i9xx_always_on_power_well_noop,
1857         .is_enabled = i9xx_always_on_power_well_enabled,
1858 };
1859
1860 static const struct i915_power_well_ops chv_pipe_power_well_ops = {
1861         .sync_hw = chv_pipe_power_well_sync_hw,
1862         .enable = chv_pipe_power_well_enable,
1863         .disable = chv_pipe_power_well_disable,
1864         .is_enabled = chv_pipe_power_well_enabled,
1865 };
1866
1867 static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = {
1868         .sync_hw = vlv_power_well_sync_hw,
1869         .enable = chv_dpio_cmn_power_well_enable,
1870         .disable = chv_dpio_cmn_power_well_disable,
1871         .is_enabled = vlv_power_well_enabled,
1872 };
1873
1874 static struct i915_power_well i9xx_always_on_power_well[] = {
1875         {
1876                 .name = "always-on",
1877                 .always_on = 1,
1878                 .domains = POWER_DOMAIN_MASK,
1879                 .ops = &i9xx_always_on_power_well_ops,
1880         },
1881 };
1882
1883 static const struct i915_power_well_ops hsw_power_well_ops = {
1884         .sync_hw = hsw_power_well_sync_hw,
1885         .enable = hsw_power_well_enable,
1886         .disable = hsw_power_well_disable,
1887         .is_enabled = hsw_power_well_enabled,
1888 };
1889
1890 static const struct i915_power_well_ops skl_power_well_ops = {
1891         .sync_hw = skl_power_well_sync_hw,
1892         .enable = skl_power_well_enable,
1893         .disable = skl_power_well_disable,
1894         .is_enabled = skl_power_well_enabled,
1895 };
1896
1897 static const struct i915_power_well_ops gen9_dc_off_power_well_ops = {
1898         .sync_hw = gen9_dc_off_power_well_sync_hw,
1899         .enable = gen9_dc_off_power_well_enable,
1900         .disable = gen9_dc_off_power_well_disable,
1901         .is_enabled = gen9_dc_off_power_well_enabled,
1902 };
1903
1904 static const struct i915_power_well_ops bxt_dpio_cmn_power_well_ops = {
1905         .sync_hw = bxt_dpio_cmn_power_well_sync_hw,
1906         .enable = bxt_dpio_cmn_power_well_enable,
1907         .disable = bxt_dpio_cmn_power_well_disable,
1908         .is_enabled = bxt_dpio_cmn_power_well_enabled,
1909 };
1910
1911 static struct i915_power_well hsw_power_wells[] = {
1912         {
1913                 .name = "always-on",
1914                 .always_on = 1,
1915                 .domains = POWER_DOMAIN_MASK,
1916                 .ops = &i9xx_always_on_power_well_ops,
1917         },
1918         {
1919                 .name = "display",
1920                 .domains = HSW_DISPLAY_POWER_DOMAINS,
1921                 .ops = &hsw_power_well_ops,
1922         },
1923 };
1924
1925 static struct i915_power_well bdw_power_wells[] = {
1926         {
1927                 .name = "always-on",
1928                 .always_on = 1,
1929                 .domains = POWER_DOMAIN_MASK,
1930                 .ops = &i9xx_always_on_power_well_ops,
1931         },
1932         {
1933                 .name = "display",
1934                 .domains = BDW_DISPLAY_POWER_DOMAINS,
1935                 .ops = &hsw_power_well_ops,
1936         },
1937 };
1938
1939 static const struct i915_power_well_ops vlv_display_power_well_ops = {
1940         .sync_hw = vlv_power_well_sync_hw,
1941         .enable = vlv_display_power_well_enable,
1942         .disable = vlv_display_power_well_disable,
1943         .is_enabled = vlv_power_well_enabled,
1944 };
1945
1946 static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = {
1947         .sync_hw = vlv_power_well_sync_hw,
1948         .enable = vlv_dpio_cmn_power_well_enable,
1949         .disable = vlv_dpio_cmn_power_well_disable,
1950         .is_enabled = vlv_power_well_enabled,
1951 };
1952
1953 static const struct i915_power_well_ops vlv_dpio_power_well_ops = {
1954         .sync_hw = vlv_power_well_sync_hw,
1955         .enable = vlv_power_well_enable,
1956         .disable = vlv_power_well_disable,
1957         .is_enabled = vlv_power_well_enabled,
1958 };
1959
1960 static struct i915_power_well vlv_power_wells[] = {
1961         {
1962                 .name = "always-on",
1963                 .always_on = 1,
1964                 .domains = POWER_DOMAIN_MASK,
1965                 .ops = &i9xx_always_on_power_well_ops,
1966                 .data = PUNIT_POWER_WELL_ALWAYS_ON,
1967         },
1968         {
1969                 .name = "display",
1970                 .domains = VLV_DISPLAY_POWER_DOMAINS,
1971                 .data = PUNIT_POWER_WELL_DISP2D,
1972                 .ops = &vlv_display_power_well_ops,
1973         },
1974         {
1975                 .name = "dpio-tx-b-01",
1976                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1977                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1978                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1979                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1980                 .ops = &vlv_dpio_power_well_ops,
1981                 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
1982         },
1983         {
1984                 .name = "dpio-tx-b-23",
1985                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1986                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1987                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1988                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1989                 .ops = &vlv_dpio_power_well_ops,
1990                 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
1991         },
1992         {
1993                 .name = "dpio-tx-c-01",
1994                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1995                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1996                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1997                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1998                 .ops = &vlv_dpio_power_well_ops,
1999                 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
2000         },
2001         {
2002                 .name = "dpio-tx-c-23",
2003                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
2004                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
2005                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
2006                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
2007                 .ops = &vlv_dpio_power_well_ops,
2008                 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
2009         },
2010         {
2011                 .name = "dpio-common",
2012                 .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,
2013                 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
2014                 .ops = &vlv_dpio_cmn_power_well_ops,
2015         },
2016 };
2017
2018 static struct i915_power_well chv_power_wells[] = {
2019         {
2020                 .name = "always-on",
2021                 .always_on = 1,
2022                 .domains = POWER_DOMAIN_MASK,
2023                 .ops = &i9xx_always_on_power_well_ops,
2024         },
2025         {
2026                 .name = "display",
2027                 /*
2028                  * Pipe A power well is the new disp2d well. Pipe B and C
2029                  * power wells don't actually exist. Pipe A power well is
2030                  * required for any pipe to work.
2031                  */
2032                 .domains = CHV_DISPLAY_POWER_DOMAINS,
2033                 .data = PIPE_A,
2034                 .ops = &chv_pipe_power_well_ops,
2035         },
2036         {
2037                 .name = "dpio-common-bc",
2038                 .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS,
2039                 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
2040                 .ops = &chv_dpio_cmn_power_well_ops,
2041         },
2042         {
2043                 .name = "dpio-common-d",
2044                 .domains = CHV_DPIO_CMN_D_POWER_DOMAINS,
2045                 .data = PUNIT_POWER_WELL_DPIO_CMN_D,
2046                 .ops = &chv_dpio_cmn_power_well_ops,
2047         },
2048 };
2049
2050 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
2051                                     int power_well_id)
2052 {
2053         struct i915_power_well *power_well;
2054         bool ret;
2055
2056         power_well = lookup_power_well(dev_priv, power_well_id);
2057         ret = power_well->ops->is_enabled(dev_priv, power_well);
2058
2059         return ret;
2060 }
2061
2062 static struct i915_power_well skl_power_wells[] = {
2063         {
2064                 .name = "always-on",
2065                 .always_on = 1,
2066                 .domains = POWER_DOMAIN_MASK,
2067                 .ops = &i9xx_always_on_power_well_ops,
2068                 .data = SKL_DISP_PW_ALWAYS_ON,
2069         },
2070         {
2071                 .name = "power well 1",
2072                 /* Handled by the DMC firmware */
2073                 .domains = 0,
2074                 .ops = &skl_power_well_ops,
2075                 .data = SKL_DISP_PW_1,
2076         },
2077         {
2078                 .name = "MISC IO power well",
2079                 /* Handled by the DMC firmware */
2080                 .domains = 0,
2081                 .ops = &skl_power_well_ops,
2082                 .data = SKL_DISP_PW_MISC_IO,
2083         },
2084         {
2085                 .name = "DC off",
2086                 .domains = SKL_DISPLAY_DC_OFF_POWER_DOMAINS,
2087                 .ops = &gen9_dc_off_power_well_ops,
2088                 .data = SKL_DISP_PW_DC_OFF,
2089         },
2090         {
2091                 .name = "power well 2",
2092                 .domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS,
2093                 .ops = &skl_power_well_ops,
2094                 .data = SKL_DISP_PW_2,
2095         },
2096         {
2097                 .name = "DDI A/E power well",
2098                 .domains = SKL_DISPLAY_DDI_A_E_POWER_DOMAINS,
2099                 .ops = &skl_power_well_ops,
2100                 .data = SKL_DISP_PW_DDI_A_E,
2101         },
2102         {
2103                 .name = "DDI B power well",
2104                 .domains = SKL_DISPLAY_DDI_B_POWER_DOMAINS,
2105                 .ops = &skl_power_well_ops,
2106                 .data = SKL_DISP_PW_DDI_B,
2107         },
2108         {
2109                 .name = "DDI C power well",
2110                 .domains = SKL_DISPLAY_DDI_C_POWER_DOMAINS,
2111                 .ops = &skl_power_well_ops,
2112                 .data = SKL_DISP_PW_DDI_C,
2113         },
2114         {
2115                 .name = "DDI D power well",
2116                 .domains = SKL_DISPLAY_DDI_D_POWER_DOMAINS,
2117                 .ops = &skl_power_well_ops,
2118                 .data = SKL_DISP_PW_DDI_D,
2119         },
2120 };
2121
2122 static struct i915_power_well bxt_power_wells[] = {
2123         {
2124                 .name = "always-on",
2125                 .always_on = 1,
2126                 .domains = POWER_DOMAIN_MASK,
2127                 .ops = &i9xx_always_on_power_well_ops,
2128         },
2129         {
2130                 .name = "power well 1",
2131                 .domains = 0,
2132                 .ops = &skl_power_well_ops,
2133                 .data = SKL_DISP_PW_1,
2134         },
2135         {
2136                 .name = "DC off",
2137                 .domains = BXT_DISPLAY_DC_OFF_POWER_DOMAINS,
2138                 .ops = &gen9_dc_off_power_well_ops,
2139                 .data = SKL_DISP_PW_DC_OFF,
2140         },
2141         {
2142                 .name = "power well 2",
2143                 .domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS,
2144                 .ops = &skl_power_well_ops,
2145                 .data = SKL_DISP_PW_2,
2146         },
2147         {
2148                 .name = "dpio-common-a",
2149                 .domains = BXT_DPIO_CMN_A_POWER_DOMAINS,
2150                 .ops = &bxt_dpio_cmn_power_well_ops,
2151                 .data = BXT_DPIO_CMN_A,
2152         },
2153         {
2154                 .name = "dpio-common-bc",
2155                 .domains = BXT_DPIO_CMN_BC_POWER_DOMAINS,
2156                 .ops = &bxt_dpio_cmn_power_well_ops,
2157                 .data = BXT_DPIO_CMN_BC,
2158         },
2159 };
2160
2161 static int
2162 sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv,
2163                                    int disable_power_well)
2164 {
2165         if (disable_power_well >= 0)
2166                 return !!disable_power_well;
2167
2168         return 1;
2169 }
2170
2171 static uint32_t get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
2172                                     int enable_dc)
2173 {
2174         uint32_t mask;
2175         int requested_dc;
2176         int max_dc;
2177
2178         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
2179                 max_dc = 2;
2180                 mask = 0;
2181         } else if (IS_BROXTON(dev_priv)) {
2182                 max_dc = 1;
2183                 /*
2184                  * DC9 has a separate HW flow from the rest of the DC states,
2185                  * not depending on the DMC firmware. It's needed by system
2186                  * suspend/resume, so allow it unconditionally.
2187                  */
2188                 mask = DC_STATE_EN_DC9;
2189         } else {
2190                 max_dc = 0;
2191                 mask = 0;
2192         }
2193
2194         if (!i915.disable_power_well)
2195                 max_dc = 0;
2196
2197         if (enable_dc >= 0 && enable_dc <= max_dc) {
2198                 requested_dc = enable_dc;
2199         } else if (enable_dc == -1) {
2200                 requested_dc = max_dc;
2201         } else if (enable_dc > max_dc && enable_dc <= 2) {
2202                 DRM_DEBUG_KMS("Adjusting requested max DC state (%d->%d)\n",
2203                               enable_dc, max_dc);
2204                 requested_dc = max_dc;
2205         } else {
2206                 DRM_ERROR("Unexpected value for enable_dc (%d)\n", enable_dc);
2207                 requested_dc = max_dc;
2208         }
2209
2210         if (requested_dc > 1)
2211                 mask |= DC_STATE_EN_UPTO_DC6;
2212         if (requested_dc > 0)
2213                 mask |= DC_STATE_EN_UPTO_DC5;
2214
2215         DRM_DEBUG_KMS("Allowed DC state mask %02x\n", mask);
2216
2217         return mask;
2218 }
2219
2220 #define set_power_wells(power_domains, __power_wells) ({                \
2221         (power_domains)->power_wells = (__power_wells);                 \
2222         (power_domains)->power_well_count = ARRAY_SIZE(__power_wells);  \
2223 })
2224
2225 /**
2226  * intel_power_domains_init - initializes the power domain structures
2227  * @dev_priv: i915 device instance
2228  *
2229  * Initializes the power domain structures for @dev_priv depending upon the
2230  * supported platform.
2231  */
2232 int intel_power_domains_init(struct drm_i915_private *dev_priv)
2233 {
2234         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2235
2236         i915.disable_power_well = sanitize_disable_power_well_option(dev_priv,
2237                                                      i915.disable_power_well);
2238         dev_priv->csr.allowed_dc_mask = get_allowed_dc_mask(dev_priv,
2239                                                             i915.enable_dc);
2240
2241         BUILD_BUG_ON(POWER_DOMAIN_NUM > 31);
2242
2243         mutex_init(&power_domains->lock);
2244
2245         /*
2246          * The enabling order will be from lower to higher indexed wells,
2247          * the disabling order is reversed.
2248          */
2249         if (IS_HASWELL(dev_priv)) {
2250                 set_power_wells(power_domains, hsw_power_wells);
2251         } else if (IS_BROADWELL(dev_priv)) {
2252                 set_power_wells(power_domains, bdw_power_wells);
2253         } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
2254                 set_power_wells(power_domains, skl_power_wells);
2255         } else if (IS_BROXTON(dev_priv)) {
2256                 set_power_wells(power_domains, bxt_power_wells);
2257         } else if (IS_CHERRYVIEW(dev_priv)) {
2258                 set_power_wells(power_domains, chv_power_wells);
2259         } else if (IS_VALLEYVIEW(dev_priv)) {
2260                 set_power_wells(power_domains, vlv_power_wells);
2261         } else {
2262                 set_power_wells(power_domains, i9xx_always_on_power_well);
2263         }
2264
2265         return 0;
2266 }
2267
2268 /**
2269  * intel_power_domains_fini - finalizes the power domain structures
2270  * @dev_priv: i915 device instance
2271  *
2272  * Finalizes the power domain structures for @dev_priv depending upon the
2273  * supported platform. This function also disables runtime pm and ensures that
2274  * the device stays powered up so that the driver can be reloaded.
2275  */
2276 void intel_power_domains_fini(struct drm_i915_private *dev_priv)
2277 {
2278         struct device *device = &dev_priv->dev->pdev->dev;
2279
2280         /*
2281          * The i915.ko module is still not prepared to be loaded when
2282          * the power well is not enabled, so just enable it in case
2283          * we're going to unload/reload.
2284          * The following also reacquires the RPM reference the core passed
2285          * to the driver during loading, which is dropped in
2286          * intel_runtime_pm_enable(). We have to hand back the control of the
2287          * device to the core with this reference held.
2288          */
2289         intel_display_set_init_power(dev_priv, true);
2290
2291         /* Remove the refcount we took to keep power well support disabled. */
2292         if (!i915.disable_power_well)
2293                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
2294
2295         /*
2296          * Remove the refcount we took in intel_runtime_pm_enable() in case
2297          * the platform doesn't support runtime PM.
2298          */
2299         if (!HAS_RUNTIME_PM(dev_priv))
2300                 pm_runtime_put(device);
2301 }
2302
2303 static void intel_power_domains_sync_hw(struct drm_i915_private *dev_priv)
2304 {
2305         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2306         struct i915_power_well *power_well;
2307         int i;
2308
2309         mutex_lock(&power_domains->lock);
2310         for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
2311                 power_well->ops->sync_hw(dev_priv, power_well);
2312                 power_well->hw_enabled = power_well->ops->is_enabled(dev_priv,
2313                                                                      power_well);
2314         }
2315         mutex_unlock(&power_domains->lock);
2316 }
2317
2318 static void gen9_dbuf_enable(struct drm_i915_private *dev_priv)
2319 {
2320         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
2321         POSTING_READ(DBUF_CTL);
2322
2323         udelay(10);
2324
2325         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
2326                 DRM_ERROR("DBuf power enable timeout\n");
2327 }
2328
2329 static void gen9_dbuf_disable(struct drm_i915_private *dev_priv)
2330 {
2331         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
2332         POSTING_READ(DBUF_CTL);
2333
2334         udelay(10);
2335
2336         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
2337                 DRM_ERROR("DBuf power disable timeout!\n");
2338 }
2339
2340 static void skl_display_core_init(struct drm_i915_private *dev_priv,
2341                                    bool resume)
2342 {
2343         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2344         struct i915_power_well *well;
2345         uint32_t val;
2346
2347         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
2348
2349         /* enable PCH reset handshake */
2350         val = I915_READ(HSW_NDE_RSTWRN_OPT);
2351         I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
2352
2353         /* enable PG1 and Misc I/O */
2354         mutex_lock(&power_domains->lock);
2355
2356         well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
2357         intel_power_well_enable(dev_priv, well);
2358
2359         well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);
2360         intel_power_well_enable(dev_priv, well);
2361
2362         mutex_unlock(&power_domains->lock);
2363
2364         skl_init_cdclk(dev_priv);
2365
2366         gen9_dbuf_enable(dev_priv);
2367
2368         if (resume && dev_priv->csr.dmc_payload)
2369                 intel_csr_load_program(dev_priv);
2370 }
2371
2372 static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
2373 {
2374         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2375         struct i915_power_well *well;
2376
2377         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
2378
2379         gen9_dbuf_disable(dev_priv);
2380
2381         skl_uninit_cdclk(dev_priv);
2382
2383         /* The spec doesn't call for removing the reset handshake flag */
2384         /* disable PG1 and Misc I/O */
2385
2386         mutex_lock(&power_domains->lock);
2387
2388         well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);
2389         intel_power_well_disable(dev_priv, well);
2390
2391         well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
2392         intel_power_well_disable(dev_priv, well);
2393
2394         mutex_unlock(&power_domains->lock);
2395 }
2396
2397 void bxt_display_core_init(struct drm_i915_private *dev_priv,
2398                            bool resume)
2399 {
2400         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2401         struct i915_power_well *well;
2402         uint32_t val;
2403
2404         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
2405
2406         /*
2407          * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
2408          * or else the reset will hang because there is no PCH to respond.
2409          * Move the handshake programming to initialization sequence.
2410          * Previously was left up to BIOS.
2411          */
2412         val = I915_READ(HSW_NDE_RSTWRN_OPT);
2413         val &= ~RESET_PCH_HANDSHAKE_ENABLE;
2414         I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
2415
2416         /* Enable PG1 */
2417         mutex_lock(&power_domains->lock);
2418
2419         well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
2420         intel_power_well_enable(dev_priv, well);
2421
2422         mutex_unlock(&power_domains->lock);
2423
2424         bxt_init_cdclk(dev_priv);
2425
2426         gen9_dbuf_enable(dev_priv);
2427
2428         if (resume && dev_priv->csr.dmc_payload)
2429                 intel_csr_load_program(dev_priv);
2430 }
2431
2432 void bxt_display_core_uninit(struct drm_i915_private *dev_priv)
2433 {
2434         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2435         struct i915_power_well *well;
2436
2437         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
2438
2439         gen9_dbuf_disable(dev_priv);
2440
2441         bxt_uninit_cdclk(dev_priv);
2442
2443         /* The spec doesn't call for removing the reset handshake flag */
2444
2445         /* Disable PG1 */
2446         mutex_lock(&power_domains->lock);
2447
2448         well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
2449         intel_power_well_disable(dev_priv, well);
2450
2451         mutex_unlock(&power_domains->lock);
2452 }
2453
2454 static void chv_phy_control_init(struct drm_i915_private *dev_priv)
2455 {
2456         struct i915_power_well *cmn_bc =
2457                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
2458         struct i915_power_well *cmn_d =
2459                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D);
2460
2461         /*
2462          * DISPLAY_PHY_CONTROL can get corrupted if read. As a
2463          * workaround never ever read DISPLAY_PHY_CONTROL, and
2464          * instead maintain a shadow copy ourselves. Use the actual
2465          * power well state and lane status to reconstruct the
2466          * expected initial value.
2467          */
2468         dev_priv->chv_phy_control =
2469                 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY0) |
2470                 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY1) |
2471                 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH0) |
2472                 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH1) |
2473                 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY1, DPIO_CH0);
2474
2475         /*
2476          * If all lanes are disabled we leave the override disabled
2477          * with all power down bits cleared to match the state we
2478          * would use after disabling the port. Otherwise enable the
2479          * override and set the lane powerdown bits accding to the
2480          * current lane status.
2481          */
2482         if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) {
2483                 uint32_t status = I915_READ(DPLL(PIPE_A));
2484                 unsigned int mask;
2485
2486                 mask = status & DPLL_PORTB_READY_MASK;
2487                 if (mask == 0xf)
2488                         mask = 0x0;
2489                 else
2490                         dev_priv->chv_phy_control |=
2491                                 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0);
2492
2493                 dev_priv->chv_phy_control |=
2494                         PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH0);
2495
2496                 mask = (status & DPLL_PORTC_READY_MASK) >> 4;
2497                 if (mask == 0xf)
2498                         mask = 0x0;
2499                 else
2500                         dev_priv->chv_phy_control |=
2501                                 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1);
2502
2503                 dev_priv->chv_phy_control |=
2504                         PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH1);
2505
2506                 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0);
2507
2508                 dev_priv->chv_phy_assert[DPIO_PHY0] = false;
2509         } else {
2510                 dev_priv->chv_phy_assert[DPIO_PHY0] = true;
2511         }
2512
2513         if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) {
2514                 uint32_t status = I915_READ(DPIO_PHY_STATUS);
2515                 unsigned int mask;
2516
2517                 mask = status & DPLL_PORTD_READY_MASK;
2518
2519                 if (mask == 0xf)
2520                         mask = 0x0;
2521                 else
2522                         dev_priv->chv_phy_control |=
2523                                 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0);
2524
2525                 dev_priv->chv_phy_control |=
2526                         PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY1, DPIO_CH0);
2527
2528                 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1);
2529
2530                 dev_priv->chv_phy_assert[DPIO_PHY1] = false;
2531         } else {
2532                 dev_priv->chv_phy_assert[DPIO_PHY1] = true;
2533         }
2534
2535         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
2536
2537         DRM_DEBUG_KMS("Initial PHY_CONTROL=0x%08x\n",
2538                       dev_priv->chv_phy_control);
2539 }
2540
2541 static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv)
2542 {
2543         struct i915_power_well *cmn =
2544                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
2545         struct i915_power_well *disp2d =
2546                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D);
2547
2548         /* If the display might be already active skip this */
2549         if (cmn->ops->is_enabled(dev_priv, cmn) &&
2550             disp2d->ops->is_enabled(dev_priv, disp2d) &&
2551             I915_READ(DPIO_CTL) & DPIO_CMNRST)
2552                 return;
2553
2554         DRM_DEBUG_KMS("toggling display PHY side reset\n");
2555
2556         /* cmnlane needs DPLL registers */
2557         disp2d->ops->enable(dev_priv, disp2d);
2558
2559         /*
2560          * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx:
2561          * Need to assert and de-assert PHY SB reset by gating the
2562          * common lane power, then un-gating it.
2563          * Simply ungating isn't enough to reset the PHY enough to get
2564          * ports and lanes running.
2565          */
2566         cmn->ops->disable(dev_priv, cmn);
2567 }
2568
2569 /**
2570  * intel_power_domains_init_hw - initialize hardware power domain state
2571  * @dev_priv: i915 device instance
2572  * @resume: Called from resume code paths or not
2573  *
2574  * This function initializes the hardware power domain state and enables all
2575  * power domains using intel_display_set_init_power().
2576  */
2577 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume)
2578 {
2579         struct drm_device *dev = dev_priv->dev;
2580         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2581
2582         power_domains->initializing = true;
2583
2584         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
2585                 skl_display_core_init(dev_priv, resume);
2586         } else if (IS_BROXTON(dev)) {
2587                 bxt_display_core_init(dev_priv, resume);
2588         } else if (IS_CHERRYVIEW(dev)) {
2589                 mutex_lock(&power_domains->lock);
2590                 chv_phy_control_init(dev_priv);
2591                 mutex_unlock(&power_domains->lock);
2592         } else if (IS_VALLEYVIEW(dev)) {
2593                 mutex_lock(&power_domains->lock);
2594                 vlv_cmnlane_wa(dev_priv);
2595                 mutex_unlock(&power_domains->lock);
2596         }
2597
2598         /* For now, we need the power well to be always enabled. */
2599         intel_display_set_init_power(dev_priv, true);
2600         /* Disable power support if the user asked so. */
2601         if (!i915.disable_power_well)
2602                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
2603         intel_power_domains_sync_hw(dev_priv);
2604         power_domains->initializing = false;
2605 }
2606
2607 /**
2608  * intel_power_domains_suspend - suspend power domain state
2609  * @dev_priv: i915 device instance
2610  *
2611  * This function prepares the hardware power domain state before entering
2612  * system suspend. It must be paired with intel_power_domains_init_hw().
2613  */
2614 void intel_power_domains_suspend(struct drm_i915_private *dev_priv)
2615 {
2616         /*
2617          * Even if power well support was disabled we still want to disable
2618          * power wells while we are system suspended.
2619          */
2620         if (!i915.disable_power_well)
2621                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
2622
2623         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
2624                 skl_display_core_uninit(dev_priv);
2625         else if (IS_BROXTON(dev_priv))
2626                 bxt_display_core_uninit(dev_priv);
2627 }
2628
2629 /**
2630  * intel_runtime_pm_get - grab a runtime pm reference
2631  * @dev_priv: i915 device instance
2632  *
2633  * This function grabs a device-level runtime pm reference (mostly used for GEM
2634  * code to ensure the GTT or GT is on) and ensures that it is powered up.
2635  *
2636  * Any runtime pm reference obtained by this function must have a symmetric
2637  * call to intel_runtime_pm_put() to release the reference again.
2638  */
2639 void intel_runtime_pm_get(struct drm_i915_private *dev_priv)
2640 {
2641         struct drm_device *dev = dev_priv->dev;
2642         struct device *device = &dev->pdev->dev;
2643
2644         pm_runtime_get_sync(device);
2645
2646         atomic_inc(&dev_priv->pm.wakeref_count);
2647         assert_rpm_wakelock_held(dev_priv);
2648 }
2649
2650 /**
2651  * intel_runtime_pm_get_if_in_use - grab a runtime pm reference if device in use
2652  * @dev_priv: i915 device instance
2653  *
2654  * This function grabs a device-level runtime pm reference if the device is
2655  * already in use and ensures that it is powered up.
2656  *
2657  * Any runtime pm reference obtained by this function must have a symmetric
2658  * call to intel_runtime_pm_put() to release the reference again.
2659  */
2660 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv)
2661 {
2662         struct drm_device *dev = dev_priv->dev;
2663         struct device *device = &dev->pdev->dev;
2664
2665         if (IS_ENABLED(CONFIG_PM)) {
2666                 int ret = pm_runtime_get_if_in_use(device);
2667
2668                 /*
2669                  * In cases runtime PM is disabled by the RPM core and we get
2670                  * an -EINVAL return value we are not supposed to call this
2671                  * function, since the power state is undefined. This applies
2672                  * atm to the late/early system suspend/resume handlers.
2673                  */
2674                 WARN_ON_ONCE(ret < 0);
2675                 if (ret <= 0)
2676                         return false;
2677         }
2678
2679         atomic_inc(&dev_priv->pm.wakeref_count);
2680         assert_rpm_wakelock_held(dev_priv);
2681
2682         return true;
2683 }
2684
2685 /**
2686  * intel_runtime_pm_get_noresume - grab a runtime pm reference
2687  * @dev_priv: i915 device instance
2688  *
2689  * This function grabs a device-level runtime pm reference (mostly used for GEM
2690  * code to ensure the GTT or GT is on).
2691  *
2692  * It will _not_ power up the device but instead only check that it's powered
2693  * on.  Therefore it is only valid to call this functions from contexts where
2694  * the device is known to be powered up and where trying to power it up would
2695  * result in hilarity and deadlocks. That pretty much means only the system
2696  * suspend/resume code where this is used to grab runtime pm references for
2697  * delayed setup down in work items.
2698  *
2699  * Any runtime pm reference obtained by this function must have a symmetric
2700  * call to intel_runtime_pm_put() to release the reference again.
2701  */
2702 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv)
2703 {
2704         struct drm_device *dev = dev_priv->dev;
2705         struct device *device = &dev->pdev->dev;
2706
2707         assert_rpm_wakelock_held(dev_priv);
2708         pm_runtime_get_noresume(device);
2709
2710         atomic_inc(&dev_priv->pm.wakeref_count);
2711 }
2712
2713 /**
2714  * intel_runtime_pm_put - release a runtime pm reference
2715  * @dev_priv: i915 device instance
2716  *
2717  * This function drops the device-level runtime pm reference obtained by
2718  * intel_runtime_pm_get() and might power down the corresponding
2719  * hardware block right away if this is the last reference.
2720  */
2721 void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
2722 {
2723         struct drm_device *dev = dev_priv->dev;
2724         struct device *device = &dev->pdev->dev;
2725
2726         assert_rpm_wakelock_held(dev_priv);
2727         if (atomic_dec_and_test(&dev_priv->pm.wakeref_count))
2728                 atomic_inc(&dev_priv->pm.atomic_seq);
2729
2730         pm_runtime_mark_last_busy(device);
2731         pm_runtime_put_autosuspend(device);
2732 }
2733
2734 /**
2735  * intel_runtime_pm_enable - enable runtime pm
2736  * @dev_priv: i915 device instance
2737  *
2738  * This function enables runtime pm at the end of the driver load sequence.
2739  *
2740  * Note that this function does currently not enable runtime pm for the
2741  * subordinate display power domains. That is only done on the first modeset
2742  * using intel_display_set_init_power().
2743  */
2744 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv)
2745 {
2746         struct drm_device *dev = dev_priv->dev;
2747         struct device *device = &dev->pdev->dev;
2748
2749         pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */
2750         pm_runtime_mark_last_busy(device);
2751
2752         /*
2753          * Take a permanent reference to disable the RPM functionality and drop
2754          * it only when unloading the driver. Use the low level get/put helpers,
2755          * so the driver's own RPM reference tracking asserts also work on
2756          * platforms without RPM support.
2757          */
2758         if (!HAS_RUNTIME_PM(dev)) {
2759                 pm_runtime_dont_use_autosuspend(device);
2760                 pm_runtime_get_sync(device);
2761         } else {
2762                 pm_runtime_use_autosuspend(device);
2763         }
2764
2765         /*
2766          * The core calls the driver load handler with an RPM reference held.
2767          * We drop that here and will reacquire it during unloading in
2768          * intel_power_domains_fini().
2769          */
2770         pm_runtime_put_autosuspend(device);
2771 }
2772