drivers/gpu/drm/i915/intel_runtime_pm.c

   1 /*
   2  * Copyright © 2012-2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *    Daniel Vetter <daniel.vetter@ffwll.ch>
  26  *
  27  */
  28
  29 #include <linux/pm_runtime.h>
  30 #include <linux/vgaarb.h>
  31
  32 #include "i915_drv.h"
  33 #include "intel_drv.h"
  34
  35 /**
  36  * DOC: runtime pm
  37  *
  38  * The i915 driver supports dynamic enabling and disabling of entire hardware
  39  * blocks at runtime. This is especially important on the display side where
  40  * software is supposed to control many power gates manually on recent hardware,
  41  * since on the GT side a lot of the power management is done by the hardware.
  42  * But even there some manual control at the device level is required.
  43  *
  44  * Since i915 supports a diverse set of platforms with a unified codebase and
  45  * hardware engineers just love to shuffle functionality around between power
  46  * domains there's a sizeable amount of indirection required. This file provides
  47  * generic functions to the driver for grabbing and releasing references for
  48  * abstract power domains. It then maps those to the actual power wells
  49  * present for a given platform.
  50  */
  51
  52 #define for_each_power_well(i, power_well, domain_mask, power_domains)  \
  53         for (i = 0;                                                     \
  54              i < (power_domains)->power_well_count &&                   \
  55                  ((power_well) = &(power_domains)->power_wells[i]);     \
  56              i++)                                                       \
  57                 for_each_if ((power_well)->domains & (domain_mask))
  58
  59 #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
  60         for (i = (power_domains)->power_well_count - 1;                  \
  61              i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
  62              i--)                                                        \
  63                 for_each_if ((power_well)->domains & (domain_mask))
  64
  65 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
  66                                     int power_well_id);
  67
  68 static struct i915_power_well *
  69 lookup_power_well(struct drm_i915_private *dev_priv, int power_well_id);
  70
  71 const char *
  72 intel_display_power_domain_str(enum intel_display_power_domain domain)
  73 {
  74         switch (domain) {
  75         case POWER_DOMAIN_PIPE_A:
  76                 return "PIPE_A";
  77         case POWER_DOMAIN_PIPE_B:
  78                 return "PIPE_B";
  79         case POWER_DOMAIN_PIPE_C:
  80                 return "PIPE_C";
  81         case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
  82                 return "PIPE_A_PANEL_FITTER";
  83         case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
  84                 return "PIPE_B_PANEL_FITTER";
  85         case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
  86                 return "PIPE_C_PANEL_FITTER";
  87         case POWER_DOMAIN_TRANSCODER_A:
  88                 return "TRANSCODER_A";
  89         case POWER_DOMAIN_TRANSCODER_B:
  90                 return "TRANSCODER_B";
  91         case POWER_DOMAIN_TRANSCODER_C:
  92                 return "TRANSCODER_C";
  93         case POWER_DOMAIN_TRANSCODER_EDP:
  94                 return "TRANSCODER_EDP";
  95         case POWER_DOMAIN_TRANSCODER_DSI_A:
  96                 return "TRANSCODER_DSI_A";
  97         case POWER_DOMAIN_TRANSCODER_DSI_C:
  98                 return "TRANSCODER_DSI_C";
  99         case POWER_DOMAIN_PORT_DDI_A_LANES:
 100                 return "PORT_DDI_A_LANES";
 101         case POWER_DOMAIN_PORT_DDI_B_LANES:
 102                 return "PORT_DDI_B_LANES";
 103         case POWER_DOMAIN_PORT_DDI_C_LANES:
 104                 return "PORT_DDI_C_LANES";
 105         case POWER_DOMAIN_PORT_DDI_D_LANES:
 106                 return "PORT_DDI_D_LANES";
 107         case POWER_DOMAIN_PORT_DDI_E_LANES:
 108                 return "PORT_DDI_E_LANES";
 109         case POWER_DOMAIN_PORT_DSI:
 110                 return "PORT_DSI";
 111         case POWER_DOMAIN_PORT_CRT:
 112                 return "PORT_CRT";
 113         case POWER_DOMAIN_PORT_OTHER:
 114                 return "PORT_OTHER";
 115         case POWER_DOMAIN_VGA:
 116                 return "VGA";
 117         case POWER_DOMAIN_AUDIO:
 118                 return "AUDIO";
 119         case POWER_DOMAIN_PLLS:
 120                 return "PLLS";
 121         case POWER_DOMAIN_AUX_A:
 122                 return "AUX_A";
 123         case POWER_DOMAIN_AUX_B:
 124                 return "AUX_B";
 125         case POWER_DOMAIN_AUX_C:
 126                 return "AUX_C";
 127         case POWER_DOMAIN_AUX_D:
 128                 return "AUX_D";
 129         case POWER_DOMAIN_GMBUS:
 130                 return "GMBUS";
 131         case POWER_DOMAIN_INIT:
 132                 return "INIT";
 133         case POWER_DOMAIN_MODESET:
 134                 return "MODESET";
 135         default:
 136                 MISSING_CASE(domain);
 137                 return "?";
 138         }
 139 }
 140
 141 static void intel_power_well_enable(struct drm_i915_private *dev_priv,
 142                                     struct i915_power_well *power_well)
 143 {
 144         DRM_DEBUG_KMS("enabling %s\n", power_well->name);
 145         power_well->ops->enable(dev_priv, power_well);
 146         power_well->hw_enabled = true;
 147 }
 148
 149 static void intel_power_well_disable(struct drm_i915_private *dev_priv,
 150                                      struct i915_power_well *power_well)
 151 {
 152         DRM_DEBUG_KMS("disabling %s\n", power_well->name);
 153         power_well->hw_enabled = false;
 154         power_well->ops->disable(dev_priv, power_well);
 155 }
 156
 157 static void intel_power_well_get(struct drm_i915_private *dev_priv,
 158                                  struct i915_power_well *power_well)
 159 {
 160         if (!power_well->count++)
 161                 intel_power_well_enable(dev_priv, power_well);
 162 }
 163
 164 static void intel_power_well_put(struct drm_i915_private *dev_priv,
 165                                  struct i915_power_well *power_well)
 166 {
 167         WARN(!power_well->count, "Use count on power well %s is already zero",
 168              power_well->name);
 169
 170         if (!--power_well->count)
 171                 intel_power_well_disable(dev_priv, power_well);
 172 }
 173
 174 /*
 175  * We should only use the power well if we explicitly asked the hardware to
 176  * enable it, so check if it's enabled and also check if we've requested it to
 177  * be enabled.
 178  */
 179 static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
 180                                    struct i915_power_well *power_well)
 181 {
 182         return I915_READ(HSW_PWR_WELL_DRIVER) ==
 183                      (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
 184 }
 185
 186 /**
 187  * __intel_display_power_is_enabled - unlocked check for a power domain
 188  * @dev_priv: i915 device instance
 189  * @domain: power domain to check
 190  *
 191  * This is the unlocked version of intel_display_power_is_enabled() and should
 192  * only be used from error capture and recovery code where deadlocks are
 193  * possible.
 194  *
 195  * Returns:
 196  * True when the power domain is enabled, false otherwise.
 197  */
 198 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
 199                                       enum intel_display_power_domain domain)
 200 {
 201         struct i915_power_domains *power_domains;
 202         struct i915_power_well *power_well;
 203         bool is_enabled;
 204         int i;
 205
 206         if (dev_priv->pm.suspended)
 207                 return false;
 208
 209         power_domains = &dev_priv->power_domains;
 210
 211         is_enabled = true;
 212
 213         for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
 214                 if (power_well->always_on)
 215                         continue;
 216
 217                 if (!power_well->hw_enabled) {
 218                         is_enabled = false;
 219                         break;
 220                 }
 221         }
 222
 223         return is_enabled;
 224 }
 225
 226 /**
 227  * intel_display_power_is_enabled - check for a power domain
 228  * @dev_priv: i915 device instance
 229  * @domain: power domain to check
 230  *
 231  * This function can be used to check the hw power domain state. It is mostly
 232  * used in hardware state readout functions. Everywhere else code should rely
 233  * upon explicit power domain reference counting to ensure that the hardware
 234  * block is powered up before accessing it.
 235  *
 236  * Callers must hold the relevant modesetting locks to ensure that concurrent
 237  * threads can't disable the power well while the caller tries to read a few
 238  * registers.
 239  *
 240  * Returns:
 241  * True when the power domain is enabled, false otherwise.
 242  */
 243 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
 244                                     enum intel_display_power_domain domain)
 245 {
 246         struct i915_power_domains *power_domains;
 247         bool ret;
 248
 249         power_domains = &dev_priv->power_domains;
 250
 251         mutex_lock(&power_domains->lock);
 252         ret = __intel_display_power_is_enabled(dev_priv, domain);
 253         mutex_unlock(&power_domains->lock);
 254
 255         return ret;
 256 }
 257
 258 /**
 259  * intel_display_set_init_power - set the initial power domain state
 260  * @dev_priv: i915 device instance
 261  * @enable: whether to enable or disable the initial power domain state
 262  *
 263  * For simplicity our driver load/unload and system suspend/resume code assumes
 264  * that all power domains are always enabled. This functions controls the state
 265  * of this little hack. While the initial power domain state is enabled runtime
 266  * pm is effectively disabled.
 267  */
 268 void intel_display_set_init_power(struct drm_i915_private *dev_priv,
 269                                   bool enable)
 270 {
 271         if (dev_priv->power_domains.init_power_on == enable)
 272                 return;
 273
 274         if (enable)
 275                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
 276         else
 277                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
 278
 279         dev_priv->power_domains.init_power_on = enable;
 280 }
 281
 282 /*
 283  * Starting with Haswell, we have a "Power Down Well" that can be turned off
 284  * when not needed anymore. We have 4 registers that can request the power well
 285  * to be enabled, and it will only be disabled if none of the registers is
 286  * requesting it to be enabled.
 287  */
 288 static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
 289 {
 290         struct drm_device *dev = dev_priv->dev;
 291
 292         /*
 293          * After we re-enable the power well, if we touch VGA register 0x3d5
 294          * we'll get unclaimed register interrupts. This stops after we write
 295          * anything to the VGA MSR register. The vgacon module uses this
 296          * register all the time, so if we unbind our driver and, as a
 297          * consequence, bind vgacon, we'll get stuck in an infinite loop at
 298          * console_unlock(). So make here we touch the VGA MSR register, making
 299          * sure vgacon can keep working normally without triggering interrupts
 300          * and error messages.
 301          */
 302         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
 303         outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
 304         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
 305
 306         if (IS_BROADWELL(dev))
 307                 gen8_irq_power_well_post_enable(dev_priv,
 308                                                 1 << PIPE_C | 1 << PIPE_B);
 309 }
 310
 311 static void hsw_power_well_pre_disable(struct drm_i915_private *dev_priv)
 312 {
 313         if (IS_BROADWELL(dev_priv))
 314                 gen8_irq_power_well_pre_disable(dev_priv,
 315                                                 1 << PIPE_C | 1 << PIPE_B);
 316 }
 317
 318 static void skl_power_well_post_enable(struct drm_i915_private *dev_priv,
 319                                        struct i915_power_well *power_well)
 320 {
 321         struct drm_device *dev = dev_priv->dev;
 322
 323         /*
 324          * After we re-enable the power well, if we touch VGA register 0x3d5
 325          * we'll get unclaimed register interrupts. This stops after we write
 326          * anything to the VGA MSR register. The vgacon module uses this
 327          * register all the time, so if we unbind our driver and, as a
 328          * consequence, bind vgacon, we'll get stuck in an infinite loop at
 329          * console_unlock(). So make here we touch the VGA MSR register, making
 330          * sure vgacon can keep working normally without triggering interrupts
 331          * and error messages.
 332          */
 333         if (power_well->data == SKL_DISP_PW_2) {
 334                 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
 335                 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
 336                 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
 337
 338                 gen8_irq_power_well_post_enable(dev_priv,
 339                                                 1 << PIPE_C | 1 << PIPE_B);
 340         }
 341 }
 342
 343 static void skl_power_well_pre_disable(struct drm_i915_private *dev_priv,
 344                                        struct i915_power_well *power_well)
 345 {
 346         if (power_well->data == SKL_DISP_PW_2)
 347                 gen8_irq_power_well_pre_disable(dev_priv,
 348                                                 1 << PIPE_C | 1 << PIPE_B);
 349 }
 350
 351 static void hsw_set_power_well(struct drm_i915_private *dev_priv,
 352                                struct i915_power_well *power_well, bool enable)
 353 {
 354         bool is_enabled, enable_requested;
 355         uint32_t tmp;
 356
 357         tmp = I915_READ(HSW_PWR_WELL_DRIVER);
 358         is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
 359         enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
 360
 361         if (enable) {
 362                 if (!enable_requested)
 363                         I915_WRITE(HSW_PWR_WELL_DRIVER,
 364                                    HSW_PWR_WELL_ENABLE_REQUEST);
 365
 366                 if (!is_enabled) {
 367                         DRM_DEBUG_KMS("Enabling power well\n");
 368                         if (intel_wait_for_register(dev_priv,
 369                                                     HSW_PWR_WELL_DRIVER,
 370                                                     HSW_PWR_WELL_STATE_ENABLED,
 371                                                     HSW_PWR_WELL_STATE_ENABLED,
 372                                                     20))
 373                                 DRM_ERROR("Timeout enabling power well\n");
 374                         hsw_power_well_post_enable(dev_priv);
 375                 }
 376
 377         } else {
 378                 if (enable_requested) {
 379                         hsw_power_well_pre_disable(dev_priv);
 380                         I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
 381                         POSTING_READ(HSW_PWR_WELL_DRIVER);
 382                         DRM_DEBUG_KMS("Requesting to disable the power well\n");
 383                 }
 384         }
 385 }
 386
 387 #define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS (         \
 388         BIT(POWER_DOMAIN_TRANSCODER_A) |                \
 389         BIT(POWER_DOMAIN_PIPE_B) |                      \
 390         BIT(POWER_DOMAIN_TRANSCODER_B) |                \
 391         BIT(POWER_DOMAIN_PIPE_C) |                      \
 392         BIT(POWER_DOMAIN_TRANSCODER_C) |                \
 393         BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |         \
 394         BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |         \
 395         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |            \
 396         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |            \
 397         BIT(POWER_DOMAIN_PORT_DDI_D_LANES) |            \
 398         BIT(POWER_DOMAIN_PORT_DDI_E_LANES) |            \
 399         BIT(POWER_DOMAIN_AUX_B) |                       \
 400         BIT(POWER_DOMAIN_AUX_C) |                       \
 401         BIT(POWER_DOMAIN_AUX_D) |                       \
 402         BIT(POWER_DOMAIN_AUDIO) |                       \
 403         BIT(POWER_DOMAIN_VGA) |                         \
 404         BIT(POWER_DOMAIN_INIT))
 405 #define SKL_DISPLAY_DDI_A_E_POWER_DOMAINS (             \
 406         BIT(POWER_DOMAIN_PORT_DDI_A_LANES) |            \
 407         BIT(POWER_DOMAIN_PORT_DDI_E_LANES) |            \
 408         BIT(POWER_DOMAIN_INIT))
 409 #define SKL_DISPLAY_DDI_B_POWER_DOMAINS (               \
 410         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |            \
 411         BIT(POWER_DOMAIN_INIT))
 412 #define SKL_DISPLAY_DDI_C_POWER_DOMAINS (               \
 413         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |            \
 414         BIT(POWER_DOMAIN_INIT))
 415 #define SKL_DISPLAY_DDI_D_POWER_DOMAINS (               \
 416         BIT(POWER_DOMAIN_PORT_DDI_D_LANES) |            \
 417         BIT(POWER_DOMAIN_INIT))
 418 #define SKL_DISPLAY_DC_OFF_POWER_DOMAINS (              \
 419         SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS |         \
 420         BIT(POWER_DOMAIN_MODESET) |                     \
 421         BIT(POWER_DOMAIN_AUX_A) |                       \
 422         BIT(POWER_DOMAIN_INIT))
 423
 424 #define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS (         \
 425         BIT(POWER_DOMAIN_TRANSCODER_A) |                \
 426         BIT(POWER_DOMAIN_PIPE_B) |                      \
 427         BIT(POWER_DOMAIN_TRANSCODER_B) |                \
 428         BIT(POWER_DOMAIN_PIPE_C) |                      \
 429         BIT(POWER_DOMAIN_TRANSCODER_C) |                \
 430         BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |         \
 431         BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |         \
 432         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |            \
 433         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |            \
 434         BIT(POWER_DOMAIN_AUX_B) |                       \
 435         BIT(POWER_DOMAIN_AUX_C) |                       \
 436         BIT(POWER_DOMAIN_AUDIO) |                       \
 437         BIT(POWER_DOMAIN_VGA) |                         \
 438         BIT(POWER_DOMAIN_GMBUS) |                       \
 439         BIT(POWER_DOMAIN_INIT))
 440 #define BXT_DISPLAY_DC_OFF_POWER_DOMAINS (              \
 441         BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS |         \
 442         BIT(POWER_DOMAIN_MODESET) |                     \
 443         BIT(POWER_DOMAIN_AUX_A) |                       \
 444         BIT(POWER_DOMAIN_INIT))
 445 #define BXT_DPIO_CMN_A_POWER_DOMAINS (                  \
 446         BIT(POWER_DOMAIN_PORT_DDI_A_LANES) |            \
 447         BIT(POWER_DOMAIN_AUX_A) |                       \
 448         BIT(POWER_DOMAIN_INIT))
 449 #define BXT_DPIO_CMN_BC_POWER_DOMAINS (                 \
 450         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |            \
 451         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |            \
 452         BIT(POWER_DOMAIN_AUX_B) |                       \
 453         BIT(POWER_DOMAIN_AUX_C) |                       \
 454         BIT(POWER_DOMAIN_INIT))
 455
 456 static void assert_can_enable_dc9(struct drm_i915_private *dev_priv)
 457 {
 458         WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9),
 459                   "DC9 already programmed to be enabled.\n");
 460         WARN_ONCE(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
 461                   "DC5 still not disabled to enable DC9.\n");
 462         WARN_ONCE(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on.\n");
 463         WARN_ONCE(intel_irqs_enabled(dev_priv),
 464                   "Interrupts not disabled yet.\n");
 465
 466          /*
 467           * TODO: check for the following to verify the conditions to enter DC9
 468           * state are satisfied:
 469           * 1] Check relevant display engine registers to verify if mode set
 470           * disable sequence was followed.
 471           * 2] Check if display uninitialize sequence is initialized.
 472           */
 473 }
 474
 475 static void assert_can_disable_dc9(struct drm_i915_private *dev_priv)
 476 {
 477         WARN_ONCE(intel_irqs_enabled(dev_priv),
 478                   "Interrupts not disabled yet.\n");
 479         WARN_ONCE(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
 480                   "DC5 still not disabled.\n");
 481
 482          /*
 483           * TODO: check for the following to verify DC9 state was indeed
 484           * entered before programming to disable it:
 485           * 1] Check relevant display engine registers to verify if mode
 486           *  set disable sequence was followed.
 487           * 2] Check if display uninitialize sequence is initialized.
 488           */
 489 }
 490
 491 static void gen9_write_dc_state(struct drm_i915_private *dev_priv,
 492                                 u32 state)
 493 {
 494         int rewrites = 0;
 495         int rereads = 0;
 496         u32 v;
 497
 498         I915_WRITE(DC_STATE_EN, state);
 499
 500         /* It has been observed that disabling the dc6 state sometimes
 501          * doesn't stick and dmc keeps returning old value. Make sure
 502          * the write really sticks enough times and also force rewrite until
 503          * we are confident that state is exactly what we want.
 504          */
 505         do  {
 506                 v = I915_READ(DC_STATE_EN);
 507
 508                 if (v != state) {
 509                         I915_WRITE(DC_STATE_EN, state);
 510                         rewrites++;
 511                         rereads = 0;
 512                 } else if (rereads++ > 5) {
 513                         break;
 514                 }
 515
 516         } while (rewrites < 100);
 517
 518         if (v != state)
 519                 DRM_ERROR("Writing dc state to 0x%x failed, now 0x%x\n",
 520                           state, v);
 521
 522         /* Most of the times we need one retry, avoid spam */
 523         if (rewrites > 1)
 524                 DRM_DEBUG_KMS("Rewrote dc state to 0x%x %d times\n",
 525                               state, rewrites);
 526 }
 527
 528 static u32 gen9_dc_mask(struct drm_i915_private *dev_priv)
 529 {
 530         u32 mask;
 531
 532         mask = DC_STATE_EN_UPTO_DC5;
 533         if (IS_BROXTON(dev_priv))
 534                 mask |= DC_STATE_EN_DC9;
 535         else
 536                 mask |= DC_STATE_EN_UPTO_DC6;
 537
 538         return mask;
 539 }
 540
 541 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv)
 542 {
 543         u32 val;
 544
 545         val = I915_READ(DC_STATE_EN) & gen9_dc_mask(dev_priv);
 546
 547         DRM_DEBUG_KMS("Resetting DC state tracking from %02x to %02x\n",
 548                       dev_priv->csr.dc_state, val);
 549         dev_priv->csr.dc_state = val;
 550 }
 551
 552 static void gen9_set_dc_state(struct drm_i915_private *dev_priv, uint32_t state)
 553 {
 554         uint32_t val;
 555         uint32_t mask;
 556
 557         if (WARN_ON_ONCE(state & ~dev_priv->csr.allowed_dc_mask))
 558                 state &= dev_priv->csr.allowed_dc_mask;
 559
 560         val = I915_READ(DC_STATE_EN);
 561         mask = gen9_dc_mask(dev_priv);
 562         DRM_DEBUG_KMS("Setting DC state from %02x to %02x\n",
 563                       val & mask, state);
 564
 565         /* Check if DMC is ignoring our DC state requests */
 566         if ((val & mask) != dev_priv->csr.dc_state)
 567                 DRM_ERROR("DC state mismatch (0x%x -> 0x%x)\n",
 568                           dev_priv->csr.dc_state, val & mask);
 569
 570         val &= ~mask;
 571         val |= state;
 572
 573         gen9_write_dc_state(dev_priv, val);
 574
 575         dev_priv->csr.dc_state = val & mask;
 576 }
 577
 578 void bxt_enable_dc9(struct drm_i915_private *dev_priv)
 579 {
 580         assert_can_enable_dc9(dev_priv);
 581
 582         DRM_DEBUG_KMS("Enabling DC9\n");
 583
 584         intel_power_sequencer_reset(dev_priv);
 585         gen9_set_dc_state(dev_priv, DC_STATE_EN_DC9);
 586 }
 587
 588 void bxt_disable_dc9(struct drm_i915_private *dev_priv)
 589 {
 590         assert_can_disable_dc9(dev_priv);
 591
 592         DRM_DEBUG_KMS("Disabling DC9\n");
 593
 594         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 595 }
 596
 597 static void assert_csr_loaded(struct drm_i915_private *dev_priv)
 598 {
 599         WARN_ONCE(!I915_READ(CSR_PROGRAM(0)),
 600                   "CSR program storage start is NULL\n");
 601         WARN_ONCE(!I915_READ(CSR_SSP_BASE), "CSR SSP Base Not fine\n");
 602         WARN_ONCE(!I915_READ(CSR_HTP_SKL), "CSR HTP Not fine\n");
 603 }
 604
 605 static void assert_can_enable_dc5(struct drm_i915_private *dev_priv)
 606 {
 607         bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv,
 608                                         SKL_DISP_PW_2);
 609
 610         WARN_ONCE(pg2_enabled, "PG2 not disabled to enable DC5.\n");
 611
 612         WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5),
 613                   "DC5 already programmed to be enabled.\n");
 614         assert_rpm_wakelock_held(dev_priv);
 615
 616         assert_csr_loaded(dev_priv);
 617 }
 618
 619 void gen9_enable_dc5(struct drm_i915_private *dev_priv)
 620 {
 621         assert_can_enable_dc5(dev_priv);
 622
 623         DRM_DEBUG_KMS("Enabling DC5\n");
 624
 625         gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5);
 626 }
 627
 628 static void assert_can_enable_dc6(struct drm_i915_private *dev_priv)
 629 {
 630         WARN_ONCE(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
 631                   "Backlight is not disabled.\n");
 632         WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6),
 633                   "DC6 already programmed to be enabled.\n");
 634
 635         assert_csr_loaded(dev_priv);
 636 }
 637
 638 void skl_enable_dc6(struct drm_i915_private *dev_priv)
 639 {
 640         assert_can_enable_dc6(dev_priv);
 641
 642         DRM_DEBUG_KMS("Enabling DC6\n");
 643
 644         gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
 645
 646 }
 647
 648 void skl_disable_dc6(struct drm_i915_private *dev_priv)
 649 {
 650         DRM_DEBUG_KMS("Disabling DC6\n");
 651
 652         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 653 }
 654
 655 static void
 656 gen9_sanitize_power_well_requests(struct drm_i915_private *dev_priv,
 657                                   struct i915_power_well *power_well)
 658 {
 659         enum skl_disp_power_wells power_well_id = power_well->data;
 660         u32 val;
 661         u32 mask;
 662
 663         mask = SKL_POWER_WELL_REQ(power_well_id);
 664
 665         val = I915_READ(HSW_PWR_WELL_KVMR);
 666         if (WARN_ONCE(val & mask, "Clearing unexpected KVMR request for %s\n",
 667                       power_well->name))
 668                 I915_WRITE(HSW_PWR_WELL_KVMR, val & ~mask);
 669
 670         val = I915_READ(HSW_PWR_WELL_BIOS);
 671         val |= I915_READ(HSW_PWR_WELL_DEBUG);
 672
 673         if (!(val & mask))
 674                 return;
 675
 676         /*
 677          * DMC is known to force on the request bits for power well 1 on SKL
 678          * and BXT and the misc IO power well on SKL but we don't expect any
 679          * other request bits to be set, so WARN for those.
 680          */
 681         if (power_well_id == SKL_DISP_PW_1 ||
 682             ((IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) &&
 683              power_well_id == SKL_DISP_PW_MISC_IO))
 684                 DRM_DEBUG_DRIVER("Clearing auxiliary requests for %s forced on "
 685                                  "by DMC\n", power_well->name);
 686         else
 687                 WARN_ONCE(1, "Clearing unexpected auxiliary requests for %s\n",
 688                           power_well->name);
 689
 690         I915_WRITE(HSW_PWR_WELL_BIOS, val & ~mask);
 691         I915_WRITE(HSW_PWR_WELL_DEBUG, val & ~mask);
 692 }
 693
 694 static void skl_set_power_well(struct drm_i915_private *dev_priv,
 695                         struct i915_power_well *power_well, bool enable)
 696 {
 697         uint32_t tmp, fuse_status;
 698         uint32_t req_mask, state_mask;
 699         bool is_enabled, enable_requested, check_fuse_status = false;
 700
 701         tmp = I915_READ(HSW_PWR_WELL_DRIVER);
 702         fuse_status = I915_READ(SKL_FUSE_STATUS);
 703
 704         switch (power_well->data) {
 705         case SKL_DISP_PW_1:
 706                 if (intel_wait_for_register(dev_priv,
 707                                             SKL_FUSE_STATUS,
 708                                             SKL_FUSE_PG0_DIST_STATUS,
 709                                             SKL_FUSE_PG0_DIST_STATUS,
 710                                             1)) {
 711                         DRM_ERROR("PG0 not enabled\n");
 712                         return;
 713                 }
 714                 break;
 715         case SKL_DISP_PW_2:
 716                 if (!(fuse_status & SKL_FUSE_PG1_DIST_STATUS)) {
 717                         DRM_ERROR("PG1 in disabled state\n");
 718                         return;
 719                 }
 720                 break;
 721         case SKL_DISP_PW_DDI_A_E:
 722         case SKL_DISP_PW_DDI_B:
 723         case SKL_DISP_PW_DDI_C:
 724         case SKL_DISP_PW_DDI_D:
 725         case SKL_DISP_PW_MISC_IO:
 726                 break;
 727         default:
 728                 WARN(1, "Unknown power well %lu\n", power_well->data);
 729                 return;
 730         }
 731
 732         req_mask = SKL_POWER_WELL_REQ(power_well->data);
 733         enable_requested = tmp & req_mask;
 734         state_mask = SKL_POWER_WELL_STATE(power_well->data);
 735         is_enabled = tmp & state_mask;
 736
 737         if (!enable && enable_requested)
 738                 skl_power_well_pre_disable(dev_priv, power_well);
 739
 740         if (enable) {
 741                 if (!enable_requested) {
 742                         WARN((tmp & state_mask) &&
 743                                 !I915_READ(HSW_PWR_WELL_BIOS),
 744                                 "Invalid for power well status to be enabled, unless done by the BIOS, \
 745                                 when request is to disable!\n");
 746                         I915_WRITE(HSW_PWR_WELL_DRIVER, tmp | req_mask);
 747                 }
 748
 749                 if (!is_enabled) {
 750                         DRM_DEBUG_KMS("Enabling %s\n", power_well->name);
 751                         check_fuse_status = true;
 752                 }
 753         } else {
 754                 if (enable_requested) {
 755                         I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask);
 756                         POSTING_READ(HSW_PWR_WELL_DRIVER);
 757                         DRM_DEBUG_KMS("Disabling %s\n", power_well->name);
 758                 }
 759
 760                 if (IS_GEN9(dev_priv))
 761                         gen9_sanitize_power_well_requests(dev_priv, power_well);
 762         }
 763
 764         if (wait_for(!!(I915_READ(HSW_PWR_WELL_DRIVER) & state_mask) == enable,
 765                      1))
 766                 DRM_ERROR("%s %s timeout\n",
 767                           power_well->name, enable ? "enable" : "disable");
 768
 769         if (check_fuse_status) {
 770                 if (power_well->data == SKL_DISP_PW_1) {
 771                         if (wait_for((I915_READ(SKL_FUSE_STATUS) &
 772                                 SKL_FUSE_PG1_DIST_STATUS), 1))
 773                                 DRM_ERROR("PG1 distributing status timeout\n");
 774                 } else if (power_well->data == SKL_DISP_PW_2) {
 775                         if (wait_for((I915_READ(SKL_FUSE_STATUS) &
 776                                 SKL_FUSE_PG2_DIST_STATUS), 1))
 777                                 DRM_ERROR("PG2 distributing status timeout\n");
 778                 }
 779         }
 780
 781         if (enable && !is_enabled)
 782                 skl_power_well_post_enable(dev_priv, power_well);
 783 }
 784
 785 static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
 786                                    struct i915_power_well *power_well)
 787 {
 788         hsw_set_power_well(dev_priv, power_well, power_well->count > 0);
 789
 790         /*
 791          * We're taking over the BIOS, so clear any requests made by it since
 792          * the driver is in charge now.
 793          */
 794         if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
 795                 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
 796 }
 797
 798 static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
 799                                   struct i915_power_well *power_well)
 800 {
 801         hsw_set_power_well(dev_priv, power_well, true);
 802 }
 803
 804 static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
 805                                    struct i915_power_well *power_well)
 806 {
 807         hsw_set_power_well(dev_priv, power_well, false);
 808 }
 809
 810 static bool skl_power_well_enabled(struct drm_i915_private *dev_priv,
 811                                         struct i915_power_well *power_well)
 812 {
 813         uint32_t mask = SKL_POWER_WELL_REQ(power_well->data) |
 814                 SKL_POWER_WELL_STATE(power_well->data);
 815
 816         return (I915_READ(HSW_PWR_WELL_DRIVER) & mask) == mask;
 817 }
 818
 819 static void skl_power_well_sync_hw(struct drm_i915_private *dev_priv,
 820                                 struct i915_power_well *power_well)
 821 {
 822         skl_set_power_well(dev_priv, power_well, power_well->count > 0);
 823
 824         /* Clear any request made by BIOS as driver is taking over */
 825         I915_WRITE(HSW_PWR_WELL_BIOS, 0);
 826 }
 827
 828 static void skl_power_well_enable(struct drm_i915_private *dev_priv,
 829                                 struct i915_power_well *power_well)
 830 {
 831         skl_set_power_well(dev_priv, power_well, true);
 832 }
 833
 834 static void skl_power_well_disable(struct drm_i915_private *dev_priv,
 835                                 struct i915_power_well *power_well)
 836 {
 837         skl_set_power_well(dev_priv, power_well, false);
 838 }
 839
 840 static enum dpio_phy bxt_power_well_to_phy(struct i915_power_well *power_well)
 841 {
 842         enum skl_disp_power_wells power_well_id = power_well->data;
 843
 844         return power_well_id == BXT_DPIO_CMN_A ? DPIO_PHY1 : DPIO_PHY0;
 845 }
 846
 847 static void bxt_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
 848                                            struct i915_power_well *power_well)
 849 {
 850         enum skl_disp_power_wells power_well_id = power_well->data;
 851         struct i915_power_well *cmn_a_well;
 852
 853         if (power_well_id == BXT_DPIO_CMN_BC) {
 854                 /*
 855                  * We need to copy the GRC calibration value from the eDP PHY,
 856                  * so make sure it's powered up.
 857                  */
 858                 cmn_a_well = lookup_power_well(dev_priv, BXT_DPIO_CMN_A);
 859                 intel_power_well_get(dev_priv, cmn_a_well);
 860         }
 861
 862         bxt_ddi_phy_init(dev_priv, bxt_power_well_to_phy(power_well));
 863
 864         if (power_well_id == BXT_DPIO_CMN_BC)
 865                 intel_power_well_put(dev_priv, cmn_a_well);
 866 }
 867
 868 static void bxt_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
 869                                             struct i915_power_well *power_well)
 870 {
 871         bxt_ddi_phy_uninit(dev_priv, bxt_power_well_to_phy(power_well));
 872 }
 873
 874 static bool bxt_dpio_cmn_power_well_enabled(struct drm_i915_private *dev_priv,
 875                                             struct i915_power_well *power_well)
 876 {
 877         return bxt_ddi_phy_is_enabled(dev_priv,
 878                                       bxt_power_well_to_phy(power_well));
 879 }
 880
 881 static void bxt_dpio_cmn_power_well_sync_hw(struct drm_i915_private *dev_priv,
 882                                             struct i915_power_well *power_well)
 883 {
 884         if (power_well->count > 0)
 885                 bxt_dpio_cmn_power_well_enable(dev_priv, power_well);
 886         else
 887                 bxt_dpio_cmn_power_well_disable(dev_priv, power_well);
 888 }
 889
 890
 891 static void bxt_verify_ddi_phy_power_wells(struct drm_i915_private *dev_priv)
 892 {
 893         struct i915_power_well *power_well;
 894
 895         power_well = lookup_power_well(dev_priv, BXT_DPIO_CMN_A);
 896         if (power_well->count > 0)
 897                 bxt_ddi_phy_verify_state(dev_priv,
 898                                          bxt_power_well_to_phy(power_well));
 899
 900         power_well = lookup_power_well(dev_priv, BXT_DPIO_CMN_BC);
 901         if (power_well->count > 0)
 902                 bxt_ddi_phy_verify_state(dev_priv,
 903                                          bxt_power_well_to_phy(power_well));
 904 }
 905
 906 static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv,
 907                                            struct i915_power_well *power_well)
 908 {
 909         return (I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0;
 910 }
 911
 912 static void gen9_assert_dbuf_enabled(struct drm_i915_private *dev_priv)
 913 {
 914         u32 tmp = I915_READ(DBUF_CTL);
 915
 916         WARN((tmp & (DBUF_POWER_STATE | DBUF_POWER_REQUEST)) !=
 917              (DBUF_POWER_STATE | DBUF_POWER_REQUEST),
 918              "Unexpected DBuf power power state (0x%08x)\n", tmp);
 919 }
 920
 921 static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
 922                                           struct i915_power_well *power_well)
 923 {
 924         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 925
 926         WARN_ON(dev_priv->cdclk_freq !=
 927                 dev_priv->display.get_display_clock_speed(dev_priv->dev));
 928
 929         gen9_assert_dbuf_enabled(dev_priv);
 930
 931         if (IS_BROXTON(dev_priv))
 932                 bxt_verify_ddi_phy_power_wells(dev_priv);
 933 }
 934
 935 static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
 936                                            struct i915_power_well *power_well)
 937 {
 938         if (!dev_priv->csr.dmc_payload)
 939                 return;
 940
 941         if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC6)
 942                 skl_enable_dc6(dev_priv);
 943         else if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5)
 944                 gen9_enable_dc5(dev_priv);
 945 }
 946
 947 static void gen9_dc_off_power_well_sync_hw(struct drm_i915_private *dev_priv,
 948                                            struct i915_power_well *power_well)
 949 {
 950         if (power_well->count > 0)
 951                 gen9_dc_off_power_well_enable(dev_priv, power_well);
 952         else
 953                 gen9_dc_off_power_well_disable(dev_priv, power_well);
 954 }
 955
 956 static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,
 957                                            struct i915_power_well *power_well)
 958 {
 959 }
 960
 961 static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,
 962                                              struct i915_power_well *power_well)
 963 {
 964         return true;
 965 }
 966
 967 static void vlv_set_power_well(struct drm_i915_private *dev_priv,
 968                                struct i915_power_well *power_well, bool enable)
 969 {
 970         enum punit_power_well power_well_id = power_well->data;
 971         u32 mask;
 972         u32 state;
 973         u32 ctrl;
 974
 975         mask = PUNIT_PWRGT_MASK(power_well_id);
 976         state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) :
 977                          PUNIT_PWRGT_PWR_GATE(power_well_id);
 978
 979         mutex_lock(&dev_priv->rps.hw_lock);
 980
 981 #define COND \
 982         ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)
 983
 984         if (COND)
 985                 goto out;
 986
 987         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL);
 988         ctrl &= ~mask;
 989         ctrl |= state;
 990         vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl);
 991
 992         if (wait_for(COND, 100))
 993                 DRM_ERROR("timeout setting power well state %08x (%08x)\n",
 994                           state,
 995                           vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL));
 996
 997 #undef COND
 998
 999 out:
1000         mutex_unlock(&dev_priv->rps.hw_lock);
1001 }
1002
1003 static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv,
1004                                    struct i915_power_well *power_well)
1005 {
1006         vlv_set_power_well(dev_priv, power_well, power_well->count > 0);
1007 }
1008
1009 static void vlv_power_well_enable(struct drm_i915_private *dev_priv,
1010                                   struct i915_power_well *power_well)
1011 {
1012         vlv_set_power_well(dev_priv, power_well, true);
1013 }
1014
1015 static void vlv_power_well_disable(struct drm_i915_private *dev_priv,
1016                                    struct i915_power_well *power_well)
1017 {
1018         vlv_set_power_well(dev_priv, power_well, false);
1019 }
1020
1021 static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
1022                                    struct i915_power_well *power_well)
1023 {
1024         int power_well_id = power_well->data;
1025         bool enabled = false;
1026         u32 mask;
1027         u32 state;
1028         u32 ctrl;
1029
1030         mask = PUNIT_PWRGT_MASK(power_well_id);
1031         ctrl = PUNIT_PWRGT_PWR_ON(power_well_id);
1032
1033         mutex_lock(&dev_priv->rps.hw_lock);
1034
1035         state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask;
1036         /*
1037          * We only ever set the power-on and power-gate states, anything
1038          * else is unexpected.
1039          */
1040         WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) &&
1041                 state != PUNIT_PWRGT_PWR_GATE(power_well_id));
1042         if (state == ctrl)
1043                 enabled = true;
1044
1045         /*
1046          * A transient state at this point would mean some unexpected party
1047          * is poking at the power controls too.
1048          */
1049         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask;
1050         WARN_ON(ctrl != state);
1051
1052         mutex_unlock(&dev_priv->rps.hw_lock);
1053
1054         return enabled;
1055 }
1056
1057 static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
1058 {
1059         I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
1060
1061         /*
1062          * Disable trickle feed and enable pnd deadline calculation
1063          */
1064         I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
1065         I915_WRITE(CBR1_VLV, 0);
1066
1067         WARN_ON(dev_priv->rawclk_freq == 0);
1068
1069         I915_WRITE(RAWCLK_FREQ_VLV,
1070                    DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 1000));
1071 }
1072
1073 static void vlv_display_power_well_init(struct drm_i915_private *dev_priv)
1074 {
1075         enum pipe pipe;
1076
1077         /*
1078          * Enable the CRI clock source so we can get at the
1079          * display and the reference clock for VGA
1080          * hotplug / manual detection. Supposedly DSI also
1081          * needs the ref clock up and running.
1082          *
1083          * CHV DPLL B/C have some issues if VGA mode is enabled.
1084          */
1085         for_each_pipe(dev_priv->dev, pipe) {
1086                 u32 val = I915_READ(DPLL(pipe));
1087
1088                 val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1089                 if (pipe != PIPE_A)
1090                         val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1091
1092                 I915_WRITE(DPLL(pipe), val);
1093         }
1094
1095         vlv_init_display_clock_gating(dev_priv);
1096
1097         spin_lock_irq(&dev_priv->irq_lock);
1098         valleyview_enable_display_irqs(dev_priv);
1099         spin_unlock_irq(&dev_priv->irq_lock);
1100
1101         /*
1102          * During driver initialization/resume we can avoid restoring the
1103          * part of the HW/SW state that will be inited anyway explicitly.
1104          */
1105         if (dev_priv->power_domains.initializing)
1106                 return;
1107
1108         intel_hpd_init(dev_priv);
1109
1110         i915_redisable_vga_power_on(dev_priv->dev);
1111 }
1112
1113 static void vlv_display_power_well_deinit(struct drm_i915_private *dev_priv)
1114 {
1115         spin_lock_irq(&dev_priv->irq_lock);
1116         valleyview_disable_display_irqs(dev_priv);
1117         spin_unlock_irq(&dev_priv->irq_lock);
1118
1119         /* make sure we're done processing display irqs */
1120         synchronize_irq(dev_priv->dev->irq);
1121
1122         intel_power_sequencer_reset(dev_priv);
1123 }
1124
1125 static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv,
1126                                           struct i915_power_well *power_well)
1127 {
1128         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
1129
1130         vlv_set_power_well(dev_priv, power_well, true);
1131
1132         vlv_display_power_well_init(dev_priv);
1133 }
1134
1135 static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv,
1136                                            struct i915_power_well *power_well)
1137 {
1138         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
1139
1140         vlv_display_power_well_deinit(dev_priv);
1141
1142         vlv_set_power_well(dev_priv, power_well, false);
1143 }
1144
1145 static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
1146                                            struct i915_power_well *power_well)
1147 {
1148         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
1149
1150         /* since ref/cri clock was enabled */
1151         udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
1152
1153         vlv_set_power_well(dev_priv, power_well, true);
1154
1155         /*
1156          * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1157          *  6.  De-assert cmn_reset/side_reset. Same as VLV X0.
1158          *   a. GUnit 0x2110 bit[0] set to 1 (def 0)
1159          *   b. The other bits such as sfr settings / modesel may all
1160          *      be set to 0.
1161          *
1162          * This should only be done on init and resume from S3 with
1163          * both PLLs disabled, or we risk losing DPIO and PLL
1164          * synchronization.
1165          */
1166         I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
1167 }
1168
1169 static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
1170                                             struct i915_power_well *power_well)
1171 {
1172         enum pipe pipe;
1173
1174         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
1175
1176         for_each_pipe(dev_priv, pipe)
1177                 assert_pll_disabled(dev_priv, pipe);
1178
1179         /* Assert common reset */
1180         I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST);
1181
1182         vlv_set_power_well(dev_priv, power_well, false);
1183 }
1184
1185 #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
1186
1187 static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv,
1188                                                  int power_well_id)
1189 {
1190         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1191         int i;
1192
1193         for (i = 0; i < power_domains->power_well_count; i++) {
1194                 struct i915_power_well *power_well;
1195
1196                 power_well = &power_domains->power_wells[i];
1197                 if (power_well->data == power_well_id)
1198                         return power_well;
1199         }
1200
1201         return NULL;
1202 }
1203
1204 #define BITS_SET(val, bits) (((val) & (bits)) == (bits))
1205
1206 static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
1207 {
1208         struct i915_power_well *cmn_bc =
1209                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
1210         struct i915_power_well *cmn_d =
1211                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D);
1212         u32 phy_control = dev_priv->chv_phy_control;
1213         u32 phy_status = 0;
1214         u32 phy_status_mask = 0xffffffff;
1215         u32 tmp;
1216
1217         /*
1218          * The BIOS can leave the PHY is some weird state
1219          * where it doesn't fully power down some parts.
1220          * Disable the asserts until the PHY has been fully
1221          * reset (ie. the power well has been disabled at
1222          * least once).
1223          */
1224         if (!dev_priv->chv_phy_assert[DPIO_PHY0])
1225                 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0) |
1226                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0) |
1227                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1) |
1228                                      PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1) |
1229                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0) |
1230                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1));
1231
1232         if (!dev_priv->chv_phy_assert[DPIO_PHY1])
1233                 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0) |
1234                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0) |
1235                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1));
1236
1237         if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) {
1238                 phy_status |= PHY_POWERGOOD(DPIO_PHY0);
1239
1240                 /* this assumes override is only used to enable lanes */
1241                 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0)) == 0)
1242                         phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0);
1243
1244                 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1)) == 0)
1245                         phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1);
1246
1247                 /* CL1 is on whenever anything is on in either channel */
1248                 if (BITS_SET(phy_control,
1249                              PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0) |
1250                              PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)))
1251                         phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0);
1252
1253                 /*
1254                  * The DPLLB check accounts for the pipe B + port A usage
1255                  * with CL2 powered up but all the lanes in the second channel
1256                  * powered down.
1257                  */
1258                 if (BITS_SET(phy_control,
1259                              PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)) &&
1260                     (I915_READ(DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0)
1261                         phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1);
1262
1263                 if (BITS_SET(phy_control,
1264                              PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH0)))
1265                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0);
1266                 if (BITS_SET(phy_control,
1267                              PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH0)))
1268                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1);
1269
1270                 if (BITS_SET(phy_control,
1271                              PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH1)))
1272                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0);
1273                 if (BITS_SET(phy_control,
1274                              PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH1)))
1275                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1);
1276         }
1277
1278         if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) {
1279                 phy_status |= PHY_POWERGOOD(DPIO_PHY1);
1280
1281                 /* this assumes override is only used to enable lanes */
1282                 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0)) == 0)
1283                         phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0);
1284
1285                 if (BITS_SET(phy_control,
1286                              PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0)))
1287                         phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0);
1288
1289                 if (BITS_SET(phy_control,
1290                              PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY1, DPIO_CH0)))
1291                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0);
1292                 if (BITS_SET(phy_control,
1293                              PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY1, DPIO_CH0)))
1294                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1);
1295         }
1296
1297         phy_status &= phy_status_mask;
1298
1299         /*
1300          * The PHY may be busy with some initial calibration and whatnot,
1301          * so the power state can take a while to actually change.
1302          */
1303         if (wait_for((tmp = I915_READ(DISPLAY_PHY_STATUS) & phy_status_mask) == phy_status, 10))
1304                 WARN(phy_status != tmp,
1305                      "Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n",
1306                      tmp, phy_status, dev_priv->chv_phy_control);
1307 }
1308
1309 #undef BITS_SET
1310
1311 static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
1312                                            struct i915_power_well *power_well)
1313 {
1314         enum dpio_phy phy;
1315         enum pipe pipe;
1316         uint32_t tmp;
1317
1318         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
1319                      power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
1320
1321         if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
1322                 pipe = PIPE_A;
1323                 phy = DPIO_PHY0;
1324         } else {
1325                 pipe = PIPE_C;
1326                 phy = DPIO_PHY1;
1327         }
1328
1329         /* since ref/cri clock was enabled */
1330         udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
1331         vlv_set_power_well(dev_priv, power_well, true);
1332
1333         /* Poll for phypwrgood signal */
1334         if (wait_for(I915_READ(DISPLAY_PHY_STATUS) & PHY_POWERGOOD(phy), 1))
1335                 DRM_ERROR("Display PHY %d is not power up\n", phy);
1336
1337         mutex_lock(&dev_priv->sb_lock);
1338
1339         /* Enable dynamic power down */
1340         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW28);
1341         tmp |= DPIO_DYNPWRDOWNEN_CH0 | DPIO_CL1POWERDOWNEN |
1342                 DPIO_SUS_CLK_CONFIG_GATE_CLKREQ;
1343         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW28, tmp);
1344
1345         if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
1346                 tmp = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW6_CH1);
1347                 tmp |= DPIO_DYNPWRDOWNEN_CH1;
1348                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW6_CH1, tmp);
1349         } else {
1350                 /*
1351                  * Force the non-existing CL2 off. BXT does this
1352                  * too, so maybe it saves some power even though
1353                  * CL2 doesn't exist?
1354                  */
1355                 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
1356                 tmp |= DPIO_CL2_LDOFUSE_PWRENB;
1357                 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, tmp);
1358         }
1359
1360         mutex_unlock(&dev_priv->sb_lock);
1361
1362         dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy);
1363         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1364
1365         DRM_DEBUG_KMS("Enabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
1366                       phy, dev_priv->chv_phy_control);
1367
1368         assert_chv_phy_status(dev_priv);
1369 }
1370
1371 static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
1372                                             struct i915_power_well *power_well)
1373 {
1374         enum dpio_phy phy;
1375
1376         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
1377                      power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
1378
1379         if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
1380                 phy = DPIO_PHY0;
1381                 assert_pll_disabled(dev_priv, PIPE_A);
1382                 assert_pll_disabled(dev_priv, PIPE_B);
1383         } else {
1384                 phy = DPIO_PHY1;
1385                 assert_pll_disabled(dev_priv, PIPE_C);
1386         }
1387
1388         dev_priv->chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy);
1389         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1390
1391         vlv_set_power_well(dev_priv, power_well, false);
1392
1393         DRM_DEBUG_KMS("Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
1394                       phy, dev_priv->chv_phy_control);
1395
1396         /* PHY is fully reset now, so we can enable the PHY state asserts */
1397         dev_priv->chv_phy_assert[phy] = true;
1398
1399         assert_chv_phy_status(dev_priv);
1400 }
1401
1402 static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1403                                      enum dpio_channel ch, bool override, unsigned int mask)
1404 {
1405         enum pipe pipe = phy == DPIO_PHY0 ? PIPE_A : PIPE_C;
1406         u32 reg, val, expected, actual;
1407
1408         /*
1409          * The BIOS can leave the PHY is some weird state
1410          * where it doesn't fully power down some parts.
1411          * Disable the asserts until the PHY has been fully
1412          * reset (ie. the power well has been disabled at
1413          * least once).
1414          */
1415         if (!dev_priv->chv_phy_assert[phy])
1416                 return;
1417
1418         if (ch == DPIO_CH0)
1419                 reg = _CHV_CMN_DW0_CH0;
1420         else
1421                 reg = _CHV_CMN_DW6_CH1;
1422
1423         mutex_lock(&dev_priv->sb_lock);
1424         val = vlv_dpio_read(dev_priv, pipe, reg);
1425         mutex_unlock(&dev_priv->sb_lock);
1426
1427         /*
1428          * This assumes !override is only used when the port is disabled.
1429          * All lanes should power down even without the override when
1430          * the port is disabled.
1431          */
1432         if (!override || mask == 0xf) {
1433                 expected = DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN;
1434                 /*
1435                  * If CH1 common lane is not active anymore
1436                  * (eg. for pipe B DPLL) the entire channel will
1437                  * shut down, which causes the common lane registers
1438                  * to read as 0. That means we can't actually check
1439                  * the lane power down status bits, but as the entire
1440                  * register reads as 0 it's a good indication that the
1441                  * channel is indeed entirely powered down.
1442                  */
1443                 if (ch == DPIO_CH1 && val == 0)
1444                         expected = 0;
1445         } else if (mask != 0x0) {
1446                 expected = DPIO_ANYDL_POWERDOWN;
1447         } else {
1448                 expected = 0;
1449         }
1450
1451         if (ch == DPIO_CH0)
1452                 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH0;
1453         else
1454                 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH1;
1455         actual &= DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN;
1456
1457         WARN(actual != expected,
1458              "Unexpected DPIO lane power down: all %d, any %d. Expected: all %d, any %d. (0x%x = 0x%08x)\n",
1459              !!(actual & DPIO_ALLDL_POWERDOWN), !!(actual & DPIO_ANYDL_POWERDOWN),
1460              !!(expected & DPIO_ALLDL_POWERDOWN), !!(expected & DPIO_ANYDL_POWERDOWN),
1461              reg, val);
1462 }
1463
1464 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1465                           enum dpio_channel ch, bool override)
1466 {
1467         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1468         bool was_override;
1469
1470         mutex_lock(&power_domains->lock);
1471
1472         was_override = dev_priv->chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1473
1474         if (override == was_override)
1475                 goto out;
1476
1477         if (override)
1478                 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1479         else
1480                 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1481
1482         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1483
1484         DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d (DPIO_PHY_CONTROL=0x%08x)\n",
1485                       phy, ch, dev_priv->chv_phy_control);
1486
1487         assert_chv_phy_status(dev_priv);
1488
1489 out:
1490         mutex_unlock(&power_domains->lock);
1491
1492         return was_override;
1493 }
1494
1495 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1496                              bool override, unsigned int mask)
1497 {
1498         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1499         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1500         enum dpio_phy phy = vlv_dport_to_phy(enc_to_dig_port(&encoder->base));
1501         enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
1502
1503         mutex_lock(&power_domains->lock);
1504
1505         dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch);
1506         dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch);
1507
1508         if (override)
1509                 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1510         else
1511                 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1512
1513         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1514
1515         DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d lanes 0x%x (PHY_CONTROL=0x%08x)\n",
1516                       phy, ch, mask, dev_priv->chv_phy_control);
1517
1518         assert_chv_phy_status(dev_priv);
1519
1520         assert_chv_phy_powergate(dev_priv, phy, ch, override, mask);
1521
1522         mutex_unlock(&power_domains->lock);
1523 }
1524
1525 static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv,
1526                                         struct i915_power_well *power_well)
1527 {
1528         enum pipe pipe = power_well->data;
1529         bool enabled;
1530         u32 state, ctrl;
1531
1532         mutex_lock(&dev_priv->rps.hw_lock);
1533
1534         state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe);
1535         /*
1536          * We only ever set the power-on and power-gate states, anything
1537          * else is unexpected.
1538          */
1539         WARN_ON(state != DP_SSS_PWR_ON(pipe) && state != DP_SSS_PWR_GATE(pipe));
1540         enabled = state == DP_SSS_PWR_ON(pipe);
1541
1542         /*
1543          * A transient state at this point would mean some unexpected party
1544          * is poking at the power controls too.
1545          */
1546         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe);
1547         WARN_ON(ctrl << 16 != state);
1548
1549         mutex_unlock(&dev_priv->rps.hw_lock);
1550
1551         return enabled;
1552 }
1553
1554 static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv,
1555                                     struct i915_power_well *power_well,
1556                                     bool enable)
1557 {
1558         enum pipe pipe = power_well->data;
1559         u32 state;
1560         u32 ctrl;
1561
1562         state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe);
1563
1564         mutex_lock(&dev_priv->rps.hw_lock);
1565
1566 #define COND \
1567         ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state)
1568
1569         if (COND)
1570                 goto out;
1571
1572         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
1573         ctrl &= ~DP_SSC_MASK(pipe);
1574         ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe);
1575         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl);
1576
1577         if (wait_for(COND, 100))
1578                 DRM_ERROR("timeout setting power well state %08x (%08x)\n",
1579                           state,
1580                           vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ));
1581
1582 #undef COND
1583
1584 out:
1585         mutex_unlock(&dev_priv->rps.hw_lock);
1586 }
1587
1588 static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv,
1589                                         struct i915_power_well *power_well)
1590 {
1591         WARN_ON_ONCE(power_well->data != PIPE_A);
1592
1593         chv_set_pipe_power_well(dev_priv, power_well, power_well->count > 0);
1594 }
1595
1596 static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv,
1597                                        struct i915_power_well *power_well)
1598 {
1599         WARN_ON_ONCE(power_well->data != PIPE_A);
1600
1601         chv_set_pipe_power_well(dev_priv, power_well, true);
1602
1603         vlv_display_power_well_init(dev_priv);
1604 }
1605
1606 static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv,
1607                                         struct i915_power_well *power_well)
1608 {
1609         WARN_ON_ONCE(power_well->data != PIPE_A);
1610
1611         vlv_display_power_well_deinit(dev_priv);
1612
1613         chv_set_pipe_power_well(dev_priv, power_well, false);
1614 }
1615
1616 static void
1617 __intel_display_power_get_domain(struct drm_i915_private *dev_priv,
1618                                  enum intel_display_power_domain domain)
1619 {
1620         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1621         struct i915_power_well *power_well;
1622         int i;
1623
1624         for_each_power_well(i, power_well, BIT(domain), power_domains)
1625                 intel_power_well_get(dev_priv, power_well);
1626
1627         power_domains->domain_use_count[domain]++;
1628 }
1629
1630 /**
1631  * intel_display_power_get - grab a power domain reference
1632  * @dev_priv: i915 device instance
1633  * @domain: power domain to reference
1634  *
1635  * This function grabs a power domain reference for @domain and ensures that the
1636  * power domain and all its parents are powered up. Therefore users should only
1637  * grab a reference to the innermost power domain they need.
1638  *
1639  * Any power domain reference obtained by this function must have a symmetric
1640  * call to intel_display_power_put() to release the reference again.
1641  */
1642 void intel_display_power_get(struct drm_i915_private *dev_priv,
1643                              enum intel_display_power_domain domain)
1644 {
1645         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1646
1647         intel_runtime_pm_get(dev_priv);
1648
1649         mutex_lock(&power_domains->lock);
1650
1651         __intel_display_power_get_domain(dev_priv, domain);
1652
1653         mutex_unlock(&power_domains->lock);
1654 }
1655
1656 /**
1657  * intel_display_power_get_if_enabled - grab a reference for an enabled display power domain
1658  * @dev_priv: i915 device instance
1659  * @domain: power domain to reference
1660  *
1661  * This function grabs a power domain reference for @domain and ensures that the
1662  * power domain and all its parents are powered up. Therefore users should only
1663  * grab a reference to the innermost power domain they need.
1664  *
1665  * Any power domain reference obtained by this function must have a symmetric
1666  * call to intel_display_power_put() to release the reference again.
1667  */
1668 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
1669                                         enum intel_display_power_domain domain)
1670 {
1671         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1672         bool is_enabled;
1673
1674         if (!intel_runtime_pm_get_if_in_use(dev_priv))
1675                 return false;
1676
1677         mutex_lock(&power_domains->lock);
1678
1679         if (__intel_display_power_is_enabled(dev_priv, domain)) {
1680                 __intel_display_power_get_domain(dev_priv, domain);
1681                 is_enabled = true;
1682         } else {
1683                 is_enabled = false;
1684         }
1685
1686         mutex_unlock(&power_domains->lock);
1687
1688         if (!is_enabled)
1689                 intel_runtime_pm_put(dev_priv);
1690
1691         return is_enabled;
1692 }
1693
1694 /**
1695  * intel_display_power_put - release a power domain reference
1696  * @dev_priv: i915 device instance
1697  * @domain: power domain to reference
1698  *
1699  * This function drops the power domain reference obtained by
1700  * intel_display_power_get() and might power down the corresponding hardware
1701  * block right away if this is the last reference.
1702  */
1703 void intel_display_power_put(struct drm_i915_private *dev_priv,
1704                              enum intel_display_power_domain domain)
1705 {
1706         struct i915_power_domains *power_domains;
1707         struct i915_power_well *power_well;
1708         int i;
1709
1710         power_domains = &dev_priv->power_domains;
1711
1712         mutex_lock(&power_domains->lock);
1713
1714         WARN(!power_domains->domain_use_count[domain],
1715              "Use count on domain %s is already zero\n",
1716              intel_display_power_domain_str(domain));
1717         power_domains->domain_use_count[domain]--;
1718
1719         for_each_power_well_rev(i, power_well, BIT(domain), power_domains)
1720                 intel_power_well_put(dev_priv, power_well);
1721
1722         mutex_unlock(&power_domains->lock);
1723
1724         intel_runtime_pm_put(dev_priv);
1725 }
1726
1727 #define HSW_DISPLAY_POWER_DOMAINS (                     \
1728         BIT(POWER_DOMAIN_PIPE_B) |                      \
1729         BIT(POWER_DOMAIN_PIPE_C) |                      \
1730         BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) |         \
1731         BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |         \
1732         BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |         \
1733         BIT(POWER_DOMAIN_TRANSCODER_A) |                \
1734         BIT(POWER_DOMAIN_TRANSCODER_B) |                \
1735         BIT(POWER_DOMAIN_TRANSCODER_C) |                \
1736         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |            \
1737         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |            \
1738         BIT(POWER_DOMAIN_PORT_DDI_D_LANES) |            \
1739         BIT(POWER_DOMAIN_PORT_CRT) | /* DDI E */        \
1740         BIT(POWER_DOMAIN_VGA) |                         \
1741         BIT(POWER_DOMAIN_AUDIO) |                       \
1742         BIT(POWER_DOMAIN_INIT))
1743
1744 #define BDW_DISPLAY_POWER_DOMAINS (                     \
1745         BIT(POWER_DOMAIN_PIPE_B) |                      \
1746         BIT(POWER_DOMAIN_PIPE_C) |                      \
1747         BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |         \
1748         BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |         \
1749         BIT(POWER_DOMAIN_TRANSCODER_A) |                \
1750         BIT(POWER_DOMAIN_TRANSCODER_B) |                \
1751         BIT(POWER_DOMAIN_TRANSCODER_C) |                \
1752         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |            \
1753         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |            \
1754         BIT(POWER_DOMAIN_PORT_DDI_D_LANES) |            \
1755         BIT(POWER_DOMAIN_PORT_CRT) | /* DDI E */        \
1756         BIT(POWER_DOMAIN_VGA) |                         \
1757         BIT(POWER_DOMAIN_AUDIO) |                       \
1758         BIT(POWER_DOMAIN_INIT))
1759
1760 #define VLV_DISPLAY_POWER_DOMAINS (             \
1761         BIT(POWER_DOMAIN_PIPE_A) |              \
1762         BIT(POWER_DOMAIN_PIPE_B) |              \
1763         BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
1764         BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
1765         BIT(POWER_DOMAIN_TRANSCODER_A) |        \
1766         BIT(POWER_DOMAIN_TRANSCODER_B) |        \
1767         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |    \
1768         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |    \
1769         BIT(POWER_DOMAIN_PORT_DSI) |            \
1770         BIT(POWER_DOMAIN_PORT_CRT) |            \
1771         BIT(POWER_DOMAIN_VGA) |                 \
1772         BIT(POWER_DOMAIN_AUDIO) |               \
1773         BIT(POWER_DOMAIN_AUX_B) |               \
1774         BIT(POWER_DOMAIN_AUX_C) |               \
1775         BIT(POWER_DOMAIN_GMBUS) |               \
1776         BIT(POWER_DOMAIN_INIT))
1777
1778 #define VLV_DPIO_CMN_BC_POWER_DOMAINS (         \
1779         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |    \
1780         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |    \
1781         BIT(POWER_DOMAIN_PORT_CRT) |            \
1782         BIT(POWER_DOMAIN_AUX_B) |               \
1783         BIT(POWER_DOMAIN_AUX_C) |               \
1784         BIT(POWER_DOMAIN_INIT))
1785
1786 #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS (  \
1787         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |    \
1788         BIT(POWER_DOMAIN_AUX_B) |               \
1789         BIT(POWER_DOMAIN_INIT))
1790
1791 #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS (  \
1792         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |    \
1793         BIT(POWER_DOMAIN_AUX_B) |               \
1794         BIT(POWER_DOMAIN_INIT))
1795
1796 #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS (  \
1797         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |    \
1798         BIT(POWER_DOMAIN_AUX_C) |               \
1799         BIT(POWER_DOMAIN_INIT))
1800
1801 #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS (  \
1802         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |    \
1803         BIT(POWER_DOMAIN_AUX_C) |               \
1804         BIT(POWER_DOMAIN_INIT))
1805
1806 #define CHV_DISPLAY_POWER_DOMAINS (             \
1807         BIT(POWER_DOMAIN_PIPE_A) |              \
1808         BIT(POWER_DOMAIN_PIPE_B) |              \
1809         BIT(POWER_DOMAIN_PIPE_C) |              \
1810         BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
1811         BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
1812         BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
1813         BIT(POWER_DOMAIN_TRANSCODER_A) |        \
1814         BIT(POWER_DOMAIN_TRANSCODER_B) |        \
1815         BIT(POWER_DOMAIN_TRANSCODER_C) |        \
1816         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |    \
1817         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |    \
1818         BIT(POWER_DOMAIN_PORT_DDI_D_LANES) |    \
1819         BIT(POWER_DOMAIN_PORT_DSI) |            \
1820         BIT(POWER_DOMAIN_VGA) |                 \
1821         BIT(POWER_DOMAIN_AUDIO) |               \
1822         BIT(POWER_DOMAIN_AUX_B) |               \
1823         BIT(POWER_DOMAIN_AUX_C) |               \
1824         BIT(POWER_DOMAIN_AUX_D) |               \
1825         BIT(POWER_DOMAIN_GMBUS) |               \
1826         BIT(POWER_DOMAIN_INIT))
1827
1828 #define CHV_DPIO_CMN_BC_POWER_DOMAINS (         \
1829         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |    \
1830         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |    \
1831         BIT(POWER_DOMAIN_AUX_B) |               \
1832         BIT(POWER_DOMAIN_AUX_C) |               \
1833         BIT(POWER_DOMAIN_INIT))
1834
1835 #define CHV_DPIO_CMN_D_POWER_DOMAINS (          \
1836         BIT(POWER_DOMAIN_PORT_DDI_D_LANES) |    \
1837         BIT(POWER_DOMAIN_AUX_D) |               \
1838         BIT(POWER_DOMAIN_INIT))
1839
1840 static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
1841         .sync_hw = i9xx_always_on_power_well_noop,
1842         .enable = i9xx_always_on_power_well_noop,
1843         .disable = i9xx_always_on_power_well_noop,
1844         .is_enabled = i9xx_always_on_power_well_enabled,
1845 };
1846
1847 static const struct i915_power_well_ops chv_pipe_power_well_ops = {
1848         .sync_hw = chv_pipe_power_well_sync_hw,
1849         .enable = chv_pipe_power_well_enable,
1850         .disable = chv_pipe_power_well_disable,
1851         .is_enabled = chv_pipe_power_well_enabled,
1852 };
1853
1854 static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = {
1855         .sync_hw = vlv_power_well_sync_hw,
1856         .enable = chv_dpio_cmn_power_well_enable,
1857         .disable = chv_dpio_cmn_power_well_disable,
1858         .is_enabled = vlv_power_well_enabled,
1859 };
1860
1861 static struct i915_power_well i9xx_always_on_power_well[] = {
1862         {
1863                 .name = "always-on",
1864                 .always_on = 1,
1865                 .domains = POWER_DOMAIN_MASK,
1866                 .ops = &i9xx_always_on_power_well_ops,
1867         },
1868 };
1869
1870 static const struct i915_power_well_ops hsw_power_well_ops = {
1871         .sync_hw = hsw_power_well_sync_hw,
1872         .enable = hsw_power_well_enable,
1873         .disable = hsw_power_well_disable,
1874         .is_enabled = hsw_power_well_enabled,
1875 };
1876
1877 static const struct i915_power_well_ops skl_power_well_ops = {
1878         .sync_hw = skl_power_well_sync_hw,
1879         .enable = skl_power_well_enable,
1880         .disable = skl_power_well_disable,
1881         .is_enabled = skl_power_well_enabled,
1882 };
1883
1884 static const struct i915_power_well_ops gen9_dc_off_power_well_ops = {
1885         .sync_hw = gen9_dc_off_power_well_sync_hw,
1886         .enable = gen9_dc_off_power_well_enable,
1887         .disable = gen9_dc_off_power_well_disable,
1888         .is_enabled = gen9_dc_off_power_well_enabled,
1889 };
1890
1891 static const struct i915_power_well_ops bxt_dpio_cmn_power_well_ops = {
1892         .sync_hw = bxt_dpio_cmn_power_well_sync_hw,
1893         .enable = bxt_dpio_cmn_power_well_enable,
1894         .disable = bxt_dpio_cmn_power_well_disable,
1895         .is_enabled = bxt_dpio_cmn_power_well_enabled,
1896 };
1897
1898 static struct i915_power_well hsw_power_wells[] = {
1899         {
1900                 .name = "always-on",
1901                 .always_on = 1,
1902                 .domains = POWER_DOMAIN_MASK,
1903                 .ops = &i9xx_always_on_power_well_ops,
1904         },
1905         {
1906                 .name = "display",
1907                 .domains = HSW_DISPLAY_POWER_DOMAINS,
1908                 .ops = &hsw_power_well_ops,
1909         },
1910 };
1911
1912 static struct i915_power_well bdw_power_wells[] = {
1913         {
1914                 .name = "always-on",
1915                 .always_on = 1,
1916                 .domains = POWER_DOMAIN_MASK,
1917                 .ops = &i9xx_always_on_power_well_ops,
1918         },
1919         {
1920                 .name = "display",
1921                 .domains = BDW_DISPLAY_POWER_DOMAINS,
1922                 .ops = &hsw_power_well_ops,
1923         },
1924 };
1925
1926 static const struct i915_power_well_ops vlv_display_power_well_ops = {
1927         .sync_hw = vlv_power_well_sync_hw,
1928         .enable = vlv_display_power_well_enable,
1929         .disable = vlv_display_power_well_disable,
1930         .is_enabled = vlv_power_well_enabled,
1931 };
1932
1933 static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = {
1934         .sync_hw = vlv_power_well_sync_hw,
1935         .enable = vlv_dpio_cmn_power_well_enable,
1936         .disable = vlv_dpio_cmn_power_well_disable,
1937         .is_enabled = vlv_power_well_enabled,
1938 };
1939
1940 static const struct i915_power_well_ops vlv_dpio_power_well_ops = {
1941         .sync_hw = vlv_power_well_sync_hw,
1942         .enable = vlv_power_well_enable,
1943         .disable = vlv_power_well_disable,
1944         .is_enabled = vlv_power_well_enabled,
1945 };
1946
1947 static struct i915_power_well vlv_power_wells[] = {
1948         {
1949                 .name = "always-on",
1950                 .always_on = 1,
1951                 .domains = POWER_DOMAIN_MASK,
1952                 .ops = &i9xx_always_on_power_well_ops,
1953                 .data = PUNIT_POWER_WELL_ALWAYS_ON,
1954         },
1955         {
1956                 .name = "display",
1957                 .domains = VLV_DISPLAY_POWER_DOMAINS,
1958                 .data = PUNIT_POWER_WELL_DISP2D,
1959                 .ops = &vlv_display_power_well_ops,
1960         },
1961         {
1962                 .name = "dpio-tx-b-01",
1963                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1964                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1965                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1966                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1967                 .ops = &vlv_dpio_power_well_ops,
1968                 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
1969         },
1970         {
1971                 .name = "dpio-tx-b-23",
1972                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1973                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1974                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1975                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1976                 .ops = &vlv_dpio_power_well_ops,
1977                 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
1978         },
1979         {
1980                 .name = "dpio-tx-c-01",
1981                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1982                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1983                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1984                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1985                 .ops = &vlv_dpio_power_well_ops,
1986                 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
1987         },
1988         {
1989                 .name = "dpio-tx-c-23",
1990                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1991                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1992                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1993                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1994                 .ops = &vlv_dpio_power_well_ops,
1995                 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
1996         },
1997         {
1998                 .name = "dpio-common",
1999                 .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,
2000                 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
2001                 .ops = &vlv_dpio_cmn_power_well_ops,
2002         },
2003 };
2004
2005 static struct i915_power_well chv_power_wells[] = {
2006         {
2007                 .name = "always-on",
2008                 .always_on = 1,
2009                 .domains = POWER_DOMAIN_MASK,
2010                 .ops = &i9xx_always_on_power_well_ops,
2011         },
2012         {
2013                 .name = "display",
2014                 /*
2015                  * Pipe A power well is the new disp2d well. Pipe B and C
2016                  * power wells don't actually exist. Pipe A power well is
2017                  * required for any pipe to work.
2018                  */
2019                 .domains = CHV_DISPLAY_POWER_DOMAINS,
2020                 .data = PIPE_A,
2021                 .ops = &chv_pipe_power_well_ops,
2022         },
2023         {
2024                 .name = "dpio-common-bc",
2025                 .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS,
2026                 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
2027                 .ops = &chv_dpio_cmn_power_well_ops,
2028         },
2029         {
2030                 .name = "dpio-common-d",
2031                 .domains = CHV_DPIO_CMN_D_POWER_DOMAINS,
2032                 .data = PUNIT_POWER_WELL_DPIO_CMN_D,
2033                 .ops = &chv_dpio_cmn_power_well_ops,
2034         },
2035 };
2036
2037 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
2038                                     int power_well_id)
2039 {
2040         struct i915_power_well *power_well;
2041         bool ret;
2042
2043         power_well = lookup_power_well(dev_priv, power_well_id);
2044         ret = power_well->ops->is_enabled(dev_priv, power_well);
2045
2046         return ret;
2047 }
2048
2049 static struct i915_power_well skl_power_wells[] = {
2050         {
2051                 .name = "always-on",
2052                 .always_on = 1,
2053                 .domains = POWER_DOMAIN_MASK,
2054                 .ops = &i9xx_always_on_power_well_ops,
2055                 .data = SKL_DISP_PW_ALWAYS_ON,
2056         },
2057         {
2058                 .name = "power well 1",
2059                 /* Handled by the DMC firmware */
2060                 .domains = 0,
2061                 .ops = &skl_power_well_ops,
2062                 .data = SKL_DISP_PW_1,
2063         },
2064         {
2065                 .name = "MISC IO power well",
2066                 /* Handled by the DMC firmware */
2067                 .domains = 0,
2068                 .ops = &skl_power_well_ops,
2069                 .data = SKL_DISP_PW_MISC_IO,
2070         },
2071         {
2072                 .name = "DC off",
2073                 .domains = SKL_DISPLAY_DC_OFF_POWER_DOMAINS,
2074                 .ops = &gen9_dc_off_power_well_ops,
2075                 .data = SKL_DISP_PW_DC_OFF,
2076         },
2077         {
2078                 .name = "power well 2",
2079                 .domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS,
2080                 .ops = &skl_power_well_ops,
2081                 .data = SKL_DISP_PW_2,
2082         },
2083         {
2084                 .name = "DDI A/E power well",
2085                 .domains = SKL_DISPLAY_DDI_A_E_POWER_DOMAINS,
2086                 .ops = &skl_power_well_ops,
2087                 .data = SKL_DISP_PW_DDI_A_E,
2088         },
2089         {
2090                 .name = "DDI B power well",
2091                 .domains = SKL_DISPLAY_DDI_B_POWER_DOMAINS,
2092                 .ops = &skl_power_well_ops,
2093                 .data = SKL_DISP_PW_DDI_B,
2094         },
2095         {
2096                 .name = "DDI C power well",
2097                 .domains = SKL_DISPLAY_DDI_C_POWER_DOMAINS,
2098                 .ops = &skl_power_well_ops,
2099                 .data = SKL_DISP_PW_DDI_C,
2100         },
2101         {
2102                 .name = "DDI D power well",
2103                 .domains = SKL_DISPLAY_DDI_D_POWER_DOMAINS,
2104                 .ops = &skl_power_well_ops,
2105                 .data = SKL_DISP_PW_DDI_D,
2106         },
2107 };
2108
2109 static struct i915_power_well bxt_power_wells[] = {
2110         {
2111                 .name = "always-on",
2112                 .always_on = 1,
2113                 .domains = POWER_DOMAIN_MASK,
2114                 .ops = &i9xx_always_on_power_well_ops,
2115         },
2116         {
2117                 .name = "power well 1",
2118                 .domains = 0,
2119                 .ops = &skl_power_well_ops,
2120                 .data = SKL_DISP_PW_1,
2121         },
2122         {
2123                 .name = "DC off",
2124                 .domains = BXT_DISPLAY_DC_OFF_POWER_DOMAINS,
2125                 .ops = &gen9_dc_off_power_well_ops,
2126                 .data = SKL_DISP_PW_DC_OFF,
2127         },
2128         {
2129                 .name = "power well 2",
2130                 .domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS,
2131                 .ops = &skl_power_well_ops,
2132                 .data = SKL_DISP_PW_2,
2133         },
2134         {
2135                 .name = "dpio-common-a",
2136                 .domains = BXT_DPIO_CMN_A_POWER_DOMAINS,
2137                 .ops = &bxt_dpio_cmn_power_well_ops,
2138                 .data = BXT_DPIO_CMN_A,
2139         },
2140         {
2141                 .name = "dpio-common-bc",
2142                 .domains = BXT_DPIO_CMN_BC_POWER_DOMAINS,
2143                 .ops = &bxt_dpio_cmn_power_well_ops,
2144                 .data = BXT_DPIO_CMN_BC,
2145         },
2146 };
2147
2148 static int
2149 sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv,
2150                                    int disable_power_well)
2151 {
2152         if (disable_power_well >= 0)
2153                 return !!disable_power_well;
2154
2155         return 1;
2156 }
2157
2158 static uint32_t get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
2159                                     int enable_dc)
2160 {
2161         uint32_t mask;
2162         int requested_dc;
2163         int max_dc;
2164
2165         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
2166                 max_dc = 2;
2167                 mask = 0;
2168         } else if (IS_BROXTON(dev_priv)) {
2169                 max_dc = 1;
2170                 /*
2171                  * DC9 has a separate HW flow from the rest of the DC states,
2172                  * not depending on the DMC firmware. It's needed by system
2173                  * suspend/resume, so allow it unconditionally.
2174                  */
2175                 mask = DC_STATE_EN_DC9;
2176         } else {
2177                 max_dc = 0;
2178                 mask = 0;
2179         }
2180
2181         if (!i915.disable_power_well)
2182                 max_dc = 0;
2183
2184         if (enable_dc >= 0 && enable_dc <= max_dc) {
2185                 requested_dc = enable_dc;
2186         } else if (enable_dc == -1) {
2187                 requested_dc = max_dc;
2188         } else if (enable_dc > max_dc && enable_dc <= 2) {
2189                 DRM_DEBUG_KMS("Adjusting requested max DC state (%d->%d)\n",
2190                               enable_dc, max_dc);
2191                 requested_dc = max_dc;
2192         } else {
2193                 DRM_ERROR("Unexpected value for enable_dc (%d)\n", enable_dc);
2194                 requested_dc = max_dc;
2195         }
2196
2197         if (requested_dc > 1)
2198                 mask |= DC_STATE_EN_UPTO_DC6;
2199         if (requested_dc > 0)
2200                 mask |= DC_STATE_EN_UPTO_DC5;
2201
2202         DRM_DEBUG_KMS("Allowed DC state mask %02x\n", mask);
2203
2204         return mask;
2205 }
2206
2207 #define set_power_wells(power_domains, __power_wells) ({                \
2208         (power_domains)->power_wells = (__power_wells);                 \
2209         (power_domains)->power_well_count = ARRAY_SIZE(__power_wells);  \
2210 })
2211
2212 /**
2213  * intel_power_domains_init - initializes the power domain structures
2214  * @dev_priv: i915 device instance
2215  *
2216  * Initializes the power domain structures for @dev_priv depending upon the
2217  * supported platform.
2218  */
2219 int intel_power_domains_init(struct drm_i915_private *dev_priv)
2220 {
2221         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2222
2223         i915.disable_power_well = sanitize_disable_power_well_option(dev_priv,
2224                                                      i915.disable_power_well);
2225         dev_priv->csr.allowed_dc_mask = get_allowed_dc_mask(dev_priv,
2226                                                             i915.enable_dc);
2227
2228         BUILD_BUG_ON(POWER_DOMAIN_NUM > 31);
2229
2230         mutex_init(&power_domains->lock);
2231
2232         /*
2233          * The enabling order will be from lower to higher indexed wells,
2234          * the disabling order is reversed.
2235          */
2236         if (IS_HASWELL(dev_priv)) {
2237                 set_power_wells(power_domains, hsw_power_wells);
2238         } else if (IS_BROADWELL(dev_priv)) {
2239                 set_power_wells(power_domains, bdw_power_wells);
2240         } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
2241                 set_power_wells(power_domains, skl_power_wells);
2242         } else if (IS_BROXTON(dev_priv)) {
2243                 set_power_wells(power_domains, bxt_power_wells);
2244         } else if (IS_CHERRYVIEW(dev_priv)) {
2245                 set_power_wells(power_domains, chv_power_wells);
2246         } else if (IS_VALLEYVIEW(dev_priv)) {
2247                 set_power_wells(power_domains, vlv_power_wells);
2248         } else {
2249                 set_power_wells(power_domains, i9xx_always_on_power_well);
2250         }
2251
2252         return 0;
2253 }
2254
2255 /**
2256  * intel_power_domains_fini - finalizes the power domain structures
2257  * @dev_priv: i915 device instance
2258  *
2259  * Finalizes the power domain structures for @dev_priv depending upon the
2260  * supported platform. This function also disables runtime pm and ensures that
2261  * the device stays powered up so that the driver can be reloaded.
2262  */
2263 void intel_power_domains_fini(struct drm_i915_private *dev_priv)
2264 {
2265         struct device *device = &dev_priv->dev->pdev->dev;
2266
2267         /*
2268          * The i915.ko module is still not prepared to be loaded when
2269          * the power well is not enabled, so just enable it in case
2270          * we're going to unload/reload.
2271          * The following also reacquires the RPM reference the core passed
2272          * to the driver during loading, which is dropped in
2273          * intel_runtime_pm_enable(). We have to hand back the control of the
2274          * device to the core with this reference held.
2275          */
2276         intel_display_set_init_power(dev_priv, true);
2277
2278         /* Remove the refcount we took to keep power well support disabled. */
2279         if (!i915.disable_power_well)
2280                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
2281
2282         /*
2283          * Remove the refcount we took in intel_runtime_pm_enable() in case
2284          * the platform doesn't support runtime PM.
2285          */
2286         if (!HAS_RUNTIME_PM(dev_priv))
2287                 pm_runtime_put(device);
2288 }
2289
2290 static void intel_power_domains_sync_hw(struct drm_i915_private *dev_priv)
2291 {
2292         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2293         struct i915_power_well *power_well;
2294         int i;
2295
2296         mutex_lock(&power_domains->lock);
2297         for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
2298                 power_well->ops->sync_hw(dev_priv, power_well);
2299                 power_well->hw_enabled = power_well->ops->is_enabled(dev_priv,
2300                                                                      power_well);
2301         }
2302         mutex_unlock(&power_domains->lock);
2303 }
2304
2305 static void gen9_dbuf_enable(struct drm_i915_private *dev_priv)
2306 {
2307         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
2308         POSTING_READ(DBUF_CTL);
2309
2310         udelay(10);
2311
2312         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
2313                 DRM_ERROR("DBuf power enable timeout\n");
2314 }
2315
2316 static void gen9_dbuf_disable(struct drm_i915_private *dev_priv)
2317 {
2318         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
2319         POSTING_READ(DBUF_CTL);
2320
2321         udelay(10);
2322
2323         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
2324                 DRM_ERROR("DBuf power disable timeout!\n");
2325 }
2326
2327 static void skl_display_core_init(struct drm_i915_private *dev_priv,
2328                                    bool resume)
2329 {
2330         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2331         struct i915_power_well *well;
2332         uint32_t val;
2333
2334         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
2335
2336         /* enable PCH reset handshake */
2337         val = I915_READ(HSW_NDE_RSTWRN_OPT);
2338         I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
2339
2340         /* enable PG1 and Misc I/O */
2341         mutex_lock(&power_domains->lock);
2342
2343         well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
2344         intel_power_well_enable(dev_priv, well);
2345
2346         well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);
2347         intel_power_well_enable(dev_priv, well);
2348
2349         mutex_unlock(&power_domains->lock);
2350
2351         skl_init_cdclk(dev_priv);
2352
2353         gen9_dbuf_enable(dev_priv);
2354
2355         if (resume && dev_priv->csr.dmc_payload)
2356                 intel_csr_load_program(dev_priv);
2357 }
2358
2359 static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
2360 {
2361         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2362         struct i915_power_well *well;
2363
2364         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
2365
2366         gen9_dbuf_disable(dev_priv);
2367
2368         skl_uninit_cdclk(dev_priv);
2369
2370         /* The spec doesn't call for removing the reset handshake flag */
2371         /* disable PG1 and Misc I/O */
2372
2373         mutex_lock(&power_domains->lock);
2374
2375         well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);
2376         intel_power_well_disable(dev_priv, well);
2377
2378         well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
2379         intel_power_well_disable(dev_priv, well);
2380
2381         mutex_unlock(&power_domains->lock);
2382 }
2383
2384 void bxt_display_core_init(struct drm_i915_private *dev_priv,
2385                            bool resume)
2386 {
2387         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2388         struct i915_power_well *well;
2389         uint32_t val;
2390
2391         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
2392
2393         /*
2394          * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
2395          * or else the reset will hang because there is no PCH to respond.
2396          * Move the handshake programming to initialization sequence.
2397          * Previously was left up to BIOS.
2398          */
2399         val = I915_READ(HSW_NDE_RSTWRN_OPT);
2400         val &= ~RESET_PCH_HANDSHAKE_ENABLE;
2401         I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
2402
2403         /* Enable PG1 */
2404         mutex_lock(&power_domains->lock);
2405
2406         well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
2407         intel_power_well_enable(dev_priv, well);
2408
2409         mutex_unlock(&power_domains->lock);
2410
2411         bxt_init_cdclk(dev_priv);
2412
2413         gen9_dbuf_enable(dev_priv);
2414
2415         if (resume && dev_priv->csr.dmc_payload)
2416                 intel_csr_load_program(dev_priv);
2417 }
2418
2419 void bxt_display_core_uninit(struct drm_i915_private *dev_priv)
2420 {
2421         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2422         struct i915_power_well *well;
2423
2424         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
2425
2426         gen9_dbuf_disable(dev_priv);
2427
2428         bxt_uninit_cdclk(dev_priv);
2429
2430         /* The spec doesn't call for removing the reset handshake flag */
2431
2432         /* Disable PG1 */
2433         mutex_lock(&power_domains->lock);
2434
2435         well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
2436         intel_power_well_disable(dev_priv, well);
2437
2438         mutex_unlock(&power_domains->lock);
2439 }
2440
2441 static void chv_phy_control_init(struct drm_i915_private *dev_priv)
2442 {
2443         struct i915_power_well *cmn_bc =
2444                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
2445         struct i915_power_well *cmn_d =
2446                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D);
2447
2448         /*
2449          * DISPLAY_PHY_CONTROL can get corrupted if read. As a
2450          * workaround never ever read DISPLAY_PHY_CONTROL, and
2451          * instead maintain a shadow copy ourselves. Use the actual
2452          * power well state and lane status to reconstruct the
2453          * expected initial value.
2454          */
2455         dev_priv->chv_phy_control =
2456                 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY0) |
2457                 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY1) |
2458                 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH0) |
2459                 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH1) |
2460                 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY1, DPIO_CH0);
2461
2462         /*
2463          * If all lanes are disabled we leave the override disabled
2464          * with all power down bits cleared to match the state we
2465          * would use after disabling the port. Otherwise enable the
2466          * override and set the lane powerdown bits accding to the
2467          * current lane status.
2468          */
2469         if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) {
2470                 uint32_t status = I915_READ(DPLL(PIPE_A));
2471                 unsigned int mask;
2472
2473                 mask = status & DPLL_PORTB_READY_MASK;
2474                 if (mask == 0xf)
2475                         mask = 0x0;
2476                 else
2477                         dev_priv->chv_phy_control |=
2478                                 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0);
2479
2480                 dev_priv->chv_phy_control |=
2481                         PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH0);
2482
2483                 mask = (status & DPLL_PORTC_READY_MASK) >> 4;
2484                 if (mask == 0xf)
2485                         mask = 0x0;
2486                 else
2487                         dev_priv->chv_phy_control |=
2488                                 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1);
2489
2490                 dev_priv->chv_phy_control |=
2491                         PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH1);
2492
2493                 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0);
2494
2495                 dev_priv->chv_phy_assert[DPIO_PHY0] = false;
2496         } else {
2497                 dev_priv->chv_phy_assert[DPIO_PHY0] = true;
2498         }
2499
2500         if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) {
2501                 uint32_t status = I915_READ(DPIO_PHY_STATUS);
2502                 unsigned int mask;
2503
2504                 mask = status & DPLL_PORTD_READY_MASK;
2505
2506                 if (mask == 0xf)
2507                         mask = 0x0;
2508                 else
2509                         dev_priv->chv_phy_control |=
2510                                 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0);
2511
2512                 dev_priv->chv_phy_control |=
2513                         PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY1, DPIO_CH0);
2514
2515                 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1);
2516
2517                 dev_priv->chv_phy_assert[DPIO_PHY1] = false;
2518         } else {
2519                 dev_priv->chv_phy_assert[DPIO_PHY1] = true;
2520         }
2521
2522         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
2523
2524         DRM_DEBUG_KMS("Initial PHY_CONTROL=0x%08x\n",
2525                       dev_priv->chv_phy_control);
2526 }
2527
2528 static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv)
2529 {
2530         struct i915_power_well *cmn =
2531                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
2532         struct i915_power_well *disp2d =
2533                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D);
2534
2535         /* If the display might be already active skip this */
2536         if (cmn->ops->is_enabled(dev_priv, cmn) &&
2537             disp2d->ops->is_enabled(dev_priv, disp2d) &&
2538             I915_READ(DPIO_CTL) & DPIO_CMNRST)
2539                 return;
2540
2541         DRM_DEBUG_KMS("toggling display PHY side reset\n");
2542
2543         /* cmnlane needs DPLL registers */
2544         disp2d->ops->enable(dev_priv, disp2d);
2545
2546         /*
2547          * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx:
2548          * Need to assert and de-assert PHY SB reset by gating the
2549          * common lane power, then un-gating it.
2550          * Simply ungating isn't enough to reset the PHY enough to get
2551          * ports and lanes running.
2552          */
2553         cmn->ops->disable(dev_priv, cmn);
2554 }
2555
2556 /**
2557  * intel_power_domains_init_hw - initialize hardware power domain state
2558  * @dev_priv: i915 device instance
2559  * @resume: Called from resume code paths or not
2560  *
2561  * This function initializes the hardware power domain state and enables all
2562  * power domains using intel_display_set_init_power().
2563  */
2564 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume)
2565 {
2566         struct drm_device *dev = dev_priv->dev;
2567         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2568
2569         power_domains->initializing = true;
2570
2571         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
2572                 skl_display_core_init(dev_priv, resume);
2573         } else if (IS_BROXTON(dev)) {
2574                 bxt_display_core_init(dev_priv, resume);
2575         } else if (IS_CHERRYVIEW(dev)) {
2576                 mutex_lock(&power_domains->lock);
2577                 chv_phy_control_init(dev_priv);
2578                 mutex_unlock(&power_domains->lock);
2579         } else if (IS_VALLEYVIEW(dev)) {
2580                 mutex_lock(&power_domains->lock);
2581                 vlv_cmnlane_wa(dev_priv);
2582                 mutex_unlock(&power_domains->lock);
2583         }
2584
2585         /* For now, we need the power well to be always enabled. */
2586         intel_display_set_init_power(dev_priv, true);
2587         /* Disable power support if the user asked so. */
2588         if (!i915.disable_power_well)
2589                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
2590         intel_power_domains_sync_hw(dev_priv);
2591         power_domains->initializing = false;
2592 }
2593
2594 /**
2595  * intel_power_domains_suspend - suspend power domain state
2596  * @dev_priv: i915 device instance
2597  *
2598  * This function prepares the hardware power domain state before entering
2599  * system suspend. It must be paired with intel_power_domains_init_hw().
2600  */
2601 void intel_power_domains_suspend(struct drm_i915_private *dev_priv)
2602 {
2603         /*
2604          * Even if power well support was disabled we still want to disable
2605          * power wells while we are system suspended.
2606          */
2607         if (!i915.disable_power_well)
2608                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
2609
2610         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
2611                 skl_display_core_uninit(dev_priv);
2612         else if (IS_BROXTON(dev_priv))
2613                 bxt_display_core_uninit(dev_priv);
2614 }
2615
2616 /**
2617  * intel_runtime_pm_get - grab a runtime pm reference
2618  * @dev_priv: i915 device instance
2619  *
2620  * This function grabs a device-level runtime pm reference (mostly used for GEM
2621  * code to ensure the GTT or GT is on) and ensures that it is powered up.
2622  *
2623  * Any runtime pm reference obtained by this function must have a symmetric
2624  * call to intel_runtime_pm_put() to release the reference again.
2625  */
2626 void intel_runtime_pm_get(struct drm_i915_private *dev_priv)
2627 {
2628         struct drm_device *dev = dev_priv->dev;
2629         struct device *device = &dev->pdev->dev;
2630
2631         pm_runtime_get_sync(device);
2632
2633         atomic_inc(&dev_priv->pm.wakeref_count);
2634         assert_rpm_wakelock_held(dev_priv);
2635 }
2636
2637 /**
2638  * intel_runtime_pm_get_if_in_use - grab a runtime pm reference if device in use
2639  * @dev_priv: i915 device instance
2640  *
2641  * This function grabs a device-level runtime pm reference if the device is
2642  * already in use and ensures that it is powered up.
2643  *
2644  * Any runtime pm reference obtained by this function must have a symmetric
2645  * call to intel_runtime_pm_put() to release the reference again.
2646  */
2647 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv)
2648 {
2649         struct drm_device *dev = dev_priv->dev;
2650         struct device *device = &dev->pdev->dev;
2651
2652         if (IS_ENABLED(CONFIG_PM)) {
2653                 int ret = pm_runtime_get_if_in_use(device);
2654
2655                 /*
2656                  * In cases runtime PM is disabled by the RPM core and we get
2657                  * an -EINVAL return value we are not supposed to call this
2658                  * function, since the power state is undefined. This applies
2659                  * atm to the late/early system suspend/resume handlers.
2660                  */
2661                 WARN_ON_ONCE(ret < 0);
2662                 if (ret <= 0)
2663                         return false;
2664         }
2665
2666         atomic_inc(&dev_priv->pm.wakeref_count);
2667         assert_rpm_wakelock_held(dev_priv);
2668
2669         return true;
2670 }
2671
2672 /**
2673  * intel_runtime_pm_get_noresume - grab a runtime pm reference
2674  * @dev_priv: i915 device instance
2675  *
2676  * This function grabs a device-level runtime pm reference (mostly used for GEM
2677  * code to ensure the GTT or GT is on).
2678  *
2679  * It will _not_ power up the device but instead only check that it's powered
2680  * on.  Therefore it is only valid to call this functions from contexts where
2681  * the device is known to be powered up and where trying to power it up would
2682  * result in hilarity and deadlocks. That pretty much means only the system
2683  * suspend/resume code where this is used to grab runtime pm references for
2684  * delayed setup down in work items.
2685  *
2686  * Any runtime pm reference obtained by this function must have a symmetric
2687  * call to intel_runtime_pm_put() to release the reference again.
2688  */
2689 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv)
2690 {
2691         struct drm_device *dev = dev_priv->dev;
2692         struct device *device = &dev->pdev->dev;
2693
2694         assert_rpm_wakelock_held(dev_priv);
2695         pm_runtime_get_noresume(device);
2696
2697         atomic_inc(&dev_priv->pm.wakeref_count);
2698 }
2699
2700 /**
2701  * intel_runtime_pm_put - release a runtime pm reference
2702  * @dev_priv: i915 device instance
2703  *
2704  * This function drops the device-level runtime pm reference obtained by
2705  * intel_runtime_pm_get() and might power down the corresponding
2706  * hardware block right away if this is the last reference.
2707  */
2708 void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
2709 {
2710         struct drm_device *dev = dev_priv->dev;
2711         struct device *device = &dev->pdev->dev;
2712
2713         assert_rpm_wakelock_held(dev_priv);
2714         if (atomic_dec_and_test(&dev_priv->pm.wakeref_count))
2715                 atomic_inc(&dev_priv->pm.atomic_seq);
2716
2717         pm_runtime_mark_last_busy(device);
2718         pm_runtime_put_autosuspend(device);
2719 }
2720
2721 /**
2722  * intel_runtime_pm_enable - enable runtime pm
2723  * @dev_priv: i915 device instance
2724  *
2725  * This function enables runtime pm at the end of the driver load sequence.
2726  *
2727  * Note that this function does currently not enable runtime pm for the
2728  * subordinate display power domains. That is only done on the first modeset
2729  * using intel_display_set_init_power().
2730  */
2731 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv)
2732 {
2733         struct drm_device *dev = dev_priv->dev;
2734         struct device *device = &dev->pdev->dev;
2735
2736         pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */
2737         pm_runtime_mark_last_busy(device);
2738
2739         /*
2740          * Take a permanent reference to disable the RPM functionality and drop
2741          * it only when unloading the driver. Use the low level get/put helpers,
2742          * so the driver's own RPM reference tracking asserts also work on
2743          * platforms without RPM support.
2744          */
2745         if (!HAS_RUNTIME_PM(dev)) {
2746                 pm_runtime_dont_use_autosuspend(device);
2747                 pm_runtime_get_sync(device);
2748         } else {
2749                 pm_runtime_use_autosuspend(device);
2750         }
2751
2752         /*
2753          * The core calls the driver load handler with an RPM reference held.
2754          * We drop that here and will reacquire it during unloading in
2755          * intel_power_domains_fini().
2756          */
2757         pm_runtime_put_autosuspend(device);
2758 }
2759