drivers/gpu/drm/i915/intel_runtime_pm.c

   1 /*
   2  * Copyright © 2012-2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *    Daniel Vetter <daniel.vetter@ffwll.ch>
  26  *
  27  */
  28
  29 #include <linux/pm_runtime.h>
  30 #include <linux/vgaarb.h>
  31
  32 #include "i915_drv.h"
  33 #include "intel_drv.h"
  34
  35 /**
  36  * DOC: runtime pm
  37  *
  38  * The i915 driver supports dynamic enabling and disabling of entire hardware
  39  * blocks at runtime. This is especially important on the display side where
  40  * software is supposed to control many power gates manually on recent hardware,
  41  * since on the GT side a lot of the power management is done by the hardware.
  42  * But even there some manual control at the device level is required.
  43  *
  44  * Since i915 supports a diverse set of platforms with a unified codebase and
  45  * hardware engineers just love to shuffle functionality around between power
  46  * domains there's a sizeable amount of indirection required. This file provides
  47  * generic functions to the driver for grabbing and releasing references for
  48  * abstract power domains. It then maps those to the actual power wells
  49  * present for a given platform.
  50  */
  51
  52 #define for_each_power_well(i, power_well, domain_mask, power_domains)  \
  53         for (i = 0;                                                     \
  54              i < (power_domains)->power_well_count &&                   \
  55                  ((power_well) = &(power_domains)->power_wells[i]);     \
  56              i++)                                                       \
  57                 for_each_if ((power_well)->domains & (domain_mask))
  58
  59 #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
  60         for (i = (power_domains)->power_well_count - 1;                  \
  61              i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
  62              i--)                                                        \
  63                 for_each_if ((power_well)->domains & (domain_mask))
  64
  65 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
  66                                     int power_well_id);
  67
  68 const char *
  69 intel_display_power_domain_str(enum intel_display_power_domain domain)
  70 {
  71         switch (domain) {
  72         case POWER_DOMAIN_PIPE_A:
  73                 return "PIPE_A";
  74         case POWER_DOMAIN_PIPE_B:
  75                 return "PIPE_B";
  76         case POWER_DOMAIN_PIPE_C:
  77                 return "PIPE_C";
  78         case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
  79                 return "PIPE_A_PANEL_FITTER";
  80         case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
  81                 return "PIPE_B_PANEL_FITTER";
  82         case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
  83                 return "PIPE_C_PANEL_FITTER";
  84         case POWER_DOMAIN_TRANSCODER_A:
  85                 return "TRANSCODER_A";
  86         case POWER_DOMAIN_TRANSCODER_B:
  87                 return "TRANSCODER_B";
  88         case POWER_DOMAIN_TRANSCODER_C:
  89                 return "TRANSCODER_C";
  90         case POWER_DOMAIN_TRANSCODER_EDP:
  91                 return "TRANSCODER_EDP";
  92         case POWER_DOMAIN_TRANSCODER_DSI_A:
  93                 return "TRANSCODER_DSI_A";
  94         case POWER_DOMAIN_TRANSCODER_DSI_C:
  95                 return "TRANSCODER_DSI_C";
  96         case POWER_DOMAIN_PORT_DDI_A_LANES:
  97                 return "PORT_DDI_A_LANES";
  98         case POWER_DOMAIN_PORT_DDI_B_LANES:
  99                 return "PORT_DDI_B_LANES";
 100         case POWER_DOMAIN_PORT_DDI_C_LANES:
 101                 return "PORT_DDI_C_LANES";
 102         case POWER_DOMAIN_PORT_DDI_D_LANES:
 103                 return "PORT_DDI_D_LANES";
 104         case POWER_DOMAIN_PORT_DDI_E_LANES:
 105                 return "PORT_DDI_E_LANES";
 106         case POWER_DOMAIN_PORT_DSI:
 107                 return "PORT_DSI";
 108         case POWER_DOMAIN_PORT_CRT:
 109                 return "PORT_CRT";
 110         case POWER_DOMAIN_PORT_OTHER:
 111                 return "PORT_OTHER";
 112         case POWER_DOMAIN_VGA:
 113                 return "VGA";
 114         case POWER_DOMAIN_AUDIO:
 115                 return "AUDIO";
 116         case POWER_DOMAIN_PLLS:
 117                 return "PLLS";
 118         case POWER_DOMAIN_AUX_A:
 119                 return "AUX_A";
 120         case POWER_DOMAIN_AUX_B:
 121                 return "AUX_B";
 122         case POWER_DOMAIN_AUX_C:
 123                 return "AUX_C";
 124         case POWER_DOMAIN_AUX_D:
 125                 return "AUX_D";
 126         case POWER_DOMAIN_GMBUS:
 127                 return "GMBUS";
 128         case POWER_DOMAIN_INIT:
 129                 return "INIT";
 130         case POWER_DOMAIN_MODESET:
 131                 return "MODESET";
 132         default:
 133                 MISSING_CASE(domain);
 134                 return "?";
 135         }
 136 }
 137
 138 static void intel_power_well_enable(struct drm_i915_private *dev_priv,
 139                                     struct i915_power_well *power_well)
 140 {
 141         DRM_DEBUG_KMS("enabling %s\n", power_well->name);
 142         power_well->ops->enable(dev_priv, power_well);
 143         power_well->hw_enabled = true;
 144 }
 145
 146 static void intel_power_well_disable(struct drm_i915_private *dev_priv,
 147                                      struct i915_power_well *power_well)
 148 {
 149         DRM_DEBUG_KMS("disabling %s\n", power_well->name);
 150         power_well->hw_enabled = false;
 151         power_well->ops->disable(dev_priv, power_well);
 152 }
 153
 154 /*
 155  * We should only use the power well if we explicitly asked the hardware to
 156  * enable it, so check if it's enabled and also check if we've requested it to
 157  * be enabled.
 158  */
 159 static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
 160                                    struct i915_power_well *power_well)
 161 {
 162         return I915_READ(HSW_PWR_WELL_DRIVER) ==
 163                      (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
 164 }
 165
 166 /**
 167  * __intel_display_power_is_enabled - unlocked check for a power domain
 168  * @dev_priv: i915 device instance
 169  * @domain: power domain to check
 170  *
 171  * This is the unlocked version of intel_display_power_is_enabled() and should
 172  * only be used from error capture and recovery code where deadlocks are
 173  * possible.
 174  *
 175  * Returns:
 176  * True when the power domain is enabled, false otherwise.
 177  */
 178 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
 179                                       enum intel_display_power_domain domain)
 180 {
 181         struct i915_power_domains *power_domains;
 182         struct i915_power_well *power_well;
 183         bool is_enabled;
 184         int i;
 185
 186         if (dev_priv->pm.suspended)
 187                 return false;
 188
 189         power_domains = &dev_priv->power_domains;
 190
 191         is_enabled = true;
 192
 193         for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
 194                 if (power_well->always_on)
 195                         continue;
 196
 197                 if (!power_well->hw_enabled) {
 198                         is_enabled = false;
 199                         break;
 200                 }
 201         }
 202
 203         return is_enabled;
 204 }
 205
 206 /**
 207  * intel_display_power_is_enabled - check for a power domain
 208  * @dev_priv: i915 device instance
 209  * @domain: power domain to check
 210  *
 211  * This function can be used to check the hw power domain state. It is mostly
 212  * used in hardware state readout functions. Everywhere else code should rely
 213  * upon explicit power domain reference counting to ensure that the hardware
 214  * block is powered up before accessing it.
 215  *
 216  * Callers must hold the relevant modesetting locks to ensure that concurrent
 217  * threads can't disable the power well while the caller tries to read a few
 218  * registers.
 219  *
 220  * Returns:
 221  * True when the power domain is enabled, false otherwise.
 222  */
 223 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
 224                                     enum intel_display_power_domain domain)
 225 {
 226         struct i915_power_domains *power_domains;
 227         bool ret;
 228
 229         power_domains = &dev_priv->power_domains;
 230
 231         mutex_lock(&power_domains->lock);
 232         ret = __intel_display_power_is_enabled(dev_priv, domain);
 233         mutex_unlock(&power_domains->lock);
 234
 235         return ret;
 236 }
 237
 238 /**
 239  * intel_display_set_init_power - set the initial power domain state
 240  * @dev_priv: i915 device instance
 241  * @enable: whether to enable or disable the initial power domain state
 242  *
 243  * For simplicity our driver load/unload and system suspend/resume code assumes
 244  * that all power domains are always enabled. This functions controls the state
 245  * of this little hack. While the initial power domain state is enabled runtime
 246  * pm is effectively disabled.
 247  */
 248 void intel_display_set_init_power(struct drm_i915_private *dev_priv,
 249                                   bool enable)
 250 {
 251         if (dev_priv->power_domains.init_power_on == enable)
 252                 return;
 253
 254         if (enable)
 255                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
 256         else
 257                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
 258
 259         dev_priv->power_domains.init_power_on = enable;
 260 }
 261
 262 /*
 263  * Starting with Haswell, we have a "Power Down Well" that can be turned off
 264  * when not needed anymore. We have 4 registers that can request the power well
 265  * to be enabled, and it will only be disabled if none of the registers is
 266  * requesting it to be enabled.
 267  */
 268 static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
 269 {
 270         struct drm_device *dev = dev_priv->dev;
 271
 272         /*
 273          * After we re-enable the power well, if we touch VGA register 0x3d5
 274          * we'll get unclaimed register interrupts. This stops after we write
 275          * anything to the VGA MSR register. The vgacon module uses this
 276          * register all the time, so if we unbind our driver and, as a
 277          * consequence, bind vgacon, we'll get stuck in an infinite loop at
 278          * console_unlock(). So make here we touch the VGA MSR register, making
 279          * sure vgacon can keep working normally without triggering interrupts
 280          * and error messages.
 281          */
 282         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
 283         outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
 284         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
 285
 286         if (IS_BROADWELL(dev))
 287                 gen8_irq_power_well_post_enable(dev_priv,
 288                                                 1 << PIPE_C | 1 << PIPE_B);
 289 }
 290
 291 static void hsw_power_well_pre_disable(struct drm_i915_private *dev_priv)
 292 {
 293         if (IS_BROADWELL(dev_priv))
 294                 gen8_irq_power_well_pre_disable(dev_priv,
 295                                                 1 << PIPE_C | 1 << PIPE_B);
 296 }
 297
 298 static void skl_power_well_post_enable(struct drm_i915_private *dev_priv,
 299                                        struct i915_power_well *power_well)
 300 {
 301         struct drm_device *dev = dev_priv->dev;
 302
 303         /*
 304          * After we re-enable the power well, if we touch VGA register 0x3d5
 305          * we'll get unclaimed register interrupts. This stops after we write
 306          * anything to the VGA MSR register. The vgacon module uses this
 307          * register all the time, so if we unbind our driver and, as a
 308          * consequence, bind vgacon, we'll get stuck in an infinite loop at
 309          * console_unlock(). So make here we touch the VGA MSR register, making
 310          * sure vgacon can keep working normally without triggering interrupts
 311          * and error messages.
 312          */
 313         if (power_well->data == SKL_DISP_PW_2) {
 314                 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
 315                 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
 316                 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
 317
 318                 gen8_irq_power_well_post_enable(dev_priv,
 319                                                 1 << PIPE_C | 1 << PIPE_B);
 320         }
 321 }
 322
 323 static void skl_power_well_pre_disable(struct drm_i915_private *dev_priv,
 324                                        struct i915_power_well *power_well)
 325 {
 326         if (power_well->data == SKL_DISP_PW_2)
 327                 gen8_irq_power_well_pre_disable(dev_priv,
 328                                                 1 << PIPE_C | 1 << PIPE_B);
 329 }
 330
 331 static void hsw_set_power_well(struct drm_i915_private *dev_priv,
 332                                struct i915_power_well *power_well, bool enable)
 333 {
 334         bool is_enabled, enable_requested;
 335         uint32_t tmp;
 336
 337         tmp = I915_READ(HSW_PWR_WELL_DRIVER);
 338         is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
 339         enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
 340
 341         if (enable) {
 342                 if (!enable_requested)
 343                         I915_WRITE(HSW_PWR_WELL_DRIVER,
 344                                    HSW_PWR_WELL_ENABLE_REQUEST);
 345
 346                 if (!is_enabled) {
 347                         DRM_DEBUG_KMS("Enabling power well\n");
 348                         if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
 349                                       HSW_PWR_WELL_STATE_ENABLED), 20))
 350                                 DRM_ERROR("Timeout enabling power well\n");
 351                         hsw_power_well_post_enable(dev_priv);
 352                 }
 353
 354         } else {
 355                 if (enable_requested) {
 356                         hsw_power_well_pre_disable(dev_priv);
 357                         I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
 358                         POSTING_READ(HSW_PWR_WELL_DRIVER);
 359                         DRM_DEBUG_KMS("Requesting to disable the power well\n");
 360                 }
 361         }
 362 }
 363
 364 #define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS (         \
 365         BIT(POWER_DOMAIN_TRANSCODER_A) |                \
 366         BIT(POWER_DOMAIN_PIPE_B) |                      \
 367         BIT(POWER_DOMAIN_TRANSCODER_B) |                \
 368         BIT(POWER_DOMAIN_PIPE_C) |                      \
 369         BIT(POWER_DOMAIN_TRANSCODER_C) |                \
 370         BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |         \
 371         BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |         \
 372         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |            \
 373         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |            \
 374         BIT(POWER_DOMAIN_PORT_DDI_D_LANES) |            \
 375         BIT(POWER_DOMAIN_PORT_DDI_E_LANES) |            \
 376         BIT(POWER_DOMAIN_AUX_B) |                       \
 377         BIT(POWER_DOMAIN_AUX_C) |                       \
 378         BIT(POWER_DOMAIN_AUX_D) |                       \
 379         BIT(POWER_DOMAIN_AUDIO) |                       \
 380         BIT(POWER_DOMAIN_VGA) |                         \
 381         BIT(POWER_DOMAIN_INIT))
 382 #define SKL_DISPLAY_DDI_A_E_POWER_DOMAINS (             \
 383         BIT(POWER_DOMAIN_PORT_DDI_A_LANES) |            \
 384         BIT(POWER_DOMAIN_PORT_DDI_E_LANES) |            \
 385         BIT(POWER_DOMAIN_INIT))
 386 #define SKL_DISPLAY_DDI_B_POWER_DOMAINS (               \
 387         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |            \
 388         BIT(POWER_DOMAIN_INIT))
 389 #define SKL_DISPLAY_DDI_C_POWER_DOMAINS (               \
 390         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |            \
 391         BIT(POWER_DOMAIN_INIT))
 392 #define SKL_DISPLAY_DDI_D_POWER_DOMAINS (               \
 393         BIT(POWER_DOMAIN_PORT_DDI_D_LANES) |            \
 394         BIT(POWER_DOMAIN_INIT))
 395 #define SKL_DISPLAY_DC_OFF_POWER_DOMAINS (              \
 396         SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS |         \
 397         BIT(POWER_DOMAIN_MODESET) |                     \
 398         BIT(POWER_DOMAIN_AUX_A) |                       \
 399         BIT(POWER_DOMAIN_INIT))
 400 #define SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS (           \
 401         (POWER_DOMAIN_MASK & ~(                         \
 402         SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS |         \
 403         SKL_DISPLAY_DC_OFF_POWER_DOMAINS)) |            \
 404         BIT(POWER_DOMAIN_INIT))
 405
 406 #define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS (         \
 407         BIT(POWER_DOMAIN_TRANSCODER_A) |                \
 408         BIT(POWER_DOMAIN_PIPE_B) |                      \
 409         BIT(POWER_DOMAIN_TRANSCODER_B) |                \
 410         BIT(POWER_DOMAIN_PIPE_C) |                      \
 411         BIT(POWER_DOMAIN_TRANSCODER_C) |                \
 412         BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |         \
 413         BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |         \
 414         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |            \
 415         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |            \
 416         BIT(POWER_DOMAIN_AUX_B) |                       \
 417         BIT(POWER_DOMAIN_AUX_C) |                       \
 418         BIT(POWER_DOMAIN_AUDIO) |                       \
 419         BIT(POWER_DOMAIN_VGA) |                         \
 420         BIT(POWER_DOMAIN_GMBUS) |                       \
 421         BIT(POWER_DOMAIN_INIT))
 422 #define BXT_DISPLAY_DC_OFF_POWER_DOMAINS (              \
 423         BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS |         \
 424         BIT(POWER_DOMAIN_MODESET) |                     \
 425         BIT(POWER_DOMAIN_AUX_A) |                       \
 426         BIT(POWER_DOMAIN_INIT))
 427 #define BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS (           \
 428         (POWER_DOMAIN_MASK & ~(                         \
 429         BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS)) |       \
 430         BIT(POWER_DOMAIN_INIT))
 431
 432 static void assert_can_enable_dc9(struct drm_i915_private *dev_priv)
 433 {
 434         WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9),
 435                   "DC9 already programmed to be enabled.\n");
 436         WARN_ONCE(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
 437                   "DC5 still not disabled to enable DC9.\n");
 438         WARN_ONCE(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on.\n");
 439         WARN_ONCE(intel_irqs_enabled(dev_priv),
 440                   "Interrupts not disabled yet.\n");
 441
 442          /*
 443           * TODO: check for the following to verify the conditions to enter DC9
 444           * state are satisfied:
 445           * 1] Check relevant display engine registers to verify if mode set
 446           * disable sequence was followed.
 447           * 2] Check if display uninitialize sequence is initialized.
 448           */
 449 }
 450
 451 static void assert_can_disable_dc9(struct drm_i915_private *dev_priv)
 452 {
 453         WARN_ONCE(intel_irqs_enabled(dev_priv),
 454                   "Interrupts not disabled yet.\n");
 455         WARN_ONCE(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
 456                   "DC5 still not disabled.\n");
 457
 458          /*
 459           * TODO: check for the following to verify DC9 state was indeed
 460           * entered before programming to disable it:
 461           * 1] Check relevant display engine registers to verify if mode
 462           *  set disable sequence was followed.
 463           * 2] Check if display uninitialize sequence is initialized.
 464           */
 465 }
 466
 467 static void gen9_write_dc_state(struct drm_i915_private *dev_priv,
 468                                 u32 state)
 469 {
 470         int rewrites = 0;
 471         int rereads = 0;
 472         u32 v;
 473
 474         I915_WRITE(DC_STATE_EN, state);
 475
 476         /* It has been observed that disabling the dc6 state sometimes
 477          * doesn't stick and dmc keeps returning old value. Make sure
 478          * the write really sticks enough times and also force rewrite until
 479          * we are confident that state is exactly what we want.
 480          */
 481         do  {
 482                 v = I915_READ(DC_STATE_EN);
 483
 484                 if (v != state) {
 485                         I915_WRITE(DC_STATE_EN, state);
 486                         rewrites++;
 487                         rereads = 0;
 488                 } else if (rereads++ > 5) {
 489                         break;
 490                 }
 491
 492         } while (rewrites < 100);
 493
 494         if (v != state)
 495                 DRM_ERROR("Writing dc state to 0x%x failed, now 0x%x\n",
 496                           state, v);
 497
 498         /* Most of the times we need one retry, avoid spam */
 499         if (rewrites > 1)
 500                 DRM_DEBUG_KMS("Rewrote dc state to 0x%x %d times\n",
 501                               state, rewrites);
 502 }
 503
 504 static void gen9_set_dc_state(struct drm_i915_private *dev_priv, uint32_t state)
 505 {
 506         uint32_t val;
 507         uint32_t mask;
 508
 509         mask = DC_STATE_EN_UPTO_DC5;
 510         if (IS_BROXTON(dev_priv))
 511                 mask |= DC_STATE_EN_DC9;
 512         else
 513                 mask |= DC_STATE_EN_UPTO_DC6;
 514
 515         if (WARN_ON_ONCE(state & ~dev_priv->csr.allowed_dc_mask))
 516                 state &= dev_priv->csr.allowed_dc_mask;
 517
 518         val = I915_READ(DC_STATE_EN);
 519         DRM_DEBUG_KMS("Setting DC state from %02x to %02x\n",
 520                       val & mask, state);
 521
 522         /* Check if DMC is ignoring our DC state requests */
 523         if ((val & mask) != dev_priv->csr.dc_state)
 524                 DRM_ERROR("DC state mismatch (0x%x -> 0x%x)\n",
 525                           dev_priv->csr.dc_state, val & mask);
 526
 527         val &= ~mask;
 528         val |= state;
 529
 530         gen9_write_dc_state(dev_priv, val);
 531
 532         dev_priv->csr.dc_state = val & mask;
 533 }
 534
 535 void bxt_enable_dc9(struct drm_i915_private *dev_priv)
 536 {
 537         assert_can_enable_dc9(dev_priv);
 538
 539         DRM_DEBUG_KMS("Enabling DC9\n");
 540
 541         gen9_set_dc_state(dev_priv, DC_STATE_EN_DC9);
 542 }
 543
 544 void bxt_disable_dc9(struct drm_i915_private *dev_priv)
 545 {
 546         assert_can_disable_dc9(dev_priv);
 547
 548         DRM_DEBUG_KMS("Disabling DC9\n");
 549
 550         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 551 }
 552
 553 static void assert_csr_loaded(struct drm_i915_private *dev_priv)
 554 {
 555         WARN_ONCE(!I915_READ(CSR_PROGRAM(0)),
 556                   "CSR program storage start is NULL\n");
 557         WARN_ONCE(!I915_READ(CSR_SSP_BASE), "CSR SSP Base Not fine\n");
 558         WARN_ONCE(!I915_READ(CSR_HTP_SKL), "CSR HTP Not fine\n");
 559 }
 560
 561 static void assert_can_enable_dc5(struct drm_i915_private *dev_priv)
 562 {
 563         bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv,
 564                                         SKL_DISP_PW_2);
 565
 566         WARN_ONCE(pg2_enabled, "PG2 not disabled to enable DC5.\n");
 567
 568         WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5),
 569                   "DC5 already programmed to be enabled.\n");
 570         assert_rpm_wakelock_held(dev_priv);
 571
 572         assert_csr_loaded(dev_priv);
 573 }
 574
 575 static void gen9_enable_dc5(struct drm_i915_private *dev_priv)
 576 {
 577         assert_can_enable_dc5(dev_priv);
 578
 579         DRM_DEBUG_KMS("Enabling DC5\n");
 580
 581         gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5);
 582 }
 583
 584 static void assert_can_enable_dc6(struct drm_i915_private *dev_priv)
 585 {
 586         WARN_ONCE(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
 587                   "Backlight is not disabled.\n");
 588         WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6),
 589                   "DC6 already programmed to be enabled.\n");
 590
 591         assert_csr_loaded(dev_priv);
 592 }
 593
 594 void skl_enable_dc6(struct drm_i915_private *dev_priv)
 595 {
 596         assert_can_enable_dc6(dev_priv);
 597
 598         DRM_DEBUG_KMS("Enabling DC6\n");
 599
 600         gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
 601
 602 }
 603
 604 void skl_disable_dc6(struct drm_i915_private *dev_priv)
 605 {
 606         DRM_DEBUG_KMS("Disabling DC6\n");
 607
 608         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 609 }
 610
 611 static void
 612 gen9_sanitize_power_well_requests(struct drm_i915_private *dev_priv,
 613                                   struct i915_power_well *power_well)
 614 {
 615         enum skl_disp_power_wells power_well_id = power_well->data;
 616         u32 val;
 617         u32 mask;
 618
 619         mask = SKL_POWER_WELL_REQ(power_well_id);
 620
 621         val = I915_READ(HSW_PWR_WELL_KVMR);
 622         if (WARN_ONCE(val & mask, "Clearing unexpected KVMR request for %s\n",
 623                       power_well->name))
 624                 I915_WRITE(HSW_PWR_WELL_KVMR, val & ~mask);
 625
 626         val = I915_READ(HSW_PWR_WELL_BIOS);
 627         val |= I915_READ(HSW_PWR_WELL_DEBUG);
 628
 629         if (!(val & mask))
 630                 return;
 631
 632         /*
 633          * DMC is known to force on the request bits for power well 1 on SKL
 634          * and BXT and the misc IO power well on SKL but we don't expect any
 635          * other request bits to be set, so WARN for those.
 636          */
 637         if (power_well_id == SKL_DISP_PW_1 ||
 638             (IS_SKYLAKE(dev_priv) && power_well_id == SKL_DISP_PW_MISC_IO))
 639                 DRM_DEBUG_DRIVER("Clearing auxiliary requests for %s forced on "
 640                                  "by DMC\n", power_well->name);
 641         else
 642                 WARN_ONCE(1, "Clearing unexpected auxiliary requests for %s\n",
 643                           power_well->name);
 644
 645         I915_WRITE(HSW_PWR_WELL_BIOS, val & ~mask);
 646         I915_WRITE(HSW_PWR_WELL_DEBUG, val & ~mask);
 647 }
 648
 649 static void skl_set_power_well(struct drm_i915_private *dev_priv,
 650                         struct i915_power_well *power_well, bool enable)
 651 {
 652         uint32_t tmp, fuse_status;
 653         uint32_t req_mask, state_mask;
 654         bool is_enabled, enable_requested, check_fuse_status = false;
 655
 656         tmp = I915_READ(HSW_PWR_WELL_DRIVER);
 657         fuse_status = I915_READ(SKL_FUSE_STATUS);
 658
 659         switch (power_well->data) {
 660         case SKL_DISP_PW_1:
 661                 if (wait_for((I915_READ(SKL_FUSE_STATUS) &
 662                         SKL_FUSE_PG0_DIST_STATUS), 1)) {
 663                         DRM_ERROR("PG0 not enabled\n");
 664                         return;
 665                 }
 666                 break;
 667         case SKL_DISP_PW_2:
 668                 if (!(fuse_status & SKL_FUSE_PG1_DIST_STATUS)) {
 669                         DRM_ERROR("PG1 in disabled state\n");
 670                         return;
 671                 }
 672                 break;
 673         case SKL_DISP_PW_DDI_A_E:
 674         case SKL_DISP_PW_DDI_B:
 675         case SKL_DISP_PW_DDI_C:
 676         case SKL_DISP_PW_DDI_D:
 677         case SKL_DISP_PW_MISC_IO:
 678                 break;
 679         default:
 680                 WARN(1, "Unknown power well %lu\n", power_well->data);
 681                 return;
 682         }
 683
 684         req_mask = SKL_POWER_WELL_REQ(power_well->data);
 685         enable_requested = tmp & req_mask;
 686         state_mask = SKL_POWER_WELL_STATE(power_well->data);
 687         is_enabled = tmp & state_mask;
 688
 689         if (!enable && enable_requested)
 690                 skl_power_well_pre_disable(dev_priv, power_well);
 691
 692         if (enable) {
 693                 if (!enable_requested) {
 694                         WARN((tmp & state_mask) &&
 695                                 !I915_READ(HSW_PWR_WELL_BIOS),
 696                                 "Invalid for power well status to be enabled, unless done by the BIOS, \
 697                                 when request is to disable!\n");
 698                         I915_WRITE(HSW_PWR_WELL_DRIVER, tmp | req_mask);
 699                 }
 700
 701                 if (!is_enabled) {
 702                         DRM_DEBUG_KMS("Enabling %s\n", power_well->name);
 703                         check_fuse_status = true;
 704                 }
 705         } else {
 706                 if (enable_requested) {
 707                         I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask);
 708                         POSTING_READ(HSW_PWR_WELL_DRIVER);
 709                         DRM_DEBUG_KMS("Disabling %s\n", power_well->name);
 710                 }
 711
 712                 if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
 713                         gen9_sanitize_power_well_requests(dev_priv, power_well);
 714         }
 715
 716         if (wait_for(!!(I915_READ(HSW_PWR_WELL_DRIVER) & state_mask) == enable,
 717                      1))
 718                 DRM_ERROR("%s %s timeout\n",
 719                           power_well->name, enable ? "enable" : "disable");
 720
 721         if (check_fuse_status) {
 722                 if (power_well->data == SKL_DISP_PW_1) {
 723                         if (wait_for((I915_READ(SKL_FUSE_STATUS) &
 724                                 SKL_FUSE_PG1_DIST_STATUS), 1))
 725                                 DRM_ERROR("PG1 distributing status timeout\n");
 726                 } else if (power_well->data == SKL_DISP_PW_2) {
 727                         if (wait_for((I915_READ(SKL_FUSE_STATUS) &
 728                                 SKL_FUSE_PG2_DIST_STATUS), 1))
 729                                 DRM_ERROR("PG2 distributing status timeout\n");
 730                 }
 731         }
 732
 733         if (enable && !is_enabled)
 734                 skl_power_well_post_enable(dev_priv, power_well);
 735 }
 736
 737 static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
 738                                    struct i915_power_well *power_well)
 739 {
 740         hsw_set_power_well(dev_priv, power_well, power_well->count > 0);
 741
 742         /*
 743          * We're taking over the BIOS, so clear any requests made by it since
 744          * the driver is in charge now.
 745          */
 746         if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
 747                 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
 748 }
 749
 750 static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
 751                                   struct i915_power_well *power_well)
 752 {
 753         hsw_set_power_well(dev_priv, power_well, true);
 754 }
 755
 756 static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
 757                                    struct i915_power_well *power_well)
 758 {
 759         hsw_set_power_well(dev_priv, power_well, false);
 760 }
 761
 762 static bool skl_power_well_enabled(struct drm_i915_private *dev_priv,
 763                                         struct i915_power_well *power_well)
 764 {
 765         uint32_t mask = SKL_POWER_WELL_REQ(power_well->data) |
 766                 SKL_POWER_WELL_STATE(power_well->data);
 767
 768         return (I915_READ(HSW_PWR_WELL_DRIVER) & mask) == mask;
 769 }
 770
 771 static void skl_power_well_sync_hw(struct drm_i915_private *dev_priv,
 772                                 struct i915_power_well *power_well)
 773 {
 774         skl_set_power_well(dev_priv, power_well, power_well->count > 0);
 775
 776         /* Clear any request made by BIOS as driver is taking over */
 777         I915_WRITE(HSW_PWR_WELL_BIOS, 0);
 778 }
 779
 780 static void skl_power_well_enable(struct drm_i915_private *dev_priv,
 781                                 struct i915_power_well *power_well)
 782 {
 783         skl_set_power_well(dev_priv, power_well, true);
 784 }
 785
 786 static void skl_power_well_disable(struct drm_i915_private *dev_priv,
 787                                 struct i915_power_well *power_well)
 788 {
 789         skl_set_power_well(dev_priv, power_well, false);
 790 }
 791
 792 static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv,
 793                                            struct i915_power_well *power_well)
 794 {
 795         return (I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0;
 796 }
 797
 798 static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
 799                                           struct i915_power_well *power_well)
 800 {
 801         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 802
 803         if (IS_BROXTON(dev_priv)) {
 804                 broxton_cdclk_verify_state(dev_priv);
 805                 broxton_ddi_phy_verify_state(dev_priv);
 806         }
 807 }
 808
 809 static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
 810                                            struct i915_power_well *power_well)
 811 {
 812         if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC6)
 813                 skl_enable_dc6(dev_priv);
 814         else if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5)
 815                 gen9_enable_dc5(dev_priv);
 816 }
 817
 818 static void gen9_dc_off_power_well_sync_hw(struct drm_i915_private *dev_priv,
 819                                            struct i915_power_well *power_well)
 820 {
 821         if (power_well->count > 0)
 822                 gen9_dc_off_power_well_enable(dev_priv, power_well);
 823         else
 824                 gen9_dc_off_power_well_disable(dev_priv, power_well);
 825 }
 826
 827 static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,
 828                                            struct i915_power_well *power_well)
 829 {
 830 }
 831
 832 static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,
 833                                              struct i915_power_well *power_well)
 834 {
 835         return true;
 836 }
 837
 838 static void vlv_set_power_well(struct drm_i915_private *dev_priv,
 839                                struct i915_power_well *power_well, bool enable)
 840 {
 841         enum punit_power_well power_well_id = power_well->data;
 842         u32 mask;
 843         u32 state;
 844         u32 ctrl;
 845
 846         mask = PUNIT_PWRGT_MASK(power_well_id);
 847         state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) :
 848                          PUNIT_PWRGT_PWR_GATE(power_well_id);
 849
 850         mutex_lock(&dev_priv->rps.hw_lock);
 851
 852 #define COND \
 853         ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)
 854
 855         if (COND)
 856                 goto out;
 857
 858         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL);
 859         ctrl &= ~mask;
 860         ctrl |= state;
 861         vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl);
 862
 863         if (wait_for(COND, 100))
 864                 DRM_ERROR("timeout setting power well state %08x (%08x)\n",
 865                           state,
 866                           vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL));
 867
 868 #undef COND
 869
 870 out:
 871         mutex_unlock(&dev_priv->rps.hw_lock);
 872 }
 873
 874 static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv,
 875                                    struct i915_power_well *power_well)
 876 {
 877         vlv_set_power_well(dev_priv, power_well, power_well->count > 0);
 878 }
 879
 880 static void vlv_power_well_enable(struct drm_i915_private *dev_priv,
 881                                   struct i915_power_well *power_well)
 882 {
 883         vlv_set_power_well(dev_priv, power_well, true);
 884 }
 885
 886 static void vlv_power_well_disable(struct drm_i915_private *dev_priv,
 887                                    struct i915_power_well *power_well)
 888 {
 889         vlv_set_power_well(dev_priv, power_well, false);
 890 }
 891
 892 static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
 893                                    struct i915_power_well *power_well)
 894 {
 895         int power_well_id = power_well->data;
 896         bool enabled = false;
 897         u32 mask;
 898         u32 state;
 899         u32 ctrl;
 900
 901         mask = PUNIT_PWRGT_MASK(power_well_id);
 902         ctrl = PUNIT_PWRGT_PWR_ON(power_well_id);
 903
 904         mutex_lock(&dev_priv->rps.hw_lock);
 905
 906         state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask;
 907         /*
 908          * We only ever set the power-on and power-gate states, anything
 909          * else is unexpected.
 910          */
 911         WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) &&
 912                 state != PUNIT_PWRGT_PWR_GATE(power_well_id));
 913         if (state == ctrl)
 914                 enabled = true;
 915
 916         /*
 917          * A transient state at this point would mean some unexpected party
 918          * is poking at the power controls too.
 919          */
 920         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask;
 921         WARN_ON(ctrl != state);
 922
 923         mutex_unlock(&dev_priv->rps.hw_lock);
 924
 925         return enabled;
 926 }
 927
 928 static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
 929 {
 930         I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
 931
 932         /*
 933          * Disable trickle feed and enable pnd deadline calculation
 934          */
 935         I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
 936         I915_WRITE(CBR1_VLV, 0);
 937 }
 938
 939 static void vlv_display_power_well_init(struct drm_i915_private *dev_priv)
 940 {
 941         enum pipe pipe;
 942
 943         /*
 944          * Enable the CRI clock source so we can get at the
 945          * display and the reference clock for VGA
 946          * hotplug / manual detection. Supposedly DSI also
 947          * needs the ref clock up and running.
 948          *
 949          * CHV DPLL B/C have some issues if VGA mode is enabled.
 950          */
 951         for_each_pipe(dev_priv->dev, pipe) {
 952                 u32 val = I915_READ(DPLL(pipe));
 953
 954                 val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
 955                 if (pipe != PIPE_A)
 956                         val |= DPLL_INTEGRATED_CRI_CLK_VLV;
 957
 958                 I915_WRITE(DPLL(pipe), val);
 959         }
 960
 961         vlv_init_display_clock_gating(dev_priv);
 962
 963         spin_lock_irq(&dev_priv->irq_lock);
 964         valleyview_enable_display_irqs(dev_priv);
 965         spin_unlock_irq(&dev_priv->irq_lock);
 966
 967         /*
 968          * During driver initialization/resume we can avoid restoring the
 969          * part of the HW/SW state that will be inited anyway explicitly.
 970          */
 971         if (dev_priv->power_domains.initializing)
 972                 return;
 973
 974         intel_hpd_init(dev_priv);
 975
 976         i915_redisable_vga_power_on(dev_priv->dev);
 977 }
 978
 979 static void vlv_display_power_well_deinit(struct drm_i915_private *dev_priv)
 980 {
 981         spin_lock_irq(&dev_priv->irq_lock);
 982         valleyview_disable_display_irqs(dev_priv);
 983         spin_unlock_irq(&dev_priv->irq_lock);
 984
 985         /* make sure we're done processing display irqs */
 986         synchronize_irq(dev_priv->dev->irq);
 987
 988         vlv_power_sequencer_reset(dev_priv);
 989 }
 990
 991 static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv,
 992                                           struct i915_power_well *power_well)
 993 {
 994         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
 995
 996         vlv_set_power_well(dev_priv, power_well, true);
 997
 998         vlv_display_power_well_init(dev_priv);
 999 }
1000
1001 static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv,
1002                                            struct i915_power_well *power_well)
1003 {
1004         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
1005
1006         vlv_display_power_well_deinit(dev_priv);
1007
1008         vlv_set_power_well(dev_priv, power_well, false);
1009 }
1010
1011 static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
1012                                            struct i915_power_well *power_well)
1013 {
1014         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
1015
1016         /* since ref/cri clock was enabled */
1017         udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
1018
1019         vlv_set_power_well(dev_priv, power_well, true);
1020
1021         /*
1022          * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1023          *  6.  De-assert cmn_reset/side_reset. Same as VLV X0.
1024          *   a. GUnit 0x2110 bit[0] set to 1 (def 0)
1025          *   b. The other bits such as sfr settings / modesel may all
1026          *      be set to 0.
1027          *
1028          * This should only be done on init and resume from S3 with
1029          * both PLLs disabled, or we risk losing DPIO and PLL
1030          * synchronization.
1031          */
1032         I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
1033 }
1034
1035 static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
1036                                             struct i915_power_well *power_well)
1037 {
1038         enum pipe pipe;
1039
1040         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
1041
1042         for_each_pipe(dev_priv, pipe)
1043                 assert_pll_disabled(dev_priv, pipe);
1044
1045         /* Assert common reset */
1046         I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST);
1047
1048         vlv_set_power_well(dev_priv, power_well, false);
1049 }
1050
1051 #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
1052
1053 static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv,
1054                                                  int power_well_id)
1055 {
1056         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1057         int i;
1058
1059         for (i = 0; i < power_domains->power_well_count; i++) {
1060                 struct i915_power_well *power_well;
1061
1062                 power_well = &power_domains->power_wells[i];
1063                 if (power_well->data == power_well_id)
1064                         return power_well;
1065         }
1066
1067         return NULL;
1068 }
1069
1070 #define BITS_SET(val, bits) (((val) & (bits)) == (bits))
1071
1072 static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
1073 {
1074         struct i915_power_well *cmn_bc =
1075                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
1076         struct i915_power_well *cmn_d =
1077                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D);
1078         u32 phy_control = dev_priv->chv_phy_control;
1079         u32 phy_status = 0;
1080         u32 phy_status_mask = 0xffffffff;
1081         u32 tmp;
1082
1083         /*
1084          * The BIOS can leave the PHY is some weird state
1085          * where it doesn't fully power down some parts.
1086          * Disable the asserts until the PHY has been fully
1087          * reset (ie. the power well has been disabled at
1088          * least once).
1089          */
1090         if (!dev_priv->chv_phy_assert[DPIO_PHY0])
1091                 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0) |
1092                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0) |
1093                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1) |
1094                                      PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1) |
1095                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0) |
1096                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1));
1097
1098         if (!dev_priv->chv_phy_assert[DPIO_PHY1])
1099                 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0) |
1100                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0) |
1101                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1));
1102
1103         if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) {
1104                 phy_status |= PHY_POWERGOOD(DPIO_PHY0);
1105
1106                 /* this assumes override is only used to enable lanes */
1107                 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0)) == 0)
1108                         phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0);
1109
1110                 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1)) == 0)
1111                         phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1);
1112
1113                 /* CL1 is on whenever anything is on in either channel */
1114                 if (BITS_SET(phy_control,
1115                              PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0) |
1116                              PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)))
1117                         phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0);
1118
1119                 /*
1120                  * The DPLLB check accounts for the pipe B + port A usage
1121                  * with CL2 powered up but all the lanes in the second channel
1122                  * powered down.
1123                  */
1124                 if (BITS_SET(phy_control,
1125                              PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)) &&
1126                     (I915_READ(DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0)
1127                         phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1);
1128
1129                 if (BITS_SET(phy_control,
1130                              PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH0)))
1131                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0);
1132                 if (BITS_SET(phy_control,
1133                              PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH0)))
1134                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1);
1135
1136                 if (BITS_SET(phy_control,
1137                              PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH1)))
1138                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0);
1139                 if (BITS_SET(phy_control,
1140                              PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH1)))
1141                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1);
1142         }
1143
1144         if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) {
1145                 phy_status |= PHY_POWERGOOD(DPIO_PHY1);
1146
1147                 /* this assumes override is only used to enable lanes */
1148                 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0)) == 0)
1149                         phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0);
1150
1151                 if (BITS_SET(phy_control,
1152                              PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0)))
1153                         phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0);
1154
1155                 if (BITS_SET(phy_control,
1156                              PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY1, DPIO_CH0)))
1157                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0);
1158                 if (BITS_SET(phy_control,
1159                              PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY1, DPIO_CH0)))
1160                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1);
1161         }
1162
1163         phy_status &= phy_status_mask;
1164
1165         /*
1166          * The PHY may be busy with some initial calibration and whatnot,
1167          * so the power state can take a while to actually change.
1168          */
1169         if (wait_for((tmp = I915_READ(DISPLAY_PHY_STATUS) & phy_status_mask) == phy_status, 10))
1170                 WARN(phy_status != tmp,
1171                      "Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n",
1172                      tmp, phy_status, dev_priv->chv_phy_control);
1173 }
1174
1175 #undef BITS_SET
1176
1177 static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
1178                                            struct i915_power_well *power_well)
1179 {
1180         enum dpio_phy phy;
1181         enum pipe pipe;
1182         uint32_t tmp;
1183
1184         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
1185                      power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
1186
1187         if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
1188                 pipe = PIPE_A;
1189                 phy = DPIO_PHY0;
1190         } else {
1191                 pipe = PIPE_C;
1192                 phy = DPIO_PHY1;
1193         }
1194
1195         /* since ref/cri clock was enabled */
1196         udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
1197         vlv_set_power_well(dev_priv, power_well, true);
1198
1199         /* Poll for phypwrgood signal */
1200         if (wait_for(I915_READ(DISPLAY_PHY_STATUS) & PHY_POWERGOOD(phy), 1))
1201                 DRM_ERROR("Display PHY %d is not power up\n", phy);
1202
1203         mutex_lock(&dev_priv->sb_lock);
1204
1205         /* Enable dynamic power down */
1206         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW28);
1207         tmp |= DPIO_DYNPWRDOWNEN_CH0 | DPIO_CL1POWERDOWNEN |
1208                 DPIO_SUS_CLK_CONFIG_GATE_CLKREQ;
1209         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW28, tmp);
1210
1211         if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
1212                 tmp = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW6_CH1);
1213                 tmp |= DPIO_DYNPWRDOWNEN_CH1;
1214                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW6_CH1, tmp);
1215         } else {
1216                 /*
1217                  * Force the non-existing CL2 off. BXT does this
1218                  * too, so maybe it saves some power even though
1219                  * CL2 doesn't exist?
1220                  */
1221                 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
1222                 tmp |= DPIO_CL2_LDOFUSE_PWRENB;
1223                 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, tmp);
1224         }
1225
1226         mutex_unlock(&dev_priv->sb_lock);
1227
1228         dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy);
1229         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1230
1231         DRM_DEBUG_KMS("Enabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
1232                       phy, dev_priv->chv_phy_control);
1233
1234         assert_chv_phy_status(dev_priv);
1235 }
1236
1237 static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
1238                                             struct i915_power_well *power_well)
1239 {
1240         enum dpio_phy phy;
1241
1242         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
1243                      power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
1244
1245         if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
1246                 phy = DPIO_PHY0;
1247                 assert_pll_disabled(dev_priv, PIPE_A);
1248                 assert_pll_disabled(dev_priv, PIPE_B);
1249         } else {
1250                 phy = DPIO_PHY1;
1251                 assert_pll_disabled(dev_priv, PIPE_C);
1252         }
1253
1254         dev_priv->chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy);
1255         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1256
1257         vlv_set_power_well(dev_priv, power_well, false);
1258
1259         DRM_DEBUG_KMS("Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
1260                       phy, dev_priv->chv_phy_control);
1261
1262         /* PHY is fully reset now, so we can enable the PHY state asserts */
1263         dev_priv->chv_phy_assert[phy] = true;
1264
1265         assert_chv_phy_status(dev_priv);
1266 }
1267
1268 static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1269                                      enum dpio_channel ch, bool override, unsigned int mask)
1270 {
1271         enum pipe pipe = phy == DPIO_PHY0 ? PIPE_A : PIPE_C;
1272         u32 reg, val, expected, actual;
1273
1274         /*
1275          * The BIOS can leave the PHY is some weird state
1276          * where it doesn't fully power down some parts.
1277          * Disable the asserts until the PHY has been fully
1278          * reset (ie. the power well has been disabled at
1279          * least once).
1280          */
1281         if (!dev_priv->chv_phy_assert[phy])
1282                 return;
1283
1284         if (ch == DPIO_CH0)
1285                 reg = _CHV_CMN_DW0_CH0;
1286         else
1287                 reg = _CHV_CMN_DW6_CH1;
1288
1289         mutex_lock(&dev_priv->sb_lock);
1290         val = vlv_dpio_read(dev_priv, pipe, reg);
1291         mutex_unlock(&dev_priv->sb_lock);
1292
1293         /*
1294          * This assumes !override is only used when the port is disabled.
1295          * All lanes should power down even without the override when
1296          * the port is disabled.
1297          */
1298         if (!override || mask == 0xf) {
1299                 expected = DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN;
1300                 /*
1301                  * If CH1 common lane is not active anymore
1302                  * (eg. for pipe B DPLL) the entire channel will
1303                  * shut down, which causes the common lane registers
1304                  * to read as 0. That means we can't actually check
1305                  * the lane power down status bits, but as the entire
1306                  * register reads as 0 it's a good indication that the
1307                  * channel is indeed entirely powered down.
1308                  */
1309                 if (ch == DPIO_CH1 && val == 0)
1310                         expected = 0;
1311         } else if (mask != 0x0) {
1312                 expected = DPIO_ANYDL_POWERDOWN;
1313         } else {
1314                 expected = 0;
1315         }
1316
1317         if (ch == DPIO_CH0)
1318                 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH0;
1319         else
1320                 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH1;
1321         actual &= DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN;
1322
1323         WARN(actual != expected,
1324              "Unexpected DPIO lane power down: all %d, any %d. Expected: all %d, any %d. (0x%x = 0x%08x)\n",
1325              !!(actual & DPIO_ALLDL_POWERDOWN), !!(actual & DPIO_ANYDL_POWERDOWN),
1326              !!(expected & DPIO_ALLDL_POWERDOWN), !!(expected & DPIO_ANYDL_POWERDOWN),
1327              reg, val);
1328 }
1329
1330 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1331                           enum dpio_channel ch, bool override)
1332 {
1333         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1334         bool was_override;
1335
1336         mutex_lock(&power_domains->lock);
1337
1338         was_override = dev_priv->chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1339
1340         if (override == was_override)
1341                 goto out;
1342
1343         if (override)
1344                 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1345         else
1346                 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1347
1348         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1349
1350         DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d (DPIO_PHY_CONTROL=0x%08x)\n",
1351                       phy, ch, dev_priv->chv_phy_control);
1352
1353         assert_chv_phy_status(dev_priv);
1354
1355 out:
1356         mutex_unlock(&power_domains->lock);
1357
1358         return was_override;
1359 }
1360
1361 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1362                              bool override, unsigned int mask)
1363 {
1364         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1365         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1366         enum dpio_phy phy = vlv_dport_to_phy(enc_to_dig_port(&encoder->base));
1367         enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
1368
1369         mutex_lock(&power_domains->lock);
1370
1371         dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch);
1372         dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch);
1373
1374         if (override)
1375                 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1376         else
1377                 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1378
1379         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1380
1381         DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d lanes 0x%x (PHY_CONTROL=0x%08x)\n",
1382                       phy, ch, mask, dev_priv->chv_phy_control);
1383
1384         assert_chv_phy_status(dev_priv);
1385
1386         assert_chv_phy_powergate(dev_priv, phy, ch, override, mask);
1387
1388         mutex_unlock(&power_domains->lock);
1389 }
1390
1391 static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv,
1392                                         struct i915_power_well *power_well)
1393 {
1394         enum pipe pipe = power_well->data;
1395         bool enabled;
1396         u32 state, ctrl;
1397
1398         mutex_lock(&dev_priv->rps.hw_lock);
1399
1400         state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe);
1401         /*
1402          * We only ever set the power-on and power-gate states, anything
1403          * else is unexpected.
1404          */
1405         WARN_ON(state != DP_SSS_PWR_ON(pipe) && state != DP_SSS_PWR_GATE(pipe));
1406         enabled = state == DP_SSS_PWR_ON(pipe);
1407
1408         /*
1409          * A transient state at this point would mean some unexpected party
1410          * is poking at the power controls too.
1411          */
1412         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe);
1413         WARN_ON(ctrl << 16 != state);
1414
1415         mutex_unlock(&dev_priv->rps.hw_lock);
1416
1417         return enabled;
1418 }
1419
1420 static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv,
1421                                     struct i915_power_well *power_well,
1422                                     bool enable)
1423 {
1424         enum pipe pipe = power_well->data;
1425         u32 state;
1426         u32 ctrl;
1427
1428         state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe);
1429
1430         mutex_lock(&dev_priv->rps.hw_lock);
1431
1432 #define COND \
1433         ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state)
1434
1435         if (COND)
1436                 goto out;
1437
1438         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
1439         ctrl &= ~DP_SSC_MASK(pipe);
1440         ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe);
1441         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl);
1442
1443         if (wait_for(COND, 100))
1444                 DRM_ERROR("timeout setting power well state %08x (%08x)\n",
1445                           state,
1446                           vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ));
1447
1448 #undef COND
1449
1450 out:
1451         mutex_unlock(&dev_priv->rps.hw_lock);
1452 }
1453
1454 static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv,
1455                                         struct i915_power_well *power_well)
1456 {
1457         WARN_ON_ONCE(power_well->data != PIPE_A);
1458
1459         chv_set_pipe_power_well(dev_priv, power_well, power_well->count > 0);
1460 }
1461
1462 static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv,
1463                                        struct i915_power_well *power_well)
1464 {
1465         WARN_ON_ONCE(power_well->data != PIPE_A);
1466
1467         chv_set_pipe_power_well(dev_priv, power_well, true);
1468
1469         vlv_display_power_well_init(dev_priv);
1470 }
1471
1472 static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv,
1473                                         struct i915_power_well *power_well)
1474 {
1475         WARN_ON_ONCE(power_well->data != PIPE_A);
1476
1477         vlv_display_power_well_deinit(dev_priv);
1478
1479         chv_set_pipe_power_well(dev_priv, power_well, false);
1480 }
1481
1482 static void
1483 __intel_display_power_get_domain(struct drm_i915_private *dev_priv,
1484                                  enum intel_display_power_domain domain)
1485 {
1486         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1487         struct i915_power_well *power_well;
1488         int i;
1489
1490         for_each_power_well(i, power_well, BIT(domain), power_domains) {
1491                 if (!power_well->count++)
1492                         intel_power_well_enable(dev_priv, power_well);
1493         }
1494
1495         power_domains->domain_use_count[domain]++;
1496 }
1497
1498 /**
1499  * intel_display_power_get - grab a power domain reference
1500  * @dev_priv: i915 device instance
1501  * @domain: power domain to reference
1502  *
1503  * This function grabs a power domain reference for @domain and ensures that the
1504  * power domain and all its parents are powered up. Therefore users should only
1505  * grab a reference to the innermost power domain they need.
1506  *
1507  * Any power domain reference obtained by this function must have a symmetric
1508  * call to intel_display_power_put() to release the reference again.
1509  */
1510 void intel_display_power_get(struct drm_i915_private *dev_priv,
1511                              enum intel_display_power_domain domain)
1512 {
1513         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1514
1515         intel_runtime_pm_get(dev_priv);
1516
1517         mutex_lock(&power_domains->lock);
1518
1519         __intel_display_power_get_domain(dev_priv, domain);
1520
1521         mutex_unlock(&power_domains->lock);
1522 }
1523
1524 /**
1525  * intel_display_power_get_if_enabled - grab a reference for an enabled display power domain
1526  * @dev_priv: i915 device instance
1527  * @domain: power domain to reference
1528  *
1529  * This function grabs a power domain reference for @domain and ensures that the
1530  * power domain and all its parents are powered up. Therefore users should only
1531  * grab a reference to the innermost power domain they need.
1532  *
1533  * Any power domain reference obtained by this function must have a symmetric
1534  * call to intel_display_power_put() to release the reference again.
1535  */
1536 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
1537                                         enum intel_display_power_domain domain)
1538 {
1539         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1540         bool is_enabled;
1541
1542         if (!intel_runtime_pm_get_if_in_use(dev_priv))
1543                 return false;
1544
1545         mutex_lock(&power_domains->lock);
1546
1547         if (__intel_display_power_is_enabled(dev_priv, domain)) {
1548                 __intel_display_power_get_domain(dev_priv, domain);
1549                 is_enabled = true;
1550         } else {
1551                 is_enabled = false;
1552         }
1553
1554         mutex_unlock(&power_domains->lock);
1555
1556         if (!is_enabled)
1557                 intel_runtime_pm_put(dev_priv);
1558
1559         return is_enabled;
1560 }
1561
1562 /**
1563  * intel_display_power_put - release a power domain reference
1564  * @dev_priv: i915 device instance
1565  * @domain: power domain to reference
1566  *
1567  * This function drops the power domain reference obtained by
1568  * intel_display_power_get() and might power down the corresponding hardware
1569  * block right away if this is the last reference.
1570  */
1571 void intel_display_power_put(struct drm_i915_private *dev_priv,
1572                              enum intel_display_power_domain domain)
1573 {
1574         struct i915_power_domains *power_domains;
1575         struct i915_power_well *power_well;
1576         int i;
1577
1578         power_domains = &dev_priv->power_domains;
1579
1580         mutex_lock(&power_domains->lock);
1581
1582         WARN(!power_domains->domain_use_count[domain],
1583              "Use count on domain %s is already zero\n",
1584              intel_display_power_domain_str(domain));
1585         power_domains->domain_use_count[domain]--;
1586
1587         for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
1588                 WARN(!power_well->count,
1589                      "Use count on power well %s is already zero",
1590                      power_well->name);
1591
1592                 if (!--power_well->count)
1593                         intel_power_well_disable(dev_priv, power_well);
1594         }
1595
1596         mutex_unlock(&power_domains->lock);
1597
1598         intel_runtime_pm_put(dev_priv);
1599 }
1600
1601 #define HSW_ALWAYS_ON_POWER_DOMAINS (                   \
1602         BIT(POWER_DOMAIN_PIPE_A) |                      \
1603         BIT(POWER_DOMAIN_TRANSCODER_EDP) |              \
1604         BIT(POWER_DOMAIN_PORT_DDI_A_LANES) |            \
1605         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |            \
1606         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |            \
1607         BIT(POWER_DOMAIN_PORT_DDI_D_LANES) |            \
1608         BIT(POWER_DOMAIN_PORT_CRT) |                    \
1609         BIT(POWER_DOMAIN_PLLS) |                        \
1610         BIT(POWER_DOMAIN_AUX_A) |                       \
1611         BIT(POWER_DOMAIN_AUX_B) |                       \
1612         BIT(POWER_DOMAIN_AUX_C) |                       \
1613         BIT(POWER_DOMAIN_AUX_D) |                       \
1614         BIT(POWER_DOMAIN_GMBUS) |                       \
1615         BIT(POWER_DOMAIN_INIT))
1616 #define HSW_DISPLAY_POWER_DOMAINS (                             \
1617         (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) |    \
1618         BIT(POWER_DOMAIN_INIT))
1619
1620 #define BDW_ALWAYS_ON_POWER_DOMAINS (                   \
1621         HSW_ALWAYS_ON_POWER_DOMAINS |                   \
1622         BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER))
1623 #define BDW_DISPLAY_POWER_DOMAINS (                             \
1624         (POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) |    \
1625         BIT(POWER_DOMAIN_INIT))
1626
1627 #define VLV_ALWAYS_ON_POWER_DOMAINS     BIT(POWER_DOMAIN_INIT)
1628 #define VLV_DISPLAY_POWER_DOMAINS       POWER_DOMAIN_MASK
1629
1630 #define VLV_DPIO_CMN_BC_POWER_DOMAINS (         \
1631         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |    \
1632         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |    \
1633         BIT(POWER_DOMAIN_PORT_CRT) |            \
1634         BIT(POWER_DOMAIN_AUX_B) |               \
1635         BIT(POWER_DOMAIN_AUX_C) |               \
1636         BIT(POWER_DOMAIN_INIT))
1637
1638 #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS (  \
1639         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |    \
1640         BIT(POWER_DOMAIN_AUX_B) |               \
1641         BIT(POWER_DOMAIN_INIT))
1642
1643 #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS (  \
1644         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |    \
1645         BIT(POWER_DOMAIN_AUX_B) |               \
1646         BIT(POWER_DOMAIN_INIT))
1647
1648 #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS (  \
1649         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |    \
1650         BIT(POWER_DOMAIN_AUX_C) |               \
1651         BIT(POWER_DOMAIN_INIT))
1652
1653 #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS (  \
1654         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |    \
1655         BIT(POWER_DOMAIN_AUX_C) |               \
1656         BIT(POWER_DOMAIN_INIT))
1657
1658 #define CHV_DPIO_CMN_BC_POWER_DOMAINS (         \
1659         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |    \
1660         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |    \
1661         BIT(POWER_DOMAIN_AUX_B) |               \
1662         BIT(POWER_DOMAIN_AUX_C) |               \
1663         BIT(POWER_DOMAIN_INIT))
1664
1665 #define CHV_DPIO_CMN_D_POWER_DOMAINS (          \
1666         BIT(POWER_DOMAIN_PORT_DDI_D_LANES) |    \
1667         BIT(POWER_DOMAIN_AUX_D) |               \
1668         BIT(POWER_DOMAIN_INIT))
1669
1670 static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
1671         .sync_hw = i9xx_always_on_power_well_noop,
1672         .enable = i9xx_always_on_power_well_noop,
1673         .disable = i9xx_always_on_power_well_noop,
1674         .is_enabled = i9xx_always_on_power_well_enabled,
1675 };
1676
1677 static const struct i915_power_well_ops chv_pipe_power_well_ops = {
1678         .sync_hw = chv_pipe_power_well_sync_hw,
1679         .enable = chv_pipe_power_well_enable,
1680         .disable = chv_pipe_power_well_disable,
1681         .is_enabled = chv_pipe_power_well_enabled,
1682 };
1683
1684 static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = {
1685         .sync_hw = vlv_power_well_sync_hw,
1686         .enable = chv_dpio_cmn_power_well_enable,
1687         .disable = chv_dpio_cmn_power_well_disable,
1688         .is_enabled = vlv_power_well_enabled,
1689 };
1690
1691 static struct i915_power_well i9xx_always_on_power_well[] = {
1692         {
1693                 .name = "always-on",
1694                 .always_on = 1,
1695                 .domains = POWER_DOMAIN_MASK,
1696                 .ops = &i9xx_always_on_power_well_ops,
1697         },
1698 };
1699
1700 static const struct i915_power_well_ops hsw_power_well_ops = {
1701         .sync_hw = hsw_power_well_sync_hw,
1702         .enable = hsw_power_well_enable,
1703         .disable = hsw_power_well_disable,
1704         .is_enabled = hsw_power_well_enabled,
1705 };
1706
1707 static const struct i915_power_well_ops skl_power_well_ops = {
1708         .sync_hw = skl_power_well_sync_hw,
1709         .enable = skl_power_well_enable,
1710         .disable = skl_power_well_disable,
1711         .is_enabled = skl_power_well_enabled,
1712 };
1713
1714 static const struct i915_power_well_ops gen9_dc_off_power_well_ops = {
1715         .sync_hw = gen9_dc_off_power_well_sync_hw,
1716         .enable = gen9_dc_off_power_well_enable,
1717         .disable = gen9_dc_off_power_well_disable,
1718         .is_enabled = gen9_dc_off_power_well_enabled,
1719 };
1720
1721 static struct i915_power_well hsw_power_wells[] = {
1722         {
1723                 .name = "always-on",
1724                 .always_on = 1,
1725                 .domains = HSW_ALWAYS_ON_POWER_DOMAINS,
1726                 .ops = &i9xx_always_on_power_well_ops,
1727         },
1728         {
1729                 .name = "display",
1730                 .domains = HSW_DISPLAY_POWER_DOMAINS,
1731                 .ops = &hsw_power_well_ops,
1732         },
1733 };
1734
1735 static struct i915_power_well bdw_power_wells[] = {
1736         {
1737                 .name = "always-on",
1738                 .always_on = 1,
1739                 .domains = BDW_ALWAYS_ON_POWER_DOMAINS,
1740                 .ops = &i9xx_always_on_power_well_ops,
1741         },
1742         {
1743                 .name = "display",
1744                 .domains = BDW_DISPLAY_POWER_DOMAINS,
1745                 .ops = &hsw_power_well_ops,
1746         },
1747 };
1748
1749 static const struct i915_power_well_ops vlv_display_power_well_ops = {
1750         .sync_hw = vlv_power_well_sync_hw,
1751         .enable = vlv_display_power_well_enable,
1752         .disable = vlv_display_power_well_disable,
1753         .is_enabled = vlv_power_well_enabled,
1754 };
1755
1756 static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = {
1757         .sync_hw = vlv_power_well_sync_hw,
1758         .enable = vlv_dpio_cmn_power_well_enable,
1759         .disable = vlv_dpio_cmn_power_well_disable,
1760         .is_enabled = vlv_power_well_enabled,
1761 };
1762
1763 static const struct i915_power_well_ops vlv_dpio_power_well_ops = {
1764         .sync_hw = vlv_power_well_sync_hw,
1765         .enable = vlv_power_well_enable,
1766         .disable = vlv_power_well_disable,
1767         .is_enabled = vlv_power_well_enabled,
1768 };
1769
1770 static struct i915_power_well vlv_power_wells[] = {
1771         {
1772                 .name = "always-on",
1773                 .always_on = 1,
1774                 .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
1775                 .ops = &i9xx_always_on_power_well_ops,
1776                 .data = PUNIT_POWER_WELL_ALWAYS_ON,
1777         },
1778         {
1779                 .name = "display",
1780                 .domains = VLV_DISPLAY_POWER_DOMAINS,
1781                 .data = PUNIT_POWER_WELL_DISP2D,
1782                 .ops = &vlv_display_power_well_ops,
1783         },
1784         {
1785                 .name = "dpio-tx-b-01",
1786                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1787                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1788                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1789                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1790                 .ops = &vlv_dpio_power_well_ops,
1791                 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
1792         },
1793         {
1794                 .name = "dpio-tx-b-23",
1795                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1796                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1797                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1798                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1799                 .ops = &vlv_dpio_power_well_ops,
1800                 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
1801         },
1802         {
1803                 .name = "dpio-tx-c-01",
1804                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1805                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1806                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1807                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1808                 .ops = &vlv_dpio_power_well_ops,
1809                 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
1810         },
1811         {
1812                 .name = "dpio-tx-c-23",
1813                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1814                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1815                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1816                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1817                 .ops = &vlv_dpio_power_well_ops,
1818                 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
1819         },
1820         {
1821                 .name = "dpio-common",
1822                 .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,
1823                 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
1824                 .ops = &vlv_dpio_cmn_power_well_ops,
1825         },
1826 };
1827
1828 static struct i915_power_well chv_power_wells[] = {
1829         {
1830                 .name = "always-on",
1831                 .always_on = 1,
1832                 .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
1833                 .ops = &i9xx_always_on_power_well_ops,
1834         },
1835         {
1836                 .name = "display",
1837                 /*
1838                  * Pipe A power well is the new disp2d well. Pipe B and C
1839                  * power wells don't actually exist. Pipe A power well is
1840                  * required for any pipe to work.
1841                  */
1842                 .domains = VLV_DISPLAY_POWER_DOMAINS,
1843                 .data = PIPE_A,
1844                 .ops = &chv_pipe_power_well_ops,
1845         },
1846         {
1847                 .name = "dpio-common-bc",
1848                 .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS,
1849                 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
1850                 .ops = &chv_dpio_cmn_power_well_ops,
1851         },
1852         {
1853                 .name = "dpio-common-d",
1854                 .domains = CHV_DPIO_CMN_D_POWER_DOMAINS,
1855                 .data = PUNIT_POWER_WELL_DPIO_CMN_D,
1856                 .ops = &chv_dpio_cmn_power_well_ops,
1857         },
1858 };
1859
1860 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
1861                                     int power_well_id)
1862 {
1863         struct i915_power_well *power_well;
1864         bool ret;
1865
1866         power_well = lookup_power_well(dev_priv, power_well_id);
1867         ret = power_well->ops->is_enabled(dev_priv, power_well);
1868
1869         return ret;
1870 }
1871
1872 static struct i915_power_well skl_power_wells[] = {
1873         {
1874                 .name = "always-on",
1875                 .always_on = 1,
1876                 .domains = SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS,
1877                 .ops = &i9xx_always_on_power_well_ops,
1878                 .data = SKL_DISP_PW_ALWAYS_ON,
1879         },
1880         {
1881                 .name = "power well 1",
1882                 /* Handled by the DMC firmware */
1883                 .domains = 0,
1884                 .ops = &skl_power_well_ops,
1885                 .data = SKL_DISP_PW_1,
1886         },
1887         {
1888                 .name = "MISC IO power well",
1889                 /* Handled by the DMC firmware */
1890                 .domains = 0,
1891                 .ops = &skl_power_well_ops,
1892                 .data = SKL_DISP_PW_MISC_IO,
1893         },
1894         {
1895                 .name = "DC off",
1896                 .domains = SKL_DISPLAY_DC_OFF_POWER_DOMAINS,
1897                 .ops = &gen9_dc_off_power_well_ops,
1898                 .data = SKL_DISP_PW_DC_OFF,
1899         },
1900         {
1901                 .name = "power well 2",
1902                 .domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS,
1903                 .ops = &skl_power_well_ops,
1904                 .data = SKL_DISP_PW_2,
1905         },
1906         {
1907                 .name = "DDI A/E power well",
1908                 .domains = SKL_DISPLAY_DDI_A_E_POWER_DOMAINS,
1909                 .ops = &skl_power_well_ops,
1910                 .data = SKL_DISP_PW_DDI_A_E,
1911         },
1912         {
1913                 .name = "DDI B power well",
1914                 .domains = SKL_DISPLAY_DDI_B_POWER_DOMAINS,
1915                 .ops = &skl_power_well_ops,
1916                 .data = SKL_DISP_PW_DDI_B,
1917         },
1918         {
1919                 .name = "DDI C power well",
1920                 .domains = SKL_DISPLAY_DDI_C_POWER_DOMAINS,
1921                 .ops = &skl_power_well_ops,
1922                 .data = SKL_DISP_PW_DDI_C,
1923         },
1924         {
1925                 .name = "DDI D power well",
1926                 .domains = SKL_DISPLAY_DDI_D_POWER_DOMAINS,
1927                 .ops = &skl_power_well_ops,
1928                 .data = SKL_DISP_PW_DDI_D,
1929         },
1930 };
1931
1932 static struct i915_power_well bxt_power_wells[] = {
1933         {
1934                 .name = "always-on",
1935                 .always_on = 1,
1936                 .domains = BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS,
1937                 .ops = &i9xx_always_on_power_well_ops,
1938         },
1939         {
1940                 .name = "power well 1",
1941                 .domains = 0,
1942                 .ops = &skl_power_well_ops,
1943                 .data = SKL_DISP_PW_1,
1944         },
1945         {
1946                 .name = "DC off",
1947                 .domains = BXT_DISPLAY_DC_OFF_POWER_DOMAINS,
1948                 .ops = &gen9_dc_off_power_well_ops,
1949                 .data = SKL_DISP_PW_DC_OFF,
1950         },
1951         {
1952                 .name = "power well 2",
1953                 .domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS,
1954                 .ops = &skl_power_well_ops,
1955                 .data = SKL_DISP_PW_2,
1956         },
1957 };
1958
1959 static int
1960 sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv,
1961                                    int disable_power_well)
1962 {
1963         if (disable_power_well >= 0)
1964                 return !!disable_power_well;
1965
1966         if (IS_BROXTON(dev_priv)) {
1967                 DRM_DEBUG_KMS("Disabling display power well support\n");
1968                 return 0;
1969         }
1970
1971         return 1;
1972 }
1973
1974 static uint32_t get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
1975                                     int enable_dc)
1976 {
1977         uint32_t mask;
1978         int requested_dc;
1979         int max_dc;
1980
1981         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
1982                 max_dc = 2;
1983                 mask = 0;
1984         } else if (IS_BROXTON(dev_priv)) {
1985                 max_dc = 1;
1986                 /*
1987                  * DC9 has a separate HW flow from the rest of the DC states,
1988                  * not depending on the DMC firmware. It's needed by system
1989                  * suspend/resume, so allow it unconditionally.
1990                  */
1991                 mask = DC_STATE_EN_DC9;
1992         } else {
1993                 max_dc = 0;
1994                 mask = 0;
1995         }
1996
1997         if (!i915.disable_power_well)
1998                 max_dc = 0;
1999
2000         if (enable_dc >= 0 && enable_dc <= max_dc) {
2001                 requested_dc = enable_dc;
2002         } else if (enable_dc == -1) {
2003                 requested_dc = max_dc;
2004         } else if (enable_dc > max_dc && enable_dc <= 2) {
2005                 DRM_DEBUG_KMS("Adjusting requested max DC state (%d->%d)\n",
2006                               enable_dc, max_dc);
2007                 requested_dc = max_dc;
2008         } else {
2009                 DRM_ERROR("Unexpected value for enable_dc (%d)\n", enable_dc);
2010                 requested_dc = max_dc;
2011         }
2012
2013         if (requested_dc > 1)
2014                 mask |= DC_STATE_EN_UPTO_DC6;
2015         if (requested_dc > 0)
2016                 mask |= DC_STATE_EN_UPTO_DC5;
2017
2018         DRM_DEBUG_KMS("Allowed DC state mask %02x\n", mask);
2019
2020         return mask;
2021 }
2022
2023 #define set_power_wells(power_domains, __power_wells) ({                \
2024         (power_domains)->power_wells = (__power_wells);                 \
2025         (power_domains)->power_well_count = ARRAY_SIZE(__power_wells);  \
2026 })
2027
2028 /**
2029  * intel_power_domains_init - initializes the power domain structures
2030  * @dev_priv: i915 device instance
2031  *
2032  * Initializes the power domain structures for @dev_priv depending upon the
2033  * supported platform.
2034  */
2035 int intel_power_domains_init(struct drm_i915_private *dev_priv)
2036 {
2037         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2038
2039         i915.disable_power_well = sanitize_disable_power_well_option(dev_priv,
2040                                                      i915.disable_power_well);
2041         dev_priv->csr.allowed_dc_mask = get_allowed_dc_mask(dev_priv,
2042                                                             i915.enable_dc);
2043
2044         BUILD_BUG_ON(POWER_DOMAIN_NUM > 31);
2045
2046         mutex_init(&power_domains->lock);
2047
2048         /*
2049          * The enabling order will be from lower to higher indexed wells,
2050          * the disabling order is reversed.
2051          */
2052         if (IS_HASWELL(dev_priv)) {
2053                 set_power_wells(power_domains, hsw_power_wells);
2054         } else if (IS_BROADWELL(dev_priv)) {
2055                 set_power_wells(power_domains, bdw_power_wells);
2056         } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
2057                 set_power_wells(power_domains, skl_power_wells);
2058         } else if (IS_BROXTON(dev_priv)) {
2059                 set_power_wells(power_domains, bxt_power_wells);
2060         } else if (IS_CHERRYVIEW(dev_priv)) {
2061                 set_power_wells(power_domains, chv_power_wells);
2062         } else if (IS_VALLEYVIEW(dev_priv)) {
2063                 set_power_wells(power_domains, vlv_power_wells);
2064         } else {
2065                 set_power_wells(power_domains, i9xx_always_on_power_well);
2066         }
2067
2068         return 0;
2069 }
2070
2071 /**
2072  * intel_power_domains_fini - finalizes the power domain structures
2073  * @dev_priv: i915 device instance
2074  *
2075  * Finalizes the power domain structures for @dev_priv depending upon the
2076  * supported platform. This function also disables runtime pm and ensures that
2077  * the device stays powered up so that the driver can be reloaded.
2078  */
2079 void intel_power_domains_fini(struct drm_i915_private *dev_priv)
2080 {
2081         struct device *device = &dev_priv->dev->pdev->dev;
2082
2083         /*
2084          * The i915.ko module is still not prepared to be loaded when
2085          * the power well is not enabled, so just enable it in case
2086          * we're going to unload/reload.
2087          * The following also reacquires the RPM reference the core passed
2088          * to the driver during loading, which is dropped in
2089          * intel_runtime_pm_enable(). We have to hand back the control of the
2090          * device to the core with this reference held.
2091          */
2092         intel_display_set_init_power(dev_priv, true);
2093
2094         /* Remove the refcount we took to keep power well support disabled. */
2095         if (!i915.disable_power_well)
2096                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
2097
2098         /*
2099          * Remove the refcount we took in intel_runtime_pm_enable() in case
2100          * the platform doesn't support runtime PM.
2101          */
2102         if (!HAS_RUNTIME_PM(dev_priv))
2103                 pm_runtime_put(device);
2104 }
2105
2106 static void intel_power_domains_sync_hw(struct drm_i915_private *dev_priv)
2107 {
2108         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2109         struct i915_power_well *power_well;
2110         int i;
2111
2112         mutex_lock(&power_domains->lock);
2113         for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
2114                 power_well->ops->sync_hw(dev_priv, power_well);
2115                 power_well->hw_enabled = power_well->ops->is_enabled(dev_priv,
2116                                                                      power_well);
2117         }
2118         mutex_unlock(&power_domains->lock);
2119 }
2120
2121 static void skl_display_core_init(struct drm_i915_private *dev_priv,
2122                                    bool resume)
2123 {
2124         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2125         struct i915_power_well *well;
2126         uint32_t val;
2127
2128         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
2129
2130         /* enable PCH reset handshake */
2131         val = I915_READ(HSW_NDE_RSTWRN_OPT);
2132         I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
2133
2134         /* enable PG1 and Misc I/O */
2135         mutex_lock(&power_domains->lock);
2136
2137         well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
2138         intel_power_well_enable(dev_priv, well);
2139
2140         well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);
2141         intel_power_well_enable(dev_priv, well);
2142
2143         mutex_unlock(&power_domains->lock);
2144
2145         if (!resume)
2146                 return;
2147
2148         skl_init_cdclk(dev_priv);
2149
2150         if (dev_priv->csr.dmc_payload)
2151                 intel_csr_load_program(dev_priv);
2152 }
2153
2154 static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
2155 {
2156         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2157         struct i915_power_well *well;
2158
2159         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
2160
2161         skl_uninit_cdclk(dev_priv);
2162
2163         /* The spec doesn't call for removing the reset handshake flag */
2164         /* disable PG1 and Misc I/O */
2165
2166         mutex_lock(&power_domains->lock);
2167
2168         well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);
2169         intel_power_well_disable(dev_priv, well);
2170
2171         well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
2172         intel_power_well_disable(dev_priv, well);
2173
2174         mutex_unlock(&power_domains->lock);
2175 }
2176
2177 void bxt_display_core_init(struct drm_i915_private *dev_priv,
2178                            bool resume)
2179 {
2180         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2181         struct i915_power_well *well;
2182         uint32_t val;
2183
2184         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
2185
2186         /*
2187          * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
2188          * or else the reset will hang because there is no PCH to respond.
2189          * Move the handshake programming to initialization sequence.
2190          * Previously was left up to BIOS.
2191          */
2192         val = I915_READ(HSW_NDE_RSTWRN_OPT);
2193         val &= ~RESET_PCH_HANDSHAKE_ENABLE;
2194         I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
2195
2196         /* Enable PG1 */
2197         mutex_lock(&power_domains->lock);
2198
2199         well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
2200         intel_power_well_enable(dev_priv, well);
2201
2202         mutex_unlock(&power_domains->lock);
2203
2204         broxton_init_cdclk(dev_priv);
2205         broxton_ddi_phy_init(dev_priv);
2206
2207         broxton_cdclk_verify_state(dev_priv);
2208         broxton_ddi_phy_verify_state(dev_priv);
2209
2210         if (resume && dev_priv->csr.dmc_payload)
2211                 intel_csr_load_program(dev_priv);
2212 }
2213
2214 void bxt_display_core_uninit(struct drm_i915_private *dev_priv)
2215 {
2216         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2217         struct i915_power_well *well;
2218
2219         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
2220
2221         broxton_ddi_phy_uninit(dev_priv);
2222         broxton_uninit_cdclk(dev_priv);
2223
2224         /* The spec doesn't call for removing the reset handshake flag */
2225
2226         /* Disable PG1 */
2227         mutex_lock(&power_domains->lock);
2228
2229         well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
2230         intel_power_well_disable(dev_priv, well);
2231
2232         mutex_unlock(&power_domains->lock);
2233 }
2234
2235 static void chv_phy_control_init(struct drm_i915_private *dev_priv)
2236 {
2237         struct i915_power_well *cmn_bc =
2238                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
2239         struct i915_power_well *cmn_d =
2240                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D);
2241
2242         /*
2243          * DISPLAY_PHY_CONTROL can get corrupted if read. As a
2244          * workaround never ever read DISPLAY_PHY_CONTROL, and
2245          * instead maintain a shadow copy ourselves. Use the actual
2246          * power well state and lane status to reconstruct the
2247          * expected initial value.
2248          */
2249         dev_priv->chv_phy_control =
2250                 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY0) |
2251                 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY1) |
2252                 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH0) |
2253                 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH1) |
2254                 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY1, DPIO_CH0);
2255
2256         /*
2257          * If all lanes are disabled we leave the override disabled
2258          * with all power down bits cleared to match the state we
2259          * would use after disabling the port. Otherwise enable the
2260          * override and set the lane powerdown bits accding to the
2261          * current lane status.
2262          */
2263         if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) {
2264                 uint32_t status = I915_READ(DPLL(PIPE_A));
2265                 unsigned int mask;
2266
2267                 mask = status & DPLL_PORTB_READY_MASK;
2268                 if (mask == 0xf)
2269                         mask = 0x0;
2270                 else
2271                         dev_priv->chv_phy_control |=
2272                                 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0);
2273
2274                 dev_priv->chv_phy_control |=
2275                         PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH0);
2276
2277                 mask = (status & DPLL_PORTC_READY_MASK) >> 4;
2278                 if (mask == 0xf)
2279                         mask = 0x0;
2280                 else
2281                         dev_priv->chv_phy_control |=
2282                                 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1);
2283
2284                 dev_priv->chv_phy_control |=
2285                         PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH1);
2286
2287                 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0);
2288
2289                 dev_priv->chv_phy_assert[DPIO_PHY0] = false;
2290         } else {
2291                 dev_priv->chv_phy_assert[DPIO_PHY0] = true;
2292         }
2293
2294         if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) {
2295                 uint32_t status = I915_READ(DPIO_PHY_STATUS);
2296                 unsigned int mask;
2297
2298                 mask = status & DPLL_PORTD_READY_MASK;
2299
2300                 if (mask == 0xf)
2301                         mask = 0x0;
2302                 else
2303                         dev_priv->chv_phy_control |=
2304                                 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0);
2305
2306                 dev_priv->chv_phy_control |=
2307                         PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY1, DPIO_CH0);
2308
2309                 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1);
2310
2311                 dev_priv->chv_phy_assert[DPIO_PHY1] = false;
2312         } else {
2313                 dev_priv->chv_phy_assert[DPIO_PHY1] = true;
2314         }
2315
2316         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
2317
2318         DRM_DEBUG_KMS("Initial PHY_CONTROL=0x%08x\n",
2319                       dev_priv->chv_phy_control);
2320 }
2321
2322 static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv)
2323 {
2324         struct i915_power_well *cmn =
2325                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
2326         struct i915_power_well *disp2d =
2327                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D);
2328
2329         /* If the display might be already active skip this */
2330         if (cmn->ops->is_enabled(dev_priv, cmn) &&
2331             disp2d->ops->is_enabled(dev_priv, disp2d) &&
2332             I915_READ(DPIO_CTL) & DPIO_CMNRST)
2333                 return;
2334
2335         DRM_DEBUG_KMS("toggling display PHY side reset\n");
2336
2337         /* cmnlane needs DPLL registers */
2338         disp2d->ops->enable(dev_priv, disp2d);
2339
2340         /*
2341          * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx:
2342          * Need to assert and de-assert PHY SB reset by gating the
2343          * common lane power, then un-gating it.
2344          * Simply ungating isn't enough to reset the PHY enough to get
2345          * ports and lanes running.
2346          */
2347         cmn->ops->disable(dev_priv, cmn);
2348 }
2349
2350 /**
2351  * intel_power_domains_init_hw - initialize hardware power domain state
2352  * @dev_priv: i915 device instance
2353  *
2354  * This function initializes the hardware power domain state and enables all
2355  * power domains using intel_display_set_init_power().
2356  */
2357 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume)
2358 {
2359         struct drm_device *dev = dev_priv->dev;
2360         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2361
2362         power_domains->initializing = true;
2363
2364         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
2365                 skl_display_core_init(dev_priv, resume);
2366         } else if (IS_BROXTON(dev)) {
2367                 bxt_display_core_init(dev_priv, resume);
2368         } else if (IS_CHERRYVIEW(dev)) {
2369                 mutex_lock(&power_domains->lock);
2370                 chv_phy_control_init(dev_priv);
2371                 mutex_unlock(&power_domains->lock);
2372         } else if (IS_VALLEYVIEW(dev)) {
2373                 mutex_lock(&power_domains->lock);
2374                 vlv_cmnlane_wa(dev_priv);
2375                 mutex_unlock(&power_domains->lock);
2376         }
2377
2378         /* For now, we need the power well to be always enabled. */
2379         intel_display_set_init_power(dev_priv, true);
2380         /* Disable power support if the user asked so. */
2381         if (!i915.disable_power_well)
2382                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
2383         intel_power_domains_sync_hw(dev_priv);
2384         power_domains->initializing = false;
2385 }
2386
2387 /**
2388  * intel_power_domains_suspend - suspend power domain state
2389  * @dev_priv: i915 device instance
2390  *
2391  * This function prepares the hardware power domain state before entering
2392  * system suspend. It must be paired with intel_power_domains_init_hw().
2393  */
2394 void intel_power_domains_suspend(struct drm_i915_private *dev_priv)
2395 {
2396         /*
2397          * Even if power well support was disabled we still want to disable
2398          * power wells while we are system suspended.
2399          */
2400         if (!i915.disable_power_well)
2401                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
2402
2403         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
2404                 skl_display_core_uninit(dev_priv);
2405         else if (IS_BROXTON(dev_priv))
2406                 bxt_display_core_uninit(dev_priv);
2407 }
2408
2409 /**
2410  * intel_runtime_pm_get - grab a runtime pm reference
2411  * @dev_priv: i915 device instance
2412  *
2413  * This function grabs a device-level runtime pm reference (mostly used for GEM
2414  * code to ensure the GTT or GT is on) and ensures that it is powered up.
2415  *
2416  * Any runtime pm reference obtained by this function must have a symmetric
2417  * call to intel_runtime_pm_put() to release the reference again.
2418  */
2419 void intel_runtime_pm_get(struct drm_i915_private *dev_priv)
2420 {
2421         struct drm_device *dev = dev_priv->dev;
2422         struct device *device = &dev->pdev->dev;
2423
2424         pm_runtime_get_sync(device);
2425
2426         atomic_inc(&dev_priv->pm.wakeref_count);
2427         assert_rpm_wakelock_held(dev_priv);
2428 }
2429
2430 /**
2431  * intel_runtime_pm_get_if_in_use - grab a runtime pm reference if device in use
2432  * @dev_priv: i915 device instance
2433  *
2434  * This function grabs a device-level runtime pm reference if the device is
2435  * already in use and ensures that it is powered up.
2436  *
2437  * Any runtime pm reference obtained by this function must have a symmetric
2438  * call to intel_runtime_pm_put() to release the reference again.
2439  */
2440 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv)
2441 {
2442         struct drm_device *dev = dev_priv->dev;
2443         struct device *device = &dev->pdev->dev;
2444
2445         if (IS_ENABLED(CONFIG_PM)) {
2446                 int ret = pm_runtime_get_if_in_use(device);
2447
2448                 /*
2449                  * In cases runtime PM is disabled by the RPM core and we get
2450                  * an -EINVAL return value we are not supposed to call this
2451                  * function, since the power state is undefined. This applies
2452                  * atm to the late/early system suspend/resume handlers.
2453                  */
2454                 WARN_ON_ONCE(ret < 0);
2455                 if (ret <= 0)
2456                         return false;
2457         }
2458
2459         atomic_inc(&dev_priv->pm.wakeref_count);
2460         assert_rpm_wakelock_held(dev_priv);
2461
2462         return true;
2463 }
2464
2465 /**
2466  * intel_runtime_pm_get_noresume - grab a runtime pm reference
2467  * @dev_priv: i915 device instance
2468  *
2469  * This function grabs a device-level runtime pm reference (mostly used for GEM
2470  * code to ensure the GTT or GT is on).
2471  *
2472  * It will _not_ power up the device but instead only check that it's powered
2473  * on.  Therefore it is only valid to call this functions from contexts where
2474  * the device is known to be powered up and where trying to power it up would
2475  * result in hilarity and deadlocks. That pretty much means only the system
2476  * suspend/resume code where this is used to grab runtime pm references for
2477  * delayed setup down in work items.
2478  *
2479  * Any runtime pm reference obtained by this function must have a symmetric
2480  * call to intel_runtime_pm_put() to release the reference again.
2481  */
2482 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv)
2483 {
2484         struct drm_device *dev = dev_priv->dev;
2485         struct device *device = &dev->pdev->dev;
2486
2487         assert_rpm_wakelock_held(dev_priv);
2488         pm_runtime_get_noresume(device);
2489
2490         atomic_inc(&dev_priv->pm.wakeref_count);
2491 }
2492
2493 /**
2494  * intel_runtime_pm_put - release a runtime pm reference
2495  * @dev_priv: i915 device instance
2496  *
2497  * This function drops the device-level runtime pm reference obtained by
2498  * intel_runtime_pm_get() and might power down the corresponding
2499  * hardware block right away if this is the last reference.
2500  */
2501 void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
2502 {
2503         struct drm_device *dev = dev_priv->dev;
2504         struct device *device = &dev->pdev->dev;
2505
2506         assert_rpm_wakelock_held(dev_priv);
2507         if (atomic_dec_and_test(&dev_priv->pm.wakeref_count))
2508                 atomic_inc(&dev_priv->pm.atomic_seq);
2509
2510         pm_runtime_mark_last_busy(device);
2511         pm_runtime_put_autosuspend(device);
2512 }
2513
2514 /**
2515  * intel_runtime_pm_enable - enable runtime pm
2516  * @dev_priv: i915 device instance
2517  *
2518  * This function enables runtime pm at the end of the driver load sequence.
2519  *
2520  * Note that this function does currently not enable runtime pm for the
2521  * subordinate display power domains. That is only done on the first modeset
2522  * using intel_display_set_init_power().
2523  */
2524 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv)
2525 {
2526         struct drm_device *dev = dev_priv->dev;
2527         struct device *device = &dev->pdev->dev;
2528
2529         pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */
2530         pm_runtime_mark_last_busy(device);
2531
2532         /*
2533          * Take a permanent reference to disable the RPM functionality and drop
2534          * it only when unloading the driver. Use the low level get/put helpers,
2535          * so the driver's own RPM reference tracking asserts also work on
2536          * platforms without RPM support.
2537          */
2538         if (!HAS_RUNTIME_PM(dev)) {
2539                 pm_runtime_dont_use_autosuspend(device);
2540                 pm_runtime_get_sync(device);
2541         } else {
2542                 pm_runtime_use_autosuspend(device);
2543         }
2544
2545         /*
2546          * The core calls the driver load handler with an RPM reference held.
2547          * We drop that here and will reacquire it during unloading in
2548          * intel_power_domains_fini().
2549          */
2550         pm_runtime_put_autosuspend(device);
2551 }
2552