drivers/gpu/drm/i915/intel_runtime_pm.c

   1 /*
   2  * Copyright © 2012-2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *    Daniel Vetter <daniel.vetter@ffwll.ch>
  26  *
  27  */
  28
  29 #include <linux/pm_runtime.h>
  30 #include <linux/vgaarb.h>
  31
  32 #include "i915_drv.h"
  33 #include "intel_drv.h"
  34
  35 /**
  36  * DOC: runtime pm
  37  *
  38  * The i915 driver supports dynamic enabling and disabling of entire hardware
  39  * blocks at runtime. This is especially important on the display side where
  40  * software is supposed to control many power gates manually on recent hardware,
  41  * since on the GT side a lot of the power management is done by the hardware.
  42  * But even there some manual control at the device level is required.
  43  *
  44  * Since i915 supports a diverse set of platforms with a unified codebase and
  45  * hardware engineers just love to shuffle functionality around between power
  46  * domains there's a sizeable amount of indirection required. This file provides
  47  * generic functions to the driver for grabbing and releasing references for
  48  * abstract power domains. It then maps those to the actual power wells
  49  * present for a given platform.
  50  */
  51
  52 #define GEN9_ENABLE_DC5(dev) 0
  53 #define SKL_ENABLE_DC6(dev) IS_SKYLAKE(dev)
  54
  55 #define for_each_power_well(i, power_well, domain_mask, power_domains)  \
  56         for (i = 0;                                                     \
  57              i < (power_domains)->power_well_count &&                   \
  58                  ((power_well) = &(power_domains)->power_wells[i]);     \
  59              i++)                                                       \
  60                 if ((power_well)->domains & (domain_mask))
  61
  62 #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
  63         for (i = (power_domains)->power_well_count - 1;                  \
  64              i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
  65              i--)                                                        \
  66                 if ((power_well)->domains & (domain_mask))
  67
  68 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
  69                                     int power_well_id);
  70
  71 static void intel_power_well_enable(struct drm_i915_private *dev_priv,
  72                                     struct i915_power_well *power_well)
  73 {
  74         DRM_DEBUG_KMS("enabling %s\n", power_well->name);
  75         power_well->ops->enable(dev_priv, power_well);
  76         power_well->hw_enabled = true;
  77 }
  78
  79 static void intel_power_well_disable(struct drm_i915_private *dev_priv,
  80                                      struct i915_power_well *power_well)
  81 {
  82         DRM_DEBUG_KMS("disabling %s\n", power_well->name);
  83         power_well->hw_enabled = false;
  84         power_well->ops->disable(dev_priv, power_well);
  85 }
  86
  87 /*
  88  * We should only use the power well if we explicitly asked the hardware to
  89  * enable it, so check if it's enabled and also check if we've requested it to
  90  * be enabled.
  91  */
  92 static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
  93                                    struct i915_power_well *power_well)
  94 {
  95         return I915_READ(HSW_PWR_WELL_DRIVER) ==
  96                      (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
  97 }
  98
  99 /**
 100  * __intel_display_power_is_enabled - unlocked check for a power domain
 101  * @dev_priv: i915 device instance
 102  * @domain: power domain to check
 103  *
 104  * This is the unlocked version of intel_display_power_is_enabled() and should
 105  * only be used from error capture and recovery code where deadlocks are
 106  * possible.
 107  *
 108  * Returns:
 109  * True when the power domain is enabled, false otherwise.
 110  */
 111 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
 112                                       enum intel_display_power_domain domain)
 113 {
 114         struct i915_power_domains *power_domains;
 115         struct i915_power_well *power_well;
 116         bool is_enabled;
 117         int i;
 118
 119         if (dev_priv->pm.suspended)
 120                 return false;
 121
 122         power_domains = &dev_priv->power_domains;
 123
 124         is_enabled = true;
 125
 126         for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
 127                 if (power_well->always_on)
 128                         continue;
 129
 130                 if (!power_well->hw_enabled) {
 131                         is_enabled = false;
 132                         break;
 133                 }
 134         }
 135
 136         return is_enabled;
 137 }
 138
 139 /**
 140  * intel_display_power_is_enabled - check for a power domain
 141  * @dev_priv: i915 device instance
 142  * @domain: power domain to check
 143  *
 144  * This function can be used to check the hw power domain state. It is mostly
 145  * used in hardware state readout functions. Everywhere else code should rely
 146  * upon explicit power domain reference counting to ensure that the hardware
 147  * block is powered up before accessing it.
 148  *
 149  * Callers must hold the relevant modesetting locks to ensure that concurrent
 150  * threads can't disable the power well while the caller tries to read a few
 151  * registers.
 152  *
 153  * Returns:
 154  * True when the power domain is enabled, false otherwise.
 155  */
 156 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
 157                                     enum intel_display_power_domain domain)
 158 {
 159         struct i915_power_domains *power_domains;
 160         bool ret;
 161
 162         power_domains = &dev_priv->power_domains;
 163
 164         mutex_lock(&power_domains->lock);
 165         ret = __intel_display_power_is_enabled(dev_priv, domain);
 166         mutex_unlock(&power_domains->lock);
 167
 168         return ret;
 169 }
 170
 171 /**
 172  * intel_display_set_init_power - set the initial power domain state
 173  * @dev_priv: i915 device instance
 174  * @enable: whether to enable or disable the initial power domain state
 175  *
 176  * For simplicity our driver load/unload and system suspend/resume code assumes
 177  * that all power domains are always enabled. This functions controls the state
 178  * of this little hack. While the initial power domain state is enabled runtime
 179  * pm is effectively disabled.
 180  */
 181 void intel_display_set_init_power(struct drm_i915_private *dev_priv,
 182                                   bool enable)
 183 {
 184         if (dev_priv->power_domains.init_power_on == enable)
 185                 return;
 186
 187         if (enable)
 188                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
 189         else
 190                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
 191
 192         dev_priv->power_domains.init_power_on = enable;
 193 }
 194
 195 /*
 196  * Starting with Haswell, we have a "Power Down Well" that can be turned off
 197  * when not needed anymore. We have 4 registers that can request the power well
 198  * to be enabled, and it will only be disabled if none of the registers is
 199  * requesting it to be enabled.
 200  */
 201 static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
 202 {
 203         struct drm_device *dev = dev_priv->dev;
 204
 205         /*
 206          * After we re-enable the power well, if we touch VGA register 0x3d5
 207          * we'll get unclaimed register interrupts. This stops after we write
 208          * anything to the VGA MSR register. The vgacon module uses this
 209          * register all the time, so if we unbind our driver and, as a
 210          * consequence, bind vgacon, we'll get stuck in an infinite loop at
 211          * console_unlock(). So make here we touch the VGA MSR register, making
 212          * sure vgacon can keep working normally without triggering interrupts
 213          * and error messages.
 214          */
 215         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
 216         outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
 217         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
 218
 219         if (IS_BROADWELL(dev))
 220                 gen8_irq_power_well_post_enable(dev_priv,
 221                                                 1 << PIPE_C | 1 << PIPE_B);
 222 }
 223
 224 static void skl_power_well_post_enable(struct drm_i915_private *dev_priv,
 225                                        struct i915_power_well *power_well)
 226 {
 227         struct drm_device *dev = dev_priv->dev;
 228
 229         /*
 230          * After we re-enable the power well, if we touch VGA register 0x3d5
 231          * we'll get unclaimed register interrupts. This stops after we write
 232          * anything to the VGA MSR register. The vgacon module uses this
 233          * register all the time, so if we unbind our driver and, as a
 234          * consequence, bind vgacon, we'll get stuck in an infinite loop at
 235          * console_unlock(). So make here we touch the VGA MSR register, making
 236          * sure vgacon can keep working normally without triggering interrupts
 237          * and error messages.
 238          */
 239         if (power_well->data == SKL_DISP_PW_2) {
 240                 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
 241                 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
 242                 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
 243
 244                 gen8_irq_power_well_post_enable(dev_priv,
 245                                                 1 << PIPE_C | 1 << PIPE_B);
 246         }
 247 }
 248
 249 static void hsw_set_power_well(struct drm_i915_private *dev_priv,
 250                                struct i915_power_well *power_well, bool enable)
 251 {
 252         bool is_enabled, enable_requested;
 253         uint32_t tmp;
 254
 255         tmp = I915_READ(HSW_PWR_WELL_DRIVER);
 256         is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
 257         enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
 258
 259         if (enable) {
 260                 if (!enable_requested)
 261                         I915_WRITE(HSW_PWR_WELL_DRIVER,
 262                                    HSW_PWR_WELL_ENABLE_REQUEST);
 263
 264                 if (!is_enabled) {
 265                         DRM_DEBUG_KMS("Enabling power well\n");
 266                         if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
 267                                       HSW_PWR_WELL_STATE_ENABLED), 20))
 268                                 DRM_ERROR("Timeout enabling power well\n");
 269                         hsw_power_well_post_enable(dev_priv);
 270                 }
 271
 272         } else {
 273                 if (enable_requested) {
 274                         I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
 275                         POSTING_READ(HSW_PWR_WELL_DRIVER);
 276                         DRM_DEBUG_KMS("Requesting to disable the power well\n");
 277                 }
 278         }
 279 }
 280
 281 #define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS (         \
 282         BIT(POWER_DOMAIN_TRANSCODER_A) |                \
 283         BIT(POWER_DOMAIN_PIPE_B) |                      \
 284         BIT(POWER_DOMAIN_TRANSCODER_B) |                \
 285         BIT(POWER_DOMAIN_PIPE_C) |                      \
 286         BIT(POWER_DOMAIN_TRANSCODER_C) |                \
 287         BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |         \
 288         BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |         \
 289         BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) |          \
 290         BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |          \
 291         BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) |          \
 292         BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |          \
 293         BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) |          \
 294         BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) |          \
 295         BIT(POWER_DOMAIN_PORT_DDI_E_2_LANES) |          \
 296         BIT(POWER_DOMAIN_AUX_B) |                       \
 297         BIT(POWER_DOMAIN_AUX_C) |                       \
 298         BIT(POWER_DOMAIN_AUX_D) |                       \
 299         BIT(POWER_DOMAIN_AUDIO) |                       \
 300         BIT(POWER_DOMAIN_VGA) |                         \
 301         BIT(POWER_DOMAIN_INIT))
 302 #define SKL_DISPLAY_DDI_A_E_POWER_DOMAINS (             \
 303         BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) |          \
 304         BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) |          \
 305         BIT(POWER_DOMAIN_PORT_DDI_E_2_LANES) |          \
 306         BIT(POWER_DOMAIN_INIT))
 307 #define SKL_DISPLAY_DDI_B_POWER_DOMAINS (               \
 308         BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) |          \
 309         BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |          \
 310         BIT(POWER_DOMAIN_INIT))
 311 #define SKL_DISPLAY_DDI_C_POWER_DOMAINS (               \
 312         BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) |          \
 313         BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |          \
 314         BIT(POWER_DOMAIN_INIT))
 315 #define SKL_DISPLAY_DDI_D_POWER_DOMAINS (               \
 316         BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) |          \
 317         BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) |          \
 318         BIT(POWER_DOMAIN_INIT))
 319 #define SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS (           \
 320         (POWER_DOMAIN_MASK & ~(                         \
 321         SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS |         \
 322         SKL_DISPLAY_DDI_A_E_POWER_DOMAINS |             \
 323         SKL_DISPLAY_DDI_B_POWER_DOMAINS |               \
 324         SKL_DISPLAY_DDI_C_POWER_DOMAINS |               \
 325         SKL_DISPLAY_DDI_D_POWER_DOMAINS)) |             \
 326         BIT(POWER_DOMAIN_INIT))
 327
 328 #define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS (         \
 329         BIT(POWER_DOMAIN_TRANSCODER_A) |                \
 330         BIT(POWER_DOMAIN_PIPE_B) |                      \
 331         BIT(POWER_DOMAIN_TRANSCODER_B) |                \
 332         BIT(POWER_DOMAIN_PIPE_C) |                      \
 333         BIT(POWER_DOMAIN_TRANSCODER_C) |                \
 334         BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |         \
 335         BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |         \
 336         BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) |          \
 337         BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |          \
 338         BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) |          \
 339         BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |          \
 340         BIT(POWER_DOMAIN_AUX_B) |                       \
 341         BIT(POWER_DOMAIN_AUX_C) |                       \
 342         BIT(POWER_DOMAIN_AUDIO) |                       \
 343         BIT(POWER_DOMAIN_VGA) |                         \
 344         BIT(POWER_DOMAIN_INIT))
 345 #define BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS (         \
 346         BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS |         \
 347         BIT(POWER_DOMAIN_PIPE_A) |                      \
 348         BIT(POWER_DOMAIN_TRANSCODER_EDP) |              \
 349         BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) |         \
 350         BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) |          \
 351         BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) |          \
 352         BIT(POWER_DOMAIN_AUX_A) |                       \
 353         BIT(POWER_DOMAIN_PLLS) |                        \
 354         BIT(POWER_DOMAIN_INIT))
 355 #define BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS (           \
 356         (POWER_DOMAIN_MASK & ~(BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS |  \
 357         BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS)) |       \
 358         BIT(POWER_DOMAIN_INIT))
 359
 360 static void assert_can_enable_dc9(struct drm_i915_private *dev_priv)
 361 {
 362         struct drm_device *dev = dev_priv->dev;
 363
 364         WARN(!IS_BROXTON(dev), "Platform doesn't support DC9.\n");
 365         WARN((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9),
 366                 "DC9 already programmed to be enabled.\n");
 367         WARN(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
 368                 "DC5 still not disabled to enable DC9.\n");
 369         WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on.\n");
 370         WARN(intel_irqs_enabled(dev_priv), "Interrupts not disabled yet.\n");
 371
 372          /*
 373           * TODO: check for the following to verify the conditions to enter DC9
 374           * state are satisfied:
 375           * 1] Check relevant display engine registers to verify if mode set
 376           * disable sequence was followed.
 377           * 2] Check if display uninitialize sequence is initialized.
 378           */
 379 }
 380
 381 static void assert_can_disable_dc9(struct drm_i915_private *dev_priv)
 382 {
 383         WARN(intel_irqs_enabled(dev_priv), "Interrupts not disabled yet.\n");
 384         WARN(!(I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9),
 385                 "DC9 already programmed to be disabled.\n");
 386         WARN(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
 387                 "DC5 still not disabled.\n");
 388
 389          /*
 390           * TODO: check for the following to verify DC9 state was indeed
 391           * entered before programming to disable it:
 392           * 1] Check relevant display engine registers to verify if mode
 393           *  set disable sequence was followed.
 394           * 2] Check if display uninitialize sequence is initialized.
 395           */
 396 }
 397
 398 static void gen9_set_dc_state(struct drm_i915_private *dev_priv, uint32_t state)
 399 {
 400         uint32_t val;
 401         uint32_t mask;
 402
 403         mask = DC_STATE_EN_UPTO_DC5;
 404         if (IS_BROXTON(dev_priv))
 405                 mask |= DC_STATE_EN_DC9;
 406         else
 407                 mask |= DC_STATE_EN_UPTO_DC6;
 408
 409         WARN_ON_ONCE(state & ~mask);
 410
 411         val = I915_READ(DC_STATE_EN);
 412         DRM_DEBUG_KMS("Setting DC state from %02x to %02x\n",
 413                       val & mask, state);
 414         val &= ~mask;
 415         val |= state;
 416         I915_WRITE(DC_STATE_EN, val);
 417         POSTING_READ(DC_STATE_EN);
 418 }
 419
 420 void bxt_enable_dc9(struct drm_i915_private *dev_priv)
 421 {
 422         assert_can_enable_dc9(dev_priv);
 423
 424         DRM_DEBUG_KMS("Enabling DC9\n");
 425
 426         gen9_set_dc_state(dev_priv, DC_STATE_EN_DC9);
 427 }
 428
 429 void bxt_disable_dc9(struct drm_i915_private *dev_priv)
 430 {
 431         assert_can_disable_dc9(dev_priv);
 432
 433         DRM_DEBUG_KMS("Disabling DC9\n");
 434
 435         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 436 }
 437
 438 static void gen9_set_dc_state_debugmask_memory_up(
 439                         struct drm_i915_private *dev_priv)
 440 {
 441         uint32_t val;
 442
 443         /* The below bit doesn't need to be cleared ever afterwards */
 444         val = I915_READ(DC_STATE_DEBUG);
 445         if (!(val & DC_STATE_DEBUG_MASK_MEMORY_UP)) {
 446                 val |= DC_STATE_DEBUG_MASK_MEMORY_UP;
 447                 I915_WRITE(DC_STATE_DEBUG, val);
 448                 POSTING_READ(DC_STATE_DEBUG);
 449         }
 450 }
 451
 452 static void assert_csr_loaded(struct drm_i915_private *dev_priv)
 453 {
 454         WARN_ONCE(!I915_READ(CSR_PROGRAM(0)),
 455                   "CSR program storage start is NULL\n");
 456         WARN_ONCE(!I915_READ(CSR_SSP_BASE), "CSR SSP Base Not fine\n");
 457         WARN_ONCE(!I915_READ(CSR_HTP_SKL), "CSR HTP Not fine\n");
 458 }
 459
 460 static void assert_can_enable_dc5(struct drm_i915_private *dev_priv)
 461 {
 462         struct drm_device *dev = dev_priv->dev;
 463         bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv,
 464                                         SKL_DISP_PW_2);
 465
 466         WARN_ONCE(!IS_SKYLAKE(dev), "Platform doesn't support DC5.\n");
 467         WARN_ONCE(!HAS_RUNTIME_PM(dev), "Runtime PM not enabled.\n");
 468         WARN_ONCE(pg2_enabled, "PG2 not disabled to enable DC5.\n");
 469
 470         WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5),
 471                   "DC5 already programmed to be enabled.\n");
 472         WARN_ONCE(dev_priv->pm.suspended,
 473                   "DC5 cannot be enabled, if platform is runtime-suspended.\n");
 474
 475         assert_csr_loaded(dev_priv);
 476 }
 477
 478 static void assert_can_disable_dc5(struct drm_i915_private *dev_priv)
 479 {
 480         bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv,
 481                                         SKL_DISP_PW_2);
 482         /*
 483          * During initialization, the firmware may not be loaded yet.
 484          * We still want to make sure that the DC enabling flag is cleared.
 485          */
 486         if (dev_priv->power_domains.initializing)
 487                 return;
 488
 489         WARN_ONCE(!pg2_enabled, "PG2 not enabled to disable DC5.\n");
 490         WARN_ONCE(dev_priv->pm.suspended,
 491                 "Disabling of DC5 while platform is runtime-suspended should never happen.\n");
 492 }
 493
 494 static void gen9_enable_dc5(struct drm_i915_private *dev_priv)
 495 {
 496         assert_can_enable_dc5(dev_priv);
 497
 498         DRM_DEBUG_KMS("Enabling DC5\n");
 499
 500         gen9_set_dc_state_debugmask_memory_up(dev_priv);
 501
 502         gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5);
 503 }
 504
 505 static void gen9_disable_dc5(struct drm_i915_private *dev_priv)
 506 {
 507         assert_can_disable_dc5(dev_priv);
 508
 509         DRM_DEBUG_KMS("Disabling DC5\n");
 510
 511         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 512 }
 513
 514 static void assert_can_enable_dc6(struct drm_i915_private *dev_priv)
 515 {
 516         struct drm_device *dev = dev_priv->dev;
 517
 518         WARN_ONCE(!IS_SKYLAKE(dev), "Platform doesn't support DC6.\n");
 519         WARN_ONCE(!HAS_RUNTIME_PM(dev), "Runtime PM not enabled.\n");
 520         WARN_ONCE(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
 521                   "Backlight is not disabled.\n");
 522         WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6),
 523                   "DC6 already programmed to be enabled.\n");
 524
 525         assert_csr_loaded(dev_priv);
 526 }
 527
 528 static void assert_can_disable_dc6(struct drm_i915_private *dev_priv)
 529 {
 530         /*
 531          * During initialization, the firmware may not be loaded yet.
 532          * We still want to make sure that the DC enabling flag is cleared.
 533          */
 534         if (dev_priv->power_domains.initializing)
 535                 return;
 536
 537         WARN_ONCE(!(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6),
 538                   "DC6 already programmed to be disabled.\n");
 539 }
 540
 541 void skl_enable_dc6(struct drm_i915_private *dev_priv)
 542 {
 543         assert_can_enable_dc6(dev_priv);
 544
 545         DRM_DEBUG_KMS("Enabling DC6\n");
 546
 547         gen9_set_dc_state_debugmask_memory_up(dev_priv);
 548
 549         gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
 550
 551 }
 552
 553 void skl_disable_dc6(struct drm_i915_private *dev_priv)
 554 {
 555         assert_can_disable_dc6(dev_priv);
 556
 557         DRM_DEBUG_KMS("Disabling DC6\n");
 558
 559         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 560 }
 561
 562 static void skl_set_power_well(struct drm_i915_private *dev_priv,
 563                         struct i915_power_well *power_well, bool enable)
 564 {
 565         struct drm_device *dev = dev_priv->dev;
 566         uint32_t tmp, fuse_status;
 567         uint32_t req_mask, state_mask;
 568         bool is_enabled, enable_requested, check_fuse_status = false;
 569
 570         tmp = I915_READ(HSW_PWR_WELL_DRIVER);
 571         fuse_status = I915_READ(SKL_FUSE_STATUS);
 572
 573         switch (power_well->data) {
 574         case SKL_DISP_PW_1:
 575                 if (wait_for((I915_READ(SKL_FUSE_STATUS) &
 576                         SKL_FUSE_PG0_DIST_STATUS), 1)) {
 577                         DRM_ERROR("PG0 not enabled\n");
 578                         return;
 579                 }
 580                 break;
 581         case SKL_DISP_PW_2:
 582                 if (!(fuse_status & SKL_FUSE_PG1_DIST_STATUS)) {
 583                         DRM_ERROR("PG1 in disabled state\n");
 584                         return;
 585                 }
 586                 break;
 587         case SKL_DISP_PW_DDI_A_E:
 588         case SKL_DISP_PW_DDI_B:
 589         case SKL_DISP_PW_DDI_C:
 590         case SKL_DISP_PW_DDI_D:
 591         case SKL_DISP_PW_MISC_IO:
 592                 break;
 593         default:
 594                 WARN(1, "Unknown power well %lu\n", power_well->data);
 595                 return;
 596         }
 597
 598         req_mask = SKL_POWER_WELL_REQ(power_well->data);
 599         enable_requested = tmp & req_mask;
 600         state_mask = SKL_POWER_WELL_STATE(power_well->data);
 601         is_enabled = tmp & state_mask;
 602
 603         if (enable) {
 604                 if (!enable_requested) {
 605                         WARN((tmp & state_mask) &&
 606                                 !I915_READ(HSW_PWR_WELL_BIOS),
 607                                 "Invalid for power well status to be enabled, unless done by the BIOS, \
 608                                 when request is to disable!\n");
 609                         if (power_well->data == SKL_DISP_PW_2) {
 610                                 if (GEN9_ENABLE_DC5(dev))
 611                                         gen9_disable_dc5(dev_priv);
 612                                 if (SKL_ENABLE_DC6(dev)) {
 613                                         /*
 614                                          * DDI buffer programming unnecessary during driver-load/resume
 615                                          * as it's already done during modeset initialization then.
 616                                          * It's also invalid here as encoder list is still uninitialized.
 617                                          */
 618                                         if (!dev_priv->power_domains.initializing)
 619                                                 intel_prepare_ddi(dev);
 620                                 }
 621                         }
 622                         I915_WRITE(HSW_PWR_WELL_DRIVER, tmp | req_mask);
 623                 }
 624
 625                 if (!is_enabled) {
 626                         DRM_DEBUG_KMS("Enabling %s\n", power_well->name);
 627                         if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
 628                                 state_mask), 1))
 629                                 DRM_ERROR("%s enable timeout\n",
 630                                         power_well->name);
 631                         check_fuse_status = true;
 632                 }
 633         } else {
 634                 if (enable_requested) {
 635                         I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask);
 636                         POSTING_READ(HSW_PWR_WELL_DRIVER);
 637                         DRM_DEBUG_KMS("Disabling %s\n", power_well->name);
 638
 639                         if (GEN9_ENABLE_DC5(dev) &&
 640                                 power_well->data == SKL_DISP_PW_2)
 641                                         gen9_enable_dc5(dev_priv);
 642                 }
 643         }
 644
 645         if (check_fuse_status) {
 646                 if (power_well->data == SKL_DISP_PW_1) {
 647                         if (wait_for((I915_READ(SKL_FUSE_STATUS) &
 648                                 SKL_FUSE_PG1_DIST_STATUS), 1))
 649                                 DRM_ERROR("PG1 distributing status timeout\n");
 650                 } else if (power_well->data == SKL_DISP_PW_2) {
 651                         if (wait_for((I915_READ(SKL_FUSE_STATUS) &
 652                                 SKL_FUSE_PG2_DIST_STATUS), 1))
 653                                 DRM_ERROR("PG2 distributing status timeout\n");
 654                 }
 655         }
 656
 657         if (enable && !is_enabled)
 658                 skl_power_well_post_enable(dev_priv, power_well);
 659 }
 660
 661 static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
 662                                    struct i915_power_well *power_well)
 663 {
 664         hsw_set_power_well(dev_priv, power_well, power_well->count > 0);
 665
 666         /*
 667          * We're taking over the BIOS, so clear any requests made by it since
 668          * the driver is in charge now.
 669          */
 670         if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
 671                 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
 672 }
 673
 674 static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
 675                                   struct i915_power_well *power_well)
 676 {
 677         hsw_set_power_well(dev_priv, power_well, true);
 678 }
 679
 680 static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
 681                                    struct i915_power_well *power_well)
 682 {
 683         hsw_set_power_well(dev_priv, power_well, false);
 684 }
 685
 686 static bool skl_power_well_enabled(struct drm_i915_private *dev_priv,
 687                                         struct i915_power_well *power_well)
 688 {
 689         uint32_t mask = SKL_POWER_WELL_REQ(power_well->data) |
 690                 SKL_POWER_WELL_STATE(power_well->data);
 691
 692         return (I915_READ(HSW_PWR_WELL_DRIVER) & mask) == mask;
 693 }
 694
 695 static void skl_power_well_sync_hw(struct drm_i915_private *dev_priv,
 696                                 struct i915_power_well *power_well)
 697 {
 698         skl_set_power_well(dev_priv, power_well, power_well->count > 0);
 699
 700         /* Clear any request made by BIOS as driver is taking over */
 701         I915_WRITE(HSW_PWR_WELL_BIOS, 0);
 702 }
 703
 704 static void skl_power_well_enable(struct drm_i915_private *dev_priv,
 705                                 struct i915_power_well *power_well)
 706 {
 707         skl_set_power_well(dev_priv, power_well, true);
 708 }
 709
 710 static void skl_power_well_disable(struct drm_i915_private *dev_priv,
 711                                 struct i915_power_well *power_well)
 712 {
 713         skl_set_power_well(dev_priv, power_well, false);
 714 }
 715
 716 static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,
 717                                            struct i915_power_well *power_well)
 718 {
 719 }
 720
 721 static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,
 722                                              struct i915_power_well *power_well)
 723 {
 724         return true;
 725 }
 726
 727 static void vlv_set_power_well(struct drm_i915_private *dev_priv,
 728                                struct i915_power_well *power_well, bool enable)
 729 {
 730         enum punit_power_well power_well_id = power_well->data;
 731         u32 mask;
 732         u32 state;
 733         u32 ctrl;
 734
 735         mask = PUNIT_PWRGT_MASK(power_well_id);
 736         state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) :
 737                          PUNIT_PWRGT_PWR_GATE(power_well_id);
 738
 739         mutex_lock(&dev_priv->rps.hw_lock);
 740
 741 #define COND \
 742         ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)
 743
 744         if (COND)
 745                 goto out;
 746
 747         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL);
 748         ctrl &= ~mask;
 749         ctrl |= state;
 750         vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl);
 751
 752         if (wait_for(COND, 100))
 753                 DRM_ERROR("timeout setting power well state %08x (%08x)\n",
 754                           state,
 755                           vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL));
 756
 757 #undef COND
 758
 759 out:
 760         mutex_unlock(&dev_priv->rps.hw_lock);
 761 }
 762
 763 static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv,
 764                                    struct i915_power_well *power_well)
 765 {
 766         vlv_set_power_well(dev_priv, power_well, power_well->count > 0);
 767 }
 768
 769 static void vlv_power_well_enable(struct drm_i915_private *dev_priv,
 770                                   struct i915_power_well *power_well)
 771 {
 772         vlv_set_power_well(dev_priv, power_well, true);
 773 }
 774
 775 static void vlv_power_well_disable(struct drm_i915_private *dev_priv,
 776                                    struct i915_power_well *power_well)
 777 {
 778         vlv_set_power_well(dev_priv, power_well, false);
 779 }
 780
 781 static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
 782                                    struct i915_power_well *power_well)
 783 {
 784         int power_well_id = power_well->data;
 785         bool enabled = false;
 786         u32 mask;
 787         u32 state;
 788         u32 ctrl;
 789
 790         mask = PUNIT_PWRGT_MASK(power_well_id);
 791         ctrl = PUNIT_PWRGT_PWR_ON(power_well_id);
 792
 793         mutex_lock(&dev_priv->rps.hw_lock);
 794
 795         state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask;
 796         /*
 797          * We only ever set the power-on and power-gate states, anything
 798          * else is unexpected.
 799          */
 800         WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) &&
 801                 state != PUNIT_PWRGT_PWR_GATE(power_well_id));
 802         if (state == ctrl)
 803                 enabled = true;
 804
 805         /*
 806          * A transient state at this point would mean some unexpected party
 807          * is poking at the power controls too.
 808          */
 809         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask;
 810         WARN_ON(ctrl != state);
 811
 812         mutex_unlock(&dev_priv->rps.hw_lock);
 813
 814         return enabled;
 815 }
 816
 817 static void vlv_display_power_well_init(struct drm_i915_private *dev_priv)
 818 {
 819         enum pipe pipe;
 820
 821         /*
 822          * Enable the CRI clock source so we can get at the
 823          * display and the reference clock for VGA
 824          * hotplug / manual detection. Supposedly DSI also
 825          * needs the ref clock up and running.
 826          *
 827          * CHV DPLL B/C have some issues if VGA mode is enabled.
 828          */
 829         for_each_pipe(dev_priv->dev, pipe) {
 830                 u32 val = I915_READ(DPLL(pipe));
 831
 832                 val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
 833                 if (pipe != PIPE_A)
 834                         val |= DPLL_INTEGRATED_CRI_CLK_VLV;
 835
 836                 I915_WRITE(DPLL(pipe), val);
 837         }
 838
 839         spin_lock_irq(&dev_priv->irq_lock);
 840         valleyview_enable_display_irqs(dev_priv);
 841         spin_unlock_irq(&dev_priv->irq_lock);
 842
 843         /*
 844          * During driver initialization/resume we can avoid restoring the
 845          * part of the HW/SW state that will be inited anyway explicitly.
 846          */
 847         if (dev_priv->power_domains.initializing)
 848                 return;
 849
 850         intel_hpd_init(dev_priv);
 851
 852         i915_redisable_vga_power_on(dev_priv->dev);
 853 }
 854
 855 static void vlv_display_power_well_deinit(struct drm_i915_private *dev_priv)
 856 {
 857         spin_lock_irq(&dev_priv->irq_lock);
 858         valleyview_disable_display_irqs(dev_priv);
 859         spin_unlock_irq(&dev_priv->irq_lock);
 860
 861         vlv_power_sequencer_reset(dev_priv);
 862 }
 863
 864 static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv,
 865                                           struct i915_power_well *power_well)
 866 {
 867         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
 868
 869         vlv_set_power_well(dev_priv, power_well, true);
 870
 871         vlv_display_power_well_init(dev_priv);
 872 }
 873
 874 static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv,
 875                                            struct i915_power_well *power_well)
 876 {
 877         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
 878
 879         vlv_display_power_well_deinit(dev_priv);
 880
 881         vlv_set_power_well(dev_priv, power_well, false);
 882 }
 883
 884 static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
 885                                            struct i915_power_well *power_well)
 886 {
 887         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
 888
 889         /* since ref/cri clock was enabled */
 890         udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
 891
 892         vlv_set_power_well(dev_priv, power_well, true);
 893
 894         /*
 895          * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
 896          *  6.  De-assert cmn_reset/side_reset. Same as VLV X0.
 897          *   a. GUnit 0x2110 bit[0] set to 1 (def 0)
 898          *   b. The other bits such as sfr settings / modesel may all
 899          *      be set to 0.
 900          *
 901          * This should only be done on init and resume from S3 with
 902          * both PLLs disabled, or we risk losing DPIO and PLL
 903          * synchronization.
 904          */
 905         I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
 906 }
 907
 908 static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
 909                                             struct i915_power_well *power_well)
 910 {
 911         enum pipe pipe;
 912
 913         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
 914
 915         for_each_pipe(dev_priv, pipe)
 916                 assert_pll_disabled(dev_priv, pipe);
 917
 918         /* Assert common reset */
 919         I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST);
 920
 921         vlv_set_power_well(dev_priv, power_well, false);
 922 }
 923
 924 #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
 925
 926 static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv,
 927                                                  int power_well_id)
 928 {
 929         struct i915_power_domains *power_domains = &dev_priv->power_domains;
 930         int i;
 931
 932         for (i = 0; i < power_domains->power_well_count; i++) {
 933                 struct i915_power_well *power_well;
 934
 935                 power_well = &power_domains->power_wells[i];
 936                 if (power_well->data == power_well_id)
 937                         return power_well;
 938         }
 939
 940         return NULL;
 941 }
 942
 943 #define BITS_SET(val, bits) (((val) & (bits)) == (bits))
 944
 945 static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
 946 {
 947         struct i915_power_well *cmn_bc =
 948                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
 949         struct i915_power_well *cmn_d =
 950                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D);
 951         u32 phy_control = dev_priv->chv_phy_control;
 952         u32 phy_status = 0;
 953         u32 phy_status_mask = 0xffffffff;
 954         u32 tmp;
 955
 956         /*
 957          * The BIOS can leave the PHY is some weird state
 958          * where it doesn't fully power down some parts.
 959          * Disable the asserts until the PHY has been fully
 960          * reset (ie. the power well has been disabled at
 961          * least once).
 962          */
 963         if (!dev_priv->chv_phy_assert[DPIO_PHY0])
 964                 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0) |
 965                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0) |
 966                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1) |
 967                                      PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1) |
 968                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0) |
 969                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1));
 970
 971         if (!dev_priv->chv_phy_assert[DPIO_PHY1])
 972                 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0) |
 973                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0) |
 974                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1));
 975
 976         if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) {
 977                 phy_status |= PHY_POWERGOOD(DPIO_PHY0);
 978
 979                 /* this assumes override is only used to enable lanes */
 980                 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0)) == 0)
 981                         phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0);
 982
 983                 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1)) == 0)
 984                         phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1);
 985
 986                 /* CL1 is on whenever anything is on in either channel */
 987                 if (BITS_SET(phy_control,
 988                              PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0) |
 989                              PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)))
 990                         phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0);
 991
 992                 /*
 993                  * The DPLLB check accounts for the pipe B + port A usage
 994                  * with CL2 powered up but all the lanes in the second channel
 995                  * powered down.
 996                  */
 997                 if (BITS_SET(phy_control,
 998                              PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)) &&
 999                     (I915_READ(DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0)
1000                         phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1);
1001
1002                 if (BITS_SET(phy_control,
1003                              PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH0)))
1004                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0);
1005                 if (BITS_SET(phy_control,
1006                              PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH0)))
1007                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1);
1008
1009                 if (BITS_SET(phy_control,
1010                              PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH1)))
1011                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0);
1012                 if (BITS_SET(phy_control,
1013                              PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH1)))
1014                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1);
1015         }
1016
1017         if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) {
1018                 phy_status |= PHY_POWERGOOD(DPIO_PHY1);
1019
1020                 /* this assumes override is only used to enable lanes */
1021                 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0)) == 0)
1022                         phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0);
1023
1024                 if (BITS_SET(phy_control,
1025                              PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0)))
1026                         phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0);
1027
1028                 if (BITS_SET(phy_control,
1029                              PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY1, DPIO_CH0)))
1030                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0);
1031                 if (BITS_SET(phy_control,
1032                              PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY1, DPIO_CH0)))
1033                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1);
1034         }
1035
1036         phy_status &= phy_status_mask;
1037
1038         /*
1039          * The PHY may be busy with some initial calibration and whatnot,
1040          * so the power state can take a while to actually change.
1041          */
1042         if (wait_for((tmp = I915_READ(DISPLAY_PHY_STATUS) & phy_status_mask) == phy_status, 10))
1043                 WARN(phy_status != tmp,
1044                      "Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n",
1045                      tmp, phy_status, dev_priv->chv_phy_control);
1046 }
1047
1048 #undef BITS_SET
1049
1050 static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
1051                                            struct i915_power_well *power_well)
1052 {
1053         enum dpio_phy phy;
1054         enum pipe pipe;
1055         uint32_t tmp;
1056
1057         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
1058                      power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
1059
1060         if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
1061                 pipe = PIPE_A;
1062                 phy = DPIO_PHY0;
1063         } else {
1064                 pipe = PIPE_C;
1065                 phy = DPIO_PHY1;
1066         }
1067
1068         /* since ref/cri clock was enabled */
1069         udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
1070         vlv_set_power_well(dev_priv, power_well, true);
1071
1072         /* Poll for phypwrgood signal */
1073         if (wait_for(I915_READ(DISPLAY_PHY_STATUS) & PHY_POWERGOOD(phy), 1))
1074                 DRM_ERROR("Display PHY %d is not power up\n", phy);
1075
1076         mutex_lock(&dev_priv->sb_lock);
1077
1078         /* Enable dynamic power down */
1079         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW28);
1080         tmp |= DPIO_DYNPWRDOWNEN_CH0 | DPIO_CL1POWERDOWNEN |
1081                 DPIO_SUS_CLK_CONFIG_GATE_CLKREQ;
1082         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW28, tmp);
1083
1084         if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
1085                 tmp = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW6_CH1);
1086                 tmp |= DPIO_DYNPWRDOWNEN_CH1;
1087                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW6_CH1, tmp);
1088         } else {
1089                 /*
1090                  * Force the non-existing CL2 off. BXT does this
1091                  * too, so maybe it saves some power even though
1092                  * CL2 doesn't exist?
1093                  */
1094                 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
1095                 tmp |= DPIO_CL2_LDOFUSE_PWRENB;
1096                 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, tmp);
1097         }
1098
1099         mutex_unlock(&dev_priv->sb_lock);
1100
1101         dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy);
1102         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1103
1104         DRM_DEBUG_KMS("Enabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
1105                       phy, dev_priv->chv_phy_control);
1106
1107         assert_chv_phy_status(dev_priv);
1108 }
1109
1110 static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
1111                                             struct i915_power_well *power_well)
1112 {
1113         enum dpio_phy phy;
1114
1115         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
1116                      power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
1117
1118         if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
1119                 phy = DPIO_PHY0;
1120                 assert_pll_disabled(dev_priv, PIPE_A);
1121                 assert_pll_disabled(dev_priv, PIPE_B);
1122         } else {
1123                 phy = DPIO_PHY1;
1124                 assert_pll_disabled(dev_priv, PIPE_C);
1125         }
1126
1127         dev_priv->chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy);
1128         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1129
1130         vlv_set_power_well(dev_priv, power_well, false);
1131
1132         DRM_DEBUG_KMS("Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
1133                       phy, dev_priv->chv_phy_control);
1134
1135         /* PHY is fully reset now, so we can enable the PHY state asserts */
1136         dev_priv->chv_phy_assert[phy] = true;
1137
1138         assert_chv_phy_status(dev_priv);
1139 }
1140
1141 static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1142                                      enum dpio_channel ch, bool override, unsigned int mask)
1143 {
1144         enum pipe pipe = phy == DPIO_PHY0 ? PIPE_A : PIPE_C;
1145         u32 reg, val, expected, actual;
1146
1147         /*
1148          * The BIOS can leave the PHY is some weird state
1149          * where it doesn't fully power down some parts.
1150          * Disable the asserts until the PHY has been fully
1151          * reset (ie. the power well has been disabled at
1152          * least once).
1153          */
1154         if (!dev_priv->chv_phy_assert[phy])
1155                 return;
1156
1157         if (ch == DPIO_CH0)
1158                 reg = _CHV_CMN_DW0_CH0;
1159         else
1160                 reg = _CHV_CMN_DW6_CH1;
1161
1162         mutex_lock(&dev_priv->sb_lock);
1163         val = vlv_dpio_read(dev_priv, pipe, reg);
1164         mutex_unlock(&dev_priv->sb_lock);
1165
1166         /*
1167          * This assumes !override is only used when the port is disabled.
1168          * All lanes should power down even without the override when
1169          * the port is disabled.
1170          */
1171         if (!override || mask == 0xf) {
1172                 expected = DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN;
1173                 /*
1174                  * If CH1 common lane is not active anymore
1175                  * (eg. for pipe B DPLL) the entire channel will
1176                  * shut down, which causes the common lane registers
1177                  * to read as 0. That means we can't actually check
1178                  * the lane power down status bits, but as the entire
1179                  * register reads as 0 it's a good indication that the
1180                  * channel is indeed entirely powered down.
1181                  */
1182                 if (ch == DPIO_CH1 && val == 0)
1183                         expected = 0;
1184         } else if (mask != 0x0) {
1185                 expected = DPIO_ANYDL_POWERDOWN;
1186         } else {
1187                 expected = 0;
1188         }
1189
1190         if (ch == DPIO_CH0)
1191                 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH0;
1192         else
1193                 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH1;
1194         actual &= DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN;
1195
1196         WARN(actual != expected,
1197              "Unexpected DPIO lane power down: all %d, any %d. Expected: all %d, any %d. (0x%x = 0x%08x)\n",
1198              !!(actual & DPIO_ALLDL_POWERDOWN), !!(actual & DPIO_ANYDL_POWERDOWN),
1199              !!(expected & DPIO_ALLDL_POWERDOWN), !!(expected & DPIO_ANYDL_POWERDOWN),
1200              reg, val);
1201 }
1202
1203 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1204                           enum dpio_channel ch, bool override)
1205 {
1206         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1207         bool was_override;
1208
1209         mutex_lock(&power_domains->lock);
1210
1211         was_override = dev_priv->chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1212
1213         if (override == was_override)
1214                 goto out;
1215
1216         if (override)
1217                 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1218         else
1219                 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1220
1221         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1222
1223         DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d (DPIO_PHY_CONTROL=0x%08x)\n",
1224                       phy, ch, dev_priv->chv_phy_control);
1225
1226         assert_chv_phy_status(dev_priv);
1227
1228 out:
1229         mutex_unlock(&power_domains->lock);
1230
1231         return was_override;
1232 }
1233
1234 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1235                              bool override, unsigned int mask)
1236 {
1237         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1238         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1239         enum dpio_phy phy = vlv_dport_to_phy(enc_to_dig_port(&encoder->base));
1240         enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
1241
1242         mutex_lock(&power_domains->lock);
1243
1244         dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch);
1245         dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch);
1246
1247         if (override)
1248                 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1249         else
1250                 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1251
1252         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1253
1254         DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d lanes 0x%x (PHY_CONTROL=0x%08x)\n",
1255                       phy, ch, mask, dev_priv->chv_phy_control);
1256
1257         assert_chv_phy_status(dev_priv);
1258
1259         assert_chv_phy_powergate(dev_priv, phy, ch, override, mask);
1260
1261         mutex_unlock(&power_domains->lock);
1262 }
1263
1264 static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv,
1265                                         struct i915_power_well *power_well)
1266 {
1267         enum pipe pipe = power_well->data;
1268         bool enabled;
1269         u32 state, ctrl;
1270
1271         mutex_lock(&dev_priv->rps.hw_lock);
1272
1273         state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe);
1274         /*
1275          * We only ever set the power-on and power-gate states, anything
1276          * else is unexpected.
1277          */
1278         WARN_ON(state != DP_SSS_PWR_ON(pipe) && state != DP_SSS_PWR_GATE(pipe));
1279         enabled = state == DP_SSS_PWR_ON(pipe);
1280
1281         /*
1282          * A transient state at this point would mean some unexpected party
1283          * is poking at the power controls too.
1284          */
1285         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe);
1286         WARN_ON(ctrl << 16 != state);
1287
1288         mutex_unlock(&dev_priv->rps.hw_lock);
1289
1290         return enabled;
1291 }
1292
1293 static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv,
1294                                     struct i915_power_well *power_well,
1295                                     bool enable)
1296 {
1297         enum pipe pipe = power_well->data;
1298         u32 state;
1299         u32 ctrl;
1300
1301         state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe);
1302
1303         mutex_lock(&dev_priv->rps.hw_lock);
1304
1305 #define COND \
1306         ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state)
1307
1308         if (COND)
1309                 goto out;
1310
1311         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
1312         ctrl &= ~DP_SSC_MASK(pipe);
1313         ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe);
1314         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl);
1315
1316         if (wait_for(COND, 100))
1317                 DRM_ERROR("timeout setting power well state %08x (%08x)\n",
1318                           state,
1319                           vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ));
1320
1321 #undef COND
1322
1323 out:
1324         mutex_unlock(&dev_priv->rps.hw_lock);
1325 }
1326
1327 static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv,
1328                                         struct i915_power_well *power_well)
1329 {
1330         WARN_ON_ONCE(power_well->data != PIPE_A);
1331
1332         chv_set_pipe_power_well(dev_priv, power_well, power_well->count > 0);
1333 }
1334
1335 static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv,
1336                                        struct i915_power_well *power_well)
1337 {
1338         WARN_ON_ONCE(power_well->data != PIPE_A);
1339
1340         chv_set_pipe_power_well(dev_priv, power_well, true);
1341
1342         vlv_display_power_well_init(dev_priv);
1343 }
1344
1345 static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv,
1346                                         struct i915_power_well *power_well)
1347 {
1348         WARN_ON_ONCE(power_well->data != PIPE_A);
1349
1350         vlv_display_power_well_deinit(dev_priv);
1351
1352         chv_set_pipe_power_well(dev_priv, power_well, false);
1353 }
1354
1355 /**
1356  * intel_display_power_get - grab a power domain reference
1357  * @dev_priv: i915 device instance
1358  * @domain: power domain to reference
1359  *
1360  * This function grabs a power domain reference for @domain and ensures that the
1361  * power domain and all its parents are powered up. Therefore users should only
1362  * grab a reference to the innermost power domain they need.
1363  *
1364  * Any power domain reference obtained by this function must have a symmetric
1365  * call to intel_display_power_put() to release the reference again.
1366  */
1367 void intel_display_power_get(struct drm_i915_private *dev_priv,
1368                              enum intel_display_power_domain domain)
1369 {
1370         struct i915_power_domains *power_domains;
1371         struct i915_power_well *power_well;
1372         int i;
1373
1374         intel_runtime_pm_get(dev_priv);
1375
1376         power_domains = &dev_priv->power_domains;
1377
1378         mutex_lock(&power_domains->lock);
1379
1380         for_each_power_well(i, power_well, BIT(domain), power_domains) {
1381                 if (!power_well->count++)
1382                         intel_power_well_enable(dev_priv, power_well);
1383         }
1384
1385         power_domains->domain_use_count[domain]++;
1386
1387         mutex_unlock(&power_domains->lock);
1388 }
1389
1390 /**
1391  * intel_display_power_put - release a power domain reference
1392  * @dev_priv: i915 device instance
1393  * @domain: power domain to reference
1394  *
1395  * This function drops the power domain reference obtained by
1396  * intel_display_power_get() and might power down the corresponding hardware
1397  * block right away if this is the last reference.
1398  */
1399 void intel_display_power_put(struct drm_i915_private *dev_priv,
1400                              enum intel_display_power_domain domain)
1401 {
1402         struct i915_power_domains *power_domains;
1403         struct i915_power_well *power_well;
1404         int i;
1405
1406         power_domains = &dev_priv->power_domains;
1407
1408         mutex_lock(&power_domains->lock);
1409
1410         WARN_ON(!power_domains->domain_use_count[domain]);
1411         power_domains->domain_use_count[domain]--;
1412
1413         for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
1414                 WARN_ON(!power_well->count);
1415
1416                 if (!--power_well->count)
1417                         intel_power_well_disable(dev_priv, power_well);
1418         }
1419
1420         mutex_unlock(&power_domains->lock);
1421
1422         intel_runtime_pm_put(dev_priv);
1423 }
1424
1425 #define HSW_ALWAYS_ON_POWER_DOMAINS (                   \
1426         BIT(POWER_DOMAIN_PIPE_A) |                      \
1427         BIT(POWER_DOMAIN_TRANSCODER_EDP) |              \
1428         BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) |          \
1429         BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) |          \
1430         BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) |          \
1431         BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |          \
1432         BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) |          \
1433         BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |          \
1434         BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) |          \
1435         BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) |          \
1436         BIT(POWER_DOMAIN_PORT_CRT) |                    \
1437         BIT(POWER_DOMAIN_PLLS) |                        \
1438         BIT(POWER_DOMAIN_AUX_A) |                       \
1439         BIT(POWER_DOMAIN_AUX_B) |                       \
1440         BIT(POWER_DOMAIN_AUX_C) |                       \
1441         BIT(POWER_DOMAIN_AUX_D) |                       \
1442         BIT(POWER_DOMAIN_INIT))
1443 #define HSW_DISPLAY_POWER_DOMAINS (                             \
1444         (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) |    \
1445         BIT(POWER_DOMAIN_INIT))
1446
1447 #define BDW_ALWAYS_ON_POWER_DOMAINS (                   \
1448         HSW_ALWAYS_ON_POWER_DOMAINS |                   \
1449         BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER))
1450 #define BDW_DISPLAY_POWER_DOMAINS (                             \
1451         (POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) |    \
1452         BIT(POWER_DOMAIN_INIT))
1453
1454 #define VLV_ALWAYS_ON_POWER_DOMAINS     BIT(POWER_DOMAIN_INIT)
1455 #define VLV_DISPLAY_POWER_DOMAINS       POWER_DOMAIN_MASK
1456
1457 #define VLV_DPIO_CMN_BC_POWER_DOMAINS (         \
1458         BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) |  \
1459         BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |  \
1460         BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) |  \
1461         BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |  \
1462         BIT(POWER_DOMAIN_PORT_CRT) |            \
1463         BIT(POWER_DOMAIN_AUX_B) |               \
1464         BIT(POWER_DOMAIN_AUX_C) |               \
1465         BIT(POWER_DOMAIN_INIT))
1466
1467 #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS (  \
1468         BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) |  \
1469         BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |  \
1470         BIT(POWER_DOMAIN_AUX_B) |               \
1471         BIT(POWER_DOMAIN_INIT))
1472
1473 #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS (  \
1474         BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |  \
1475         BIT(POWER_DOMAIN_AUX_B) |               \
1476         BIT(POWER_DOMAIN_INIT))
1477
1478 #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS (  \
1479         BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) |  \
1480         BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |  \
1481         BIT(POWER_DOMAIN_AUX_C) |               \
1482         BIT(POWER_DOMAIN_INIT))
1483
1484 #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS (  \
1485         BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |  \
1486         BIT(POWER_DOMAIN_AUX_C) |               \
1487         BIT(POWER_DOMAIN_INIT))
1488
1489 #define CHV_DPIO_CMN_BC_POWER_DOMAINS (         \
1490         BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) |  \
1491         BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |  \
1492         BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) |  \
1493         BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |  \
1494         BIT(POWER_DOMAIN_AUX_B) |               \
1495         BIT(POWER_DOMAIN_AUX_C) |               \
1496         BIT(POWER_DOMAIN_INIT))
1497
1498 #define CHV_DPIO_CMN_D_POWER_DOMAINS (          \
1499         BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) |  \
1500         BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) |  \
1501         BIT(POWER_DOMAIN_AUX_D) |               \
1502         BIT(POWER_DOMAIN_INIT))
1503
1504 static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
1505         .sync_hw = i9xx_always_on_power_well_noop,
1506         .enable = i9xx_always_on_power_well_noop,
1507         .disable = i9xx_always_on_power_well_noop,
1508         .is_enabled = i9xx_always_on_power_well_enabled,
1509 };
1510
1511 static const struct i915_power_well_ops chv_pipe_power_well_ops = {
1512         .sync_hw = chv_pipe_power_well_sync_hw,
1513         .enable = chv_pipe_power_well_enable,
1514         .disable = chv_pipe_power_well_disable,
1515         .is_enabled = chv_pipe_power_well_enabled,
1516 };
1517
1518 static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = {
1519         .sync_hw = vlv_power_well_sync_hw,
1520         .enable = chv_dpio_cmn_power_well_enable,
1521         .disable = chv_dpio_cmn_power_well_disable,
1522         .is_enabled = vlv_power_well_enabled,
1523 };
1524
1525 static struct i915_power_well i9xx_always_on_power_well[] = {
1526         {
1527                 .name = "always-on",
1528                 .always_on = 1,
1529                 .domains = POWER_DOMAIN_MASK,
1530                 .ops = &i9xx_always_on_power_well_ops,
1531         },
1532 };
1533
1534 static const struct i915_power_well_ops hsw_power_well_ops = {
1535         .sync_hw = hsw_power_well_sync_hw,
1536         .enable = hsw_power_well_enable,
1537         .disable = hsw_power_well_disable,
1538         .is_enabled = hsw_power_well_enabled,
1539 };
1540
1541 static const struct i915_power_well_ops skl_power_well_ops = {
1542         .sync_hw = skl_power_well_sync_hw,
1543         .enable = skl_power_well_enable,
1544         .disable = skl_power_well_disable,
1545         .is_enabled = skl_power_well_enabled,
1546 };
1547
1548 static struct i915_power_well hsw_power_wells[] = {
1549         {
1550                 .name = "always-on",
1551                 .always_on = 1,
1552                 .domains = HSW_ALWAYS_ON_POWER_DOMAINS,
1553                 .ops = &i9xx_always_on_power_well_ops,
1554         },
1555         {
1556                 .name = "display",
1557                 .domains = HSW_DISPLAY_POWER_DOMAINS,
1558                 .ops = &hsw_power_well_ops,
1559         },
1560 };
1561
1562 static struct i915_power_well bdw_power_wells[] = {
1563         {
1564                 .name = "always-on",
1565                 .always_on = 1,
1566                 .domains = BDW_ALWAYS_ON_POWER_DOMAINS,
1567                 .ops = &i9xx_always_on_power_well_ops,
1568         },
1569         {
1570                 .name = "display",
1571                 .domains = BDW_DISPLAY_POWER_DOMAINS,
1572                 .ops = &hsw_power_well_ops,
1573         },
1574 };
1575
1576 static const struct i915_power_well_ops vlv_display_power_well_ops = {
1577         .sync_hw = vlv_power_well_sync_hw,
1578         .enable = vlv_display_power_well_enable,
1579         .disable = vlv_display_power_well_disable,
1580         .is_enabled = vlv_power_well_enabled,
1581 };
1582
1583 static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = {
1584         .sync_hw = vlv_power_well_sync_hw,
1585         .enable = vlv_dpio_cmn_power_well_enable,
1586         .disable = vlv_dpio_cmn_power_well_disable,
1587         .is_enabled = vlv_power_well_enabled,
1588 };
1589
1590 static const struct i915_power_well_ops vlv_dpio_power_well_ops = {
1591         .sync_hw = vlv_power_well_sync_hw,
1592         .enable = vlv_power_well_enable,
1593         .disable = vlv_power_well_disable,
1594         .is_enabled = vlv_power_well_enabled,
1595 };
1596
1597 static struct i915_power_well vlv_power_wells[] = {
1598         {
1599                 .name = "always-on",
1600                 .always_on = 1,
1601                 .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
1602                 .ops = &i9xx_always_on_power_well_ops,
1603                 .data = PUNIT_POWER_WELL_ALWAYS_ON,
1604         },
1605         {
1606                 .name = "display",
1607                 .domains = VLV_DISPLAY_POWER_DOMAINS,
1608                 .data = PUNIT_POWER_WELL_DISP2D,
1609                 .ops = &vlv_display_power_well_ops,
1610         },
1611         {
1612                 .name = "dpio-tx-b-01",
1613                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1614                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1615                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1616                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1617                 .ops = &vlv_dpio_power_well_ops,
1618                 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
1619         },
1620         {
1621                 .name = "dpio-tx-b-23",
1622                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1623                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1624                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1625                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1626                 .ops = &vlv_dpio_power_well_ops,
1627                 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
1628         },
1629         {
1630                 .name = "dpio-tx-c-01",
1631                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1632                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1633                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1634                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1635                 .ops = &vlv_dpio_power_well_ops,
1636                 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
1637         },
1638         {
1639                 .name = "dpio-tx-c-23",
1640                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1641                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1642                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1643                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1644                 .ops = &vlv_dpio_power_well_ops,
1645                 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
1646         },
1647         {
1648                 .name = "dpio-common",
1649                 .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,
1650                 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
1651                 .ops = &vlv_dpio_cmn_power_well_ops,
1652         },
1653 };
1654
1655 static struct i915_power_well chv_power_wells[] = {
1656         {
1657                 .name = "always-on",
1658                 .always_on = 1,
1659                 .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
1660                 .ops = &i9xx_always_on_power_well_ops,
1661         },
1662         {
1663                 .name = "display",
1664                 /*
1665                  * Pipe A power well is the new disp2d well. Pipe B and C
1666                  * power wells don't actually exist. Pipe A power well is
1667                  * required for any pipe to work.
1668                  */
1669                 .domains = VLV_DISPLAY_POWER_DOMAINS,
1670                 .data = PIPE_A,
1671                 .ops = &chv_pipe_power_well_ops,
1672         },
1673         {
1674                 .name = "dpio-common-bc",
1675                 .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS,
1676                 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
1677                 .ops = &chv_dpio_cmn_power_well_ops,
1678         },
1679         {
1680                 .name = "dpio-common-d",
1681                 .domains = CHV_DPIO_CMN_D_POWER_DOMAINS,
1682                 .data = PUNIT_POWER_WELL_DPIO_CMN_D,
1683                 .ops = &chv_dpio_cmn_power_well_ops,
1684         },
1685 };
1686
1687 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
1688                                     int power_well_id)
1689 {
1690         struct i915_power_well *power_well;
1691         bool ret;
1692
1693         power_well = lookup_power_well(dev_priv, power_well_id);
1694         ret = power_well->ops->is_enabled(dev_priv, power_well);
1695
1696         return ret;
1697 }
1698
1699 static struct i915_power_well skl_power_wells[] = {
1700         {
1701                 .name = "always-on",
1702                 .always_on = 1,
1703                 .domains = SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS,
1704                 .ops = &i9xx_always_on_power_well_ops,
1705                 .data = SKL_DISP_PW_ALWAYS_ON,
1706         },
1707         {
1708                 .name = "power well 1",
1709                 /* Handled by the DMC firmware */
1710                 .domains = 0,
1711                 .ops = &skl_power_well_ops,
1712                 .data = SKL_DISP_PW_1,
1713         },
1714         {
1715                 .name = "MISC IO power well",
1716                 /* Handled by the DMC firmware */
1717                 .domains = 0,
1718                 .ops = &skl_power_well_ops,
1719                 .data = SKL_DISP_PW_MISC_IO,
1720         },
1721         {
1722                 .name = "power well 2",
1723                 .domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS,
1724                 .ops = &skl_power_well_ops,
1725                 .data = SKL_DISP_PW_2,
1726         },
1727         {
1728                 .name = "DDI A/E power well",
1729                 .domains = SKL_DISPLAY_DDI_A_E_POWER_DOMAINS,
1730                 .ops = &skl_power_well_ops,
1731                 .data = SKL_DISP_PW_DDI_A_E,
1732         },
1733         {
1734                 .name = "DDI B power well",
1735                 .domains = SKL_DISPLAY_DDI_B_POWER_DOMAINS,
1736                 .ops = &skl_power_well_ops,
1737                 .data = SKL_DISP_PW_DDI_B,
1738         },
1739         {
1740                 .name = "DDI C power well",
1741                 .domains = SKL_DISPLAY_DDI_C_POWER_DOMAINS,
1742                 .ops = &skl_power_well_ops,
1743                 .data = SKL_DISP_PW_DDI_C,
1744         },
1745         {
1746                 .name = "DDI D power well",
1747                 .domains = SKL_DISPLAY_DDI_D_POWER_DOMAINS,
1748                 .ops = &skl_power_well_ops,
1749                 .data = SKL_DISP_PW_DDI_D,
1750         },
1751 };
1752
1753 void skl_pw1_misc_io_init(struct drm_i915_private *dev_priv)
1754 {
1755         struct i915_power_well *well;
1756
1757         if (!IS_SKYLAKE(dev_priv))
1758                 return;
1759
1760         well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
1761         intel_power_well_enable(dev_priv, well);
1762
1763         well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);
1764         intel_power_well_enable(dev_priv, well);
1765 }
1766
1767 void skl_pw1_misc_io_fini(struct drm_i915_private *dev_priv)
1768 {
1769         struct i915_power_well *well;
1770
1771         if (!IS_SKYLAKE(dev_priv))
1772                 return;
1773
1774         well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
1775         intel_power_well_disable(dev_priv, well);
1776
1777         well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);
1778         intel_power_well_disable(dev_priv, well);
1779 }
1780
1781 static struct i915_power_well bxt_power_wells[] = {
1782         {
1783                 .name = "always-on",
1784                 .always_on = 1,
1785                 .domains = BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS,
1786                 .ops = &i9xx_always_on_power_well_ops,
1787         },
1788         {
1789                 .name = "power well 1",
1790                 .domains = BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS,
1791                 .ops = &skl_power_well_ops,
1792                 .data = SKL_DISP_PW_1,
1793         },
1794         {
1795                 .name = "power well 2",
1796                 .domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS,
1797                 .ops = &skl_power_well_ops,
1798                 .data = SKL_DISP_PW_2,
1799         }
1800 };
1801
1802 #define set_power_wells(power_domains, __power_wells) ({                \
1803         (power_domains)->power_wells = (__power_wells);                 \
1804         (power_domains)->power_well_count = ARRAY_SIZE(__power_wells);  \
1805 })
1806
1807 /**
1808  * intel_power_domains_init - initializes the power domain structures
1809  * @dev_priv: i915 device instance
1810  *
1811  * Initializes the power domain structures for @dev_priv depending upon the
1812  * supported platform.
1813  */
1814 int intel_power_domains_init(struct drm_i915_private *dev_priv)
1815 {
1816         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1817
1818         mutex_init(&power_domains->lock);
1819
1820         /*
1821          * The enabling order will be from lower to higher indexed wells,
1822          * the disabling order is reversed.
1823          */
1824         if (IS_HASWELL(dev_priv->dev)) {
1825                 set_power_wells(power_domains, hsw_power_wells);
1826         } else if (IS_BROADWELL(dev_priv->dev)) {
1827                 set_power_wells(power_domains, bdw_power_wells);
1828         } else if (IS_SKYLAKE(dev_priv->dev) || IS_KABYLAKE(dev_priv->dev)) {
1829                 set_power_wells(power_domains, skl_power_wells);
1830         } else if (IS_BROXTON(dev_priv->dev)) {
1831                 set_power_wells(power_domains, bxt_power_wells);
1832         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1833                 set_power_wells(power_domains, chv_power_wells);
1834         } else if (IS_VALLEYVIEW(dev_priv->dev)) {
1835                 set_power_wells(power_domains, vlv_power_wells);
1836         } else {
1837                 set_power_wells(power_domains, i9xx_always_on_power_well);
1838         }
1839
1840         return 0;
1841 }
1842
1843 /**
1844  * intel_power_domains_fini - finalizes the power domain structures
1845  * @dev_priv: i915 device instance
1846  *
1847  * Finalizes the power domain structures for @dev_priv depending upon the
1848  * supported platform. This function also disables runtime pm and ensures that
1849  * the device stays powered up so that the driver can be reloaded.
1850  */
1851 void intel_power_domains_fini(struct drm_i915_private *dev_priv)
1852 {
1853         /* The i915.ko module is still not prepared to be loaded when
1854          * the power well is not enabled, so just enable it in case
1855          * we're going to unload/reload. */
1856         intel_display_set_init_power(dev_priv, true);
1857
1858         /* Remove the refcount we took to keep power well support disabled. */
1859         if (!i915.disable_power_well)
1860                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
1861 }
1862
1863 static void intel_power_domains_sync_hw(struct drm_i915_private *dev_priv)
1864 {
1865         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1866         struct i915_power_well *power_well;
1867         int i;
1868
1869         mutex_lock(&power_domains->lock);
1870         for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
1871                 power_well->ops->sync_hw(dev_priv, power_well);
1872                 power_well->hw_enabled = power_well->ops->is_enabled(dev_priv,
1873                                                                      power_well);
1874         }
1875         mutex_unlock(&power_domains->lock);
1876 }
1877
1878 static void skl_display_core_init(struct drm_i915_private *dev_priv,
1879                                   bool resume)
1880 {
1881         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1882         uint32_t val;
1883
1884         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
1885
1886         /* enable PCH reset handshake */
1887         val = I915_READ(HSW_NDE_RSTWRN_OPT);
1888         I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
1889
1890         /* enable PG1 and Misc I/O */
1891         mutex_lock(&power_domains->lock);
1892         skl_pw1_misc_io_init(dev_priv);
1893         mutex_unlock(&power_domains->lock);
1894
1895         if (!resume)
1896                 return;
1897
1898         skl_init_cdclk(dev_priv);
1899
1900         if (dev_priv->csr.dmc_payload)
1901                 intel_csr_load_program(dev_priv);
1902 }
1903
1904 static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
1905 {
1906         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1907
1908         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
1909
1910         skl_uninit_cdclk(dev_priv);
1911
1912         /* The spec doesn't call for removing the reset handshake flag */
1913         /* disable PG1 and Misc I/O */
1914         mutex_lock(&power_domains->lock);
1915         skl_pw1_misc_io_fini(dev_priv);
1916         mutex_unlock(&power_domains->lock);
1917 }
1918
1919 static void chv_phy_control_init(struct drm_i915_private *dev_priv)
1920 {
1921         struct i915_power_well *cmn_bc =
1922                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
1923         struct i915_power_well *cmn_d =
1924                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D);
1925
1926         /*
1927          * DISPLAY_PHY_CONTROL can get corrupted if read. As a
1928          * workaround never ever read DISPLAY_PHY_CONTROL, and
1929          * instead maintain a shadow copy ourselves. Use the actual
1930          * power well state and lane status to reconstruct the
1931          * expected initial value.
1932          */
1933         dev_priv->chv_phy_control =
1934                 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY0) |
1935                 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY1) |
1936                 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH0) |
1937                 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH1) |
1938                 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY1, DPIO_CH0);
1939
1940         /*
1941          * If all lanes are disabled we leave the override disabled
1942          * with all power down bits cleared to match the state we
1943          * would use after disabling the port. Otherwise enable the
1944          * override and set the lane powerdown bits accding to the
1945          * current lane status.
1946          */
1947         if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) {
1948                 uint32_t status = I915_READ(DPLL(PIPE_A));
1949                 unsigned int mask;
1950
1951                 mask = status & DPLL_PORTB_READY_MASK;
1952                 if (mask == 0xf)
1953                         mask = 0x0;
1954                 else
1955                         dev_priv->chv_phy_control |=
1956                                 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0);
1957
1958                 dev_priv->chv_phy_control |=
1959                         PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH0);
1960
1961                 mask = (status & DPLL_PORTC_READY_MASK) >> 4;
1962                 if (mask == 0xf)
1963                         mask = 0x0;
1964                 else
1965                         dev_priv->chv_phy_control |=
1966                                 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1);
1967
1968                 dev_priv->chv_phy_control |=
1969                         PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH1);
1970
1971                 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0);
1972
1973                 dev_priv->chv_phy_assert[DPIO_PHY0] = false;
1974         } else {
1975                 dev_priv->chv_phy_assert[DPIO_PHY0] = true;
1976         }
1977
1978         if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) {
1979                 uint32_t status = I915_READ(DPIO_PHY_STATUS);
1980                 unsigned int mask;
1981
1982                 mask = status & DPLL_PORTD_READY_MASK;
1983
1984                 if (mask == 0xf)
1985                         mask = 0x0;
1986                 else
1987                         dev_priv->chv_phy_control |=
1988                                 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0);
1989
1990                 dev_priv->chv_phy_control |=
1991                         PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY1, DPIO_CH0);
1992
1993                 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1);
1994
1995                 dev_priv->chv_phy_assert[DPIO_PHY1] = false;
1996         } else {
1997                 dev_priv->chv_phy_assert[DPIO_PHY1] = true;
1998         }
1999
2000         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
2001
2002         DRM_DEBUG_KMS("Initial PHY_CONTROL=0x%08x\n",
2003                       dev_priv->chv_phy_control);
2004 }
2005
2006 static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv)
2007 {
2008         struct i915_power_well *cmn =
2009                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
2010         struct i915_power_well *disp2d =
2011                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D);
2012
2013         /* If the display might be already active skip this */
2014         if (cmn->ops->is_enabled(dev_priv, cmn) &&
2015             disp2d->ops->is_enabled(dev_priv, disp2d) &&
2016             I915_READ(DPIO_CTL) & DPIO_CMNRST)
2017                 return;
2018
2019         DRM_DEBUG_KMS("toggling display PHY side reset\n");
2020
2021         /* cmnlane needs DPLL registers */
2022         disp2d->ops->enable(dev_priv, disp2d);
2023
2024         /*
2025          * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx:
2026          * Need to assert and de-assert PHY SB reset by gating the
2027          * common lane power, then un-gating it.
2028          * Simply ungating isn't enough to reset the PHY enough to get
2029          * ports and lanes running.
2030          */
2031         cmn->ops->disable(dev_priv, cmn);
2032 }
2033
2034 /**
2035  * intel_power_domains_init_hw - initialize hardware power domain state
2036  * @dev_priv: i915 device instance
2037  *
2038  * This function initializes the hardware power domain state and enables all
2039  * power domains using intel_display_set_init_power().
2040  */
2041 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume)
2042 {
2043         struct drm_device *dev = dev_priv->dev;
2044         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2045
2046         power_domains->initializing = true;
2047
2048         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
2049                 skl_display_core_init(dev_priv, resume);
2050         } else if (IS_CHERRYVIEW(dev)) {
2051                 mutex_lock(&power_domains->lock);
2052                 chv_phy_control_init(dev_priv);
2053                 mutex_unlock(&power_domains->lock);
2054         } else if (IS_VALLEYVIEW(dev)) {
2055                 mutex_lock(&power_domains->lock);
2056                 vlv_cmnlane_wa(dev_priv);
2057                 mutex_unlock(&power_domains->lock);
2058         }
2059
2060         /* For now, we need the power well to be always enabled. */
2061         intel_display_set_init_power(dev_priv, true);
2062         /* Disable power support if the user asked so. */
2063         if (!i915.disable_power_well)
2064                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
2065         intel_power_domains_sync_hw(dev_priv);
2066         power_domains->initializing = false;
2067 }
2068
2069 /**
2070  * intel_power_domains_suspend - suspend power domain state
2071  * @dev_priv: i915 device instance
2072  *
2073  * This function prepares the hardware power domain state before entering
2074  * system suspend. It must be paired with intel_power_domains_init_hw().
2075  */
2076 void intel_power_domains_suspend(struct drm_i915_private *dev_priv)
2077 {
2078         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
2079                 skl_display_core_uninit(dev_priv);
2080
2081         /*
2082          * Even if power well support was disabled we still want to disable
2083          * power wells while we are system suspended.
2084          */
2085         if (!i915.disable_power_well)
2086                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
2087 }
2088
2089 /**
2090  * intel_aux_display_runtime_get - grab an auxiliary power domain reference
2091  * @dev_priv: i915 device instance
2092  *
2093  * This function grabs a power domain reference for the auxiliary power domain
2094  * (for access to the GMBUS and DP AUX blocks) and ensures that it and all its
2095  * parents are powered up. Therefore users should only grab a reference to the
2096  * innermost power domain they need.
2097  *
2098  * Any power domain reference obtained by this function must have a symmetric
2099  * call to intel_aux_display_runtime_put() to release the reference again.
2100  */
2101 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv)
2102 {
2103         intel_runtime_pm_get(dev_priv);
2104 }
2105
2106 /**
2107  * intel_aux_display_runtime_put - release an auxiliary power domain reference
2108  * @dev_priv: i915 device instance
2109  *
2110  * This function drops the auxiliary power domain reference obtained by
2111  * intel_aux_display_runtime_get() and might power down the corresponding
2112  * hardware block right away if this is the last reference.
2113  */
2114 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv)
2115 {
2116         intel_runtime_pm_put(dev_priv);
2117 }
2118
2119 /**
2120  * intel_runtime_pm_get - grab a runtime pm reference
2121  * @dev_priv: i915 device instance
2122  *
2123  * This function grabs a device-level runtime pm reference (mostly used for GEM
2124  * code to ensure the GTT or GT is on) and ensures that it is powered up.
2125  *
2126  * Any runtime pm reference obtained by this function must have a symmetric
2127  * call to intel_runtime_pm_put() to release the reference again.
2128  */
2129 void intel_runtime_pm_get(struct drm_i915_private *dev_priv)
2130 {
2131         struct drm_device *dev = dev_priv->dev;
2132         struct device *device = &dev->pdev->dev;
2133
2134         if (!HAS_RUNTIME_PM(dev))
2135                 return;
2136
2137         pm_runtime_get_sync(device);
2138         WARN(dev_priv->pm.suspended, "Device still suspended.\n");
2139 }
2140
2141 /**
2142  * intel_runtime_pm_get_noresume - grab a runtime pm reference
2143  * @dev_priv: i915 device instance
2144  *
2145  * This function grabs a device-level runtime pm reference (mostly used for GEM
2146  * code to ensure the GTT or GT is on).
2147  *
2148  * It will _not_ power up the device but instead only check that it's powered
2149  * on.  Therefore it is only valid to call this functions from contexts where
2150  * the device is known to be powered up and where trying to power it up would
2151  * result in hilarity and deadlocks. That pretty much means only the system
2152  * suspend/resume code where this is used to grab runtime pm references for
2153  * delayed setup down in work items.
2154  *
2155  * Any runtime pm reference obtained by this function must have a symmetric
2156  * call to intel_runtime_pm_put() to release the reference again.
2157  */
2158 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv)
2159 {
2160         struct drm_device *dev = dev_priv->dev;
2161         struct device *device = &dev->pdev->dev;
2162
2163         if (!HAS_RUNTIME_PM(dev))
2164                 return;
2165
2166         WARN(dev_priv->pm.suspended, "Getting nosync-ref while suspended.\n");
2167         pm_runtime_get_noresume(device);
2168 }
2169
2170 /**
2171  * intel_runtime_pm_put - release a runtime pm reference
2172  * @dev_priv: i915 device instance
2173  *
2174  * This function drops the device-level runtime pm reference obtained by
2175  * intel_runtime_pm_get() and might power down the corresponding
2176  * hardware block right away if this is the last reference.
2177  */
2178 void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
2179 {
2180         struct drm_device *dev = dev_priv->dev;
2181         struct device *device = &dev->pdev->dev;
2182
2183         if (!HAS_RUNTIME_PM(dev))
2184                 return;
2185
2186         pm_runtime_mark_last_busy(device);
2187         pm_runtime_put_autosuspend(device);
2188 }
2189
2190 /**
2191  * intel_runtime_pm_enable - enable runtime pm
2192  * @dev_priv: i915 device instance
2193  *
2194  * This function enables runtime pm at the end of the driver load sequence.
2195  *
2196  * Note that this function does currently not enable runtime pm for the
2197  * subordinate display power domains. That is only done on the first modeset
2198  * using intel_display_set_init_power().
2199  */
2200 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv)
2201 {
2202         struct drm_device *dev = dev_priv->dev;
2203         struct device *device = &dev->pdev->dev;
2204
2205         if (!HAS_RUNTIME_PM(dev))
2206                 return;
2207
2208         /*
2209          * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
2210          * requirement.
2211          */
2212         if (!intel_enable_rc6(dev)) {
2213                 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
2214                 return;
2215         }
2216
2217         pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */
2218         pm_runtime_mark_last_busy(device);
2219         pm_runtime_use_autosuspend(device);
2220
2221         pm_runtime_put_autosuspend(device);
2222 }
2223