drivers/gpu/drm/i915/intel_runtime_pm.c

   1 /*
   2  * Copyright © 2012-2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *    Daniel Vetter <daniel.vetter@ffwll.ch>
  26  *
  27  */
  28
  29 #include <linux/pm_runtime.h>
  30 #include <linux/vgaarb.h>
  31
  32 #include "i915_drv.h"
  33 #include "intel_drv.h"
  34
  35 /**
  36  * DOC: runtime pm
  37  *
  38  * The i915 driver supports dynamic enabling and disabling of entire hardware
  39  * blocks at runtime. This is especially important on the display side where
  40  * software is supposed to control many power gates manually on recent hardware,
  41  * since on the GT side a lot of the power management is done by the hardware.
  42  * But even there some manual control at the device level is required.
  43  *
  44  * Since i915 supports a diverse set of platforms with a unified codebase and
  45  * hardware engineers just love to shuffle functionality around between power
  46  * domains there's a sizeable amount of indirection required. This file provides
  47  * generic functions to the driver for grabbing and releasing references for
  48  * abstract power domains. It then maps those to the actual power wells
  49  * present for a given platform.
  50  */
  51
  52 #define for_each_power_well(i, power_well, domain_mask, power_domains)  \
  53         for (i = 0;                                                     \
  54              i < (power_domains)->power_well_count &&                   \
  55                  ((power_well) = &(power_domains)->power_wells[i]);     \
  56              i++)                                                       \
  57                 for_each_if ((power_well)->domains & (domain_mask))
  58
  59 #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
  60         for (i = (power_domains)->power_well_count - 1;                  \
  61              i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
  62              i--)                                                        \
  63                 for_each_if ((power_well)->domains & (domain_mask))
  64
  65 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
  66                                     int power_well_id);
  67
  68 const char *
  69 intel_display_power_domain_str(enum intel_display_power_domain domain)
  70 {
  71         switch (domain) {
  72         case POWER_DOMAIN_PIPE_A:
  73                 return "PIPE_A";
  74         case POWER_DOMAIN_PIPE_B:
  75                 return "PIPE_B";
  76         case POWER_DOMAIN_PIPE_C:
  77                 return "PIPE_C";
  78         case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
  79                 return "PIPE_A_PANEL_FITTER";
  80         case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
  81                 return "PIPE_B_PANEL_FITTER";
  82         case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
  83                 return "PIPE_C_PANEL_FITTER";
  84         case POWER_DOMAIN_TRANSCODER_A:
  85                 return "TRANSCODER_A";
  86         case POWER_DOMAIN_TRANSCODER_B:
  87                 return "TRANSCODER_B";
  88         case POWER_DOMAIN_TRANSCODER_C:
  89                 return "TRANSCODER_C";
  90         case POWER_DOMAIN_TRANSCODER_EDP:
  91                 return "TRANSCODER_EDP";
  92         case POWER_DOMAIN_PORT_DDI_A_LANES:
  93                 return "PORT_DDI_A_LANES";
  94         case POWER_DOMAIN_PORT_DDI_B_LANES:
  95                 return "PORT_DDI_B_LANES";
  96         case POWER_DOMAIN_PORT_DDI_C_LANES:
  97                 return "PORT_DDI_C_LANES";
  98         case POWER_DOMAIN_PORT_DDI_D_LANES:
  99                 return "PORT_DDI_D_LANES";
 100         case POWER_DOMAIN_PORT_DDI_E_LANES:
 101                 return "PORT_DDI_E_LANES";
 102         case POWER_DOMAIN_PORT_DSI:
 103                 return "PORT_DSI";
 104         case POWER_DOMAIN_PORT_CRT:
 105                 return "PORT_CRT";
 106         case POWER_DOMAIN_PORT_OTHER:
 107                 return "PORT_OTHER";
 108         case POWER_DOMAIN_VGA:
 109                 return "VGA";
 110         case POWER_DOMAIN_AUDIO:
 111                 return "AUDIO";
 112         case POWER_DOMAIN_PLLS:
 113                 return "PLLS";
 114         case POWER_DOMAIN_AUX_A:
 115                 return "AUX_A";
 116         case POWER_DOMAIN_AUX_B:
 117                 return "AUX_B";
 118         case POWER_DOMAIN_AUX_C:
 119                 return "AUX_C";
 120         case POWER_DOMAIN_AUX_D:
 121                 return "AUX_D";
 122         case POWER_DOMAIN_GMBUS:
 123                 return "GMBUS";
 124         case POWER_DOMAIN_INIT:
 125                 return "INIT";
 126         case POWER_DOMAIN_MODESET:
 127                 return "MODESET";
 128         default:
 129                 MISSING_CASE(domain);
 130                 return "?";
 131         }
 132 }
 133
 134 static void intel_power_well_enable(struct drm_i915_private *dev_priv,
 135                                     struct i915_power_well *power_well)
 136 {
 137         DRM_DEBUG_KMS("enabling %s\n", power_well->name);
 138         power_well->ops->enable(dev_priv, power_well);
 139         power_well->hw_enabled = true;
 140 }
 141
 142 static void intel_power_well_disable(struct drm_i915_private *dev_priv,
 143                                      struct i915_power_well *power_well)
 144 {
 145         DRM_DEBUG_KMS("disabling %s\n", power_well->name);
 146         power_well->hw_enabled = false;
 147         power_well->ops->disable(dev_priv, power_well);
 148 }
 149
 150 /*
 151  * We should only use the power well if we explicitly asked the hardware to
 152  * enable it, so check if it's enabled and also check if we've requested it to
 153  * be enabled.
 154  */
 155 static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
 156                                    struct i915_power_well *power_well)
 157 {
 158         return I915_READ(HSW_PWR_WELL_DRIVER) ==
 159                      (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
 160 }
 161
 162 /**
 163  * __intel_display_power_is_enabled - unlocked check for a power domain
 164  * @dev_priv: i915 device instance
 165  * @domain: power domain to check
 166  *
 167  * This is the unlocked version of intel_display_power_is_enabled() and should
 168  * only be used from error capture and recovery code where deadlocks are
 169  * possible.
 170  *
 171  * Returns:
 172  * True when the power domain is enabled, false otherwise.
 173  */
 174 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
 175                                       enum intel_display_power_domain domain)
 176 {
 177         struct i915_power_domains *power_domains;
 178         struct i915_power_well *power_well;
 179         bool is_enabled;
 180         int i;
 181
 182         if (dev_priv->pm.suspended)
 183                 return false;
 184
 185         power_domains = &dev_priv->power_domains;
 186
 187         is_enabled = true;
 188
 189         for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
 190                 if (power_well->always_on)
 191                         continue;
 192
 193                 if (!power_well->hw_enabled) {
 194                         is_enabled = false;
 195                         break;
 196                 }
 197         }
 198
 199         return is_enabled;
 200 }
 201
 202 /**
 203  * intel_display_power_is_enabled - check for a power domain
 204  * @dev_priv: i915 device instance
 205  * @domain: power domain to check
 206  *
 207  * This function can be used to check the hw power domain state. It is mostly
 208  * used in hardware state readout functions. Everywhere else code should rely
 209  * upon explicit power domain reference counting to ensure that the hardware
 210  * block is powered up before accessing it.
 211  *
 212  * Callers must hold the relevant modesetting locks to ensure that concurrent
 213  * threads can't disable the power well while the caller tries to read a few
 214  * registers.
 215  *
 216  * Returns:
 217  * True when the power domain is enabled, false otherwise.
 218  */
 219 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
 220                                     enum intel_display_power_domain domain)
 221 {
 222         struct i915_power_domains *power_domains;
 223         bool ret;
 224
 225         power_domains = &dev_priv->power_domains;
 226
 227         mutex_lock(&power_domains->lock);
 228         ret = __intel_display_power_is_enabled(dev_priv, domain);
 229         mutex_unlock(&power_domains->lock);
 230
 231         return ret;
 232 }
 233
 234 /**
 235  * intel_display_set_init_power - set the initial power domain state
 236  * @dev_priv: i915 device instance
 237  * @enable: whether to enable or disable the initial power domain state
 238  *
 239  * For simplicity our driver load/unload and system suspend/resume code assumes
 240  * that all power domains are always enabled. This functions controls the state
 241  * of this little hack. While the initial power domain state is enabled runtime
 242  * pm is effectively disabled.
 243  */
 244 void intel_display_set_init_power(struct drm_i915_private *dev_priv,
 245                                   bool enable)
 246 {
 247         if (dev_priv->power_domains.init_power_on == enable)
 248                 return;
 249
 250         if (enable)
 251                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
 252         else
 253                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
 254
 255         dev_priv->power_domains.init_power_on = enable;
 256 }
 257
 258 /*
 259  * Starting with Haswell, we have a "Power Down Well" that can be turned off
 260  * when not needed anymore. We have 4 registers that can request the power well
 261  * to be enabled, and it will only be disabled if none of the registers is
 262  * requesting it to be enabled.
 263  */
 264 static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
 265 {
 266         struct drm_device *dev = dev_priv->dev;
 267
 268         /*
 269          * After we re-enable the power well, if we touch VGA register 0x3d5
 270          * we'll get unclaimed register interrupts. This stops after we write
 271          * anything to the VGA MSR register. The vgacon module uses this
 272          * register all the time, so if we unbind our driver and, as a
 273          * consequence, bind vgacon, we'll get stuck in an infinite loop at
 274          * console_unlock(). So make here we touch the VGA MSR register, making
 275          * sure vgacon can keep working normally without triggering interrupts
 276          * and error messages.
 277          */
 278         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
 279         outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
 280         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
 281
 282         if (IS_BROADWELL(dev))
 283                 gen8_irq_power_well_post_enable(dev_priv,
 284                                                 1 << PIPE_C | 1 << PIPE_B);
 285 }
 286
 287 static void hsw_power_well_pre_disable(struct drm_i915_private *dev_priv)
 288 {
 289         if (IS_BROADWELL(dev_priv))
 290                 gen8_irq_power_well_pre_disable(dev_priv,
 291                                                 1 << PIPE_C | 1 << PIPE_B);
 292 }
 293
 294 static void skl_power_well_post_enable(struct drm_i915_private *dev_priv,
 295                                        struct i915_power_well *power_well)
 296 {
 297         struct drm_device *dev = dev_priv->dev;
 298
 299         /*
 300          * After we re-enable the power well, if we touch VGA register 0x3d5
 301          * we'll get unclaimed register interrupts. This stops after we write
 302          * anything to the VGA MSR register. The vgacon module uses this
 303          * register all the time, so if we unbind our driver and, as a
 304          * consequence, bind vgacon, we'll get stuck in an infinite loop at
 305          * console_unlock(). So make here we touch the VGA MSR register, making
 306          * sure vgacon can keep working normally without triggering interrupts
 307          * and error messages.
 308          */
 309         if (power_well->data == SKL_DISP_PW_2) {
 310                 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
 311                 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
 312                 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
 313
 314                 gen8_irq_power_well_post_enable(dev_priv,
 315                                                 1 << PIPE_C | 1 << PIPE_B);
 316         }
 317 }
 318
 319 static void skl_power_well_pre_disable(struct drm_i915_private *dev_priv,
 320                                        struct i915_power_well *power_well)
 321 {
 322         if (power_well->data == SKL_DISP_PW_2)
 323                 gen8_irq_power_well_pre_disable(dev_priv,
 324                                                 1 << PIPE_C | 1 << PIPE_B);
 325 }
 326
 327 static void hsw_set_power_well(struct drm_i915_private *dev_priv,
 328                                struct i915_power_well *power_well, bool enable)
 329 {
 330         bool is_enabled, enable_requested;
 331         uint32_t tmp;
 332
 333         tmp = I915_READ(HSW_PWR_WELL_DRIVER);
 334         is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
 335         enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
 336
 337         if (enable) {
 338                 if (!enable_requested)
 339                         I915_WRITE(HSW_PWR_WELL_DRIVER,
 340                                    HSW_PWR_WELL_ENABLE_REQUEST);
 341
 342                 if (!is_enabled) {
 343                         DRM_DEBUG_KMS("Enabling power well\n");
 344                         if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
 345                                       HSW_PWR_WELL_STATE_ENABLED), 20))
 346                                 DRM_ERROR("Timeout enabling power well\n");
 347                         hsw_power_well_post_enable(dev_priv);
 348                 }
 349
 350         } else {
 351                 if (enable_requested) {
 352                         hsw_power_well_pre_disable(dev_priv);
 353                         I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
 354                         POSTING_READ(HSW_PWR_WELL_DRIVER);
 355                         DRM_DEBUG_KMS("Requesting to disable the power well\n");
 356                 }
 357         }
 358 }
 359
 360 #define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS (         \
 361         BIT(POWER_DOMAIN_TRANSCODER_A) |                \
 362         BIT(POWER_DOMAIN_PIPE_B) |                      \
 363         BIT(POWER_DOMAIN_TRANSCODER_B) |                \
 364         BIT(POWER_DOMAIN_PIPE_C) |                      \
 365         BIT(POWER_DOMAIN_TRANSCODER_C) |                \
 366         BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |         \
 367         BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |         \
 368         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |            \
 369         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |            \
 370         BIT(POWER_DOMAIN_PORT_DDI_D_LANES) |            \
 371         BIT(POWER_DOMAIN_PORT_DDI_E_LANES) |            \
 372         BIT(POWER_DOMAIN_AUX_B) |                       \
 373         BIT(POWER_DOMAIN_AUX_C) |                       \
 374         BIT(POWER_DOMAIN_AUX_D) |                       \
 375         BIT(POWER_DOMAIN_AUDIO) |                       \
 376         BIT(POWER_DOMAIN_VGA) |                         \
 377         BIT(POWER_DOMAIN_INIT))
 378 #define SKL_DISPLAY_DDI_A_E_POWER_DOMAINS (             \
 379         BIT(POWER_DOMAIN_PORT_DDI_A_LANES) |            \
 380         BIT(POWER_DOMAIN_PORT_DDI_E_LANES) |            \
 381         BIT(POWER_DOMAIN_INIT))
 382 #define SKL_DISPLAY_DDI_B_POWER_DOMAINS (               \
 383         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |            \
 384         BIT(POWER_DOMAIN_INIT))
 385 #define SKL_DISPLAY_DDI_C_POWER_DOMAINS (               \
 386         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |            \
 387         BIT(POWER_DOMAIN_INIT))
 388 #define SKL_DISPLAY_DDI_D_POWER_DOMAINS (               \
 389         BIT(POWER_DOMAIN_PORT_DDI_D_LANES) |            \
 390         BIT(POWER_DOMAIN_INIT))
 391 #define SKL_DISPLAY_DC_OFF_POWER_DOMAINS (              \
 392         SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS |         \
 393         BIT(POWER_DOMAIN_MODESET) |                     \
 394         BIT(POWER_DOMAIN_AUX_A) |                       \
 395         BIT(POWER_DOMAIN_INIT))
 396 #define SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS (           \
 397         (POWER_DOMAIN_MASK & ~(                         \
 398         SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS |         \
 399         SKL_DISPLAY_DC_OFF_POWER_DOMAINS)) |            \
 400         BIT(POWER_DOMAIN_INIT))
 401
 402 #define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS (         \
 403         BIT(POWER_DOMAIN_TRANSCODER_A) |                \
 404         BIT(POWER_DOMAIN_PIPE_B) |                      \
 405         BIT(POWER_DOMAIN_TRANSCODER_B) |                \
 406         BIT(POWER_DOMAIN_PIPE_C) |                      \
 407         BIT(POWER_DOMAIN_TRANSCODER_C) |                \
 408         BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |         \
 409         BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |         \
 410         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |            \
 411         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |            \
 412         BIT(POWER_DOMAIN_AUX_B) |                       \
 413         BIT(POWER_DOMAIN_AUX_C) |                       \
 414         BIT(POWER_DOMAIN_AUDIO) |                       \
 415         BIT(POWER_DOMAIN_VGA) |                         \
 416         BIT(POWER_DOMAIN_GMBUS) |                       \
 417         BIT(POWER_DOMAIN_INIT))
 418 #define BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS (         \
 419         BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS |         \
 420         BIT(POWER_DOMAIN_PIPE_A) |                      \
 421         BIT(POWER_DOMAIN_TRANSCODER_EDP) |              \
 422         BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) |         \
 423         BIT(POWER_DOMAIN_PORT_DDI_A_LANES) |            \
 424         BIT(POWER_DOMAIN_AUX_A) |                       \
 425         BIT(POWER_DOMAIN_PLLS) |                        \
 426         BIT(POWER_DOMAIN_INIT))
 427 #define BXT_DISPLAY_DC_OFF_POWER_DOMAINS (              \
 428         BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS |         \
 429         BIT(POWER_DOMAIN_MODESET) |                     \
 430         BIT(POWER_DOMAIN_AUX_A) |                       \
 431         BIT(POWER_DOMAIN_INIT))
 432 #define BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS (           \
 433         (POWER_DOMAIN_MASK & ~(BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS |  \
 434         BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS)) |       \
 435         BIT(POWER_DOMAIN_INIT))
 436
 437 static void assert_can_enable_dc9(struct drm_i915_private *dev_priv)
 438 {
 439         struct drm_device *dev = dev_priv->dev;
 440
 441         WARN(!IS_BROXTON(dev), "Platform doesn't support DC9.\n");
 442         WARN((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9),
 443                 "DC9 already programmed to be enabled.\n");
 444         WARN(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
 445                 "DC5 still not disabled to enable DC9.\n");
 446         WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on.\n");
 447         WARN(intel_irqs_enabled(dev_priv), "Interrupts not disabled yet.\n");
 448
 449          /*
 450           * TODO: check for the following to verify the conditions to enter DC9
 451           * state are satisfied:
 452           * 1] Check relevant display engine registers to verify if mode set
 453           * disable sequence was followed.
 454           * 2] Check if display uninitialize sequence is initialized.
 455           */
 456 }
 457
 458 static void assert_can_disable_dc9(struct drm_i915_private *dev_priv)
 459 {
 460         WARN(intel_irqs_enabled(dev_priv), "Interrupts not disabled yet.\n");
 461         WARN(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
 462                 "DC5 still not disabled.\n");
 463
 464          /*
 465           * TODO: check for the following to verify DC9 state was indeed
 466           * entered before programming to disable it:
 467           * 1] Check relevant display engine registers to verify if mode
 468           *  set disable sequence was followed.
 469           * 2] Check if display uninitialize sequence is initialized.
 470           */
 471 }
 472
 473 static void gen9_write_dc_state(struct drm_i915_private *dev_priv,
 474                                 u32 state)
 475 {
 476         int rewrites = 0;
 477         int rereads = 0;
 478         u32 v;
 479
 480         I915_WRITE(DC_STATE_EN, state);
 481
 482         /* It has been observed that disabling the dc6 state sometimes
 483          * doesn't stick and dmc keeps returning old value. Make sure
 484          * the write really sticks enough times and also force rewrite until
 485          * we are confident that state is exactly what we want.
 486          */
 487         do  {
 488                 v = I915_READ(DC_STATE_EN);
 489
 490                 if (v != state) {
 491                         I915_WRITE(DC_STATE_EN, state);
 492                         rewrites++;
 493                         rereads = 0;
 494                 } else if (rereads++ > 5) {
 495                         break;
 496                 }
 497
 498         } while (rewrites < 100);
 499
 500         if (v != state)
 501                 DRM_ERROR("Writing dc state to 0x%x failed, now 0x%x\n",
 502                           state, v);
 503
 504         /* Most of the times we need one retry, avoid spam */
 505         if (rewrites > 1)
 506                 DRM_DEBUG_KMS("Rewrote dc state to 0x%x %d times\n",
 507                               state, rewrites);
 508 }
 509
 510 static void gen9_set_dc_state(struct drm_i915_private *dev_priv, uint32_t state)
 511 {
 512         uint32_t val;
 513         uint32_t mask;
 514
 515         mask = DC_STATE_EN_UPTO_DC5;
 516         if (IS_BROXTON(dev_priv))
 517                 mask |= DC_STATE_EN_DC9;
 518         else
 519                 mask |= DC_STATE_EN_UPTO_DC6;
 520
 521         if (WARN_ON_ONCE(state & ~dev_priv->csr.allowed_dc_mask))
 522                 state &= dev_priv->csr.allowed_dc_mask;
 523
 524         val = I915_READ(DC_STATE_EN);
 525         DRM_DEBUG_KMS("Setting DC state from %02x to %02x\n",
 526                       val & mask, state);
 527
 528         /* Check if DMC is ignoring our DC state requests */
 529         if ((val & mask) != dev_priv->csr.dc_state)
 530                 DRM_ERROR("DC state mismatch (0x%x -> 0x%x)\n",
 531                           dev_priv->csr.dc_state, val & mask);
 532
 533         val &= ~mask;
 534         val |= state;
 535
 536         gen9_write_dc_state(dev_priv, val);
 537
 538         dev_priv->csr.dc_state = val & mask;
 539 }
 540
 541 void bxt_enable_dc9(struct drm_i915_private *dev_priv)
 542 {
 543         assert_can_enable_dc9(dev_priv);
 544
 545         DRM_DEBUG_KMS("Enabling DC9\n");
 546
 547         gen9_set_dc_state(dev_priv, DC_STATE_EN_DC9);
 548 }
 549
 550 void bxt_disable_dc9(struct drm_i915_private *dev_priv)
 551 {
 552         assert_can_disable_dc9(dev_priv);
 553
 554         DRM_DEBUG_KMS("Disabling DC9\n");
 555
 556         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 557 }
 558
 559 static void assert_csr_loaded(struct drm_i915_private *dev_priv)
 560 {
 561         WARN_ONCE(!I915_READ(CSR_PROGRAM(0)),
 562                   "CSR program storage start is NULL\n");
 563         WARN_ONCE(!I915_READ(CSR_SSP_BASE), "CSR SSP Base Not fine\n");
 564         WARN_ONCE(!I915_READ(CSR_HTP_SKL), "CSR HTP Not fine\n");
 565 }
 566
 567 static void assert_can_enable_dc5(struct drm_i915_private *dev_priv)
 568 {
 569         struct drm_device *dev = dev_priv->dev;
 570         bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv,
 571                                         SKL_DISP_PW_2);
 572
 573         WARN_ONCE(!IS_SKYLAKE(dev) && !IS_KABYLAKE(dev),
 574                   "Platform doesn't support DC5.\n");
 575         WARN_ONCE(!HAS_RUNTIME_PM(dev), "Runtime PM not enabled.\n");
 576         WARN_ONCE(pg2_enabled, "PG2 not disabled to enable DC5.\n");
 577
 578         WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5),
 579                   "DC5 already programmed to be enabled.\n");
 580         assert_rpm_wakelock_held(dev_priv);
 581
 582         assert_csr_loaded(dev_priv);
 583 }
 584
 585 static void gen9_enable_dc5(struct drm_i915_private *dev_priv)
 586 {
 587         assert_can_enable_dc5(dev_priv);
 588
 589         DRM_DEBUG_KMS("Enabling DC5\n");
 590
 591         gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5);
 592 }
 593
 594 static void assert_can_enable_dc6(struct drm_i915_private *dev_priv)
 595 {
 596         struct drm_device *dev = dev_priv->dev;
 597
 598         WARN_ONCE(!IS_SKYLAKE(dev) && !IS_KABYLAKE(dev),
 599                   "Platform doesn't support DC6.\n");
 600         WARN_ONCE(!HAS_RUNTIME_PM(dev), "Runtime PM not enabled.\n");
 601         WARN_ONCE(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
 602                   "Backlight is not disabled.\n");
 603         WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6),
 604                   "DC6 already programmed to be enabled.\n");
 605
 606         assert_csr_loaded(dev_priv);
 607 }
 608
 609 void skl_enable_dc6(struct drm_i915_private *dev_priv)
 610 {
 611         assert_can_enable_dc6(dev_priv);
 612
 613         DRM_DEBUG_KMS("Enabling DC6\n");
 614
 615         gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
 616
 617 }
 618
 619 void skl_disable_dc6(struct drm_i915_private *dev_priv)
 620 {
 621         DRM_DEBUG_KMS("Disabling DC6\n");
 622
 623         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 624 }
 625
 626 static void skl_set_power_well(struct drm_i915_private *dev_priv,
 627                         struct i915_power_well *power_well, bool enable)
 628 {
 629         uint32_t tmp, fuse_status;
 630         uint32_t req_mask, state_mask;
 631         bool is_enabled, enable_requested, check_fuse_status = false;
 632
 633         tmp = I915_READ(HSW_PWR_WELL_DRIVER);
 634         fuse_status = I915_READ(SKL_FUSE_STATUS);
 635
 636         switch (power_well->data) {
 637         case SKL_DISP_PW_1:
 638                 if (wait_for((I915_READ(SKL_FUSE_STATUS) &
 639                         SKL_FUSE_PG0_DIST_STATUS), 1)) {
 640                         DRM_ERROR("PG0 not enabled\n");
 641                         return;
 642                 }
 643                 break;
 644         case SKL_DISP_PW_2:
 645                 if (!(fuse_status & SKL_FUSE_PG1_DIST_STATUS)) {
 646                         DRM_ERROR("PG1 in disabled state\n");
 647                         return;
 648                 }
 649                 break;
 650         case SKL_DISP_PW_DDI_A_E:
 651         case SKL_DISP_PW_DDI_B:
 652         case SKL_DISP_PW_DDI_C:
 653         case SKL_DISP_PW_DDI_D:
 654         case SKL_DISP_PW_MISC_IO:
 655                 break;
 656         default:
 657                 WARN(1, "Unknown power well %lu\n", power_well->data);
 658                 return;
 659         }
 660
 661         req_mask = SKL_POWER_WELL_REQ(power_well->data);
 662         enable_requested = tmp & req_mask;
 663         state_mask = SKL_POWER_WELL_STATE(power_well->data);
 664         is_enabled = tmp & state_mask;
 665
 666         if (!enable && enable_requested)
 667                 skl_power_well_pre_disable(dev_priv, power_well);
 668
 669         if (enable) {
 670                 if (!enable_requested) {
 671                         WARN((tmp & state_mask) &&
 672                                 !I915_READ(HSW_PWR_WELL_BIOS),
 673                                 "Invalid for power well status to be enabled, unless done by the BIOS, \
 674                                 when request is to disable!\n");
 675                         I915_WRITE(HSW_PWR_WELL_DRIVER, tmp | req_mask);
 676                 }
 677
 678                 if (!is_enabled) {
 679                         DRM_DEBUG_KMS("Enabling %s\n", power_well->name);
 680                         if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
 681                                 state_mask), 1))
 682                                 DRM_ERROR("%s enable timeout\n",
 683                                         power_well->name);
 684                         check_fuse_status = true;
 685                 }
 686         } else {
 687                 if (enable_requested) {
 688                         I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask);
 689                         POSTING_READ(HSW_PWR_WELL_DRIVER);
 690                         DRM_DEBUG_KMS("Disabling %s\n", power_well->name);
 691                 }
 692         }
 693
 694         if (check_fuse_status) {
 695                 if (power_well->data == SKL_DISP_PW_1) {
 696                         if (wait_for((I915_READ(SKL_FUSE_STATUS) &
 697                                 SKL_FUSE_PG1_DIST_STATUS), 1))
 698                                 DRM_ERROR("PG1 distributing status timeout\n");
 699                 } else if (power_well->data == SKL_DISP_PW_2) {
 700                         if (wait_for((I915_READ(SKL_FUSE_STATUS) &
 701                                 SKL_FUSE_PG2_DIST_STATUS), 1))
 702                                 DRM_ERROR("PG2 distributing status timeout\n");
 703                 }
 704         }
 705
 706         if (enable && !is_enabled)
 707                 skl_power_well_post_enable(dev_priv, power_well);
 708 }
 709
 710 static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
 711                                    struct i915_power_well *power_well)
 712 {
 713         hsw_set_power_well(dev_priv, power_well, power_well->count > 0);
 714
 715         /*
 716          * We're taking over the BIOS, so clear any requests made by it since
 717          * the driver is in charge now.
 718          */
 719         if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
 720                 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
 721 }
 722
 723 static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
 724                                   struct i915_power_well *power_well)
 725 {
 726         hsw_set_power_well(dev_priv, power_well, true);
 727 }
 728
 729 static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
 730                                    struct i915_power_well *power_well)
 731 {
 732         hsw_set_power_well(dev_priv, power_well, false);
 733 }
 734
 735 static bool skl_power_well_enabled(struct drm_i915_private *dev_priv,
 736                                         struct i915_power_well *power_well)
 737 {
 738         uint32_t mask = SKL_POWER_WELL_REQ(power_well->data) |
 739                 SKL_POWER_WELL_STATE(power_well->data);
 740
 741         return (I915_READ(HSW_PWR_WELL_DRIVER) & mask) == mask;
 742 }
 743
 744 static void skl_power_well_sync_hw(struct drm_i915_private *dev_priv,
 745                                 struct i915_power_well *power_well)
 746 {
 747         skl_set_power_well(dev_priv, power_well, power_well->count > 0);
 748
 749         /* Clear any request made by BIOS as driver is taking over */
 750         I915_WRITE(HSW_PWR_WELL_BIOS, 0);
 751 }
 752
 753 static void skl_power_well_enable(struct drm_i915_private *dev_priv,
 754                                 struct i915_power_well *power_well)
 755 {
 756         skl_set_power_well(dev_priv, power_well, true);
 757 }
 758
 759 static void skl_power_well_disable(struct drm_i915_private *dev_priv,
 760                                 struct i915_power_well *power_well)
 761 {
 762         skl_set_power_well(dev_priv, power_well, false);
 763 }
 764
 765 static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv,
 766                                            struct i915_power_well *power_well)
 767 {
 768         return (I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0;
 769 }
 770
 771 static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
 772                                           struct i915_power_well *power_well)
 773 {
 774         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 775 }
 776
 777 static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
 778                                            struct i915_power_well *power_well)
 779 {
 780         if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC6)
 781                 skl_enable_dc6(dev_priv);
 782         else if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5)
 783                 gen9_enable_dc5(dev_priv);
 784 }
 785
 786 static void gen9_dc_off_power_well_sync_hw(struct drm_i915_private *dev_priv,
 787                                            struct i915_power_well *power_well)
 788 {
 789         if (power_well->count > 0)
 790                 gen9_dc_off_power_well_enable(dev_priv, power_well);
 791         else
 792                 gen9_dc_off_power_well_disable(dev_priv, power_well);
 793 }
 794
 795 static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,
 796                                            struct i915_power_well *power_well)
 797 {
 798 }
 799
 800 static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,
 801                                              struct i915_power_well *power_well)
 802 {
 803         return true;
 804 }
 805
 806 static void vlv_set_power_well(struct drm_i915_private *dev_priv,
 807                                struct i915_power_well *power_well, bool enable)
 808 {
 809         enum punit_power_well power_well_id = power_well->data;
 810         u32 mask;
 811         u32 state;
 812         u32 ctrl;
 813
 814         mask = PUNIT_PWRGT_MASK(power_well_id);
 815         state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) :
 816                          PUNIT_PWRGT_PWR_GATE(power_well_id);
 817
 818         mutex_lock(&dev_priv->rps.hw_lock);
 819
 820 #define COND \
 821         ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)
 822
 823         if (COND)
 824                 goto out;
 825
 826         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL);
 827         ctrl &= ~mask;
 828         ctrl |= state;
 829         vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl);
 830
 831         if (wait_for(COND, 100))
 832                 DRM_ERROR("timeout setting power well state %08x (%08x)\n",
 833                           state,
 834                           vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL));
 835
 836 #undef COND
 837
 838 out:
 839         mutex_unlock(&dev_priv->rps.hw_lock);
 840 }
 841
 842 static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv,
 843                                    struct i915_power_well *power_well)
 844 {
 845         vlv_set_power_well(dev_priv, power_well, power_well->count > 0);
 846 }
 847
 848 static void vlv_power_well_enable(struct drm_i915_private *dev_priv,
 849                                   struct i915_power_well *power_well)
 850 {
 851         vlv_set_power_well(dev_priv, power_well, true);
 852 }
 853
 854 static void vlv_power_well_disable(struct drm_i915_private *dev_priv,
 855                                    struct i915_power_well *power_well)
 856 {
 857         vlv_set_power_well(dev_priv, power_well, false);
 858 }
 859
 860 static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
 861                                    struct i915_power_well *power_well)
 862 {
 863         int power_well_id = power_well->data;
 864         bool enabled = false;
 865         u32 mask;
 866         u32 state;
 867         u32 ctrl;
 868
 869         mask = PUNIT_PWRGT_MASK(power_well_id);
 870         ctrl = PUNIT_PWRGT_PWR_ON(power_well_id);
 871
 872         mutex_lock(&dev_priv->rps.hw_lock);
 873
 874         state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask;
 875         /*
 876          * We only ever set the power-on and power-gate states, anything
 877          * else is unexpected.
 878          */
 879         WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) &&
 880                 state != PUNIT_PWRGT_PWR_GATE(power_well_id));
 881         if (state == ctrl)
 882                 enabled = true;
 883
 884         /*
 885          * A transient state at this point would mean some unexpected party
 886          * is poking at the power controls too.
 887          */
 888         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask;
 889         WARN_ON(ctrl != state);
 890
 891         mutex_unlock(&dev_priv->rps.hw_lock);
 892
 893         return enabled;
 894 }
 895
 896 static void vlv_display_power_well_init(struct drm_i915_private *dev_priv)
 897 {
 898         enum pipe pipe;
 899
 900         /*
 901          * Enable the CRI clock source so we can get at the
 902          * display and the reference clock for VGA
 903          * hotplug / manual detection. Supposedly DSI also
 904          * needs the ref clock up and running.
 905          *
 906          * CHV DPLL B/C have some issues if VGA mode is enabled.
 907          */
 908         for_each_pipe(dev_priv->dev, pipe) {
 909                 u32 val = I915_READ(DPLL(pipe));
 910
 911                 val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
 912                 if (pipe != PIPE_A)
 913                         val |= DPLL_INTEGRATED_CRI_CLK_VLV;
 914
 915                 I915_WRITE(DPLL(pipe), val);
 916         }
 917
 918         spin_lock_irq(&dev_priv->irq_lock);
 919         valleyview_enable_display_irqs(dev_priv);
 920         spin_unlock_irq(&dev_priv->irq_lock);
 921
 922         /*
 923          * During driver initialization/resume we can avoid restoring the
 924          * part of the HW/SW state that will be inited anyway explicitly.
 925          */
 926         if (dev_priv->power_domains.initializing)
 927                 return;
 928
 929         intel_hpd_init(dev_priv);
 930
 931         i915_redisable_vga_power_on(dev_priv->dev);
 932 }
 933
 934 static void vlv_display_power_well_deinit(struct drm_i915_private *dev_priv)
 935 {
 936         spin_lock_irq(&dev_priv->irq_lock);
 937         valleyview_disable_display_irqs(dev_priv);
 938         spin_unlock_irq(&dev_priv->irq_lock);
 939
 940         /* make sure we're done processing display irqs */
 941         synchronize_irq(dev_priv->dev->irq);
 942
 943         vlv_power_sequencer_reset(dev_priv);
 944 }
 945
 946 static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv,
 947                                           struct i915_power_well *power_well)
 948 {
 949         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
 950
 951         vlv_set_power_well(dev_priv, power_well, true);
 952
 953         vlv_display_power_well_init(dev_priv);
 954 }
 955
 956 static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv,
 957                                            struct i915_power_well *power_well)
 958 {
 959         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
 960
 961         vlv_display_power_well_deinit(dev_priv);
 962
 963         vlv_set_power_well(dev_priv, power_well, false);
 964 }
 965
 966 static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
 967                                            struct i915_power_well *power_well)
 968 {
 969         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
 970
 971         /* since ref/cri clock was enabled */
 972         udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
 973
 974         vlv_set_power_well(dev_priv, power_well, true);
 975
 976         /*
 977          * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
 978          *  6.  De-assert cmn_reset/side_reset. Same as VLV X0.
 979          *   a. GUnit 0x2110 bit[0] set to 1 (def 0)
 980          *   b. The other bits such as sfr settings / modesel may all
 981          *      be set to 0.
 982          *
 983          * This should only be done on init and resume from S3 with
 984          * both PLLs disabled, or we risk losing DPIO and PLL
 985          * synchronization.
 986          */
 987         I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
 988 }
 989
 990 static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
 991                                             struct i915_power_well *power_well)
 992 {
 993         enum pipe pipe;
 994
 995         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
 996
 997         for_each_pipe(dev_priv, pipe)
 998                 assert_pll_disabled(dev_priv, pipe);
 999
1000         /* Assert common reset */
1001         I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST);
1002
1003         vlv_set_power_well(dev_priv, power_well, false);
1004 }
1005
1006 #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
1007
1008 static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv,
1009                                                  int power_well_id)
1010 {
1011         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1012         int i;
1013
1014         for (i = 0; i < power_domains->power_well_count; i++) {
1015                 struct i915_power_well *power_well;
1016
1017                 power_well = &power_domains->power_wells[i];
1018                 if (power_well->data == power_well_id)
1019                         return power_well;
1020         }
1021
1022         return NULL;
1023 }
1024
1025 #define BITS_SET(val, bits) (((val) & (bits)) == (bits))
1026
1027 static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
1028 {
1029         struct i915_power_well *cmn_bc =
1030                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
1031         struct i915_power_well *cmn_d =
1032                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D);
1033         u32 phy_control = dev_priv->chv_phy_control;
1034         u32 phy_status = 0;
1035         u32 phy_status_mask = 0xffffffff;
1036         u32 tmp;
1037
1038         /*
1039          * The BIOS can leave the PHY is some weird state
1040          * where it doesn't fully power down some parts.
1041          * Disable the asserts until the PHY has been fully
1042          * reset (ie. the power well has been disabled at
1043          * least once).
1044          */
1045         if (!dev_priv->chv_phy_assert[DPIO_PHY0])
1046                 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0) |
1047                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0) |
1048                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1) |
1049                                      PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1) |
1050                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0) |
1051                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1));
1052
1053         if (!dev_priv->chv_phy_assert[DPIO_PHY1])
1054                 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0) |
1055                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0) |
1056                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1));
1057
1058         if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) {
1059                 phy_status |= PHY_POWERGOOD(DPIO_PHY0);
1060
1061                 /* this assumes override is only used to enable lanes */
1062                 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0)) == 0)
1063                         phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0);
1064
1065                 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1)) == 0)
1066                         phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1);
1067
1068                 /* CL1 is on whenever anything is on in either channel */
1069                 if (BITS_SET(phy_control,
1070                              PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0) |
1071                              PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)))
1072                         phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0);
1073
1074                 /*
1075                  * The DPLLB check accounts for the pipe B + port A usage
1076                  * with CL2 powered up but all the lanes in the second channel
1077                  * powered down.
1078                  */
1079                 if (BITS_SET(phy_control,
1080                              PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)) &&
1081                     (I915_READ(DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0)
1082                         phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1);
1083
1084                 if (BITS_SET(phy_control,
1085                              PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH0)))
1086                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0);
1087                 if (BITS_SET(phy_control,
1088                              PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH0)))
1089                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1);
1090
1091                 if (BITS_SET(phy_control,
1092                              PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH1)))
1093                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0);
1094                 if (BITS_SET(phy_control,
1095                              PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH1)))
1096                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1);
1097         }
1098
1099         if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) {
1100                 phy_status |= PHY_POWERGOOD(DPIO_PHY1);
1101
1102                 /* this assumes override is only used to enable lanes */
1103                 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0)) == 0)
1104                         phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0);
1105
1106                 if (BITS_SET(phy_control,
1107                              PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0)))
1108                         phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0);
1109
1110                 if (BITS_SET(phy_control,
1111                              PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY1, DPIO_CH0)))
1112                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0);
1113                 if (BITS_SET(phy_control,
1114                              PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY1, DPIO_CH0)))
1115                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1);
1116         }
1117
1118         phy_status &= phy_status_mask;
1119
1120         /*
1121          * The PHY may be busy with some initial calibration and whatnot,
1122          * so the power state can take a while to actually change.
1123          */
1124         if (wait_for((tmp = I915_READ(DISPLAY_PHY_STATUS) & phy_status_mask) == phy_status, 10))
1125                 WARN(phy_status != tmp,
1126                      "Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n",
1127                      tmp, phy_status, dev_priv->chv_phy_control);
1128 }
1129
1130 #undef BITS_SET
1131
1132 static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
1133                                            struct i915_power_well *power_well)
1134 {
1135         enum dpio_phy phy;
1136         enum pipe pipe;
1137         uint32_t tmp;
1138
1139         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
1140                      power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
1141
1142         if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
1143                 pipe = PIPE_A;
1144                 phy = DPIO_PHY0;
1145         } else {
1146                 pipe = PIPE_C;
1147                 phy = DPIO_PHY1;
1148         }
1149
1150         /* since ref/cri clock was enabled */
1151         udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
1152         vlv_set_power_well(dev_priv, power_well, true);
1153
1154         /* Poll for phypwrgood signal */
1155         if (wait_for(I915_READ(DISPLAY_PHY_STATUS) & PHY_POWERGOOD(phy), 1))
1156                 DRM_ERROR("Display PHY %d is not power up\n", phy);
1157
1158         mutex_lock(&dev_priv->sb_lock);
1159
1160         /* Enable dynamic power down */
1161         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW28);
1162         tmp |= DPIO_DYNPWRDOWNEN_CH0 | DPIO_CL1POWERDOWNEN |
1163                 DPIO_SUS_CLK_CONFIG_GATE_CLKREQ;
1164         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW28, tmp);
1165
1166         if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
1167                 tmp = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW6_CH1);
1168                 tmp |= DPIO_DYNPWRDOWNEN_CH1;
1169                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW6_CH1, tmp);
1170         } else {
1171                 /*
1172                  * Force the non-existing CL2 off. BXT does this
1173                  * too, so maybe it saves some power even though
1174                  * CL2 doesn't exist?
1175                  */
1176                 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
1177                 tmp |= DPIO_CL2_LDOFUSE_PWRENB;
1178                 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, tmp);
1179         }
1180
1181         mutex_unlock(&dev_priv->sb_lock);
1182
1183         dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy);
1184         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1185
1186         DRM_DEBUG_KMS("Enabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
1187                       phy, dev_priv->chv_phy_control);
1188
1189         assert_chv_phy_status(dev_priv);
1190 }
1191
1192 static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
1193                                             struct i915_power_well *power_well)
1194 {
1195         enum dpio_phy phy;
1196
1197         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
1198                      power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
1199
1200         if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
1201                 phy = DPIO_PHY0;
1202                 assert_pll_disabled(dev_priv, PIPE_A);
1203                 assert_pll_disabled(dev_priv, PIPE_B);
1204         } else {
1205                 phy = DPIO_PHY1;
1206                 assert_pll_disabled(dev_priv, PIPE_C);
1207         }
1208
1209         dev_priv->chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy);
1210         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1211
1212         vlv_set_power_well(dev_priv, power_well, false);
1213
1214         DRM_DEBUG_KMS("Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
1215                       phy, dev_priv->chv_phy_control);
1216
1217         /* PHY is fully reset now, so we can enable the PHY state asserts */
1218         dev_priv->chv_phy_assert[phy] = true;
1219
1220         assert_chv_phy_status(dev_priv);
1221 }
1222
1223 static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1224                                      enum dpio_channel ch, bool override, unsigned int mask)
1225 {
1226         enum pipe pipe = phy == DPIO_PHY0 ? PIPE_A : PIPE_C;
1227         u32 reg, val, expected, actual;
1228
1229         /*
1230          * The BIOS can leave the PHY is some weird state
1231          * where it doesn't fully power down some parts.
1232          * Disable the asserts until the PHY has been fully
1233          * reset (ie. the power well has been disabled at
1234          * least once).
1235          */
1236         if (!dev_priv->chv_phy_assert[phy])
1237                 return;
1238
1239         if (ch == DPIO_CH0)
1240                 reg = _CHV_CMN_DW0_CH0;
1241         else
1242                 reg = _CHV_CMN_DW6_CH1;
1243
1244         mutex_lock(&dev_priv->sb_lock);
1245         val = vlv_dpio_read(dev_priv, pipe, reg);
1246         mutex_unlock(&dev_priv->sb_lock);
1247
1248         /*
1249          * This assumes !override is only used when the port is disabled.
1250          * All lanes should power down even without the override when
1251          * the port is disabled.
1252          */
1253         if (!override || mask == 0xf) {
1254                 expected = DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN;
1255                 /*
1256                  * If CH1 common lane is not active anymore
1257                  * (eg. for pipe B DPLL) the entire channel will
1258                  * shut down, which causes the common lane registers
1259                  * to read as 0. That means we can't actually check
1260                  * the lane power down status bits, but as the entire
1261                  * register reads as 0 it's a good indication that the
1262                  * channel is indeed entirely powered down.
1263                  */
1264                 if (ch == DPIO_CH1 && val == 0)
1265                         expected = 0;
1266         } else if (mask != 0x0) {
1267                 expected = DPIO_ANYDL_POWERDOWN;
1268         } else {
1269                 expected = 0;
1270         }
1271
1272         if (ch == DPIO_CH0)
1273                 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH0;
1274         else
1275                 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH1;
1276         actual &= DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN;
1277
1278         WARN(actual != expected,
1279              "Unexpected DPIO lane power down: all %d, any %d. Expected: all %d, any %d. (0x%x = 0x%08x)\n",
1280              !!(actual & DPIO_ALLDL_POWERDOWN), !!(actual & DPIO_ANYDL_POWERDOWN),
1281              !!(expected & DPIO_ALLDL_POWERDOWN), !!(expected & DPIO_ANYDL_POWERDOWN),
1282              reg, val);
1283 }
1284
1285 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1286                           enum dpio_channel ch, bool override)
1287 {
1288         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1289         bool was_override;
1290
1291         mutex_lock(&power_domains->lock);
1292
1293         was_override = dev_priv->chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1294
1295         if (override == was_override)
1296                 goto out;
1297
1298         if (override)
1299                 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1300         else
1301                 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1302
1303         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1304
1305         DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d (DPIO_PHY_CONTROL=0x%08x)\n",
1306                       phy, ch, dev_priv->chv_phy_control);
1307
1308         assert_chv_phy_status(dev_priv);
1309
1310 out:
1311         mutex_unlock(&power_domains->lock);
1312
1313         return was_override;
1314 }
1315
1316 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1317                              bool override, unsigned int mask)
1318 {
1319         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1320         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1321         enum dpio_phy phy = vlv_dport_to_phy(enc_to_dig_port(&encoder->base));
1322         enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
1323
1324         mutex_lock(&power_domains->lock);
1325
1326         dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch);
1327         dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch);
1328
1329         if (override)
1330                 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1331         else
1332                 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1333
1334         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1335
1336         DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d lanes 0x%x (PHY_CONTROL=0x%08x)\n",
1337                       phy, ch, mask, dev_priv->chv_phy_control);
1338
1339         assert_chv_phy_status(dev_priv);
1340
1341         assert_chv_phy_powergate(dev_priv, phy, ch, override, mask);
1342
1343         mutex_unlock(&power_domains->lock);
1344 }
1345
1346 static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv,
1347                                         struct i915_power_well *power_well)
1348 {
1349         enum pipe pipe = power_well->data;
1350         bool enabled;
1351         u32 state, ctrl;
1352
1353         mutex_lock(&dev_priv->rps.hw_lock);
1354
1355         state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe);
1356         /*
1357          * We only ever set the power-on and power-gate states, anything
1358          * else is unexpected.
1359          */
1360         WARN_ON(state != DP_SSS_PWR_ON(pipe) && state != DP_SSS_PWR_GATE(pipe));
1361         enabled = state == DP_SSS_PWR_ON(pipe);
1362
1363         /*
1364          * A transient state at this point would mean some unexpected party
1365          * is poking at the power controls too.
1366          */
1367         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe);
1368         WARN_ON(ctrl << 16 != state);
1369
1370         mutex_unlock(&dev_priv->rps.hw_lock);
1371
1372         return enabled;
1373 }
1374
1375 static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv,
1376                                     struct i915_power_well *power_well,
1377                                     bool enable)
1378 {
1379         enum pipe pipe = power_well->data;
1380         u32 state;
1381         u32 ctrl;
1382
1383         state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe);
1384
1385         mutex_lock(&dev_priv->rps.hw_lock);
1386
1387 #define COND \
1388         ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state)
1389
1390         if (COND)
1391                 goto out;
1392
1393         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
1394         ctrl &= ~DP_SSC_MASK(pipe);
1395         ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe);
1396         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl);
1397
1398         if (wait_for(COND, 100))
1399                 DRM_ERROR("timeout setting power well state %08x (%08x)\n",
1400                           state,
1401                           vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ));
1402
1403 #undef COND
1404
1405 out:
1406         mutex_unlock(&dev_priv->rps.hw_lock);
1407 }
1408
1409 static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv,
1410                                         struct i915_power_well *power_well)
1411 {
1412         WARN_ON_ONCE(power_well->data != PIPE_A);
1413
1414         chv_set_pipe_power_well(dev_priv, power_well, power_well->count > 0);
1415 }
1416
1417 static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv,
1418                                        struct i915_power_well *power_well)
1419 {
1420         WARN_ON_ONCE(power_well->data != PIPE_A);
1421
1422         chv_set_pipe_power_well(dev_priv, power_well, true);
1423
1424         vlv_display_power_well_init(dev_priv);
1425 }
1426
1427 static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv,
1428                                         struct i915_power_well *power_well)
1429 {
1430         WARN_ON_ONCE(power_well->data != PIPE_A);
1431
1432         vlv_display_power_well_deinit(dev_priv);
1433
1434         chv_set_pipe_power_well(dev_priv, power_well, false);
1435 }
1436
1437 static void
1438 __intel_display_power_get_domain(struct drm_i915_private *dev_priv,
1439                                  enum intel_display_power_domain domain)
1440 {
1441         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1442         struct i915_power_well *power_well;
1443         int i;
1444
1445         for_each_power_well(i, power_well, BIT(domain), power_domains) {
1446                 if (!power_well->count++)
1447                         intel_power_well_enable(dev_priv, power_well);
1448         }
1449
1450         power_domains->domain_use_count[domain]++;
1451 }
1452
1453 /**
1454  * intel_display_power_get - grab a power domain reference
1455  * @dev_priv: i915 device instance
1456  * @domain: power domain to reference
1457  *
1458  * This function grabs a power domain reference for @domain and ensures that the
1459  * power domain and all its parents are powered up. Therefore users should only
1460  * grab a reference to the innermost power domain they need.
1461  *
1462  * Any power domain reference obtained by this function must have a symmetric
1463  * call to intel_display_power_put() to release the reference again.
1464  */
1465 void intel_display_power_get(struct drm_i915_private *dev_priv,
1466                              enum intel_display_power_domain domain)
1467 {
1468         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1469
1470         intel_runtime_pm_get(dev_priv);
1471
1472         mutex_lock(&power_domains->lock);
1473
1474         __intel_display_power_get_domain(dev_priv, domain);
1475
1476         mutex_unlock(&power_domains->lock);
1477 }
1478
1479 /**
1480  * intel_display_power_get_if_enabled - grab a reference for an enabled display power domain
1481  * @dev_priv: i915 device instance
1482  * @domain: power domain to reference
1483  *
1484  * This function grabs a power domain reference for @domain and ensures that the
1485  * power domain and all its parents are powered up. Therefore users should only
1486  * grab a reference to the innermost power domain they need.
1487  *
1488  * Any power domain reference obtained by this function must have a symmetric
1489  * call to intel_display_power_put() to release the reference again.
1490  */
1491 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
1492                                         enum intel_display_power_domain domain)
1493 {
1494         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1495         bool is_enabled;
1496
1497         if (!intel_runtime_pm_get_if_in_use(dev_priv))
1498                 return false;
1499
1500         mutex_lock(&power_domains->lock);
1501
1502         if (__intel_display_power_is_enabled(dev_priv, domain)) {
1503                 __intel_display_power_get_domain(dev_priv, domain);
1504                 is_enabled = true;
1505         } else {
1506                 is_enabled = false;
1507         }
1508
1509         mutex_unlock(&power_domains->lock);
1510
1511         if (!is_enabled)
1512                 intel_runtime_pm_put(dev_priv);
1513
1514         return is_enabled;
1515 }
1516
1517 /**
1518  * intel_display_power_put - release a power domain reference
1519  * @dev_priv: i915 device instance
1520  * @domain: power domain to reference
1521  *
1522  * This function drops the power domain reference obtained by
1523  * intel_display_power_get() and might power down the corresponding hardware
1524  * block right away if this is the last reference.
1525  */
1526 void intel_display_power_put(struct drm_i915_private *dev_priv,
1527                              enum intel_display_power_domain domain)
1528 {
1529         struct i915_power_domains *power_domains;
1530         struct i915_power_well *power_well;
1531         int i;
1532
1533         power_domains = &dev_priv->power_domains;
1534
1535         mutex_lock(&power_domains->lock);
1536
1537         WARN(!power_domains->domain_use_count[domain],
1538              "Use count on domain %s is already zero\n",
1539              intel_display_power_domain_str(domain));
1540         power_domains->domain_use_count[domain]--;
1541
1542         for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
1543                 WARN(!power_well->count,
1544                      "Use count on power well %s is already zero",
1545                      power_well->name);
1546
1547                 if (!--power_well->count)
1548                         intel_power_well_disable(dev_priv, power_well);
1549         }
1550
1551         mutex_unlock(&power_domains->lock);
1552
1553         intel_runtime_pm_put(dev_priv);
1554 }
1555
1556 #define HSW_ALWAYS_ON_POWER_DOMAINS (                   \
1557         BIT(POWER_DOMAIN_PIPE_A) |                      \
1558         BIT(POWER_DOMAIN_TRANSCODER_EDP) |              \
1559         BIT(POWER_DOMAIN_PORT_DDI_A_LANES) |            \
1560         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |            \
1561         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |            \
1562         BIT(POWER_DOMAIN_PORT_DDI_D_LANES) |            \
1563         BIT(POWER_DOMAIN_PORT_CRT) |                    \
1564         BIT(POWER_DOMAIN_PLLS) |                        \
1565         BIT(POWER_DOMAIN_AUX_A) |                       \
1566         BIT(POWER_DOMAIN_AUX_B) |                       \
1567         BIT(POWER_DOMAIN_AUX_C) |                       \
1568         BIT(POWER_DOMAIN_AUX_D) |                       \
1569         BIT(POWER_DOMAIN_GMBUS) |                       \
1570         BIT(POWER_DOMAIN_INIT))
1571 #define HSW_DISPLAY_POWER_DOMAINS (                             \
1572         (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) |    \
1573         BIT(POWER_DOMAIN_INIT))
1574
1575 #define BDW_ALWAYS_ON_POWER_DOMAINS (                   \
1576         HSW_ALWAYS_ON_POWER_DOMAINS |                   \
1577         BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER))
1578 #define BDW_DISPLAY_POWER_DOMAINS (                             \
1579         (POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) |    \
1580         BIT(POWER_DOMAIN_INIT))
1581
1582 #define VLV_ALWAYS_ON_POWER_DOMAINS     BIT(POWER_DOMAIN_INIT)
1583 #define VLV_DISPLAY_POWER_DOMAINS       POWER_DOMAIN_MASK
1584
1585 #define VLV_DPIO_CMN_BC_POWER_DOMAINS (         \
1586         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |    \
1587         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |    \
1588         BIT(POWER_DOMAIN_PORT_CRT) |            \
1589         BIT(POWER_DOMAIN_AUX_B) |               \
1590         BIT(POWER_DOMAIN_AUX_C) |               \
1591         BIT(POWER_DOMAIN_INIT))
1592
1593 #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS (  \
1594         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |    \
1595         BIT(POWER_DOMAIN_AUX_B) |               \
1596         BIT(POWER_DOMAIN_INIT))
1597
1598 #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS (  \
1599         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |    \
1600         BIT(POWER_DOMAIN_AUX_B) |               \
1601         BIT(POWER_DOMAIN_INIT))
1602
1603 #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS (  \
1604         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |    \
1605         BIT(POWER_DOMAIN_AUX_C) |               \
1606         BIT(POWER_DOMAIN_INIT))
1607
1608 #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS (  \
1609         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |    \
1610         BIT(POWER_DOMAIN_AUX_C) |               \
1611         BIT(POWER_DOMAIN_INIT))
1612
1613 #define CHV_DPIO_CMN_BC_POWER_DOMAINS (         \
1614         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |    \
1615         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |    \
1616         BIT(POWER_DOMAIN_AUX_B) |               \
1617         BIT(POWER_DOMAIN_AUX_C) |               \
1618         BIT(POWER_DOMAIN_INIT))
1619
1620 #define CHV_DPIO_CMN_D_POWER_DOMAINS (          \
1621         BIT(POWER_DOMAIN_PORT_DDI_D_LANES) |    \
1622         BIT(POWER_DOMAIN_AUX_D) |               \
1623         BIT(POWER_DOMAIN_INIT))
1624
1625 static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
1626         .sync_hw = i9xx_always_on_power_well_noop,
1627         .enable = i9xx_always_on_power_well_noop,
1628         .disable = i9xx_always_on_power_well_noop,
1629         .is_enabled = i9xx_always_on_power_well_enabled,
1630 };
1631
1632 static const struct i915_power_well_ops chv_pipe_power_well_ops = {
1633         .sync_hw = chv_pipe_power_well_sync_hw,
1634         .enable = chv_pipe_power_well_enable,
1635         .disable = chv_pipe_power_well_disable,
1636         .is_enabled = chv_pipe_power_well_enabled,
1637 };
1638
1639 static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = {
1640         .sync_hw = vlv_power_well_sync_hw,
1641         .enable = chv_dpio_cmn_power_well_enable,
1642         .disable = chv_dpio_cmn_power_well_disable,
1643         .is_enabled = vlv_power_well_enabled,
1644 };
1645
1646 static struct i915_power_well i9xx_always_on_power_well[] = {
1647         {
1648                 .name = "always-on",
1649                 .always_on = 1,
1650                 .domains = POWER_DOMAIN_MASK,
1651                 .ops = &i9xx_always_on_power_well_ops,
1652         },
1653 };
1654
1655 static const struct i915_power_well_ops hsw_power_well_ops = {
1656         .sync_hw = hsw_power_well_sync_hw,
1657         .enable = hsw_power_well_enable,
1658         .disable = hsw_power_well_disable,
1659         .is_enabled = hsw_power_well_enabled,
1660 };
1661
1662 static const struct i915_power_well_ops skl_power_well_ops = {
1663         .sync_hw = skl_power_well_sync_hw,
1664         .enable = skl_power_well_enable,
1665         .disable = skl_power_well_disable,
1666         .is_enabled = skl_power_well_enabled,
1667 };
1668
1669 static const struct i915_power_well_ops gen9_dc_off_power_well_ops = {
1670         .sync_hw = gen9_dc_off_power_well_sync_hw,
1671         .enable = gen9_dc_off_power_well_enable,
1672         .disable = gen9_dc_off_power_well_disable,
1673         .is_enabled = gen9_dc_off_power_well_enabled,
1674 };
1675
1676 static struct i915_power_well hsw_power_wells[] = {
1677         {
1678                 .name = "always-on",
1679                 .always_on = 1,
1680                 .domains = HSW_ALWAYS_ON_POWER_DOMAINS,
1681                 .ops = &i9xx_always_on_power_well_ops,
1682         },
1683         {
1684                 .name = "display",
1685                 .domains = HSW_DISPLAY_POWER_DOMAINS,
1686                 .ops = &hsw_power_well_ops,
1687         },
1688 };
1689
1690 static struct i915_power_well bdw_power_wells[] = {
1691         {
1692                 .name = "always-on",
1693                 .always_on = 1,
1694                 .domains = BDW_ALWAYS_ON_POWER_DOMAINS,
1695                 .ops = &i9xx_always_on_power_well_ops,
1696         },
1697         {
1698                 .name = "display",
1699                 .domains = BDW_DISPLAY_POWER_DOMAINS,
1700                 .ops = &hsw_power_well_ops,
1701         },
1702 };
1703
1704 static const struct i915_power_well_ops vlv_display_power_well_ops = {
1705         .sync_hw = vlv_power_well_sync_hw,
1706         .enable = vlv_display_power_well_enable,
1707         .disable = vlv_display_power_well_disable,
1708         .is_enabled = vlv_power_well_enabled,
1709 };
1710
1711 static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = {
1712         .sync_hw = vlv_power_well_sync_hw,
1713         .enable = vlv_dpio_cmn_power_well_enable,
1714         .disable = vlv_dpio_cmn_power_well_disable,
1715         .is_enabled = vlv_power_well_enabled,
1716 };
1717
1718 static const struct i915_power_well_ops vlv_dpio_power_well_ops = {
1719         .sync_hw = vlv_power_well_sync_hw,
1720         .enable = vlv_power_well_enable,
1721         .disable = vlv_power_well_disable,
1722         .is_enabled = vlv_power_well_enabled,
1723 };
1724
1725 static struct i915_power_well vlv_power_wells[] = {
1726         {
1727                 .name = "always-on",
1728                 .always_on = 1,
1729                 .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
1730                 .ops = &i9xx_always_on_power_well_ops,
1731                 .data = PUNIT_POWER_WELL_ALWAYS_ON,
1732         },
1733         {
1734                 .name = "display",
1735                 .domains = VLV_DISPLAY_POWER_DOMAINS,
1736                 .data = PUNIT_POWER_WELL_DISP2D,
1737                 .ops = &vlv_display_power_well_ops,
1738         },
1739         {
1740                 .name = "dpio-tx-b-01",
1741                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1742                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1743                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1744                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1745                 .ops = &vlv_dpio_power_well_ops,
1746                 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
1747         },
1748         {
1749                 .name = "dpio-tx-b-23",
1750                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1751                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1752                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1753                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1754                 .ops = &vlv_dpio_power_well_ops,
1755                 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
1756         },
1757         {
1758                 .name = "dpio-tx-c-01",
1759                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1760                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1761                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1762                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1763                 .ops = &vlv_dpio_power_well_ops,
1764                 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
1765         },
1766         {
1767                 .name = "dpio-tx-c-23",
1768                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1769                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1770                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1771                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1772                 .ops = &vlv_dpio_power_well_ops,
1773                 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
1774         },
1775         {
1776                 .name = "dpio-common",
1777                 .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,
1778                 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
1779                 .ops = &vlv_dpio_cmn_power_well_ops,
1780         },
1781 };
1782
1783 static struct i915_power_well chv_power_wells[] = {
1784         {
1785                 .name = "always-on",
1786                 .always_on = 1,
1787                 .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
1788                 .ops = &i9xx_always_on_power_well_ops,
1789         },
1790         {
1791                 .name = "display",
1792                 /*
1793                  * Pipe A power well is the new disp2d well. Pipe B and C
1794                  * power wells don't actually exist. Pipe A power well is
1795                  * required for any pipe to work.
1796                  */
1797                 .domains = VLV_DISPLAY_POWER_DOMAINS,
1798                 .data = PIPE_A,
1799                 .ops = &chv_pipe_power_well_ops,
1800         },
1801         {
1802                 .name = "dpio-common-bc",
1803                 .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS,
1804                 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
1805                 .ops = &chv_dpio_cmn_power_well_ops,
1806         },
1807         {
1808                 .name = "dpio-common-d",
1809                 .domains = CHV_DPIO_CMN_D_POWER_DOMAINS,
1810                 .data = PUNIT_POWER_WELL_DPIO_CMN_D,
1811                 .ops = &chv_dpio_cmn_power_well_ops,
1812         },
1813 };
1814
1815 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
1816                                     int power_well_id)
1817 {
1818         struct i915_power_well *power_well;
1819         bool ret;
1820
1821         power_well = lookup_power_well(dev_priv, power_well_id);
1822         ret = power_well->ops->is_enabled(dev_priv, power_well);
1823
1824         return ret;
1825 }
1826
1827 static struct i915_power_well skl_power_wells[] = {
1828         {
1829                 .name = "always-on",
1830                 .always_on = 1,
1831                 .domains = SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS,
1832                 .ops = &i9xx_always_on_power_well_ops,
1833                 .data = SKL_DISP_PW_ALWAYS_ON,
1834         },
1835         {
1836                 .name = "power well 1",
1837                 /* Handled by the DMC firmware */
1838                 .domains = 0,
1839                 .ops = &skl_power_well_ops,
1840                 .data = SKL_DISP_PW_1,
1841         },
1842         {
1843                 .name = "MISC IO power well",
1844                 /* Handled by the DMC firmware */
1845                 .domains = 0,
1846                 .ops = &skl_power_well_ops,
1847                 .data = SKL_DISP_PW_MISC_IO,
1848         },
1849         {
1850                 .name = "DC off",
1851                 .domains = SKL_DISPLAY_DC_OFF_POWER_DOMAINS,
1852                 .ops = &gen9_dc_off_power_well_ops,
1853                 .data = SKL_DISP_PW_DC_OFF,
1854         },
1855         {
1856                 .name = "power well 2",
1857                 .domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS,
1858                 .ops = &skl_power_well_ops,
1859                 .data = SKL_DISP_PW_2,
1860         },
1861         {
1862                 .name = "DDI A/E power well",
1863                 .domains = SKL_DISPLAY_DDI_A_E_POWER_DOMAINS,
1864                 .ops = &skl_power_well_ops,
1865                 .data = SKL_DISP_PW_DDI_A_E,
1866         },
1867         {
1868                 .name = "DDI B power well",
1869                 .domains = SKL_DISPLAY_DDI_B_POWER_DOMAINS,
1870                 .ops = &skl_power_well_ops,
1871                 .data = SKL_DISP_PW_DDI_B,
1872         },
1873         {
1874                 .name = "DDI C power well",
1875                 .domains = SKL_DISPLAY_DDI_C_POWER_DOMAINS,
1876                 .ops = &skl_power_well_ops,
1877                 .data = SKL_DISP_PW_DDI_C,
1878         },
1879         {
1880                 .name = "DDI D power well",
1881                 .domains = SKL_DISPLAY_DDI_D_POWER_DOMAINS,
1882                 .ops = &skl_power_well_ops,
1883                 .data = SKL_DISP_PW_DDI_D,
1884         },
1885 };
1886
1887 void skl_pw1_misc_io_init(struct drm_i915_private *dev_priv)
1888 {
1889         struct i915_power_well *well;
1890
1891         if (!(IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)))
1892                 return;
1893
1894         well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
1895         intel_power_well_enable(dev_priv, well);
1896
1897         well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);
1898         intel_power_well_enable(dev_priv, well);
1899 }
1900
1901 void skl_pw1_misc_io_fini(struct drm_i915_private *dev_priv)
1902 {
1903         struct i915_power_well *well;
1904
1905         if (!(IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)))
1906                 return;
1907
1908         well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
1909         intel_power_well_disable(dev_priv, well);
1910
1911         well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);
1912         intel_power_well_disable(dev_priv, well);
1913 }
1914
1915 static struct i915_power_well bxt_power_wells[] = {
1916         {
1917                 .name = "always-on",
1918                 .always_on = 1,
1919                 .domains = BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS,
1920                 .ops = &i9xx_always_on_power_well_ops,
1921         },
1922         {
1923                 .name = "power well 1",
1924                 .domains = BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS,
1925                 .ops = &skl_power_well_ops,
1926                 .data = SKL_DISP_PW_1,
1927         },
1928         {
1929                 .name = "DC off",
1930                 .domains = BXT_DISPLAY_DC_OFF_POWER_DOMAINS,
1931                 .ops = &gen9_dc_off_power_well_ops,
1932                 .data = SKL_DISP_PW_DC_OFF,
1933         },
1934         {
1935                 .name = "power well 2",
1936                 .domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS,
1937                 .ops = &skl_power_well_ops,
1938                 .data = SKL_DISP_PW_2,
1939         },
1940 };
1941
1942 static int
1943 sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv,
1944                                    int disable_power_well)
1945 {
1946         if (disable_power_well >= 0)
1947                 return !!disable_power_well;
1948
1949         if (IS_BROXTON(dev_priv)) {
1950                 DRM_DEBUG_KMS("Disabling display power well support\n");
1951                 return 0;
1952         }
1953
1954         return 1;
1955 }
1956
1957 static uint32_t get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
1958                                     int enable_dc)
1959 {
1960         uint32_t mask;
1961         int requested_dc;
1962         int max_dc;
1963
1964         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
1965                 max_dc = 2;
1966                 mask = 0;
1967         } else if (IS_BROXTON(dev_priv)) {
1968                 max_dc = 1;
1969                 /*
1970                  * DC9 has a separate HW flow from the rest of the DC states,
1971                  * not depending on the DMC firmware. It's needed by system
1972                  * suspend/resume, so allow it unconditionally.
1973                  */
1974                 mask = DC_STATE_EN_DC9;
1975         } else {
1976                 max_dc = 0;
1977                 mask = 0;
1978         }
1979
1980         if (!i915.disable_power_well)
1981                 max_dc = 0;
1982
1983         if (enable_dc >= 0 && enable_dc <= max_dc) {
1984                 requested_dc = enable_dc;
1985         } else if (enable_dc == -1) {
1986                 requested_dc = max_dc;
1987         } else if (enable_dc > max_dc && enable_dc <= 2) {
1988                 DRM_DEBUG_KMS("Adjusting requested max DC state (%d->%d)\n",
1989                               enable_dc, max_dc);
1990                 requested_dc = max_dc;
1991         } else {
1992                 DRM_ERROR("Unexpected value for enable_dc (%d)\n", enable_dc);
1993                 requested_dc = max_dc;
1994         }
1995
1996         if (requested_dc > 1)
1997                 mask |= DC_STATE_EN_UPTO_DC6;
1998         if (requested_dc > 0)
1999                 mask |= DC_STATE_EN_UPTO_DC5;
2000
2001         DRM_DEBUG_KMS("Allowed DC state mask %02x\n", mask);
2002
2003         return mask;
2004 }
2005
2006 #define set_power_wells(power_domains, __power_wells) ({                \
2007         (power_domains)->power_wells = (__power_wells);                 \
2008         (power_domains)->power_well_count = ARRAY_SIZE(__power_wells);  \
2009 })
2010
2011 /**
2012  * intel_power_domains_init - initializes the power domain structures
2013  * @dev_priv: i915 device instance
2014  *
2015  * Initializes the power domain structures for @dev_priv depending upon the
2016  * supported platform.
2017  */
2018 int intel_power_domains_init(struct drm_i915_private *dev_priv)
2019 {
2020         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2021
2022         i915.disable_power_well = sanitize_disable_power_well_option(dev_priv,
2023                                                      i915.disable_power_well);
2024         dev_priv->csr.allowed_dc_mask = get_allowed_dc_mask(dev_priv,
2025                                                             i915.enable_dc);
2026
2027         BUILD_BUG_ON(POWER_DOMAIN_NUM > 31);
2028
2029         mutex_init(&power_domains->lock);
2030
2031         /*
2032          * The enabling order will be from lower to higher indexed wells,
2033          * the disabling order is reversed.
2034          */
2035         if (IS_HASWELL(dev_priv->dev)) {
2036                 set_power_wells(power_domains, hsw_power_wells);
2037         } else if (IS_BROADWELL(dev_priv->dev)) {
2038                 set_power_wells(power_domains, bdw_power_wells);
2039         } else if (IS_SKYLAKE(dev_priv->dev) || IS_KABYLAKE(dev_priv->dev)) {
2040                 set_power_wells(power_domains, skl_power_wells);
2041         } else if (IS_BROXTON(dev_priv->dev)) {
2042                 set_power_wells(power_domains, bxt_power_wells);
2043         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
2044                 set_power_wells(power_domains, chv_power_wells);
2045         } else if (IS_VALLEYVIEW(dev_priv->dev)) {
2046                 set_power_wells(power_domains, vlv_power_wells);
2047         } else {
2048                 set_power_wells(power_domains, i9xx_always_on_power_well);
2049         }
2050
2051         return 0;
2052 }
2053
2054 /**
2055  * intel_power_domains_fini - finalizes the power domain structures
2056  * @dev_priv: i915 device instance
2057  *
2058  * Finalizes the power domain structures for @dev_priv depending upon the
2059  * supported platform. This function also disables runtime pm and ensures that
2060  * the device stays powered up so that the driver can be reloaded.
2061  */
2062 void intel_power_domains_fini(struct drm_i915_private *dev_priv)
2063 {
2064         struct device *device = &dev_priv->dev->pdev->dev;
2065
2066         /*
2067          * The i915.ko module is still not prepared to be loaded when
2068          * the power well is not enabled, so just enable it in case
2069          * we're going to unload/reload.
2070          * The following also reacquires the RPM reference the core passed
2071          * to the driver during loading, which is dropped in
2072          * intel_runtime_pm_enable(). We have to hand back the control of the
2073          * device to the core with this reference held.
2074          */
2075         intel_display_set_init_power(dev_priv, true);
2076
2077         /* Remove the refcount we took to keep power well support disabled. */
2078         if (!i915.disable_power_well)
2079                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
2080
2081         /*
2082          * Remove the refcount we took in intel_runtime_pm_enable() in case
2083          * the platform doesn't support runtime PM.
2084          */
2085         if (!HAS_RUNTIME_PM(dev_priv))
2086                 pm_runtime_put(device);
2087 }
2088
2089 static void intel_power_domains_sync_hw(struct drm_i915_private *dev_priv)
2090 {
2091         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2092         struct i915_power_well *power_well;
2093         int i;
2094
2095         mutex_lock(&power_domains->lock);
2096         for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
2097                 power_well->ops->sync_hw(dev_priv, power_well);
2098                 power_well->hw_enabled = power_well->ops->is_enabled(dev_priv,
2099                                                                      power_well);
2100         }
2101         mutex_unlock(&power_domains->lock);
2102 }
2103
2104 static void skl_display_core_init(struct drm_i915_private *dev_priv,
2105                                   bool resume)
2106 {
2107         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2108         uint32_t val;
2109
2110         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
2111
2112         /* enable PCH reset handshake */
2113         val = I915_READ(HSW_NDE_RSTWRN_OPT);
2114         I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
2115
2116         /* enable PG1 and Misc I/O */
2117         mutex_lock(&power_domains->lock);
2118         skl_pw1_misc_io_init(dev_priv);
2119         mutex_unlock(&power_domains->lock);
2120
2121         if (!resume)
2122                 return;
2123
2124         skl_init_cdclk(dev_priv);
2125
2126         if (dev_priv->csr.dmc_payload)
2127                 intel_csr_load_program(dev_priv);
2128 }
2129
2130 static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
2131 {
2132         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2133
2134         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
2135
2136         skl_uninit_cdclk(dev_priv);
2137
2138         /* The spec doesn't call for removing the reset handshake flag */
2139         /* disable PG1 and Misc I/O */
2140         mutex_lock(&power_domains->lock);
2141         skl_pw1_misc_io_fini(dev_priv);
2142         mutex_unlock(&power_domains->lock);
2143 }
2144
2145 static void chv_phy_control_init(struct drm_i915_private *dev_priv)
2146 {
2147         struct i915_power_well *cmn_bc =
2148                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
2149         struct i915_power_well *cmn_d =
2150                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D);
2151
2152         /*
2153          * DISPLAY_PHY_CONTROL can get corrupted if read. As a
2154          * workaround never ever read DISPLAY_PHY_CONTROL, and
2155          * instead maintain a shadow copy ourselves. Use the actual
2156          * power well state and lane status to reconstruct the
2157          * expected initial value.
2158          */
2159         dev_priv->chv_phy_control =
2160                 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY0) |
2161                 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY1) |
2162                 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH0) |
2163                 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH1) |
2164                 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY1, DPIO_CH0);
2165
2166         /*
2167          * If all lanes are disabled we leave the override disabled
2168          * with all power down bits cleared to match the state we
2169          * would use after disabling the port. Otherwise enable the
2170          * override and set the lane powerdown bits accding to the
2171          * current lane status.
2172          */
2173         if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) {
2174                 uint32_t status = I915_READ(DPLL(PIPE_A));
2175                 unsigned int mask;
2176
2177                 mask = status & DPLL_PORTB_READY_MASK;
2178                 if (mask == 0xf)
2179                         mask = 0x0;
2180                 else
2181                         dev_priv->chv_phy_control |=
2182                                 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0);
2183
2184                 dev_priv->chv_phy_control |=
2185                         PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH0);
2186
2187                 mask = (status & DPLL_PORTC_READY_MASK) >> 4;
2188                 if (mask == 0xf)
2189                         mask = 0x0;
2190                 else
2191                         dev_priv->chv_phy_control |=
2192                                 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1);
2193
2194                 dev_priv->chv_phy_control |=
2195                         PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH1);
2196
2197                 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0);
2198
2199                 dev_priv->chv_phy_assert[DPIO_PHY0] = false;
2200         } else {
2201                 dev_priv->chv_phy_assert[DPIO_PHY0] = true;
2202         }
2203
2204         if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) {
2205                 uint32_t status = I915_READ(DPIO_PHY_STATUS);
2206                 unsigned int mask;
2207
2208                 mask = status & DPLL_PORTD_READY_MASK;
2209
2210                 if (mask == 0xf)
2211                         mask = 0x0;
2212                 else
2213                         dev_priv->chv_phy_control |=
2214                                 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0);
2215
2216                 dev_priv->chv_phy_control |=
2217                         PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY1, DPIO_CH0);
2218
2219                 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1);
2220
2221                 dev_priv->chv_phy_assert[DPIO_PHY1] = false;
2222         } else {
2223                 dev_priv->chv_phy_assert[DPIO_PHY1] = true;
2224         }
2225
2226         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
2227
2228         DRM_DEBUG_KMS("Initial PHY_CONTROL=0x%08x\n",
2229                       dev_priv->chv_phy_control);
2230 }
2231
2232 static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv)
2233 {
2234         struct i915_power_well *cmn =
2235                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
2236         struct i915_power_well *disp2d =
2237                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D);
2238
2239         /* If the display might be already active skip this */
2240         if (cmn->ops->is_enabled(dev_priv, cmn) &&
2241             disp2d->ops->is_enabled(dev_priv, disp2d) &&
2242             I915_READ(DPIO_CTL) & DPIO_CMNRST)
2243                 return;
2244
2245         DRM_DEBUG_KMS("toggling display PHY side reset\n");
2246
2247         /* cmnlane needs DPLL registers */
2248         disp2d->ops->enable(dev_priv, disp2d);
2249
2250         /*
2251          * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx:
2252          * Need to assert and de-assert PHY SB reset by gating the
2253          * common lane power, then un-gating it.
2254          * Simply ungating isn't enough to reset the PHY enough to get
2255          * ports and lanes running.
2256          */
2257         cmn->ops->disable(dev_priv, cmn);
2258 }
2259
2260 /**
2261  * intel_power_domains_init_hw - initialize hardware power domain state
2262  * @dev_priv: i915 device instance
2263  *
2264  * This function initializes the hardware power domain state and enables all
2265  * power domains using intel_display_set_init_power().
2266  */
2267 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume)
2268 {
2269         struct drm_device *dev = dev_priv->dev;
2270         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2271
2272         power_domains->initializing = true;
2273
2274         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
2275                 skl_display_core_init(dev_priv, resume);
2276         } else if (IS_CHERRYVIEW(dev)) {
2277                 mutex_lock(&power_domains->lock);
2278                 chv_phy_control_init(dev_priv);
2279                 mutex_unlock(&power_domains->lock);
2280         } else if (IS_VALLEYVIEW(dev)) {
2281                 mutex_lock(&power_domains->lock);
2282                 vlv_cmnlane_wa(dev_priv);
2283                 mutex_unlock(&power_domains->lock);
2284         }
2285
2286         /* For now, we need the power well to be always enabled. */
2287         intel_display_set_init_power(dev_priv, true);
2288         /* Disable power support if the user asked so. */
2289         if (!i915.disable_power_well)
2290                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
2291         intel_power_domains_sync_hw(dev_priv);
2292         power_domains->initializing = false;
2293 }
2294
2295 /**
2296  * intel_power_domains_suspend - suspend power domain state
2297  * @dev_priv: i915 device instance
2298  *
2299  * This function prepares the hardware power domain state before entering
2300  * system suspend. It must be paired with intel_power_domains_init_hw().
2301  */
2302 void intel_power_domains_suspend(struct drm_i915_private *dev_priv)
2303 {
2304         /*
2305          * Even if power well support was disabled we still want to disable
2306          * power wells while we are system suspended.
2307          */
2308         if (!i915.disable_power_well)
2309                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
2310
2311         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
2312                 skl_display_core_uninit(dev_priv);
2313 }
2314
2315 /**
2316  * intel_runtime_pm_get - grab a runtime pm reference
2317  * @dev_priv: i915 device instance
2318  *
2319  * This function grabs a device-level runtime pm reference (mostly used for GEM
2320  * code to ensure the GTT or GT is on) and ensures that it is powered up.
2321  *
2322  * Any runtime pm reference obtained by this function must have a symmetric
2323  * call to intel_runtime_pm_put() to release the reference again.
2324  */
2325 void intel_runtime_pm_get(struct drm_i915_private *dev_priv)
2326 {
2327         struct drm_device *dev = dev_priv->dev;
2328         struct device *device = &dev->pdev->dev;
2329
2330         pm_runtime_get_sync(device);
2331
2332         atomic_inc(&dev_priv->pm.wakeref_count);
2333         assert_rpm_wakelock_held(dev_priv);
2334 }
2335
2336 /**
2337  * intel_runtime_pm_get_if_in_use - grab a runtime pm reference if device in use
2338  * @dev_priv: i915 device instance
2339  *
2340  * This function grabs a device-level runtime pm reference if the device is
2341  * already in use and ensures that it is powered up.
2342  *
2343  * Any runtime pm reference obtained by this function must have a symmetric
2344  * call to intel_runtime_pm_put() to release the reference again.
2345  */
2346 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv)
2347 {
2348         struct drm_device *dev = dev_priv->dev;
2349         struct device *device = &dev->pdev->dev;
2350
2351         if (IS_ENABLED(CONFIG_PM)) {
2352                 int ret = pm_runtime_get_if_in_use(device);
2353
2354                 /*
2355                  * In cases runtime PM is disabled by the RPM core and we get
2356                  * an -EINVAL return value we are not supposed to call this
2357                  * function, since the power state is undefined. This applies
2358                  * atm to the late/early system suspend/resume handlers.
2359                  */
2360                 WARN_ON_ONCE(ret < 0);
2361                 if (ret <= 0)
2362                         return false;
2363         }
2364
2365         atomic_inc(&dev_priv->pm.wakeref_count);
2366         assert_rpm_wakelock_held(dev_priv);
2367
2368         return true;
2369 }
2370
2371 /**
2372  * intel_runtime_pm_get_noresume - grab a runtime pm reference
2373  * @dev_priv: i915 device instance
2374  *
2375  * This function grabs a device-level runtime pm reference (mostly used for GEM
2376  * code to ensure the GTT or GT is on).
2377  *
2378  * It will _not_ power up the device but instead only check that it's powered
2379  * on.  Therefore it is only valid to call this functions from contexts where
2380  * the device is known to be powered up and where trying to power it up would
2381  * result in hilarity and deadlocks. That pretty much means only the system
2382  * suspend/resume code where this is used to grab runtime pm references for
2383  * delayed setup down in work items.
2384  *
2385  * Any runtime pm reference obtained by this function must have a symmetric
2386  * call to intel_runtime_pm_put() to release the reference again.
2387  */
2388 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv)
2389 {
2390         struct drm_device *dev = dev_priv->dev;
2391         struct device *device = &dev->pdev->dev;
2392
2393         assert_rpm_wakelock_held(dev_priv);
2394         pm_runtime_get_noresume(device);
2395
2396         atomic_inc(&dev_priv->pm.wakeref_count);
2397 }
2398
2399 /**
2400  * intel_runtime_pm_put - release a runtime pm reference
2401  * @dev_priv: i915 device instance
2402  *
2403  * This function drops the device-level runtime pm reference obtained by
2404  * intel_runtime_pm_get() and might power down the corresponding
2405  * hardware block right away if this is the last reference.
2406  */
2407 void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
2408 {
2409         struct drm_device *dev = dev_priv->dev;
2410         struct device *device = &dev->pdev->dev;
2411
2412         assert_rpm_wakelock_held(dev_priv);
2413         if (atomic_dec_and_test(&dev_priv->pm.wakeref_count))
2414                 atomic_inc(&dev_priv->pm.atomic_seq);
2415
2416         pm_runtime_mark_last_busy(device);
2417         pm_runtime_put_autosuspend(device);
2418 }
2419
2420 /**
2421  * intel_runtime_pm_enable - enable runtime pm
2422  * @dev_priv: i915 device instance
2423  *
2424  * This function enables runtime pm at the end of the driver load sequence.
2425  *
2426  * Note that this function does currently not enable runtime pm for the
2427  * subordinate display power domains. That is only done on the first modeset
2428  * using intel_display_set_init_power().
2429  */
2430 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv)
2431 {
2432         struct drm_device *dev = dev_priv->dev;
2433         struct device *device = &dev->pdev->dev;
2434
2435         pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */
2436         pm_runtime_mark_last_busy(device);
2437
2438         /*
2439          * Take a permanent reference to disable the RPM functionality and drop
2440          * it only when unloading the driver. Use the low level get/put helpers,
2441          * so the driver's own RPM reference tracking asserts also work on
2442          * platforms without RPM support.
2443          */
2444         if (!HAS_RUNTIME_PM(dev)) {
2445                 pm_runtime_dont_use_autosuspend(device);
2446                 pm_runtime_get_sync(device);
2447         } else {
2448                 pm_runtime_use_autosuspend(device);
2449         }
2450
2451         /*
2452          * The core calls the driver load handler with an RPM reference held.
2453          * We drop that here and will reacquire it during unloading in
2454          * intel_power_domains_fini().
2455          */
2456         pm_runtime_put_autosuspend(device);
2457 }
2458