drivers/gpu/drm/i915/intel_runtime_pm.c

   1 /*
   2  * Copyright © 2012-2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *    Daniel Vetter <daniel.vetter@ffwll.ch>
  26  *
  27  */
  28
  29 #include <linux/pm_runtime.h>
  30 #include <linux/vgaarb.h>
  31
  32 #include "i915_drv.h"
  33 #include "intel_drv.h"
  34
  35 /**
  36  * DOC: runtime pm
  37  *
  38  * The i915 driver supports dynamic enabling and disabling of entire hardware
  39  * blocks at runtime. This is especially important on the display side where
  40  * software is supposed to control many power gates manually on recent hardware,
  41  * since on the GT side a lot of the power management is done by the hardware.
  42  * But even there some manual control at the device level is required.
  43  *
  44  * Since i915 supports a diverse set of platforms with a unified codebase and
  45  * hardware engineers just love to shuffle functionality around between power
  46  * domains there's a sizeable amount of indirection required. This file provides
  47  * generic functions to the driver for grabbing and releasing references for
  48  * abstract power domains. It then maps those to the actual power wells
  49  * present for a given platform.
  50  */
  51
  52 #define for_each_power_well(i, power_well, domain_mask, power_domains)  \
  53         for (i = 0;                                                     \
  54              i < (power_domains)->power_well_count &&                   \
  55                  ((power_well) = &(power_domains)->power_wells[i]);     \
  56              i++)                                                       \
  57                 for_each_if ((power_well)->domains & (domain_mask))
  58
  59 #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
  60         for (i = (power_domains)->power_well_count - 1;                  \
  61              i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
  62              i--)                                                        \
  63                 for_each_if ((power_well)->domains & (domain_mask))
  64
  65 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
  66                                     int power_well_id);
  67
  68 const char *
  69 intel_display_power_domain_str(enum intel_display_power_domain domain)
  70 {
  71         switch (domain) {
  72         case POWER_DOMAIN_PIPE_A:
  73                 return "PIPE_A";
  74         case POWER_DOMAIN_PIPE_B:
  75                 return "PIPE_B";
  76         case POWER_DOMAIN_PIPE_C:
  77                 return "PIPE_C";
  78         case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
  79                 return "PIPE_A_PANEL_FITTER";
  80         case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
  81                 return "PIPE_B_PANEL_FITTER";
  82         case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
  83                 return "PIPE_C_PANEL_FITTER";
  84         case POWER_DOMAIN_TRANSCODER_A:
  85                 return "TRANSCODER_A";
  86         case POWER_DOMAIN_TRANSCODER_B:
  87                 return "TRANSCODER_B";
  88         case POWER_DOMAIN_TRANSCODER_C:
  89                 return "TRANSCODER_C";
  90         case POWER_DOMAIN_TRANSCODER_EDP:
  91                 return "TRANSCODER_EDP";
  92         case POWER_DOMAIN_PORT_DDI_A_LANES:
  93                 return "PORT_DDI_A_LANES";
  94         case POWER_DOMAIN_PORT_DDI_B_LANES:
  95                 return "PORT_DDI_B_LANES";
  96         case POWER_DOMAIN_PORT_DDI_C_LANES:
  97                 return "PORT_DDI_C_LANES";
  98         case POWER_DOMAIN_PORT_DDI_D_LANES:
  99                 return "PORT_DDI_D_LANES";
 100         case POWER_DOMAIN_PORT_DDI_E_LANES:
 101                 return "PORT_DDI_E_LANES";
 102         case POWER_DOMAIN_PORT_DSI:
 103                 return "PORT_DSI";
 104         case POWER_DOMAIN_PORT_CRT:
 105                 return "PORT_CRT";
 106         case POWER_DOMAIN_PORT_OTHER:
 107                 return "PORT_OTHER";
 108         case POWER_DOMAIN_VGA:
 109                 return "VGA";
 110         case POWER_DOMAIN_AUDIO:
 111                 return "AUDIO";
 112         case POWER_DOMAIN_PLLS:
 113                 return "PLLS";
 114         case POWER_DOMAIN_AUX_A:
 115                 return "AUX_A";
 116         case POWER_DOMAIN_AUX_B:
 117                 return "AUX_B";
 118         case POWER_DOMAIN_AUX_C:
 119                 return "AUX_C";
 120         case POWER_DOMAIN_AUX_D:
 121                 return "AUX_D";
 122         case POWER_DOMAIN_GMBUS:
 123                 return "GMBUS";
 124         case POWER_DOMAIN_INIT:
 125                 return "INIT";
 126         case POWER_DOMAIN_MODESET:
 127                 return "MODESET";
 128         default:
 129                 MISSING_CASE(domain);
 130                 return "?";
 131         }
 132 }
 133
 134 static void intel_power_well_enable(struct drm_i915_private *dev_priv,
 135                                     struct i915_power_well *power_well)
 136 {
 137         DRM_DEBUG_KMS("enabling %s\n", power_well->name);
 138         power_well->ops->enable(dev_priv, power_well);
 139         power_well->hw_enabled = true;
 140 }
 141
 142 static void intel_power_well_disable(struct drm_i915_private *dev_priv,
 143                                      struct i915_power_well *power_well)
 144 {
 145         DRM_DEBUG_KMS("disabling %s\n", power_well->name);
 146         power_well->hw_enabled = false;
 147         power_well->ops->disable(dev_priv, power_well);
 148 }
 149
 150 /*
 151  * We should only use the power well if we explicitly asked the hardware to
 152  * enable it, so check if it's enabled and also check if we've requested it to
 153  * be enabled.
 154  */
 155 static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
 156                                    struct i915_power_well *power_well)
 157 {
 158         return I915_READ(HSW_PWR_WELL_DRIVER) ==
 159                      (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
 160 }
 161
 162 /**
 163  * __intel_display_power_is_enabled - unlocked check for a power domain
 164  * @dev_priv: i915 device instance
 165  * @domain: power domain to check
 166  *
 167  * This is the unlocked version of intel_display_power_is_enabled() and should
 168  * only be used from error capture and recovery code where deadlocks are
 169  * possible.
 170  *
 171  * Returns:
 172  * True when the power domain is enabled, false otherwise.
 173  */
 174 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
 175                                       enum intel_display_power_domain domain)
 176 {
 177         struct i915_power_domains *power_domains;
 178         struct i915_power_well *power_well;
 179         bool is_enabled;
 180         int i;
 181
 182         if (dev_priv->pm.suspended)
 183                 return false;
 184
 185         power_domains = &dev_priv->power_domains;
 186
 187         is_enabled = true;
 188
 189         for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
 190                 if (power_well->always_on)
 191                         continue;
 192
 193                 if (!power_well->hw_enabled) {
 194                         is_enabled = false;
 195                         break;
 196                 }
 197         }
 198
 199         return is_enabled;
 200 }
 201
 202 /**
 203  * intel_display_power_is_enabled - check for a power domain
 204  * @dev_priv: i915 device instance
 205  * @domain: power domain to check
 206  *
 207  * This function can be used to check the hw power domain state. It is mostly
 208  * used in hardware state readout functions. Everywhere else code should rely
 209  * upon explicit power domain reference counting to ensure that the hardware
 210  * block is powered up before accessing it.
 211  *
 212  * Callers must hold the relevant modesetting locks to ensure that concurrent
 213  * threads can't disable the power well while the caller tries to read a few
 214  * registers.
 215  *
 216  * Returns:
 217  * True when the power domain is enabled, false otherwise.
 218  */
 219 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
 220                                     enum intel_display_power_domain domain)
 221 {
 222         struct i915_power_domains *power_domains;
 223         bool ret;
 224
 225         power_domains = &dev_priv->power_domains;
 226
 227         mutex_lock(&power_domains->lock);
 228         ret = __intel_display_power_is_enabled(dev_priv, domain);
 229         mutex_unlock(&power_domains->lock);
 230
 231         return ret;
 232 }
 233
 234 /**
 235  * intel_display_set_init_power - set the initial power domain state
 236  * @dev_priv: i915 device instance
 237  * @enable: whether to enable or disable the initial power domain state
 238  *
 239  * For simplicity our driver load/unload and system suspend/resume code assumes
 240  * that all power domains are always enabled. This functions controls the state
 241  * of this little hack. While the initial power domain state is enabled runtime
 242  * pm is effectively disabled.
 243  */
 244 void intel_display_set_init_power(struct drm_i915_private *dev_priv,
 245                                   bool enable)
 246 {
 247         if (dev_priv->power_domains.init_power_on == enable)
 248                 return;
 249
 250         if (enable)
 251                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
 252         else
 253                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
 254
 255         dev_priv->power_domains.init_power_on = enable;
 256 }
 257
 258 /*
 259  * Starting with Haswell, we have a "Power Down Well" that can be turned off
 260  * when not needed anymore. We have 4 registers that can request the power well
 261  * to be enabled, and it will only be disabled if none of the registers is
 262  * requesting it to be enabled.
 263  */
 264 static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
 265 {
 266         struct drm_device *dev = dev_priv->dev;
 267
 268         /*
 269          * After we re-enable the power well, if we touch VGA register 0x3d5
 270          * we'll get unclaimed register interrupts. This stops after we write
 271          * anything to the VGA MSR register. The vgacon module uses this
 272          * register all the time, so if we unbind our driver and, as a
 273          * consequence, bind vgacon, we'll get stuck in an infinite loop at
 274          * console_unlock(). So make here we touch the VGA MSR register, making
 275          * sure vgacon can keep working normally without triggering interrupts
 276          * and error messages.
 277          */
 278         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
 279         outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
 280         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
 281
 282         if (IS_BROADWELL(dev))
 283                 gen8_irq_power_well_post_enable(dev_priv,
 284                                                 1 << PIPE_C | 1 << PIPE_B);
 285 }
 286
 287 static void skl_power_well_post_enable(struct drm_i915_private *dev_priv,
 288                                        struct i915_power_well *power_well)
 289 {
 290         struct drm_device *dev = dev_priv->dev;
 291
 292         /*
 293          * After we re-enable the power well, if we touch VGA register 0x3d5
 294          * we'll get unclaimed register interrupts. This stops after we write
 295          * anything to the VGA MSR register. The vgacon module uses this
 296          * register all the time, so if we unbind our driver and, as a
 297          * consequence, bind vgacon, we'll get stuck in an infinite loop at
 298          * console_unlock(). So make here we touch the VGA MSR register, making
 299          * sure vgacon can keep working normally without triggering interrupts
 300          * and error messages.
 301          */
 302         if (power_well->data == SKL_DISP_PW_2) {
 303                 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
 304                 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
 305                 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
 306
 307                 gen8_irq_power_well_post_enable(dev_priv,
 308                                                 1 << PIPE_C | 1 << PIPE_B);
 309         }
 310 }
 311
 312 static void hsw_set_power_well(struct drm_i915_private *dev_priv,
 313                                struct i915_power_well *power_well, bool enable)
 314 {
 315         bool is_enabled, enable_requested;
 316         uint32_t tmp;
 317
 318         tmp = I915_READ(HSW_PWR_WELL_DRIVER);
 319         is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
 320         enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
 321
 322         if (enable) {
 323                 if (!enable_requested)
 324                         I915_WRITE(HSW_PWR_WELL_DRIVER,
 325                                    HSW_PWR_WELL_ENABLE_REQUEST);
 326
 327                 if (!is_enabled) {
 328                         DRM_DEBUG_KMS("Enabling power well\n");
 329                         if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
 330                                       HSW_PWR_WELL_STATE_ENABLED), 20))
 331                                 DRM_ERROR("Timeout enabling power well\n");
 332                         hsw_power_well_post_enable(dev_priv);
 333                 }
 334
 335         } else {
 336                 if (enable_requested) {
 337                         I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
 338                         POSTING_READ(HSW_PWR_WELL_DRIVER);
 339                         DRM_DEBUG_KMS("Requesting to disable the power well\n");
 340                 }
 341         }
 342 }
 343
 344 #define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS (         \
 345         BIT(POWER_DOMAIN_TRANSCODER_A) |                \
 346         BIT(POWER_DOMAIN_PIPE_B) |                      \
 347         BIT(POWER_DOMAIN_TRANSCODER_B) |                \
 348         BIT(POWER_DOMAIN_PIPE_C) |                      \
 349         BIT(POWER_DOMAIN_TRANSCODER_C) |                \
 350         BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |         \
 351         BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |         \
 352         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |            \
 353         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |            \
 354         BIT(POWER_DOMAIN_PORT_DDI_D_LANES) |            \
 355         BIT(POWER_DOMAIN_PORT_DDI_E_LANES) |            \
 356         BIT(POWER_DOMAIN_AUX_B) |                       \
 357         BIT(POWER_DOMAIN_AUX_C) |                       \
 358         BIT(POWER_DOMAIN_AUX_D) |                       \
 359         BIT(POWER_DOMAIN_AUDIO) |                       \
 360         BIT(POWER_DOMAIN_VGA) |                         \
 361         BIT(POWER_DOMAIN_INIT))
 362 #define SKL_DISPLAY_DDI_A_E_POWER_DOMAINS (             \
 363         BIT(POWER_DOMAIN_PORT_DDI_A_LANES) |            \
 364         BIT(POWER_DOMAIN_PORT_DDI_E_LANES) |            \
 365         BIT(POWER_DOMAIN_INIT))
 366 #define SKL_DISPLAY_DDI_B_POWER_DOMAINS (               \
 367         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |            \
 368         BIT(POWER_DOMAIN_INIT))
 369 #define SKL_DISPLAY_DDI_C_POWER_DOMAINS (               \
 370         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |            \
 371         BIT(POWER_DOMAIN_INIT))
 372 #define SKL_DISPLAY_DDI_D_POWER_DOMAINS (               \
 373         BIT(POWER_DOMAIN_PORT_DDI_D_LANES) |            \
 374         BIT(POWER_DOMAIN_INIT))
 375 #define SKL_DISPLAY_DC_OFF_POWER_DOMAINS (              \
 376         SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS |         \
 377         BIT(POWER_DOMAIN_MODESET) |                     \
 378         BIT(POWER_DOMAIN_AUX_A) |                       \
 379         BIT(POWER_DOMAIN_INIT))
 380 #define SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS (           \
 381         (POWER_DOMAIN_MASK & ~(                         \
 382         SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS |         \
 383         SKL_DISPLAY_DC_OFF_POWER_DOMAINS)) |            \
 384         BIT(POWER_DOMAIN_INIT))
 385
 386 #define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS (         \
 387         BIT(POWER_DOMAIN_TRANSCODER_A) |                \
 388         BIT(POWER_DOMAIN_PIPE_B) |                      \
 389         BIT(POWER_DOMAIN_TRANSCODER_B) |                \
 390         BIT(POWER_DOMAIN_PIPE_C) |                      \
 391         BIT(POWER_DOMAIN_TRANSCODER_C) |                \
 392         BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |         \
 393         BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |         \
 394         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |            \
 395         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |            \
 396         BIT(POWER_DOMAIN_AUX_B) |                       \
 397         BIT(POWER_DOMAIN_AUX_C) |                       \
 398         BIT(POWER_DOMAIN_AUDIO) |                       \
 399         BIT(POWER_DOMAIN_VGA) |                         \
 400         BIT(POWER_DOMAIN_GMBUS) |                       \
 401         BIT(POWER_DOMAIN_INIT))
 402 #define BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS (         \
 403         BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS |         \
 404         BIT(POWER_DOMAIN_PIPE_A) |                      \
 405         BIT(POWER_DOMAIN_TRANSCODER_EDP) |              \
 406         BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) |         \
 407         BIT(POWER_DOMAIN_PORT_DDI_A_LANES) |            \
 408         BIT(POWER_DOMAIN_AUX_A) |                       \
 409         BIT(POWER_DOMAIN_PLLS) |                        \
 410         BIT(POWER_DOMAIN_INIT))
 411 #define BXT_DISPLAY_DC_OFF_POWER_DOMAINS (              \
 412         BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS |         \
 413         BIT(POWER_DOMAIN_MODESET) |                     \
 414         BIT(POWER_DOMAIN_AUX_A) |                       \
 415         BIT(POWER_DOMAIN_INIT))
 416 #define BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS (           \
 417         (POWER_DOMAIN_MASK & ~(BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS |  \
 418         BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS)) |       \
 419         BIT(POWER_DOMAIN_INIT))
 420
 421 static void assert_can_enable_dc9(struct drm_i915_private *dev_priv)
 422 {
 423         struct drm_device *dev = dev_priv->dev;
 424
 425         WARN(!IS_BROXTON(dev), "Platform doesn't support DC9.\n");
 426         WARN((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9),
 427                 "DC9 already programmed to be enabled.\n");
 428         WARN(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
 429                 "DC5 still not disabled to enable DC9.\n");
 430         WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on.\n");
 431         WARN(intel_irqs_enabled(dev_priv), "Interrupts not disabled yet.\n");
 432
 433          /*
 434           * TODO: check for the following to verify the conditions to enter DC9
 435           * state are satisfied:
 436           * 1] Check relevant display engine registers to verify if mode set
 437           * disable sequence was followed.
 438           * 2] Check if display uninitialize sequence is initialized.
 439           */
 440 }
 441
 442 static void assert_can_disable_dc9(struct drm_i915_private *dev_priv)
 443 {
 444         WARN(intel_irqs_enabled(dev_priv), "Interrupts not disabled yet.\n");
 445         WARN(!(I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9),
 446                 "DC9 already programmed to be disabled.\n");
 447         WARN(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
 448                 "DC5 still not disabled.\n");
 449
 450          /*
 451           * TODO: check for the following to verify DC9 state was indeed
 452           * entered before programming to disable it:
 453           * 1] Check relevant display engine registers to verify if mode
 454           *  set disable sequence was followed.
 455           * 2] Check if display uninitialize sequence is initialized.
 456           */
 457 }
 458
 459 static void gen9_set_dc_state_debugmask_memory_up(
 460                         struct drm_i915_private *dev_priv)
 461 {
 462         uint32_t val;
 463
 464         /* The below bit doesn't need to be cleared ever afterwards */
 465         val = I915_READ(DC_STATE_DEBUG);
 466         if (!(val & DC_STATE_DEBUG_MASK_MEMORY_UP)) {
 467                 val |= DC_STATE_DEBUG_MASK_MEMORY_UP;
 468                 I915_WRITE(DC_STATE_DEBUG, val);
 469                 POSTING_READ(DC_STATE_DEBUG);
 470         }
 471 }
 472
 473 static void gen9_set_dc_state(struct drm_i915_private *dev_priv, uint32_t state)
 474 {
 475         uint32_t val;
 476         uint32_t mask;
 477
 478         mask = DC_STATE_EN_UPTO_DC5;
 479         if (IS_BROXTON(dev_priv))
 480                 mask |= DC_STATE_EN_DC9;
 481         else
 482                 mask |= DC_STATE_EN_UPTO_DC6;
 483
 484         WARN_ON_ONCE(state & ~mask);
 485
 486         if (i915.enable_dc == 0)
 487                 state = DC_STATE_DISABLE;
 488         else if (i915.enable_dc == 1 && state > DC_STATE_EN_UPTO_DC5)
 489                 state = DC_STATE_EN_UPTO_DC5;
 490
 491         if (state & DC_STATE_EN_UPTO_DC5_DC6_MASK)
 492                 gen9_set_dc_state_debugmask_memory_up(dev_priv);
 493
 494         val = I915_READ(DC_STATE_EN);
 495         DRM_DEBUG_KMS("Setting DC state from %02x to %02x\n",
 496                       val & mask, state);
 497
 498         /* Check if DMC is ignoring our DC state requests */
 499         if ((val & mask) != dev_priv->csr.dc_state)
 500                 DRM_ERROR("DC state mismatch (0x%x -> 0x%x)\n",
 501                           dev_priv->csr.dc_state, val & mask);
 502
 503         val &= ~mask;
 504         val |= state;
 505         I915_WRITE(DC_STATE_EN, val);
 506         POSTING_READ(DC_STATE_EN);
 507
 508         dev_priv->csr.dc_state = val & mask;
 509 }
 510
 511 void bxt_enable_dc9(struct drm_i915_private *dev_priv)
 512 {
 513         assert_can_enable_dc9(dev_priv);
 514
 515         DRM_DEBUG_KMS("Enabling DC9\n");
 516
 517         gen9_set_dc_state(dev_priv, DC_STATE_EN_DC9);
 518 }
 519
 520 void bxt_disable_dc9(struct drm_i915_private *dev_priv)
 521 {
 522         assert_can_disable_dc9(dev_priv);
 523
 524         DRM_DEBUG_KMS("Disabling DC9\n");
 525
 526         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 527 }
 528
 529 static void assert_csr_loaded(struct drm_i915_private *dev_priv)
 530 {
 531         WARN_ONCE(!I915_READ(CSR_PROGRAM(0)),
 532                   "CSR program storage start is NULL\n");
 533         WARN_ONCE(!I915_READ(CSR_SSP_BASE), "CSR SSP Base Not fine\n");
 534         WARN_ONCE(!I915_READ(CSR_HTP_SKL), "CSR HTP Not fine\n");
 535 }
 536
 537 static void assert_can_enable_dc5(struct drm_i915_private *dev_priv)
 538 {
 539         struct drm_device *dev = dev_priv->dev;
 540         bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv,
 541                                         SKL_DISP_PW_2);
 542
 543         WARN_ONCE(!IS_SKYLAKE(dev) && !IS_KABYLAKE(dev),
 544                   "Platform doesn't support DC5.\n");
 545         WARN_ONCE(!HAS_RUNTIME_PM(dev), "Runtime PM not enabled.\n");
 546         WARN_ONCE(pg2_enabled, "PG2 not disabled to enable DC5.\n");
 547
 548         WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5),
 549                   "DC5 already programmed to be enabled.\n");
 550         assert_rpm_wakelock_held(dev_priv);
 551
 552         assert_csr_loaded(dev_priv);
 553 }
 554
 555 static void assert_can_disable_dc5(struct drm_i915_private *dev_priv)
 556 {
 557         /*
 558          * During initialization, the firmware may not be loaded yet.
 559          * We still want to make sure that the DC enabling flag is cleared.
 560          */
 561         if (dev_priv->power_domains.initializing)
 562                 return;
 563
 564         assert_rpm_wakelock_held(dev_priv);
 565 }
 566
 567 static void gen9_enable_dc5(struct drm_i915_private *dev_priv)
 568 {
 569         assert_can_enable_dc5(dev_priv);
 570
 571         DRM_DEBUG_KMS("Enabling DC5\n");
 572
 573         gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5);
 574 }
 575
 576 static void assert_can_enable_dc6(struct drm_i915_private *dev_priv)
 577 {
 578         struct drm_device *dev = dev_priv->dev;
 579
 580         WARN_ONCE(!IS_SKYLAKE(dev) && !IS_KABYLAKE(dev),
 581                   "Platform doesn't support DC6.\n");
 582         WARN_ONCE(!HAS_RUNTIME_PM(dev), "Runtime PM not enabled.\n");
 583         WARN_ONCE(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
 584                   "Backlight is not disabled.\n");
 585         WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6),
 586                   "DC6 already programmed to be enabled.\n");
 587
 588         assert_csr_loaded(dev_priv);
 589 }
 590
 591 static void assert_can_disable_dc6(struct drm_i915_private *dev_priv)
 592 {
 593         /*
 594          * During initialization, the firmware may not be loaded yet.
 595          * We still want to make sure that the DC enabling flag is cleared.
 596          */
 597         if (dev_priv->power_domains.initializing)
 598                 return;
 599
 600         WARN_ONCE(!(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6),
 601                   "DC6 already programmed to be disabled.\n");
 602 }
 603
 604 static void gen9_disable_dc5_dc6(struct drm_i915_private *dev_priv)
 605 {
 606         assert_can_disable_dc5(dev_priv);
 607
 608         if ((IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) &&
 609             i915.enable_dc != 0 && i915.enable_dc != 1)
 610                 assert_can_disable_dc6(dev_priv);
 611
 612         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 613 }
 614
 615 void skl_enable_dc6(struct drm_i915_private *dev_priv)
 616 {
 617         assert_can_enable_dc6(dev_priv);
 618
 619         DRM_DEBUG_KMS("Enabling DC6\n");
 620
 621         gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
 622
 623 }
 624
 625 void skl_disable_dc6(struct drm_i915_private *dev_priv)
 626 {
 627         assert_can_disable_dc6(dev_priv);
 628
 629         DRM_DEBUG_KMS("Disabling DC6\n");
 630
 631         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 632 }
 633
 634 static void skl_set_power_well(struct drm_i915_private *dev_priv,
 635                         struct i915_power_well *power_well, bool enable)
 636 {
 637         uint32_t tmp, fuse_status;
 638         uint32_t req_mask, state_mask;
 639         bool is_enabled, enable_requested, check_fuse_status = false;
 640
 641         tmp = I915_READ(HSW_PWR_WELL_DRIVER);
 642         fuse_status = I915_READ(SKL_FUSE_STATUS);
 643
 644         switch (power_well->data) {
 645         case SKL_DISP_PW_1:
 646                 if (wait_for((I915_READ(SKL_FUSE_STATUS) &
 647                         SKL_FUSE_PG0_DIST_STATUS), 1)) {
 648                         DRM_ERROR("PG0 not enabled\n");
 649                         return;
 650                 }
 651                 break;
 652         case SKL_DISP_PW_2:
 653                 if (!(fuse_status & SKL_FUSE_PG1_DIST_STATUS)) {
 654                         DRM_ERROR("PG1 in disabled state\n");
 655                         return;
 656                 }
 657                 break;
 658         case SKL_DISP_PW_DDI_A_E:
 659         case SKL_DISP_PW_DDI_B:
 660         case SKL_DISP_PW_DDI_C:
 661         case SKL_DISP_PW_DDI_D:
 662         case SKL_DISP_PW_MISC_IO:
 663                 break;
 664         default:
 665                 WARN(1, "Unknown power well %lu\n", power_well->data);
 666                 return;
 667         }
 668
 669         req_mask = SKL_POWER_WELL_REQ(power_well->data);
 670         enable_requested = tmp & req_mask;
 671         state_mask = SKL_POWER_WELL_STATE(power_well->data);
 672         is_enabled = tmp & state_mask;
 673
 674         if (enable) {
 675                 if (!enable_requested) {
 676                         WARN((tmp & state_mask) &&
 677                                 !I915_READ(HSW_PWR_WELL_BIOS),
 678                                 "Invalid for power well status to be enabled, unless done by the BIOS, \
 679                                 when request is to disable!\n");
 680                         I915_WRITE(HSW_PWR_WELL_DRIVER, tmp | req_mask);
 681                 }
 682
 683                 if (!is_enabled) {
 684                         DRM_DEBUG_KMS("Enabling %s\n", power_well->name);
 685                         if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
 686                                 state_mask), 1))
 687                                 DRM_ERROR("%s enable timeout\n",
 688                                         power_well->name);
 689                         check_fuse_status = true;
 690                 }
 691         } else {
 692                 if (enable_requested) {
 693                         I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask);
 694                         POSTING_READ(HSW_PWR_WELL_DRIVER);
 695                         DRM_DEBUG_KMS("Disabling %s\n", power_well->name);
 696                 }
 697         }
 698
 699         if (check_fuse_status) {
 700                 if (power_well->data == SKL_DISP_PW_1) {
 701                         if (wait_for((I915_READ(SKL_FUSE_STATUS) &
 702                                 SKL_FUSE_PG1_DIST_STATUS), 1))
 703                                 DRM_ERROR("PG1 distributing status timeout\n");
 704                 } else if (power_well->data == SKL_DISP_PW_2) {
 705                         if (wait_for((I915_READ(SKL_FUSE_STATUS) &
 706                                 SKL_FUSE_PG2_DIST_STATUS), 1))
 707                                 DRM_ERROR("PG2 distributing status timeout\n");
 708                 }
 709         }
 710
 711         if (enable && !is_enabled)
 712                 skl_power_well_post_enable(dev_priv, power_well);
 713 }
 714
 715 static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
 716                                    struct i915_power_well *power_well)
 717 {
 718         hsw_set_power_well(dev_priv, power_well, power_well->count > 0);
 719
 720         /*
 721          * We're taking over the BIOS, so clear any requests made by it since
 722          * the driver is in charge now.
 723          */
 724         if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
 725                 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
 726 }
 727
 728 static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
 729                                   struct i915_power_well *power_well)
 730 {
 731         hsw_set_power_well(dev_priv, power_well, true);
 732 }
 733
 734 static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
 735                                    struct i915_power_well *power_well)
 736 {
 737         hsw_set_power_well(dev_priv, power_well, false);
 738 }
 739
 740 static bool skl_power_well_enabled(struct drm_i915_private *dev_priv,
 741                                         struct i915_power_well *power_well)
 742 {
 743         uint32_t mask = SKL_POWER_WELL_REQ(power_well->data) |
 744                 SKL_POWER_WELL_STATE(power_well->data);
 745
 746         return (I915_READ(HSW_PWR_WELL_DRIVER) & mask) == mask;
 747 }
 748
 749 static void skl_power_well_sync_hw(struct drm_i915_private *dev_priv,
 750                                 struct i915_power_well *power_well)
 751 {
 752         skl_set_power_well(dev_priv, power_well, power_well->count > 0);
 753
 754         /* Clear any request made by BIOS as driver is taking over */
 755         I915_WRITE(HSW_PWR_WELL_BIOS, 0);
 756 }
 757
 758 static void skl_power_well_enable(struct drm_i915_private *dev_priv,
 759                                 struct i915_power_well *power_well)
 760 {
 761         skl_set_power_well(dev_priv, power_well, true);
 762 }
 763
 764 static void skl_power_well_disable(struct drm_i915_private *dev_priv,
 765                                 struct i915_power_well *power_well)
 766 {
 767         skl_set_power_well(dev_priv, power_well, false);
 768 }
 769
 770 static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv,
 771                                            struct i915_power_well *power_well)
 772 {
 773         return (I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0;
 774 }
 775
 776 static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
 777                                           struct i915_power_well *power_well)
 778 {
 779         gen9_disable_dc5_dc6(dev_priv);
 780 }
 781
 782 static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
 783                                            struct i915_power_well *power_well)
 784 {
 785         if ((IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) &&
 786             i915.enable_dc != 0 && i915.enable_dc != 1)
 787                 skl_enable_dc6(dev_priv);
 788         else
 789                 gen9_enable_dc5(dev_priv);
 790 }
 791
 792 static void gen9_dc_off_power_well_sync_hw(struct drm_i915_private *dev_priv,
 793                                            struct i915_power_well *power_well)
 794 {
 795         if (power_well->count > 0) {
 796                 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 797         } else {
 798                 if ((IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) &&
 799                     i915.enable_dc != 0 &&
 800                     i915.enable_dc != 1)
 801                         gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
 802                 else
 803                         gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5);
 804         }
 805 }
 806
 807 static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,
 808                                            struct i915_power_well *power_well)
 809 {
 810 }
 811
 812 static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,
 813                                              struct i915_power_well *power_well)
 814 {
 815         return true;
 816 }
 817
 818 static void vlv_set_power_well(struct drm_i915_private *dev_priv,
 819                                struct i915_power_well *power_well, bool enable)
 820 {
 821         enum punit_power_well power_well_id = power_well->data;
 822         u32 mask;
 823         u32 state;
 824         u32 ctrl;
 825
 826         mask = PUNIT_PWRGT_MASK(power_well_id);
 827         state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) :
 828                          PUNIT_PWRGT_PWR_GATE(power_well_id);
 829
 830         mutex_lock(&dev_priv->rps.hw_lock);
 831
 832 #define COND \
 833         ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)
 834
 835         if (COND)
 836                 goto out;
 837
 838         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL);
 839         ctrl &= ~mask;
 840         ctrl |= state;
 841         vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl);
 842
 843         if (wait_for(COND, 100))
 844                 DRM_ERROR("timeout setting power well state %08x (%08x)\n",
 845                           state,
 846                           vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL));
 847
 848 #undef COND
 849
 850 out:
 851         mutex_unlock(&dev_priv->rps.hw_lock);
 852 }
 853
 854 static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv,
 855                                    struct i915_power_well *power_well)
 856 {
 857         vlv_set_power_well(dev_priv, power_well, power_well->count > 0);
 858 }
 859
 860 static void vlv_power_well_enable(struct drm_i915_private *dev_priv,
 861                                   struct i915_power_well *power_well)
 862 {
 863         vlv_set_power_well(dev_priv, power_well, true);
 864 }
 865
 866 static void vlv_power_well_disable(struct drm_i915_private *dev_priv,
 867                                    struct i915_power_well *power_well)
 868 {
 869         vlv_set_power_well(dev_priv, power_well, false);
 870 }
 871
 872 static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
 873                                    struct i915_power_well *power_well)
 874 {
 875         int power_well_id = power_well->data;
 876         bool enabled = false;
 877         u32 mask;
 878         u32 state;
 879         u32 ctrl;
 880
 881         mask = PUNIT_PWRGT_MASK(power_well_id);
 882         ctrl = PUNIT_PWRGT_PWR_ON(power_well_id);
 883
 884         mutex_lock(&dev_priv->rps.hw_lock);
 885
 886         state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask;
 887         /*
 888          * We only ever set the power-on and power-gate states, anything
 889          * else is unexpected.
 890          */
 891         WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) &&
 892                 state != PUNIT_PWRGT_PWR_GATE(power_well_id));
 893         if (state == ctrl)
 894                 enabled = true;
 895
 896         /*
 897          * A transient state at this point would mean some unexpected party
 898          * is poking at the power controls too.
 899          */
 900         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask;
 901         WARN_ON(ctrl != state);
 902
 903         mutex_unlock(&dev_priv->rps.hw_lock);
 904
 905         return enabled;
 906 }
 907
 908 static void vlv_display_power_well_init(struct drm_i915_private *dev_priv)
 909 {
 910         enum pipe pipe;
 911
 912         /*
 913          * Enable the CRI clock source so we can get at the
 914          * display and the reference clock for VGA
 915          * hotplug / manual detection. Supposedly DSI also
 916          * needs the ref clock up and running.
 917          *
 918          * CHV DPLL B/C have some issues if VGA mode is enabled.
 919          */
 920         for_each_pipe(dev_priv->dev, pipe) {
 921                 u32 val = I915_READ(DPLL(pipe));
 922
 923                 val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
 924                 if (pipe != PIPE_A)
 925                         val |= DPLL_INTEGRATED_CRI_CLK_VLV;
 926
 927                 I915_WRITE(DPLL(pipe), val);
 928         }
 929
 930         spin_lock_irq(&dev_priv->irq_lock);
 931         valleyview_enable_display_irqs(dev_priv);
 932         spin_unlock_irq(&dev_priv->irq_lock);
 933
 934         /*
 935          * During driver initialization/resume we can avoid restoring the
 936          * part of the HW/SW state that will be inited anyway explicitly.
 937          */
 938         if (dev_priv->power_domains.initializing)
 939                 return;
 940
 941         intel_hpd_init(dev_priv);
 942
 943         i915_redisable_vga_power_on(dev_priv->dev);
 944 }
 945
 946 static void vlv_display_power_well_deinit(struct drm_i915_private *dev_priv)
 947 {
 948         spin_lock_irq(&dev_priv->irq_lock);
 949         valleyview_disable_display_irqs(dev_priv);
 950         spin_unlock_irq(&dev_priv->irq_lock);
 951
 952         vlv_power_sequencer_reset(dev_priv);
 953 }
 954
 955 static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv,
 956                                           struct i915_power_well *power_well)
 957 {
 958         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
 959
 960         vlv_set_power_well(dev_priv, power_well, true);
 961
 962         vlv_display_power_well_init(dev_priv);
 963 }
 964
 965 static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv,
 966                                            struct i915_power_well *power_well)
 967 {
 968         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
 969
 970         vlv_display_power_well_deinit(dev_priv);
 971
 972         vlv_set_power_well(dev_priv, power_well, false);
 973 }
 974
 975 static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
 976                                            struct i915_power_well *power_well)
 977 {
 978         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
 979
 980         /* since ref/cri clock was enabled */
 981         udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
 982
 983         vlv_set_power_well(dev_priv, power_well, true);
 984
 985         /*
 986          * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
 987          *  6.  De-assert cmn_reset/side_reset. Same as VLV X0.
 988          *   a. GUnit 0x2110 bit[0] set to 1 (def 0)
 989          *   b. The other bits such as sfr settings / modesel may all
 990          *      be set to 0.
 991          *
 992          * This should only be done on init and resume from S3 with
 993          * both PLLs disabled, or we risk losing DPIO and PLL
 994          * synchronization.
 995          */
 996         I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
 997 }
 998
 999 static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
1000                                             struct i915_power_well *power_well)
1001 {
1002         enum pipe pipe;
1003
1004         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
1005
1006         for_each_pipe(dev_priv, pipe)
1007                 assert_pll_disabled(dev_priv, pipe);
1008
1009         /* Assert common reset */
1010         I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST);
1011
1012         vlv_set_power_well(dev_priv, power_well, false);
1013 }
1014
1015 #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
1016
1017 static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv,
1018                                                  int power_well_id)
1019 {
1020         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1021         int i;
1022
1023         for (i = 0; i < power_domains->power_well_count; i++) {
1024                 struct i915_power_well *power_well;
1025
1026                 power_well = &power_domains->power_wells[i];
1027                 if (power_well->data == power_well_id)
1028                         return power_well;
1029         }
1030
1031         return NULL;
1032 }
1033
1034 #define BITS_SET(val, bits) (((val) & (bits)) == (bits))
1035
1036 static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
1037 {
1038         struct i915_power_well *cmn_bc =
1039                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
1040         struct i915_power_well *cmn_d =
1041                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D);
1042         u32 phy_control = dev_priv->chv_phy_control;
1043         u32 phy_status = 0;
1044         u32 phy_status_mask = 0xffffffff;
1045         u32 tmp;
1046
1047         /*
1048          * The BIOS can leave the PHY is some weird state
1049          * where it doesn't fully power down some parts.
1050          * Disable the asserts until the PHY has been fully
1051          * reset (ie. the power well has been disabled at
1052          * least once).
1053          */
1054         if (!dev_priv->chv_phy_assert[DPIO_PHY0])
1055                 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0) |
1056                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0) |
1057                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1) |
1058                                      PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1) |
1059                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0) |
1060                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1));
1061
1062         if (!dev_priv->chv_phy_assert[DPIO_PHY1])
1063                 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0) |
1064                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0) |
1065                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1));
1066
1067         if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) {
1068                 phy_status |= PHY_POWERGOOD(DPIO_PHY0);
1069
1070                 /* this assumes override is only used to enable lanes */
1071                 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0)) == 0)
1072                         phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0);
1073
1074                 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1)) == 0)
1075                         phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1);
1076
1077                 /* CL1 is on whenever anything is on in either channel */
1078                 if (BITS_SET(phy_control,
1079                              PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0) |
1080                              PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)))
1081                         phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0);
1082
1083                 /*
1084                  * The DPLLB check accounts for the pipe B + port A usage
1085                  * with CL2 powered up but all the lanes in the second channel
1086                  * powered down.
1087                  */
1088                 if (BITS_SET(phy_control,
1089                              PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)) &&
1090                     (I915_READ(DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0)
1091                         phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1);
1092
1093                 if (BITS_SET(phy_control,
1094                              PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH0)))
1095                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0);
1096                 if (BITS_SET(phy_control,
1097                              PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH0)))
1098                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1);
1099
1100                 if (BITS_SET(phy_control,
1101                              PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH1)))
1102                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0);
1103                 if (BITS_SET(phy_control,
1104                              PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH1)))
1105                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1);
1106         }
1107
1108         if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) {
1109                 phy_status |= PHY_POWERGOOD(DPIO_PHY1);
1110
1111                 /* this assumes override is only used to enable lanes */
1112                 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0)) == 0)
1113                         phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0);
1114
1115                 if (BITS_SET(phy_control,
1116                              PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0)))
1117                         phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0);
1118
1119                 if (BITS_SET(phy_control,
1120                              PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY1, DPIO_CH0)))
1121                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0);
1122                 if (BITS_SET(phy_control,
1123                              PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY1, DPIO_CH0)))
1124                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1);
1125         }
1126
1127         phy_status &= phy_status_mask;
1128
1129         /*
1130          * The PHY may be busy with some initial calibration and whatnot,
1131          * so the power state can take a while to actually change.
1132          */
1133         if (wait_for((tmp = I915_READ(DISPLAY_PHY_STATUS) & phy_status_mask) == phy_status, 10))
1134                 WARN(phy_status != tmp,
1135                      "Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n",
1136                      tmp, phy_status, dev_priv->chv_phy_control);
1137 }
1138
1139 #undef BITS_SET
1140
1141 static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
1142                                            struct i915_power_well *power_well)
1143 {
1144         enum dpio_phy phy;
1145         enum pipe pipe;
1146         uint32_t tmp;
1147
1148         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
1149                      power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
1150
1151         if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
1152                 pipe = PIPE_A;
1153                 phy = DPIO_PHY0;
1154         } else {
1155                 pipe = PIPE_C;
1156                 phy = DPIO_PHY1;
1157         }
1158
1159         /* since ref/cri clock was enabled */
1160         udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
1161         vlv_set_power_well(dev_priv, power_well, true);
1162
1163         /* Poll for phypwrgood signal */
1164         if (wait_for(I915_READ(DISPLAY_PHY_STATUS) & PHY_POWERGOOD(phy), 1))
1165                 DRM_ERROR("Display PHY %d is not power up\n", phy);
1166
1167         mutex_lock(&dev_priv->sb_lock);
1168
1169         /* Enable dynamic power down */
1170         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW28);
1171         tmp |= DPIO_DYNPWRDOWNEN_CH0 | DPIO_CL1POWERDOWNEN |
1172                 DPIO_SUS_CLK_CONFIG_GATE_CLKREQ;
1173         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW28, tmp);
1174
1175         if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
1176                 tmp = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW6_CH1);
1177                 tmp |= DPIO_DYNPWRDOWNEN_CH1;
1178                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW6_CH1, tmp);
1179         } else {
1180                 /*
1181                  * Force the non-existing CL2 off. BXT does this
1182                  * too, so maybe it saves some power even though
1183                  * CL2 doesn't exist?
1184                  */
1185                 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
1186                 tmp |= DPIO_CL2_LDOFUSE_PWRENB;
1187                 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, tmp);
1188         }
1189
1190         mutex_unlock(&dev_priv->sb_lock);
1191
1192         dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy);
1193         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1194
1195         DRM_DEBUG_KMS("Enabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
1196                       phy, dev_priv->chv_phy_control);
1197
1198         assert_chv_phy_status(dev_priv);
1199 }
1200
1201 static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
1202                                             struct i915_power_well *power_well)
1203 {
1204         enum dpio_phy phy;
1205
1206         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
1207                      power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
1208
1209         if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
1210                 phy = DPIO_PHY0;
1211                 assert_pll_disabled(dev_priv, PIPE_A);
1212                 assert_pll_disabled(dev_priv, PIPE_B);
1213         } else {
1214                 phy = DPIO_PHY1;
1215                 assert_pll_disabled(dev_priv, PIPE_C);
1216         }
1217
1218         dev_priv->chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy);
1219         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1220
1221         vlv_set_power_well(dev_priv, power_well, false);
1222
1223         DRM_DEBUG_KMS("Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
1224                       phy, dev_priv->chv_phy_control);
1225
1226         /* PHY is fully reset now, so we can enable the PHY state asserts */
1227         dev_priv->chv_phy_assert[phy] = true;
1228
1229         assert_chv_phy_status(dev_priv);
1230 }
1231
1232 static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1233                                      enum dpio_channel ch, bool override, unsigned int mask)
1234 {
1235         enum pipe pipe = phy == DPIO_PHY0 ? PIPE_A : PIPE_C;
1236         u32 reg, val, expected, actual;
1237
1238         /*
1239          * The BIOS can leave the PHY is some weird state
1240          * where it doesn't fully power down some parts.
1241          * Disable the asserts until the PHY has been fully
1242          * reset (ie. the power well has been disabled at
1243          * least once).
1244          */
1245         if (!dev_priv->chv_phy_assert[phy])
1246                 return;
1247
1248         if (ch == DPIO_CH0)
1249                 reg = _CHV_CMN_DW0_CH0;
1250         else
1251                 reg = _CHV_CMN_DW6_CH1;
1252
1253         mutex_lock(&dev_priv->sb_lock);
1254         val = vlv_dpio_read(dev_priv, pipe, reg);
1255         mutex_unlock(&dev_priv->sb_lock);
1256
1257         /*
1258          * This assumes !override is only used when the port is disabled.
1259          * All lanes should power down even without the override when
1260          * the port is disabled.
1261          */
1262         if (!override || mask == 0xf) {
1263                 expected = DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN;
1264                 /*
1265                  * If CH1 common lane is not active anymore
1266                  * (eg. for pipe B DPLL) the entire channel will
1267                  * shut down, which causes the common lane registers
1268                  * to read as 0. That means we can't actually check
1269                  * the lane power down status bits, but as the entire
1270                  * register reads as 0 it's a good indication that the
1271                  * channel is indeed entirely powered down.
1272                  */
1273                 if (ch == DPIO_CH1 && val == 0)
1274                         expected = 0;
1275         } else if (mask != 0x0) {
1276                 expected = DPIO_ANYDL_POWERDOWN;
1277         } else {
1278                 expected = 0;
1279         }
1280
1281         if (ch == DPIO_CH0)
1282                 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH0;
1283         else
1284                 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH1;
1285         actual &= DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN;
1286
1287         WARN(actual != expected,
1288              "Unexpected DPIO lane power down: all %d, any %d. Expected: all %d, any %d. (0x%x = 0x%08x)\n",
1289              !!(actual & DPIO_ALLDL_POWERDOWN), !!(actual & DPIO_ANYDL_POWERDOWN),
1290              !!(expected & DPIO_ALLDL_POWERDOWN), !!(expected & DPIO_ANYDL_POWERDOWN),
1291              reg, val);
1292 }
1293
1294 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1295                           enum dpio_channel ch, bool override)
1296 {
1297         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1298         bool was_override;
1299
1300         mutex_lock(&power_domains->lock);
1301
1302         was_override = dev_priv->chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1303
1304         if (override == was_override)
1305                 goto out;
1306
1307         if (override)
1308                 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1309         else
1310                 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1311
1312         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1313
1314         DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d (DPIO_PHY_CONTROL=0x%08x)\n",
1315                       phy, ch, dev_priv->chv_phy_control);
1316
1317         assert_chv_phy_status(dev_priv);
1318
1319 out:
1320         mutex_unlock(&power_domains->lock);
1321
1322         return was_override;
1323 }
1324
1325 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1326                              bool override, unsigned int mask)
1327 {
1328         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1329         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1330         enum dpio_phy phy = vlv_dport_to_phy(enc_to_dig_port(&encoder->base));
1331         enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
1332
1333         mutex_lock(&power_domains->lock);
1334
1335         dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch);
1336         dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch);
1337
1338         if (override)
1339                 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1340         else
1341                 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1342
1343         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1344
1345         DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d lanes 0x%x (PHY_CONTROL=0x%08x)\n",
1346                       phy, ch, mask, dev_priv->chv_phy_control);
1347
1348         assert_chv_phy_status(dev_priv);
1349
1350         assert_chv_phy_powergate(dev_priv, phy, ch, override, mask);
1351
1352         mutex_unlock(&power_domains->lock);
1353 }
1354
1355 static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv,
1356                                         struct i915_power_well *power_well)
1357 {
1358         enum pipe pipe = power_well->data;
1359         bool enabled;
1360         u32 state, ctrl;
1361
1362         mutex_lock(&dev_priv->rps.hw_lock);
1363
1364         state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe);
1365         /*
1366          * We only ever set the power-on and power-gate states, anything
1367          * else is unexpected.
1368          */
1369         WARN_ON(state != DP_SSS_PWR_ON(pipe) && state != DP_SSS_PWR_GATE(pipe));
1370         enabled = state == DP_SSS_PWR_ON(pipe);
1371
1372         /*
1373          * A transient state at this point would mean some unexpected party
1374          * is poking at the power controls too.
1375          */
1376         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe);
1377         WARN_ON(ctrl << 16 != state);
1378
1379         mutex_unlock(&dev_priv->rps.hw_lock);
1380
1381         return enabled;
1382 }
1383
1384 static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv,
1385                                     struct i915_power_well *power_well,
1386                                     bool enable)
1387 {
1388         enum pipe pipe = power_well->data;
1389         u32 state;
1390         u32 ctrl;
1391
1392         state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe);
1393
1394         mutex_lock(&dev_priv->rps.hw_lock);
1395
1396 #define COND \
1397         ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state)
1398
1399         if (COND)
1400                 goto out;
1401
1402         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
1403         ctrl &= ~DP_SSC_MASK(pipe);
1404         ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe);
1405         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl);
1406
1407         if (wait_for(COND, 100))
1408                 DRM_ERROR("timeout setting power well state %08x (%08x)\n",
1409                           state,
1410                           vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ));
1411
1412 #undef COND
1413
1414 out:
1415         mutex_unlock(&dev_priv->rps.hw_lock);
1416 }
1417
1418 static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv,
1419                                         struct i915_power_well *power_well)
1420 {
1421         WARN_ON_ONCE(power_well->data != PIPE_A);
1422
1423         chv_set_pipe_power_well(dev_priv, power_well, power_well->count > 0);
1424 }
1425
1426 static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv,
1427                                        struct i915_power_well *power_well)
1428 {
1429         WARN_ON_ONCE(power_well->data != PIPE_A);
1430
1431         chv_set_pipe_power_well(dev_priv, power_well, true);
1432
1433         vlv_display_power_well_init(dev_priv);
1434 }
1435
1436 static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv,
1437                                         struct i915_power_well *power_well)
1438 {
1439         WARN_ON_ONCE(power_well->data != PIPE_A);
1440
1441         vlv_display_power_well_deinit(dev_priv);
1442
1443         chv_set_pipe_power_well(dev_priv, power_well, false);
1444 }
1445
1446 static void
1447 __intel_display_power_get_domain(struct drm_i915_private *dev_priv,
1448                                  enum intel_display_power_domain domain)
1449 {
1450         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1451         struct i915_power_well *power_well;
1452         int i;
1453
1454         for_each_power_well(i, power_well, BIT(domain), power_domains) {
1455                 if (!power_well->count++)
1456                         intel_power_well_enable(dev_priv, power_well);
1457         }
1458
1459         power_domains->domain_use_count[domain]++;
1460 }
1461
1462 /**
1463  * intel_display_power_get - grab a power domain reference
1464  * @dev_priv: i915 device instance
1465  * @domain: power domain to reference
1466  *
1467  * This function grabs a power domain reference for @domain and ensures that the
1468  * power domain and all its parents are powered up. Therefore users should only
1469  * grab a reference to the innermost power domain they need.
1470  *
1471  * Any power domain reference obtained by this function must have a symmetric
1472  * call to intel_display_power_put() to release the reference again.
1473  */
1474 void intel_display_power_get(struct drm_i915_private *dev_priv,
1475                              enum intel_display_power_domain domain)
1476 {
1477         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1478
1479         intel_runtime_pm_get(dev_priv);
1480
1481         mutex_lock(&power_domains->lock);
1482
1483         __intel_display_power_get_domain(dev_priv, domain);
1484
1485         mutex_unlock(&power_domains->lock);
1486 }
1487
1488 /**
1489  * intel_display_power_get_if_enabled - grab a reference for an enabled display power domain
1490  * @dev_priv: i915 device instance
1491  * @domain: power domain to reference
1492  *
1493  * This function grabs a power domain reference for @domain and ensures that the
1494  * power domain and all its parents are powered up. Therefore users should only
1495  * grab a reference to the innermost power domain they need.
1496  *
1497  * Any power domain reference obtained by this function must have a symmetric
1498  * call to intel_display_power_put() to release the reference again.
1499  */
1500 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
1501                                         enum intel_display_power_domain domain)
1502 {
1503         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1504         bool is_enabled;
1505
1506         if (!intel_runtime_pm_get_if_in_use(dev_priv))
1507                 return false;
1508
1509         mutex_lock(&power_domains->lock);
1510
1511         if (__intel_display_power_is_enabled(dev_priv, domain)) {
1512                 __intel_display_power_get_domain(dev_priv, domain);
1513                 is_enabled = true;
1514         } else {
1515                 is_enabled = false;
1516         }
1517
1518         mutex_unlock(&power_domains->lock);
1519
1520         if (!is_enabled)
1521                 intel_runtime_pm_put(dev_priv);
1522
1523         return is_enabled;
1524 }
1525
1526 /**
1527  * intel_display_power_put - release a power domain reference
1528  * @dev_priv: i915 device instance
1529  * @domain: power domain to reference
1530  *
1531  * This function drops the power domain reference obtained by
1532  * intel_display_power_get() and might power down the corresponding hardware
1533  * block right away if this is the last reference.
1534  */
1535 void intel_display_power_put(struct drm_i915_private *dev_priv,
1536                              enum intel_display_power_domain domain)
1537 {
1538         struct i915_power_domains *power_domains;
1539         struct i915_power_well *power_well;
1540         int i;
1541
1542         power_domains = &dev_priv->power_domains;
1543
1544         mutex_lock(&power_domains->lock);
1545
1546         WARN(!power_domains->domain_use_count[domain],
1547              "Use count on domain %s is already zero\n",
1548              intel_display_power_domain_str(domain));
1549         power_domains->domain_use_count[domain]--;
1550
1551         for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
1552                 WARN(!power_well->count,
1553                      "Use count on power well %s is already zero",
1554                      power_well->name);
1555
1556                 if (!--power_well->count)
1557                         intel_power_well_disable(dev_priv, power_well);
1558         }
1559
1560         mutex_unlock(&power_domains->lock);
1561
1562         intel_runtime_pm_put(dev_priv);
1563 }
1564
1565 #define HSW_ALWAYS_ON_POWER_DOMAINS (                   \
1566         BIT(POWER_DOMAIN_PIPE_A) |                      \
1567         BIT(POWER_DOMAIN_TRANSCODER_EDP) |              \
1568         BIT(POWER_DOMAIN_PORT_DDI_A_LANES) |            \
1569         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |            \
1570         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |            \
1571         BIT(POWER_DOMAIN_PORT_DDI_D_LANES) |            \
1572         BIT(POWER_DOMAIN_PORT_CRT) |                    \
1573         BIT(POWER_DOMAIN_PLLS) |                        \
1574         BIT(POWER_DOMAIN_AUX_A) |                       \
1575         BIT(POWER_DOMAIN_AUX_B) |                       \
1576         BIT(POWER_DOMAIN_AUX_C) |                       \
1577         BIT(POWER_DOMAIN_AUX_D) |                       \
1578         BIT(POWER_DOMAIN_GMBUS) |                       \
1579         BIT(POWER_DOMAIN_INIT))
1580 #define HSW_DISPLAY_POWER_DOMAINS (                             \
1581         (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) |    \
1582         BIT(POWER_DOMAIN_INIT))
1583
1584 #define BDW_ALWAYS_ON_POWER_DOMAINS (                   \
1585         HSW_ALWAYS_ON_POWER_DOMAINS |                   \
1586         BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER))
1587 #define BDW_DISPLAY_POWER_DOMAINS (                             \
1588         (POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) |    \
1589         BIT(POWER_DOMAIN_INIT))
1590
1591 #define VLV_ALWAYS_ON_POWER_DOMAINS     BIT(POWER_DOMAIN_INIT)
1592 #define VLV_DISPLAY_POWER_DOMAINS       POWER_DOMAIN_MASK
1593
1594 #define VLV_DPIO_CMN_BC_POWER_DOMAINS (         \
1595         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |    \
1596         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |    \
1597         BIT(POWER_DOMAIN_PORT_CRT) |            \
1598         BIT(POWER_DOMAIN_AUX_B) |               \
1599         BIT(POWER_DOMAIN_AUX_C) |               \
1600         BIT(POWER_DOMAIN_INIT))
1601
1602 #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS (  \
1603         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |    \
1604         BIT(POWER_DOMAIN_AUX_B) |               \
1605         BIT(POWER_DOMAIN_INIT))
1606
1607 #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS (  \
1608         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |    \
1609         BIT(POWER_DOMAIN_AUX_B) |               \
1610         BIT(POWER_DOMAIN_INIT))
1611
1612 #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS (  \
1613         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |    \
1614         BIT(POWER_DOMAIN_AUX_C) |               \
1615         BIT(POWER_DOMAIN_INIT))
1616
1617 #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS (  \
1618         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |    \
1619         BIT(POWER_DOMAIN_AUX_C) |               \
1620         BIT(POWER_DOMAIN_INIT))
1621
1622 #define CHV_DPIO_CMN_BC_POWER_DOMAINS (         \
1623         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |    \
1624         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |    \
1625         BIT(POWER_DOMAIN_AUX_B) |               \
1626         BIT(POWER_DOMAIN_AUX_C) |               \
1627         BIT(POWER_DOMAIN_INIT))
1628
1629 #define CHV_DPIO_CMN_D_POWER_DOMAINS (          \
1630         BIT(POWER_DOMAIN_PORT_DDI_D_LANES) |    \
1631         BIT(POWER_DOMAIN_AUX_D) |               \
1632         BIT(POWER_DOMAIN_INIT))
1633
1634 static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
1635         .sync_hw = i9xx_always_on_power_well_noop,
1636         .enable = i9xx_always_on_power_well_noop,
1637         .disable = i9xx_always_on_power_well_noop,
1638         .is_enabled = i9xx_always_on_power_well_enabled,
1639 };
1640
1641 static const struct i915_power_well_ops chv_pipe_power_well_ops = {
1642         .sync_hw = chv_pipe_power_well_sync_hw,
1643         .enable = chv_pipe_power_well_enable,
1644         .disable = chv_pipe_power_well_disable,
1645         .is_enabled = chv_pipe_power_well_enabled,
1646 };
1647
1648 static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = {
1649         .sync_hw = vlv_power_well_sync_hw,
1650         .enable = chv_dpio_cmn_power_well_enable,
1651         .disable = chv_dpio_cmn_power_well_disable,
1652         .is_enabled = vlv_power_well_enabled,
1653 };
1654
1655 static struct i915_power_well i9xx_always_on_power_well[] = {
1656         {
1657                 .name = "always-on",
1658                 .always_on = 1,
1659                 .domains = POWER_DOMAIN_MASK,
1660                 .ops = &i9xx_always_on_power_well_ops,
1661         },
1662 };
1663
1664 static const struct i915_power_well_ops hsw_power_well_ops = {
1665         .sync_hw = hsw_power_well_sync_hw,
1666         .enable = hsw_power_well_enable,
1667         .disable = hsw_power_well_disable,
1668         .is_enabled = hsw_power_well_enabled,
1669 };
1670
1671 static const struct i915_power_well_ops skl_power_well_ops = {
1672         .sync_hw = skl_power_well_sync_hw,
1673         .enable = skl_power_well_enable,
1674         .disable = skl_power_well_disable,
1675         .is_enabled = skl_power_well_enabled,
1676 };
1677
1678 static const struct i915_power_well_ops gen9_dc_off_power_well_ops = {
1679         .sync_hw = gen9_dc_off_power_well_sync_hw,
1680         .enable = gen9_dc_off_power_well_enable,
1681         .disable = gen9_dc_off_power_well_disable,
1682         .is_enabled = gen9_dc_off_power_well_enabled,
1683 };
1684
1685 static struct i915_power_well hsw_power_wells[] = {
1686         {
1687                 .name = "always-on",
1688                 .always_on = 1,
1689                 .domains = HSW_ALWAYS_ON_POWER_DOMAINS,
1690                 .ops = &i9xx_always_on_power_well_ops,
1691         },
1692         {
1693                 .name = "display",
1694                 .domains = HSW_DISPLAY_POWER_DOMAINS,
1695                 .ops = &hsw_power_well_ops,
1696         },
1697 };
1698
1699 static struct i915_power_well bdw_power_wells[] = {
1700         {
1701                 .name = "always-on",
1702                 .always_on = 1,
1703                 .domains = BDW_ALWAYS_ON_POWER_DOMAINS,
1704                 .ops = &i9xx_always_on_power_well_ops,
1705         },
1706         {
1707                 .name = "display",
1708                 .domains = BDW_DISPLAY_POWER_DOMAINS,
1709                 .ops = &hsw_power_well_ops,
1710         },
1711 };
1712
1713 static const struct i915_power_well_ops vlv_display_power_well_ops = {
1714         .sync_hw = vlv_power_well_sync_hw,
1715         .enable = vlv_display_power_well_enable,
1716         .disable = vlv_display_power_well_disable,
1717         .is_enabled = vlv_power_well_enabled,
1718 };
1719
1720 static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = {
1721         .sync_hw = vlv_power_well_sync_hw,
1722         .enable = vlv_dpio_cmn_power_well_enable,
1723         .disable = vlv_dpio_cmn_power_well_disable,
1724         .is_enabled = vlv_power_well_enabled,
1725 };
1726
1727 static const struct i915_power_well_ops vlv_dpio_power_well_ops = {
1728         .sync_hw = vlv_power_well_sync_hw,
1729         .enable = vlv_power_well_enable,
1730         .disable = vlv_power_well_disable,
1731         .is_enabled = vlv_power_well_enabled,
1732 };
1733
1734 static struct i915_power_well vlv_power_wells[] = {
1735         {
1736                 .name = "always-on",
1737                 .always_on = 1,
1738                 .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
1739                 .ops = &i9xx_always_on_power_well_ops,
1740                 .data = PUNIT_POWER_WELL_ALWAYS_ON,
1741         },
1742         {
1743                 .name = "display",
1744                 .domains = VLV_DISPLAY_POWER_DOMAINS,
1745                 .data = PUNIT_POWER_WELL_DISP2D,
1746                 .ops = &vlv_display_power_well_ops,
1747         },
1748         {
1749                 .name = "dpio-tx-b-01",
1750                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1751                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1752                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1753                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1754                 .ops = &vlv_dpio_power_well_ops,
1755                 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
1756         },
1757         {
1758                 .name = "dpio-tx-b-23",
1759                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1760                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1761                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1762                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1763                 .ops = &vlv_dpio_power_well_ops,
1764                 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
1765         },
1766         {
1767                 .name = "dpio-tx-c-01",
1768                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1769                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1770                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1771                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1772                 .ops = &vlv_dpio_power_well_ops,
1773                 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
1774         },
1775         {
1776                 .name = "dpio-tx-c-23",
1777                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1778                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1779                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1780                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1781                 .ops = &vlv_dpio_power_well_ops,
1782                 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
1783         },
1784         {
1785                 .name = "dpio-common",
1786                 .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,
1787                 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
1788                 .ops = &vlv_dpio_cmn_power_well_ops,
1789         },
1790 };
1791
1792 static struct i915_power_well chv_power_wells[] = {
1793         {
1794                 .name = "always-on",
1795                 .always_on = 1,
1796                 .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
1797                 .ops = &i9xx_always_on_power_well_ops,
1798         },
1799         {
1800                 .name = "display",
1801                 /*
1802                  * Pipe A power well is the new disp2d well. Pipe B and C
1803                  * power wells don't actually exist. Pipe A power well is
1804                  * required for any pipe to work.
1805                  */
1806                 .domains = VLV_DISPLAY_POWER_DOMAINS,
1807                 .data = PIPE_A,
1808                 .ops = &chv_pipe_power_well_ops,
1809         },
1810         {
1811                 .name = "dpio-common-bc",
1812                 .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS,
1813                 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
1814                 .ops = &chv_dpio_cmn_power_well_ops,
1815         },
1816         {
1817                 .name = "dpio-common-d",
1818                 .domains = CHV_DPIO_CMN_D_POWER_DOMAINS,
1819                 .data = PUNIT_POWER_WELL_DPIO_CMN_D,
1820                 .ops = &chv_dpio_cmn_power_well_ops,
1821         },
1822 };
1823
1824 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
1825                                     int power_well_id)
1826 {
1827         struct i915_power_well *power_well;
1828         bool ret;
1829
1830         power_well = lookup_power_well(dev_priv, power_well_id);
1831         ret = power_well->ops->is_enabled(dev_priv, power_well);
1832
1833         return ret;
1834 }
1835
1836 static struct i915_power_well skl_power_wells[] = {
1837         {
1838                 .name = "always-on",
1839                 .always_on = 1,
1840                 .domains = SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS,
1841                 .ops = &i9xx_always_on_power_well_ops,
1842                 .data = SKL_DISP_PW_ALWAYS_ON,
1843         },
1844         {
1845                 .name = "power well 1",
1846                 /* Handled by the DMC firmware */
1847                 .domains = 0,
1848                 .ops = &skl_power_well_ops,
1849                 .data = SKL_DISP_PW_1,
1850         },
1851         {
1852                 .name = "MISC IO power well",
1853                 /* Handled by the DMC firmware */
1854                 .domains = 0,
1855                 .ops = &skl_power_well_ops,
1856                 .data = SKL_DISP_PW_MISC_IO,
1857         },
1858         {
1859                 .name = "DC off",
1860                 .domains = SKL_DISPLAY_DC_OFF_POWER_DOMAINS,
1861                 .ops = &gen9_dc_off_power_well_ops,
1862                 .data = SKL_DISP_PW_DC_OFF,
1863         },
1864         {
1865                 .name = "power well 2",
1866                 .domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS,
1867                 .ops = &skl_power_well_ops,
1868                 .data = SKL_DISP_PW_2,
1869         },
1870         {
1871                 .name = "DDI A/E power well",
1872                 .domains = SKL_DISPLAY_DDI_A_E_POWER_DOMAINS,
1873                 .ops = &skl_power_well_ops,
1874                 .data = SKL_DISP_PW_DDI_A_E,
1875         },
1876         {
1877                 .name = "DDI B power well",
1878                 .domains = SKL_DISPLAY_DDI_B_POWER_DOMAINS,
1879                 .ops = &skl_power_well_ops,
1880                 .data = SKL_DISP_PW_DDI_B,
1881         },
1882         {
1883                 .name = "DDI C power well",
1884                 .domains = SKL_DISPLAY_DDI_C_POWER_DOMAINS,
1885                 .ops = &skl_power_well_ops,
1886                 .data = SKL_DISP_PW_DDI_C,
1887         },
1888         {
1889                 .name = "DDI D power well",
1890                 .domains = SKL_DISPLAY_DDI_D_POWER_DOMAINS,
1891                 .ops = &skl_power_well_ops,
1892                 .data = SKL_DISP_PW_DDI_D,
1893         },
1894 };
1895
1896 void skl_pw1_misc_io_init(struct drm_i915_private *dev_priv)
1897 {
1898         struct i915_power_well *well;
1899
1900         if (!(IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)))
1901                 return;
1902
1903         well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
1904         intel_power_well_enable(dev_priv, well);
1905
1906         well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);
1907         intel_power_well_enable(dev_priv, well);
1908 }
1909
1910 void skl_pw1_misc_io_fini(struct drm_i915_private *dev_priv)
1911 {
1912         struct i915_power_well *well;
1913
1914         if (!(IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)))
1915                 return;
1916
1917         well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
1918         intel_power_well_disable(dev_priv, well);
1919
1920         well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);
1921         intel_power_well_disable(dev_priv, well);
1922 }
1923
1924 static struct i915_power_well bxt_power_wells[] = {
1925         {
1926                 .name = "always-on",
1927                 .always_on = 1,
1928                 .domains = BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS,
1929                 .ops = &i9xx_always_on_power_well_ops,
1930         },
1931         {
1932                 .name = "power well 1",
1933                 .domains = BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS,
1934                 .ops = &skl_power_well_ops,
1935                 .data = SKL_DISP_PW_1,
1936         },
1937         {
1938                 .name = "DC off",
1939                 .domains = BXT_DISPLAY_DC_OFF_POWER_DOMAINS,
1940                 .ops = &gen9_dc_off_power_well_ops,
1941                 .data = SKL_DISP_PW_DC_OFF,
1942         },
1943         {
1944                 .name = "power well 2",
1945                 .domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS,
1946                 .ops = &skl_power_well_ops,
1947                 .data = SKL_DISP_PW_2,
1948         },
1949 };
1950
1951 static int
1952 sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv,
1953                                    int disable_power_well)
1954 {
1955         if (disable_power_well >= 0)
1956                 return !!disable_power_well;
1957
1958         if (IS_BROXTON(dev_priv)) {
1959                 DRM_DEBUG_KMS("Disabling display power well support\n");
1960                 return 0;
1961         }
1962
1963         return 1;
1964 }
1965
1966 #define set_power_wells(power_domains, __power_wells) ({                \
1967         (power_domains)->power_wells = (__power_wells);                 \
1968         (power_domains)->power_well_count = ARRAY_SIZE(__power_wells);  \
1969 })
1970
1971 /**
1972  * intel_power_domains_init - initializes the power domain structures
1973  * @dev_priv: i915 device instance
1974  *
1975  * Initializes the power domain structures for @dev_priv depending upon the
1976  * supported platform.
1977  */
1978 int intel_power_domains_init(struct drm_i915_private *dev_priv)
1979 {
1980         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1981
1982         i915.disable_power_well = sanitize_disable_power_well_option(dev_priv,
1983                                                      i915.disable_power_well);
1984
1985         BUILD_BUG_ON(POWER_DOMAIN_NUM > 31);
1986
1987         mutex_init(&power_domains->lock);
1988
1989         /*
1990          * The enabling order will be from lower to higher indexed wells,
1991          * the disabling order is reversed.
1992          */
1993         if (IS_HASWELL(dev_priv->dev)) {
1994                 set_power_wells(power_domains, hsw_power_wells);
1995         } else if (IS_BROADWELL(dev_priv->dev)) {
1996                 set_power_wells(power_domains, bdw_power_wells);
1997         } else if (IS_SKYLAKE(dev_priv->dev) || IS_KABYLAKE(dev_priv->dev)) {
1998                 set_power_wells(power_domains, skl_power_wells);
1999         } else if (IS_BROXTON(dev_priv->dev)) {
2000                 set_power_wells(power_domains, bxt_power_wells);
2001         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
2002                 set_power_wells(power_domains, chv_power_wells);
2003         } else if (IS_VALLEYVIEW(dev_priv->dev)) {
2004                 set_power_wells(power_domains, vlv_power_wells);
2005         } else {
2006                 set_power_wells(power_domains, i9xx_always_on_power_well);
2007         }
2008
2009         return 0;
2010 }
2011
2012 /**
2013  * intel_power_domains_fini - finalizes the power domain structures
2014  * @dev_priv: i915 device instance
2015  *
2016  * Finalizes the power domain structures for @dev_priv depending upon the
2017  * supported platform. This function also disables runtime pm and ensures that
2018  * the device stays powered up so that the driver can be reloaded.
2019  */
2020 void intel_power_domains_fini(struct drm_i915_private *dev_priv)
2021 {
2022         struct device *device = &dev_priv->dev->pdev->dev;
2023
2024         /*
2025          * The i915.ko module is still not prepared to be loaded when
2026          * the power well is not enabled, so just enable it in case
2027          * we're going to unload/reload.
2028          * The following also reacquires the RPM reference the core passed
2029          * to the driver during loading, which is dropped in
2030          * intel_runtime_pm_enable(). We have to hand back the control of the
2031          * device to the core with this reference held.
2032          */
2033         intel_display_set_init_power(dev_priv, true);
2034
2035         /* Remove the refcount we took to keep power well support disabled. */
2036         if (!i915.disable_power_well)
2037                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
2038
2039         /*
2040          * Remove the refcount we took in intel_runtime_pm_enable() in case
2041          * the platform doesn't support runtime PM.
2042          */
2043         if (!HAS_RUNTIME_PM(dev_priv))
2044                 pm_runtime_put(device);
2045 }
2046
2047 static void intel_power_domains_sync_hw(struct drm_i915_private *dev_priv)
2048 {
2049         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2050         struct i915_power_well *power_well;
2051         int i;
2052
2053         mutex_lock(&power_domains->lock);
2054         for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
2055                 power_well->ops->sync_hw(dev_priv, power_well);
2056                 power_well->hw_enabled = power_well->ops->is_enabled(dev_priv,
2057                                                                      power_well);
2058         }
2059         mutex_unlock(&power_domains->lock);
2060 }
2061
2062 static void skl_display_core_init(struct drm_i915_private *dev_priv,
2063                                   bool resume)
2064 {
2065         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2066         uint32_t val;
2067
2068         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
2069
2070         /* enable PCH reset handshake */
2071         val = I915_READ(HSW_NDE_RSTWRN_OPT);
2072         I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
2073
2074         /* enable PG1 and Misc I/O */
2075         mutex_lock(&power_domains->lock);
2076         skl_pw1_misc_io_init(dev_priv);
2077         mutex_unlock(&power_domains->lock);
2078
2079         if (!resume)
2080                 return;
2081
2082         skl_init_cdclk(dev_priv);
2083
2084         if (dev_priv->csr.dmc_payload)
2085                 intel_csr_load_program(dev_priv);
2086 }
2087
2088 static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
2089 {
2090         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2091
2092         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
2093
2094         skl_uninit_cdclk(dev_priv);
2095
2096         /* The spec doesn't call for removing the reset handshake flag */
2097         /* disable PG1 and Misc I/O */
2098         mutex_lock(&power_domains->lock);
2099         skl_pw1_misc_io_fini(dev_priv);
2100         mutex_unlock(&power_domains->lock);
2101 }
2102
2103 static void chv_phy_control_init(struct drm_i915_private *dev_priv)
2104 {
2105         struct i915_power_well *cmn_bc =
2106                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
2107         struct i915_power_well *cmn_d =
2108                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D);
2109
2110         /*
2111          * DISPLAY_PHY_CONTROL can get corrupted if read. As a
2112          * workaround never ever read DISPLAY_PHY_CONTROL, and
2113          * instead maintain a shadow copy ourselves. Use the actual
2114          * power well state and lane status to reconstruct the
2115          * expected initial value.
2116          */
2117         dev_priv->chv_phy_control =
2118                 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY0) |
2119                 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY1) |
2120                 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH0) |
2121                 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH1) |
2122                 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY1, DPIO_CH0);
2123
2124         /*
2125          * If all lanes are disabled we leave the override disabled
2126          * with all power down bits cleared to match the state we
2127          * would use after disabling the port. Otherwise enable the
2128          * override and set the lane powerdown bits accding to the
2129          * current lane status.
2130          */
2131         if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) {
2132                 uint32_t status = I915_READ(DPLL(PIPE_A));
2133                 unsigned int mask;
2134
2135                 mask = status & DPLL_PORTB_READY_MASK;
2136                 if (mask == 0xf)
2137                         mask = 0x0;
2138                 else
2139                         dev_priv->chv_phy_control |=
2140                                 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0);
2141
2142                 dev_priv->chv_phy_control |=
2143                         PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH0);
2144
2145                 mask = (status & DPLL_PORTC_READY_MASK) >> 4;
2146                 if (mask == 0xf)
2147                         mask = 0x0;
2148                 else
2149                         dev_priv->chv_phy_control |=
2150                                 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1);
2151
2152                 dev_priv->chv_phy_control |=
2153                         PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH1);
2154
2155                 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0);
2156
2157                 dev_priv->chv_phy_assert[DPIO_PHY0] = false;
2158         } else {
2159                 dev_priv->chv_phy_assert[DPIO_PHY0] = true;
2160         }
2161
2162         if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) {
2163                 uint32_t status = I915_READ(DPIO_PHY_STATUS);
2164                 unsigned int mask;
2165
2166                 mask = status & DPLL_PORTD_READY_MASK;
2167
2168                 if (mask == 0xf)
2169                         mask = 0x0;
2170                 else
2171                         dev_priv->chv_phy_control |=
2172                                 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0);
2173
2174                 dev_priv->chv_phy_control |=
2175                         PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY1, DPIO_CH0);
2176
2177                 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1);
2178
2179                 dev_priv->chv_phy_assert[DPIO_PHY1] = false;
2180         } else {
2181                 dev_priv->chv_phy_assert[DPIO_PHY1] = true;
2182         }
2183
2184         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
2185
2186         DRM_DEBUG_KMS("Initial PHY_CONTROL=0x%08x\n",
2187                       dev_priv->chv_phy_control);
2188 }
2189
2190 static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv)
2191 {
2192         struct i915_power_well *cmn =
2193                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
2194         struct i915_power_well *disp2d =
2195                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D);
2196
2197         /* If the display might be already active skip this */
2198         if (cmn->ops->is_enabled(dev_priv, cmn) &&
2199             disp2d->ops->is_enabled(dev_priv, disp2d) &&
2200             I915_READ(DPIO_CTL) & DPIO_CMNRST)
2201                 return;
2202
2203         DRM_DEBUG_KMS("toggling display PHY side reset\n");
2204
2205         /* cmnlane needs DPLL registers */
2206         disp2d->ops->enable(dev_priv, disp2d);
2207
2208         /*
2209          * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx:
2210          * Need to assert and de-assert PHY SB reset by gating the
2211          * common lane power, then un-gating it.
2212          * Simply ungating isn't enough to reset the PHY enough to get
2213          * ports and lanes running.
2214          */
2215         cmn->ops->disable(dev_priv, cmn);
2216 }
2217
2218 /**
2219  * intel_power_domains_init_hw - initialize hardware power domain state
2220  * @dev_priv: i915 device instance
2221  *
2222  * This function initializes the hardware power domain state and enables all
2223  * power domains using intel_display_set_init_power().
2224  */
2225 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume)
2226 {
2227         struct drm_device *dev = dev_priv->dev;
2228         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2229
2230         power_domains->initializing = true;
2231
2232         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
2233                 skl_display_core_init(dev_priv, resume);
2234         } else if (IS_CHERRYVIEW(dev)) {
2235                 mutex_lock(&power_domains->lock);
2236                 chv_phy_control_init(dev_priv);
2237                 mutex_unlock(&power_domains->lock);
2238         } else if (IS_VALLEYVIEW(dev)) {
2239                 mutex_lock(&power_domains->lock);
2240                 vlv_cmnlane_wa(dev_priv);
2241                 mutex_unlock(&power_domains->lock);
2242         }
2243
2244         /* For now, we need the power well to be always enabled. */
2245         intel_display_set_init_power(dev_priv, true);
2246         /* Disable power support if the user asked so. */
2247         if (!i915.disable_power_well)
2248                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
2249         intel_power_domains_sync_hw(dev_priv);
2250         power_domains->initializing = false;
2251 }
2252
2253 /**
2254  * intel_power_domains_suspend - suspend power domain state
2255  * @dev_priv: i915 device instance
2256  *
2257  * This function prepares the hardware power domain state before entering
2258  * system suspend. It must be paired with intel_power_domains_init_hw().
2259  */
2260 void intel_power_domains_suspend(struct drm_i915_private *dev_priv)
2261 {
2262         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
2263                 skl_display_core_uninit(dev_priv);
2264
2265         /*
2266          * Even if power well support was disabled we still want to disable
2267          * power wells while we are system suspended.
2268          */
2269         if (!i915.disable_power_well)
2270                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
2271 }
2272
2273 /**
2274  * intel_runtime_pm_get - grab a runtime pm reference
2275  * @dev_priv: i915 device instance
2276  *
2277  * This function grabs a device-level runtime pm reference (mostly used for GEM
2278  * code to ensure the GTT or GT is on) and ensures that it is powered up.
2279  *
2280  * Any runtime pm reference obtained by this function must have a symmetric
2281  * call to intel_runtime_pm_put() to release the reference again.
2282  */
2283 void intel_runtime_pm_get(struct drm_i915_private *dev_priv)
2284 {
2285         struct drm_device *dev = dev_priv->dev;
2286         struct device *device = &dev->pdev->dev;
2287
2288         pm_runtime_get_sync(device);
2289
2290         atomic_inc(&dev_priv->pm.wakeref_count);
2291         assert_rpm_wakelock_held(dev_priv);
2292 }
2293
2294 /**
2295  * intel_runtime_pm_get_if_in_use - grab a runtime pm reference if device in use
2296  * @dev_priv: i915 device instance
2297  *
2298  * This function grabs a device-level runtime pm reference if the device is
2299  * already in use and ensures that it is powered up.
2300  *
2301  * Any runtime pm reference obtained by this function must have a symmetric
2302  * call to intel_runtime_pm_put() to release the reference again.
2303  */
2304 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv)
2305 {
2306         struct drm_device *dev = dev_priv->dev;
2307         struct device *device = &dev->pdev->dev;
2308         int ret;
2309
2310         if (!IS_ENABLED(CONFIG_PM))
2311                 return true;
2312
2313         ret = pm_runtime_get_if_in_use(device);
2314
2315         /*
2316          * In cases runtime PM is disabled by the RPM core and we get an
2317          * -EINVAL return value we are not supposed to call this function,
2318          * since the power state is undefined. This applies atm to the
2319          * late/early system suspend/resume handlers.
2320          */
2321         WARN_ON_ONCE(ret < 0);
2322         if (ret <= 0)
2323                 return false;
2324
2325         atomic_inc(&dev_priv->pm.wakeref_count);
2326         assert_rpm_wakelock_held(dev_priv);
2327
2328         return true;
2329 }
2330
2331 /**
2332  * intel_runtime_pm_get_noresume - grab a runtime pm reference
2333  * @dev_priv: i915 device instance
2334  *
2335  * This function grabs a device-level runtime pm reference (mostly used for GEM
2336  * code to ensure the GTT or GT is on).
2337  *
2338  * It will _not_ power up the device but instead only check that it's powered
2339  * on.  Therefore it is only valid to call this functions from contexts where
2340  * the device is known to be powered up and where trying to power it up would
2341  * result in hilarity and deadlocks. That pretty much means only the system
2342  * suspend/resume code where this is used to grab runtime pm references for
2343  * delayed setup down in work items.
2344  *
2345  * Any runtime pm reference obtained by this function must have a symmetric
2346  * call to intel_runtime_pm_put() to release the reference again.
2347  */
2348 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv)
2349 {
2350         struct drm_device *dev = dev_priv->dev;
2351         struct device *device = &dev->pdev->dev;
2352
2353         assert_rpm_wakelock_held(dev_priv);
2354         pm_runtime_get_noresume(device);
2355
2356         atomic_inc(&dev_priv->pm.wakeref_count);
2357 }
2358
2359 /**
2360  * intel_runtime_pm_put - release a runtime pm reference
2361  * @dev_priv: i915 device instance
2362  *
2363  * This function drops the device-level runtime pm reference obtained by
2364  * intel_runtime_pm_get() and might power down the corresponding
2365  * hardware block right away if this is the last reference.
2366  */
2367 void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
2368 {
2369         struct drm_device *dev = dev_priv->dev;
2370         struct device *device = &dev->pdev->dev;
2371
2372         assert_rpm_wakelock_held(dev_priv);
2373         if (atomic_dec_and_test(&dev_priv->pm.wakeref_count))
2374                 atomic_inc(&dev_priv->pm.atomic_seq);
2375
2376         pm_runtime_mark_last_busy(device);
2377         pm_runtime_put_autosuspend(device);
2378 }
2379
2380 /**
2381  * intel_runtime_pm_enable - enable runtime pm
2382  * @dev_priv: i915 device instance
2383  *
2384  * This function enables runtime pm at the end of the driver load sequence.
2385  *
2386  * Note that this function does currently not enable runtime pm for the
2387  * subordinate display power domains. That is only done on the first modeset
2388  * using intel_display_set_init_power().
2389  */
2390 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv)
2391 {
2392         struct drm_device *dev = dev_priv->dev;
2393         struct device *device = &dev->pdev->dev;
2394
2395         pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */
2396         pm_runtime_mark_last_busy(device);
2397
2398         /*
2399          * Take a permanent reference to disable the RPM functionality and drop
2400          * it only when unloading the driver. Use the low level get/put helpers,
2401          * so the driver's own RPM reference tracking asserts also work on
2402          * platforms without RPM support.
2403          */
2404         if (!HAS_RUNTIME_PM(dev)) {
2405                 pm_runtime_dont_use_autosuspend(device);
2406                 pm_runtime_get_sync(device);
2407         } else {
2408                 pm_runtime_use_autosuspend(device);
2409         }
2410
2411         /*
2412          * The core calls the driver load handler with an RPM reference held.
2413          * We drop that here and will reacquire it during unloading in
2414          * intel_power_domains_fini().
2415          */
2416         pm_runtime_put_autosuspend(device);
2417 }
2418