drivers/gpu/drm/i915/intel_runtime_pm.c

   1 /*
   2  * Copyright © 2012-2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *    Daniel Vetter <daniel.vetter@ffwll.ch>
  26  *
  27  */
  28
  29 #include <linux/pm_runtime.h>
  30 #include <linux/vgaarb.h>
  31
  32 #include "i915_drv.h"
  33 #include "intel_drv.h"
  34
  35 /**
  36  * DOC: runtime pm
  37  *
  38  * The i915 driver supports dynamic enabling and disabling of entire hardware
  39  * blocks at runtime. This is especially important on the display side where
  40  * software is supposed to control many power gates manually on recent hardware,
  41  * since on the GT side a lot of the power management is done by the hardware.
  42  * But even there some manual control at the device level is required.
  43  *
  44  * Since i915 supports a diverse set of platforms with a unified codebase and
  45  * hardware engineers just love to shuffle functionality around between power
  46  * domains there's a sizeable amount of indirection required. This file provides
  47  * generic functions to the driver for grabbing and releasing references for
  48  * abstract power domains. It then maps those to the actual power wells
  49  * present for a given platform.
  50  */
  51
  52 #define for_each_power_well(i, power_well, domain_mask, power_domains)  \
  53         for (i = 0;                                                     \
  54              i < (power_domains)->power_well_count &&                   \
  55                  ((power_well) = &(power_domains)->power_wells[i]);     \
  56              i++)                                                       \
  57                 for_each_if ((power_well)->domains & (domain_mask))
  58
  59 #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
  60         for (i = (power_domains)->power_well_count - 1;                  \
  61              i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
  62              i--)                                                        \
  63                 for_each_if ((power_well)->domains & (domain_mask))
  64
  65 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
  66                                     int power_well_id);
  67
  68 static struct i915_power_well *
  69 lookup_power_well(struct drm_i915_private *dev_priv, int power_well_id);
  70
  71 const char *
  72 intel_display_power_domain_str(enum intel_display_power_domain domain)
  73 {
  74         switch (domain) {
  75         case POWER_DOMAIN_PIPE_A:
  76                 return "PIPE_A";
  77         case POWER_DOMAIN_PIPE_B:
  78                 return "PIPE_B";
  79         case POWER_DOMAIN_PIPE_C:
  80                 return "PIPE_C";
  81         case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
  82                 return "PIPE_A_PANEL_FITTER";
  83         case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
  84                 return "PIPE_B_PANEL_FITTER";
  85         case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
  86                 return "PIPE_C_PANEL_FITTER";
  87         case POWER_DOMAIN_TRANSCODER_A:
  88                 return "TRANSCODER_A";
  89         case POWER_DOMAIN_TRANSCODER_B:
  90                 return "TRANSCODER_B";
  91         case POWER_DOMAIN_TRANSCODER_C:
  92                 return "TRANSCODER_C";
  93         case POWER_DOMAIN_TRANSCODER_EDP:
  94                 return "TRANSCODER_EDP";
  95         case POWER_DOMAIN_TRANSCODER_DSI_A:
  96                 return "TRANSCODER_DSI_A";
  97         case POWER_DOMAIN_TRANSCODER_DSI_C:
  98                 return "TRANSCODER_DSI_C";
  99         case POWER_DOMAIN_PORT_DDI_A_LANES:
 100                 return "PORT_DDI_A_LANES";
 101         case POWER_DOMAIN_PORT_DDI_B_LANES:
 102                 return "PORT_DDI_B_LANES";
 103         case POWER_DOMAIN_PORT_DDI_C_LANES:
 104                 return "PORT_DDI_C_LANES";
 105         case POWER_DOMAIN_PORT_DDI_D_LANES:
 106                 return "PORT_DDI_D_LANES";
 107         case POWER_DOMAIN_PORT_DDI_E_LANES:
 108                 return "PORT_DDI_E_LANES";
 109         case POWER_DOMAIN_PORT_DSI:
 110                 return "PORT_DSI";
 111         case POWER_DOMAIN_PORT_CRT:
 112                 return "PORT_CRT";
 113         case POWER_DOMAIN_PORT_OTHER:
 114                 return "PORT_OTHER";
 115         case POWER_DOMAIN_VGA:
 116                 return "VGA";
 117         case POWER_DOMAIN_AUDIO:
 118                 return "AUDIO";
 119         case POWER_DOMAIN_PLLS:
 120                 return "PLLS";
 121         case POWER_DOMAIN_AUX_A:
 122                 return "AUX_A";
 123         case POWER_DOMAIN_AUX_B:
 124                 return "AUX_B";
 125         case POWER_DOMAIN_AUX_C:
 126                 return "AUX_C";
 127         case POWER_DOMAIN_AUX_D:
 128                 return "AUX_D";
 129         case POWER_DOMAIN_GMBUS:
 130                 return "GMBUS";
 131         case POWER_DOMAIN_INIT:
 132                 return "INIT";
 133         case POWER_DOMAIN_MODESET:
 134                 return "MODESET";
 135         default:
 136                 MISSING_CASE(domain);
 137                 return "?";
 138         }
 139 }
 140
 141 static void intel_power_well_enable(struct drm_i915_private *dev_priv,
 142                                     struct i915_power_well *power_well)
 143 {
 144         DRM_DEBUG_KMS("enabling %s\n", power_well->name);
 145         power_well->ops->enable(dev_priv, power_well);
 146         power_well->hw_enabled = true;
 147 }
 148
 149 static void intel_power_well_disable(struct drm_i915_private *dev_priv,
 150                                      struct i915_power_well *power_well)
 151 {
 152         DRM_DEBUG_KMS("disabling %s\n", power_well->name);
 153         power_well->hw_enabled = false;
 154         power_well->ops->disable(dev_priv, power_well);
 155 }
 156
 157 static void intel_power_well_get(struct drm_i915_private *dev_priv,
 158                                  struct i915_power_well *power_well)
 159 {
 160         if (!power_well->count++)
 161                 intel_power_well_enable(dev_priv, power_well);
 162 }
 163
 164 static void intel_power_well_put(struct drm_i915_private *dev_priv,
 165                                  struct i915_power_well *power_well)
 166 {
 167         WARN(!power_well->count, "Use count on power well %s is already zero",
 168              power_well->name);
 169
 170         if (!--power_well->count)
 171                 intel_power_well_disable(dev_priv, power_well);
 172 }
 173
 174 /*
 175  * We should only use the power well if we explicitly asked the hardware to
 176  * enable it, so check if it's enabled and also check if we've requested it to
 177  * be enabled.
 178  */
 179 static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
 180                                    struct i915_power_well *power_well)
 181 {
 182         return I915_READ(HSW_PWR_WELL_DRIVER) ==
 183                      (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
 184 }
 185
 186 /**
 187  * __intel_display_power_is_enabled - unlocked check for a power domain
 188  * @dev_priv: i915 device instance
 189  * @domain: power domain to check
 190  *
 191  * This is the unlocked version of intel_display_power_is_enabled() and should
 192  * only be used from error capture and recovery code where deadlocks are
 193  * possible.
 194  *
 195  * Returns:
 196  * True when the power domain is enabled, false otherwise.
 197  */
 198 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
 199                                       enum intel_display_power_domain domain)
 200 {
 201         struct i915_power_domains *power_domains;
 202         struct i915_power_well *power_well;
 203         bool is_enabled;
 204         int i;
 205
 206         if (dev_priv->pm.suspended)
 207                 return false;
 208
 209         power_domains = &dev_priv->power_domains;
 210
 211         is_enabled = true;
 212
 213         for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
 214                 if (power_well->always_on)
 215                         continue;
 216
 217                 if (!power_well->hw_enabled) {
 218                         is_enabled = false;
 219                         break;
 220                 }
 221         }
 222
 223         return is_enabled;
 224 }
 225
 226 /**
 227  * intel_display_power_is_enabled - check for a power domain
 228  * @dev_priv: i915 device instance
 229  * @domain: power domain to check
 230  *
 231  * This function can be used to check the hw power domain state. It is mostly
 232  * used in hardware state readout functions. Everywhere else code should rely
 233  * upon explicit power domain reference counting to ensure that the hardware
 234  * block is powered up before accessing it.
 235  *
 236  * Callers must hold the relevant modesetting locks to ensure that concurrent
 237  * threads can't disable the power well while the caller tries to read a few
 238  * registers.
 239  *
 240  * Returns:
 241  * True when the power domain is enabled, false otherwise.
 242  */
 243 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
 244                                     enum intel_display_power_domain domain)
 245 {
 246         struct i915_power_domains *power_domains;
 247         bool ret;
 248
 249         power_domains = &dev_priv->power_domains;
 250
 251         mutex_lock(&power_domains->lock);
 252         ret = __intel_display_power_is_enabled(dev_priv, domain);
 253         mutex_unlock(&power_domains->lock);
 254
 255         return ret;
 256 }
 257
 258 /**
 259  * intel_display_set_init_power - set the initial power domain state
 260  * @dev_priv: i915 device instance
 261  * @enable: whether to enable or disable the initial power domain state
 262  *
 263  * For simplicity our driver load/unload and system suspend/resume code assumes
 264  * that all power domains are always enabled. This functions controls the state
 265  * of this little hack. While the initial power domain state is enabled runtime
 266  * pm is effectively disabled.
 267  */
 268 void intel_display_set_init_power(struct drm_i915_private *dev_priv,
 269                                   bool enable)
 270 {
 271         if (dev_priv->power_domains.init_power_on == enable)
 272                 return;
 273
 274         if (enable)
 275                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
 276         else
 277                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
 278
 279         dev_priv->power_domains.init_power_on = enable;
 280 }
 281
 282 /*
 283  * Starting with Haswell, we have a "Power Down Well" that can be turned off
 284  * when not needed anymore. We have 4 registers that can request the power well
 285  * to be enabled, and it will only be disabled if none of the registers is
 286  * requesting it to be enabled.
 287  */
 288 static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
 289 {
 290         struct drm_device *dev = dev_priv->dev;
 291
 292         /*
 293          * After we re-enable the power well, if we touch VGA register 0x3d5
 294          * we'll get unclaimed register interrupts. This stops after we write
 295          * anything to the VGA MSR register. The vgacon module uses this
 296          * register all the time, so if we unbind our driver and, as a
 297          * consequence, bind vgacon, we'll get stuck in an infinite loop at
 298          * console_unlock(). So make here we touch the VGA MSR register, making
 299          * sure vgacon can keep working normally without triggering interrupts
 300          * and error messages.
 301          */
 302         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
 303         outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
 304         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
 305
 306         if (IS_BROADWELL(dev))
 307                 gen8_irq_power_well_post_enable(dev_priv,
 308                                                 1 << PIPE_C | 1 << PIPE_B);
 309 }
 310
 311 static void hsw_power_well_pre_disable(struct drm_i915_private *dev_priv)
 312 {
 313         if (IS_BROADWELL(dev_priv))
 314                 gen8_irq_power_well_pre_disable(dev_priv,
 315                                                 1 << PIPE_C | 1 << PIPE_B);
 316 }
 317
 318 static void skl_power_well_post_enable(struct drm_i915_private *dev_priv,
 319                                        struct i915_power_well *power_well)
 320 {
 321         struct drm_device *dev = dev_priv->dev;
 322
 323         /*
 324          * After we re-enable the power well, if we touch VGA register 0x3d5
 325          * we'll get unclaimed register interrupts. This stops after we write
 326          * anything to the VGA MSR register. The vgacon module uses this
 327          * register all the time, so if we unbind our driver and, as a
 328          * consequence, bind vgacon, we'll get stuck in an infinite loop at
 329          * console_unlock(). So make here we touch the VGA MSR register, making
 330          * sure vgacon can keep working normally without triggering interrupts
 331          * and error messages.
 332          */
 333         if (power_well->data == SKL_DISP_PW_2) {
 334                 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
 335                 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
 336                 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
 337
 338                 gen8_irq_power_well_post_enable(dev_priv,
 339                                                 1 << PIPE_C | 1 << PIPE_B);
 340         }
 341 }
 342
 343 static void skl_power_well_pre_disable(struct drm_i915_private *dev_priv,
 344                                        struct i915_power_well *power_well)
 345 {
 346         if (power_well->data == SKL_DISP_PW_2)
 347                 gen8_irq_power_well_pre_disable(dev_priv,
 348                                                 1 << PIPE_C | 1 << PIPE_B);
 349 }
 350
 351 static void hsw_set_power_well(struct drm_i915_private *dev_priv,
 352                                struct i915_power_well *power_well, bool enable)
 353 {
 354         bool is_enabled, enable_requested;
 355         uint32_t tmp;
 356
 357         tmp = I915_READ(HSW_PWR_WELL_DRIVER);
 358         is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
 359         enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
 360
 361         if (enable) {
 362                 if (!enable_requested)
 363                         I915_WRITE(HSW_PWR_WELL_DRIVER,
 364                                    HSW_PWR_WELL_ENABLE_REQUEST);
 365
 366                 if (!is_enabled) {
 367                         DRM_DEBUG_KMS("Enabling power well\n");
 368                         if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
 369                                       HSW_PWR_WELL_STATE_ENABLED), 20))
 370                                 DRM_ERROR("Timeout enabling power well\n");
 371                         hsw_power_well_post_enable(dev_priv);
 372                 }
 373
 374         } else {
 375                 if (enable_requested) {
 376                         hsw_power_well_pre_disable(dev_priv);
 377                         I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
 378                         POSTING_READ(HSW_PWR_WELL_DRIVER);
 379                         DRM_DEBUG_KMS("Requesting to disable the power well\n");
 380                 }
 381         }
 382 }
 383
 384 #define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS (         \
 385         BIT(POWER_DOMAIN_TRANSCODER_A) |                \
 386         BIT(POWER_DOMAIN_PIPE_B) |                      \
 387         BIT(POWER_DOMAIN_TRANSCODER_B) |                \
 388         BIT(POWER_DOMAIN_PIPE_C) |                      \
 389         BIT(POWER_DOMAIN_TRANSCODER_C) |                \
 390         BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |         \
 391         BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |         \
 392         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |            \
 393         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |            \
 394         BIT(POWER_DOMAIN_PORT_DDI_D_LANES) |            \
 395         BIT(POWER_DOMAIN_PORT_DDI_E_LANES) |            \
 396         BIT(POWER_DOMAIN_AUX_B) |                       \
 397         BIT(POWER_DOMAIN_AUX_C) |                       \
 398         BIT(POWER_DOMAIN_AUX_D) |                       \
 399         BIT(POWER_DOMAIN_AUDIO) |                       \
 400         BIT(POWER_DOMAIN_VGA) |                         \
 401         BIT(POWER_DOMAIN_INIT))
 402 #define SKL_DISPLAY_DDI_A_E_POWER_DOMAINS (             \
 403         BIT(POWER_DOMAIN_PORT_DDI_A_LANES) |            \
 404         BIT(POWER_DOMAIN_PORT_DDI_E_LANES) |            \
 405         BIT(POWER_DOMAIN_INIT))
 406 #define SKL_DISPLAY_DDI_B_POWER_DOMAINS (               \
 407         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |            \
 408         BIT(POWER_DOMAIN_INIT))
 409 #define SKL_DISPLAY_DDI_C_POWER_DOMAINS (               \
 410         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |            \
 411         BIT(POWER_DOMAIN_INIT))
 412 #define SKL_DISPLAY_DDI_D_POWER_DOMAINS (               \
 413         BIT(POWER_DOMAIN_PORT_DDI_D_LANES) |            \
 414         BIT(POWER_DOMAIN_INIT))
 415 #define SKL_DISPLAY_DC_OFF_POWER_DOMAINS (              \
 416         SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS |         \
 417         BIT(POWER_DOMAIN_MODESET) |                     \
 418         BIT(POWER_DOMAIN_AUX_A) |                       \
 419         BIT(POWER_DOMAIN_INIT))
 420
 421 #define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS (         \
 422         BIT(POWER_DOMAIN_TRANSCODER_A) |                \
 423         BIT(POWER_DOMAIN_PIPE_B) |                      \
 424         BIT(POWER_DOMAIN_TRANSCODER_B) |                \
 425         BIT(POWER_DOMAIN_PIPE_C) |                      \
 426         BIT(POWER_DOMAIN_TRANSCODER_C) |                \
 427         BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |         \
 428         BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |         \
 429         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |            \
 430         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |            \
 431         BIT(POWER_DOMAIN_AUX_B) |                       \
 432         BIT(POWER_DOMAIN_AUX_C) |                       \
 433         BIT(POWER_DOMAIN_AUDIO) |                       \
 434         BIT(POWER_DOMAIN_VGA) |                         \
 435         BIT(POWER_DOMAIN_GMBUS) |                       \
 436         BIT(POWER_DOMAIN_INIT))
 437 #define BXT_DISPLAY_DC_OFF_POWER_DOMAINS (              \
 438         BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS |         \
 439         BIT(POWER_DOMAIN_MODESET) |                     \
 440         BIT(POWER_DOMAIN_AUX_A) |                       \
 441         BIT(POWER_DOMAIN_INIT))
 442 #define BXT_DPIO_CMN_A_POWER_DOMAINS (                  \
 443         BIT(POWER_DOMAIN_PORT_DDI_A_LANES) |            \
 444         BIT(POWER_DOMAIN_AUX_A) |                       \
 445         BIT(POWER_DOMAIN_INIT))
 446 #define BXT_DPIO_CMN_BC_POWER_DOMAINS (                 \
 447         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |            \
 448         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |            \
 449         BIT(POWER_DOMAIN_AUX_B) |                       \
 450         BIT(POWER_DOMAIN_AUX_C) |                       \
 451         BIT(POWER_DOMAIN_INIT))
 452
 453 static void assert_can_enable_dc9(struct drm_i915_private *dev_priv)
 454 {
 455         WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9),
 456                   "DC9 already programmed to be enabled.\n");
 457         WARN_ONCE(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
 458                   "DC5 still not disabled to enable DC9.\n");
 459         WARN_ONCE(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on.\n");
 460         WARN_ONCE(intel_irqs_enabled(dev_priv),
 461                   "Interrupts not disabled yet.\n");
 462
 463          /*
 464           * TODO: check for the following to verify the conditions to enter DC9
 465           * state are satisfied:
 466           * 1] Check relevant display engine registers to verify if mode set
 467           * disable sequence was followed.
 468           * 2] Check if display uninitialize sequence is initialized.
 469           */
 470 }
 471
 472 static void assert_can_disable_dc9(struct drm_i915_private *dev_priv)
 473 {
 474         WARN_ONCE(intel_irqs_enabled(dev_priv),
 475                   "Interrupts not disabled yet.\n");
 476         WARN_ONCE(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
 477                   "DC5 still not disabled.\n");
 478
 479          /*
 480           * TODO: check for the following to verify DC9 state was indeed
 481           * entered before programming to disable it:
 482           * 1] Check relevant display engine registers to verify if mode
 483           *  set disable sequence was followed.
 484           * 2] Check if display uninitialize sequence is initialized.
 485           */
 486 }
 487
 488 static void gen9_write_dc_state(struct drm_i915_private *dev_priv,
 489                                 u32 state)
 490 {
 491         int rewrites = 0;
 492         int rereads = 0;
 493         u32 v;
 494
 495         I915_WRITE(DC_STATE_EN, state);
 496
 497         /* It has been observed that disabling the dc6 state sometimes
 498          * doesn't stick and dmc keeps returning old value. Make sure
 499          * the write really sticks enough times and also force rewrite until
 500          * we are confident that state is exactly what we want.
 501          */
 502         do  {
 503                 v = I915_READ(DC_STATE_EN);
 504
 505                 if (v != state) {
 506                         I915_WRITE(DC_STATE_EN, state);
 507                         rewrites++;
 508                         rereads = 0;
 509                 } else if (rereads++ > 5) {
 510                         break;
 511                 }
 512
 513         } while (rewrites < 100);
 514
 515         if (v != state)
 516                 DRM_ERROR("Writing dc state to 0x%x failed, now 0x%x\n",
 517                           state, v);
 518
 519         /* Most of the times we need one retry, avoid spam */
 520         if (rewrites > 1)
 521                 DRM_DEBUG_KMS("Rewrote dc state to 0x%x %d times\n",
 522                               state, rewrites);
 523 }
 524
 525 static u32 gen9_dc_mask(struct drm_i915_private *dev_priv)
 526 {
 527         u32 mask;
 528
 529         mask = DC_STATE_EN_UPTO_DC5;
 530         if (IS_BROXTON(dev_priv))
 531                 mask |= DC_STATE_EN_DC9;
 532         else
 533                 mask |= DC_STATE_EN_UPTO_DC6;
 534
 535         return mask;
 536 }
 537
 538 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv)
 539 {
 540         u32 val;
 541
 542         val = I915_READ(DC_STATE_EN) & gen9_dc_mask(dev_priv);
 543
 544         DRM_DEBUG_KMS("Resetting DC state tracking from %02x to %02x\n",
 545                       dev_priv->csr.dc_state, val);
 546         dev_priv->csr.dc_state = val;
 547 }
 548
 549 static void gen9_set_dc_state(struct drm_i915_private *dev_priv, uint32_t state)
 550 {
 551         uint32_t val;
 552         uint32_t mask;
 553
 554         if (WARN_ON_ONCE(state & ~dev_priv->csr.allowed_dc_mask))
 555                 state &= dev_priv->csr.allowed_dc_mask;
 556
 557         val = I915_READ(DC_STATE_EN);
 558         mask = gen9_dc_mask(dev_priv);
 559         DRM_DEBUG_KMS("Setting DC state from %02x to %02x\n",
 560                       val & mask, state);
 561
 562         /* Check if DMC is ignoring our DC state requests */
 563         if ((val & mask) != dev_priv->csr.dc_state)
 564                 DRM_ERROR("DC state mismatch (0x%x -> 0x%x)\n",
 565                           dev_priv->csr.dc_state, val & mask);
 566
 567         val &= ~mask;
 568         val |= state;
 569
 570         gen9_write_dc_state(dev_priv, val);
 571
 572         dev_priv->csr.dc_state = val & mask;
 573 }
 574
 575 void bxt_enable_dc9(struct drm_i915_private *dev_priv)
 576 {
 577         assert_can_enable_dc9(dev_priv);
 578
 579         DRM_DEBUG_KMS("Enabling DC9\n");
 580
 581         gen9_set_dc_state(dev_priv, DC_STATE_EN_DC9);
 582 }
 583
 584 void bxt_disable_dc9(struct drm_i915_private *dev_priv)
 585 {
 586         assert_can_disable_dc9(dev_priv);
 587
 588         DRM_DEBUG_KMS("Disabling DC9\n");
 589
 590         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 591 }
 592
 593 static void assert_csr_loaded(struct drm_i915_private *dev_priv)
 594 {
 595         WARN_ONCE(!I915_READ(CSR_PROGRAM(0)),
 596                   "CSR program storage start is NULL\n");
 597         WARN_ONCE(!I915_READ(CSR_SSP_BASE), "CSR SSP Base Not fine\n");
 598         WARN_ONCE(!I915_READ(CSR_HTP_SKL), "CSR HTP Not fine\n");
 599 }
 600
 601 static void assert_can_enable_dc5(struct drm_i915_private *dev_priv)
 602 {
 603         bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv,
 604                                         SKL_DISP_PW_2);
 605
 606         WARN_ONCE(pg2_enabled, "PG2 not disabled to enable DC5.\n");
 607
 608         WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5),
 609                   "DC5 already programmed to be enabled.\n");
 610         assert_rpm_wakelock_held(dev_priv);
 611
 612         assert_csr_loaded(dev_priv);
 613 }
 614
 615 void gen9_enable_dc5(struct drm_i915_private *dev_priv)
 616 {
 617         assert_can_enable_dc5(dev_priv);
 618
 619         DRM_DEBUG_KMS("Enabling DC5\n");
 620
 621         gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5);
 622 }
 623
 624 static void assert_can_enable_dc6(struct drm_i915_private *dev_priv)
 625 {
 626         WARN_ONCE(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
 627                   "Backlight is not disabled.\n");
 628         WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6),
 629                   "DC6 already programmed to be enabled.\n");
 630
 631         assert_csr_loaded(dev_priv);
 632 }
 633
 634 void skl_enable_dc6(struct drm_i915_private *dev_priv)
 635 {
 636         assert_can_enable_dc6(dev_priv);
 637
 638         DRM_DEBUG_KMS("Enabling DC6\n");
 639
 640         gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
 641
 642 }
 643
 644 void skl_disable_dc6(struct drm_i915_private *dev_priv)
 645 {
 646         DRM_DEBUG_KMS("Disabling DC6\n");
 647
 648         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 649 }
 650
 651 static void
 652 gen9_sanitize_power_well_requests(struct drm_i915_private *dev_priv,
 653                                   struct i915_power_well *power_well)
 654 {
 655         enum skl_disp_power_wells power_well_id = power_well->data;
 656         u32 val;
 657         u32 mask;
 658
 659         mask = SKL_POWER_WELL_REQ(power_well_id);
 660
 661         val = I915_READ(HSW_PWR_WELL_KVMR);
 662         if (WARN_ONCE(val & mask, "Clearing unexpected KVMR request for %s\n",
 663                       power_well->name))
 664                 I915_WRITE(HSW_PWR_WELL_KVMR, val & ~mask);
 665
 666         val = I915_READ(HSW_PWR_WELL_BIOS);
 667         val |= I915_READ(HSW_PWR_WELL_DEBUG);
 668
 669         if (!(val & mask))
 670                 return;
 671
 672         /*
 673          * DMC is known to force on the request bits for power well 1 on SKL
 674          * and BXT and the misc IO power well on SKL but we don't expect any
 675          * other request bits to be set, so WARN for those.
 676          */
 677         if (power_well_id == SKL_DISP_PW_1 ||
 678             ((IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) &&
 679              power_well_id == SKL_DISP_PW_MISC_IO))
 680                 DRM_DEBUG_DRIVER("Clearing auxiliary requests for %s forced on "
 681                                  "by DMC\n", power_well->name);
 682         else
 683                 WARN_ONCE(1, "Clearing unexpected auxiliary requests for %s\n",
 684                           power_well->name);
 685
 686         I915_WRITE(HSW_PWR_WELL_BIOS, val & ~mask);
 687         I915_WRITE(HSW_PWR_WELL_DEBUG, val & ~mask);
 688 }
 689
 690 static void skl_set_power_well(struct drm_i915_private *dev_priv,
 691                         struct i915_power_well *power_well, bool enable)
 692 {
 693         uint32_t tmp, fuse_status;
 694         uint32_t req_mask, state_mask;
 695         bool is_enabled, enable_requested, check_fuse_status = false;
 696
 697         tmp = I915_READ(HSW_PWR_WELL_DRIVER);
 698         fuse_status = I915_READ(SKL_FUSE_STATUS);
 699
 700         switch (power_well->data) {
 701         case SKL_DISP_PW_1:
 702                 if (wait_for((I915_READ(SKL_FUSE_STATUS) &
 703                         SKL_FUSE_PG0_DIST_STATUS), 1)) {
 704                         DRM_ERROR("PG0 not enabled\n");
 705                         return;
 706                 }
 707                 break;
 708         case SKL_DISP_PW_2:
 709                 if (!(fuse_status & SKL_FUSE_PG1_DIST_STATUS)) {
 710                         DRM_ERROR("PG1 in disabled state\n");
 711                         return;
 712                 }
 713                 break;
 714         case SKL_DISP_PW_DDI_A_E:
 715         case SKL_DISP_PW_DDI_B:
 716         case SKL_DISP_PW_DDI_C:
 717         case SKL_DISP_PW_DDI_D:
 718         case SKL_DISP_PW_MISC_IO:
 719                 break;
 720         default:
 721                 WARN(1, "Unknown power well %lu\n", power_well->data);
 722                 return;
 723         }
 724
 725         req_mask = SKL_POWER_WELL_REQ(power_well->data);
 726         enable_requested = tmp & req_mask;
 727         state_mask = SKL_POWER_WELL_STATE(power_well->data);
 728         is_enabled = tmp & state_mask;
 729
 730         if (!enable && enable_requested)
 731                 skl_power_well_pre_disable(dev_priv, power_well);
 732
 733         if (enable) {
 734                 if (!enable_requested) {
 735                         WARN((tmp & state_mask) &&
 736                                 !I915_READ(HSW_PWR_WELL_BIOS),
 737                                 "Invalid for power well status to be enabled, unless done by the BIOS, \
 738                                 when request is to disable!\n");
 739                         I915_WRITE(HSW_PWR_WELL_DRIVER, tmp | req_mask);
 740                 }
 741
 742                 if (!is_enabled) {
 743                         DRM_DEBUG_KMS("Enabling %s\n", power_well->name);
 744                         check_fuse_status = true;
 745                 }
 746         } else {
 747                 if (enable_requested) {
 748                         I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask);
 749                         POSTING_READ(HSW_PWR_WELL_DRIVER);
 750                         DRM_DEBUG_KMS("Disabling %s\n", power_well->name);
 751                 }
 752
 753                 if (IS_GEN9(dev_priv))
 754                         gen9_sanitize_power_well_requests(dev_priv, power_well);
 755         }
 756
 757         if (wait_for(!!(I915_READ(HSW_PWR_WELL_DRIVER) & state_mask) == enable,
 758                      1))
 759                 DRM_ERROR("%s %s timeout\n",
 760                           power_well->name, enable ? "enable" : "disable");
 761
 762         if (check_fuse_status) {
 763                 if (power_well->data == SKL_DISP_PW_1) {
 764                         if (wait_for((I915_READ(SKL_FUSE_STATUS) &
 765                                 SKL_FUSE_PG1_DIST_STATUS), 1))
 766                                 DRM_ERROR("PG1 distributing status timeout\n");
 767                 } else if (power_well->data == SKL_DISP_PW_2) {
 768                         if (wait_for((I915_READ(SKL_FUSE_STATUS) &
 769                                 SKL_FUSE_PG2_DIST_STATUS), 1))
 770                                 DRM_ERROR("PG2 distributing status timeout\n");
 771                 }
 772         }
 773
 774         if (enable && !is_enabled)
 775                 skl_power_well_post_enable(dev_priv, power_well);
 776 }
 777
 778 static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
 779                                    struct i915_power_well *power_well)
 780 {
 781         hsw_set_power_well(dev_priv, power_well, power_well->count > 0);
 782
 783         /*
 784          * We're taking over the BIOS, so clear any requests made by it since
 785          * the driver is in charge now.
 786          */
 787         if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
 788                 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
 789 }
 790
 791 static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
 792                                   struct i915_power_well *power_well)
 793 {
 794         hsw_set_power_well(dev_priv, power_well, true);
 795 }
 796
 797 static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
 798                                    struct i915_power_well *power_well)
 799 {
 800         hsw_set_power_well(dev_priv, power_well, false);
 801 }
 802
 803 static bool skl_power_well_enabled(struct drm_i915_private *dev_priv,
 804                                         struct i915_power_well *power_well)
 805 {
 806         uint32_t mask = SKL_POWER_WELL_REQ(power_well->data) |
 807                 SKL_POWER_WELL_STATE(power_well->data);
 808
 809         return (I915_READ(HSW_PWR_WELL_DRIVER) & mask) == mask;
 810 }
 811
 812 static void skl_power_well_sync_hw(struct drm_i915_private *dev_priv,
 813                                 struct i915_power_well *power_well)
 814 {
 815         skl_set_power_well(dev_priv, power_well, power_well->count > 0);
 816
 817         /* Clear any request made by BIOS as driver is taking over */
 818         I915_WRITE(HSW_PWR_WELL_BIOS, 0);
 819 }
 820
 821 static void skl_power_well_enable(struct drm_i915_private *dev_priv,
 822                                 struct i915_power_well *power_well)
 823 {
 824         skl_set_power_well(dev_priv, power_well, true);
 825 }
 826
 827 static void skl_power_well_disable(struct drm_i915_private *dev_priv,
 828                                 struct i915_power_well *power_well)
 829 {
 830         skl_set_power_well(dev_priv, power_well, false);
 831 }
 832
 833 static enum dpio_phy bxt_power_well_to_phy(struct i915_power_well *power_well)
 834 {
 835         enum skl_disp_power_wells power_well_id = power_well->data;
 836
 837         return power_well_id == BXT_DPIO_CMN_A ? DPIO_PHY1 : DPIO_PHY0;
 838 }
 839
 840 static void bxt_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
 841                                            struct i915_power_well *power_well)
 842 {
 843         enum skl_disp_power_wells power_well_id = power_well->data;
 844         struct i915_power_well *cmn_a_well;
 845
 846         if (power_well_id == BXT_DPIO_CMN_BC) {
 847                 /*
 848                  * We need to copy the GRC calibration value from the eDP PHY,
 849                  * so make sure it's powered up.
 850                  */
 851                 cmn_a_well = lookup_power_well(dev_priv, BXT_DPIO_CMN_A);
 852                 intel_power_well_get(dev_priv, cmn_a_well);
 853         }
 854
 855         bxt_ddi_phy_init(dev_priv, bxt_power_well_to_phy(power_well));
 856
 857         if (power_well_id == BXT_DPIO_CMN_BC)
 858                 intel_power_well_put(dev_priv, cmn_a_well);
 859 }
 860
 861 static void bxt_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
 862                                             struct i915_power_well *power_well)
 863 {
 864         bxt_ddi_phy_uninit(dev_priv, bxt_power_well_to_phy(power_well));
 865 }
 866
 867 static bool bxt_dpio_cmn_power_well_enabled(struct drm_i915_private *dev_priv,
 868                                             struct i915_power_well *power_well)
 869 {
 870         return bxt_ddi_phy_is_enabled(dev_priv,
 871                                       bxt_power_well_to_phy(power_well));
 872 }
 873
 874 static void bxt_dpio_cmn_power_well_sync_hw(struct drm_i915_private *dev_priv,
 875                                             struct i915_power_well *power_well)
 876 {
 877         if (power_well->count > 0)
 878                 bxt_dpio_cmn_power_well_enable(dev_priv, power_well);
 879         else
 880                 bxt_dpio_cmn_power_well_disable(dev_priv, power_well);
 881 }
 882
 883
 884 static void bxt_verify_ddi_phy_power_wells(struct drm_i915_private *dev_priv)
 885 {
 886         struct i915_power_well *power_well;
 887
 888         power_well = lookup_power_well(dev_priv, BXT_DPIO_CMN_A);
 889         if (power_well->count > 0)
 890                 bxt_ddi_phy_verify_state(dev_priv,
 891                                          bxt_power_well_to_phy(power_well));
 892
 893         power_well = lookup_power_well(dev_priv, BXT_DPIO_CMN_BC);
 894         if (power_well->count > 0)
 895                 bxt_ddi_phy_verify_state(dev_priv,
 896                                          bxt_power_well_to_phy(power_well));
 897 }
 898
 899 static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv,
 900                                            struct i915_power_well *power_well)
 901 {
 902         return (I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0;
 903 }
 904
 905 static void gen9_assert_dbuf_enabled(struct drm_i915_private *dev_priv)
 906 {
 907         u32 tmp = I915_READ(DBUF_CTL);
 908
 909         WARN((tmp & (DBUF_POWER_STATE | DBUF_POWER_REQUEST)) !=
 910              (DBUF_POWER_STATE | DBUF_POWER_REQUEST),
 911              "Unexpected DBuf power power state (0x%08x)\n", tmp);
 912 }
 913
 914 static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
 915                                           struct i915_power_well *power_well)
 916 {
 917         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 918
 919         WARN_ON(dev_priv->cdclk_freq !=
 920                 dev_priv->display.get_display_clock_speed(dev_priv->dev));
 921
 922         gen9_assert_dbuf_enabled(dev_priv);
 923
 924         if (IS_BROXTON(dev_priv))
 925                 bxt_verify_ddi_phy_power_wells(dev_priv);
 926 }
 927
 928 static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
 929                                            struct i915_power_well *power_well)
 930 {
 931         if (!dev_priv->csr.dmc_payload)
 932                 return;
 933
 934         if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC6)
 935                 skl_enable_dc6(dev_priv);
 936         else if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5)
 937                 gen9_enable_dc5(dev_priv);
 938 }
 939
 940 static void gen9_dc_off_power_well_sync_hw(struct drm_i915_private *dev_priv,
 941                                            struct i915_power_well *power_well)
 942 {
 943         if (power_well->count > 0)
 944                 gen9_dc_off_power_well_enable(dev_priv, power_well);
 945         else
 946                 gen9_dc_off_power_well_disable(dev_priv, power_well);
 947 }
 948
 949 static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,
 950                                            struct i915_power_well *power_well)
 951 {
 952 }
 953
 954 static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,
 955                                              struct i915_power_well *power_well)
 956 {
 957         return true;
 958 }
 959
 960 static void vlv_set_power_well(struct drm_i915_private *dev_priv,
 961                                struct i915_power_well *power_well, bool enable)
 962 {
 963         enum punit_power_well power_well_id = power_well->data;
 964         u32 mask;
 965         u32 state;
 966         u32 ctrl;
 967
 968         mask = PUNIT_PWRGT_MASK(power_well_id);
 969         state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) :
 970                          PUNIT_PWRGT_PWR_GATE(power_well_id);
 971
 972         mutex_lock(&dev_priv->rps.hw_lock);
 973
 974 #define COND \
 975         ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)
 976
 977         if (COND)
 978                 goto out;
 979
 980         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL);
 981         ctrl &= ~mask;
 982         ctrl |= state;
 983         vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl);
 984
 985         if (wait_for(COND, 100))
 986                 DRM_ERROR("timeout setting power well state %08x (%08x)\n",
 987                           state,
 988                           vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL));
 989
 990 #undef COND
 991
 992 out:
 993         mutex_unlock(&dev_priv->rps.hw_lock);
 994 }
 995
 996 static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv,
 997                                    struct i915_power_well *power_well)
 998 {
 999         vlv_set_power_well(dev_priv, power_well, power_well->count > 0);
1000 }
1001
1002 static void vlv_power_well_enable(struct drm_i915_private *dev_priv,
1003                                   struct i915_power_well *power_well)
1004 {
1005         vlv_set_power_well(dev_priv, power_well, true);
1006 }
1007
1008 static void vlv_power_well_disable(struct drm_i915_private *dev_priv,
1009                                    struct i915_power_well *power_well)
1010 {
1011         vlv_set_power_well(dev_priv, power_well, false);
1012 }
1013
1014 static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
1015                                    struct i915_power_well *power_well)
1016 {
1017         int power_well_id = power_well->data;
1018         bool enabled = false;
1019         u32 mask;
1020         u32 state;
1021         u32 ctrl;
1022
1023         mask = PUNIT_PWRGT_MASK(power_well_id);
1024         ctrl = PUNIT_PWRGT_PWR_ON(power_well_id);
1025
1026         mutex_lock(&dev_priv->rps.hw_lock);
1027
1028         state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask;
1029         /*
1030          * We only ever set the power-on and power-gate states, anything
1031          * else is unexpected.
1032          */
1033         WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) &&
1034                 state != PUNIT_PWRGT_PWR_GATE(power_well_id));
1035         if (state == ctrl)
1036                 enabled = true;
1037
1038         /*
1039          * A transient state at this point would mean some unexpected party
1040          * is poking at the power controls too.
1041          */
1042         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask;
1043         WARN_ON(ctrl != state);
1044
1045         mutex_unlock(&dev_priv->rps.hw_lock);
1046
1047         return enabled;
1048 }
1049
1050 static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
1051 {
1052         I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
1053
1054         /*
1055          * Disable trickle feed and enable pnd deadline calculation
1056          */
1057         I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
1058         I915_WRITE(CBR1_VLV, 0);
1059
1060         WARN_ON(dev_priv->rawclk_freq == 0);
1061
1062         I915_WRITE(RAWCLK_FREQ_VLV,
1063                    DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 1000));
1064 }
1065
1066 static void vlv_display_power_well_init(struct drm_i915_private *dev_priv)
1067 {
1068         enum pipe pipe;
1069
1070         /*
1071          * Enable the CRI clock source so we can get at the
1072          * display and the reference clock for VGA
1073          * hotplug / manual detection. Supposedly DSI also
1074          * needs the ref clock up and running.
1075          *
1076          * CHV DPLL B/C have some issues if VGA mode is enabled.
1077          */
1078         for_each_pipe(dev_priv->dev, pipe) {
1079                 u32 val = I915_READ(DPLL(pipe));
1080
1081                 val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1082                 if (pipe != PIPE_A)
1083                         val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1084
1085                 I915_WRITE(DPLL(pipe), val);
1086         }
1087
1088         vlv_init_display_clock_gating(dev_priv);
1089
1090         spin_lock_irq(&dev_priv->irq_lock);
1091         valleyview_enable_display_irqs(dev_priv);
1092         spin_unlock_irq(&dev_priv->irq_lock);
1093
1094         /*
1095          * During driver initialization/resume we can avoid restoring the
1096          * part of the HW/SW state that will be inited anyway explicitly.
1097          */
1098         if (dev_priv->power_domains.initializing)
1099                 return;
1100
1101         intel_hpd_init(dev_priv);
1102
1103         i915_redisable_vga_power_on(dev_priv->dev);
1104 }
1105
1106 static void vlv_display_power_well_deinit(struct drm_i915_private *dev_priv)
1107 {
1108         spin_lock_irq(&dev_priv->irq_lock);
1109         valleyview_disable_display_irqs(dev_priv);
1110         spin_unlock_irq(&dev_priv->irq_lock);
1111
1112         /* make sure we're done processing display irqs */
1113         synchronize_irq(dev_priv->dev->irq);
1114
1115         vlv_power_sequencer_reset(dev_priv);
1116 }
1117
1118 static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv,
1119                                           struct i915_power_well *power_well)
1120 {
1121         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
1122
1123         vlv_set_power_well(dev_priv, power_well, true);
1124
1125         vlv_display_power_well_init(dev_priv);
1126 }
1127
1128 static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv,
1129                                            struct i915_power_well *power_well)
1130 {
1131         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
1132
1133         vlv_display_power_well_deinit(dev_priv);
1134
1135         vlv_set_power_well(dev_priv, power_well, false);
1136 }
1137
1138 static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
1139                                            struct i915_power_well *power_well)
1140 {
1141         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
1142
1143         /* since ref/cri clock was enabled */
1144         udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
1145
1146         vlv_set_power_well(dev_priv, power_well, true);
1147
1148         /*
1149          * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1150          *  6.  De-assert cmn_reset/side_reset. Same as VLV X0.
1151          *   a. GUnit 0x2110 bit[0] set to 1 (def 0)
1152          *   b. The other bits such as sfr settings / modesel may all
1153          *      be set to 0.
1154          *
1155          * This should only be done on init and resume from S3 with
1156          * both PLLs disabled, or we risk losing DPIO and PLL
1157          * synchronization.
1158          */
1159         I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
1160 }
1161
1162 static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
1163                                             struct i915_power_well *power_well)
1164 {
1165         enum pipe pipe;
1166
1167         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
1168
1169         for_each_pipe(dev_priv, pipe)
1170                 assert_pll_disabled(dev_priv, pipe);
1171
1172         /* Assert common reset */
1173         I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST);
1174
1175         vlv_set_power_well(dev_priv, power_well, false);
1176 }
1177
1178 #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
1179
1180 static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv,
1181                                                  int power_well_id)
1182 {
1183         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1184         int i;
1185
1186         for (i = 0; i < power_domains->power_well_count; i++) {
1187                 struct i915_power_well *power_well;
1188
1189                 power_well = &power_domains->power_wells[i];
1190                 if (power_well->data == power_well_id)
1191                         return power_well;
1192         }
1193
1194         return NULL;
1195 }
1196
1197 #define BITS_SET(val, bits) (((val) & (bits)) == (bits))
1198
1199 static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
1200 {
1201         struct i915_power_well *cmn_bc =
1202                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
1203         struct i915_power_well *cmn_d =
1204                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D);
1205         u32 phy_control = dev_priv->chv_phy_control;
1206         u32 phy_status = 0;
1207         u32 phy_status_mask = 0xffffffff;
1208         u32 tmp;
1209
1210         /*
1211          * The BIOS can leave the PHY is some weird state
1212          * where it doesn't fully power down some parts.
1213          * Disable the asserts until the PHY has been fully
1214          * reset (ie. the power well has been disabled at
1215          * least once).
1216          */
1217         if (!dev_priv->chv_phy_assert[DPIO_PHY0])
1218                 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0) |
1219                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0) |
1220                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1) |
1221                                      PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1) |
1222                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0) |
1223                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1));
1224
1225         if (!dev_priv->chv_phy_assert[DPIO_PHY1])
1226                 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0) |
1227                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0) |
1228                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1));
1229
1230         if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) {
1231                 phy_status |= PHY_POWERGOOD(DPIO_PHY0);
1232
1233                 /* this assumes override is only used to enable lanes */
1234                 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0)) == 0)
1235                         phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0);
1236
1237                 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1)) == 0)
1238                         phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1);
1239
1240                 /* CL1 is on whenever anything is on in either channel */
1241                 if (BITS_SET(phy_control,
1242                              PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0) |
1243                              PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)))
1244                         phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0);
1245
1246                 /*
1247                  * The DPLLB check accounts for the pipe B + port A usage
1248                  * with CL2 powered up but all the lanes in the second channel
1249                  * powered down.
1250                  */
1251                 if (BITS_SET(phy_control,
1252                              PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)) &&
1253                     (I915_READ(DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0)
1254                         phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1);
1255
1256                 if (BITS_SET(phy_control,
1257                              PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH0)))
1258                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0);
1259                 if (BITS_SET(phy_control,
1260                              PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH0)))
1261                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1);
1262
1263                 if (BITS_SET(phy_control,
1264                              PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH1)))
1265                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0);
1266                 if (BITS_SET(phy_control,
1267                              PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH1)))
1268                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1);
1269         }
1270
1271         if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) {
1272                 phy_status |= PHY_POWERGOOD(DPIO_PHY1);
1273
1274                 /* this assumes override is only used to enable lanes */
1275                 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0)) == 0)
1276                         phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0);
1277
1278                 if (BITS_SET(phy_control,
1279                              PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0)))
1280                         phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0);
1281
1282                 if (BITS_SET(phy_control,
1283                              PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY1, DPIO_CH0)))
1284                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0);
1285                 if (BITS_SET(phy_control,
1286                              PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY1, DPIO_CH0)))
1287                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1);
1288         }
1289
1290         phy_status &= phy_status_mask;
1291
1292         /*
1293          * The PHY may be busy with some initial calibration and whatnot,
1294          * so the power state can take a while to actually change.
1295          */
1296         if (wait_for((tmp = I915_READ(DISPLAY_PHY_STATUS) & phy_status_mask) == phy_status, 10))
1297                 WARN(phy_status != tmp,
1298                      "Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n",
1299                      tmp, phy_status, dev_priv->chv_phy_control);
1300 }
1301
1302 #undef BITS_SET
1303
1304 static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
1305                                            struct i915_power_well *power_well)
1306 {
1307         enum dpio_phy phy;
1308         enum pipe pipe;
1309         uint32_t tmp;
1310
1311         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
1312                      power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
1313
1314         if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
1315                 pipe = PIPE_A;
1316                 phy = DPIO_PHY0;
1317         } else {
1318                 pipe = PIPE_C;
1319                 phy = DPIO_PHY1;
1320         }
1321
1322         /* since ref/cri clock was enabled */
1323         udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
1324         vlv_set_power_well(dev_priv, power_well, true);
1325
1326         /* Poll for phypwrgood signal */
1327         if (wait_for(I915_READ(DISPLAY_PHY_STATUS) & PHY_POWERGOOD(phy), 1))
1328                 DRM_ERROR("Display PHY %d is not power up\n", phy);
1329
1330         mutex_lock(&dev_priv->sb_lock);
1331
1332         /* Enable dynamic power down */
1333         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW28);
1334         tmp |= DPIO_DYNPWRDOWNEN_CH0 | DPIO_CL1POWERDOWNEN |
1335                 DPIO_SUS_CLK_CONFIG_GATE_CLKREQ;
1336         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW28, tmp);
1337
1338         if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
1339                 tmp = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW6_CH1);
1340                 tmp |= DPIO_DYNPWRDOWNEN_CH1;
1341                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW6_CH1, tmp);
1342         } else {
1343                 /*
1344                  * Force the non-existing CL2 off. BXT does this
1345                  * too, so maybe it saves some power even though
1346                  * CL2 doesn't exist?
1347                  */
1348                 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
1349                 tmp |= DPIO_CL2_LDOFUSE_PWRENB;
1350                 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, tmp);
1351         }
1352
1353         mutex_unlock(&dev_priv->sb_lock);
1354
1355         dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy);
1356         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1357
1358         DRM_DEBUG_KMS("Enabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
1359                       phy, dev_priv->chv_phy_control);
1360
1361         assert_chv_phy_status(dev_priv);
1362 }
1363
1364 static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
1365                                             struct i915_power_well *power_well)
1366 {
1367         enum dpio_phy phy;
1368
1369         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
1370                      power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
1371
1372         if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
1373                 phy = DPIO_PHY0;
1374                 assert_pll_disabled(dev_priv, PIPE_A);
1375                 assert_pll_disabled(dev_priv, PIPE_B);
1376         } else {
1377                 phy = DPIO_PHY1;
1378                 assert_pll_disabled(dev_priv, PIPE_C);
1379         }
1380
1381         dev_priv->chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy);
1382         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1383
1384         vlv_set_power_well(dev_priv, power_well, false);
1385
1386         DRM_DEBUG_KMS("Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
1387                       phy, dev_priv->chv_phy_control);
1388
1389         /* PHY is fully reset now, so we can enable the PHY state asserts */
1390         dev_priv->chv_phy_assert[phy] = true;
1391
1392         assert_chv_phy_status(dev_priv);
1393 }
1394
1395 static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1396                                      enum dpio_channel ch, bool override, unsigned int mask)
1397 {
1398         enum pipe pipe = phy == DPIO_PHY0 ? PIPE_A : PIPE_C;
1399         u32 reg, val, expected, actual;
1400
1401         /*
1402          * The BIOS can leave the PHY is some weird state
1403          * where it doesn't fully power down some parts.
1404          * Disable the asserts until the PHY has been fully
1405          * reset (ie. the power well has been disabled at
1406          * least once).
1407          */
1408         if (!dev_priv->chv_phy_assert[phy])
1409                 return;
1410
1411         if (ch == DPIO_CH0)
1412                 reg = _CHV_CMN_DW0_CH0;
1413         else
1414                 reg = _CHV_CMN_DW6_CH1;
1415
1416         mutex_lock(&dev_priv->sb_lock);
1417         val = vlv_dpio_read(dev_priv, pipe, reg);
1418         mutex_unlock(&dev_priv->sb_lock);
1419
1420         /*
1421          * This assumes !override is only used when the port is disabled.
1422          * All lanes should power down even without the override when
1423          * the port is disabled.
1424          */
1425         if (!override || mask == 0xf) {
1426                 expected = DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN;
1427                 /*
1428                  * If CH1 common lane is not active anymore
1429                  * (eg. for pipe B DPLL) the entire channel will
1430                  * shut down, which causes the common lane registers
1431                  * to read as 0. That means we can't actually check
1432                  * the lane power down status bits, but as the entire
1433                  * register reads as 0 it's a good indication that the
1434                  * channel is indeed entirely powered down.
1435                  */
1436                 if (ch == DPIO_CH1 && val == 0)
1437                         expected = 0;
1438         } else if (mask != 0x0) {
1439                 expected = DPIO_ANYDL_POWERDOWN;
1440         } else {
1441                 expected = 0;
1442         }
1443
1444         if (ch == DPIO_CH0)
1445                 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH0;
1446         else
1447                 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH1;
1448         actual &= DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN;
1449
1450         WARN(actual != expected,
1451              "Unexpected DPIO lane power down: all %d, any %d. Expected: all %d, any %d. (0x%x = 0x%08x)\n",
1452              !!(actual & DPIO_ALLDL_POWERDOWN), !!(actual & DPIO_ANYDL_POWERDOWN),
1453              !!(expected & DPIO_ALLDL_POWERDOWN), !!(expected & DPIO_ANYDL_POWERDOWN),
1454              reg, val);
1455 }
1456
1457 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1458                           enum dpio_channel ch, bool override)
1459 {
1460         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1461         bool was_override;
1462
1463         mutex_lock(&power_domains->lock);
1464
1465         was_override = dev_priv->chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1466
1467         if (override == was_override)
1468                 goto out;
1469
1470         if (override)
1471                 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1472         else
1473                 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1474
1475         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1476
1477         DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d (DPIO_PHY_CONTROL=0x%08x)\n",
1478                       phy, ch, dev_priv->chv_phy_control);
1479
1480         assert_chv_phy_status(dev_priv);
1481
1482 out:
1483         mutex_unlock(&power_domains->lock);
1484
1485         return was_override;
1486 }
1487
1488 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1489                              bool override, unsigned int mask)
1490 {
1491         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1492         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1493         enum dpio_phy phy = vlv_dport_to_phy(enc_to_dig_port(&encoder->base));
1494         enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
1495
1496         mutex_lock(&power_domains->lock);
1497
1498         dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch);
1499         dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch);
1500
1501         if (override)
1502                 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1503         else
1504                 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1505
1506         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1507
1508         DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d lanes 0x%x (PHY_CONTROL=0x%08x)\n",
1509                       phy, ch, mask, dev_priv->chv_phy_control);
1510
1511         assert_chv_phy_status(dev_priv);
1512
1513         assert_chv_phy_powergate(dev_priv, phy, ch, override, mask);
1514
1515         mutex_unlock(&power_domains->lock);
1516 }
1517
1518 static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv,
1519                                         struct i915_power_well *power_well)
1520 {
1521         enum pipe pipe = power_well->data;
1522         bool enabled;
1523         u32 state, ctrl;
1524
1525         mutex_lock(&dev_priv->rps.hw_lock);
1526
1527         state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe);
1528         /*
1529          * We only ever set the power-on and power-gate states, anything
1530          * else is unexpected.
1531          */
1532         WARN_ON(state != DP_SSS_PWR_ON(pipe) && state != DP_SSS_PWR_GATE(pipe));
1533         enabled = state == DP_SSS_PWR_ON(pipe);
1534
1535         /*
1536          * A transient state at this point would mean some unexpected party
1537          * is poking at the power controls too.
1538          */
1539         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe);
1540         WARN_ON(ctrl << 16 != state);
1541
1542         mutex_unlock(&dev_priv->rps.hw_lock);
1543
1544         return enabled;
1545 }
1546
1547 static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv,
1548                                     struct i915_power_well *power_well,
1549                                     bool enable)
1550 {
1551         enum pipe pipe = power_well->data;
1552         u32 state;
1553         u32 ctrl;
1554
1555         state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe);
1556
1557         mutex_lock(&dev_priv->rps.hw_lock);
1558
1559 #define COND \
1560         ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state)
1561
1562         if (COND)
1563                 goto out;
1564
1565         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
1566         ctrl &= ~DP_SSC_MASK(pipe);
1567         ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe);
1568         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl);
1569
1570         if (wait_for(COND, 100))
1571                 DRM_ERROR("timeout setting power well state %08x (%08x)\n",
1572                           state,
1573                           vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ));
1574
1575 #undef COND
1576
1577 out:
1578         mutex_unlock(&dev_priv->rps.hw_lock);
1579 }
1580
1581 static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv,
1582                                         struct i915_power_well *power_well)
1583 {
1584         WARN_ON_ONCE(power_well->data != PIPE_A);
1585
1586         chv_set_pipe_power_well(dev_priv, power_well, power_well->count > 0);
1587 }
1588
1589 static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv,
1590                                        struct i915_power_well *power_well)
1591 {
1592         WARN_ON_ONCE(power_well->data != PIPE_A);
1593
1594         chv_set_pipe_power_well(dev_priv, power_well, true);
1595
1596         vlv_display_power_well_init(dev_priv);
1597 }
1598
1599 static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv,
1600                                         struct i915_power_well *power_well)
1601 {
1602         WARN_ON_ONCE(power_well->data != PIPE_A);
1603
1604         vlv_display_power_well_deinit(dev_priv);
1605
1606         chv_set_pipe_power_well(dev_priv, power_well, false);
1607 }
1608
1609 static void
1610 __intel_display_power_get_domain(struct drm_i915_private *dev_priv,
1611                                  enum intel_display_power_domain domain)
1612 {
1613         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1614         struct i915_power_well *power_well;
1615         int i;
1616
1617         for_each_power_well(i, power_well, BIT(domain), power_domains)
1618                 intel_power_well_get(dev_priv, power_well);
1619
1620         power_domains->domain_use_count[domain]++;
1621 }
1622
1623 /**
1624  * intel_display_power_get - grab a power domain reference
1625  * @dev_priv: i915 device instance
1626  * @domain: power domain to reference
1627  *
1628  * This function grabs a power domain reference for @domain and ensures that the
1629  * power domain and all its parents are powered up. Therefore users should only
1630  * grab a reference to the innermost power domain they need.
1631  *
1632  * Any power domain reference obtained by this function must have a symmetric
1633  * call to intel_display_power_put() to release the reference again.
1634  */
1635 void intel_display_power_get(struct drm_i915_private *dev_priv,
1636                              enum intel_display_power_domain domain)
1637 {
1638         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1639
1640         intel_runtime_pm_get(dev_priv);
1641
1642         mutex_lock(&power_domains->lock);
1643
1644         __intel_display_power_get_domain(dev_priv, domain);
1645
1646         mutex_unlock(&power_domains->lock);
1647 }
1648
1649 /**
1650  * intel_display_power_get_if_enabled - grab a reference for an enabled display power domain
1651  * @dev_priv: i915 device instance
1652  * @domain: power domain to reference
1653  *
1654  * This function grabs a power domain reference for @domain and ensures that the
1655  * power domain and all its parents are powered up. Therefore users should only
1656  * grab a reference to the innermost power domain they need.
1657  *
1658  * Any power domain reference obtained by this function must have a symmetric
1659  * call to intel_display_power_put() to release the reference again.
1660  */
1661 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
1662                                         enum intel_display_power_domain domain)
1663 {
1664         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1665         bool is_enabled;
1666
1667         if (!intel_runtime_pm_get_if_in_use(dev_priv))
1668                 return false;
1669
1670         mutex_lock(&power_domains->lock);
1671
1672         if (__intel_display_power_is_enabled(dev_priv, domain)) {
1673                 __intel_display_power_get_domain(dev_priv, domain);
1674                 is_enabled = true;
1675         } else {
1676                 is_enabled = false;
1677         }
1678
1679         mutex_unlock(&power_domains->lock);
1680
1681         if (!is_enabled)
1682                 intel_runtime_pm_put(dev_priv);
1683
1684         return is_enabled;
1685 }
1686
1687 /**
1688  * intel_display_power_put - release a power domain reference
1689  * @dev_priv: i915 device instance
1690  * @domain: power domain to reference
1691  *
1692  * This function drops the power domain reference obtained by
1693  * intel_display_power_get() and might power down the corresponding hardware
1694  * block right away if this is the last reference.
1695  */
1696 void intel_display_power_put(struct drm_i915_private *dev_priv,
1697                              enum intel_display_power_domain domain)
1698 {
1699         struct i915_power_domains *power_domains;
1700         struct i915_power_well *power_well;
1701         int i;
1702
1703         power_domains = &dev_priv->power_domains;
1704
1705         mutex_lock(&power_domains->lock);
1706
1707         WARN(!power_domains->domain_use_count[domain],
1708              "Use count on domain %s is already zero\n",
1709              intel_display_power_domain_str(domain));
1710         power_domains->domain_use_count[domain]--;
1711
1712         for_each_power_well_rev(i, power_well, BIT(domain), power_domains)
1713                 intel_power_well_put(dev_priv, power_well);
1714
1715         mutex_unlock(&power_domains->lock);
1716
1717         intel_runtime_pm_put(dev_priv);
1718 }
1719
1720 #define HSW_DISPLAY_POWER_DOMAINS (                     \
1721         BIT(POWER_DOMAIN_PIPE_B) |                      \
1722         BIT(POWER_DOMAIN_PIPE_C) |                      \
1723         BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) |         \
1724         BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |         \
1725         BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |         \
1726         BIT(POWER_DOMAIN_TRANSCODER_A) |                \
1727         BIT(POWER_DOMAIN_TRANSCODER_B) |                \
1728         BIT(POWER_DOMAIN_TRANSCODER_C) |                \
1729         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |            \
1730         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |            \
1731         BIT(POWER_DOMAIN_PORT_DDI_D_LANES) |            \
1732         BIT(POWER_DOMAIN_PORT_CRT) | /* DDI E */        \
1733         BIT(POWER_DOMAIN_VGA) |                         \
1734         BIT(POWER_DOMAIN_AUDIO) |                       \
1735         BIT(POWER_DOMAIN_INIT))
1736
1737 #define BDW_DISPLAY_POWER_DOMAINS (                     \
1738         BIT(POWER_DOMAIN_PIPE_B) |                      \
1739         BIT(POWER_DOMAIN_PIPE_C) |                      \
1740         BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |         \
1741         BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |         \
1742         BIT(POWER_DOMAIN_TRANSCODER_A) |                \
1743         BIT(POWER_DOMAIN_TRANSCODER_B) |                \
1744         BIT(POWER_DOMAIN_TRANSCODER_C) |                \
1745         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |            \
1746         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |            \
1747         BIT(POWER_DOMAIN_PORT_DDI_D_LANES) |            \
1748         BIT(POWER_DOMAIN_PORT_CRT) | /* DDI E */        \
1749         BIT(POWER_DOMAIN_VGA) |                         \
1750         BIT(POWER_DOMAIN_AUDIO) |                       \
1751         BIT(POWER_DOMAIN_INIT))
1752
1753 #define VLV_DISPLAY_POWER_DOMAINS (             \
1754         BIT(POWER_DOMAIN_PIPE_A) |              \
1755         BIT(POWER_DOMAIN_PIPE_B) |              \
1756         BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
1757         BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
1758         BIT(POWER_DOMAIN_TRANSCODER_A) |        \
1759         BIT(POWER_DOMAIN_TRANSCODER_B) |        \
1760         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |    \
1761         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |    \
1762         BIT(POWER_DOMAIN_PORT_DSI) |            \
1763         BIT(POWER_DOMAIN_PORT_CRT) |            \
1764         BIT(POWER_DOMAIN_VGA) |                 \
1765         BIT(POWER_DOMAIN_AUDIO) |               \
1766         BIT(POWER_DOMAIN_AUX_B) |               \
1767         BIT(POWER_DOMAIN_AUX_C) |               \
1768         BIT(POWER_DOMAIN_GMBUS) |               \
1769         BIT(POWER_DOMAIN_INIT))
1770
1771 #define VLV_DPIO_CMN_BC_POWER_DOMAINS (         \
1772         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |    \
1773         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |    \
1774         BIT(POWER_DOMAIN_PORT_CRT) |            \
1775         BIT(POWER_DOMAIN_AUX_B) |               \
1776         BIT(POWER_DOMAIN_AUX_C) |               \
1777         BIT(POWER_DOMAIN_INIT))
1778
1779 #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS (  \
1780         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |    \
1781         BIT(POWER_DOMAIN_AUX_B) |               \
1782         BIT(POWER_DOMAIN_INIT))
1783
1784 #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS (  \
1785         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |    \
1786         BIT(POWER_DOMAIN_AUX_B) |               \
1787         BIT(POWER_DOMAIN_INIT))
1788
1789 #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS (  \
1790         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |    \
1791         BIT(POWER_DOMAIN_AUX_C) |               \
1792         BIT(POWER_DOMAIN_INIT))
1793
1794 #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS (  \
1795         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |    \
1796         BIT(POWER_DOMAIN_AUX_C) |               \
1797         BIT(POWER_DOMAIN_INIT))
1798
1799 #define CHV_DISPLAY_POWER_DOMAINS (             \
1800         BIT(POWER_DOMAIN_PIPE_A) |              \
1801         BIT(POWER_DOMAIN_PIPE_B) |              \
1802         BIT(POWER_DOMAIN_PIPE_C) |              \
1803         BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
1804         BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
1805         BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
1806         BIT(POWER_DOMAIN_TRANSCODER_A) |        \
1807         BIT(POWER_DOMAIN_TRANSCODER_B) |        \
1808         BIT(POWER_DOMAIN_TRANSCODER_C) |        \
1809         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |    \
1810         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |    \
1811         BIT(POWER_DOMAIN_PORT_DDI_D_LANES) |    \
1812         BIT(POWER_DOMAIN_PORT_DSI) |            \
1813         BIT(POWER_DOMAIN_VGA) |                 \
1814         BIT(POWER_DOMAIN_AUDIO) |               \
1815         BIT(POWER_DOMAIN_AUX_B) |               \
1816         BIT(POWER_DOMAIN_AUX_C) |               \
1817         BIT(POWER_DOMAIN_AUX_D) |               \
1818         BIT(POWER_DOMAIN_GMBUS) |               \
1819         BIT(POWER_DOMAIN_INIT))
1820
1821 #define CHV_DPIO_CMN_BC_POWER_DOMAINS (         \
1822         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |    \
1823         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |    \
1824         BIT(POWER_DOMAIN_AUX_B) |               \
1825         BIT(POWER_DOMAIN_AUX_C) |               \
1826         BIT(POWER_DOMAIN_INIT))
1827
1828 #define CHV_DPIO_CMN_D_POWER_DOMAINS (          \
1829         BIT(POWER_DOMAIN_PORT_DDI_D_LANES) |    \
1830         BIT(POWER_DOMAIN_AUX_D) |               \
1831         BIT(POWER_DOMAIN_INIT))
1832
1833 static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
1834         .sync_hw = i9xx_always_on_power_well_noop,
1835         .enable = i9xx_always_on_power_well_noop,
1836         .disable = i9xx_always_on_power_well_noop,
1837         .is_enabled = i9xx_always_on_power_well_enabled,
1838 };
1839
1840 static const struct i915_power_well_ops chv_pipe_power_well_ops = {
1841         .sync_hw = chv_pipe_power_well_sync_hw,
1842         .enable = chv_pipe_power_well_enable,
1843         .disable = chv_pipe_power_well_disable,
1844         .is_enabled = chv_pipe_power_well_enabled,
1845 };
1846
1847 static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = {
1848         .sync_hw = vlv_power_well_sync_hw,
1849         .enable = chv_dpio_cmn_power_well_enable,
1850         .disable = chv_dpio_cmn_power_well_disable,
1851         .is_enabled = vlv_power_well_enabled,
1852 };
1853
1854 static struct i915_power_well i9xx_always_on_power_well[] = {
1855         {
1856                 .name = "always-on",
1857                 .always_on = 1,
1858                 .domains = POWER_DOMAIN_MASK,
1859                 .ops = &i9xx_always_on_power_well_ops,
1860         },
1861 };
1862
1863 static const struct i915_power_well_ops hsw_power_well_ops = {
1864         .sync_hw = hsw_power_well_sync_hw,
1865         .enable = hsw_power_well_enable,
1866         .disable = hsw_power_well_disable,
1867         .is_enabled = hsw_power_well_enabled,
1868 };
1869
1870 static const struct i915_power_well_ops skl_power_well_ops = {
1871         .sync_hw = skl_power_well_sync_hw,
1872         .enable = skl_power_well_enable,
1873         .disable = skl_power_well_disable,
1874         .is_enabled = skl_power_well_enabled,
1875 };
1876
1877 static const struct i915_power_well_ops gen9_dc_off_power_well_ops = {
1878         .sync_hw = gen9_dc_off_power_well_sync_hw,
1879         .enable = gen9_dc_off_power_well_enable,
1880         .disable = gen9_dc_off_power_well_disable,
1881         .is_enabled = gen9_dc_off_power_well_enabled,
1882 };
1883
1884 static const struct i915_power_well_ops bxt_dpio_cmn_power_well_ops = {
1885         .sync_hw = bxt_dpio_cmn_power_well_sync_hw,
1886         .enable = bxt_dpio_cmn_power_well_enable,
1887         .disable = bxt_dpio_cmn_power_well_disable,
1888         .is_enabled = bxt_dpio_cmn_power_well_enabled,
1889 };
1890
1891 static struct i915_power_well hsw_power_wells[] = {
1892         {
1893                 .name = "always-on",
1894                 .always_on = 1,
1895                 .domains = POWER_DOMAIN_MASK,
1896                 .ops = &i9xx_always_on_power_well_ops,
1897         },
1898         {
1899                 .name = "display",
1900                 .domains = HSW_DISPLAY_POWER_DOMAINS,
1901                 .ops = &hsw_power_well_ops,
1902         },
1903 };
1904
1905 static struct i915_power_well bdw_power_wells[] = {
1906         {
1907                 .name = "always-on",
1908                 .always_on = 1,
1909                 .domains = POWER_DOMAIN_MASK,
1910                 .ops = &i9xx_always_on_power_well_ops,
1911         },
1912         {
1913                 .name = "display",
1914                 .domains = BDW_DISPLAY_POWER_DOMAINS,
1915                 .ops = &hsw_power_well_ops,
1916         },
1917 };
1918
1919 static const struct i915_power_well_ops vlv_display_power_well_ops = {
1920         .sync_hw = vlv_power_well_sync_hw,
1921         .enable = vlv_display_power_well_enable,
1922         .disable = vlv_display_power_well_disable,
1923         .is_enabled = vlv_power_well_enabled,
1924 };
1925
1926 static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = {
1927         .sync_hw = vlv_power_well_sync_hw,
1928         .enable = vlv_dpio_cmn_power_well_enable,
1929         .disable = vlv_dpio_cmn_power_well_disable,
1930         .is_enabled = vlv_power_well_enabled,
1931 };
1932
1933 static const struct i915_power_well_ops vlv_dpio_power_well_ops = {
1934         .sync_hw = vlv_power_well_sync_hw,
1935         .enable = vlv_power_well_enable,
1936         .disable = vlv_power_well_disable,
1937         .is_enabled = vlv_power_well_enabled,
1938 };
1939
1940 static struct i915_power_well vlv_power_wells[] = {
1941         {
1942                 .name = "always-on",
1943                 .always_on = 1,
1944                 .domains = POWER_DOMAIN_MASK,
1945                 .ops = &i9xx_always_on_power_well_ops,
1946                 .data = PUNIT_POWER_WELL_ALWAYS_ON,
1947         },
1948         {
1949                 .name = "display",
1950                 .domains = VLV_DISPLAY_POWER_DOMAINS,
1951                 .data = PUNIT_POWER_WELL_DISP2D,
1952                 .ops = &vlv_display_power_well_ops,
1953         },
1954         {
1955                 .name = "dpio-tx-b-01",
1956                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1957                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1958                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1959                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1960                 .ops = &vlv_dpio_power_well_ops,
1961                 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
1962         },
1963         {
1964                 .name = "dpio-tx-b-23",
1965                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1966                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1967                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1968                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1969                 .ops = &vlv_dpio_power_well_ops,
1970                 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
1971         },
1972         {
1973                 .name = "dpio-tx-c-01",
1974                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1975                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1976                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1977                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1978                 .ops = &vlv_dpio_power_well_ops,
1979                 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
1980         },
1981         {
1982                 .name = "dpio-tx-c-23",
1983                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1984                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1985                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1986                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1987                 .ops = &vlv_dpio_power_well_ops,
1988                 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
1989         },
1990         {
1991                 .name = "dpio-common",
1992                 .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,
1993                 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
1994                 .ops = &vlv_dpio_cmn_power_well_ops,
1995         },
1996 };
1997
1998 static struct i915_power_well chv_power_wells[] = {
1999         {
2000                 .name = "always-on",
2001                 .always_on = 1,
2002                 .domains = POWER_DOMAIN_MASK,
2003                 .ops = &i9xx_always_on_power_well_ops,
2004         },
2005         {
2006                 .name = "display",
2007                 /*
2008                  * Pipe A power well is the new disp2d well. Pipe B and C
2009                  * power wells don't actually exist. Pipe A power well is
2010                  * required for any pipe to work.
2011                  */
2012                 .domains = CHV_DISPLAY_POWER_DOMAINS,
2013                 .data = PIPE_A,
2014                 .ops = &chv_pipe_power_well_ops,
2015         },
2016         {
2017                 .name = "dpio-common-bc",
2018                 .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS,
2019                 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
2020                 .ops = &chv_dpio_cmn_power_well_ops,
2021         },
2022         {
2023                 .name = "dpio-common-d",
2024                 .domains = CHV_DPIO_CMN_D_POWER_DOMAINS,
2025                 .data = PUNIT_POWER_WELL_DPIO_CMN_D,
2026                 .ops = &chv_dpio_cmn_power_well_ops,
2027         },
2028 };
2029
2030 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
2031                                     int power_well_id)
2032 {
2033         struct i915_power_well *power_well;
2034         bool ret;
2035
2036         power_well = lookup_power_well(dev_priv, power_well_id);
2037         ret = power_well->ops->is_enabled(dev_priv, power_well);
2038
2039         return ret;
2040 }
2041
2042 static struct i915_power_well skl_power_wells[] = {
2043         {
2044                 .name = "always-on",
2045                 .always_on = 1,
2046                 .domains = POWER_DOMAIN_MASK,
2047                 .ops = &i9xx_always_on_power_well_ops,
2048                 .data = SKL_DISP_PW_ALWAYS_ON,
2049         },
2050         {
2051                 .name = "power well 1",
2052                 /* Handled by the DMC firmware */
2053                 .domains = 0,
2054                 .ops = &skl_power_well_ops,
2055                 .data = SKL_DISP_PW_1,
2056         },
2057         {
2058                 .name = "MISC IO power well",
2059                 /* Handled by the DMC firmware */
2060                 .domains = 0,
2061                 .ops = &skl_power_well_ops,
2062                 .data = SKL_DISP_PW_MISC_IO,
2063         },
2064         {
2065                 .name = "DC off",
2066                 .domains = SKL_DISPLAY_DC_OFF_POWER_DOMAINS,
2067                 .ops = &gen9_dc_off_power_well_ops,
2068                 .data = SKL_DISP_PW_DC_OFF,
2069         },
2070         {
2071                 .name = "power well 2",
2072                 .domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS,
2073                 .ops = &skl_power_well_ops,
2074                 .data = SKL_DISP_PW_2,
2075         },
2076         {
2077                 .name = "DDI A/E power well",
2078                 .domains = SKL_DISPLAY_DDI_A_E_POWER_DOMAINS,
2079                 .ops = &skl_power_well_ops,
2080                 .data = SKL_DISP_PW_DDI_A_E,
2081         },
2082         {
2083                 .name = "DDI B power well",
2084                 .domains = SKL_DISPLAY_DDI_B_POWER_DOMAINS,
2085                 .ops = &skl_power_well_ops,
2086                 .data = SKL_DISP_PW_DDI_B,
2087         },
2088         {
2089                 .name = "DDI C power well",
2090                 .domains = SKL_DISPLAY_DDI_C_POWER_DOMAINS,
2091                 .ops = &skl_power_well_ops,
2092                 .data = SKL_DISP_PW_DDI_C,
2093         },
2094         {
2095                 .name = "DDI D power well",
2096                 .domains = SKL_DISPLAY_DDI_D_POWER_DOMAINS,
2097                 .ops = &skl_power_well_ops,
2098                 .data = SKL_DISP_PW_DDI_D,
2099         },
2100 };
2101
2102 static struct i915_power_well bxt_power_wells[] = {
2103         {
2104                 .name = "always-on",
2105                 .always_on = 1,
2106                 .domains = POWER_DOMAIN_MASK,
2107                 .ops = &i9xx_always_on_power_well_ops,
2108         },
2109         {
2110                 .name = "power well 1",
2111                 .domains = 0,
2112                 .ops = &skl_power_well_ops,
2113                 .data = SKL_DISP_PW_1,
2114         },
2115         {
2116                 .name = "DC off",
2117                 .domains = BXT_DISPLAY_DC_OFF_POWER_DOMAINS,
2118                 .ops = &gen9_dc_off_power_well_ops,
2119                 .data = SKL_DISP_PW_DC_OFF,
2120         },
2121         {
2122                 .name = "power well 2",
2123                 .domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS,
2124                 .ops = &skl_power_well_ops,
2125                 .data = SKL_DISP_PW_2,
2126         },
2127         {
2128                 .name = "dpio-common-a",
2129                 .domains = BXT_DPIO_CMN_A_POWER_DOMAINS,
2130                 .ops = &bxt_dpio_cmn_power_well_ops,
2131                 .data = BXT_DPIO_CMN_A,
2132         },
2133         {
2134                 .name = "dpio-common-bc",
2135                 .domains = BXT_DPIO_CMN_BC_POWER_DOMAINS,
2136                 .ops = &bxt_dpio_cmn_power_well_ops,
2137                 .data = BXT_DPIO_CMN_BC,
2138         },
2139 };
2140
2141 static int
2142 sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv,
2143                                    int disable_power_well)
2144 {
2145         if (disable_power_well >= 0)
2146                 return !!disable_power_well;
2147
2148         return 1;
2149 }
2150
2151 static uint32_t get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
2152                                     int enable_dc)
2153 {
2154         uint32_t mask;
2155         int requested_dc;
2156         int max_dc;
2157
2158         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
2159                 max_dc = 2;
2160                 mask = 0;
2161         } else if (IS_BROXTON(dev_priv)) {
2162                 max_dc = 1;
2163                 /*
2164                  * DC9 has a separate HW flow from the rest of the DC states,
2165                  * not depending on the DMC firmware. It's needed by system
2166                  * suspend/resume, so allow it unconditionally.
2167                  */
2168                 mask = DC_STATE_EN_DC9;
2169         } else {
2170                 max_dc = 0;
2171                 mask = 0;
2172         }
2173
2174         if (!i915.disable_power_well)
2175                 max_dc = 0;
2176
2177         if (enable_dc >= 0 && enable_dc <= max_dc) {
2178                 requested_dc = enable_dc;
2179         } else if (enable_dc == -1) {
2180                 requested_dc = max_dc;
2181         } else if (enable_dc > max_dc && enable_dc <= 2) {
2182                 DRM_DEBUG_KMS("Adjusting requested max DC state (%d->%d)\n",
2183                               enable_dc, max_dc);
2184                 requested_dc = max_dc;
2185         } else {
2186                 DRM_ERROR("Unexpected value for enable_dc (%d)\n", enable_dc);
2187                 requested_dc = max_dc;
2188         }
2189
2190         if (requested_dc > 1)
2191                 mask |= DC_STATE_EN_UPTO_DC6;
2192         if (requested_dc > 0)
2193                 mask |= DC_STATE_EN_UPTO_DC5;
2194
2195         DRM_DEBUG_KMS("Allowed DC state mask %02x\n", mask);
2196
2197         return mask;
2198 }
2199
2200 #define set_power_wells(power_domains, __power_wells) ({                \
2201         (power_domains)->power_wells = (__power_wells);                 \
2202         (power_domains)->power_well_count = ARRAY_SIZE(__power_wells);  \
2203 })
2204
2205 /**
2206  * intel_power_domains_init - initializes the power domain structures
2207  * @dev_priv: i915 device instance
2208  *
2209  * Initializes the power domain structures for @dev_priv depending upon the
2210  * supported platform.
2211  */
2212 int intel_power_domains_init(struct drm_i915_private *dev_priv)
2213 {
2214         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2215
2216         i915.disable_power_well = sanitize_disable_power_well_option(dev_priv,
2217                                                      i915.disable_power_well);
2218         dev_priv->csr.allowed_dc_mask = get_allowed_dc_mask(dev_priv,
2219                                                             i915.enable_dc);
2220
2221         BUILD_BUG_ON(POWER_DOMAIN_NUM > 31);
2222
2223         mutex_init(&power_domains->lock);
2224
2225         /*
2226          * The enabling order will be from lower to higher indexed wells,
2227          * the disabling order is reversed.
2228          */
2229         if (IS_HASWELL(dev_priv)) {
2230                 set_power_wells(power_domains, hsw_power_wells);
2231         } else if (IS_BROADWELL(dev_priv)) {
2232                 set_power_wells(power_domains, bdw_power_wells);
2233         } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
2234                 set_power_wells(power_domains, skl_power_wells);
2235         } else if (IS_BROXTON(dev_priv)) {
2236                 set_power_wells(power_domains, bxt_power_wells);
2237         } else if (IS_CHERRYVIEW(dev_priv)) {
2238                 set_power_wells(power_domains, chv_power_wells);
2239         } else if (IS_VALLEYVIEW(dev_priv)) {
2240                 set_power_wells(power_domains, vlv_power_wells);
2241         } else {
2242                 set_power_wells(power_domains, i9xx_always_on_power_well);
2243         }
2244
2245         return 0;
2246 }
2247
2248 /**
2249  * intel_power_domains_fini - finalizes the power domain structures
2250  * @dev_priv: i915 device instance
2251  *
2252  * Finalizes the power domain structures for @dev_priv depending upon the
2253  * supported platform. This function also disables runtime pm and ensures that
2254  * the device stays powered up so that the driver can be reloaded.
2255  */
2256 void intel_power_domains_fini(struct drm_i915_private *dev_priv)
2257 {
2258         struct device *device = &dev_priv->dev->pdev->dev;
2259
2260         /*
2261          * The i915.ko module is still not prepared to be loaded when
2262          * the power well is not enabled, so just enable it in case
2263          * we're going to unload/reload.
2264          * The following also reacquires the RPM reference the core passed
2265          * to the driver during loading, which is dropped in
2266          * intel_runtime_pm_enable(). We have to hand back the control of the
2267          * device to the core with this reference held.
2268          */
2269         intel_display_set_init_power(dev_priv, true);
2270
2271         /* Remove the refcount we took to keep power well support disabled. */
2272         if (!i915.disable_power_well)
2273                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
2274
2275         /*
2276          * Remove the refcount we took in intel_runtime_pm_enable() in case
2277          * the platform doesn't support runtime PM.
2278          */
2279         if (!HAS_RUNTIME_PM(dev_priv))
2280                 pm_runtime_put(device);
2281 }
2282
2283 static void intel_power_domains_sync_hw(struct drm_i915_private *dev_priv)
2284 {
2285         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2286         struct i915_power_well *power_well;
2287         int i;
2288
2289         mutex_lock(&power_domains->lock);
2290         for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
2291                 power_well->ops->sync_hw(dev_priv, power_well);
2292                 power_well->hw_enabled = power_well->ops->is_enabled(dev_priv,
2293                                                                      power_well);
2294         }
2295         mutex_unlock(&power_domains->lock);
2296 }
2297
2298 static void gen9_dbuf_enable(struct drm_i915_private *dev_priv)
2299 {
2300         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
2301         POSTING_READ(DBUF_CTL);
2302
2303         udelay(10);
2304
2305         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
2306                 DRM_ERROR("DBuf power enable timeout\n");
2307 }
2308
2309 static void gen9_dbuf_disable(struct drm_i915_private *dev_priv)
2310 {
2311         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
2312         POSTING_READ(DBUF_CTL);
2313
2314         udelay(10);
2315
2316         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
2317                 DRM_ERROR("DBuf power disable timeout!\n");
2318 }
2319
2320 static void skl_display_core_init(struct drm_i915_private *dev_priv,
2321                                    bool resume)
2322 {
2323         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2324         struct i915_power_well *well;
2325         uint32_t val;
2326
2327         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
2328
2329         /* enable PCH reset handshake */
2330         val = I915_READ(HSW_NDE_RSTWRN_OPT);
2331         I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
2332
2333         /* enable PG1 and Misc I/O */
2334         mutex_lock(&power_domains->lock);
2335
2336         well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
2337         intel_power_well_enable(dev_priv, well);
2338
2339         well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);
2340         intel_power_well_enable(dev_priv, well);
2341
2342         mutex_unlock(&power_domains->lock);
2343
2344         skl_init_cdclk(dev_priv);
2345
2346         gen9_dbuf_enable(dev_priv);
2347
2348         if (resume && dev_priv->csr.dmc_payload)
2349                 intel_csr_load_program(dev_priv);
2350 }
2351
2352 static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
2353 {
2354         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2355         struct i915_power_well *well;
2356
2357         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
2358
2359         gen9_dbuf_disable(dev_priv);
2360
2361         skl_uninit_cdclk(dev_priv);
2362
2363         /* The spec doesn't call for removing the reset handshake flag */
2364         /* disable PG1 and Misc I/O */
2365
2366         mutex_lock(&power_domains->lock);
2367
2368         well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);
2369         intel_power_well_disable(dev_priv, well);
2370
2371         well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
2372         intel_power_well_disable(dev_priv, well);
2373
2374         mutex_unlock(&power_domains->lock);
2375 }
2376
2377 void bxt_display_core_init(struct drm_i915_private *dev_priv,
2378                            bool resume)
2379 {
2380         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2381         struct i915_power_well *well;
2382         uint32_t val;
2383
2384         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
2385
2386         /*
2387          * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
2388          * or else the reset will hang because there is no PCH to respond.
2389          * Move the handshake programming to initialization sequence.
2390          * Previously was left up to BIOS.
2391          */
2392         val = I915_READ(HSW_NDE_RSTWRN_OPT);
2393         val &= ~RESET_PCH_HANDSHAKE_ENABLE;
2394         I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
2395
2396         /* Enable PG1 */
2397         mutex_lock(&power_domains->lock);
2398
2399         well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
2400         intel_power_well_enable(dev_priv, well);
2401
2402         mutex_unlock(&power_domains->lock);
2403
2404         bxt_init_cdclk(dev_priv);
2405
2406         gen9_dbuf_enable(dev_priv);
2407
2408         if (resume && dev_priv->csr.dmc_payload)
2409                 intel_csr_load_program(dev_priv);
2410 }
2411
2412 void bxt_display_core_uninit(struct drm_i915_private *dev_priv)
2413 {
2414         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2415         struct i915_power_well *well;
2416
2417         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
2418
2419         gen9_dbuf_disable(dev_priv);
2420
2421         bxt_uninit_cdclk(dev_priv);
2422
2423         /* The spec doesn't call for removing the reset handshake flag */
2424
2425         /* Disable PG1 */
2426         mutex_lock(&power_domains->lock);
2427
2428         well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
2429         intel_power_well_disable(dev_priv, well);
2430
2431         mutex_unlock(&power_domains->lock);
2432 }
2433
2434 static void chv_phy_control_init(struct drm_i915_private *dev_priv)
2435 {
2436         struct i915_power_well *cmn_bc =
2437                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
2438         struct i915_power_well *cmn_d =
2439                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D);
2440
2441         /*
2442          * DISPLAY_PHY_CONTROL can get corrupted if read. As a
2443          * workaround never ever read DISPLAY_PHY_CONTROL, and
2444          * instead maintain a shadow copy ourselves. Use the actual
2445          * power well state and lane status to reconstruct the
2446          * expected initial value.
2447          */
2448         dev_priv->chv_phy_control =
2449                 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY0) |
2450                 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY1) |
2451                 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH0) |
2452                 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH1) |
2453                 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY1, DPIO_CH0);
2454
2455         /*
2456          * If all lanes are disabled we leave the override disabled
2457          * with all power down bits cleared to match the state we
2458          * would use after disabling the port. Otherwise enable the
2459          * override and set the lane powerdown bits accding to the
2460          * current lane status.
2461          */
2462         if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) {
2463                 uint32_t status = I915_READ(DPLL(PIPE_A));
2464                 unsigned int mask;
2465
2466                 mask = status & DPLL_PORTB_READY_MASK;
2467                 if (mask == 0xf)
2468                         mask = 0x0;
2469                 else
2470                         dev_priv->chv_phy_control |=
2471                                 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0);
2472
2473                 dev_priv->chv_phy_control |=
2474                         PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH0);
2475
2476                 mask = (status & DPLL_PORTC_READY_MASK) >> 4;
2477                 if (mask == 0xf)
2478                         mask = 0x0;
2479                 else
2480                         dev_priv->chv_phy_control |=
2481                                 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1);
2482
2483                 dev_priv->chv_phy_control |=
2484                         PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH1);
2485
2486                 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0);
2487
2488                 dev_priv->chv_phy_assert[DPIO_PHY0] = false;
2489         } else {
2490                 dev_priv->chv_phy_assert[DPIO_PHY0] = true;
2491         }
2492
2493         if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) {
2494                 uint32_t status = I915_READ(DPIO_PHY_STATUS);
2495                 unsigned int mask;
2496
2497                 mask = status & DPLL_PORTD_READY_MASK;
2498
2499                 if (mask == 0xf)
2500                         mask = 0x0;
2501                 else
2502                         dev_priv->chv_phy_control |=
2503                                 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0);
2504
2505                 dev_priv->chv_phy_control |=
2506                         PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY1, DPIO_CH0);
2507
2508                 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1);
2509
2510                 dev_priv->chv_phy_assert[DPIO_PHY1] = false;
2511         } else {
2512                 dev_priv->chv_phy_assert[DPIO_PHY1] = true;
2513         }
2514
2515         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
2516
2517         DRM_DEBUG_KMS("Initial PHY_CONTROL=0x%08x\n",
2518                       dev_priv->chv_phy_control);
2519 }
2520
2521 static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv)
2522 {
2523         struct i915_power_well *cmn =
2524                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
2525         struct i915_power_well *disp2d =
2526                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D);
2527
2528         /* If the display might be already active skip this */
2529         if (cmn->ops->is_enabled(dev_priv, cmn) &&
2530             disp2d->ops->is_enabled(dev_priv, disp2d) &&
2531             I915_READ(DPIO_CTL) & DPIO_CMNRST)
2532                 return;
2533
2534         DRM_DEBUG_KMS("toggling display PHY side reset\n");
2535
2536         /* cmnlane needs DPLL registers */
2537         disp2d->ops->enable(dev_priv, disp2d);
2538
2539         /*
2540          * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx:
2541          * Need to assert and de-assert PHY SB reset by gating the
2542          * common lane power, then un-gating it.
2543          * Simply ungating isn't enough to reset the PHY enough to get
2544          * ports and lanes running.
2545          */
2546         cmn->ops->disable(dev_priv, cmn);
2547 }
2548
2549 /**
2550  * intel_power_domains_init_hw - initialize hardware power domain state
2551  * @dev_priv: i915 device instance
2552  * @resume: Called from resume code paths or not
2553  *
2554  * This function initializes the hardware power domain state and enables all
2555  * power domains using intel_display_set_init_power().
2556  */
2557 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume)
2558 {
2559         struct drm_device *dev = dev_priv->dev;
2560         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2561
2562         power_domains->initializing = true;
2563
2564         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
2565                 skl_display_core_init(dev_priv, resume);
2566         } else if (IS_BROXTON(dev)) {
2567                 bxt_display_core_init(dev_priv, resume);
2568         } else if (IS_CHERRYVIEW(dev)) {
2569                 mutex_lock(&power_domains->lock);
2570                 chv_phy_control_init(dev_priv);
2571                 mutex_unlock(&power_domains->lock);
2572         } else if (IS_VALLEYVIEW(dev)) {
2573                 mutex_lock(&power_domains->lock);
2574                 vlv_cmnlane_wa(dev_priv);
2575                 mutex_unlock(&power_domains->lock);
2576         }
2577
2578         /* For now, we need the power well to be always enabled. */
2579         intel_display_set_init_power(dev_priv, true);
2580         /* Disable power support if the user asked so. */
2581         if (!i915.disable_power_well)
2582                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
2583         intel_power_domains_sync_hw(dev_priv);
2584         power_domains->initializing = false;
2585 }
2586
2587 /**
2588  * intel_power_domains_suspend - suspend power domain state
2589  * @dev_priv: i915 device instance
2590  *
2591  * This function prepares the hardware power domain state before entering
2592  * system suspend. It must be paired with intel_power_domains_init_hw().
2593  */
2594 void intel_power_domains_suspend(struct drm_i915_private *dev_priv)
2595 {
2596         /*
2597          * Even if power well support was disabled we still want to disable
2598          * power wells while we are system suspended.
2599          */
2600         if (!i915.disable_power_well)
2601                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
2602
2603         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
2604                 skl_display_core_uninit(dev_priv);
2605         else if (IS_BROXTON(dev_priv))
2606                 bxt_display_core_uninit(dev_priv);
2607 }
2608
2609 /**
2610  * intel_runtime_pm_get - grab a runtime pm reference
2611  * @dev_priv: i915 device instance
2612  *
2613  * This function grabs a device-level runtime pm reference (mostly used for GEM
2614  * code to ensure the GTT or GT is on) and ensures that it is powered up.
2615  *
2616  * Any runtime pm reference obtained by this function must have a symmetric
2617  * call to intel_runtime_pm_put() to release the reference again.
2618  */
2619 void intel_runtime_pm_get(struct drm_i915_private *dev_priv)
2620 {
2621         struct drm_device *dev = dev_priv->dev;
2622         struct device *device = &dev->pdev->dev;
2623
2624         pm_runtime_get_sync(device);
2625
2626         atomic_inc(&dev_priv->pm.wakeref_count);
2627         assert_rpm_wakelock_held(dev_priv);
2628 }
2629
2630 /**
2631  * intel_runtime_pm_get_if_in_use - grab a runtime pm reference if device in use
2632  * @dev_priv: i915 device instance
2633  *
2634  * This function grabs a device-level runtime pm reference if the device is
2635  * already in use and ensures that it is powered up.
2636  *
2637  * Any runtime pm reference obtained by this function must have a symmetric
2638  * call to intel_runtime_pm_put() to release the reference again.
2639  */
2640 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv)
2641 {
2642         struct drm_device *dev = dev_priv->dev;
2643         struct device *device = &dev->pdev->dev;
2644
2645         if (IS_ENABLED(CONFIG_PM)) {
2646                 int ret = pm_runtime_get_if_in_use(device);
2647
2648                 /*
2649                  * In cases runtime PM is disabled by the RPM core and we get
2650                  * an -EINVAL return value we are not supposed to call this
2651                  * function, since the power state is undefined. This applies
2652                  * atm to the late/early system suspend/resume handlers.
2653                  */
2654                 WARN_ON_ONCE(ret < 0);
2655                 if (ret <= 0)
2656                         return false;
2657         }
2658
2659         atomic_inc(&dev_priv->pm.wakeref_count);
2660         assert_rpm_wakelock_held(dev_priv);
2661
2662         return true;
2663 }
2664
2665 /**
2666  * intel_runtime_pm_get_noresume - grab a runtime pm reference
2667  * @dev_priv: i915 device instance
2668  *
2669  * This function grabs a device-level runtime pm reference (mostly used for GEM
2670  * code to ensure the GTT or GT is on).
2671  *
2672  * It will _not_ power up the device but instead only check that it's powered
2673  * on.  Therefore it is only valid to call this functions from contexts where
2674  * the device is known to be powered up and where trying to power it up would
2675  * result in hilarity and deadlocks. That pretty much means only the system
2676  * suspend/resume code where this is used to grab runtime pm references for
2677  * delayed setup down in work items.
2678  *
2679  * Any runtime pm reference obtained by this function must have a symmetric
2680  * call to intel_runtime_pm_put() to release the reference again.
2681  */
2682 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv)
2683 {
2684         struct drm_device *dev = dev_priv->dev;
2685         struct device *device = &dev->pdev->dev;
2686
2687         assert_rpm_wakelock_held(dev_priv);
2688         pm_runtime_get_noresume(device);
2689
2690         atomic_inc(&dev_priv->pm.wakeref_count);
2691 }
2692
2693 /**
2694  * intel_runtime_pm_put - release a runtime pm reference
2695  * @dev_priv: i915 device instance
2696  *
2697  * This function drops the device-level runtime pm reference obtained by
2698  * intel_runtime_pm_get() and might power down the corresponding
2699  * hardware block right away if this is the last reference.
2700  */
2701 void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
2702 {
2703         struct drm_device *dev = dev_priv->dev;
2704         struct device *device = &dev->pdev->dev;
2705
2706         assert_rpm_wakelock_held(dev_priv);
2707         if (atomic_dec_and_test(&dev_priv->pm.wakeref_count))
2708                 atomic_inc(&dev_priv->pm.atomic_seq);
2709
2710         pm_runtime_mark_last_busy(device);
2711         pm_runtime_put_autosuspend(device);
2712 }
2713
2714 /**
2715  * intel_runtime_pm_enable - enable runtime pm
2716  * @dev_priv: i915 device instance
2717  *
2718  * This function enables runtime pm at the end of the driver load sequence.
2719  *
2720  * Note that this function does currently not enable runtime pm for the
2721  * subordinate display power domains. That is only done on the first modeset
2722  * using intel_display_set_init_power().
2723  */
2724 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv)
2725 {
2726         struct drm_device *dev = dev_priv->dev;
2727         struct device *device = &dev->pdev->dev;
2728
2729         pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */
2730         pm_runtime_mark_last_busy(device);
2731
2732         /*
2733          * Take a permanent reference to disable the RPM functionality and drop
2734          * it only when unloading the driver. Use the low level get/put helpers,
2735          * so the driver's own RPM reference tracking asserts also work on
2736          * platforms without RPM support.
2737          */
2738         if (!HAS_RUNTIME_PM(dev)) {
2739                 pm_runtime_dont_use_autosuspend(device);
2740                 pm_runtime_get_sync(device);
2741         } else {
2742                 pm_runtime_use_autosuspend(device);
2743         }
2744
2745         /*
2746          * The core calls the driver load handler with an RPM reference held.
2747          * We drop that here and will reacquire it during unloading in
2748          * intel_power_domains_fini().
2749          */
2750         pm_runtime_put_autosuspend(device);
2751 }
2752