drivers/gpu/drm/i915/intel_sprite.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *   Jesse Barnes <jbarnes@virtuousgeek.org>
  25  *
  26  * New plane/sprite handling.
  27  *
  28  * The older chips had a separate interface for programming plane related
  29  * registers; newer ones are much simpler and we can use the new DRM plane
  30  * support.
  31  */
  32 #include <drm/drmP.h>
  33 #include <drm/drm_crtc.h>
  34 #include <drm/drm_fourcc.h>
  35 #include <drm/drm_rect.h>
  36 #include <drm/drm_atomic.h>
  37 #include <drm/drm_plane_helper.h>
  38 #include "intel_drv.h"
  39 #include <drm/i915_drm.h>
  40 #include "i915_drv.h"
  41
  42 static bool
  43 format_is_yuv(uint32_t format)
  44 {
  45         switch (format) {
  46         case DRM_FORMAT_YUYV:
  47         case DRM_FORMAT_UYVY:
  48         case DRM_FORMAT_VYUY:
  49         case DRM_FORMAT_YVYU:
  50                 return true;
  51         default:
  52                 return false;
  53         }
  54 }
  55
  56 static int usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
  57                               int usecs)
  58 {
  59         /* paranoia */
  60         if (!adjusted_mode->crtc_htotal)
  61                 return 1;
  62
  63         return DIV_ROUND_UP(usecs * adjusted_mode->crtc_clock,
  64                             1000 * adjusted_mode->crtc_htotal);
  65 }
  66
  67 /**
  68  * intel_pipe_update_start() - start update of a set of display registers
  69  * @crtc: the crtc of which the registers are going to be updated
  70  * @start_vbl_count: vblank counter return pointer used for error checking
  71  *
  72  * Mark the start of an update to pipe registers that should be updated
  73  * atomically regarding vblank. If the next vblank will happens within
  74  * the next 100 us, this function waits until the vblank passes.
  75  *
  76  * After a successful call to this function, interrupts will be disabled
  77  * until a subsequent call to intel_pipe_update_end(). That is done to
  78  * avoid random delays. The value written to @start_vbl_count should be
  79  * supplied to intel_pipe_update_end() for error checking.
  80  */
  81 void intel_pipe_update_start(struct intel_crtc *crtc)
  82 {
  83         struct drm_device *dev = crtc->base.dev;
  84         const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
  85         enum pipe pipe = crtc->pipe;
  86         long timeout = msecs_to_jiffies_timeout(1);
  87         int scanline, min, max, vblank_start;
  88         wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);
  89         DEFINE_WAIT(wait);
  90
  91         vblank_start = adjusted_mode->crtc_vblank_start;
  92         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
  93                 vblank_start = DIV_ROUND_UP(vblank_start, 2);
  94
  95         /* FIXME needs to be calibrated sensibly */
  96         min = vblank_start - usecs_to_scanlines(adjusted_mode, 100);
  97         max = vblank_start - 1;
  98
  99         local_irq_disable();
 100
 101         if (min <= 0 || max <= 0)
 102                 return;
 103
 104         if (WARN_ON(drm_crtc_vblank_get(&crtc->base)))
 105                 return;
 106
 107         crtc->debug.min_vbl = min;
 108         crtc->debug.max_vbl = max;
 109         trace_i915_pipe_update_start(crtc);
 110
 111         for (;;) {
 112                 /*
 113                  * prepare_to_wait() has a memory barrier, which guarantees
 114                  * other CPUs can see the task state update by the time we
 115                  * read the scanline.
 116                  */
 117                 prepare_to_wait(wq, &wait, TASK_UNINTERRUPTIBLE);
 118
 119                 scanline = intel_get_crtc_scanline(crtc);
 120                 if (scanline < min || scanline > max)
 121                         break;
 122
 123                 if (timeout <= 0) {
 124                         DRM_ERROR("Potential atomic update failure on pipe %c\n",
 125                                   pipe_name(crtc->pipe));
 126                         break;
 127                 }
 128
 129                 local_irq_enable();
 130
 131                 timeout = schedule_timeout(timeout);
 132
 133                 local_irq_disable();
 134         }
 135
 136         finish_wait(wq, &wait);
 137
 138         drm_crtc_vblank_put(&crtc->base);
 139
 140         crtc->debug.scanline_start = scanline;
 141         crtc->debug.start_vbl_time = ktime_get();
 142         crtc->debug.start_vbl_count =
 143                 dev->driver->get_vblank_counter(dev, pipe);
 144
 145         trace_i915_pipe_update_vblank_evaded(crtc);
 146 }
 147
 148 /**
 149  * intel_pipe_update_end() - end update of a set of display registers
 150  * @crtc: the crtc of which the registers were updated
 151  * @start_vbl_count: start vblank counter (used for error checking)
 152  *
 153  * Mark the end of an update started with intel_pipe_update_start(). This
 154  * re-enables interrupts and verifies the update was actually completed
 155  * before a vblank using the value of @start_vbl_count.
 156  */
 157 void intel_pipe_update_end(struct intel_crtc *crtc)
 158 {
 159         struct drm_device *dev = crtc->base.dev;
 160         enum pipe pipe = crtc->pipe;
 161         int scanline_end = intel_get_crtc_scanline(crtc);
 162         u32 end_vbl_count = dev->driver->get_vblank_counter(dev, pipe);
 163         ktime_t end_vbl_time = ktime_get();
 164
 165         trace_i915_pipe_update_end(crtc, end_vbl_count, scanline_end);
 166
 167         local_irq_enable();
 168
 169         if (crtc->debug.start_vbl_count &&
 170             crtc->debug.start_vbl_count != end_vbl_count) {
 171                 DRM_ERROR("Atomic update failure on pipe %c (start=%u end=%u) time %lld us, min %d, max %d, scanline start %d, end %d\n",
 172                           pipe_name(pipe), crtc->debug.start_vbl_count,
 173                           end_vbl_count,
 174                           ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time),
 175                           crtc->debug.min_vbl, crtc->debug.max_vbl,
 176                           crtc->debug.scanline_start, scanline_end);
 177         }
 178 }
 179
 180 static void
 181 skl_update_plane(struct drm_plane *drm_plane,
 182                  const struct intel_crtc_state *crtc_state,
 183                  const struct intel_plane_state *plane_state)
 184 {
 185         struct drm_device *dev = drm_plane->dev;
 186         struct drm_i915_private *dev_priv = dev->dev_private;
 187         struct intel_plane *intel_plane = to_intel_plane(drm_plane);
 188         struct drm_framebuffer *fb = plane_state->base.fb;
 189         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
 190         const int pipe = intel_plane->pipe;
 191         const int plane = intel_plane->plane + 1;
 192         u32 plane_ctl, stride_div, stride;
 193         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 194         u32 surf_addr;
 195         u32 tile_height, plane_offset, plane_size;
 196         unsigned int rotation;
 197         int x_offset, y_offset;
 198         int crtc_x = plane_state->dst.x1;
 199         int crtc_y = plane_state->dst.y1;
 200         uint32_t crtc_w = drm_rect_width(&plane_state->dst);
 201         uint32_t crtc_h = drm_rect_height(&plane_state->dst);
 202         uint32_t x = plane_state->src.x1 >> 16;
 203         uint32_t y = plane_state->src.y1 >> 16;
 204         uint32_t src_w = drm_rect_width(&plane_state->src) >> 16;
 205         uint32_t src_h = drm_rect_height(&plane_state->src) >> 16;
 206         const struct intel_scaler *scaler =
 207                 &crtc_state->scaler_state.scalers[plane_state->scaler_id];
 208
 209         plane_ctl = PLANE_CTL_ENABLE |
 210                 PLANE_CTL_PIPE_GAMMA_ENABLE |
 211                 PLANE_CTL_PIPE_CSC_ENABLE;
 212
 213         plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
 214         plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
 215
 216         rotation = plane_state->base.rotation;
 217         plane_ctl |= skl_plane_ctl_rotation(rotation);
 218
 219         stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
 220                                                fb->pixel_format);
 221
 222         /* Sizes are 0 based */
 223         src_w--;
 224         src_h--;
 225         crtc_w--;
 226         crtc_h--;
 227
 228         if (key->flags) {
 229                 I915_WRITE(PLANE_KEYVAL(pipe, plane), key->min_value);
 230                 I915_WRITE(PLANE_KEYMAX(pipe, plane), key->max_value);
 231                 I915_WRITE(PLANE_KEYMSK(pipe, plane), key->channel_mask);
 232         }
 233
 234         if (key->flags & I915_SET_COLORKEY_DESTINATION)
 235                 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
 236         else if (key->flags & I915_SET_COLORKEY_SOURCE)
 237                 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
 238
 239         surf_addr = intel_plane_obj_offset(intel_plane, obj, 0);
 240
 241         if (intel_rotation_90_or_270(rotation)) {
 242                 /* stride: Surface height in tiles */
 243                 tile_height = intel_tile_height(dev, fb->pixel_format,
 244                                                 fb->modifier[0], 0);
 245                 stride = DIV_ROUND_UP(fb->height, tile_height);
 246                 plane_size = (src_w << 16) | src_h;
 247                 x_offset = stride * tile_height - y - (src_h + 1);
 248                 y_offset = x;
 249         } else {
 250                 stride = fb->pitches[0] / stride_div;
 251                 plane_size = (src_h << 16) | src_w;
 252                 x_offset = x;
 253                 y_offset = y;
 254         }
 255         plane_offset = y_offset << 16 | x_offset;
 256
 257         I915_WRITE(PLANE_OFFSET(pipe, plane), plane_offset);
 258         I915_WRITE(PLANE_STRIDE(pipe, plane), stride);
 259         I915_WRITE(PLANE_SIZE(pipe, plane), plane_size);
 260
 261         /* program plane scaler */
 262         if (plane_state->scaler_id >= 0) {
 263                 uint32_t ps_ctrl = 0;
 264                 int scaler_id = plane_state->scaler_id;
 265
 266                 DRM_DEBUG_KMS("plane = %d PS_PLANE_SEL(plane) = 0x%x\n", plane,
 267                         PS_PLANE_SEL(plane));
 268                 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane) | scaler->mode;
 269                 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
 270                 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
 271                 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (crtc_x << 16) | crtc_y);
 272                 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id),
 273                         ((crtc_w + 1) << 16)|(crtc_h + 1));
 274
 275                 I915_WRITE(PLANE_POS(pipe, plane), 0);
 276         } else {
 277                 I915_WRITE(PLANE_POS(pipe, plane), (crtc_y << 16) | crtc_x);
 278         }
 279
 280         I915_WRITE(PLANE_CTL(pipe, plane), plane_ctl);
 281         I915_WRITE(PLANE_SURF(pipe, plane), surf_addr);
 282         POSTING_READ(PLANE_SURF(pipe, plane));
 283 }
 284
 285 static void
 286 skl_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc)
 287 {
 288         struct drm_device *dev = dplane->dev;
 289         struct drm_i915_private *dev_priv = dev->dev_private;
 290         struct intel_plane *intel_plane = to_intel_plane(dplane);
 291         const int pipe = intel_plane->pipe;
 292         const int plane = intel_plane->plane + 1;
 293
 294         I915_WRITE(PLANE_CTL(pipe, plane), 0);
 295
 296         I915_WRITE(PLANE_SURF(pipe, plane), 0);
 297         POSTING_READ(PLANE_SURF(pipe, plane));
 298 }
 299
 300 static void
 301 chv_update_csc(struct intel_plane *intel_plane, uint32_t format)
 302 {
 303         struct drm_i915_private *dev_priv = intel_plane->base.dev->dev_private;
 304         int plane = intel_plane->plane;
 305
 306         /* Seems RGB data bypasses the CSC always */
 307         if (!format_is_yuv(format))
 308                 return;
 309
 310         /*
 311          * BT.601 limited range YCbCr -> full range RGB
 312          *
 313          * |r|   | 6537 4769     0|   |cr  |
 314          * |g| = |-3330 4769 -1605| x |y-64|
 315          * |b|   |    0 4769  8263|   |cb  |
 316          *
 317          * Cb and Cr apparently come in as signed already, so no
 318          * need for any offset. For Y we need to remove the offset.
 319          */
 320         I915_WRITE(SPCSCYGOFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(-64));
 321         I915_WRITE(SPCSCCBOFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(0));
 322         I915_WRITE(SPCSCCROFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(0));
 323
 324         I915_WRITE(SPCSCC01(plane), SPCSC_C1(4769) | SPCSC_C0(6537));
 325         I915_WRITE(SPCSCC23(plane), SPCSC_C1(-3330) | SPCSC_C0(0));
 326         I915_WRITE(SPCSCC45(plane), SPCSC_C1(-1605) | SPCSC_C0(4769));
 327         I915_WRITE(SPCSCC67(plane), SPCSC_C1(4769) | SPCSC_C0(0));
 328         I915_WRITE(SPCSCC8(plane), SPCSC_C0(8263));
 329
 330         I915_WRITE(SPCSCYGICLAMP(plane), SPCSC_IMAX(940) | SPCSC_IMIN(64));
 331         I915_WRITE(SPCSCCBICLAMP(plane), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
 332         I915_WRITE(SPCSCCRICLAMP(plane), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
 333
 334         I915_WRITE(SPCSCYGOCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
 335         I915_WRITE(SPCSCCBOCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
 336         I915_WRITE(SPCSCCROCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
 337 }
 338
 339 static void
 340 vlv_update_plane(struct drm_plane *dplane,
 341                  const struct intel_crtc_state *crtc_state,
 342                  const struct intel_plane_state *plane_state)
 343 {
 344         struct drm_device *dev = dplane->dev;
 345         struct drm_i915_private *dev_priv = dev->dev_private;
 346         struct intel_plane *intel_plane = to_intel_plane(dplane);
 347         struct drm_framebuffer *fb = plane_state->base.fb;
 348         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
 349         int pipe = intel_plane->pipe;
 350         int plane = intel_plane->plane;
 351         u32 sprctl;
 352         unsigned long sprsurf_offset, linear_offset;
 353         int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
 354         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 355         int crtc_x = plane_state->dst.x1;
 356         int crtc_y = plane_state->dst.y1;
 357         uint32_t crtc_w = drm_rect_width(&plane_state->dst);
 358         uint32_t crtc_h = drm_rect_height(&plane_state->dst);
 359         uint32_t x = plane_state->src.x1 >> 16;
 360         uint32_t y = plane_state->src.y1 >> 16;
 361         uint32_t src_w = drm_rect_width(&plane_state->src) >> 16;
 362         uint32_t src_h = drm_rect_height(&plane_state->src) >> 16;
 363
 364         sprctl = SP_ENABLE;
 365
 366         switch (fb->pixel_format) {
 367         case DRM_FORMAT_YUYV:
 368                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YUYV;
 369                 break;
 370         case DRM_FORMAT_YVYU:
 371                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YVYU;
 372                 break;
 373         case DRM_FORMAT_UYVY:
 374                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_UYVY;
 375                 break;
 376         case DRM_FORMAT_VYUY:
 377                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY;
 378                 break;
 379         case DRM_FORMAT_RGB565:
 380                 sprctl |= SP_FORMAT_BGR565;
 381                 break;
 382         case DRM_FORMAT_XRGB8888:
 383                 sprctl |= SP_FORMAT_BGRX8888;
 384                 break;
 385         case DRM_FORMAT_ARGB8888:
 386                 sprctl |= SP_FORMAT_BGRA8888;
 387                 break;
 388         case DRM_FORMAT_XBGR2101010:
 389                 sprctl |= SP_FORMAT_RGBX1010102;
 390                 break;
 391         case DRM_FORMAT_ABGR2101010:
 392                 sprctl |= SP_FORMAT_RGBA1010102;
 393                 break;
 394         case DRM_FORMAT_XBGR8888:
 395                 sprctl |= SP_FORMAT_RGBX8888;
 396                 break;
 397         case DRM_FORMAT_ABGR8888:
 398                 sprctl |= SP_FORMAT_RGBA8888;
 399                 break;
 400         default:
 401                 /*
 402                  * If we get here one of the upper layers failed to filter
 403                  * out the unsupported plane formats
 404                  */
 405                 BUG();
 406                 break;
 407         }
 408
 409         /*
 410          * Enable gamma to match primary/cursor plane behaviour.
 411          * FIXME should be user controllable via propertiesa.
 412          */
 413         sprctl |= SP_GAMMA_ENABLE;
 414
 415         if (obj->tiling_mode != I915_TILING_NONE)
 416                 sprctl |= SP_TILED;
 417
 418         /* Sizes are 0 based */
 419         src_w--;
 420         src_h--;
 421         crtc_w--;
 422         crtc_h--;
 423
 424         linear_offset = y * fb->pitches[0] + x * pixel_size;
 425         sprsurf_offset = intel_gen4_compute_page_offset(dev_priv,
 426                                                         &x, &y,
 427                                                         obj->tiling_mode,
 428                                                         pixel_size,
 429                                                         fb->pitches[0]);
 430         linear_offset -= sprsurf_offset;
 431
 432         if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
 433                 sprctl |= SP_ROTATE_180;
 434
 435                 x += src_w;
 436                 y += src_h;
 437                 linear_offset += src_h * fb->pitches[0] + src_w * pixel_size;
 438         }
 439
 440         if (key->flags) {
 441                 I915_WRITE(SPKEYMINVAL(pipe, plane), key->min_value);
 442                 I915_WRITE(SPKEYMAXVAL(pipe, plane), key->max_value);
 443                 I915_WRITE(SPKEYMSK(pipe, plane), key->channel_mask);
 444         }
 445
 446         if (key->flags & I915_SET_COLORKEY_SOURCE)
 447                 sprctl |= SP_SOURCE_KEY;
 448
 449         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B)
 450                 chv_update_csc(intel_plane, fb->pixel_format);
 451
 452         I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]);
 453         I915_WRITE(SPPOS(pipe, plane), (crtc_y << 16) | crtc_x);
 454
 455         if (obj->tiling_mode != I915_TILING_NONE)
 456                 I915_WRITE(SPTILEOFF(pipe, plane), (y << 16) | x);
 457         else
 458                 I915_WRITE(SPLINOFF(pipe, plane), linear_offset);
 459
 460         I915_WRITE(SPCONSTALPHA(pipe, plane), 0);
 461
 462         I915_WRITE(SPSIZE(pipe, plane), (crtc_h << 16) | crtc_w);
 463         I915_WRITE(SPCNTR(pipe, plane), sprctl);
 464         I915_WRITE(SPSURF(pipe, plane), i915_gem_obj_ggtt_offset(obj) +
 465                    sprsurf_offset);
 466         POSTING_READ(SPSURF(pipe, plane));
 467 }
 468
 469 static void
 470 vlv_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc)
 471 {
 472         struct drm_device *dev = dplane->dev;
 473         struct drm_i915_private *dev_priv = dev->dev_private;
 474         struct intel_plane *intel_plane = to_intel_plane(dplane);
 475         int pipe = intel_plane->pipe;
 476         int plane = intel_plane->plane;
 477
 478         I915_WRITE(SPCNTR(pipe, plane), 0);
 479
 480         I915_WRITE(SPSURF(pipe, plane), 0);
 481         POSTING_READ(SPSURF(pipe, plane));
 482 }
 483
 484 static void
 485 ivb_update_plane(struct drm_plane *plane,
 486                  const struct intel_crtc_state *crtc_state,
 487                  const struct intel_plane_state *plane_state)
 488 {
 489         struct drm_device *dev = plane->dev;
 490         struct drm_i915_private *dev_priv = dev->dev_private;
 491         struct intel_plane *intel_plane = to_intel_plane(plane);
 492         struct drm_framebuffer *fb = plane_state->base.fb;
 493         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
 494         enum pipe pipe = intel_plane->pipe;
 495         u32 sprctl, sprscale = 0;
 496         unsigned long sprsurf_offset, linear_offset;
 497         int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
 498         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 499         int crtc_x = plane_state->dst.x1;
 500         int crtc_y = plane_state->dst.y1;
 501         uint32_t crtc_w = drm_rect_width(&plane_state->dst);
 502         uint32_t crtc_h = drm_rect_height(&plane_state->dst);
 503         uint32_t x = plane_state->src.x1 >> 16;
 504         uint32_t y = plane_state->src.y1 >> 16;
 505         uint32_t src_w = drm_rect_width(&plane_state->src) >> 16;
 506         uint32_t src_h = drm_rect_height(&plane_state->src) >> 16;
 507
 508         sprctl = SPRITE_ENABLE;
 509
 510         switch (fb->pixel_format) {
 511         case DRM_FORMAT_XBGR8888:
 512                 sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;
 513                 break;
 514         case DRM_FORMAT_XRGB8888:
 515                 sprctl |= SPRITE_FORMAT_RGBX888;
 516                 break;
 517         case DRM_FORMAT_YUYV:
 518                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV;
 519                 break;
 520         case DRM_FORMAT_YVYU:
 521                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU;
 522                 break;
 523         case DRM_FORMAT_UYVY:
 524                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY;
 525                 break;
 526         case DRM_FORMAT_VYUY:
 527                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY;
 528                 break;
 529         default:
 530                 BUG();
 531         }
 532
 533         /*
 534          * Enable gamma to match primary/cursor plane behaviour.
 535          * FIXME should be user controllable via propertiesa.
 536          */
 537         sprctl |= SPRITE_GAMMA_ENABLE;
 538
 539         if (obj->tiling_mode != I915_TILING_NONE)
 540                 sprctl |= SPRITE_TILED;
 541
 542         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
 543                 sprctl &= ~SPRITE_TRICKLE_FEED_DISABLE;
 544         else
 545                 sprctl |= SPRITE_TRICKLE_FEED_DISABLE;
 546
 547         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
 548                 sprctl |= SPRITE_PIPE_CSC_ENABLE;
 549
 550         /* Sizes are 0 based */
 551         src_w--;
 552         src_h--;
 553         crtc_w--;
 554         crtc_h--;
 555
 556         if (crtc_w != src_w || crtc_h != src_h)
 557                 sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
 558
 559         linear_offset = y * fb->pitches[0] + x * pixel_size;
 560         sprsurf_offset =
 561                 intel_gen4_compute_page_offset(dev_priv,
 562                                                &x, &y, obj->tiling_mode,
 563                                                pixel_size, fb->pitches[0]);
 564         linear_offset -= sprsurf_offset;
 565
 566         if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
 567                 sprctl |= SPRITE_ROTATE_180;
 568
 569                 /* HSW and BDW does this automagically in hardware */
 570                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
 571                         x += src_w;
 572                         y += src_h;
 573                         linear_offset += src_h * fb->pitches[0] +
 574                                 src_w * pixel_size;
 575                 }
 576         }
 577
 578         if (key->flags) {
 579                 I915_WRITE(SPRKEYVAL(pipe), key->min_value);
 580                 I915_WRITE(SPRKEYMAX(pipe), key->max_value);
 581                 I915_WRITE(SPRKEYMSK(pipe), key->channel_mask);
 582         }
 583
 584         if (key->flags & I915_SET_COLORKEY_DESTINATION)
 585                 sprctl |= SPRITE_DEST_KEY;
 586         else if (key->flags & I915_SET_COLORKEY_SOURCE)
 587                 sprctl |= SPRITE_SOURCE_KEY;
 588
 589         I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]);
 590         I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x);
 591
 592         /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
 593          * register */
 594         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
 595                 I915_WRITE(SPROFFSET(pipe), (y << 16) | x);
 596         else if (obj->tiling_mode != I915_TILING_NONE)
 597                 I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x);
 598         else
 599                 I915_WRITE(SPRLINOFF(pipe), linear_offset);
 600
 601         I915_WRITE(SPRSIZE(pipe), (crtc_h << 16) | crtc_w);
 602         if (intel_plane->can_scale)
 603                 I915_WRITE(SPRSCALE(pipe), sprscale);
 604         I915_WRITE(SPRCTL(pipe), sprctl);
 605         I915_WRITE(SPRSURF(pipe),
 606                    i915_gem_obj_ggtt_offset(obj) + sprsurf_offset);
 607         POSTING_READ(SPRSURF(pipe));
 608 }
 609
 610 static void
 611 ivb_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc)
 612 {
 613         struct drm_device *dev = plane->dev;
 614         struct drm_i915_private *dev_priv = dev->dev_private;
 615         struct intel_plane *intel_plane = to_intel_plane(plane);
 616         int pipe = intel_plane->pipe;
 617
 618         I915_WRITE(SPRCTL(pipe), 0);
 619         /* Can't leave the scaler enabled... */
 620         if (intel_plane->can_scale)
 621                 I915_WRITE(SPRSCALE(pipe), 0);
 622
 623         I915_WRITE(SPRSURF(pipe), 0);
 624         POSTING_READ(SPRSURF(pipe));
 625 }
 626
 627 static void
 628 ilk_update_plane(struct drm_plane *plane,
 629                  const struct intel_crtc_state *crtc_state,
 630                  const struct intel_plane_state *plane_state)
 631 {
 632         struct drm_device *dev = plane->dev;
 633         struct drm_i915_private *dev_priv = dev->dev_private;
 634         struct intel_plane *intel_plane = to_intel_plane(plane);
 635         struct drm_framebuffer *fb = plane_state->base.fb;
 636         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
 637         int pipe = intel_plane->pipe;
 638         unsigned long dvssurf_offset, linear_offset;
 639         u32 dvscntr, dvsscale;
 640         int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
 641         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 642         int crtc_x = plane_state->dst.x1;
 643         int crtc_y = plane_state->dst.y1;
 644         uint32_t crtc_w = drm_rect_width(&plane_state->dst);
 645         uint32_t crtc_h = drm_rect_height(&plane_state->dst);
 646         uint32_t x = plane_state->src.x1 >> 16;
 647         uint32_t y = plane_state->src.y1 >> 16;
 648         uint32_t src_w = drm_rect_width(&plane_state->src) >> 16;
 649         uint32_t src_h = drm_rect_height(&plane_state->src) >> 16;
 650
 651         dvscntr = DVS_ENABLE;
 652
 653         switch (fb->pixel_format) {
 654         case DRM_FORMAT_XBGR8888:
 655                 dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR;
 656                 break;
 657         case DRM_FORMAT_XRGB8888:
 658                 dvscntr |= DVS_FORMAT_RGBX888;
 659                 break;
 660         case DRM_FORMAT_YUYV:
 661                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV;
 662                 break;
 663         case DRM_FORMAT_YVYU:
 664                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU;
 665                 break;
 666         case DRM_FORMAT_UYVY:
 667                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY;
 668                 break;
 669         case DRM_FORMAT_VYUY:
 670                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY;
 671                 break;
 672         default:
 673                 BUG();
 674         }
 675
 676         /*
 677          * Enable gamma to match primary/cursor plane behaviour.
 678          * FIXME should be user controllable via propertiesa.
 679          */
 680         dvscntr |= DVS_GAMMA_ENABLE;
 681
 682         if (obj->tiling_mode != I915_TILING_NONE)
 683                 dvscntr |= DVS_TILED;
 684
 685         if (IS_GEN6(dev))
 686                 dvscntr |= DVS_TRICKLE_FEED_DISABLE; /* must disable */
 687
 688         /* Sizes are 0 based */
 689         src_w--;
 690         src_h--;
 691         crtc_w--;
 692         crtc_h--;
 693
 694         dvsscale = 0;
 695         if (crtc_w != src_w || crtc_h != src_h)
 696                 dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
 697
 698         linear_offset = y * fb->pitches[0] + x * pixel_size;
 699         dvssurf_offset =
 700                 intel_gen4_compute_page_offset(dev_priv,
 701                                                &x, &y, obj->tiling_mode,
 702                                                pixel_size, fb->pitches[0]);
 703         linear_offset -= dvssurf_offset;
 704
 705         if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
 706                 dvscntr |= DVS_ROTATE_180;
 707
 708                 x += src_w;
 709                 y += src_h;
 710                 linear_offset += src_h * fb->pitches[0] + src_w * pixel_size;
 711         }
 712
 713         if (key->flags) {
 714                 I915_WRITE(DVSKEYVAL(pipe), key->min_value);
 715                 I915_WRITE(DVSKEYMAX(pipe), key->max_value);
 716                 I915_WRITE(DVSKEYMSK(pipe), key->channel_mask);
 717         }
 718
 719         if (key->flags & I915_SET_COLORKEY_DESTINATION)
 720                 dvscntr |= DVS_DEST_KEY;
 721         else if (key->flags & I915_SET_COLORKEY_SOURCE)
 722                 dvscntr |= DVS_SOURCE_KEY;
 723
 724         I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]);
 725         I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x);
 726
 727         if (obj->tiling_mode != I915_TILING_NONE)
 728                 I915_WRITE(DVSTILEOFF(pipe), (y << 16) | x);
 729         else
 730                 I915_WRITE(DVSLINOFF(pipe), linear_offset);
 731
 732         I915_WRITE(DVSSIZE(pipe), (crtc_h << 16) | crtc_w);
 733         I915_WRITE(DVSSCALE(pipe), dvsscale);
 734         I915_WRITE(DVSCNTR(pipe), dvscntr);
 735         I915_WRITE(DVSSURF(pipe),
 736                    i915_gem_obj_ggtt_offset(obj) + dvssurf_offset);
 737         POSTING_READ(DVSSURF(pipe));
 738 }
 739
 740 static void
 741 ilk_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc)
 742 {
 743         struct drm_device *dev = plane->dev;
 744         struct drm_i915_private *dev_priv = dev->dev_private;
 745         struct intel_plane *intel_plane = to_intel_plane(plane);
 746         int pipe = intel_plane->pipe;
 747
 748         I915_WRITE(DVSCNTR(pipe), 0);
 749         /* Disable the scaler */
 750         I915_WRITE(DVSSCALE(pipe), 0);
 751
 752         I915_WRITE(DVSSURF(pipe), 0);
 753         POSTING_READ(DVSSURF(pipe));
 754 }
 755
 756 static int
 757 intel_check_sprite_plane(struct drm_plane *plane,
 758                          struct intel_crtc_state *crtc_state,
 759                          struct intel_plane_state *state)
 760 {
 761         struct drm_device *dev = plane->dev;
 762         struct drm_crtc *crtc = state->base.crtc;
 763         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 764         struct intel_plane *intel_plane = to_intel_plane(plane);
 765         struct drm_framebuffer *fb = state->base.fb;
 766         int crtc_x, crtc_y;
 767         unsigned int crtc_w, crtc_h;
 768         uint32_t src_x, src_y, src_w, src_h;
 769         struct drm_rect *src = &state->src;
 770         struct drm_rect *dst = &state->dst;
 771         const struct drm_rect *clip = &state->clip;
 772         int hscale, vscale;
 773         int max_scale, min_scale;
 774         bool can_scale;
 775         int pixel_size;
 776
 777         if (!fb) {
 778                 state->visible = false;
 779                 return 0;
 780         }
 781
 782         /* Don't modify another pipe's plane */
 783         if (intel_plane->pipe != intel_crtc->pipe) {
 784                 DRM_DEBUG_KMS("Wrong plane <-> crtc mapping\n");
 785                 return -EINVAL;
 786         }
 787
 788         /* FIXME check all gen limits */
 789         if (fb->width < 3 || fb->height < 3 || fb->pitches[0] > 16384) {
 790                 DRM_DEBUG_KMS("Unsuitable framebuffer for plane\n");
 791                 return -EINVAL;
 792         }
 793
 794         /* setup can_scale, min_scale, max_scale */
 795         if (INTEL_INFO(dev)->gen >= 9) {
 796                 /* use scaler when colorkey is not required */
 797                 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
 798                         can_scale = 1;
 799                         min_scale = 1;
 800                         max_scale = skl_max_scale(intel_crtc, crtc_state);
 801                 } else {
 802                         can_scale = 0;
 803                         min_scale = DRM_PLANE_HELPER_NO_SCALING;
 804                         max_scale = DRM_PLANE_HELPER_NO_SCALING;
 805                 }
 806         } else {
 807                 can_scale = intel_plane->can_scale;
 808                 max_scale = intel_plane->max_downscale << 16;
 809                 min_scale = intel_plane->can_scale ? 1 : (1 << 16);
 810         }
 811
 812         /*
 813          * FIXME the following code does a bunch of fuzzy adjustments to the
 814          * coordinates and sizes. We probably need some way to decide whether
 815          * more strict checking should be done instead.
 816          */
 817         drm_rect_rotate(src, fb->width << 16, fb->height << 16,
 818                         state->base.rotation);
 819
 820         hscale = drm_rect_calc_hscale_relaxed(src, dst, min_scale, max_scale);
 821         BUG_ON(hscale < 0);
 822
 823         vscale = drm_rect_calc_vscale_relaxed(src, dst, min_scale, max_scale);
 824         BUG_ON(vscale < 0);
 825
 826         state->visible = drm_rect_clip_scaled(src, dst, clip, hscale, vscale);
 827
 828         crtc_x = dst->x1;
 829         crtc_y = dst->y1;
 830         crtc_w = drm_rect_width(dst);
 831         crtc_h = drm_rect_height(dst);
 832
 833         if (state->visible) {
 834                 /* check again in case clipping clamped the results */
 835                 hscale = drm_rect_calc_hscale(src, dst, min_scale, max_scale);
 836                 if (hscale < 0) {
 837                         DRM_DEBUG_KMS("Horizontal scaling factor out of limits\n");
 838                         drm_rect_debug_print("src: ", src, true);
 839                         drm_rect_debug_print("dst: ", dst, false);
 840
 841                         return hscale;
 842                 }
 843
 844                 vscale = drm_rect_calc_vscale(src, dst, min_scale, max_scale);
 845                 if (vscale < 0) {
 846                         DRM_DEBUG_KMS("Vertical scaling factor out of limits\n");
 847                         drm_rect_debug_print("src: ", src, true);
 848                         drm_rect_debug_print("dst: ", dst, false);
 849
 850                         return vscale;
 851                 }
 852
 853                 /* Make the source viewport size an exact multiple of the scaling factors. */
 854                 drm_rect_adjust_size(src,
 855                                      drm_rect_width(dst) * hscale - drm_rect_width(src),
 856                                      drm_rect_height(dst) * vscale - drm_rect_height(src));
 857
 858                 drm_rect_rotate_inv(src, fb->width << 16, fb->height << 16,
 859                                     state->base.rotation);
 860
 861                 /* sanity check to make sure the src viewport wasn't enlarged */
 862                 WARN_ON(src->x1 < (int) state->base.src_x ||
 863                         src->y1 < (int) state->base.src_y ||
 864                         src->x2 > (int) state->base.src_x + state->base.src_w ||
 865                         src->y2 > (int) state->base.src_y + state->base.src_h);
 866
 867                 /*
 868                  * Hardware doesn't handle subpixel coordinates.
 869                  * Adjust to (macro)pixel boundary, but be careful not to
 870                  * increase the source viewport size, because that could
 871                  * push the downscaling factor out of bounds.
 872                  */
 873                 src_x = src->x1 >> 16;
 874                 src_w = drm_rect_width(src) >> 16;
 875                 src_y = src->y1 >> 16;
 876                 src_h = drm_rect_height(src) >> 16;
 877
 878                 if (format_is_yuv(fb->pixel_format)) {
 879                         src_x &= ~1;
 880                         src_w &= ~1;
 881
 882                         /*
 883                          * Must keep src and dst the
 884                          * same if we can't scale.
 885                          */
 886                         if (!can_scale)
 887                                 crtc_w &= ~1;
 888
 889                         if (crtc_w == 0)
 890                                 state->visible = false;
 891                 }
 892         }
 893
 894         /* Check size restrictions when scaling */
 895         if (state->visible && (src_w != crtc_w || src_h != crtc_h)) {
 896                 unsigned int width_bytes;
 897
 898                 WARN_ON(!can_scale);
 899
 900                 /* FIXME interlacing min height is 6 */
 901
 902                 if (crtc_w < 3 || crtc_h < 3)
 903                         state->visible = false;
 904
 905                 if (src_w < 3 || src_h < 3)
 906                         state->visible = false;
 907
 908                 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
 909                 width_bytes = ((src_x * pixel_size) & 63) +
 910                                         src_w * pixel_size;
 911
 912                 if (INTEL_INFO(dev)->gen < 9 && (src_w > 2048 || src_h > 2048 ||
 913                     width_bytes > 4096 || fb->pitches[0] > 4096)) {
 914                         DRM_DEBUG_KMS("Source dimensions exceed hardware limits\n");
 915                         return -EINVAL;
 916                 }
 917         }
 918
 919         if (state->visible) {
 920                 src->x1 = src_x << 16;
 921                 src->x2 = (src_x + src_w) << 16;
 922                 src->y1 = src_y << 16;
 923                 src->y2 = (src_y + src_h) << 16;
 924         }
 925
 926         dst->x1 = crtc_x;
 927         dst->x2 = crtc_x + crtc_w;
 928         dst->y1 = crtc_y;
 929         dst->y2 = crtc_y + crtc_h;
 930
 931         return 0;
 932 }
 933
 934 static void
 935 intel_commit_sprite_plane(struct drm_plane *plane,
 936                           struct intel_plane_state *state)
 937 {
 938         struct intel_plane *intel_plane = to_intel_plane(plane);
 939
 940         if (state->visible) {
 941                 struct intel_crtc_state *crtc_state =
 942                         to_intel_crtc(state->base.crtc)->config;
 943
 944                 intel_plane->update_plane(plane, crtc_state, state);
 945         } else {
 946                 struct drm_crtc *crtc = state->base.crtc;
 947
 948                 intel_plane->disable_plane(plane, crtc ?: plane->crtc);
 949         }
 950 }
 951
 952 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
 953                               struct drm_file *file_priv)
 954 {
 955         struct drm_intel_sprite_colorkey *set = data;
 956         struct drm_plane *plane;
 957         struct drm_plane_state *plane_state;
 958         struct drm_atomic_state *state;
 959         struct drm_modeset_acquire_ctx ctx;
 960         int ret = 0;
 961
 962         /* Make sure we don't try to enable both src & dest simultaneously */
 963         if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
 964                 return -EINVAL;
 965
 966         if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
 967             set->flags & I915_SET_COLORKEY_DESTINATION)
 968                 return -EINVAL;
 969
 970         plane = drm_plane_find(dev, set->plane_id);
 971         if (!plane || plane->type != DRM_PLANE_TYPE_OVERLAY)
 972                 return -ENOENT;
 973
 974         drm_modeset_acquire_init(&ctx, 0);
 975
 976         state = drm_atomic_state_alloc(plane->dev);
 977         if (!state) {
 978                 ret = -ENOMEM;
 979                 goto out;
 980         }
 981         state->acquire_ctx = &ctx;
 982
 983         while (1) {
 984                 plane_state = drm_atomic_get_plane_state(state, plane);
 985                 ret = PTR_ERR_OR_ZERO(plane_state);
 986                 if (!ret) {
 987                         to_intel_plane_state(plane_state)->ckey = *set;
 988                         ret = drm_atomic_commit(state);
 989                 }
 990
 991                 if (ret != -EDEADLK)
 992                         break;
 993
 994                 drm_atomic_state_clear(state);
 995                 drm_modeset_backoff(&ctx);
 996         }
 997
 998         if (ret)
 999                 drm_atomic_state_free(state);
1000
1001 out:
1002         drm_modeset_drop_locks(&ctx);
1003         drm_modeset_acquire_fini(&ctx);
1004         return ret;
1005 }
1006
1007 static const uint32_t ilk_plane_formats[] = {
1008         DRM_FORMAT_XRGB8888,
1009         DRM_FORMAT_YUYV,
1010         DRM_FORMAT_YVYU,
1011         DRM_FORMAT_UYVY,
1012         DRM_FORMAT_VYUY,
1013 };
1014
1015 static const uint32_t snb_plane_formats[] = {
1016         DRM_FORMAT_XBGR8888,
1017         DRM_FORMAT_XRGB8888,
1018         DRM_FORMAT_YUYV,
1019         DRM_FORMAT_YVYU,
1020         DRM_FORMAT_UYVY,
1021         DRM_FORMAT_VYUY,
1022 };
1023
1024 static const uint32_t vlv_plane_formats[] = {
1025         DRM_FORMAT_RGB565,
1026         DRM_FORMAT_ABGR8888,
1027         DRM_FORMAT_ARGB8888,
1028         DRM_FORMAT_XBGR8888,
1029         DRM_FORMAT_XRGB8888,
1030         DRM_FORMAT_XBGR2101010,
1031         DRM_FORMAT_ABGR2101010,
1032         DRM_FORMAT_YUYV,
1033         DRM_FORMAT_YVYU,
1034         DRM_FORMAT_UYVY,
1035         DRM_FORMAT_VYUY,
1036 };
1037
1038 static uint32_t skl_plane_formats[] = {
1039         DRM_FORMAT_RGB565,
1040         DRM_FORMAT_ABGR8888,
1041         DRM_FORMAT_ARGB8888,
1042         DRM_FORMAT_XBGR8888,
1043         DRM_FORMAT_XRGB8888,
1044         DRM_FORMAT_YUYV,
1045         DRM_FORMAT_YVYU,
1046         DRM_FORMAT_UYVY,
1047         DRM_FORMAT_VYUY,
1048 };
1049
1050 int
1051 intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane)
1052 {
1053         struct intel_plane *intel_plane;
1054         struct intel_plane_state *state;
1055         unsigned long possible_crtcs;
1056         const uint32_t *plane_formats;
1057         int num_plane_formats;
1058         int ret;
1059
1060         if (INTEL_INFO(dev)->gen < 5)
1061                 return -ENODEV;
1062
1063         intel_plane = kzalloc(sizeof(*intel_plane), GFP_KERNEL);
1064         if (!intel_plane)
1065                 return -ENOMEM;
1066
1067         state = intel_create_plane_state(&intel_plane->base);
1068         if (!state) {
1069                 kfree(intel_plane);
1070                 return -ENOMEM;
1071         }
1072         intel_plane->base.state = &state->base;
1073
1074         switch (INTEL_INFO(dev)->gen) {
1075         case 5:
1076         case 6:
1077                 intel_plane->can_scale = true;
1078                 intel_plane->max_downscale = 16;
1079                 intel_plane->update_plane = ilk_update_plane;
1080                 intel_plane->disable_plane = ilk_disable_plane;
1081
1082                 if (IS_GEN6(dev)) {
1083                         plane_formats = snb_plane_formats;
1084                         num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1085                 } else {
1086                         plane_formats = ilk_plane_formats;
1087                         num_plane_formats = ARRAY_SIZE(ilk_plane_formats);
1088                 }
1089                 break;
1090
1091         case 7:
1092         case 8:
1093                 if (IS_IVYBRIDGE(dev)) {
1094                         intel_plane->can_scale = true;
1095                         intel_plane->max_downscale = 2;
1096                 } else {
1097                         intel_plane->can_scale = false;
1098                         intel_plane->max_downscale = 1;
1099                 }
1100
1101                 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1102                         intel_plane->update_plane = vlv_update_plane;
1103                         intel_plane->disable_plane = vlv_disable_plane;
1104
1105                         plane_formats = vlv_plane_formats;
1106                         num_plane_formats = ARRAY_SIZE(vlv_plane_formats);
1107                 } else {
1108                         intel_plane->update_plane = ivb_update_plane;
1109                         intel_plane->disable_plane = ivb_disable_plane;
1110
1111                         plane_formats = snb_plane_formats;
1112                         num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1113                 }
1114                 break;
1115         case 9:
1116                 intel_plane->can_scale = true;
1117                 intel_plane->update_plane = skl_update_plane;
1118                 intel_plane->disable_plane = skl_disable_plane;
1119                 state->scaler_id = -1;
1120
1121                 plane_formats = skl_plane_formats;
1122                 num_plane_formats = ARRAY_SIZE(skl_plane_formats);
1123                 break;
1124         default:
1125                 kfree(intel_plane);
1126                 return -ENODEV;
1127         }
1128
1129         intel_plane->pipe = pipe;
1130         intel_plane->plane = plane;
1131         intel_plane->frontbuffer_bit = INTEL_FRONTBUFFER_SPRITE(pipe, plane);
1132         intel_plane->check_plane = intel_check_sprite_plane;
1133         intel_plane->commit_plane = intel_commit_sprite_plane;
1134         possible_crtcs = (1 << pipe);
1135         ret = drm_universal_plane_init(dev, &intel_plane->base, possible_crtcs,
1136                                        &intel_plane_funcs,
1137                                        plane_formats, num_plane_formats,
1138                                        DRM_PLANE_TYPE_OVERLAY);
1139         if (ret) {
1140                 kfree(intel_plane);
1141                 goto out;
1142         }
1143
1144         intel_create_rotation_property(dev, intel_plane);
1145
1146         drm_plane_helper_add(&intel_plane->base, &intel_plane_helper_funcs);
1147
1148 out:
1149         return ret;
1150 }