drivers/gpu/drm/i915/intel_sprite.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *   Jesse Barnes <jbarnes@virtuousgeek.org>
  25  *
  26  * New plane/sprite handling.
  27  *
  28  * The older chips had a separate interface for programming plane related
  29  * registers; newer ones are much simpler and we can use the new DRM plane
  30  * support.
  31  */
  32 #include <drm/drmP.h>
  33 #include <drm/drm_crtc.h>
  34 #include <drm/drm_fourcc.h>
  35 #include "intel_drv.h"
  36 #include <drm/i915_drm.h>
  37 #include "i915_drv.h"
  38
  39 static void
  40 ivb_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb,
  41                  struct drm_i915_gem_object *obj, int crtc_x, int crtc_y,
  42                  unsigned int crtc_w, unsigned int crtc_h,
  43                  uint32_t x, uint32_t y,
  44                  uint32_t src_w, uint32_t src_h)
  45 {
  46         struct drm_device *dev = plane->dev;
  47         struct drm_i915_private *dev_priv = dev->dev_private;
  48         struct intel_plane *intel_plane = to_intel_plane(plane);
  49         int pipe = intel_plane->pipe;
  50         u32 sprctl, sprscale = 0;
  51         int pixel_size;
  52
  53         sprctl = I915_READ(SPRCTL(pipe));
  54
  55         /* Mask out pixel format bits in case we change it */
  56         sprctl &= ~SPRITE_PIXFORMAT_MASK;
  57         sprctl &= ~SPRITE_RGB_ORDER_RGBX;
  58         sprctl &= ~SPRITE_YUV_BYTE_ORDER_MASK;
  59         sprctl &= ~SPRITE_TILED;
  60
  61         switch (fb->pixel_format) {
  62         case DRM_FORMAT_XBGR8888:
  63                 sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;
  64                 pixel_size = 4;
  65                 break;
  66         case DRM_FORMAT_XRGB8888:
  67                 sprctl |= SPRITE_FORMAT_RGBX888;
  68                 pixel_size = 4;
  69                 break;
  70         case DRM_FORMAT_YUYV:
  71                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV;
  72                 pixel_size = 2;
  73                 break;
  74         case DRM_FORMAT_YVYU:
  75                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU;
  76                 pixel_size = 2;
  77                 break;
  78         case DRM_FORMAT_UYVY:
  79                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY;
  80                 pixel_size = 2;
  81                 break;
  82         case DRM_FORMAT_VYUY:
  83                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY;
  84                 pixel_size = 2;
  85                 break;
  86         default:
  87                 DRM_DEBUG_DRIVER("bad pixel format, assuming RGBX888\n");
  88                 sprctl |= SPRITE_FORMAT_RGBX888;
  89                 pixel_size = 4;
  90                 break;
  91         }
  92
  93         if (obj->tiling_mode != I915_TILING_NONE)
  94                 sprctl |= SPRITE_TILED;
  95
  96         /* must disable */
  97         sprctl |= SPRITE_TRICKLE_FEED_DISABLE;
  98         sprctl |= SPRITE_ENABLE;
  99
 100         /* Sizes are 0 based */
 101         src_w--;
 102         src_h--;
 103         crtc_w--;
 104         crtc_h--;
 105
 106         intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size);
 107
 108         /*
 109          * IVB workaround: must disable low power watermarks for at least
 110          * one frame before enabling scaling.  LP watermarks can be re-enabled
 111          * when scaling is disabled.
 112          */
 113         if (crtc_w != src_w || crtc_h != src_h) {
 114                 if (!dev_priv->sprite_scaling_enabled) {
 115                         dev_priv->sprite_scaling_enabled = true;
 116                         intel_update_watermarks(dev);
 117                         intel_wait_for_vblank(dev, pipe);
 118                 }
 119                 sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
 120         } else {
 121                 if (dev_priv->sprite_scaling_enabled) {
 122                         dev_priv->sprite_scaling_enabled = false;
 123                         /* potentially re-enable LP watermarks */
 124                         intel_update_watermarks(dev);
 125                 }
 126         }
 127
 128         I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]);
 129         I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x);
 130         if (obj->tiling_mode != I915_TILING_NONE) {
 131                 I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x);
 132         } else {
 133                 unsigned long offset;
 134
 135                 offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
 136                 I915_WRITE(SPRLINOFF(pipe), offset);
 137         }
 138         I915_WRITE(SPRSIZE(pipe), (crtc_h << 16) | crtc_w);
 139         if (intel_plane->can_scale)
 140                 I915_WRITE(SPRSCALE(pipe), sprscale);
 141         I915_WRITE(SPRCTL(pipe), sprctl);
 142         I915_MODIFY_DISPBASE(SPRSURF(pipe), obj->gtt_offset);
 143         POSTING_READ(SPRSURF(pipe));
 144 }
 145
 146 static void
 147 ivb_disable_plane(struct drm_plane *plane)
 148 {
 149         struct drm_device *dev = plane->dev;
 150         struct drm_i915_private *dev_priv = dev->dev_private;
 151         struct intel_plane *intel_plane = to_intel_plane(plane);
 152         int pipe = intel_plane->pipe;
 153
 154         I915_WRITE(SPRCTL(pipe), I915_READ(SPRCTL(pipe)) & ~SPRITE_ENABLE);
 155         /* Can't leave the scaler enabled... */
 156         if (intel_plane->can_scale)
 157                 I915_WRITE(SPRSCALE(pipe), 0);
 158         /* Activate double buffered register update */
 159         I915_MODIFY_DISPBASE(SPRSURF(pipe), 0);
 160         POSTING_READ(SPRSURF(pipe));
 161
 162         dev_priv->sprite_scaling_enabled = false;
 163         intel_update_watermarks(dev);
 164 }
 165
 166 static int
 167 ivb_update_colorkey(struct drm_plane *plane,
 168                     struct drm_intel_sprite_colorkey *key)
 169 {
 170         struct drm_device *dev = plane->dev;
 171         struct drm_i915_private *dev_priv = dev->dev_private;
 172         struct intel_plane *intel_plane;
 173         u32 sprctl;
 174         int ret = 0;
 175
 176         intel_plane = to_intel_plane(plane);
 177
 178         I915_WRITE(SPRKEYVAL(intel_plane->pipe), key->min_value);
 179         I915_WRITE(SPRKEYMAX(intel_plane->pipe), key->max_value);
 180         I915_WRITE(SPRKEYMSK(intel_plane->pipe), key->channel_mask);
 181
 182         sprctl = I915_READ(SPRCTL(intel_plane->pipe));
 183         sprctl &= ~(SPRITE_SOURCE_KEY | SPRITE_DEST_KEY);
 184         if (key->flags & I915_SET_COLORKEY_DESTINATION)
 185                 sprctl |= SPRITE_DEST_KEY;
 186         else if (key->flags & I915_SET_COLORKEY_SOURCE)
 187                 sprctl |= SPRITE_SOURCE_KEY;
 188         I915_WRITE(SPRCTL(intel_plane->pipe), sprctl);
 189
 190         POSTING_READ(SPRKEYMSK(intel_plane->pipe));
 191
 192         return ret;
 193 }
 194
 195 static void
 196 ivb_get_colorkey(struct drm_plane *plane, struct drm_intel_sprite_colorkey *key)
 197 {
 198         struct drm_device *dev = plane->dev;
 199         struct drm_i915_private *dev_priv = dev->dev_private;
 200         struct intel_plane *intel_plane;
 201         u32 sprctl;
 202
 203         intel_plane = to_intel_plane(plane);
 204
 205         key->min_value = I915_READ(SPRKEYVAL(intel_plane->pipe));
 206         key->max_value = I915_READ(SPRKEYMAX(intel_plane->pipe));
 207         key->channel_mask = I915_READ(SPRKEYMSK(intel_plane->pipe));
 208         key->flags = 0;
 209
 210         sprctl = I915_READ(SPRCTL(intel_plane->pipe));
 211
 212         if (sprctl & SPRITE_DEST_KEY)
 213                 key->flags = I915_SET_COLORKEY_DESTINATION;
 214         else if (sprctl & SPRITE_SOURCE_KEY)
 215                 key->flags = I915_SET_COLORKEY_SOURCE;
 216         else
 217                 key->flags = I915_SET_COLORKEY_NONE;
 218 }
 219
 220 static void
 221 ilk_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb,
 222                  struct drm_i915_gem_object *obj, int crtc_x, int crtc_y,
 223                  unsigned int crtc_w, unsigned int crtc_h,
 224                  uint32_t x, uint32_t y,
 225                  uint32_t src_w, uint32_t src_h)
 226 {
 227         struct drm_device *dev = plane->dev;
 228         struct drm_i915_private *dev_priv = dev->dev_private;
 229         struct intel_plane *intel_plane = to_intel_plane(plane);
 230         int pipe = intel_plane->pipe, pixel_size;
 231         u32 dvscntr, dvsscale;
 232
 233         dvscntr = I915_READ(DVSCNTR(pipe));
 234
 235         /* Mask out pixel format bits in case we change it */
 236         dvscntr &= ~DVS_PIXFORMAT_MASK;
 237         dvscntr &= ~DVS_RGB_ORDER_XBGR;
 238         dvscntr &= ~DVS_YUV_BYTE_ORDER_MASK;
 239         dvscntr &= ~DVS_TILED;
 240
 241         switch (fb->pixel_format) {
 242         case DRM_FORMAT_XBGR8888:
 243                 dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR;
 244                 pixel_size = 4;
 245                 break;
 246         case DRM_FORMAT_XRGB8888:
 247                 dvscntr |= DVS_FORMAT_RGBX888;
 248                 pixel_size = 4;
 249                 break;
 250         case DRM_FORMAT_YUYV:
 251                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV;
 252                 pixel_size = 2;
 253                 break;
 254         case DRM_FORMAT_YVYU:
 255                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU;
 256                 pixel_size = 2;
 257                 break;
 258         case DRM_FORMAT_UYVY:
 259                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY;
 260                 pixel_size = 2;
 261                 break;
 262         case DRM_FORMAT_VYUY:
 263                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY;
 264                 pixel_size = 2;
 265                 break;
 266         default:
 267                 DRM_DEBUG_DRIVER("bad pixel format, assuming RGBX888\n");
 268                 dvscntr |= DVS_FORMAT_RGBX888;
 269                 pixel_size = 4;
 270                 break;
 271         }
 272
 273         if (obj->tiling_mode != I915_TILING_NONE)
 274                 dvscntr |= DVS_TILED;
 275
 276         if (IS_GEN6(dev))
 277                 dvscntr |= DVS_TRICKLE_FEED_DISABLE; /* must disable */
 278         dvscntr |= DVS_ENABLE;
 279
 280         /* Sizes are 0 based */
 281         src_w--;
 282         src_h--;
 283         crtc_w--;
 284         crtc_h--;
 285
 286         intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size);
 287
 288         dvsscale = 0;
 289         if (IS_GEN5(dev) || crtc_w != src_w || crtc_h != src_h)
 290                 dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
 291
 292         I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]);
 293         I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x);
 294         if (obj->tiling_mode != I915_TILING_NONE) {
 295                 I915_WRITE(DVSTILEOFF(pipe), (y << 16) | x);
 296         } else {
 297                 unsigned long offset;
 298
 299                 offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
 300                 I915_WRITE(DVSLINOFF(pipe), offset);
 301         }
 302         I915_WRITE(DVSSIZE(pipe), (crtc_h << 16) | crtc_w);
 303         I915_WRITE(DVSSCALE(pipe), dvsscale);
 304         I915_WRITE(DVSCNTR(pipe), dvscntr);
 305         I915_MODIFY_DISPBASE(DVSSURF(pipe), obj->gtt_offset);
 306         POSTING_READ(DVSSURF(pipe));
 307 }
 308
 309 static void
 310 ilk_disable_plane(struct drm_plane *plane)
 311 {
 312         struct drm_device *dev = plane->dev;
 313         struct drm_i915_private *dev_priv = dev->dev_private;
 314         struct intel_plane *intel_plane = to_intel_plane(plane);
 315         int pipe = intel_plane->pipe;
 316
 317         I915_WRITE(DVSCNTR(pipe), I915_READ(DVSCNTR(pipe)) & ~DVS_ENABLE);
 318         /* Disable the scaler */
 319         I915_WRITE(DVSSCALE(pipe), 0);
 320         /* Flush double buffered register updates */
 321         I915_MODIFY_DISPBASE(DVSSURF(pipe), 0);
 322         POSTING_READ(DVSSURF(pipe));
 323 }
 324
 325 static void
 326 intel_enable_primary(struct drm_crtc *crtc)
 327 {
 328         struct drm_device *dev = crtc->dev;
 329         struct drm_i915_private *dev_priv = dev->dev_private;
 330         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 331         int reg = DSPCNTR(intel_crtc->plane);
 332
 333         if (!intel_crtc->primary_disabled)
 334                 return;
 335
 336         intel_crtc->primary_disabled = false;
 337         intel_update_fbc(dev);
 338
 339         I915_WRITE(reg, I915_READ(reg) | DISPLAY_PLANE_ENABLE);
 340 }
 341
 342 static void
 343 intel_disable_primary(struct drm_crtc *crtc)
 344 {
 345         struct drm_device *dev = crtc->dev;
 346         struct drm_i915_private *dev_priv = dev->dev_private;
 347         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 348         int reg = DSPCNTR(intel_crtc->plane);
 349
 350         if (intel_crtc->primary_disabled)
 351                 return;
 352
 353         I915_WRITE(reg, I915_READ(reg) & ~DISPLAY_PLANE_ENABLE);
 354
 355         intel_crtc->primary_disabled = true;
 356         intel_update_fbc(dev);
 357 }
 358
 359 static int
 360 ilk_update_colorkey(struct drm_plane *plane,
 361                     struct drm_intel_sprite_colorkey *key)
 362 {
 363         struct drm_device *dev = plane->dev;
 364         struct drm_i915_private *dev_priv = dev->dev_private;
 365         struct intel_plane *intel_plane;
 366         u32 dvscntr;
 367         int ret = 0;
 368
 369         intel_plane = to_intel_plane(plane);
 370
 371         I915_WRITE(DVSKEYVAL(intel_plane->pipe), key->min_value);
 372         I915_WRITE(DVSKEYMAX(intel_plane->pipe), key->max_value);
 373         I915_WRITE(DVSKEYMSK(intel_plane->pipe), key->channel_mask);
 374
 375         dvscntr = I915_READ(DVSCNTR(intel_plane->pipe));
 376         dvscntr &= ~(DVS_SOURCE_KEY | DVS_DEST_KEY);
 377         if (key->flags & I915_SET_COLORKEY_DESTINATION)
 378                 dvscntr |= DVS_DEST_KEY;
 379         else if (key->flags & I915_SET_COLORKEY_SOURCE)
 380                 dvscntr |= DVS_SOURCE_KEY;
 381         I915_WRITE(DVSCNTR(intel_plane->pipe), dvscntr);
 382
 383         POSTING_READ(DVSKEYMSK(intel_plane->pipe));
 384
 385         return ret;
 386 }
 387
 388 static void
 389 ilk_get_colorkey(struct drm_plane *plane, struct drm_intel_sprite_colorkey *key)
 390 {
 391         struct drm_device *dev = plane->dev;
 392         struct drm_i915_private *dev_priv = dev->dev_private;
 393         struct intel_plane *intel_plane;
 394         u32 dvscntr;
 395
 396         intel_plane = to_intel_plane(plane);
 397
 398         key->min_value = I915_READ(DVSKEYVAL(intel_plane->pipe));
 399         key->max_value = I915_READ(DVSKEYMAX(intel_plane->pipe));
 400         key->channel_mask = I915_READ(DVSKEYMSK(intel_plane->pipe));
 401         key->flags = 0;
 402
 403         dvscntr = I915_READ(DVSCNTR(intel_plane->pipe));
 404
 405         if (dvscntr & DVS_DEST_KEY)
 406                 key->flags = I915_SET_COLORKEY_DESTINATION;
 407         else if (dvscntr & DVS_SOURCE_KEY)
 408                 key->flags = I915_SET_COLORKEY_SOURCE;
 409         else
 410                 key->flags = I915_SET_COLORKEY_NONE;
 411 }
 412
 413 static int
 414 intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
 415                    struct drm_framebuffer *fb, int crtc_x, int crtc_y,
 416                    unsigned int crtc_w, unsigned int crtc_h,
 417                    uint32_t src_x, uint32_t src_y,
 418                    uint32_t src_w, uint32_t src_h)
 419 {
 420         struct drm_device *dev = plane->dev;
 421         struct drm_i915_private *dev_priv = dev->dev_private;
 422         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 423         struct intel_plane *intel_plane = to_intel_plane(plane);
 424         struct intel_framebuffer *intel_fb;
 425         struct drm_i915_gem_object *obj, *old_obj;
 426         int pipe = intel_plane->pipe;
 427         int ret = 0;
 428         int x = src_x >> 16, y = src_y >> 16;
 429         int primary_w = crtc->mode.hdisplay, primary_h = crtc->mode.vdisplay;
 430         bool disable_primary = false;
 431
 432         intel_fb = to_intel_framebuffer(fb);
 433         obj = intel_fb->obj;
 434
 435         old_obj = intel_plane->obj;
 436
 437         src_w = src_w >> 16;
 438         src_h = src_h >> 16;
 439
 440         /* Pipe must be running... */
 441         if (!(I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE))
 442                 return -EINVAL;
 443
 444         if (crtc_x >= primary_w || crtc_y >= primary_h)
 445                 return -EINVAL;
 446
 447         /* Don't modify another pipe's plane */
 448         if (intel_plane->pipe != intel_crtc->pipe)
 449                 return -EINVAL;
 450
 451         /*
 452          * Clamp the width & height into the visible area.  Note we don't
 453          * try to scale the source if part of the visible region is offscreen.
 454          * The caller must handle that by adjusting source offset and size.
 455          */
 456         if ((crtc_x < 0) && ((crtc_x + crtc_w) > 0)) {
 457                 crtc_w += crtc_x;
 458                 crtc_x = 0;
 459         }
 460         if ((crtc_x + crtc_w) <= 0) /* Nothing to display */
 461                 goto out;
 462         if ((crtc_x + crtc_w) > primary_w)
 463                 crtc_w = primary_w - crtc_x;
 464
 465         if ((crtc_y < 0) && ((crtc_y + crtc_h) > 0)) {
 466                 crtc_h += crtc_y;
 467                 crtc_y = 0;
 468         }
 469         if ((crtc_y + crtc_h) <= 0) /* Nothing to display */
 470                 goto out;
 471         if (crtc_y + crtc_h > primary_h)
 472                 crtc_h = primary_h - crtc_y;
 473
 474         if (!crtc_w || !crtc_h) /* Again, nothing to display */
 475                 goto out;
 476
 477         /*
 478          * We may not have a scaler, eg. HSW does not have it any more
 479          */
 480         if (!intel_plane->can_scale && (crtc_w != src_w || crtc_h != src_h))
 481                 return -EINVAL;
 482
 483         /*
 484          * We can take a larger source and scale it down, but
 485          * only so much...  16x is the max on SNB.
 486          */
 487         if (((src_w * src_h) / (crtc_w * crtc_h)) > intel_plane->max_downscale)
 488                 return -EINVAL;
 489
 490         /*
 491          * If the sprite is completely covering the primary plane,
 492          * we can disable the primary and save power.
 493          */
 494         if ((crtc_x == 0) && (crtc_y == 0) &&
 495             (crtc_w == primary_w) && (crtc_h == primary_h))
 496                 disable_primary = true;
 497
 498         mutex_lock(&dev->struct_mutex);
 499
 500         ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
 501         if (ret)
 502                 goto out_unlock;
 503
 504         intel_plane->obj = obj;
 505
 506         /*
 507          * Be sure to re-enable the primary before the sprite is no longer
 508          * covering it fully.
 509          */
 510         if (!disable_primary)
 511                 intel_enable_primary(crtc);
 512
 513         intel_plane->update_plane(plane, fb, obj, crtc_x, crtc_y,
 514                                   crtc_w, crtc_h, x, y, src_w, src_h);
 515
 516         if (disable_primary)
 517                 intel_disable_primary(crtc);
 518
 519         /* Unpin old obj after new one is active to avoid ugliness */
 520         if (old_obj) {
 521                 /*
 522                  * It's fairly common to simply update the position of
 523                  * an existing object.  In that case, we don't need to
 524                  * wait for vblank to avoid ugliness, we only need to
 525                  * do the pin & ref bookkeeping.
 526                  */
 527                 if (old_obj != obj) {
 528                         mutex_unlock(&dev->struct_mutex);
 529                         intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
 530                         mutex_lock(&dev->struct_mutex);
 531                 }
 532                 intel_unpin_fb_obj(old_obj);
 533         }
 534
 535 out_unlock:
 536         mutex_unlock(&dev->struct_mutex);
 537 out:
 538         return ret;
 539 }
 540
 541 static int
 542 intel_disable_plane(struct drm_plane *plane)
 543 {
 544         struct drm_device *dev = plane->dev;
 545         struct intel_plane *intel_plane = to_intel_plane(plane);
 546         int ret = 0;
 547
 548         if (plane->crtc)
 549                 intel_enable_primary(plane->crtc);
 550         intel_plane->disable_plane(plane);
 551
 552         if (!intel_plane->obj)
 553                 goto out;
 554
 555         mutex_lock(&dev->struct_mutex);
 556         intel_unpin_fb_obj(intel_plane->obj);
 557         intel_plane->obj = NULL;
 558         mutex_unlock(&dev->struct_mutex);
 559 out:
 560
 561         return ret;
 562 }
 563
 564 static void intel_destroy_plane(struct drm_plane *plane)
 565 {
 566         struct intel_plane *intel_plane = to_intel_plane(plane);
 567         intel_disable_plane(plane);
 568         drm_plane_cleanup(plane);
 569         kfree(intel_plane);
 570 }
 571
 572 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
 573                               struct drm_file *file_priv)
 574 {
 575         struct drm_intel_sprite_colorkey *set = data;
 576         struct drm_mode_object *obj;
 577         struct drm_plane *plane;
 578         struct intel_plane *intel_plane;
 579         int ret = 0;
 580
 581         if (!drm_core_check_feature(dev, DRIVER_MODESET))
 582                 return -ENODEV;
 583
 584         /* Make sure we don't try to enable both src & dest simultaneously */
 585         if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
 586                 return -EINVAL;
 587
 588         mutex_lock(&dev->mode_config.mutex);
 589
 590         obj = drm_mode_object_find(dev, set->plane_id, DRM_MODE_OBJECT_PLANE);
 591         if (!obj) {
 592                 ret = -EINVAL;
 593                 goto out_unlock;
 594         }
 595
 596         plane = obj_to_plane(obj);
 597         intel_plane = to_intel_plane(plane);
 598         ret = intel_plane->update_colorkey(plane, set);
 599
 600 out_unlock:
 601         mutex_unlock(&dev->mode_config.mutex);
 602         return ret;
 603 }
 604
 605 int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
 606                               struct drm_file *file_priv)
 607 {
 608         struct drm_intel_sprite_colorkey *get = data;
 609         struct drm_mode_object *obj;
 610         struct drm_plane *plane;
 611         struct intel_plane *intel_plane;
 612         int ret = 0;
 613
 614         if (!drm_core_check_feature(dev, DRIVER_MODESET))
 615                 return -ENODEV;
 616
 617         mutex_lock(&dev->mode_config.mutex);
 618
 619         obj = drm_mode_object_find(dev, get->plane_id, DRM_MODE_OBJECT_PLANE);
 620         if (!obj) {
 621                 ret = -EINVAL;
 622                 goto out_unlock;
 623         }
 624
 625         plane = obj_to_plane(obj);
 626         intel_plane = to_intel_plane(plane);
 627         intel_plane->get_colorkey(plane, get);
 628
 629 out_unlock:
 630         mutex_unlock(&dev->mode_config.mutex);
 631         return ret;
 632 }
 633
 634 static const struct drm_plane_funcs intel_plane_funcs = {
 635         .update_plane = intel_update_plane,
 636         .disable_plane = intel_disable_plane,
 637         .destroy = intel_destroy_plane,
 638 };
 639
 640 static uint32_t ilk_plane_formats[] = {
 641         DRM_FORMAT_XRGB8888,
 642         DRM_FORMAT_YUYV,
 643         DRM_FORMAT_YVYU,
 644         DRM_FORMAT_UYVY,
 645         DRM_FORMAT_VYUY,
 646 };
 647
 648 static uint32_t snb_plane_formats[] = {
 649         DRM_FORMAT_XBGR8888,
 650         DRM_FORMAT_XRGB8888,
 651         DRM_FORMAT_YUYV,
 652         DRM_FORMAT_YVYU,
 653         DRM_FORMAT_UYVY,
 654         DRM_FORMAT_VYUY,
 655 };
 656
 657 int
 658 intel_plane_init(struct drm_device *dev, enum pipe pipe)
 659 {
 660         struct intel_plane *intel_plane;
 661         unsigned long possible_crtcs;
 662         const uint32_t *plane_formats;
 663         int num_plane_formats;
 664         int ret;
 665
 666         if (INTEL_INFO(dev)->gen < 5)
 667                 return -ENODEV;
 668
 669         intel_plane = kzalloc(sizeof(struct intel_plane), GFP_KERNEL);
 670         if (!intel_plane)
 671                 return -ENOMEM;
 672
 673         switch (INTEL_INFO(dev)->gen) {
 674         case 5:
 675         case 6:
 676                 intel_plane->can_scale = true;
 677                 intel_plane->max_downscale = 16;
 678                 intel_plane->update_plane = ilk_update_plane;
 679                 intel_plane->disable_plane = ilk_disable_plane;
 680                 intel_plane->update_colorkey = ilk_update_colorkey;
 681                 intel_plane->get_colorkey = ilk_get_colorkey;
 682
 683                 if (IS_GEN6(dev)) {
 684                         plane_formats = snb_plane_formats;
 685                         num_plane_formats = ARRAY_SIZE(snb_plane_formats);
 686                 } else {
 687                         plane_formats = ilk_plane_formats;
 688                         num_plane_formats = ARRAY_SIZE(ilk_plane_formats);
 689                 }
 690                 break;
 691
 692         case 7:
 693                 if (IS_HASWELL(dev))
 694                         intel_plane->can_scale = false;
 695                 else
 696                         intel_plane->can_scale = true;
 697                 intel_plane->max_downscale = 2;
 698                 intel_plane->update_plane = ivb_update_plane;
 699                 intel_plane->disable_plane = ivb_disable_plane;
 700                 intel_plane->update_colorkey = ivb_update_colorkey;
 701                 intel_plane->get_colorkey = ivb_get_colorkey;
 702
 703                 plane_formats = snb_plane_formats;
 704                 num_plane_formats = ARRAY_SIZE(snb_plane_formats);
 705                 break;
 706
 707         default:
 708                 kfree(intel_plane);
 709                 return -ENODEV;
 710         }
 711
 712         intel_plane->pipe = pipe;
 713         possible_crtcs = (1 << pipe);
 714         ret = drm_plane_init(dev, &intel_plane->base, possible_crtcs,
 715                              &intel_plane_funcs,
 716                              plane_formats, num_plane_formats,
 717                              false);
 718         if (ret)
 719                 kfree(intel_plane);
 720
 721         return ret;
 722 }