drivers/gpu/drm/i915/intel_sprite.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *   Jesse Barnes <jbarnes@virtuousgeek.org>
  25  *
  26  * New plane/sprite handling.
  27  *
  28  * The older chips had a separate interface for programming plane related
  29  * registers; newer ones are much simpler and we can use the new DRM plane
  30  * support.
  31  */
  32 #include <drm/drmP.h>
  33 #include <drm/drm_crtc.h>
  34 #include <drm/drm_fourcc.h>
  35 #include <drm/drm_rect.h>
  36 #include <drm/drm_atomic.h>
  37 #include <drm/drm_plane_helper.h>
  38 #include "intel_drv.h"
  39 #include "intel_frontbuffer.h"
  40 #include <drm/i915_drm.h>
  41 #include "i915_drv.h"
  42
  43 static bool
  44 format_is_yuv(uint32_t format)
  45 {
  46         switch (format) {
  47         case DRM_FORMAT_YUYV:
  48         case DRM_FORMAT_UYVY:
  49         case DRM_FORMAT_VYUY:
  50         case DRM_FORMAT_YVYU:
  51                 return true;
  52         default:
  53                 return false;
  54         }
  55 }
  56
  57 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
  58                              int usecs)
  59 {
  60         /* paranoia */
  61         if (!adjusted_mode->crtc_htotal)
  62                 return 1;
  63
  64         return DIV_ROUND_UP(usecs * adjusted_mode->crtc_clock,
  65                             1000 * adjusted_mode->crtc_htotal);
  66 }
  67
  68 /**
  69  * intel_pipe_update_start() - start update of a set of display registers
  70  * @crtc: the crtc of which the registers are going to be updated
  71  * @start_vbl_count: vblank counter return pointer used for error checking
  72  *
  73  * Mark the start of an update to pipe registers that should be updated
  74  * atomically regarding vblank. If the next vblank will happens within
  75  * the next 100 us, this function waits until the vblank passes.
  76  *
  77  * After a successful call to this function, interrupts will be disabled
  78  * until a subsequent call to intel_pipe_update_end(). That is done to
  79  * avoid random delays. The value written to @start_vbl_count should be
  80  * supplied to intel_pipe_update_end() for error checking.
  81  */
  82 void intel_pipe_update_start(struct intel_crtc *crtc)
  83 {
  84         const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
  85         long timeout = msecs_to_jiffies_timeout(1);
  86         int scanline, min, max, vblank_start;
  87         wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);
  88         DEFINE_WAIT(wait);
  89
  90         vblank_start = adjusted_mode->crtc_vblank_start;
  91         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
  92                 vblank_start = DIV_ROUND_UP(vblank_start, 2);
  93
  94         /* FIXME needs to be calibrated sensibly */
  95         min = vblank_start - intel_usecs_to_scanlines(adjusted_mode, 100);
  96         max = vblank_start - 1;
  97
  98         local_irq_disable();
  99
 100         if (min <= 0 || max <= 0)
 101                 return;
 102
 103         if (WARN_ON(drm_crtc_vblank_get(&crtc->base)))
 104                 return;
 105
 106         crtc->debug.min_vbl = min;
 107         crtc->debug.max_vbl = max;
 108         trace_i915_pipe_update_start(crtc);
 109
 110         for (;;) {
 111                 /*
 112                  * prepare_to_wait() has a memory barrier, which guarantees
 113                  * other CPUs can see the task state update by the time we
 114                  * read the scanline.
 115                  */
 116                 prepare_to_wait(wq, &wait, TASK_UNINTERRUPTIBLE);
 117
 118                 scanline = intel_get_crtc_scanline(crtc);
 119                 if (scanline < min || scanline > max)
 120                         break;
 121
 122                 if (timeout <= 0) {
 123                         DRM_ERROR("Potential atomic update failure on pipe %c\n",
 124                                   pipe_name(crtc->pipe));
 125                         break;
 126                 }
 127
 128                 local_irq_enable();
 129
 130                 timeout = schedule_timeout(timeout);
 131
 132                 local_irq_disable();
 133         }
 134
 135         finish_wait(wq, &wait);
 136
 137         drm_crtc_vblank_put(&crtc->base);
 138
 139         crtc->debug.scanline_start = scanline;
 140         crtc->debug.start_vbl_time = ktime_get();
 141         crtc->debug.start_vbl_count = intel_crtc_get_vblank_counter(crtc);
 142
 143         trace_i915_pipe_update_vblank_evaded(crtc);
 144 }
 145
 146 /**
 147  * intel_pipe_update_end() - end update of a set of display registers
 148  * @crtc: the crtc of which the registers were updated
 149  * @start_vbl_count: start vblank counter (used for error checking)
 150  *
 151  * Mark the end of an update started with intel_pipe_update_start(). This
 152  * re-enables interrupts and verifies the update was actually completed
 153  * before a vblank using the value of @start_vbl_count.
 154  */
 155 void intel_pipe_update_end(struct intel_crtc *crtc, struct intel_flip_work *work)
 156 {
 157         enum pipe pipe = crtc->pipe;
 158         int scanline_end = intel_get_crtc_scanline(crtc);
 159         u32 end_vbl_count = intel_crtc_get_vblank_counter(crtc);
 160         ktime_t end_vbl_time = ktime_get();
 161
 162         if (work) {
 163                 work->flip_queued_vblank = end_vbl_count;
 164                 smp_mb__before_atomic();
 165                 atomic_set(&work->pending, 1);
 166         }
 167
 168         trace_i915_pipe_update_end(crtc, end_vbl_count, scanline_end);
 169
 170         /* We're still in the vblank-evade critical section, this can't race.
 171          * Would be slightly nice to just grab the vblank count and arm the
 172          * event outside of the critical section - the spinlock might spin for a
 173          * while ... */
 174         if (crtc->base.state->event) {
 175                 WARN_ON(drm_crtc_vblank_get(&crtc->base) != 0);
 176
 177                 spin_lock(&crtc->base.dev->event_lock);
 178                 drm_crtc_arm_vblank_event(&crtc->base, crtc->base.state->event);
 179                 spin_unlock(&crtc->base.dev->event_lock);
 180
 181                 crtc->base.state->event = NULL;
 182         }
 183
 184         local_irq_enable();
 185
 186         if (crtc->debug.start_vbl_count &&
 187             crtc->debug.start_vbl_count != end_vbl_count) {
 188                 DRM_ERROR("Atomic update failure on pipe %c (start=%u end=%u) time %lld us, min %d, max %d, scanline start %d, end %d\n",
 189                           pipe_name(pipe), crtc->debug.start_vbl_count,
 190                           end_vbl_count,
 191                           ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time),
 192                           crtc->debug.min_vbl, crtc->debug.max_vbl,
 193                           crtc->debug.scanline_start, scanline_end);
 194         }
 195 }
 196
 197 static void
 198 skl_update_plane(struct drm_plane *drm_plane,
 199                  const struct intel_crtc_state *crtc_state,
 200                  const struct intel_plane_state *plane_state)
 201 {
 202         struct drm_device *dev = drm_plane->dev;
 203         struct drm_i915_private *dev_priv = to_i915(dev);
 204         struct intel_plane *intel_plane = to_intel_plane(drm_plane);
 205         struct drm_framebuffer *fb = plane_state->base.fb;
 206         const struct skl_wm_values *wm = &dev_priv->wm.skl_results;
 207         struct drm_crtc *crtc = crtc_state->base.crtc;
 208         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 209         const int pipe = intel_plane->pipe;
 210         const int plane = intel_plane->plane + 1;
 211         u32 plane_ctl;
 212         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 213         u32 surf_addr = plane_state->main.offset;
 214         unsigned int rotation = plane_state->base.rotation;
 215         u32 stride = skl_plane_stride(fb, 0, rotation);
 216         int crtc_x = plane_state->base.dst.x1;
 217         int crtc_y = plane_state->base.dst.y1;
 218         uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
 219         uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
 220         uint32_t x = plane_state->main.x;
 221         uint32_t y = plane_state->main.y;
 222         uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
 223         uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
 224
 225         plane_ctl = PLANE_CTL_ENABLE |
 226                 PLANE_CTL_PIPE_GAMMA_ENABLE |
 227                 PLANE_CTL_PIPE_CSC_ENABLE;
 228
 229         plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
 230         plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
 231
 232         plane_ctl |= skl_plane_ctl_rotation(rotation);
 233
 234         if (wm->dirty_pipes & drm_crtc_mask(crtc))
 235                 skl_write_plane_wm(intel_crtc, wm, plane);
 236
 237         if (key->flags) {
 238                 I915_WRITE(PLANE_KEYVAL(pipe, plane), key->min_value);
 239                 I915_WRITE(PLANE_KEYMAX(pipe, plane), key->max_value);
 240                 I915_WRITE(PLANE_KEYMSK(pipe, plane), key->channel_mask);
 241         }
 242
 243         if (key->flags & I915_SET_COLORKEY_DESTINATION)
 244                 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
 245         else if (key->flags & I915_SET_COLORKEY_SOURCE)
 246                 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
 247
 248         /* Sizes are 0 based */
 249         src_w--;
 250         src_h--;
 251         crtc_w--;
 252         crtc_h--;
 253
 254         I915_WRITE(PLANE_OFFSET(pipe, plane), (y << 16) | x);
 255         I915_WRITE(PLANE_STRIDE(pipe, plane), stride);
 256         I915_WRITE(PLANE_SIZE(pipe, plane), (src_h << 16) | src_w);
 257
 258         /* program plane scaler */
 259         if (plane_state->scaler_id >= 0) {
 260                 int scaler_id = plane_state->scaler_id;
 261                 const struct intel_scaler *scaler;
 262
 263                 DRM_DEBUG_KMS("plane = %d PS_PLANE_SEL(plane) = 0x%x\n", plane,
 264                         PS_PLANE_SEL(plane));
 265
 266                 scaler = &crtc_state->scaler_state.scalers[scaler_id];
 267
 268                 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id),
 269                            PS_SCALER_EN | PS_PLANE_SEL(plane) | scaler->mode);
 270                 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
 271                 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (crtc_x << 16) | crtc_y);
 272                 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id),
 273                         ((crtc_w + 1) << 16)|(crtc_h + 1));
 274
 275                 I915_WRITE(PLANE_POS(pipe, plane), 0);
 276         } else {
 277                 I915_WRITE(PLANE_POS(pipe, plane), (crtc_y << 16) | crtc_x);
 278         }
 279
 280         I915_WRITE(PLANE_CTL(pipe, plane), plane_ctl);
 281         I915_WRITE(PLANE_SURF(pipe, plane),
 282                    intel_fb_gtt_offset(fb, rotation) + surf_addr);
 283         POSTING_READ(PLANE_SURF(pipe, plane));
 284 }
 285
 286 static void
 287 skl_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc)
 288 {
 289         struct drm_device *dev = dplane->dev;
 290         struct drm_i915_private *dev_priv = to_i915(dev);
 291         struct intel_plane *intel_plane = to_intel_plane(dplane);
 292         const int pipe = intel_plane->pipe;
 293         const int plane = intel_plane->plane + 1;
 294
 295         /*
 296          * We only populate skl_results on watermark updates, and if the
 297          * plane's visiblity isn't actually changing neither is its watermarks.
 298          */
 299         if (!dplane->state->visible)
 300                 skl_write_plane_wm(to_intel_crtc(crtc),
 301                                    &dev_priv->wm.skl_results, plane);
 302
 303         I915_WRITE(PLANE_CTL(pipe, plane), 0);
 304
 305         I915_WRITE(PLANE_SURF(pipe, plane), 0);
 306         POSTING_READ(PLANE_SURF(pipe, plane));
 307 }
 308
 309 static void
 310 chv_update_csc(struct intel_plane *intel_plane, uint32_t format)
 311 {
 312         struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
 313         int plane = intel_plane->plane;
 314
 315         /* Seems RGB data bypasses the CSC always */
 316         if (!format_is_yuv(format))
 317                 return;
 318
 319         /*
 320          * BT.601 limited range YCbCr -> full range RGB
 321          *
 322          * |r|   | 6537 4769     0|   |cr  |
 323          * |g| = |-3330 4769 -1605| x |y-64|
 324          * |b|   |    0 4769  8263|   |cb  |
 325          *
 326          * Cb and Cr apparently come in as signed already, so no
 327          * need for any offset. For Y we need to remove the offset.
 328          */
 329         I915_WRITE(SPCSCYGOFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(-64));
 330         I915_WRITE(SPCSCCBOFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(0));
 331         I915_WRITE(SPCSCCROFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(0));
 332
 333         I915_WRITE(SPCSCC01(plane), SPCSC_C1(4769) | SPCSC_C0(6537));
 334         I915_WRITE(SPCSCC23(plane), SPCSC_C1(-3330) | SPCSC_C0(0));
 335         I915_WRITE(SPCSCC45(plane), SPCSC_C1(-1605) | SPCSC_C0(4769));
 336         I915_WRITE(SPCSCC67(plane), SPCSC_C1(4769) | SPCSC_C0(0));
 337         I915_WRITE(SPCSCC8(plane), SPCSC_C0(8263));
 338
 339         I915_WRITE(SPCSCYGICLAMP(plane), SPCSC_IMAX(940) | SPCSC_IMIN(64));
 340         I915_WRITE(SPCSCCBICLAMP(plane), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
 341         I915_WRITE(SPCSCCRICLAMP(plane), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
 342
 343         I915_WRITE(SPCSCYGOCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
 344         I915_WRITE(SPCSCCBOCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
 345         I915_WRITE(SPCSCCROCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
 346 }
 347
 348 static void
 349 vlv_update_plane(struct drm_plane *dplane,
 350                  const struct intel_crtc_state *crtc_state,
 351                  const struct intel_plane_state *plane_state)
 352 {
 353         struct drm_device *dev = dplane->dev;
 354         struct drm_i915_private *dev_priv = to_i915(dev);
 355         struct intel_plane *intel_plane = to_intel_plane(dplane);
 356         struct drm_framebuffer *fb = plane_state->base.fb;
 357         int pipe = intel_plane->pipe;
 358         int plane = intel_plane->plane;
 359         u32 sprctl;
 360         u32 sprsurf_offset, linear_offset;
 361         unsigned int rotation = dplane->state->rotation;
 362         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 363         int crtc_x = plane_state->base.dst.x1;
 364         int crtc_y = plane_state->base.dst.y1;
 365         uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
 366         uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
 367         uint32_t x = plane_state->base.src.x1 >> 16;
 368         uint32_t y = plane_state->base.src.y1 >> 16;
 369         uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
 370         uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
 371
 372         sprctl = SP_ENABLE;
 373
 374         switch (fb->pixel_format) {
 375         case DRM_FORMAT_YUYV:
 376                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YUYV;
 377                 break;
 378         case DRM_FORMAT_YVYU:
 379                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YVYU;
 380                 break;
 381         case DRM_FORMAT_UYVY:
 382                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_UYVY;
 383                 break;
 384         case DRM_FORMAT_VYUY:
 385                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY;
 386                 break;
 387         case DRM_FORMAT_RGB565:
 388                 sprctl |= SP_FORMAT_BGR565;
 389                 break;
 390         case DRM_FORMAT_XRGB8888:
 391                 sprctl |= SP_FORMAT_BGRX8888;
 392                 break;
 393         case DRM_FORMAT_ARGB8888:
 394                 sprctl |= SP_FORMAT_BGRA8888;
 395                 break;
 396         case DRM_FORMAT_XBGR2101010:
 397                 sprctl |= SP_FORMAT_RGBX1010102;
 398                 break;
 399         case DRM_FORMAT_ABGR2101010:
 400                 sprctl |= SP_FORMAT_RGBA1010102;
 401                 break;
 402         case DRM_FORMAT_XBGR8888:
 403                 sprctl |= SP_FORMAT_RGBX8888;
 404                 break;
 405         case DRM_FORMAT_ABGR8888:
 406                 sprctl |= SP_FORMAT_RGBA8888;
 407                 break;
 408         default:
 409                 /*
 410                  * If we get here one of the upper layers failed to filter
 411                  * out the unsupported plane formats
 412                  */
 413                 BUG();
 414                 break;
 415         }
 416
 417         /*
 418          * Enable gamma to match primary/cursor plane behaviour.
 419          * FIXME should be user controllable via propertiesa.
 420          */
 421         sprctl |= SP_GAMMA_ENABLE;
 422
 423         if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
 424                 sprctl |= SP_TILED;
 425
 426         /* Sizes are 0 based */
 427         src_w--;
 428         src_h--;
 429         crtc_w--;
 430         crtc_h--;
 431
 432         intel_add_fb_offsets(&x, &y, plane_state, 0);
 433         sprsurf_offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
 434
 435         if (rotation == DRM_ROTATE_180) {
 436                 sprctl |= SP_ROTATE_180;
 437
 438                 x += src_w;
 439                 y += src_h;
 440         }
 441
 442         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
 443
 444         if (key->flags) {
 445                 I915_WRITE(SPKEYMINVAL(pipe, plane), key->min_value);
 446                 I915_WRITE(SPKEYMAXVAL(pipe, plane), key->max_value);
 447                 I915_WRITE(SPKEYMSK(pipe, plane), key->channel_mask);
 448         }
 449
 450         if (key->flags & I915_SET_COLORKEY_SOURCE)
 451                 sprctl |= SP_SOURCE_KEY;
 452
 453         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B)
 454                 chv_update_csc(intel_plane, fb->pixel_format);
 455
 456         I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]);
 457         I915_WRITE(SPPOS(pipe, plane), (crtc_y << 16) | crtc_x);
 458
 459         if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
 460                 I915_WRITE(SPTILEOFF(pipe, plane), (y << 16) | x);
 461         else
 462                 I915_WRITE(SPLINOFF(pipe, plane), linear_offset);
 463
 464         I915_WRITE(SPCONSTALPHA(pipe, plane), 0);
 465
 466         I915_WRITE(SPSIZE(pipe, plane), (crtc_h << 16) | crtc_w);
 467         I915_WRITE(SPCNTR(pipe, plane), sprctl);
 468         I915_WRITE(SPSURF(pipe, plane),
 469                    intel_fb_gtt_offset(fb, rotation) + sprsurf_offset);
 470         POSTING_READ(SPSURF(pipe, plane));
 471 }
 472
 473 static void
 474 vlv_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc)
 475 {
 476         struct drm_device *dev = dplane->dev;
 477         struct drm_i915_private *dev_priv = to_i915(dev);
 478         struct intel_plane *intel_plane = to_intel_plane(dplane);
 479         int pipe = intel_plane->pipe;
 480         int plane = intel_plane->plane;
 481
 482         I915_WRITE(SPCNTR(pipe, plane), 0);
 483
 484         I915_WRITE(SPSURF(pipe, plane), 0);
 485         POSTING_READ(SPSURF(pipe, plane));
 486 }
 487
 488 static void
 489 ivb_update_plane(struct drm_plane *plane,
 490                  const struct intel_crtc_state *crtc_state,
 491                  const struct intel_plane_state *plane_state)
 492 {
 493         struct drm_device *dev = plane->dev;
 494         struct drm_i915_private *dev_priv = to_i915(dev);
 495         struct intel_plane *intel_plane = to_intel_plane(plane);
 496         struct drm_framebuffer *fb = plane_state->base.fb;
 497         enum pipe pipe = intel_plane->pipe;
 498         u32 sprctl, sprscale = 0;
 499         u32 sprsurf_offset, linear_offset;
 500         unsigned int rotation = plane_state->base.rotation;
 501         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 502         int crtc_x = plane_state->base.dst.x1;
 503         int crtc_y = plane_state->base.dst.y1;
 504         uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
 505         uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
 506         uint32_t x = plane_state->base.src.x1 >> 16;
 507         uint32_t y = plane_state->base.src.y1 >> 16;
 508         uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
 509         uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
 510
 511         sprctl = SPRITE_ENABLE;
 512
 513         switch (fb->pixel_format) {
 514         case DRM_FORMAT_XBGR8888:
 515                 sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;
 516                 break;
 517         case DRM_FORMAT_XRGB8888:
 518                 sprctl |= SPRITE_FORMAT_RGBX888;
 519                 break;
 520         case DRM_FORMAT_YUYV:
 521                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV;
 522                 break;
 523         case DRM_FORMAT_YVYU:
 524                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU;
 525                 break;
 526         case DRM_FORMAT_UYVY:
 527                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY;
 528                 break;
 529         case DRM_FORMAT_VYUY:
 530                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY;
 531                 break;
 532         default:
 533                 BUG();
 534         }
 535
 536         /*
 537          * Enable gamma to match primary/cursor plane behaviour.
 538          * FIXME should be user controllable via propertiesa.
 539          */
 540         sprctl |= SPRITE_GAMMA_ENABLE;
 541
 542         if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
 543                 sprctl |= SPRITE_TILED;
 544
 545         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
 546                 sprctl &= ~SPRITE_TRICKLE_FEED_DISABLE;
 547         else
 548                 sprctl |= SPRITE_TRICKLE_FEED_DISABLE;
 549
 550         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
 551                 sprctl |= SPRITE_PIPE_CSC_ENABLE;
 552
 553         /* Sizes are 0 based */
 554         src_w--;
 555         src_h--;
 556         crtc_w--;
 557         crtc_h--;
 558
 559         if (crtc_w != src_w || crtc_h != src_h)
 560                 sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
 561
 562         intel_add_fb_offsets(&x, &y, plane_state, 0);
 563         sprsurf_offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
 564
 565         if (rotation == DRM_ROTATE_180) {
 566                 sprctl |= SPRITE_ROTATE_180;
 567
 568                 /* HSW and BDW does this automagically in hardware */
 569                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
 570                         x += src_w;
 571                         y += src_h;
 572                 }
 573         }
 574
 575         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
 576
 577         if (key->flags) {
 578                 I915_WRITE(SPRKEYVAL(pipe), key->min_value);
 579                 I915_WRITE(SPRKEYMAX(pipe), key->max_value);
 580                 I915_WRITE(SPRKEYMSK(pipe), key->channel_mask);
 581         }
 582
 583         if (key->flags & I915_SET_COLORKEY_DESTINATION)
 584                 sprctl |= SPRITE_DEST_KEY;
 585         else if (key->flags & I915_SET_COLORKEY_SOURCE)
 586                 sprctl |= SPRITE_SOURCE_KEY;
 587
 588         I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]);
 589         I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x);
 590
 591         /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
 592          * register */
 593         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
 594                 I915_WRITE(SPROFFSET(pipe), (y << 16) | x);
 595         else if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
 596                 I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x);
 597         else
 598                 I915_WRITE(SPRLINOFF(pipe), linear_offset);
 599
 600         I915_WRITE(SPRSIZE(pipe), (crtc_h << 16) | crtc_w);
 601         if (intel_plane->can_scale)
 602                 I915_WRITE(SPRSCALE(pipe), sprscale);
 603         I915_WRITE(SPRCTL(pipe), sprctl);
 604         I915_WRITE(SPRSURF(pipe),
 605                    intel_fb_gtt_offset(fb, rotation) + sprsurf_offset);
 606         POSTING_READ(SPRSURF(pipe));
 607 }
 608
 609 static void
 610 ivb_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc)
 611 {
 612         struct drm_device *dev = plane->dev;
 613         struct drm_i915_private *dev_priv = to_i915(dev);
 614         struct intel_plane *intel_plane = to_intel_plane(plane);
 615         int pipe = intel_plane->pipe;
 616
 617         I915_WRITE(SPRCTL(pipe), 0);
 618         /* Can't leave the scaler enabled... */
 619         if (intel_plane->can_scale)
 620                 I915_WRITE(SPRSCALE(pipe), 0);
 621
 622         I915_WRITE(SPRSURF(pipe), 0);
 623         POSTING_READ(SPRSURF(pipe));
 624 }
 625
 626 static void
 627 ilk_update_plane(struct drm_plane *plane,
 628                  const struct intel_crtc_state *crtc_state,
 629                  const struct intel_plane_state *plane_state)
 630 {
 631         struct drm_device *dev = plane->dev;
 632         struct drm_i915_private *dev_priv = to_i915(dev);
 633         struct intel_plane *intel_plane = to_intel_plane(plane);
 634         struct drm_framebuffer *fb = plane_state->base.fb;
 635         int pipe = intel_plane->pipe;
 636         u32 dvscntr, dvsscale;
 637         u32 dvssurf_offset, linear_offset;
 638         unsigned int rotation = plane_state->base.rotation;
 639         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 640         int crtc_x = plane_state->base.dst.x1;
 641         int crtc_y = plane_state->base.dst.y1;
 642         uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
 643         uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
 644         uint32_t x = plane_state->base.src.x1 >> 16;
 645         uint32_t y = plane_state->base.src.y1 >> 16;
 646         uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
 647         uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
 648
 649         dvscntr = DVS_ENABLE;
 650
 651         switch (fb->pixel_format) {
 652         case DRM_FORMAT_XBGR8888:
 653                 dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR;
 654                 break;
 655         case DRM_FORMAT_XRGB8888:
 656                 dvscntr |= DVS_FORMAT_RGBX888;
 657                 break;
 658         case DRM_FORMAT_YUYV:
 659                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV;
 660                 break;
 661         case DRM_FORMAT_YVYU:
 662                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU;
 663                 break;
 664         case DRM_FORMAT_UYVY:
 665                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY;
 666                 break;
 667         case DRM_FORMAT_VYUY:
 668                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY;
 669                 break;
 670         default:
 671                 BUG();
 672         }
 673
 674         /*
 675          * Enable gamma to match primary/cursor plane behaviour.
 676          * FIXME should be user controllable via propertiesa.
 677          */
 678         dvscntr |= DVS_GAMMA_ENABLE;
 679
 680         if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
 681                 dvscntr |= DVS_TILED;
 682
 683         if (IS_GEN6(dev))
 684                 dvscntr |= DVS_TRICKLE_FEED_DISABLE; /* must disable */
 685
 686         /* Sizes are 0 based */
 687         src_w--;
 688         src_h--;
 689         crtc_w--;
 690         crtc_h--;
 691
 692         dvsscale = 0;
 693         if (crtc_w != src_w || crtc_h != src_h)
 694                 dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
 695
 696         intel_add_fb_offsets(&x, &y, plane_state, 0);
 697         dvssurf_offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
 698
 699         if (rotation == DRM_ROTATE_180) {
 700                 dvscntr |= DVS_ROTATE_180;
 701
 702                 x += src_w;
 703                 y += src_h;
 704         }
 705
 706         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
 707
 708         if (key->flags) {
 709                 I915_WRITE(DVSKEYVAL(pipe), key->min_value);
 710                 I915_WRITE(DVSKEYMAX(pipe), key->max_value);
 711                 I915_WRITE(DVSKEYMSK(pipe), key->channel_mask);
 712         }
 713
 714         if (key->flags & I915_SET_COLORKEY_DESTINATION)
 715                 dvscntr |= DVS_DEST_KEY;
 716         else if (key->flags & I915_SET_COLORKEY_SOURCE)
 717                 dvscntr |= DVS_SOURCE_KEY;
 718
 719         I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]);
 720         I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x);
 721
 722         if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
 723                 I915_WRITE(DVSTILEOFF(pipe), (y << 16) | x);
 724         else
 725                 I915_WRITE(DVSLINOFF(pipe), linear_offset);
 726
 727         I915_WRITE(DVSSIZE(pipe), (crtc_h << 16) | crtc_w);
 728         I915_WRITE(DVSSCALE(pipe), dvsscale);
 729         I915_WRITE(DVSCNTR(pipe), dvscntr);
 730         I915_WRITE(DVSSURF(pipe),
 731                    intel_fb_gtt_offset(fb, rotation) + dvssurf_offset);
 732         POSTING_READ(DVSSURF(pipe));
 733 }
 734
 735 static void
 736 ilk_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc)
 737 {
 738         struct drm_device *dev = plane->dev;
 739         struct drm_i915_private *dev_priv = to_i915(dev);
 740         struct intel_plane *intel_plane = to_intel_plane(plane);
 741         int pipe = intel_plane->pipe;
 742
 743         I915_WRITE(DVSCNTR(pipe), 0);
 744         /* Disable the scaler */
 745         I915_WRITE(DVSSCALE(pipe), 0);
 746
 747         I915_WRITE(DVSSURF(pipe), 0);
 748         POSTING_READ(DVSSURF(pipe));
 749 }
 750
 751 static int
 752 intel_check_sprite_plane(struct drm_plane *plane,
 753                          struct intel_crtc_state *crtc_state,
 754                          struct intel_plane_state *state)
 755 {
 756         struct drm_device *dev = plane->dev;
 757         struct drm_crtc *crtc = state->base.crtc;
 758         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 759         struct intel_plane *intel_plane = to_intel_plane(plane);
 760         struct drm_framebuffer *fb = state->base.fb;
 761         int crtc_x, crtc_y;
 762         unsigned int crtc_w, crtc_h;
 763         uint32_t src_x, src_y, src_w, src_h;
 764         struct drm_rect *src = &state->base.src;
 765         struct drm_rect *dst = &state->base.dst;
 766         const struct drm_rect *clip = &state->clip;
 767         int hscale, vscale;
 768         int max_scale, min_scale;
 769         bool can_scale;
 770         int ret;
 771
 772         src->x1 = state->base.src_x;
 773         src->y1 = state->base.src_y;
 774         src->x2 = state->base.src_x + state->base.src_w;
 775         src->y2 = state->base.src_y + state->base.src_h;
 776
 777         dst->x1 = state->base.crtc_x;
 778         dst->y1 = state->base.crtc_y;
 779         dst->x2 = state->base.crtc_x + state->base.crtc_w;
 780         dst->y2 = state->base.crtc_y + state->base.crtc_h;
 781
 782         if (!fb) {
 783                 state->base.visible = false;
 784                 return 0;
 785         }
 786
 787         /* Don't modify another pipe's plane */
 788         if (intel_plane->pipe != intel_crtc->pipe) {
 789                 DRM_DEBUG_KMS("Wrong plane <-> crtc mapping\n");
 790                 return -EINVAL;
 791         }
 792
 793         /* FIXME check all gen limits */
 794         if (fb->width < 3 || fb->height < 3 || fb->pitches[0] > 16384) {
 795                 DRM_DEBUG_KMS("Unsuitable framebuffer for plane\n");
 796                 return -EINVAL;
 797         }
 798
 799         /* setup can_scale, min_scale, max_scale */
 800         if (INTEL_INFO(dev)->gen >= 9) {
 801                 /* use scaler when colorkey is not required */
 802                 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
 803                         can_scale = 1;
 804                         min_scale = 1;
 805                         max_scale = skl_max_scale(intel_crtc, crtc_state);
 806                 } else {
 807                         can_scale = 0;
 808                         min_scale = DRM_PLANE_HELPER_NO_SCALING;
 809                         max_scale = DRM_PLANE_HELPER_NO_SCALING;
 810                 }
 811         } else {
 812                 can_scale = intel_plane->can_scale;
 813                 max_scale = intel_plane->max_downscale << 16;
 814                 min_scale = intel_plane->can_scale ? 1 : (1 << 16);
 815         }
 816
 817         /*
 818          * FIXME the following code does a bunch of fuzzy adjustments to the
 819          * coordinates and sizes. We probably need some way to decide whether
 820          * more strict checking should be done instead.
 821          */
 822         drm_rect_rotate(src, fb->width << 16, fb->height << 16,
 823                         state->base.rotation);
 824
 825         hscale = drm_rect_calc_hscale_relaxed(src, dst, min_scale, max_scale);
 826         BUG_ON(hscale < 0);
 827
 828         vscale = drm_rect_calc_vscale_relaxed(src, dst, min_scale, max_scale);
 829         BUG_ON(vscale < 0);
 830
 831         state->base.visible = drm_rect_clip_scaled(src, dst, clip, hscale, vscale);
 832
 833         crtc_x = dst->x1;
 834         crtc_y = dst->y1;
 835         crtc_w = drm_rect_width(dst);
 836         crtc_h = drm_rect_height(dst);
 837
 838         if (state->base.visible) {
 839                 /* check again in case clipping clamped the results */
 840                 hscale = drm_rect_calc_hscale(src, dst, min_scale, max_scale);
 841                 if (hscale < 0) {
 842                         DRM_DEBUG_KMS("Horizontal scaling factor out of limits\n");
 843                         drm_rect_debug_print("src: ", src, true);
 844                         drm_rect_debug_print("dst: ", dst, false);
 845
 846                         return hscale;
 847                 }
 848
 849                 vscale = drm_rect_calc_vscale(src, dst, min_scale, max_scale);
 850                 if (vscale < 0) {
 851                         DRM_DEBUG_KMS("Vertical scaling factor out of limits\n");
 852                         drm_rect_debug_print("src: ", src, true);
 853                         drm_rect_debug_print("dst: ", dst, false);
 854
 855                         return vscale;
 856                 }
 857
 858                 /* Make the source viewport size an exact multiple of the scaling factors. */
 859                 drm_rect_adjust_size(src,
 860                                      drm_rect_width(dst) * hscale - drm_rect_width(src),
 861                                      drm_rect_height(dst) * vscale - drm_rect_height(src));
 862
 863                 drm_rect_rotate_inv(src, fb->width << 16, fb->height << 16,
 864                                     state->base.rotation);
 865
 866                 /* sanity check to make sure the src viewport wasn't enlarged */
 867                 WARN_ON(src->x1 < (int) state->base.src_x ||
 868                         src->y1 < (int) state->base.src_y ||
 869                         src->x2 > (int) state->base.src_x + state->base.src_w ||
 870                         src->y2 > (int) state->base.src_y + state->base.src_h);
 871
 872                 /*
 873                  * Hardware doesn't handle subpixel coordinates.
 874                  * Adjust to (macro)pixel boundary, but be careful not to
 875                  * increase the source viewport size, because that could
 876                  * push the downscaling factor out of bounds.
 877                  */
 878                 src_x = src->x1 >> 16;
 879                 src_w = drm_rect_width(src) >> 16;
 880                 src_y = src->y1 >> 16;
 881                 src_h = drm_rect_height(src) >> 16;
 882
 883                 if (format_is_yuv(fb->pixel_format)) {
 884                         src_x &= ~1;
 885                         src_w &= ~1;
 886
 887                         /*
 888                          * Must keep src and dst the
 889                          * same if we can't scale.
 890                          */
 891                         if (!can_scale)
 892                                 crtc_w &= ~1;
 893
 894                         if (crtc_w == 0)
 895                                 state->base.visible = false;
 896                 }
 897         }
 898
 899         /* Check size restrictions when scaling */
 900         if (state->base.visible && (src_w != crtc_w || src_h != crtc_h)) {
 901                 unsigned int width_bytes;
 902                 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
 903
 904                 WARN_ON(!can_scale);
 905
 906                 /* FIXME interlacing min height is 6 */
 907
 908                 if (crtc_w < 3 || crtc_h < 3)
 909                         state->base.visible = false;
 910
 911                 if (src_w < 3 || src_h < 3)
 912                         state->base.visible = false;
 913
 914                 width_bytes = ((src_x * cpp) & 63) + src_w * cpp;
 915
 916                 if (INTEL_INFO(dev)->gen < 9 && (src_w > 2048 || src_h > 2048 ||
 917                     width_bytes > 4096 || fb->pitches[0] > 4096)) {
 918                         DRM_DEBUG_KMS("Source dimensions exceed hardware limits\n");
 919                         return -EINVAL;
 920                 }
 921         }
 922
 923         if (state->base.visible) {
 924                 src->x1 = src_x << 16;
 925                 src->x2 = (src_x + src_w) << 16;
 926                 src->y1 = src_y << 16;
 927                 src->y2 = (src_y + src_h) << 16;
 928         }
 929
 930         dst->x1 = crtc_x;
 931         dst->x2 = crtc_x + crtc_w;
 932         dst->y1 = crtc_y;
 933         dst->y2 = crtc_y + crtc_h;
 934
 935         if (INTEL_GEN(dev) >= 9) {
 936                 ret = skl_check_plane_surface(state);
 937                 if (ret)
 938                         return ret;
 939         }
 940
 941         return 0;
 942 }
 943
 944 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
 945                               struct drm_file *file_priv)
 946 {
 947         struct drm_intel_sprite_colorkey *set = data;
 948         struct drm_plane *plane;
 949         struct drm_plane_state *plane_state;
 950         struct drm_atomic_state *state;
 951         struct drm_modeset_acquire_ctx ctx;
 952         int ret = 0;
 953
 954         /* Make sure we don't try to enable both src & dest simultaneously */
 955         if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
 956                 return -EINVAL;
 957
 958         if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
 959             set->flags & I915_SET_COLORKEY_DESTINATION)
 960                 return -EINVAL;
 961
 962         plane = drm_plane_find(dev, set->plane_id);
 963         if (!plane || plane->type != DRM_PLANE_TYPE_OVERLAY)
 964                 return -ENOENT;
 965
 966         drm_modeset_acquire_init(&ctx, 0);
 967
 968         state = drm_atomic_state_alloc(plane->dev);
 969         if (!state) {
 970                 ret = -ENOMEM;
 971                 goto out;
 972         }
 973         state->acquire_ctx = &ctx;
 974
 975         while (1) {
 976                 plane_state = drm_atomic_get_plane_state(state, plane);
 977                 ret = PTR_ERR_OR_ZERO(plane_state);
 978                 if (!ret) {
 979                         to_intel_plane_state(plane_state)->ckey = *set;
 980                         ret = drm_atomic_commit(state);
 981                 }
 982
 983                 if (ret != -EDEADLK)
 984                         break;
 985
 986                 drm_atomic_state_clear(state);
 987                 drm_modeset_backoff(&ctx);
 988         }
 989
 990         if (ret)
 991                 drm_atomic_state_free(state);
 992
 993 out:
 994         drm_modeset_drop_locks(&ctx);
 995         drm_modeset_acquire_fini(&ctx);
 996         return ret;
 997 }
 998
 999 static const uint32_t ilk_plane_formats[] = {
1000         DRM_FORMAT_XRGB8888,
1001         DRM_FORMAT_YUYV,
1002         DRM_FORMAT_YVYU,
1003         DRM_FORMAT_UYVY,
1004         DRM_FORMAT_VYUY,
1005 };
1006
1007 static const uint32_t snb_plane_formats[] = {
1008         DRM_FORMAT_XBGR8888,
1009         DRM_FORMAT_XRGB8888,
1010         DRM_FORMAT_YUYV,
1011         DRM_FORMAT_YVYU,
1012         DRM_FORMAT_UYVY,
1013         DRM_FORMAT_VYUY,
1014 };
1015
1016 static const uint32_t vlv_plane_formats[] = {
1017         DRM_FORMAT_RGB565,
1018         DRM_FORMAT_ABGR8888,
1019         DRM_FORMAT_ARGB8888,
1020         DRM_FORMAT_XBGR8888,
1021         DRM_FORMAT_XRGB8888,
1022         DRM_FORMAT_XBGR2101010,
1023         DRM_FORMAT_ABGR2101010,
1024         DRM_FORMAT_YUYV,
1025         DRM_FORMAT_YVYU,
1026         DRM_FORMAT_UYVY,
1027         DRM_FORMAT_VYUY,
1028 };
1029
1030 static uint32_t skl_plane_formats[] = {
1031         DRM_FORMAT_RGB565,
1032         DRM_FORMAT_ABGR8888,
1033         DRM_FORMAT_ARGB8888,
1034         DRM_FORMAT_XBGR8888,
1035         DRM_FORMAT_XRGB8888,
1036         DRM_FORMAT_YUYV,
1037         DRM_FORMAT_YVYU,
1038         DRM_FORMAT_UYVY,
1039         DRM_FORMAT_VYUY,
1040 };
1041
1042 int
1043 intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane)
1044 {
1045         struct intel_plane *intel_plane = NULL;
1046         struct intel_plane_state *state = NULL;
1047         unsigned long possible_crtcs;
1048         const uint32_t *plane_formats;
1049         int num_plane_formats;
1050         int ret;
1051
1052         if (INTEL_INFO(dev)->gen < 5)
1053                 return -ENODEV;
1054
1055         intel_plane = kzalloc(sizeof(*intel_plane), GFP_KERNEL);
1056         if (!intel_plane) {
1057                 ret = -ENOMEM;
1058                 goto fail;
1059         }
1060
1061         state = intel_create_plane_state(&intel_plane->base);
1062         if (!state) {
1063                 ret = -ENOMEM;
1064                 goto fail;
1065         }
1066         intel_plane->base.state = &state->base;
1067
1068         switch (INTEL_INFO(dev)->gen) {
1069         case 5:
1070         case 6:
1071                 intel_plane->can_scale = true;
1072                 intel_plane->max_downscale = 16;
1073                 intel_plane->update_plane = ilk_update_plane;
1074                 intel_plane->disable_plane = ilk_disable_plane;
1075
1076                 if (IS_GEN6(dev)) {
1077                         plane_formats = snb_plane_formats;
1078                         num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1079                 } else {
1080                         plane_formats = ilk_plane_formats;
1081                         num_plane_formats = ARRAY_SIZE(ilk_plane_formats);
1082                 }
1083                 break;
1084
1085         case 7:
1086         case 8:
1087                 if (IS_IVYBRIDGE(dev)) {
1088                         intel_plane->can_scale = true;
1089                         intel_plane->max_downscale = 2;
1090                 } else {
1091                         intel_plane->can_scale = false;
1092                         intel_plane->max_downscale = 1;
1093                 }
1094
1095                 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1096                         intel_plane->update_plane = vlv_update_plane;
1097                         intel_plane->disable_plane = vlv_disable_plane;
1098
1099                         plane_formats = vlv_plane_formats;
1100                         num_plane_formats = ARRAY_SIZE(vlv_plane_formats);
1101                 } else {
1102                         intel_plane->update_plane = ivb_update_plane;
1103                         intel_plane->disable_plane = ivb_disable_plane;
1104
1105                         plane_formats = snb_plane_formats;
1106                         num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1107                 }
1108                 break;
1109         case 9:
1110                 intel_plane->can_scale = true;
1111                 intel_plane->update_plane = skl_update_plane;
1112                 intel_plane->disable_plane = skl_disable_plane;
1113                 state->scaler_id = -1;
1114
1115                 plane_formats = skl_plane_formats;
1116                 num_plane_formats = ARRAY_SIZE(skl_plane_formats);
1117                 break;
1118         default:
1119                 MISSING_CASE(INTEL_INFO(dev)->gen);
1120                 ret = -ENODEV;
1121                 goto fail;
1122         }
1123
1124         intel_plane->pipe = pipe;
1125         intel_plane->plane = plane;
1126         intel_plane->frontbuffer_bit = INTEL_FRONTBUFFER_SPRITE(pipe, plane);
1127         intel_plane->check_plane = intel_check_sprite_plane;
1128
1129         possible_crtcs = (1 << pipe);
1130
1131         if (INTEL_INFO(dev)->gen >= 9)
1132                 ret = drm_universal_plane_init(dev, &intel_plane->base, possible_crtcs,
1133                                                &intel_plane_funcs,
1134                                                plane_formats, num_plane_formats,
1135                                                DRM_PLANE_TYPE_OVERLAY,
1136                                                "plane %d%c", plane + 2, pipe_name(pipe));
1137         else
1138                 ret = drm_universal_plane_init(dev, &intel_plane->base, possible_crtcs,
1139                                                &intel_plane_funcs,
1140                                                plane_formats, num_plane_formats,
1141                                                DRM_PLANE_TYPE_OVERLAY,
1142                                                "sprite %c", sprite_name(pipe, plane));
1143         if (ret)
1144                 goto fail;
1145
1146         intel_create_rotation_property(dev, intel_plane);
1147
1148         drm_plane_helper_add(&intel_plane->base, &intel_plane_helper_funcs);
1149
1150         return 0;
1151
1152 fail:
1153         kfree(state);
1154         kfree(intel_plane);
1155
1156         return ret;
1157 }