drivers/gpu/drm/i915/intel_uncore.c

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "i915_drv.h"
  25 #include "intel_drv.h"
  26 #include "i915_vgpu.h"
  27
  28 #include <linux/pm_runtime.h>
  29
  30 #define FORCEWAKE_ACK_TIMEOUT_MS 50
  31
  32 #define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32((dev_priv__), (reg__))
  33
  34 static const char * const forcewake_domain_names[] = {
  35         "render",
  36         "blitter",
  37         "media",
  38 };
  39
  40 const char *
  41 intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id)
  42 {
  43         BUILD_BUG_ON(ARRAY_SIZE(forcewake_domain_names) != FW_DOMAIN_ID_COUNT);
  44
  45         if (id >= 0 && id < FW_DOMAIN_ID_COUNT)
  46                 return forcewake_domain_names[id];
  47
  48         WARN_ON(id);
  49
  50         return "unknown";
  51 }
  52
  53 static inline void
  54 fw_domain_reset(const struct intel_uncore_forcewake_domain *d)
  55 {
  56         WARN_ON(!i915_mmio_reg_valid(d->reg_set));
  57         __raw_i915_write32(d->i915, d->reg_set, d->val_reset);
  58 }
  59
  60 static inline void
  61 fw_domain_arm_timer(struct intel_uncore_forcewake_domain *d)
  62 {
  63         d->wake_count++;
  64         hrtimer_start_range_ns(&d->timer,
  65                                ktime_set(0, NSEC_PER_MSEC),
  66                                NSEC_PER_MSEC,
  67                                HRTIMER_MODE_REL);
  68 }
  69
  70 static inline void
  71 fw_domain_wait_ack_clear(const struct intel_uncore_forcewake_domain *d)
  72 {
  73         if (wait_for_atomic((__raw_i915_read32(d->i915, d->reg_ack) &
  74                              FORCEWAKE_KERNEL) == 0,
  75                             FORCEWAKE_ACK_TIMEOUT_MS))
  76                 DRM_ERROR("%s: timed out waiting for forcewake ack to clear.\n",
  77                           intel_uncore_forcewake_domain_to_str(d->id));
  78 }
  79
  80 static inline void
  81 fw_domain_get(const struct intel_uncore_forcewake_domain *d)
  82 {
  83         __raw_i915_write32(d->i915, d->reg_set, d->val_set);
  84 }
  85
  86 static inline void
  87 fw_domain_wait_ack(const struct intel_uncore_forcewake_domain *d)
  88 {
  89         if (wait_for_atomic((__raw_i915_read32(d->i915, d->reg_ack) &
  90                              FORCEWAKE_KERNEL),
  91                             FORCEWAKE_ACK_TIMEOUT_MS))
  92                 DRM_ERROR("%s: timed out waiting for forcewake ack request.\n",
  93                           intel_uncore_forcewake_domain_to_str(d->id));
  94 }
  95
  96 static inline void
  97 fw_domain_put(const struct intel_uncore_forcewake_domain *d)
  98 {
  99         __raw_i915_write32(d->i915, d->reg_set, d->val_clear);
 100 }
 101
 102 static inline void
 103 fw_domain_posting_read(const struct intel_uncore_forcewake_domain *d)
 104 {
 105         /* something from same cacheline, but not from the set register */
 106         if (i915_mmio_reg_valid(d->reg_post))
 107                 __raw_posting_read(d->i915, d->reg_post);
 108 }
 109
 110 static void
 111 fw_domains_get(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains)
 112 {
 113         struct intel_uncore_forcewake_domain *d;
 114
 115         for_each_fw_domain_masked(d, fw_domains, dev_priv) {
 116                 fw_domain_wait_ack_clear(d);
 117                 fw_domain_get(d);
 118         }
 119
 120         for_each_fw_domain_masked(d, fw_domains, dev_priv)
 121                 fw_domain_wait_ack(d);
 122 }
 123
 124 static void
 125 fw_domains_put(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains)
 126 {
 127         struct intel_uncore_forcewake_domain *d;
 128
 129         for_each_fw_domain_masked(d, fw_domains, dev_priv) {
 130                 fw_domain_put(d);
 131                 fw_domain_posting_read(d);
 132         }
 133 }
 134
 135 static void
 136 fw_domains_posting_read(struct drm_i915_private *dev_priv)
 137 {
 138         struct intel_uncore_forcewake_domain *d;
 139
 140         /* No need to do for all, just do for first found */
 141         for_each_fw_domain(d, dev_priv) {
 142                 fw_domain_posting_read(d);
 143                 break;
 144         }
 145 }
 146
 147 static void
 148 fw_domains_reset(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains)
 149 {
 150         struct intel_uncore_forcewake_domain *d;
 151
 152         if (dev_priv->uncore.fw_domains == 0)
 153                 return;
 154
 155         for_each_fw_domain_masked(d, fw_domains, dev_priv)
 156                 fw_domain_reset(d);
 157
 158         fw_domains_posting_read(dev_priv);
 159 }
 160
 161 static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
 162 {
 163         /* w/a for a sporadic read returning 0 by waiting for the GT
 164          * thread to wake up.
 165          */
 166         if (wait_for_atomic_us((__raw_i915_read32(dev_priv, GEN6_GT_THREAD_STATUS_REG) &
 167                                 GEN6_GT_THREAD_STATUS_CORE_MASK) == 0, 500))
 168                 DRM_ERROR("GT thread status wait timed out\n");
 169 }
 170
 171 static void fw_domains_get_with_thread_status(struct drm_i915_private *dev_priv,
 172                                               enum forcewake_domains fw_domains)
 173 {
 174         fw_domains_get(dev_priv, fw_domains);
 175
 176         /* WaRsForcewakeWaitTC0:snb,ivb,hsw,bdw,vlv */
 177         __gen6_gt_wait_for_thread_c0(dev_priv);
 178 }
 179
 180 static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
 181 {
 182         u32 gtfifodbg;
 183
 184         gtfifodbg = __raw_i915_read32(dev_priv, GTFIFODBG);
 185         if (WARN(gtfifodbg, "GT wake FIFO error 0x%x\n", gtfifodbg))
 186                 __raw_i915_write32(dev_priv, GTFIFODBG, gtfifodbg);
 187 }
 188
 189 static void fw_domains_put_with_fifo(struct drm_i915_private *dev_priv,
 190                                      enum forcewake_domains fw_domains)
 191 {
 192         fw_domains_put(dev_priv, fw_domains);
 193         gen6_gt_check_fifodbg(dev_priv);
 194 }
 195
 196 static inline u32 fifo_free_entries(struct drm_i915_private *dev_priv)
 197 {
 198         u32 count = __raw_i915_read32(dev_priv, GTFIFOCTL);
 199
 200         return count & GT_FIFO_FREE_ENTRIES_MASK;
 201 }
 202
 203 static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
 204 {
 205         int ret = 0;
 206
 207         /* On VLV, FIFO will be shared by both SW and HW.
 208          * So, we need to read the FREE_ENTRIES everytime */
 209         if (IS_VALLEYVIEW(dev_priv))
 210                 dev_priv->uncore.fifo_count = fifo_free_entries(dev_priv);
 211
 212         if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
 213                 int loop = 500;
 214                 u32 fifo = fifo_free_entries(dev_priv);
 215
 216                 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
 217                         udelay(10);
 218                         fifo = fifo_free_entries(dev_priv);
 219                 }
 220                 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
 221                         ++ret;
 222                 dev_priv->uncore.fifo_count = fifo;
 223         }
 224         dev_priv->uncore.fifo_count--;
 225
 226         return ret;
 227 }
 228
 229 static enum hrtimer_restart
 230 intel_uncore_fw_release_timer(struct hrtimer *timer)
 231 {
 232         struct intel_uncore_forcewake_domain *domain =
 233                container_of(timer, struct intel_uncore_forcewake_domain, timer);
 234         unsigned long irqflags;
 235
 236         assert_rpm_device_not_suspended(domain->i915);
 237
 238         spin_lock_irqsave(&domain->i915->uncore.lock, irqflags);
 239         if (WARN_ON(domain->wake_count == 0))
 240                 domain->wake_count++;
 241
 242         if (--domain->wake_count == 0)
 243                 domain->i915->uncore.funcs.force_wake_put(domain->i915,
 244                                                           1 << domain->id);
 245
 246         spin_unlock_irqrestore(&domain->i915->uncore.lock, irqflags);
 247
 248         return HRTIMER_NORESTART;
 249 }
 250
 251 void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore)
 252 {
 253         struct drm_i915_private *dev_priv = dev->dev_private;
 254         unsigned long irqflags;
 255         struct intel_uncore_forcewake_domain *domain;
 256         int retry_count = 100;
 257         enum forcewake_domains fw = 0, active_domains;
 258
 259         /* Hold uncore.lock across reset to prevent any register access
 260          * with forcewake not set correctly. Wait until all pending
 261          * timers are run before holding.
 262          */
 263         while (1) {
 264                 active_domains = 0;
 265
 266                 for_each_fw_domain(domain, dev_priv) {
 267                         if (hrtimer_cancel(&domain->timer) == 0)
 268                                 continue;
 269
 270                         intel_uncore_fw_release_timer(&domain->timer);
 271                 }
 272
 273                 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 274
 275                 for_each_fw_domain(domain, dev_priv) {
 276                         if (hrtimer_active(&domain->timer))
 277                                 active_domains |= domain->mask;
 278                 }
 279
 280                 if (active_domains == 0)
 281                         break;
 282
 283                 if (--retry_count == 0) {
 284                         DRM_ERROR("Timed out waiting for forcewake timers to finish\n");
 285                         break;
 286                 }
 287
 288                 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 289                 cond_resched();
 290         }
 291
 292         WARN_ON(active_domains);
 293
 294         for_each_fw_domain(domain, dev_priv)
 295                 if (domain->wake_count)
 296                         fw |= domain->mask;
 297
 298         if (fw)
 299                 dev_priv->uncore.funcs.force_wake_put(dev_priv, fw);
 300
 301         fw_domains_reset(dev_priv, FORCEWAKE_ALL);
 302
 303         if (restore) { /* If reset with a user forcewake, try to restore */
 304                 if (fw)
 305                         dev_priv->uncore.funcs.force_wake_get(dev_priv, fw);
 306
 307                 if (IS_GEN6(dev) || IS_GEN7(dev))
 308                         dev_priv->uncore.fifo_count =
 309                                 fifo_free_entries(dev_priv);
 310         }
 311
 312         if (!restore)
 313                 assert_forcewakes_inactive(dev_priv);
 314
 315         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 316 }
 317
 318 static void intel_uncore_ellc_detect(struct drm_device *dev)
 319 {
 320         struct drm_i915_private *dev_priv = dev->dev_private;
 321
 322         if ((IS_HASWELL(dev) || IS_BROADWELL(dev) ||
 323              INTEL_INFO(dev)->gen >= 9) &&
 324             (__raw_i915_read32(dev_priv, HSW_EDRAM_PRESENT) & EDRAM_ENABLED)) {
 325                 /* The docs do not explain exactly how the calculation can be
 326                  * made. It is somewhat guessable, but for now, it's always
 327                  * 128MB.
 328                  * NB: We can't write IDICR yet because we do not have gt funcs
 329                  * set up */
 330                 dev_priv->ellc_size = 128;
 331                 DRM_INFO("Found %zuMB of eLLC\n", dev_priv->ellc_size);
 332         }
 333 }
 334
 335 static bool
 336 fpga_check_for_unclaimed_mmio(struct drm_i915_private *dev_priv)
 337 {
 338         u32 dbg;
 339
 340         dbg = __raw_i915_read32(dev_priv, FPGA_DBG);
 341         if (likely(!(dbg & FPGA_DBG_RM_NOCLAIM)))
 342                 return false;
 343
 344         __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
 345
 346         return true;
 347 }
 348
 349 static bool
 350 vlv_check_for_unclaimed_mmio(struct drm_i915_private *dev_priv)
 351 {
 352         u32 cer;
 353
 354         cer = __raw_i915_read32(dev_priv, CLAIM_ER);
 355         if (likely(!(cer & (CLAIM_ER_OVERFLOW | CLAIM_ER_CTR_MASK))))
 356                 return false;
 357
 358         __raw_i915_write32(dev_priv, CLAIM_ER, CLAIM_ER_CLR);
 359
 360         return true;
 361 }
 362
 363 static bool
 364 check_for_unclaimed_mmio(struct drm_i915_private *dev_priv)
 365 {
 366         if (HAS_FPGA_DBG_UNCLAIMED(dev_priv))
 367                 return fpga_check_for_unclaimed_mmio(dev_priv);
 368
 369         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 370                 return vlv_check_for_unclaimed_mmio(dev_priv);
 371
 372         return false;
 373 }
 374
 375 static void __intel_uncore_early_sanitize(struct drm_device *dev,
 376                                           bool restore_forcewake)
 377 {
 378         struct drm_i915_private *dev_priv = dev->dev_private;
 379
 380         /* clear out unclaimed reg detection bit */
 381         if (check_for_unclaimed_mmio(dev_priv))
 382                 DRM_DEBUG("unclaimed mmio detected on uncore init, clearing\n");
 383
 384         /* clear out old GT FIFO errors */
 385         if (IS_GEN6(dev) || IS_GEN7(dev))
 386                 __raw_i915_write32(dev_priv, GTFIFODBG,
 387                                    __raw_i915_read32(dev_priv, GTFIFODBG));
 388
 389         /* WaDisableShadowRegForCpd:chv */
 390         if (IS_CHERRYVIEW(dev)) {
 391                 __raw_i915_write32(dev_priv, GTFIFOCTL,
 392                                    __raw_i915_read32(dev_priv, GTFIFOCTL) |
 393                                    GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL |
 394                                    GT_FIFO_CTL_RC6_POLICY_STALL);
 395         }
 396
 397         intel_uncore_forcewake_reset(dev, restore_forcewake);
 398 }
 399
 400 void intel_uncore_early_sanitize(struct drm_device *dev, bool restore_forcewake)
 401 {
 402         __intel_uncore_early_sanitize(dev, restore_forcewake);
 403         i915_check_and_clear_faults(dev);
 404 }
 405
 406 void intel_uncore_sanitize(struct drm_device *dev)
 407 {
 408         i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6);
 409
 410         /* BIOS often leaves RC6 enabled, but disable it for hw init */
 411         intel_disable_gt_powersave(dev);
 412 }
 413
 414 static void __intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
 415                                          enum forcewake_domains fw_domains)
 416 {
 417         struct intel_uncore_forcewake_domain *domain;
 418
 419         if (!dev_priv->uncore.funcs.force_wake_get)
 420                 return;
 421
 422         fw_domains &= dev_priv->uncore.fw_domains;
 423
 424         for_each_fw_domain_masked(domain, fw_domains, dev_priv) {
 425                 if (domain->wake_count++)
 426                         fw_domains &= ~domain->mask;
 427         }
 428
 429         if (fw_domains)
 430                 dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains);
 431 }
 432
 433 /**
 434  * intel_uncore_forcewake_get - grab forcewake domain references
 435  * @dev_priv: i915 device instance
 436  * @fw_domains: forcewake domains to get reference on
 437  *
 438  * This function can be used get GT's forcewake domain references.
 439  * Normal register access will handle the forcewake domains automatically.
 440  * However if some sequence requires the GT to not power down a particular
 441  * forcewake domains this function should be called at the beginning of the
 442  * sequence. And subsequently the reference should be dropped by symmetric
 443  * call to intel_unforce_forcewake_put(). Usually caller wants all the domains
 444  * to be kept awake so the @fw_domains would be then FORCEWAKE_ALL.
 445  */
 446 void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
 447                                 enum forcewake_domains fw_domains)
 448 {
 449         unsigned long irqflags;
 450
 451         if (!dev_priv->uncore.funcs.force_wake_get)
 452                 return;
 453
 454         assert_rpm_wakelock_held(dev_priv);
 455
 456         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 457         __intel_uncore_forcewake_get(dev_priv, fw_domains);
 458         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 459 }
 460
 461 /**
 462  * intel_uncore_forcewake_get__locked - grab forcewake domain references
 463  * @dev_priv: i915 device instance
 464  * @fw_domains: forcewake domains to get reference on
 465  *
 466  * See intel_uncore_forcewake_get(). This variant places the onus
 467  * on the caller to explicitly handle the dev_priv->uncore.lock spinlock.
 468  */
 469 void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
 470                                         enum forcewake_domains fw_domains)
 471 {
 472         assert_spin_locked(&dev_priv->uncore.lock);
 473
 474         if (!dev_priv->uncore.funcs.force_wake_get)
 475                 return;
 476
 477         __intel_uncore_forcewake_get(dev_priv, fw_domains);
 478 }
 479
 480 static void __intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
 481                                          enum forcewake_domains fw_domains)
 482 {
 483         struct intel_uncore_forcewake_domain *domain;
 484
 485         if (!dev_priv->uncore.funcs.force_wake_put)
 486                 return;
 487
 488         fw_domains &= dev_priv->uncore.fw_domains;
 489
 490         for_each_fw_domain_masked(domain, fw_domains, dev_priv) {
 491                 if (WARN_ON(domain->wake_count == 0))
 492                         continue;
 493
 494                 if (--domain->wake_count)
 495                         continue;
 496
 497                 fw_domain_arm_timer(domain);
 498         }
 499 }
 500
 501 /**
 502  * intel_uncore_forcewake_put - release a forcewake domain reference
 503  * @dev_priv: i915 device instance
 504  * @fw_domains: forcewake domains to put references
 505  *
 506  * This function drops the device-level forcewakes for specified
 507  * domains obtained by intel_uncore_forcewake_get().
 508  */
 509 void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
 510                                 enum forcewake_domains fw_domains)
 511 {
 512         unsigned long irqflags;
 513
 514         if (!dev_priv->uncore.funcs.force_wake_put)
 515                 return;
 516
 517         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 518         __intel_uncore_forcewake_put(dev_priv, fw_domains);
 519         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 520 }
 521
 522 /**
 523  * intel_uncore_forcewake_put__locked - grab forcewake domain references
 524  * @dev_priv: i915 device instance
 525  * @fw_domains: forcewake domains to get reference on
 526  *
 527  * See intel_uncore_forcewake_put(). This variant places the onus
 528  * on the caller to explicitly handle the dev_priv->uncore.lock spinlock.
 529  */
 530 void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
 531                                         enum forcewake_domains fw_domains)
 532 {
 533         assert_spin_locked(&dev_priv->uncore.lock);
 534
 535         if (!dev_priv->uncore.funcs.force_wake_put)
 536                 return;
 537
 538         __intel_uncore_forcewake_put(dev_priv, fw_domains);
 539 }
 540
 541 void assert_forcewakes_inactive(struct drm_i915_private *dev_priv)
 542 {
 543         struct intel_uncore_forcewake_domain *domain;
 544
 545         if (!dev_priv->uncore.funcs.force_wake_get)
 546                 return;
 547
 548         for_each_fw_domain(domain, dev_priv)
 549                 WARN_ON(domain->wake_count);
 550 }
 551
 552 /* We give fast paths for the really cool registers */
 553 #define NEEDS_FORCE_WAKE(reg) ((reg) < 0x40000)
 554
 555 #define __gen6_reg_read_fw_domains(offset) \
 556 ({ \
 557         enum forcewake_domains __fwd; \
 558         if (NEEDS_FORCE_WAKE(offset)) \
 559                 __fwd = FORCEWAKE_RENDER; \
 560         else \
 561                 __fwd = 0; \
 562         __fwd; \
 563 })
 564
 565 #define REG_RANGE(reg, start, end) ((reg) >= (start) && (reg) < (end))
 566
 567 #define FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg) \
 568         (REG_RANGE((reg), 0x2000, 0x4000) || \
 569          REG_RANGE((reg), 0x5000, 0x8000) || \
 570          REG_RANGE((reg), 0xB000, 0x12000) || \
 571          REG_RANGE((reg), 0x2E000, 0x30000))
 572
 573 #define FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg) \
 574         (REG_RANGE((reg), 0x12000, 0x14000) || \
 575          REG_RANGE((reg), 0x22000, 0x24000) || \
 576          REG_RANGE((reg), 0x30000, 0x40000))
 577
 578 #define __vlv_reg_read_fw_domains(offset) \
 579 ({ \
 580         enum forcewake_domains __fwd = 0; \
 581         if (!NEEDS_FORCE_WAKE(offset)) \
 582                 __fwd = 0; \
 583         else if (FORCEWAKE_VLV_RENDER_RANGE_OFFSET(offset)) \
 584                 __fwd = FORCEWAKE_RENDER; \
 585         else if (FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(offset)) \
 586                 __fwd = FORCEWAKE_MEDIA; \
 587         __fwd; \
 588 })
 589
 590 static const i915_reg_t gen8_shadowed_regs[] = {
 591         GEN6_RPNSWREQ,
 592         GEN6_RC_VIDEO_FREQ,
 593         RING_TAIL(RENDER_RING_BASE),
 594         RING_TAIL(GEN6_BSD_RING_BASE),
 595         RING_TAIL(VEBOX_RING_BASE),
 596         RING_TAIL(BLT_RING_BASE),
 597         /* TODO: Other registers are not yet used */
 598 };
 599
 600 static bool is_gen8_shadowed(u32 offset)
 601 {
 602         int i;
 603         for (i = 0; i < ARRAY_SIZE(gen8_shadowed_regs); i++)
 604                 if (offset == gen8_shadowed_regs[i].reg)
 605                         return true;
 606
 607         return false;
 608 }
 609
 610 #define __gen8_reg_write_fw_domains(offset) \
 611 ({ \
 612         enum forcewake_domains __fwd; \
 613         if (NEEDS_FORCE_WAKE(offset) && !is_gen8_shadowed(offset)) \
 614                 __fwd = FORCEWAKE_RENDER; \
 615         else \
 616                 __fwd = 0; \
 617         __fwd; \
 618 })
 619
 620 #define FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg) \
 621         (REG_RANGE((reg), 0x2000, 0x4000) || \
 622          REG_RANGE((reg), 0x5200, 0x8000) || \
 623          REG_RANGE((reg), 0x8300, 0x8500) || \
 624          REG_RANGE((reg), 0xB000, 0xB480) || \
 625          REG_RANGE((reg), 0xE000, 0xE800))
 626
 627 #define FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg) \
 628         (REG_RANGE((reg), 0x8800, 0x8900) || \
 629          REG_RANGE((reg), 0xD000, 0xD800) || \
 630          REG_RANGE((reg), 0x12000, 0x14000) || \
 631          REG_RANGE((reg), 0x1A000, 0x1C000) || \
 632          REG_RANGE((reg), 0x1E800, 0x1EA00) || \
 633          REG_RANGE((reg), 0x30000, 0x38000))
 634
 635 #define FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg) \
 636         (REG_RANGE((reg), 0x4000, 0x5000) || \
 637          REG_RANGE((reg), 0x8000, 0x8300) || \
 638          REG_RANGE((reg), 0x8500, 0x8600) || \
 639          REG_RANGE((reg), 0x9000, 0xB000) || \
 640          REG_RANGE((reg), 0xF000, 0x10000))
 641
 642 #define __chv_reg_read_fw_domains(offset) \
 643 ({ \
 644         enum forcewake_domains __fwd = 0; \
 645         if (!NEEDS_FORCE_WAKE(offset)) \
 646                 __fwd = 0; \
 647         else if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(offset)) \
 648                 __fwd = FORCEWAKE_RENDER; \
 649         else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(offset)) \
 650                 __fwd = FORCEWAKE_MEDIA; \
 651         else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(offset)) \
 652                 __fwd = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \
 653         __fwd; \
 654 })
 655
 656 #define __chv_reg_write_fw_domains(offset) \
 657 ({ \
 658         enum forcewake_domains __fwd = 0; \
 659         if (!NEEDS_FORCE_WAKE(offset) || is_gen8_shadowed(offset)) \
 660                 __fwd = 0; \
 661         else if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(offset)) \
 662                 __fwd = FORCEWAKE_RENDER; \
 663         else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(offset)) \
 664                 __fwd = FORCEWAKE_MEDIA; \
 665         else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(offset)) \
 666                 __fwd = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \
 667         __fwd; \
 668 })
 669
 670 #define FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg) \
 671         REG_RANGE((reg), 0xB00,  0x2000)
 672
 673 #define FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg) \
 674         (REG_RANGE((reg), 0x2000, 0x2700) || \
 675          REG_RANGE((reg), 0x3000, 0x4000) || \
 676          REG_RANGE((reg), 0x5200, 0x8000) || \
 677          REG_RANGE((reg), 0x8140, 0x8160) || \
 678          REG_RANGE((reg), 0x8300, 0x8500) || \
 679          REG_RANGE((reg), 0x8C00, 0x8D00) || \
 680          REG_RANGE((reg), 0xB000, 0xB480) || \
 681          REG_RANGE((reg), 0xE000, 0xE900) || \
 682          REG_RANGE((reg), 0x24400, 0x24800))
 683
 684 #define FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg) \
 685         (REG_RANGE((reg), 0x8130, 0x8140) || \
 686          REG_RANGE((reg), 0x8800, 0x8A00) || \
 687          REG_RANGE((reg), 0xD000, 0xD800) || \
 688          REG_RANGE((reg), 0x12000, 0x14000) || \
 689          REG_RANGE((reg), 0x1A000, 0x1EA00) || \
 690          REG_RANGE((reg), 0x30000, 0x40000))
 691
 692 #define FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg) \
 693         REG_RANGE((reg), 0x9400, 0x9800)
 694
 695 #define FORCEWAKE_GEN9_BLITTER_RANGE_OFFSET(reg) \
 696         ((reg) < 0x40000 && \
 697          !FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg) && \
 698          !FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg) && \
 699          !FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg) && \
 700          !FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg))
 701
 702 #define SKL_NEEDS_FORCE_WAKE(reg) \
 703         ((reg) < 0x40000 && !FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg))
 704
 705 #define __gen9_reg_read_fw_domains(offset) \
 706 ({ \
 707         enum forcewake_domains __fwd; \
 708         if (!SKL_NEEDS_FORCE_WAKE(offset)) \
 709                 __fwd = 0; \
 710         else if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(offset)) \
 711                 __fwd = FORCEWAKE_RENDER; \
 712         else if (FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(offset)) \
 713                 __fwd = FORCEWAKE_MEDIA; \
 714         else if (FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(offset)) \
 715                 __fwd = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \
 716         else \
 717                 __fwd = FORCEWAKE_BLITTER; \
 718         __fwd; \
 719 })
 720
 721 static const i915_reg_t gen9_shadowed_regs[] = {
 722         RING_TAIL(RENDER_RING_BASE),
 723         RING_TAIL(GEN6_BSD_RING_BASE),
 724         RING_TAIL(VEBOX_RING_BASE),
 725         RING_TAIL(BLT_RING_BASE),
 726         GEN6_RPNSWREQ,
 727         GEN6_RC_VIDEO_FREQ,
 728         /* TODO: Other registers are not yet used */
 729 };
 730
 731 static bool is_gen9_shadowed(u32 offset)
 732 {
 733         int i;
 734         for (i = 0; i < ARRAY_SIZE(gen9_shadowed_regs); i++)
 735                 if (offset == gen9_shadowed_regs[i].reg)
 736                         return true;
 737
 738         return false;
 739 }
 740
 741 #define __gen9_reg_write_fw_domains(offset) \
 742 ({ \
 743         enum forcewake_domains __fwd; \
 744         if (!SKL_NEEDS_FORCE_WAKE(offset) || is_gen9_shadowed(offset)) \
 745                 __fwd = 0; \
 746         else if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(offset)) \
 747                 __fwd = FORCEWAKE_RENDER; \
 748         else if (FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(offset)) \
 749                 __fwd = FORCEWAKE_MEDIA; \
 750         else if (FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(offset)) \
 751                 __fwd = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \
 752         else \
 753                 __fwd = FORCEWAKE_BLITTER; \
 754         __fwd; \
 755 })
 756
 757 static void
 758 ilk_dummy_write(struct drm_i915_private *dev_priv)
 759 {
 760         /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up
 761          * the chip from rc6 before touching it for real. MI_MODE is masked,
 762          * hence harmless to write 0 into. */
 763         __raw_i915_write32(dev_priv, MI_MODE, 0);
 764 }
 765
 766 static void
 767 __unclaimed_reg_debug(struct drm_i915_private *dev_priv,
 768                       const i915_reg_t reg,
 769                       const bool read,
 770                       const bool before)
 771 {
 772         if (WARN(check_for_unclaimed_mmio(dev_priv),
 773                  "Unclaimed register detected %s %s register 0x%x\n",
 774                  before ? "before" : "after",
 775                  read ? "reading" : "writing to",
 776                  i915_mmio_reg_offset(reg)))
 777                 i915.mmio_debug--; /* Only report the first N failures */
 778 }
 779
 780 static inline void
 781 unclaimed_reg_debug(struct drm_i915_private *dev_priv,
 782                     const i915_reg_t reg,
 783                     const bool read,
 784                     const bool before)
 785 {
 786         if (likely(!i915.mmio_debug))
 787                 return;
 788
 789         __unclaimed_reg_debug(dev_priv, reg, read, before);
 790 }
 791
 792 #define GEN2_READ_HEADER(x) \
 793         u##x val = 0; \
 794         assert_rpm_wakelock_held(dev_priv);
 795
 796 #define GEN2_READ_FOOTER \
 797         trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
 798         return val
 799
 800 #define __gen2_read(x) \
 801 static u##x \
 802 gen2_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
 803         GEN2_READ_HEADER(x); \
 804         val = __raw_i915_read##x(dev_priv, reg); \
 805         GEN2_READ_FOOTER; \
 806 }
 807
 808 #define __gen5_read(x) \
 809 static u##x \
 810 gen5_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
 811         GEN2_READ_HEADER(x); \
 812         ilk_dummy_write(dev_priv); \
 813         val = __raw_i915_read##x(dev_priv, reg); \
 814         GEN2_READ_FOOTER; \
 815 }
 816
 817 __gen5_read(8)
 818 __gen5_read(16)
 819 __gen5_read(32)
 820 __gen5_read(64)
 821 __gen2_read(8)
 822 __gen2_read(16)
 823 __gen2_read(32)
 824 __gen2_read(64)
 825
 826 #undef __gen5_read
 827 #undef __gen2_read
 828
 829 #undef GEN2_READ_FOOTER
 830 #undef GEN2_READ_HEADER
 831
 832 #define GEN6_READ_HEADER(x) \
 833         u32 offset = i915_mmio_reg_offset(reg); \
 834         unsigned long irqflags; \
 835         u##x val = 0; \
 836         assert_rpm_wakelock_held(dev_priv); \
 837         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); \
 838         unclaimed_reg_debug(dev_priv, reg, true, true)
 839
 840 #define GEN6_READ_FOOTER \
 841         unclaimed_reg_debug(dev_priv, reg, true, false); \
 842         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
 843         trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
 844         return val
 845
 846 static inline void __force_wake_auto(struct drm_i915_private *dev_priv,
 847                                      enum forcewake_domains fw_domains)
 848 {
 849         struct intel_uncore_forcewake_domain *domain;
 850
 851         if (WARN_ON(!fw_domains))
 852                 return;
 853
 854         /* Ideally GCC would be constant-fold and eliminate this loop */
 855         for_each_fw_domain_masked(domain, fw_domains, dev_priv) {
 856                 if (domain->wake_count) {
 857                         fw_domains &= ~domain->mask;
 858                         continue;
 859                 }
 860
 861                 fw_domain_arm_timer(domain);
 862         }
 863
 864         if (fw_domains)
 865                 dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains);
 866 }
 867
 868 #define __gen6_read(x) \
 869 static u##x \
 870 gen6_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
 871         enum forcewake_domains fw_engine; \
 872         GEN6_READ_HEADER(x); \
 873         fw_engine = __gen6_reg_read_fw_domains(offset); \
 874         if (fw_engine) \
 875                 __force_wake_auto(dev_priv, fw_engine); \
 876         val = __raw_i915_read##x(dev_priv, reg); \
 877         GEN6_READ_FOOTER; \
 878 }
 879
 880 #define __vlv_read(x) \
 881 static u##x \
 882 vlv_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
 883         enum forcewake_domains fw_engine; \
 884         GEN6_READ_HEADER(x); \
 885         fw_engine = __vlv_reg_read_fw_domains(offset); \
 886         if (fw_engine) \
 887                 __force_wake_auto(dev_priv, fw_engine); \
 888         val = __raw_i915_read##x(dev_priv, reg); \
 889         GEN6_READ_FOOTER; \
 890 }
 891
 892 #define __chv_read(x) \
 893 static u##x \
 894 chv_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
 895         enum forcewake_domains fw_engine; \
 896         GEN6_READ_HEADER(x); \
 897         fw_engine = __chv_reg_read_fw_domains(offset); \
 898         if (fw_engine) \
 899                 __force_wake_auto(dev_priv, fw_engine); \
 900         val = __raw_i915_read##x(dev_priv, reg); \
 901         GEN6_READ_FOOTER; \
 902 }
 903
 904 #define __gen9_read(x) \
 905 static u##x \
 906 gen9_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
 907         enum forcewake_domains fw_engine; \
 908         GEN6_READ_HEADER(x); \
 909         fw_engine = __gen9_reg_read_fw_domains(offset); \
 910         if (fw_engine) \
 911                 __force_wake_auto(dev_priv, fw_engine); \
 912         val = __raw_i915_read##x(dev_priv, reg); \
 913         GEN6_READ_FOOTER; \
 914 }
 915
 916 __gen9_read(8)
 917 __gen9_read(16)
 918 __gen9_read(32)
 919 __gen9_read(64)
 920 __chv_read(8)
 921 __chv_read(16)
 922 __chv_read(32)
 923 __chv_read(64)
 924 __vlv_read(8)
 925 __vlv_read(16)
 926 __vlv_read(32)
 927 __vlv_read(64)
 928 __gen6_read(8)
 929 __gen6_read(16)
 930 __gen6_read(32)
 931 __gen6_read(64)
 932
 933 #undef __gen9_read
 934 #undef __chv_read
 935 #undef __vlv_read
 936 #undef __gen6_read
 937 #undef GEN6_READ_FOOTER
 938 #undef GEN6_READ_HEADER
 939
 940 #define VGPU_READ_HEADER(x) \
 941         unsigned long irqflags; \
 942         u##x val = 0; \
 943         assert_rpm_device_not_suspended(dev_priv); \
 944         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
 945
 946 #define VGPU_READ_FOOTER \
 947         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
 948         trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
 949         return val
 950
 951 #define __vgpu_read(x) \
 952 static u##x \
 953 vgpu_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
 954         VGPU_READ_HEADER(x); \
 955         val = __raw_i915_read##x(dev_priv, reg); \
 956         VGPU_READ_FOOTER; \
 957 }
 958
 959 __vgpu_read(8)
 960 __vgpu_read(16)
 961 __vgpu_read(32)
 962 __vgpu_read(64)
 963
 964 #undef __vgpu_read
 965 #undef VGPU_READ_FOOTER
 966 #undef VGPU_READ_HEADER
 967
 968 #define GEN2_WRITE_HEADER \
 969         trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
 970         assert_rpm_wakelock_held(dev_priv); \
 971
 972 #define GEN2_WRITE_FOOTER
 973
 974 #define __gen2_write(x) \
 975 static void \
 976 gen2_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
 977         GEN2_WRITE_HEADER; \
 978         __raw_i915_write##x(dev_priv, reg, val); \
 979         GEN2_WRITE_FOOTER; \
 980 }
 981
 982 #define __gen5_write(x) \
 983 static void \
 984 gen5_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
 985         GEN2_WRITE_HEADER; \
 986         ilk_dummy_write(dev_priv); \
 987         __raw_i915_write##x(dev_priv, reg, val); \
 988         GEN2_WRITE_FOOTER; \
 989 }
 990
 991 __gen5_write(8)
 992 __gen5_write(16)
 993 __gen5_write(32)
 994 __gen5_write(64)
 995 __gen2_write(8)
 996 __gen2_write(16)
 997 __gen2_write(32)
 998 __gen2_write(64)
 999
1000 #undef __gen5_write
1001 #undef __gen2_write
1002
1003 #undef GEN2_WRITE_FOOTER
1004 #undef GEN2_WRITE_HEADER
1005
1006 #define GEN6_WRITE_HEADER \
1007         u32 offset = i915_mmio_reg_offset(reg); \
1008         unsigned long irqflags; \
1009         trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
1010         assert_rpm_wakelock_held(dev_priv); \
1011         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); \
1012         unclaimed_reg_debug(dev_priv, reg, false, true)
1013
1014 #define GEN6_WRITE_FOOTER \
1015         unclaimed_reg_debug(dev_priv, reg, false, false); \
1016         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags)
1017
1018 #define __gen6_write(x) \
1019 static void \
1020 gen6_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
1021         u32 __fifo_ret = 0; \
1022         GEN6_WRITE_HEADER; \
1023         if (NEEDS_FORCE_WAKE(offset)) { \
1024                 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
1025         } \
1026         __raw_i915_write##x(dev_priv, reg, val); \
1027         if (unlikely(__fifo_ret)) { \
1028                 gen6_gt_check_fifodbg(dev_priv); \
1029         } \
1030         GEN6_WRITE_FOOTER; \
1031 }
1032
1033 #define __hsw_write(x) \
1034 static void \
1035 hsw_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
1036         u32 __fifo_ret = 0; \
1037         GEN6_WRITE_HEADER; \
1038         if (NEEDS_FORCE_WAKE(offset)) { \
1039                 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
1040         } \
1041         __raw_i915_write##x(dev_priv, reg, val); \
1042         if (unlikely(__fifo_ret)) { \
1043                 gen6_gt_check_fifodbg(dev_priv); \
1044         } \
1045         GEN6_WRITE_FOOTER; \
1046 }
1047
1048 #define __gen8_write(x) \
1049 static void \
1050 gen8_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
1051         enum forcewake_domains fw_engine; \
1052         GEN6_WRITE_HEADER; \
1053         fw_engine = __gen8_reg_write_fw_domains(offset); \
1054         if (fw_engine) \
1055                 __force_wake_auto(dev_priv, fw_engine); \
1056         __raw_i915_write##x(dev_priv, reg, val); \
1057         GEN6_WRITE_FOOTER; \
1058 }
1059
1060 #define __chv_write(x) \
1061 static void \
1062 chv_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
1063         enum forcewake_domains fw_engine; \
1064         GEN6_WRITE_HEADER; \
1065         fw_engine = __chv_reg_write_fw_domains(offset); \
1066         if (fw_engine) \
1067                 __force_wake_auto(dev_priv, fw_engine); \
1068         __raw_i915_write##x(dev_priv, reg, val); \
1069         GEN6_WRITE_FOOTER; \
1070 }
1071
1072 #define __gen9_write(x) \
1073 static void \
1074 gen9_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, \
1075                 bool trace) { \
1076         enum forcewake_domains fw_engine; \
1077         GEN6_WRITE_HEADER; \
1078         fw_engine = __gen9_reg_write_fw_domains(offset); \
1079         if (fw_engine) \
1080                 __force_wake_auto(dev_priv, fw_engine); \
1081         __raw_i915_write##x(dev_priv, reg, val); \
1082         GEN6_WRITE_FOOTER; \
1083 }
1084
1085 __gen9_write(8)
1086 __gen9_write(16)
1087 __gen9_write(32)
1088 __gen9_write(64)
1089 __chv_write(8)
1090 __chv_write(16)
1091 __chv_write(32)
1092 __chv_write(64)
1093 __gen8_write(8)
1094 __gen8_write(16)
1095 __gen8_write(32)
1096 __gen8_write(64)
1097 __hsw_write(8)
1098 __hsw_write(16)
1099 __hsw_write(32)
1100 __hsw_write(64)
1101 __gen6_write(8)
1102 __gen6_write(16)
1103 __gen6_write(32)
1104 __gen6_write(64)
1105
1106 #undef __gen9_write
1107 #undef __chv_write
1108 #undef __gen8_write
1109 #undef __hsw_write
1110 #undef __gen6_write
1111 #undef GEN6_WRITE_FOOTER
1112 #undef GEN6_WRITE_HEADER
1113
1114 #define VGPU_WRITE_HEADER \
1115         unsigned long irqflags; \
1116         trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
1117         assert_rpm_device_not_suspended(dev_priv); \
1118         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
1119
1120 #define VGPU_WRITE_FOOTER \
1121         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags)
1122
1123 #define __vgpu_write(x) \
1124 static void vgpu_write##x(struct drm_i915_private *dev_priv, \
1125                           i915_reg_t reg, u##x val, bool trace) { \
1126         VGPU_WRITE_HEADER; \
1127         __raw_i915_write##x(dev_priv, reg, val); \
1128         VGPU_WRITE_FOOTER; \
1129 }
1130
1131 __vgpu_write(8)
1132 __vgpu_write(16)
1133 __vgpu_write(32)
1134 __vgpu_write(64)
1135
1136 #undef __vgpu_write
1137 #undef VGPU_WRITE_FOOTER
1138 #undef VGPU_WRITE_HEADER
1139
1140 #define ASSIGN_WRITE_MMIO_VFUNCS(x) \
1141 do { \
1142         dev_priv->uncore.funcs.mmio_writeb = x##_write8; \
1143         dev_priv->uncore.funcs.mmio_writew = x##_write16; \
1144         dev_priv->uncore.funcs.mmio_writel = x##_write32; \
1145         dev_priv->uncore.funcs.mmio_writeq = x##_write64; \
1146 } while (0)
1147
1148 #define ASSIGN_READ_MMIO_VFUNCS(x) \
1149 do { \
1150         dev_priv->uncore.funcs.mmio_readb = x##_read8; \
1151         dev_priv->uncore.funcs.mmio_readw = x##_read16; \
1152         dev_priv->uncore.funcs.mmio_readl = x##_read32; \
1153         dev_priv->uncore.funcs.mmio_readq = x##_read64; \
1154 } while (0)
1155
1156
1157 static void fw_domain_init(struct drm_i915_private *dev_priv,
1158                            enum forcewake_domain_id domain_id,
1159                            i915_reg_t reg_set,
1160                            i915_reg_t reg_ack)
1161 {
1162         struct intel_uncore_forcewake_domain *d;
1163
1164         if (WARN_ON(domain_id >= FW_DOMAIN_ID_COUNT))
1165                 return;
1166
1167         d = &dev_priv->uncore.fw_domain[domain_id];
1168
1169         WARN_ON(d->wake_count);
1170
1171         d->wake_count = 0;
1172         d->reg_set = reg_set;
1173         d->reg_ack = reg_ack;
1174
1175         if (IS_GEN6(dev_priv)) {
1176                 d->val_reset = 0;
1177                 d->val_set = FORCEWAKE_KERNEL;
1178                 d->val_clear = 0;
1179         } else {
1180                 /* WaRsClearFWBitsAtReset:bdw,skl */
1181                 d->val_reset = _MASKED_BIT_DISABLE(0xffff);
1182                 d->val_set = _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL);
1183                 d->val_clear = _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL);
1184         }
1185
1186         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1187                 d->reg_post = FORCEWAKE_ACK_VLV;
1188         else if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv) || IS_GEN8(dev_priv))
1189                 d->reg_post = ECOBUS;
1190
1191         d->i915 = dev_priv;
1192         d->id = domain_id;
1193
1194         BUILD_BUG_ON(FORCEWAKE_RENDER != (1 << FW_DOMAIN_ID_RENDER));
1195         BUILD_BUG_ON(FORCEWAKE_BLITTER != (1 << FW_DOMAIN_ID_BLITTER));
1196         BUILD_BUG_ON(FORCEWAKE_MEDIA != (1 << FW_DOMAIN_ID_MEDIA));
1197
1198         d->mask = 1 << domain_id;
1199
1200         hrtimer_init(&d->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
1201         d->timer.function = intel_uncore_fw_release_timer;
1202
1203         dev_priv->uncore.fw_domains |= (1 << domain_id);
1204
1205         fw_domain_reset(d);
1206 }
1207
1208 static void intel_uncore_fw_domains_init(struct drm_device *dev)
1209 {
1210         struct drm_i915_private *dev_priv = dev->dev_private;
1211
1212         if (INTEL_INFO(dev_priv)->gen <= 5)
1213                 return;
1214
1215         if (IS_GEN9(dev)) {
1216                 dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
1217                 dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
1218                 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1219                                FORCEWAKE_RENDER_GEN9,
1220                                FORCEWAKE_ACK_RENDER_GEN9);
1221                 fw_domain_init(dev_priv, FW_DOMAIN_ID_BLITTER,
1222                                FORCEWAKE_BLITTER_GEN9,
1223                                FORCEWAKE_ACK_BLITTER_GEN9);
1224                 fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA,
1225                                FORCEWAKE_MEDIA_GEN9, FORCEWAKE_ACK_MEDIA_GEN9);
1226         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1227                 dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
1228                 if (!IS_CHERRYVIEW(dev))
1229                         dev_priv->uncore.funcs.force_wake_put =
1230                                 fw_domains_put_with_fifo;
1231                 else
1232                         dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
1233                 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1234                                FORCEWAKE_VLV, FORCEWAKE_ACK_VLV);
1235                 fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA,
1236                                FORCEWAKE_MEDIA_VLV, FORCEWAKE_ACK_MEDIA_VLV);
1237         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1238                 dev_priv->uncore.funcs.force_wake_get =
1239                         fw_domains_get_with_thread_status;
1240                 dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
1241                 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1242                                FORCEWAKE_MT, FORCEWAKE_ACK_HSW);
1243         } else if (IS_IVYBRIDGE(dev)) {
1244                 u32 ecobus;
1245
1246                 /* IVB configs may use multi-threaded forcewake */
1247
1248                 /* A small trick here - if the bios hasn't configured
1249                  * MT forcewake, and if the device is in RC6, then
1250                  * force_wake_mt_get will not wake the device and the
1251                  * ECOBUS read will return zero. Which will be
1252                  * (correctly) interpreted by the test below as MT
1253                  * forcewake being disabled.
1254                  */
1255                 dev_priv->uncore.funcs.force_wake_get =
1256                         fw_domains_get_with_thread_status;
1257                 dev_priv->uncore.funcs.force_wake_put =
1258                         fw_domains_put_with_fifo;
1259
1260                 /* We need to init first for ECOBUS access and then
1261                  * determine later if we want to reinit, in case of MT access is
1262                  * not working. In this stage we don't know which flavour this
1263                  * ivb is, so it is better to reset also the gen6 fw registers
1264                  * before the ecobus check.
1265                  */
1266
1267                 __raw_i915_write32(dev_priv, FORCEWAKE, 0);
1268                 __raw_posting_read(dev_priv, ECOBUS);
1269
1270                 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1271                                FORCEWAKE_MT, FORCEWAKE_MT_ACK);
1272
1273                 mutex_lock(&dev->struct_mutex);
1274                 fw_domains_get_with_thread_status(dev_priv, FORCEWAKE_ALL);
1275                 ecobus = __raw_i915_read32(dev_priv, ECOBUS);
1276                 fw_domains_put_with_fifo(dev_priv, FORCEWAKE_ALL);
1277                 mutex_unlock(&dev->struct_mutex);
1278
1279                 if (!(ecobus & FORCEWAKE_MT_ENABLE)) {
1280                         DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n");
1281                         DRM_INFO("when using vblank-synced partial screen updates.\n");
1282                         fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1283                                        FORCEWAKE, FORCEWAKE_ACK);
1284                 }
1285         } else if (IS_GEN6(dev)) {
1286                 dev_priv->uncore.funcs.force_wake_get =
1287                         fw_domains_get_with_thread_status;
1288                 dev_priv->uncore.funcs.force_wake_put =
1289                         fw_domains_put_with_fifo;
1290                 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1291                                FORCEWAKE, FORCEWAKE_ACK);
1292         }
1293
1294         /* All future platforms are expected to require complex power gating */
1295         WARN_ON(dev_priv->uncore.fw_domains == 0);
1296 }
1297
1298 void intel_uncore_init(struct drm_device *dev)
1299 {
1300         struct drm_i915_private *dev_priv = dev->dev_private;
1301
1302         i915_check_vgpu(dev);
1303
1304         intel_uncore_ellc_detect(dev);
1305         intel_uncore_fw_domains_init(dev);
1306         __intel_uncore_early_sanitize(dev, false);
1307
1308         dev_priv->uncore.unclaimed_mmio_check = 1;
1309
1310         switch (INTEL_INFO(dev)->gen) {
1311         default:
1312         case 9:
1313                 ASSIGN_WRITE_MMIO_VFUNCS(gen9);
1314                 ASSIGN_READ_MMIO_VFUNCS(gen9);
1315                 break;
1316         case 8:
1317                 if (IS_CHERRYVIEW(dev)) {
1318                         ASSIGN_WRITE_MMIO_VFUNCS(chv);
1319                         ASSIGN_READ_MMIO_VFUNCS(chv);
1320
1321                 } else {
1322                         ASSIGN_WRITE_MMIO_VFUNCS(gen8);
1323                         ASSIGN_READ_MMIO_VFUNCS(gen6);
1324                 }
1325                 break;
1326         case 7:
1327         case 6:
1328                 if (IS_HASWELL(dev)) {
1329                         ASSIGN_WRITE_MMIO_VFUNCS(hsw);
1330                 } else {
1331                         ASSIGN_WRITE_MMIO_VFUNCS(gen6);
1332                 }
1333
1334                 if (IS_VALLEYVIEW(dev)) {
1335                         ASSIGN_READ_MMIO_VFUNCS(vlv);
1336                 } else {
1337                         ASSIGN_READ_MMIO_VFUNCS(gen6);
1338                 }
1339                 break;
1340         case 5:
1341                 ASSIGN_WRITE_MMIO_VFUNCS(gen5);
1342                 ASSIGN_READ_MMIO_VFUNCS(gen5);
1343                 break;
1344         case 4:
1345         case 3:
1346         case 2:
1347                 ASSIGN_WRITE_MMIO_VFUNCS(gen2);
1348                 ASSIGN_READ_MMIO_VFUNCS(gen2);
1349                 break;
1350         }
1351
1352         if (intel_vgpu_active(dev)) {
1353                 ASSIGN_WRITE_MMIO_VFUNCS(vgpu);
1354                 ASSIGN_READ_MMIO_VFUNCS(vgpu);
1355         }
1356
1357         i915_check_and_clear_faults(dev);
1358 }
1359 #undef ASSIGN_WRITE_MMIO_VFUNCS
1360 #undef ASSIGN_READ_MMIO_VFUNCS
1361
1362 void intel_uncore_fini(struct drm_device *dev)
1363 {
1364         /* Paranoia: make sure we have disabled everything before we exit. */
1365         intel_uncore_sanitize(dev);
1366         intel_uncore_forcewake_reset(dev, false);
1367 }
1368
1369 #define GEN_RANGE(l, h) GENMASK(h, l)
1370
1371 static const struct register_whitelist {
1372         i915_reg_t offset_ldw, offset_udw;
1373         uint32_t size;
1374         /* supported gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
1375         uint32_t gen_bitmask;
1376 } whitelist[] = {
1377         { .offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE),
1378           .offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE),
1379           .size = 8, .gen_bitmask = GEN_RANGE(4, 9) },
1380 };
1381
1382 int i915_reg_read_ioctl(struct drm_device *dev,
1383                         void *data, struct drm_file *file)
1384 {
1385         struct drm_i915_private *dev_priv = dev->dev_private;
1386         struct drm_i915_reg_read *reg = data;
1387         struct register_whitelist const *entry = whitelist;
1388         unsigned size;
1389         i915_reg_t offset_ldw, offset_udw;
1390         int i, ret = 0;
1391
1392         for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) {
1393                 if (i915_mmio_reg_offset(entry->offset_ldw) == (reg->offset & -entry->size) &&
1394                     (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask))
1395                         break;
1396         }
1397
1398         if (i == ARRAY_SIZE(whitelist))
1399                 return -EINVAL;
1400
1401         /* We use the low bits to encode extra flags as the register should
1402          * be naturally aligned (and those that are not so aligned merely
1403          * limit the available flags for that register).
1404          */
1405         offset_ldw = entry->offset_ldw;
1406         offset_udw = entry->offset_udw;
1407         size = entry->size;
1408         size |= reg->offset ^ i915_mmio_reg_offset(offset_ldw);
1409
1410         intel_runtime_pm_get(dev_priv);
1411
1412         switch (size) {
1413         case 8 | 1:
1414                 reg->val = I915_READ64_2x32(offset_ldw, offset_udw);
1415                 break;
1416         case 8:
1417                 reg->val = I915_READ64(offset_ldw);
1418                 break;
1419         case 4:
1420                 reg->val = I915_READ(offset_ldw);
1421                 break;
1422         case 2:
1423                 reg->val = I915_READ16(offset_ldw);
1424                 break;
1425         case 1:
1426                 reg->val = I915_READ8(offset_ldw);
1427                 break;
1428         default:
1429                 ret = -EINVAL;
1430                 goto out;
1431         }
1432
1433 out:
1434         intel_runtime_pm_put(dev_priv);
1435         return ret;
1436 }
1437
1438 int i915_get_reset_stats_ioctl(struct drm_device *dev,
1439                                void *data, struct drm_file *file)
1440 {
1441         struct drm_i915_private *dev_priv = dev->dev_private;
1442         struct drm_i915_reset_stats *args = data;
1443         struct i915_ctx_hang_stats *hs;
1444         struct intel_context *ctx;
1445         int ret;
1446
1447         if (args->flags || args->pad)
1448                 return -EINVAL;
1449
1450         if (args->ctx_id == DEFAULT_CONTEXT_HANDLE && !capable(CAP_SYS_ADMIN))
1451                 return -EPERM;
1452
1453         ret = mutex_lock_interruptible(&dev->struct_mutex);
1454         if (ret)
1455                 return ret;
1456
1457         ctx = i915_gem_context_get(file->driver_priv, args->ctx_id);
1458         if (IS_ERR(ctx)) {
1459                 mutex_unlock(&dev->struct_mutex);
1460                 return PTR_ERR(ctx);
1461         }
1462         hs = &ctx->hang_stats;
1463
1464         if (capable(CAP_SYS_ADMIN))
1465                 args->reset_count = i915_reset_count(&dev_priv->gpu_error);
1466         else
1467                 args->reset_count = 0;
1468
1469         args->batch_active = hs->batch_active;
1470         args->batch_pending = hs->batch_pending;
1471
1472         mutex_unlock(&dev->struct_mutex);
1473
1474         return 0;
1475 }
1476
1477 static int i915_reset_complete(struct drm_device *dev)
1478 {
1479         u8 gdrst;
1480         pci_read_config_byte(dev->pdev, I915_GDRST, &gdrst);
1481         return (gdrst & GRDOM_RESET_STATUS) == 0;
1482 }
1483
1484 static int i915_do_reset(struct drm_device *dev, unsigned engine_mask)
1485 {
1486         /* assert reset for at least 20 usec */
1487         pci_write_config_byte(dev->pdev, I915_GDRST, GRDOM_RESET_ENABLE);
1488         udelay(20);
1489         pci_write_config_byte(dev->pdev, I915_GDRST, 0);
1490
1491         return wait_for(i915_reset_complete(dev), 500);
1492 }
1493
1494 static int g4x_reset_complete(struct drm_device *dev)
1495 {
1496         u8 gdrst;
1497         pci_read_config_byte(dev->pdev, I915_GDRST, &gdrst);
1498         return (gdrst & GRDOM_RESET_ENABLE) == 0;
1499 }
1500
1501 static int g33_do_reset(struct drm_device *dev, unsigned engine_mask)
1502 {
1503         pci_write_config_byte(dev->pdev, I915_GDRST, GRDOM_RESET_ENABLE);
1504         return wait_for(g4x_reset_complete(dev), 500);
1505 }
1506
1507 static int g4x_do_reset(struct drm_device *dev, unsigned engine_mask)
1508 {
1509         struct drm_i915_private *dev_priv = dev->dev_private;
1510         int ret;
1511
1512         pci_write_config_byte(dev->pdev, I915_GDRST,
1513                               GRDOM_RENDER | GRDOM_RESET_ENABLE);
1514         ret =  wait_for(g4x_reset_complete(dev), 500);
1515         if (ret)
1516                 return ret;
1517
1518         /* WaVcpClkGateDisableForMediaReset:ctg,elk */
1519         I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) | VCP_UNIT_CLOCK_GATE_DISABLE);
1520         POSTING_READ(VDECCLK_GATE_D);
1521
1522         pci_write_config_byte(dev->pdev, I915_GDRST,
1523                               GRDOM_MEDIA | GRDOM_RESET_ENABLE);
1524         ret =  wait_for(g4x_reset_complete(dev), 500);
1525         if (ret)
1526                 return ret;
1527
1528         /* WaVcpClkGateDisableForMediaReset:ctg,elk */
1529         I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) & ~VCP_UNIT_CLOCK_GATE_DISABLE);
1530         POSTING_READ(VDECCLK_GATE_D);
1531
1532         pci_write_config_byte(dev->pdev, I915_GDRST, 0);
1533
1534         return 0;
1535 }
1536
1537 static int ironlake_do_reset(struct drm_device *dev, unsigned engine_mask)
1538 {
1539         struct drm_i915_private *dev_priv = dev->dev_private;
1540         int ret;
1541
1542         I915_WRITE(ILK_GDSR,
1543                    ILK_GRDOM_RENDER | ILK_GRDOM_RESET_ENABLE);
1544         ret = wait_for((I915_READ(ILK_GDSR) &
1545                         ILK_GRDOM_RESET_ENABLE) == 0, 500);
1546         if (ret)
1547                 return ret;
1548
1549         I915_WRITE(ILK_GDSR,
1550                    ILK_GRDOM_MEDIA | ILK_GRDOM_RESET_ENABLE);
1551         ret = wait_for((I915_READ(ILK_GDSR) &
1552                         ILK_GRDOM_RESET_ENABLE) == 0, 500);
1553         if (ret)
1554                 return ret;
1555
1556         I915_WRITE(ILK_GDSR, 0);
1557
1558         return 0;
1559 }
1560
1561 /* Reset the hardware domains (GENX_GRDOM_*) specified by mask */
1562 static int gen6_hw_domain_reset(struct drm_i915_private *dev_priv,
1563                                 u32 hw_domain_mask)
1564 {
1565         int ret;
1566
1567         /* GEN6_GDRST is not in the gt power well, no need to check
1568          * for fifo space for the write or forcewake the chip for
1569          * the read
1570          */
1571         __raw_i915_write32(dev_priv, GEN6_GDRST, hw_domain_mask);
1572
1573 #define ACKED ((__raw_i915_read32(dev_priv, GEN6_GDRST) & hw_domain_mask) == 0)
1574         /* Spin waiting for the device to ack the reset requests */
1575         ret = wait_for(ACKED, 500);
1576 #undef ACKED
1577
1578         return ret;
1579 }
1580
1581 /**
1582  * gen6_reset_engines - reset individual engines
1583  * @dev: DRM device
1584  * @engine_mask: mask of intel_ring_flag() engines or ALL_ENGINES for full reset
1585  *
1586  * This function will reset the individual engines that are set in engine_mask.
1587  * If you provide ALL_ENGINES as mask, full global domain reset will be issued.
1588  *
1589  * Note: It is responsibility of the caller to handle the difference between
1590  * asking full domain reset versus reset for all available individual engines.
1591  *
1592  * Returns 0 on success, nonzero on error.
1593  */
1594 static int gen6_reset_engines(struct drm_device *dev, unsigned engine_mask)
1595 {
1596         struct drm_i915_private *dev_priv = dev->dev_private;
1597         struct intel_engine_cs *engine;
1598         const u32 hw_engine_mask[I915_NUM_ENGINES] = {
1599                 [RCS] = GEN6_GRDOM_RENDER,
1600                 [BCS] = GEN6_GRDOM_BLT,
1601                 [VCS] = GEN6_GRDOM_MEDIA,
1602                 [VCS2] = GEN8_GRDOM_MEDIA2,
1603                 [VECS] = GEN6_GRDOM_VECS,
1604         };
1605         u32 hw_mask;
1606         int ret;
1607
1608         if (engine_mask == ALL_ENGINES) {
1609                 hw_mask = GEN6_GRDOM_FULL;
1610         } else {
1611                 hw_mask = 0;
1612                 for_each_engine_masked(engine, dev_priv, engine_mask)
1613                         hw_mask |= hw_engine_mask[engine->id];
1614         }
1615
1616         ret = gen6_hw_domain_reset(dev_priv, hw_mask);
1617
1618         intel_uncore_forcewake_reset(dev, true);
1619
1620         return ret;
1621 }
1622
1623 static int wait_for_register_fw(struct drm_i915_private *dev_priv,
1624                                 i915_reg_t reg,
1625                                 const u32 mask,
1626                                 const u32 value,
1627                                 const unsigned long timeout_ms)
1628 {
1629         return wait_for((I915_READ_FW(reg) & mask) == value, timeout_ms);
1630 }
1631
1632 static int gen8_request_engine_reset(struct intel_engine_cs *engine)
1633 {
1634         int ret;
1635         struct drm_i915_private *dev_priv = engine->dev->dev_private;
1636
1637         I915_WRITE_FW(RING_RESET_CTL(engine->mmio_base),
1638                       _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET));
1639
1640         ret = wait_for_register_fw(dev_priv,
1641                                    RING_RESET_CTL(engine->mmio_base),
1642                                    RESET_CTL_READY_TO_RESET,
1643                                    RESET_CTL_READY_TO_RESET,
1644                                    700);
1645         if (ret)
1646                 DRM_ERROR("%s: reset request timeout\n", engine->name);
1647
1648         return ret;
1649 }
1650
1651 static void gen8_unrequest_engine_reset(struct intel_engine_cs *engine)
1652 {
1653         struct drm_i915_private *dev_priv = engine->dev->dev_private;
1654
1655         I915_WRITE_FW(RING_RESET_CTL(engine->mmio_base),
1656                       _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET));
1657 }
1658
1659 static int gen8_reset_engines(struct drm_device *dev, unsigned engine_mask)
1660 {
1661         struct drm_i915_private *dev_priv = dev->dev_private;
1662         struct intel_engine_cs *engine;
1663
1664         for_each_engine_masked(engine, dev_priv, engine_mask)
1665                 if (gen8_request_engine_reset(engine))
1666                         goto not_ready;
1667
1668         return gen6_reset_engines(dev, engine_mask);
1669
1670 not_ready:
1671         for_each_engine_masked(engine, dev_priv, engine_mask)
1672                 gen8_unrequest_engine_reset(engine);
1673
1674         return -EIO;
1675 }
1676
1677 static int (*intel_get_gpu_reset(struct drm_device *dev))(struct drm_device *,
1678                                                           unsigned engine_mask)
1679 {
1680         if (!i915.reset)
1681                 return NULL;
1682
1683         if (INTEL_INFO(dev)->gen >= 8)
1684                 return gen8_reset_engines;
1685         else if (INTEL_INFO(dev)->gen >= 6)
1686                 return gen6_reset_engines;
1687         else if (IS_GEN5(dev))
1688                 return ironlake_do_reset;
1689         else if (IS_G4X(dev))
1690                 return g4x_do_reset;
1691         else if (IS_G33(dev))
1692                 return g33_do_reset;
1693         else if (INTEL_INFO(dev)->gen >= 3)
1694                 return i915_do_reset;
1695         else
1696                 return NULL;
1697 }
1698
1699 int intel_gpu_reset(struct drm_device *dev, unsigned engine_mask)
1700 {
1701         struct drm_i915_private *dev_priv = to_i915(dev);
1702         int (*reset)(struct drm_device *, unsigned);
1703         int ret;
1704
1705         reset = intel_get_gpu_reset(dev);
1706         if (reset == NULL)
1707                 return -ENODEV;
1708
1709         /* If the power well sleeps during the reset, the reset
1710          * request may be dropped and never completes (causing -EIO).
1711          */
1712         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1713         ret = reset(dev, engine_mask);
1714         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1715
1716         return ret;
1717 }
1718
1719 bool intel_has_gpu_reset(struct drm_device *dev)
1720 {
1721         return intel_get_gpu_reset(dev) != NULL;
1722 }
1723
1724 int intel_guc_reset(struct drm_i915_private *dev_priv)
1725 {
1726         int ret;
1727         unsigned long irqflags;
1728
1729         if (!i915.enable_guc_submission)
1730                 return -EINVAL;
1731
1732         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1733         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
1734
1735         ret = gen6_hw_domain_reset(dev_priv, GEN9_GRDOM_GUC);
1736
1737         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
1738         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1739
1740         return ret;
1741 }
1742
1743 bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv)
1744 {
1745         return check_for_unclaimed_mmio(dev_priv);
1746 }
1747
1748 bool
1749 intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv)
1750 {
1751         if (unlikely(i915.mmio_debug ||
1752                      dev_priv->uncore.unclaimed_mmio_check <= 0))
1753                 return false;
1754
1755         if (unlikely(intel_uncore_unclaimed_mmio(dev_priv))) {
1756                 DRM_DEBUG("Unclaimed register detected, "
1757                           "enabling oneshot unclaimed register reporting. "
1758                           "Please use i915.mmio_debug=N for more information.\n");
1759                 i915.mmio_debug++;
1760                 dev_priv->uncore.unclaimed_mmio_check--;
1761                 return true;
1762         }
1763
1764         return false;
1765 }
1766
1767 static enum forcewake_domains
1768 intel_uncore_forcewake_for_read(struct drm_i915_private *dev_priv,
1769                                 i915_reg_t reg)
1770 {
1771         enum forcewake_domains fw_domains;
1772
1773         if (intel_vgpu_active(dev_priv->dev))
1774                 return 0;
1775
1776         switch (INTEL_INFO(dev_priv)->gen) {
1777         case 9:
1778                 fw_domains = __gen9_reg_read_fw_domains(i915_mmio_reg_offset(reg));
1779                 break;
1780         case 8:
1781                 if (IS_CHERRYVIEW(dev_priv))
1782                         fw_domains = __chv_reg_read_fw_domains(i915_mmio_reg_offset(reg));
1783                 else
1784                         fw_domains = __gen6_reg_read_fw_domains(i915_mmio_reg_offset(reg));
1785                 break;
1786         case 7:
1787         case 6:
1788                 if (IS_VALLEYVIEW(dev_priv))
1789                         fw_domains = __vlv_reg_read_fw_domains(i915_mmio_reg_offset(reg));
1790                 else
1791                         fw_domains = __gen6_reg_read_fw_domains(i915_mmio_reg_offset(reg));
1792                 break;
1793         default:
1794                 MISSING_CASE(INTEL_INFO(dev_priv)->gen);
1795         case 5: /* forcewake was introduced with gen6 */
1796         case 4:
1797         case 3:
1798         case 2:
1799                 return 0;
1800         }
1801
1802         WARN_ON(fw_domains & ~dev_priv->uncore.fw_domains);
1803
1804         return fw_domains;
1805 }
1806
1807 static enum forcewake_domains
1808 intel_uncore_forcewake_for_write(struct drm_i915_private *dev_priv,
1809                                  i915_reg_t reg)
1810 {
1811         enum forcewake_domains fw_domains;
1812
1813         if (intel_vgpu_active(dev_priv->dev))
1814                 return 0;
1815
1816         switch (INTEL_INFO(dev_priv)->gen) {
1817         case 9:
1818                 fw_domains = __gen9_reg_write_fw_domains(i915_mmio_reg_offset(reg));
1819                 break;
1820         case 8:
1821                 if (IS_CHERRYVIEW(dev_priv))
1822                         fw_domains = __chv_reg_write_fw_domains(i915_mmio_reg_offset(reg));
1823                 else
1824                         fw_domains = __gen8_reg_write_fw_domains(i915_mmio_reg_offset(reg));
1825                 break;
1826         case 7:
1827         case 6:
1828                 fw_domains = FORCEWAKE_RENDER;
1829                 break;
1830         default:
1831                 MISSING_CASE(INTEL_INFO(dev_priv)->gen);
1832         case 5:
1833         case 4:
1834         case 3:
1835         case 2:
1836                 return 0;
1837         }
1838
1839         WARN_ON(fw_domains & ~dev_priv->uncore.fw_domains);
1840
1841         return fw_domains;
1842 }
1843
1844 /**
1845  * intel_uncore_forcewake_for_reg - which forcewake domains are needed to access
1846  *                                  a register
1847  * @dev_priv: pointer to struct drm_i915_private
1848  * @reg: register in question
1849  * @op: operation bitmask of FW_REG_READ and/or FW_REG_WRITE
1850  *
1851  * Returns a set of forcewake domains required to be taken with for example
1852  * intel_uncore_forcewake_get for the specified register to be accessible in the
1853  * specified mode (read, write or read/write) with raw mmio accessors.
1854  *
1855  * NOTE: On Gen6 and Gen7 write forcewake domain (FORCEWAKE_RENDER) requires the
1856  * callers to do FIFO management on their own or risk losing writes.
1857  */
1858 enum forcewake_domains
1859 intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv,
1860                                i915_reg_t reg, unsigned int op)
1861 {
1862         enum forcewake_domains fw_domains = 0;
1863
1864         WARN_ON(!op);
1865
1866         if (op & FW_REG_READ)
1867                 fw_domains = intel_uncore_forcewake_for_read(dev_priv, reg);
1868
1869         if (op & FW_REG_WRITE)
1870                 fw_domains |= intel_uncore_forcewake_for_write(dev_priv, reg);
1871
1872         return fw_domains;
1873 }