drivers/gpu/drm/i915/intel_uncore.c

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "i915_drv.h"
  25 #include "intel_drv.h"
  26 #include "i915_vgpu.h"
  27
  28 #include <linux/pm_runtime.h>
  29
  30 #define FORCEWAKE_ACK_TIMEOUT_MS 2
  31
  32 #define __raw_i915_read8(dev_priv__, reg__) readb((dev_priv__)->regs + (reg__))
  33 #define __raw_i915_write8(dev_priv__, reg__, val__) writeb(val__, (dev_priv__)->regs + (reg__))
  34
  35 #define __raw_i915_read16(dev_priv__, reg__) readw((dev_priv__)->regs + (reg__))
  36 #define __raw_i915_write16(dev_priv__, reg__, val__) writew(val__, (dev_priv__)->regs + (reg__))
  37
  38 #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
  39 #define __raw_i915_write32(dev_priv__, reg__, val__) writel(val__, (dev_priv__)->regs + (reg__))
  40
  41 #define __raw_i915_read64(dev_priv__, reg__) readq((dev_priv__)->regs + (reg__))
  42 #define __raw_i915_write64(dev_priv__, reg__, val__) writeq(val__, (dev_priv__)->regs + (reg__))
  43
  44 #define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32(dev_priv__, reg__)
  45
  46 static const char * const forcewake_domain_names[] = {
  47         "render",
  48         "blitter",
  49         "media",
  50 };
  51
  52 const char *
  53 intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id)
  54 {
  55         BUILD_BUG_ON((sizeof(forcewake_domain_names)/sizeof(const char *)) !=
  56                      FW_DOMAIN_ID_COUNT);
  57
  58         if (id >= 0 && id < FW_DOMAIN_ID_COUNT)
  59                 return forcewake_domain_names[id];
  60
  61         WARN_ON(id);
  62
  63         return "unknown";
  64 }
  65
  66 static void
  67 assert_device_not_suspended(struct drm_i915_private *dev_priv)
  68 {
  69         WARN_ONCE(HAS_RUNTIME_PM(dev_priv->dev) && dev_priv->pm.suspended,
  70                   "Device suspended\n");
  71 }
  72
  73 static inline void
  74 fw_domain_reset(const struct intel_uncore_forcewake_domain *d)
  75 {
  76         WARN_ON(d->reg_set == 0);
  77         __raw_i915_write32(d->i915, d->reg_set, d->val_reset);
  78 }
  79
  80 static inline void
  81 fw_domain_arm_timer(struct intel_uncore_forcewake_domain *d)
  82 {
  83         mod_timer_pinned(&d->timer, jiffies + 1);
  84 }
  85
  86 static inline void
  87 fw_domain_wait_ack_clear(const struct intel_uncore_forcewake_domain *d)
  88 {
  89         if (wait_for_atomic((__raw_i915_read32(d->i915, d->reg_ack) &
  90                              FORCEWAKE_KERNEL) == 0,
  91                             FORCEWAKE_ACK_TIMEOUT_MS))
  92                 DRM_ERROR("%s: timed out waiting for forcewake ack to clear.\n",
  93                           intel_uncore_forcewake_domain_to_str(d->id));
  94 }
  95
  96 static inline void
  97 fw_domain_get(const struct intel_uncore_forcewake_domain *d)
  98 {
  99         __raw_i915_write32(d->i915, d->reg_set, d->val_set);
 100 }
 101
 102 static inline void
 103 fw_domain_wait_ack(const struct intel_uncore_forcewake_domain *d)
 104 {
 105         if (wait_for_atomic((__raw_i915_read32(d->i915, d->reg_ack) &
 106                              FORCEWAKE_KERNEL),
 107                             FORCEWAKE_ACK_TIMEOUT_MS))
 108                 DRM_ERROR("%s: timed out waiting for forcewake ack request.\n",
 109                           intel_uncore_forcewake_domain_to_str(d->id));
 110 }
 111
 112 static inline void
 113 fw_domain_put(const struct intel_uncore_forcewake_domain *d)
 114 {
 115         __raw_i915_write32(d->i915, d->reg_set, d->val_clear);
 116 }
 117
 118 static inline void
 119 fw_domain_posting_read(const struct intel_uncore_forcewake_domain *d)
 120 {
 121         /* something from same cacheline, but not from the set register */
 122         if (d->reg_post)
 123                 __raw_posting_read(d->i915, d->reg_post);
 124 }
 125
 126 static void
 127 fw_domains_get(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains)
 128 {
 129         struct intel_uncore_forcewake_domain *d;
 130         enum forcewake_domain_id id;
 131
 132         for_each_fw_domain_mask(d, fw_domains, dev_priv, id) {
 133                 fw_domain_wait_ack_clear(d);
 134                 fw_domain_get(d);
 135                 fw_domain_wait_ack(d);
 136         }
 137 }
 138
 139 static void
 140 fw_domains_put(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains)
 141 {
 142         struct intel_uncore_forcewake_domain *d;
 143         enum forcewake_domain_id id;
 144
 145         for_each_fw_domain_mask(d, fw_domains, dev_priv, id) {
 146                 fw_domain_put(d);
 147                 fw_domain_posting_read(d);
 148         }
 149 }
 150
 151 static void
 152 fw_domains_posting_read(struct drm_i915_private *dev_priv)
 153 {
 154         struct intel_uncore_forcewake_domain *d;
 155         enum forcewake_domain_id id;
 156
 157         /* No need to do for all, just do for first found */
 158         for_each_fw_domain(d, dev_priv, id) {
 159                 fw_domain_posting_read(d);
 160                 break;
 161         }
 162 }
 163
 164 static void
 165 fw_domains_reset(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains)
 166 {
 167         struct intel_uncore_forcewake_domain *d;
 168         enum forcewake_domain_id id;
 169
 170         WARN_ON(dev_priv->uncore.fw_domains == 0);
 171
 172         for_each_fw_domain_mask(d, fw_domains, dev_priv, id)
 173                 fw_domain_reset(d);
 174
 175         fw_domains_posting_read(dev_priv);
 176 }
 177
 178 static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
 179 {
 180         /* w/a for a sporadic read returning 0 by waiting for the GT
 181          * thread to wake up.
 182          */
 183         if (wait_for_atomic_us((__raw_i915_read32(dev_priv, GEN6_GT_THREAD_STATUS_REG) &
 184                                 GEN6_GT_THREAD_STATUS_CORE_MASK) == 0, 500))
 185                 DRM_ERROR("GT thread status wait timed out\n");
 186 }
 187
 188 static void fw_domains_get_with_thread_status(struct drm_i915_private *dev_priv,
 189                                               enum forcewake_domains fw_domains)
 190 {
 191         fw_domains_get(dev_priv, fw_domains);
 192
 193         /* WaRsForcewakeWaitTC0:snb,ivb,hsw,bdw,vlv */
 194         __gen6_gt_wait_for_thread_c0(dev_priv);
 195 }
 196
 197 static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
 198 {
 199         u32 gtfifodbg;
 200
 201         gtfifodbg = __raw_i915_read32(dev_priv, GTFIFODBG);
 202         if (WARN(gtfifodbg, "GT wake FIFO error 0x%x\n", gtfifodbg))
 203                 __raw_i915_write32(dev_priv, GTFIFODBG, gtfifodbg);
 204 }
 205
 206 static void fw_domains_put_with_fifo(struct drm_i915_private *dev_priv,
 207                                      enum forcewake_domains fw_domains)
 208 {
 209         fw_domains_put(dev_priv, fw_domains);
 210         gen6_gt_check_fifodbg(dev_priv);
 211 }
 212
 213 static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
 214 {
 215         int ret = 0;
 216
 217         /* On VLV, FIFO will be shared by both SW and HW.
 218          * So, we need to read the FREE_ENTRIES everytime */
 219         if (IS_VALLEYVIEW(dev_priv->dev))
 220                 dev_priv->uncore.fifo_count =
 221                         __raw_i915_read32(dev_priv, GTFIFOCTL) &
 222                                                 GT_FIFO_FREE_ENTRIES_MASK;
 223
 224         if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
 225                 int loop = 500;
 226                 u32 fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK;
 227                 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
 228                         udelay(10);
 229                         fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK;
 230                 }
 231                 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
 232                         ++ret;
 233                 dev_priv->uncore.fifo_count = fifo;
 234         }
 235         dev_priv->uncore.fifo_count--;
 236
 237         return ret;
 238 }
 239
 240 static void intel_uncore_fw_release_timer(unsigned long arg)
 241 {
 242         struct intel_uncore_forcewake_domain *domain = (void *)arg;
 243         unsigned long irqflags;
 244
 245         assert_device_not_suspended(domain->i915);
 246
 247         spin_lock_irqsave(&domain->i915->uncore.lock, irqflags);
 248         if (WARN_ON(domain->wake_count == 0))
 249                 domain->wake_count++;
 250
 251         if (--domain->wake_count == 0)
 252                 domain->i915->uncore.funcs.force_wake_put(domain->i915,
 253                                                           1 << domain->id);
 254
 255         spin_unlock_irqrestore(&domain->i915->uncore.lock, irqflags);
 256 }
 257
 258 void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore)
 259 {
 260         struct drm_i915_private *dev_priv = dev->dev_private;
 261         unsigned long irqflags;
 262         struct intel_uncore_forcewake_domain *domain;
 263         int retry_count = 100;
 264         enum forcewake_domain_id id;
 265         enum forcewake_domains fw = 0, active_domains;
 266
 267         /* Hold uncore.lock across reset to prevent any register access
 268          * with forcewake not set correctly. Wait until all pending
 269          * timers are run before holding.
 270          */
 271         while (1) {
 272                 active_domains = 0;
 273
 274                 for_each_fw_domain(domain, dev_priv, id) {
 275                         if (del_timer_sync(&domain->timer) == 0)
 276                                 continue;
 277
 278                         intel_uncore_fw_release_timer((unsigned long)domain);
 279                 }
 280
 281                 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 282
 283                 for_each_fw_domain(domain, dev_priv, id) {
 284                         if (timer_pending(&domain->timer))
 285                                 active_domains |= (1 << id);
 286                 }
 287
 288                 if (active_domains == 0)
 289                         break;
 290
 291                 if (--retry_count == 0) {
 292                         DRM_ERROR("Timed out waiting for forcewake timers to finish\n");
 293                         break;
 294                 }
 295
 296                 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 297                 cond_resched();
 298         }
 299
 300         WARN_ON(active_domains);
 301
 302         for_each_fw_domain(domain, dev_priv, id)
 303                 if (domain->wake_count)
 304                         fw |= 1 << id;
 305
 306         if (fw)
 307                 dev_priv->uncore.funcs.force_wake_put(dev_priv, fw);
 308
 309         fw_domains_reset(dev_priv, FORCEWAKE_ALL);
 310
 311         if (restore) { /* If reset with a user forcewake, try to restore */
 312                 if (fw)
 313                         dev_priv->uncore.funcs.force_wake_get(dev_priv, fw);
 314
 315                 if (IS_GEN6(dev) || IS_GEN7(dev))
 316                         dev_priv->uncore.fifo_count =
 317                                 __raw_i915_read32(dev_priv, GTFIFOCTL) &
 318                                 GT_FIFO_FREE_ENTRIES_MASK;
 319         }
 320
 321         if (!restore)
 322                 assert_forcewakes_inactive(dev_priv);
 323
 324         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 325 }
 326
 327 static void intel_uncore_ellc_detect(struct drm_device *dev)
 328 {
 329         struct drm_i915_private *dev_priv = dev->dev_private;
 330
 331         if ((IS_HASWELL(dev) || IS_BROADWELL(dev)) &&
 332             (__raw_i915_read32(dev_priv, HSW_EDRAM_PRESENT) & EDRAM_ENABLED)) {
 333                 /* The docs do not explain exactly how the calculation can be
 334                  * made. It is somewhat guessable, but for now, it's always
 335                  * 128MB.
 336                  * NB: We can't write IDICR yet because we do not have gt funcs
 337                  * set up */
 338                 dev_priv->ellc_size = 128;
 339                 DRM_INFO("Found %zuMB of eLLC\n", dev_priv->ellc_size);
 340         }
 341 }
 342
 343 static void __intel_uncore_early_sanitize(struct drm_device *dev,
 344                                           bool restore_forcewake)
 345 {
 346         struct drm_i915_private *dev_priv = dev->dev_private;
 347
 348         if (HAS_FPGA_DBG_UNCLAIMED(dev))
 349                 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
 350
 351         /* clear out old GT FIFO errors */
 352         if (IS_GEN6(dev) || IS_GEN7(dev))
 353                 __raw_i915_write32(dev_priv, GTFIFODBG,
 354                                    __raw_i915_read32(dev_priv, GTFIFODBG));
 355
 356         intel_uncore_forcewake_reset(dev, restore_forcewake);
 357 }
 358
 359 void intel_uncore_early_sanitize(struct drm_device *dev, bool restore_forcewake)
 360 {
 361         __intel_uncore_early_sanitize(dev, restore_forcewake);
 362         i915_check_and_clear_faults(dev);
 363 }
 364
 365 void intel_uncore_sanitize(struct drm_device *dev)
 366 {
 367         /* BIOS often leaves RC6 enabled, but disable it for hw init */
 368         intel_disable_gt_powersave(dev);
 369 }
 370
 371 /**
 372  * intel_uncore_forcewake_get - grab forcewake domain references
 373  * @dev_priv: i915 device instance
 374  * @fw_domains: forcewake domains to get reference on
 375  *
 376  * This function can be used get GT's forcewake domain references.
 377  * Normal register access will handle the forcewake domains automatically.
 378  * However if some sequence requires the GT to not power down a particular
 379  * forcewake domains this function should be called at the beginning of the
 380  * sequence. And subsequently the reference should be dropped by symmetric
 381  * call to intel_unforce_forcewake_put(). Usually caller wants all the domains
 382  * to be kept awake so the @fw_domains would be then FORCEWAKE_ALL.
 383  */
 384 void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
 385                                 enum forcewake_domains fw_domains)
 386 {
 387         unsigned long irqflags;
 388         struct intel_uncore_forcewake_domain *domain;
 389         enum forcewake_domain_id id;
 390
 391         if (!dev_priv->uncore.funcs.force_wake_get)
 392                 return;
 393
 394         WARN_ON(dev_priv->pm.suspended);
 395
 396         fw_domains &= dev_priv->uncore.fw_domains;
 397
 398         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 399
 400         for_each_fw_domain_mask(domain, fw_domains, dev_priv, id) {
 401                 if (domain->wake_count++)
 402                         fw_domains &= ~(1 << id);
 403         }
 404
 405         if (fw_domains)
 406                 dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains);
 407
 408         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 409 }
 410
 411 /**
 412  * intel_uncore_forcewake_put - release a forcewake domain reference
 413  * @dev_priv: i915 device instance
 414  * @fw_domains: forcewake domains to put references
 415  *
 416  * This function drops the device-level forcewakes for specified
 417  * domains obtained by intel_uncore_forcewake_get().
 418  */
 419 void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
 420                                 enum forcewake_domains fw_domains)
 421 {
 422         unsigned long irqflags;
 423         struct intel_uncore_forcewake_domain *domain;
 424         enum forcewake_domain_id id;
 425
 426         if (!dev_priv->uncore.funcs.force_wake_put)
 427                 return;
 428
 429         fw_domains &= dev_priv->uncore.fw_domains;
 430
 431         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 432
 433         for_each_fw_domain_mask(domain, fw_domains, dev_priv, id) {
 434                 if (WARN_ON(domain->wake_count == 0))
 435                         continue;
 436
 437                 if (--domain->wake_count)
 438                         continue;
 439
 440                 domain->wake_count++;
 441                 fw_domain_arm_timer(domain);
 442         }
 443
 444         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 445 }
 446
 447 void assert_forcewakes_inactive(struct drm_i915_private *dev_priv)
 448 {
 449         struct intel_uncore_forcewake_domain *domain;
 450         enum forcewake_domain_id id;
 451
 452         if (!dev_priv->uncore.funcs.force_wake_get)
 453                 return;
 454
 455         for_each_fw_domain(domain, dev_priv, id)
 456                 WARN_ON(domain->wake_count);
 457 }
 458
 459 /* We give fast paths for the really cool registers */
 460 #define NEEDS_FORCE_WAKE(dev_priv, reg) \
 461          ((reg) < 0x40000 && (reg) != FORCEWAKE)
 462
 463 #define REG_RANGE(reg, start, end) ((reg) >= (start) && (reg) < (end))
 464
 465 #define FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg) \
 466         (REG_RANGE((reg), 0x2000, 0x4000) || \
 467          REG_RANGE((reg), 0x5000, 0x8000) || \
 468          REG_RANGE((reg), 0xB000, 0x12000) || \
 469          REG_RANGE((reg), 0x2E000, 0x30000))
 470
 471 #define FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg) \
 472         (REG_RANGE((reg), 0x12000, 0x14000) || \
 473          REG_RANGE((reg), 0x22000, 0x24000) || \
 474          REG_RANGE((reg), 0x30000, 0x40000))
 475
 476 #define FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg) \
 477         (REG_RANGE((reg), 0x2000, 0x4000) || \
 478          REG_RANGE((reg), 0x5200, 0x8000) || \
 479          REG_RANGE((reg), 0x8300, 0x8500) || \
 480          REG_RANGE((reg), 0xB000, 0xB480) || \
 481          REG_RANGE((reg), 0xE000, 0xE800))
 482
 483 #define FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg) \
 484         (REG_RANGE((reg), 0x8800, 0x8900) || \
 485          REG_RANGE((reg), 0xD000, 0xD800) || \
 486          REG_RANGE((reg), 0x12000, 0x14000) || \
 487          REG_RANGE((reg), 0x1A000, 0x1C000) || \
 488          REG_RANGE((reg), 0x1E800, 0x1EA00) || \
 489          REG_RANGE((reg), 0x30000, 0x38000))
 490
 491 #define FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg) \
 492         (REG_RANGE((reg), 0x4000, 0x5000) || \
 493          REG_RANGE((reg), 0x8000, 0x8300) || \
 494          REG_RANGE((reg), 0x8500, 0x8600) || \
 495          REG_RANGE((reg), 0x9000, 0xB000) || \
 496          REG_RANGE((reg), 0xF000, 0x10000))
 497
 498 #define FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg) \
 499         REG_RANGE((reg), 0xB00,  0x2000)
 500
 501 #define FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg) \
 502         (REG_RANGE((reg), 0x2000, 0x2700) || \
 503          REG_RANGE((reg), 0x3000, 0x4000) || \
 504          REG_RANGE((reg), 0x5200, 0x8000) || \
 505          REG_RANGE((reg), 0x8140, 0x8160) || \
 506          REG_RANGE((reg), 0x8300, 0x8500) || \
 507          REG_RANGE((reg), 0x8C00, 0x8D00) || \
 508          REG_RANGE((reg), 0xB000, 0xB480) || \
 509          REG_RANGE((reg), 0xE000, 0xE900) || \
 510          REG_RANGE((reg), 0x24400, 0x24800))
 511
 512 #define FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg) \
 513         (REG_RANGE((reg), 0x8130, 0x8140) || \
 514          REG_RANGE((reg), 0x8800, 0x8A00) || \
 515          REG_RANGE((reg), 0xD000, 0xD800) || \
 516          REG_RANGE((reg), 0x12000, 0x14000) || \
 517          REG_RANGE((reg), 0x1A000, 0x1EA00) || \
 518          REG_RANGE((reg), 0x30000, 0x40000))
 519
 520 #define FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg) \
 521         REG_RANGE((reg), 0x9400, 0x9800)
 522
 523 #define FORCEWAKE_GEN9_BLITTER_RANGE_OFFSET(reg) \
 524         ((reg) < 0x40000 &&\
 525          !FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg) && \
 526          !FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg) && \
 527          !FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg) && \
 528          !FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg))
 529
 530 static void
 531 ilk_dummy_write(struct drm_i915_private *dev_priv)
 532 {
 533         /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up
 534          * the chip from rc6 before touching it for real. MI_MODE is masked,
 535          * hence harmless to write 0 into. */
 536         __raw_i915_write32(dev_priv, MI_MODE, 0);
 537 }
 538
 539 static void
 540 hsw_unclaimed_reg_debug(struct drm_i915_private *dev_priv, u32 reg, bool read,
 541                         bool before)
 542 {
 543         const char *op = read ? "reading" : "writing to";
 544         const char *when = before ? "before" : "after";
 545
 546         if (!i915.mmio_debug)
 547                 return;
 548
 549         if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) {
 550                 WARN(1, "Unclaimed register detected %s %s register 0x%x\n",
 551                      when, op, reg);
 552                 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
 553         }
 554 }
 555
 556 static void
 557 hsw_unclaimed_reg_detect(struct drm_i915_private *dev_priv)
 558 {
 559         if (i915.mmio_debug)
 560                 return;
 561
 562         if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) {
 563                 DRM_ERROR("Unclaimed register detected. Please use the i915.mmio_debug=1 to debug this problem.");
 564                 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
 565         }
 566 }
 567
 568 #define GEN2_READ_HEADER(x) \
 569         u##x val = 0; \
 570         assert_device_not_suspended(dev_priv);
 571
 572 #define GEN2_READ_FOOTER \
 573         trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
 574         return val
 575
 576 #define __gen2_read(x) \
 577 static u##x \
 578 gen2_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
 579         GEN2_READ_HEADER(x); \
 580         val = __raw_i915_read##x(dev_priv, reg); \
 581         GEN2_READ_FOOTER; \
 582 }
 583
 584 #define __gen5_read(x) \
 585 static u##x \
 586 gen5_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
 587         GEN2_READ_HEADER(x); \
 588         ilk_dummy_write(dev_priv); \
 589         val = __raw_i915_read##x(dev_priv, reg); \
 590         GEN2_READ_FOOTER; \
 591 }
 592
 593 __gen5_read(8)
 594 __gen5_read(16)
 595 __gen5_read(32)
 596 __gen5_read(64)
 597 __gen2_read(8)
 598 __gen2_read(16)
 599 __gen2_read(32)
 600 __gen2_read(64)
 601
 602 #undef __gen5_read
 603 #undef __gen2_read
 604
 605 #undef GEN2_READ_FOOTER
 606 #undef GEN2_READ_HEADER
 607
 608 #define GEN6_READ_HEADER(x) \
 609         unsigned long irqflags; \
 610         u##x val = 0; \
 611         assert_device_not_suspended(dev_priv); \
 612         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
 613
 614 #define GEN6_READ_FOOTER \
 615         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
 616         trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
 617         return val
 618
 619 static inline void __force_wake_get(struct drm_i915_private *dev_priv,
 620                                     enum forcewake_domains fw_domains)
 621 {
 622         struct intel_uncore_forcewake_domain *domain;
 623         enum forcewake_domain_id id;
 624
 625         if (WARN_ON(!fw_domains))
 626                 return;
 627
 628         /* Ideally GCC would be constant-fold and eliminate this loop */
 629         for_each_fw_domain_mask(domain, fw_domains, dev_priv, id) {
 630                 if (domain->wake_count) {
 631                         fw_domains &= ~(1 << id);
 632                         continue;
 633                 }
 634
 635                 domain->wake_count++;
 636                 fw_domain_arm_timer(domain);
 637         }
 638
 639         if (fw_domains)
 640                 dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains);
 641 }
 642
 643 #define __vgpu_read(x) \
 644 static u##x \
 645 vgpu_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
 646         GEN6_READ_HEADER(x); \
 647         val = __raw_i915_read##x(dev_priv, reg); \
 648         GEN6_READ_FOOTER; \
 649 }
 650
 651 #define __gen6_read(x) \
 652 static u##x \
 653 gen6_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
 654         GEN6_READ_HEADER(x); \
 655         hsw_unclaimed_reg_debug(dev_priv, reg, true, true); \
 656         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) \
 657                 __force_wake_get(dev_priv, FORCEWAKE_RENDER); \
 658         val = __raw_i915_read##x(dev_priv, reg); \
 659         hsw_unclaimed_reg_debug(dev_priv, reg, true, false); \
 660         GEN6_READ_FOOTER; \
 661 }
 662
 663 #define __vlv_read(x) \
 664 static u##x \
 665 vlv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
 666         GEN6_READ_HEADER(x); \
 667         if (FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg)) \
 668                 __force_wake_get(dev_priv, FORCEWAKE_RENDER); \
 669         else if (FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg)) \
 670                 __force_wake_get(dev_priv, FORCEWAKE_MEDIA); \
 671         val = __raw_i915_read##x(dev_priv, reg); \
 672         GEN6_READ_FOOTER; \
 673 }
 674
 675 #define __chv_read(x) \
 676 static u##x \
 677 chv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
 678         GEN6_READ_HEADER(x); \
 679         if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) \
 680                 __force_wake_get(dev_priv, FORCEWAKE_RENDER); \
 681         else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) \
 682                 __force_wake_get(dev_priv, FORCEWAKE_MEDIA); \
 683         else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) \
 684                 __force_wake_get(dev_priv, \
 685                                  FORCEWAKE_RENDER | FORCEWAKE_MEDIA); \
 686         val = __raw_i915_read##x(dev_priv, reg); \
 687         GEN6_READ_FOOTER; \
 688 }
 689
 690 #define SKL_NEEDS_FORCE_WAKE(dev_priv, reg)     \
 691          ((reg) < 0x40000 && !FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg))
 692
 693 #define __gen9_read(x) \
 694 static u##x \
 695 gen9_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
 696         enum forcewake_domains fw_engine; \
 697         GEN6_READ_HEADER(x); \
 698         if (!SKL_NEEDS_FORCE_WAKE((dev_priv), (reg)))   \
 699                 fw_engine = 0; \
 700         else if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg))       \
 701                 fw_engine = FORCEWAKE_RENDER; \
 702         else if (FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg)) \
 703                 fw_engine = FORCEWAKE_MEDIA; \
 704         else if (FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg)) \
 705                 fw_engine = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \
 706         else \
 707                 fw_engine = FORCEWAKE_BLITTER; \
 708         if (fw_engine) \
 709                 __force_wake_get(dev_priv, fw_engine); \
 710         val = __raw_i915_read##x(dev_priv, reg); \
 711         GEN6_READ_FOOTER; \
 712 }
 713
 714 __vgpu_read(8)
 715 __vgpu_read(16)
 716 __vgpu_read(32)
 717 __vgpu_read(64)
 718 __gen9_read(8)
 719 __gen9_read(16)
 720 __gen9_read(32)
 721 __gen9_read(64)
 722 __chv_read(8)
 723 __chv_read(16)
 724 __chv_read(32)
 725 __chv_read(64)
 726 __vlv_read(8)
 727 __vlv_read(16)
 728 __vlv_read(32)
 729 __vlv_read(64)
 730 __gen6_read(8)
 731 __gen6_read(16)
 732 __gen6_read(32)
 733 __gen6_read(64)
 734
 735 #undef __gen9_read
 736 #undef __chv_read
 737 #undef __vlv_read
 738 #undef __gen6_read
 739 #undef __vgpu_read
 740 #undef GEN6_READ_FOOTER
 741 #undef GEN6_READ_HEADER
 742
 743 #define GEN2_WRITE_HEADER \
 744         trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
 745         assert_device_not_suspended(dev_priv); \
 746
 747 #define GEN2_WRITE_FOOTER
 748
 749 #define __gen2_write(x) \
 750 static void \
 751 gen2_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
 752         GEN2_WRITE_HEADER; \
 753         __raw_i915_write##x(dev_priv, reg, val); \
 754         GEN2_WRITE_FOOTER; \
 755 }
 756
 757 #define __gen5_write(x) \
 758 static void \
 759 gen5_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
 760         GEN2_WRITE_HEADER; \
 761         ilk_dummy_write(dev_priv); \
 762         __raw_i915_write##x(dev_priv, reg, val); \
 763         GEN2_WRITE_FOOTER; \
 764 }
 765
 766 __gen5_write(8)
 767 __gen5_write(16)
 768 __gen5_write(32)
 769 __gen5_write(64)
 770 __gen2_write(8)
 771 __gen2_write(16)
 772 __gen2_write(32)
 773 __gen2_write(64)
 774
 775 #undef __gen5_write
 776 #undef __gen2_write
 777
 778 #undef GEN2_WRITE_FOOTER
 779 #undef GEN2_WRITE_HEADER
 780
 781 #define GEN6_WRITE_HEADER \
 782         unsigned long irqflags; \
 783         trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
 784         assert_device_not_suspended(dev_priv); \
 785         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
 786
 787 #define GEN6_WRITE_FOOTER \
 788         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags)
 789
 790 #define __gen6_write(x) \
 791 static void \
 792 gen6_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
 793         u32 __fifo_ret = 0; \
 794         GEN6_WRITE_HEADER; \
 795         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
 796                 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
 797         } \
 798         __raw_i915_write##x(dev_priv, reg, val); \
 799         if (unlikely(__fifo_ret)) { \
 800                 gen6_gt_check_fifodbg(dev_priv); \
 801         } \
 802         GEN6_WRITE_FOOTER; \
 803 }
 804
 805 #define __hsw_write(x) \
 806 static void \
 807 hsw_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
 808         u32 __fifo_ret = 0; \
 809         GEN6_WRITE_HEADER; \
 810         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
 811                 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
 812         } \
 813         hsw_unclaimed_reg_debug(dev_priv, reg, false, true); \
 814         __raw_i915_write##x(dev_priv, reg, val); \
 815         if (unlikely(__fifo_ret)) { \
 816                 gen6_gt_check_fifodbg(dev_priv); \
 817         } \
 818         hsw_unclaimed_reg_debug(dev_priv, reg, false, false); \
 819         hsw_unclaimed_reg_detect(dev_priv); \
 820         GEN6_WRITE_FOOTER; \
 821 }
 822
 823 #define __vgpu_write(x) \
 824 static void vgpu_write##x(struct drm_i915_private *dev_priv, \
 825                           off_t reg, u##x val, bool trace) { \
 826         GEN6_WRITE_HEADER; \
 827         __raw_i915_write##x(dev_priv, reg, val); \
 828         GEN6_WRITE_FOOTER; \
 829 }
 830
 831 static const u32 gen8_shadowed_regs[] = {
 832         FORCEWAKE_MT,
 833         GEN6_RPNSWREQ,
 834         GEN6_RC_VIDEO_FREQ,
 835         RING_TAIL(RENDER_RING_BASE),
 836         RING_TAIL(GEN6_BSD_RING_BASE),
 837         RING_TAIL(VEBOX_RING_BASE),
 838         RING_TAIL(BLT_RING_BASE),
 839         /* TODO: Other registers are not yet used */
 840 };
 841
 842 static bool is_gen8_shadowed(struct drm_i915_private *dev_priv, u32 reg)
 843 {
 844         int i;
 845         for (i = 0; i < ARRAY_SIZE(gen8_shadowed_regs); i++)
 846                 if (reg == gen8_shadowed_regs[i])
 847                         return true;
 848
 849         return false;
 850 }
 851
 852 #define __gen8_write(x) \
 853 static void \
 854 gen8_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
 855         GEN6_WRITE_HEADER; \
 856         hsw_unclaimed_reg_debug(dev_priv, reg, false, true); \
 857         if (reg < 0x40000 && !is_gen8_shadowed(dev_priv, reg)) \
 858                 __force_wake_get(dev_priv, FORCEWAKE_RENDER); \
 859         __raw_i915_write##x(dev_priv, reg, val); \
 860         hsw_unclaimed_reg_debug(dev_priv, reg, false, false); \
 861         hsw_unclaimed_reg_detect(dev_priv); \
 862         GEN6_WRITE_FOOTER; \
 863 }
 864
 865 #define __chv_write(x) \
 866 static void \
 867 chv_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
 868         bool shadowed = is_gen8_shadowed(dev_priv, reg); \
 869         GEN6_WRITE_HEADER; \
 870         if (!shadowed) { \
 871                 if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) \
 872                         __force_wake_get(dev_priv, FORCEWAKE_RENDER); \
 873                 else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) \
 874                         __force_wake_get(dev_priv, FORCEWAKE_MEDIA); \
 875                 else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) \
 876                         __force_wake_get(dev_priv, FORCEWAKE_RENDER | FORCEWAKE_MEDIA); \
 877         } \
 878         __raw_i915_write##x(dev_priv, reg, val); \
 879         GEN6_WRITE_FOOTER; \
 880 }
 881
 882 static const u32 gen9_shadowed_regs[] = {
 883         RING_TAIL(RENDER_RING_BASE),
 884         RING_TAIL(GEN6_BSD_RING_BASE),
 885         RING_TAIL(VEBOX_RING_BASE),
 886         RING_TAIL(BLT_RING_BASE),
 887         FORCEWAKE_BLITTER_GEN9,
 888         FORCEWAKE_RENDER_GEN9,
 889         FORCEWAKE_MEDIA_GEN9,
 890         GEN6_RPNSWREQ,
 891         GEN6_RC_VIDEO_FREQ,
 892         /* TODO: Other registers are not yet used */
 893 };
 894
 895 static bool is_gen9_shadowed(struct drm_i915_private *dev_priv, u32 reg)
 896 {
 897         int i;
 898         for (i = 0; i < ARRAY_SIZE(gen9_shadowed_regs); i++)
 899                 if (reg == gen9_shadowed_regs[i])
 900                         return true;
 901
 902         return false;
 903 }
 904
 905 #define __gen9_write(x) \
 906 static void \
 907 gen9_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, \
 908                 bool trace) { \
 909         enum forcewake_domains fw_engine; \
 910         GEN6_WRITE_HEADER; \
 911         if (!SKL_NEEDS_FORCE_WAKE((dev_priv), (reg)) || \
 912             is_gen9_shadowed(dev_priv, reg)) \
 913                 fw_engine = 0; \
 914         else if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg)) \
 915                 fw_engine = FORCEWAKE_RENDER; \
 916         else if (FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg)) \
 917                 fw_engine = FORCEWAKE_MEDIA; \
 918         else if (FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg)) \
 919                 fw_engine = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \
 920         else \
 921                 fw_engine = FORCEWAKE_BLITTER; \
 922         if (fw_engine) \
 923                 __force_wake_get(dev_priv, fw_engine); \
 924         __raw_i915_write##x(dev_priv, reg, val); \
 925         GEN6_WRITE_FOOTER; \
 926 }
 927
 928 __gen9_write(8)
 929 __gen9_write(16)
 930 __gen9_write(32)
 931 __gen9_write(64)
 932 __chv_write(8)
 933 __chv_write(16)
 934 __chv_write(32)
 935 __chv_write(64)
 936 __gen8_write(8)
 937 __gen8_write(16)
 938 __gen8_write(32)
 939 __gen8_write(64)
 940 __hsw_write(8)
 941 __hsw_write(16)
 942 __hsw_write(32)
 943 __hsw_write(64)
 944 __gen6_write(8)
 945 __gen6_write(16)
 946 __gen6_write(32)
 947 __gen6_write(64)
 948 __vgpu_write(8)
 949 __vgpu_write(16)
 950 __vgpu_write(32)
 951 __vgpu_write(64)
 952
 953 #undef __gen9_write
 954 #undef __chv_write
 955 #undef __gen8_write
 956 #undef __hsw_write
 957 #undef __gen6_write
 958 #undef __vgpu_write
 959 #undef GEN6_WRITE_FOOTER
 960 #undef GEN6_WRITE_HEADER
 961
 962 #define ASSIGN_WRITE_MMIO_VFUNCS(x) \
 963 do { \
 964         dev_priv->uncore.funcs.mmio_writeb = x##_write8; \
 965         dev_priv->uncore.funcs.mmio_writew = x##_write16; \
 966         dev_priv->uncore.funcs.mmio_writel = x##_write32; \
 967         dev_priv->uncore.funcs.mmio_writeq = x##_write64; \
 968 } while (0)
 969
 970 #define ASSIGN_READ_MMIO_VFUNCS(x) \
 971 do { \
 972         dev_priv->uncore.funcs.mmio_readb = x##_read8; \
 973         dev_priv->uncore.funcs.mmio_readw = x##_read16; \
 974         dev_priv->uncore.funcs.mmio_readl = x##_read32; \
 975         dev_priv->uncore.funcs.mmio_readq = x##_read64; \
 976 } while (0)
 977
 978
 979 static void fw_domain_init(struct drm_i915_private *dev_priv,
 980                            enum forcewake_domain_id domain_id,
 981                            u32 reg_set, u32 reg_ack)
 982 {
 983         struct intel_uncore_forcewake_domain *d;
 984
 985         if (WARN_ON(domain_id >= FW_DOMAIN_ID_COUNT))
 986                 return;
 987
 988         d = &dev_priv->uncore.fw_domain[domain_id];
 989
 990         WARN_ON(d->wake_count);
 991
 992         d->wake_count = 0;
 993         d->reg_set = reg_set;
 994         d->reg_ack = reg_ack;
 995
 996         if (IS_GEN6(dev_priv)) {
 997                 d->val_reset = 0;
 998                 d->val_set = FORCEWAKE_KERNEL;
 999                 d->val_clear = 0;
1000         } else {
1001                 d->val_reset = _MASKED_BIT_DISABLE(0xffff);
1002                 d->val_set = _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL);
1003                 d->val_clear = _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL);
1004         }
1005
1006         if (IS_VALLEYVIEW(dev_priv))
1007                 d->reg_post = FORCEWAKE_ACK_VLV;
1008         else if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv) || IS_GEN8(dev_priv))
1009                 d->reg_post = ECOBUS;
1010         else
1011                 d->reg_post = 0;
1012
1013         d->i915 = dev_priv;
1014         d->id = domain_id;
1015
1016         setup_timer(&d->timer, intel_uncore_fw_release_timer, (unsigned long)d);
1017
1018         dev_priv->uncore.fw_domains |= (1 << domain_id);
1019
1020         fw_domain_reset(d);
1021 }
1022
1023 static void intel_uncore_fw_domains_init(struct drm_device *dev)
1024 {
1025         struct drm_i915_private *dev_priv = dev->dev_private;
1026
1027         if (IS_GEN9(dev)) {
1028                 dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
1029                 dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
1030                 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1031                                FORCEWAKE_RENDER_GEN9,
1032                                FORCEWAKE_ACK_RENDER_GEN9);
1033                 fw_domain_init(dev_priv, FW_DOMAIN_ID_BLITTER,
1034                                FORCEWAKE_BLITTER_GEN9,
1035                                FORCEWAKE_ACK_BLITTER_GEN9);
1036                 fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA,
1037                                FORCEWAKE_MEDIA_GEN9, FORCEWAKE_ACK_MEDIA_GEN9);
1038         } else if (IS_VALLEYVIEW(dev)) {
1039                 dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
1040                 if (!IS_CHERRYVIEW(dev))
1041                         dev_priv->uncore.funcs.force_wake_put =
1042                                 fw_domains_put_with_fifo;
1043                 else
1044                         dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
1045                 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1046                                FORCEWAKE_VLV, FORCEWAKE_ACK_VLV);
1047                 fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA,
1048                                FORCEWAKE_MEDIA_VLV, FORCEWAKE_ACK_MEDIA_VLV);
1049         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1050                 dev_priv->uncore.funcs.force_wake_get =
1051                         fw_domains_get_with_thread_status;
1052                 dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
1053                 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1054                                FORCEWAKE_MT, FORCEWAKE_ACK_HSW);
1055         } else if (IS_IVYBRIDGE(dev)) {
1056                 u32 ecobus;
1057
1058                 /* IVB configs may use multi-threaded forcewake */
1059
1060                 /* A small trick here - if the bios hasn't configured
1061                  * MT forcewake, and if the device is in RC6, then
1062                  * force_wake_mt_get will not wake the device and the
1063                  * ECOBUS read will return zero. Which will be
1064                  * (correctly) interpreted by the test below as MT
1065                  * forcewake being disabled.
1066                  */
1067                 dev_priv->uncore.funcs.force_wake_get =
1068                         fw_domains_get_with_thread_status;
1069                 dev_priv->uncore.funcs.force_wake_put =
1070                         fw_domains_put_with_fifo;
1071
1072                 /* We need to init first for ECOBUS access and then
1073                  * determine later if we want to reinit, in case of MT access is
1074                  * not working
1075                  */
1076                 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1077                                FORCEWAKE_MT, FORCEWAKE_MT_ACK);
1078
1079                 mutex_lock(&dev->struct_mutex);
1080                 fw_domains_get_with_thread_status(dev_priv, FORCEWAKE_ALL);
1081                 ecobus = __raw_i915_read32(dev_priv, ECOBUS);
1082                 fw_domains_put_with_fifo(dev_priv, FORCEWAKE_ALL);
1083                 mutex_unlock(&dev->struct_mutex);
1084
1085                 if (!(ecobus & FORCEWAKE_MT_ENABLE)) {
1086                         DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n");
1087                         DRM_INFO("when using vblank-synced partial screen updates.\n");
1088                         fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1089                                        FORCEWAKE, FORCEWAKE_ACK);
1090                 }
1091         } else if (IS_GEN6(dev)) {
1092                 dev_priv->uncore.funcs.force_wake_get =
1093                         fw_domains_get_with_thread_status;
1094                 dev_priv->uncore.funcs.force_wake_put =
1095                         fw_domains_put_with_fifo;
1096                 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1097                                FORCEWAKE, FORCEWAKE_ACK);
1098         }
1099 }
1100
1101 void intel_uncore_init(struct drm_device *dev)
1102 {
1103         struct drm_i915_private *dev_priv = dev->dev_private;
1104
1105         i915_check_vgpu(dev);
1106
1107         intel_uncore_ellc_detect(dev);
1108         intel_uncore_fw_domains_init(dev);
1109         __intel_uncore_early_sanitize(dev, false);
1110
1111         switch (INTEL_INFO(dev)->gen) {
1112         default:
1113                 MISSING_CASE(INTEL_INFO(dev)->gen);
1114                 return;
1115         case 9:
1116                 ASSIGN_WRITE_MMIO_VFUNCS(gen9);
1117                 ASSIGN_READ_MMIO_VFUNCS(gen9);
1118                 break;
1119         case 8:
1120                 if (IS_CHERRYVIEW(dev)) {
1121                         ASSIGN_WRITE_MMIO_VFUNCS(chv);
1122                         ASSIGN_READ_MMIO_VFUNCS(chv);
1123
1124                 } else {
1125                         ASSIGN_WRITE_MMIO_VFUNCS(gen8);
1126                         ASSIGN_READ_MMIO_VFUNCS(gen6);
1127                 }
1128                 break;
1129         case 7:
1130         case 6:
1131                 if (IS_HASWELL(dev)) {
1132                         ASSIGN_WRITE_MMIO_VFUNCS(hsw);
1133                 } else {
1134                         ASSIGN_WRITE_MMIO_VFUNCS(gen6);
1135                 }
1136
1137                 if (IS_VALLEYVIEW(dev)) {
1138                         ASSIGN_READ_MMIO_VFUNCS(vlv);
1139                 } else {
1140                         ASSIGN_READ_MMIO_VFUNCS(gen6);
1141                 }
1142                 break;
1143         case 5:
1144                 ASSIGN_WRITE_MMIO_VFUNCS(gen5);
1145                 ASSIGN_READ_MMIO_VFUNCS(gen5);
1146                 break;
1147         case 4:
1148         case 3:
1149         case 2:
1150                 ASSIGN_WRITE_MMIO_VFUNCS(gen2);
1151                 ASSIGN_READ_MMIO_VFUNCS(gen2);
1152                 break;
1153         }
1154
1155         if (intel_vgpu_active(dev)) {
1156                 ASSIGN_WRITE_MMIO_VFUNCS(vgpu);
1157                 ASSIGN_READ_MMIO_VFUNCS(vgpu);
1158         }
1159
1160         i915_check_and_clear_faults(dev);
1161 }
1162 #undef ASSIGN_WRITE_MMIO_VFUNCS
1163 #undef ASSIGN_READ_MMIO_VFUNCS
1164
1165 void intel_uncore_fini(struct drm_device *dev)
1166 {
1167         /* Paranoia: make sure we have disabled everything before we exit. */
1168         intel_uncore_sanitize(dev);
1169         intel_uncore_forcewake_reset(dev, false);
1170 }
1171
1172 #define GEN_RANGE(l, h) GENMASK(h, l)
1173
1174 static const struct register_whitelist {
1175         uint64_t offset;
1176         uint32_t size;
1177         /* supported gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
1178         uint32_t gen_bitmask;
1179 } whitelist[] = {
1180         { RING_TIMESTAMP(RENDER_RING_BASE), 8, GEN_RANGE(4, 9) },
1181 };
1182
1183 int i915_reg_read_ioctl(struct drm_device *dev,
1184                         void *data, struct drm_file *file)
1185 {
1186         struct drm_i915_private *dev_priv = dev->dev_private;
1187         struct drm_i915_reg_read *reg = data;
1188         struct register_whitelist const *entry = whitelist;
1189         int i, ret = 0;
1190
1191         for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) {
1192                 if (entry->offset == reg->offset &&
1193                     (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask))
1194                         break;
1195         }
1196
1197         if (i == ARRAY_SIZE(whitelist))
1198                 return -EINVAL;
1199
1200         intel_runtime_pm_get(dev_priv);
1201
1202         switch (entry->size) {
1203         case 8:
1204                 reg->val = I915_READ64(reg->offset);
1205                 break;
1206         case 4:
1207                 reg->val = I915_READ(reg->offset);
1208                 break;
1209         case 2:
1210                 reg->val = I915_READ16(reg->offset);
1211                 break;
1212         case 1:
1213                 reg->val = I915_READ8(reg->offset);
1214                 break;
1215         default:
1216                 MISSING_CASE(entry->size);
1217                 ret = -EINVAL;
1218                 goto out;
1219         }
1220
1221 out:
1222         intel_runtime_pm_put(dev_priv);
1223         return ret;
1224 }
1225
1226 int i915_get_reset_stats_ioctl(struct drm_device *dev,
1227                                void *data, struct drm_file *file)
1228 {
1229         struct drm_i915_private *dev_priv = dev->dev_private;
1230         struct drm_i915_reset_stats *args = data;
1231         struct i915_ctx_hang_stats *hs;
1232         struct intel_context *ctx;
1233         int ret;
1234
1235         if (args->flags || args->pad)
1236                 return -EINVAL;
1237
1238         if (args->ctx_id == DEFAULT_CONTEXT_HANDLE && !capable(CAP_SYS_ADMIN))
1239                 return -EPERM;
1240
1241         ret = mutex_lock_interruptible(&dev->struct_mutex);
1242         if (ret)
1243                 return ret;
1244
1245         ctx = i915_gem_context_get(file->driver_priv, args->ctx_id);
1246         if (IS_ERR(ctx)) {
1247                 mutex_unlock(&dev->struct_mutex);
1248                 return PTR_ERR(ctx);
1249         }
1250         hs = &ctx->hang_stats;
1251
1252         if (capable(CAP_SYS_ADMIN))
1253                 args->reset_count = i915_reset_count(&dev_priv->gpu_error);
1254         else
1255                 args->reset_count = 0;
1256
1257         args->batch_active = hs->batch_active;
1258         args->batch_pending = hs->batch_pending;
1259
1260         mutex_unlock(&dev->struct_mutex);
1261
1262         return 0;
1263 }
1264
1265 static int i915_reset_complete(struct drm_device *dev)
1266 {
1267         u8 gdrst;
1268         pci_read_config_byte(dev->pdev, I915_GDRST, &gdrst);
1269         return (gdrst & GRDOM_RESET_STATUS) == 0;
1270 }
1271
1272 static int i915_do_reset(struct drm_device *dev)
1273 {
1274         /* assert reset for at least 20 usec */
1275         pci_write_config_byte(dev->pdev, I915_GDRST, GRDOM_RESET_ENABLE);
1276         udelay(20);
1277         pci_write_config_byte(dev->pdev, I915_GDRST, 0);
1278
1279         return wait_for(i915_reset_complete(dev), 500);
1280 }
1281
1282 static int g4x_reset_complete(struct drm_device *dev)
1283 {
1284         u8 gdrst;
1285         pci_read_config_byte(dev->pdev, I915_GDRST, &gdrst);
1286         return (gdrst & GRDOM_RESET_ENABLE) == 0;
1287 }
1288
1289 static int g33_do_reset(struct drm_device *dev)
1290 {
1291         pci_write_config_byte(dev->pdev, I915_GDRST, GRDOM_RESET_ENABLE);
1292         return wait_for(g4x_reset_complete(dev), 500);
1293 }
1294
1295 static int g4x_do_reset(struct drm_device *dev)
1296 {
1297         struct drm_i915_private *dev_priv = dev->dev_private;
1298         int ret;
1299
1300         pci_write_config_byte(dev->pdev, I915_GDRST,
1301                               GRDOM_RENDER | GRDOM_RESET_ENABLE);
1302         ret =  wait_for(g4x_reset_complete(dev), 500);
1303         if (ret)
1304                 return ret;
1305
1306         /* WaVcpClkGateDisableForMediaReset:ctg,elk */
1307         I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) | VCP_UNIT_CLOCK_GATE_DISABLE);
1308         POSTING_READ(VDECCLK_GATE_D);
1309
1310         pci_write_config_byte(dev->pdev, I915_GDRST,
1311                               GRDOM_MEDIA | GRDOM_RESET_ENABLE);
1312         ret =  wait_for(g4x_reset_complete(dev), 500);
1313         if (ret)
1314                 return ret;
1315
1316         /* WaVcpClkGateDisableForMediaReset:ctg,elk */
1317         I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) & ~VCP_UNIT_CLOCK_GATE_DISABLE);
1318         POSTING_READ(VDECCLK_GATE_D);
1319
1320         pci_write_config_byte(dev->pdev, I915_GDRST, 0);
1321
1322         return 0;
1323 }
1324
1325 static int ironlake_do_reset(struct drm_device *dev)
1326 {
1327         struct drm_i915_private *dev_priv = dev->dev_private;
1328         int ret;
1329
1330         I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
1331                    ILK_GRDOM_RENDER | ILK_GRDOM_RESET_ENABLE);
1332         ret = wait_for((I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) &
1333                         ILK_GRDOM_RESET_ENABLE) == 0, 500);
1334         if (ret)
1335                 return ret;
1336
1337         I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
1338                    ILK_GRDOM_MEDIA | ILK_GRDOM_RESET_ENABLE);
1339         ret = wait_for((I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) &
1340                         ILK_GRDOM_RESET_ENABLE) == 0, 500);
1341         if (ret)
1342                 return ret;
1343
1344         I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, 0);
1345
1346         return 0;
1347 }
1348
1349 static int gen6_do_reset(struct drm_device *dev)
1350 {
1351         struct drm_i915_private *dev_priv = dev->dev_private;
1352         int     ret;
1353
1354         /* Reset the chip */
1355
1356         /* GEN6_GDRST is not in the gt power well, no need to check
1357          * for fifo space for the write or forcewake the chip for
1358          * the read
1359          */
1360         __raw_i915_write32(dev_priv, GEN6_GDRST, GEN6_GRDOM_FULL);
1361
1362         /* Spin waiting for the device to ack the reset request */
1363         ret = wait_for((__raw_i915_read32(dev_priv, GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
1364
1365         intel_uncore_forcewake_reset(dev, true);
1366
1367         return ret;
1368 }
1369
1370 int intel_gpu_reset(struct drm_device *dev)
1371 {
1372         if (INTEL_INFO(dev)->gen >= 6)
1373                 return gen6_do_reset(dev);
1374         else if (IS_GEN5(dev))
1375                 return ironlake_do_reset(dev);
1376         else if (IS_G4X(dev))
1377                 return g4x_do_reset(dev);
1378         else if (IS_G33(dev))
1379                 return g33_do_reset(dev);
1380         else if (INTEL_INFO(dev)->gen >= 3)
1381                 return i915_do_reset(dev);
1382         else
1383                 return -ENODEV;
1384 }
1385
1386 void intel_uncore_check_errors(struct drm_device *dev)
1387 {
1388         struct drm_i915_private *dev_priv = dev->dev_private;
1389
1390         if (HAS_FPGA_DBG_UNCLAIMED(dev) &&
1391             (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {
1392                 DRM_ERROR("Unclaimed register before interrupt\n");
1393                 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
1394         }
1395 }