drivers/gpu/drm/i915/intel_uncore.c

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "i915_drv.h"
  25 #include "intel_drv.h"
  26 #include "i915_vgpu.h"
  27
  28 #include <linux/pm_runtime.h>
  29
  30 #define FORCEWAKE_ACK_TIMEOUT_MS 50
  31
  32 #define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32((dev_priv__), (reg__))
  33
  34 static const char * const forcewake_domain_names[] = {
  35         "render",
  36         "blitter",
  37         "media",
  38 };
  39
  40 const char *
  41 intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id)
  42 {
  43         BUILD_BUG_ON(ARRAY_SIZE(forcewake_domain_names) != FW_DOMAIN_ID_COUNT);
  44
  45         if (id >= 0 && id < FW_DOMAIN_ID_COUNT)
  46                 return forcewake_domain_names[id];
  47
  48         WARN_ON(id);
  49
  50         return "unknown";
  51 }
  52
  53 static inline void
  54 fw_domain_reset(const struct intel_uncore_forcewake_domain *d)
  55 {
  56         WARN_ON(!i915_mmio_reg_valid(d->reg_set));
  57         __raw_i915_write32(d->i915, d->reg_set, d->val_reset);
  58 }
  59
  60 static inline void
  61 fw_domain_arm_timer(struct intel_uncore_forcewake_domain *d)
  62 {
  63         d->wake_count++;
  64         hrtimer_start_range_ns(&d->timer,
  65                                ktime_set(0, NSEC_PER_MSEC),
  66                                NSEC_PER_MSEC,
  67                                HRTIMER_MODE_REL);
  68 }
  69
  70 static inline void
  71 fw_domain_wait_ack_clear(const struct intel_uncore_forcewake_domain *d)
  72 {
  73         if (wait_for_atomic((__raw_i915_read32(d->i915, d->reg_ack) &
  74                              FORCEWAKE_KERNEL) == 0,
  75                             FORCEWAKE_ACK_TIMEOUT_MS))
  76                 DRM_ERROR("%s: timed out waiting for forcewake ack to clear.\n",
  77                           intel_uncore_forcewake_domain_to_str(d->id));
  78 }
  79
  80 static inline void
  81 fw_domain_get(const struct intel_uncore_forcewake_domain *d)
  82 {
  83         __raw_i915_write32(d->i915, d->reg_set, d->val_set);
  84 }
  85
  86 static inline void
  87 fw_domain_wait_ack(const struct intel_uncore_forcewake_domain *d)
  88 {
  89         if (wait_for_atomic((__raw_i915_read32(d->i915, d->reg_ack) &
  90                              FORCEWAKE_KERNEL),
  91                             FORCEWAKE_ACK_TIMEOUT_MS))
  92                 DRM_ERROR("%s: timed out waiting for forcewake ack request.\n",
  93                           intel_uncore_forcewake_domain_to_str(d->id));
  94 }
  95
  96 static inline void
  97 fw_domain_put(const struct intel_uncore_forcewake_domain *d)
  98 {
  99         __raw_i915_write32(d->i915, d->reg_set, d->val_clear);
 100 }
 101
 102 static inline void
 103 fw_domain_posting_read(const struct intel_uncore_forcewake_domain *d)
 104 {
 105         /* something from same cacheline, but not from the set register */
 106         if (i915_mmio_reg_valid(d->reg_post))
 107                 __raw_posting_read(d->i915, d->reg_post);
 108 }
 109
 110 static void
 111 fw_domains_get(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains)
 112 {
 113         struct intel_uncore_forcewake_domain *d;
 114
 115         for_each_fw_domain_masked(d, fw_domains, dev_priv) {
 116                 fw_domain_wait_ack_clear(d);
 117                 fw_domain_get(d);
 118         }
 119
 120         for_each_fw_domain_masked(d, fw_domains, dev_priv)
 121                 fw_domain_wait_ack(d);
 122 }
 123
 124 static void
 125 fw_domains_put(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains)
 126 {
 127         struct intel_uncore_forcewake_domain *d;
 128
 129         for_each_fw_domain_masked(d, fw_domains, dev_priv) {
 130                 fw_domain_put(d);
 131                 fw_domain_posting_read(d);
 132         }
 133 }
 134
 135 static void
 136 fw_domains_posting_read(struct drm_i915_private *dev_priv)
 137 {
 138         struct intel_uncore_forcewake_domain *d;
 139
 140         /* No need to do for all, just do for first found */
 141         for_each_fw_domain(d, dev_priv) {
 142                 fw_domain_posting_read(d);
 143                 break;
 144         }
 145 }
 146
 147 static void
 148 fw_domains_reset(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains)
 149 {
 150         struct intel_uncore_forcewake_domain *d;
 151
 152         if (dev_priv->uncore.fw_domains == 0)
 153                 return;
 154
 155         for_each_fw_domain_masked(d, fw_domains, dev_priv)
 156                 fw_domain_reset(d);
 157
 158         fw_domains_posting_read(dev_priv);
 159 }
 160
 161 static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
 162 {
 163         /* w/a for a sporadic read returning 0 by waiting for the GT
 164          * thread to wake up.
 165          */
 166         if (wait_for_atomic_us((__raw_i915_read32(dev_priv, GEN6_GT_THREAD_STATUS_REG) &
 167                                 GEN6_GT_THREAD_STATUS_CORE_MASK) == 0, 500))
 168                 DRM_ERROR("GT thread status wait timed out\n");
 169 }
 170
 171 static void fw_domains_get_with_thread_status(struct drm_i915_private *dev_priv,
 172                                               enum forcewake_domains fw_domains)
 173 {
 174         fw_domains_get(dev_priv, fw_domains);
 175
 176         /* WaRsForcewakeWaitTC0:snb,ivb,hsw,bdw,vlv */
 177         __gen6_gt_wait_for_thread_c0(dev_priv);
 178 }
 179
 180 static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
 181 {
 182         u32 gtfifodbg;
 183
 184         gtfifodbg = __raw_i915_read32(dev_priv, GTFIFODBG);
 185         if (WARN(gtfifodbg, "GT wake FIFO error 0x%x\n", gtfifodbg))
 186                 __raw_i915_write32(dev_priv, GTFIFODBG, gtfifodbg);
 187 }
 188
 189 static void fw_domains_put_with_fifo(struct drm_i915_private *dev_priv,
 190                                      enum forcewake_domains fw_domains)
 191 {
 192         fw_domains_put(dev_priv, fw_domains);
 193         gen6_gt_check_fifodbg(dev_priv);
 194 }
 195
 196 static inline u32 fifo_free_entries(struct drm_i915_private *dev_priv)
 197 {
 198         u32 count = __raw_i915_read32(dev_priv, GTFIFOCTL);
 199
 200         return count & GT_FIFO_FREE_ENTRIES_MASK;
 201 }
 202
 203 static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
 204 {
 205         int ret = 0;
 206
 207         /* On VLV, FIFO will be shared by both SW and HW.
 208          * So, we need to read the FREE_ENTRIES everytime */
 209         if (IS_VALLEYVIEW(dev_priv))
 210                 dev_priv->uncore.fifo_count = fifo_free_entries(dev_priv);
 211
 212         if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
 213                 int loop = 500;
 214                 u32 fifo = fifo_free_entries(dev_priv);
 215
 216                 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
 217                         udelay(10);
 218                         fifo = fifo_free_entries(dev_priv);
 219                 }
 220                 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
 221                         ++ret;
 222                 dev_priv->uncore.fifo_count = fifo;
 223         }
 224         dev_priv->uncore.fifo_count--;
 225
 226         return ret;
 227 }
 228
 229 static enum hrtimer_restart
 230 intel_uncore_fw_release_timer(struct hrtimer *timer)
 231 {
 232         struct intel_uncore_forcewake_domain *domain =
 233                container_of(timer, struct intel_uncore_forcewake_domain, timer);
 234         unsigned long irqflags;
 235
 236         assert_rpm_device_not_suspended(domain->i915);
 237
 238         spin_lock_irqsave(&domain->i915->uncore.lock, irqflags);
 239         if (WARN_ON(domain->wake_count == 0))
 240                 domain->wake_count++;
 241
 242         if (--domain->wake_count == 0)
 243                 domain->i915->uncore.funcs.force_wake_put(domain->i915,
 244                                                           1 << domain->id);
 245
 246         spin_unlock_irqrestore(&domain->i915->uncore.lock, irqflags);
 247
 248         return HRTIMER_NORESTART;
 249 }
 250
 251 void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore)
 252 {
 253         struct drm_i915_private *dev_priv = dev->dev_private;
 254         unsigned long irqflags;
 255         struct intel_uncore_forcewake_domain *domain;
 256         int retry_count = 100;
 257         enum forcewake_domains fw = 0, active_domains;
 258
 259         /* Hold uncore.lock across reset to prevent any register access
 260          * with forcewake not set correctly. Wait until all pending
 261          * timers are run before holding.
 262          */
 263         while (1) {
 264                 active_domains = 0;
 265
 266                 for_each_fw_domain(domain, dev_priv) {
 267                         if (hrtimer_cancel(&domain->timer) == 0)
 268                                 continue;
 269
 270                         intel_uncore_fw_release_timer(&domain->timer);
 271                 }
 272
 273                 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 274
 275                 for_each_fw_domain(domain, dev_priv) {
 276                         if (hrtimer_active(&domain->timer))
 277                                 active_domains |= domain->mask;
 278                 }
 279
 280                 if (active_domains == 0)
 281                         break;
 282
 283                 if (--retry_count == 0) {
 284                         DRM_ERROR("Timed out waiting for forcewake timers to finish\n");
 285                         break;
 286                 }
 287
 288                 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 289                 cond_resched();
 290         }
 291
 292         WARN_ON(active_domains);
 293
 294         for_each_fw_domain(domain, dev_priv)
 295                 if (domain->wake_count)
 296                         fw |= domain->mask;
 297
 298         if (fw)
 299                 dev_priv->uncore.funcs.force_wake_put(dev_priv, fw);
 300
 301         fw_domains_reset(dev_priv, FORCEWAKE_ALL);
 302
 303         if (restore) { /* If reset with a user forcewake, try to restore */
 304                 if (fw)
 305                         dev_priv->uncore.funcs.force_wake_get(dev_priv, fw);
 306
 307                 if (IS_GEN6(dev) || IS_GEN7(dev))
 308                         dev_priv->uncore.fifo_count =
 309                                 fifo_free_entries(dev_priv);
 310         }
 311
 312         if (!restore)
 313                 assert_forcewakes_inactive(dev_priv);
 314
 315         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 316 }
 317
 318 u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv)
 319 {
 320         if (!HAS_EDRAM(dev_priv))
 321                 return 0;
 322
 323         /* The docs do not explain exactly how the calculation can be
 324          * made. It is somewhat guessable, but for now, it's always
 325          * 128MB.
 326          */
 327
 328         return 128 * 1024 * 1024;
 329 }
 330
 331 static void intel_uncore_edram_detect(struct drm_i915_private *dev_priv)
 332 {
 333         if (IS_HASWELL(dev_priv) ||
 334             IS_BROADWELL(dev_priv) ||
 335             INTEL_GEN(dev_priv) >= 9) {
 336                 dev_priv->edram_cap = __raw_i915_read32(dev_priv,
 337                                                         HSW_EDRAM_CAP);
 338
 339                 /* NB: We can't write IDICR yet because we do not have gt funcs
 340                  * set up */
 341         } else {
 342                 dev_priv->edram_cap = 0;
 343         }
 344
 345         if (HAS_EDRAM(dev_priv))
 346                 DRM_INFO("Found %lluMB of eDRAM\n",
 347                          intel_uncore_edram_size(dev_priv) / (1024 * 1024));
 348 }
 349
 350 static bool
 351 fpga_check_for_unclaimed_mmio(struct drm_i915_private *dev_priv)
 352 {
 353         u32 dbg;
 354
 355         dbg = __raw_i915_read32(dev_priv, FPGA_DBG);
 356         if (likely(!(dbg & FPGA_DBG_RM_NOCLAIM)))
 357                 return false;
 358
 359         __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
 360
 361         return true;
 362 }
 363
 364 static bool
 365 vlv_check_for_unclaimed_mmio(struct drm_i915_private *dev_priv)
 366 {
 367         u32 cer;
 368
 369         cer = __raw_i915_read32(dev_priv, CLAIM_ER);
 370         if (likely(!(cer & (CLAIM_ER_OVERFLOW | CLAIM_ER_CTR_MASK))))
 371                 return false;
 372
 373         __raw_i915_write32(dev_priv, CLAIM_ER, CLAIM_ER_CLR);
 374
 375         return true;
 376 }
 377
 378 static bool
 379 check_for_unclaimed_mmio(struct drm_i915_private *dev_priv)
 380 {
 381         if (HAS_FPGA_DBG_UNCLAIMED(dev_priv))
 382                 return fpga_check_for_unclaimed_mmio(dev_priv);
 383
 384         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 385                 return vlv_check_for_unclaimed_mmio(dev_priv);
 386
 387         return false;
 388 }
 389
 390 static void __intel_uncore_early_sanitize(struct drm_device *dev,
 391                                           bool restore_forcewake)
 392 {
 393         struct drm_i915_private *dev_priv = dev->dev_private;
 394
 395         /* clear out unclaimed reg detection bit */
 396         if (check_for_unclaimed_mmio(dev_priv))
 397                 DRM_DEBUG("unclaimed mmio detected on uncore init, clearing\n");
 398
 399         /* clear out old GT FIFO errors */
 400         if (IS_GEN6(dev) || IS_GEN7(dev))
 401                 __raw_i915_write32(dev_priv, GTFIFODBG,
 402                                    __raw_i915_read32(dev_priv, GTFIFODBG));
 403
 404         /* WaDisableShadowRegForCpd:chv */
 405         if (IS_CHERRYVIEW(dev)) {
 406                 __raw_i915_write32(dev_priv, GTFIFOCTL,
 407                                    __raw_i915_read32(dev_priv, GTFIFOCTL) |
 408                                    GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL |
 409                                    GT_FIFO_CTL_RC6_POLICY_STALL);
 410         }
 411
 412         intel_uncore_forcewake_reset(dev, restore_forcewake);
 413 }
 414
 415 void intel_uncore_early_sanitize(struct drm_device *dev, bool restore_forcewake)
 416 {
 417         __intel_uncore_early_sanitize(dev, restore_forcewake);
 418         i915_check_and_clear_faults(dev);
 419 }
 420
 421 void intel_uncore_sanitize(struct drm_device *dev)
 422 {
 423         i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6);
 424
 425         /* BIOS often leaves RC6 enabled, but disable it for hw init */
 426         intel_disable_gt_powersave(dev);
 427 }
 428
 429 static void __intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
 430                                          enum forcewake_domains fw_domains)
 431 {
 432         struct intel_uncore_forcewake_domain *domain;
 433
 434         if (!dev_priv->uncore.funcs.force_wake_get)
 435                 return;
 436
 437         fw_domains &= dev_priv->uncore.fw_domains;
 438
 439         for_each_fw_domain_masked(domain, fw_domains, dev_priv) {
 440                 if (domain->wake_count++)
 441                         fw_domains &= ~domain->mask;
 442         }
 443
 444         if (fw_domains)
 445                 dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains);
 446 }
 447
 448 /**
 449  * intel_uncore_forcewake_get - grab forcewake domain references
 450  * @dev_priv: i915 device instance
 451  * @fw_domains: forcewake domains to get reference on
 452  *
 453  * This function can be used get GT's forcewake domain references.
 454  * Normal register access will handle the forcewake domains automatically.
 455  * However if some sequence requires the GT to not power down a particular
 456  * forcewake domains this function should be called at the beginning of the
 457  * sequence. And subsequently the reference should be dropped by symmetric
 458  * call to intel_unforce_forcewake_put(). Usually caller wants all the domains
 459  * to be kept awake so the @fw_domains would be then FORCEWAKE_ALL.
 460  */
 461 void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
 462                                 enum forcewake_domains fw_domains)
 463 {
 464         unsigned long irqflags;
 465
 466         if (!dev_priv->uncore.funcs.force_wake_get)
 467                 return;
 468
 469         assert_rpm_wakelock_held(dev_priv);
 470
 471         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 472         __intel_uncore_forcewake_get(dev_priv, fw_domains);
 473         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 474 }
 475
 476 /**
 477  * intel_uncore_forcewake_get__locked - grab forcewake domain references
 478  * @dev_priv: i915 device instance
 479  * @fw_domains: forcewake domains to get reference on
 480  *
 481  * See intel_uncore_forcewake_get(). This variant places the onus
 482  * on the caller to explicitly handle the dev_priv->uncore.lock spinlock.
 483  */
 484 void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
 485                                         enum forcewake_domains fw_domains)
 486 {
 487         assert_spin_locked(&dev_priv->uncore.lock);
 488
 489         if (!dev_priv->uncore.funcs.force_wake_get)
 490                 return;
 491
 492         __intel_uncore_forcewake_get(dev_priv, fw_domains);
 493 }
 494
 495 static void __intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
 496                                          enum forcewake_domains fw_domains)
 497 {
 498         struct intel_uncore_forcewake_domain *domain;
 499
 500         if (!dev_priv->uncore.funcs.force_wake_put)
 501                 return;
 502
 503         fw_domains &= dev_priv->uncore.fw_domains;
 504
 505         for_each_fw_domain_masked(domain, fw_domains, dev_priv) {
 506                 if (WARN_ON(domain->wake_count == 0))
 507                         continue;
 508
 509                 if (--domain->wake_count)
 510                         continue;
 511
 512                 fw_domain_arm_timer(domain);
 513         }
 514 }
 515
 516 /**
 517  * intel_uncore_forcewake_put - release a forcewake domain reference
 518  * @dev_priv: i915 device instance
 519  * @fw_domains: forcewake domains to put references
 520  *
 521  * This function drops the device-level forcewakes for specified
 522  * domains obtained by intel_uncore_forcewake_get().
 523  */
 524 void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
 525                                 enum forcewake_domains fw_domains)
 526 {
 527         unsigned long irqflags;
 528
 529         if (!dev_priv->uncore.funcs.force_wake_put)
 530                 return;
 531
 532         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 533         __intel_uncore_forcewake_put(dev_priv, fw_domains);
 534         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 535 }
 536
 537 /**
 538  * intel_uncore_forcewake_put__locked - grab forcewake domain references
 539  * @dev_priv: i915 device instance
 540  * @fw_domains: forcewake domains to get reference on
 541  *
 542  * See intel_uncore_forcewake_put(). This variant places the onus
 543  * on the caller to explicitly handle the dev_priv->uncore.lock spinlock.
 544  */
 545 void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
 546                                         enum forcewake_domains fw_domains)
 547 {
 548         assert_spin_locked(&dev_priv->uncore.lock);
 549
 550         if (!dev_priv->uncore.funcs.force_wake_put)
 551                 return;
 552
 553         __intel_uncore_forcewake_put(dev_priv, fw_domains);
 554 }
 555
 556 void assert_forcewakes_inactive(struct drm_i915_private *dev_priv)
 557 {
 558         struct intel_uncore_forcewake_domain *domain;
 559
 560         if (!dev_priv->uncore.funcs.force_wake_get)
 561                 return;
 562
 563         for_each_fw_domain(domain, dev_priv)
 564                 WARN_ON(domain->wake_count);
 565 }
 566
 567 /* We give fast paths for the really cool registers */
 568 #define NEEDS_FORCE_WAKE(reg) ((reg) < 0x40000)
 569
 570 #define __gen6_reg_read_fw_domains(offset) \
 571 ({ \
 572         enum forcewake_domains __fwd; \
 573         if (NEEDS_FORCE_WAKE(offset)) \
 574                 __fwd = FORCEWAKE_RENDER; \
 575         else \
 576                 __fwd = 0; \
 577         __fwd; \
 578 })
 579
 580 #define REG_RANGE(reg, start, end) ((reg) >= (start) && (reg) < (end))
 581
 582 #define FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg) \
 583         (REG_RANGE((reg), 0x2000, 0x4000) || \
 584          REG_RANGE((reg), 0x5000, 0x8000) || \
 585          REG_RANGE((reg), 0xB000, 0x12000) || \
 586          REG_RANGE((reg), 0x2E000, 0x30000))
 587
 588 #define FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg) \
 589         (REG_RANGE((reg), 0x12000, 0x14000) || \
 590          REG_RANGE((reg), 0x22000, 0x24000) || \
 591          REG_RANGE((reg), 0x30000, 0x40000))
 592
 593 #define __vlv_reg_read_fw_domains(offset) \
 594 ({ \
 595         enum forcewake_domains __fwd = 0; \
 596         if (!NEEDS_FORCE_WAKE(offset)) \
 597                 __fwd = 0; \
 598         else if (FORCEWAKE_VLV_RENDER_RANGE_OFFSET(offset)) \
 599                 __fwd = FORCEWAKE_RENDER; \
 600         else if (FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(offset)) \
 601                 __fwd = FORCEWAKE_MEDIA; \
 602         __fwd; \
 603 })
 604
 605 static const i915_reg_t gen8_shadowed_regs[] = {
 606         GEN6_RPNSWREQ,
 607         GEN6_RC_VIDEO_FREQ,
 608         RING_TAIL(RENDER_RING_BASE),
 609         RING_TAIL(GEN6_BSD_RING_BASE),
 610         RING_TAIL(VEBOX_RING_BASE),
 611         RING_TAIL(BLT_RING_BASE),
 612         /* TODO: Other registers are not yet used */
 613 };
 614
 615 static bool is_gen8_shadowed(u32 offset)
 616 {
 617         int i;
 618         for (i = 0; i < ARRAY_SIZE(gen8_shadowed_regs); i++)
 619                 if (offset == gen8_shadowed_regs[i].reg)
 620                         return true;
 621
 622         return false;
 623 }
 624
 625 #define __gen8_reg_write_fw_domains(offset) \
 626 ({ \
 627         enum forcewake_domains __fwd; \
 628         if (NEEDS_FORCE_WAKE(offset) && !is_gen8_shadowed(offset)) \
 629                 __fwd = FORCEWAKE_RENDER; \
 630         else \
 631                 __fwd = 0; \
 632         __fwd; \
 633 })
 634
 635 #define FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg) \
 636         (REG_RANGE((reg), 0x2000, 0x4000) || \
 637          REG_RANGE((reg), 0x5200, 0x8000) || \
 638          REG_RANGE((reg), 0x8300, 0x8500) || \
 639          REG_RANGE((reg), 0xB000, 0xB480) || \
 640          REG_RANGE((reg), 0xE000, 0xE800))
 641
 642 #define FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg) \
 643         (REG_RANGE((reg), 0x8800, 0x8900) || \
 644          REG_RANGE((reg), 0xD000, 0xD800) || \
 645          REG_RANGE((reg), 0x12000, 0x14000) || \
 646          REG_RANGE((reg), 0x1A000, 0x1C000) || \
 647          REG_RANGE((reg), 0x1E800, 0x1EA00) || \
 648          REG_RANGE((reg), 0x30000, 0x38000))
 649
 650 #define FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg) \
 651         (REG_RANGE((reg), 0x4000, 0x5000) || \
 652          REG_RANGE((reg), 0x8000, 0x8300) || \
 653          REG_RANGE((reg), 0x8500, 0x8600) || \
 654          REG_RANGE((reg), 0x9000, 0xB000) || \
 655          REG_RANGE((reg), 0xF000, 0x10000))
 656
 657 #define __chv_reg_read_fw_domains(offset) \
 658 ({ \
 659         enum forcewake_domains __fwd = 0; \
 660         if (!NEEDS_FORCE_WAKE(offset)) \
 661                 __fwd = 0; \
 662         else if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(offset)) \
 663                 __fwd = FORCEWAKE_RENDER; \
 664         else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(offset)) \
 665                 __fwd = FORCEWAKE_MEDIA; \
 666         else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(offset)) \
 667                 __fwd = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \
 668         __fwd; \
 669 })
 670
 671 #define __chv_reg_write_fw_domains(offset) \
 672 ({ \
 673         enum forcewake_domains __fwd = 0; \
 674         if (!NEEDS_FORCE_WAKE(offset) || is_gen8_shadowed(offset)) \
 675                 __fwd = 0; \
 676         else if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(offset)) \
 677                 __fwd = FORCEWAKE_RENDER; \
 678         else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(offset)) \
 679                 __fwd = FORCEWAKE_MEDIA; \
 680         else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(offset)) \
 681                 __fwd = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \
 682         __fwd; \
 683 })
 684
 685 #define FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg) \
 686         REG_RANGE((reg), 0xB00,  0x2000)
 687
 688 #define FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg) \
 689         (REG_RANGE((reg), 0x2000, 0x2700) || \
 690          REG_RANGE((reg), 0x3000, 0x4000) || \
 691          REG_RANGE((reg), 0x5200, 0x8000) || \
 692          REG_RANGE((reg), 0x8140, 0x8160) || \
 693          REG_RANGE((reg), 0x8300, 0x8500) || \
 694          REG_RANGE((reg), 0x8C00, 0x8D00) || \
 695          REG_RANGE((reg), 0xB000, 0xB480) || \
 696          REG_RANGE((reg), 0xE000, 0xE900) || \
 697          REG_RANGE((reg), 0x24400, 0x24800))
 698
 699 #define FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg) \
 700         (REG_RANGE((reg), 0x8130, 0x8140) || \
 701          REG_RANGE((reg), 0x8800, 0x8A00) || \
 702          REG_RANGE((reg), 0xD000, 0xD800) || \
 703          REG_RANGE((reg), 0x12000, 0x14000) || \
 704          REG_RANGE((reg), 0x1A000, 0x1EA00) || \
 705          REG_RANGE((reg), 0x30000, 0x40000))
 706
 707 #define FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg) \
 708         REG_RANGE((reg), 0x9400, 0x9800)
 709
 710 #define FORCEWAKE_GEN9_BLITTER_RANGE_OFFSET(reg) \
 711         ((reg) < 0x40000 && \
 712          !FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg) && \
 713          !FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg) && \
 714          !FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg) && \
 715          !FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg))
 716
 717 #define SKL_NEEDS_FORCE_WAKE(reg) \
 718         ((reg) < 0x40000 && !FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg))
 719
 720 #define __gen9_reg_read_fw_domains(offset) \
 721 ({ \
 722         enum forcewake_domains __fwd; \
 723         if (!SKL_NEEDS_FORCE_WAKE(offset)) \
 724                 __fwd = 0; \
 725         else if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(offset)) \
 726                 __fwd = FORCEWAKE_RENDER; \
 727         else if (FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(offset)) \
 728                 __fwd = FORCEWAKE_MEDIA; \
 729         else if (FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(offset)) \
 730                 __fwd = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \
 731         else \
 732                 __fwd = FORCEWAKE_BLITTER; \
 733         __fwd; \
 734 })
 735
 736 static const i915_reg_t gen9_shadowed_regs[] = {
 737         RING_TAIL(RENDER_RING_BASE),
 738         RING_TAIL(GEN6_BSD_RING_BASE),
 739         RING_TAIL(VEBOX_RING_BASE),
 740         RING_TAIL(BLT_RING_BASE),
 741         GEN6_RPNSWREQ,
 742         GEN6_RC_VIDEO_FREQ,
 743         /* TODO: Other registers are not yet used */
 744 };
 745
 746 static bool is_gen9_shadowed(u32 offset)
 747 {
 748         int i;
 749         for (i = 0; i < ARRAY_SIZE(gen9_shadowed_regs); i++)
 750                 if (offset == gen9_shadowed_regs[i].reg)
 751                         return true;
 752
 753         return false;
 754 }
 755
 756 #define __gen9_reg_write_fw_domains(offset) \
 757 ({ \
 758         enum forcewake_domains __fwd; \
 759         if (!SKL_NEEDS_FORCE_WAKE(offset) || is_gen9_shadowed(offset)) \
 760                 __fwd = 0; \
 761         else if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(offset)) \
 762                 __fwd = FORCEWAKE_RENDER; \
 763         else if (FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(offset)) \
 764                 __fwd = FORCEWAKE_MEDIA; \
 765         else if (FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(offset)) \
 766                 __fwd = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \
 767         else \
 768                 __fwd = FORCEWAKE_BLITTER; \
 769         __fwd; \
 770 })
 771
 772 static void
 773 ilk_dummy_write(struct drm_i915_private *dev_priv)
 774 {
 775         /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up
 776          * the chip from rc6 before touching it for real. MI_MODE is masked,
 777          * hence harmless to write 0 into. */
 778         __raw_i915_write32(dev_priv, MI_MODE, 0);
 779 }
 780
 781 static void
 782 __unclaimed_reg_debug(struct drm_i915_private *dev_priv,
 783                       const i915_reg_t reg,
 784                       const bool read,
 785                       const bool before)
 786 {
 787         if (WARN(check_for_unclaimed_mmio(dev_priv),
 788                  "Unclaimed register detected %s %s register 0x%x\n",
 789                  before ? "before" : "after",
 790                  read ? "reading" : "writing to",
 791                  i915_mmio_reg_offset(reg)))
 792                 i915.mmio_debug--; /* Only report the first N failures */
 793 }
 794
 795 static inline void
 796 unclaimed_reg_debug(struct drm_i915_private *dev_priv,
 797                     const i915_reg_t reg,
 798                     const bool read,
 799                     const bool before)
 800 {
 801         if (likely(!i915.mmio_debug))
 802                 return;
 803
 804         __unclaimed_reg_debug(dev_priv, reg, read, before);
 805 }
 806
 807 #define GEN2_READ_HEADER(x) \
 808         u##x val = 0; \
 809         assert_rpm_wakelock_held(dev_priv);
 810
 811 #define GEN2_READ_FOOTER \
 812         trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
 813         return val
 814
 815 #define __gen2_read(x) \
 816 static u##x \
 817 gen2_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
 818         GEN2_READ_HEADER(x); \
 819         val = __raw_i915_read##x(dev_priv, reg); \
 820         GEN2_READ_FOOTER; \
 821 }
 822
 823 #define __gen5_read(x) \
 824 static u##x \
 825 gen5_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
 826         GEN2_READ_HEADER(x); \
 827         ilk_dummy_write(dev_priv); \
 828         val = __raw_i915_read##x(dev_priv, reg); \
 829         GEN2_READ_FOOTER; \
 830 }
 831
 832 __gen5_read(8)
 833 __gen5_read(16)
 834 __gen5_read(32)
 835 __gen5_read(64)
 836 __gen2_read(8)
 837 __gen2_read(16)
 838 __gen2_read(32)
 839 __gen2_read(64)
 840
 841 #undef __gen5_read
 842 #undef __gen2_read
 843
 844 #undef GEN2_READ_FOOTER
 845 #undef GEN2_READ_HEADER
 846
 847 #define GEN6_READ_HEADER(x) \
 848         u32 offset = i915_mmio_reg_offset(reg); \
 849         unsigned long irqflags; \
 850         u##x val = 0; \
 851         assert_rpm_wakelock_held(dev_priv); \
 852         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); \
 853         unclaimed_reg_debug(dev_priv, reg, true, true)
 854
 855 #define GEN6_READ_FOOTER \
 856         unclaimed_reg_debug(dev_priv, reg, true, false); \
 857         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
 858         trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
 859         return val
 860
 861 static inline void __force_wake_auto(struct drm_i915_private *dev_priv,
 862                                      enum forcewake_domains fw_domains)
 863 {
 864         struct intel_uncore_forcewake_domain *domain;
 865
 866         if (WARN_ON(!fw_domains))
 867                 return;
 868
 869         /* Ideally GCC would be constant-fold and eliminate this loop */
 870         for_each_fw_domain_masked(domain, fw_domains, dev_priv) {
 871                 if (domain->wake_count) {
 872                         fw_domains &= ~domain->mask;
 873                         continue;
 874                 }
 875
 876                 fw_domain_arm_timer(domain);
 877         }
 878
 879         if (fw_domains)
 880                 dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains);
 881 }
 882
 883 #define __gen6_read(x) \
 884 static u##x \
 885 gen6_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
 886         enum forcewake_domains fw_engine; \
 887         GEN6_READ_HEADER(x); \
 888         fw_engine = __gen6_reg_read_fw_domains(offset); \
 889         if (fw_engine) \
 890                 __force_wake_auto(dev_priv, fw_engine); \
 891         val = __raw_i915_read##x(dev_priv, reg); \
 892         GEN6_READ_FOOTER; \
 893 }
 894
 895 #define __vlv_read(x) \
 896 static u##x \
 897 vlv_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
 898         enum forcewake_domains fw_engine; \
 899         GEN6_READ_HEADER(x); \
 900         fw_engine = __vlv_reg_read_fw_domains(offset); \
 901         if (fw_engine) \
 902                 __force_wake_auto(dev_priv, fw_engine); \
 903         val = __raw_i915_read##x(dev_priv, reg); \
 904         GEN6_READ_FOOTER; \
 905 }
 906
 907 #define __chv_read(x) \
 908 static u##x \
 909 chv_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
 910         enum forcewake_domains fw_engine; \
 911         GEN6_READ_HEADER(x); \
 912         fw_engine = __chv_reg_read_fw_domains(offset); \
 913         if (fw_engine) \
 914                 __force_wake_auto(dev_priv, fw_engine); \
 915         val = __raw_i915_read##x(dev_priv, reg); \
 916         GEN6_READ_FOOTER; \
 917 }
 918
 919 #define __gen9_read(x) \
 920 static u##x \
 921 gen9_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
 922         enum forcewake_domains fw_engine; \
 923         GEN6_READ_HEADER(x); \
 924         fw_engine = __gen9_reg_read_fw_domains(offset); \
 925         if (fw_engine) \
 926                 __force_wake_auto(dev_priv, fw_engine); \
 927         val = __raw_i915_read##x(dev_priv, reg); \
 928         GEN6_READ_FOOTER; \
 929 }
 930
 931 __gen9_read(8)
 932 __gen9_read(16)
 933 __gen9_read(32)
 934 __gen9_read(64)
 935 __chv_read(8)
 936 __chv_read(16)
 937 __chv_read(32)
 938 __chv_read(64)
 939 __vlv_read(8)
 940 __vlv_read(16)
 941 __vlv_read(32)
 942 __vlv_read(64)
 943 __gen6_read(8)
 944 __gen6_read(16)
 945 __gen6_read(32)
 946 __gen6_read(64)
 947
 948 #undef __gen9_read
 949 #undef __chv_read
 950 #undef __vlv_read
 951 #undef __gen6_read
 952 #undef GEN6_READ_FOOTER
 953 #undef GEN6_READ_HEADER
 954
 955 #define VGPU_READ_HEADER(x) \
 956         unsigned long irqflags; \
 957         u##x val = 0; \
 958         assert_rpm_device_not_suspended(dev_priv); \
 959         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
 960
 961 #define VGPU_READ_FOOTER \
 962         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
 963         trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
 964         return val
 965
 966 #define __vgpu_read(x) \
 967 static u##x \
 968 vgpu_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
 969         VGPU_READ_HEADER(x); \
 970         val = __raw_i915_read##x(dev_priv, reg); \
 971         VGPU_READ_FOOTER; \
 972 }
 973
 974 __vgpu_read(8)
 975 __vgpu_read(16)
 976 __vgpu_read(32)
 977 __vgpu_read(64)
 978
 979 #undef __vgpu_read
 980 #undef VGPU_READ_FOOTER
 981 #undef VGPU_READ_HEADER
 982
 983 #define GEN2_WRITE_HEADER \
 984         trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
 985         assert_rpm_wakelock_held(dev_priv); \
 986
 987 #define GEN2_WRITE_FOOTER
 988
 989 #define __gen2_write(x) \
 990 static void \
 991 gen2_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
 992         GEN2_WRITE_HEADER; \
 993         __raw_i915_write##x(dev_priv, reg, val); \
 994         GEN2_WRITE_FOOTER; \
 995 }
 996
 997 #define __gen5_write(x) \
 998 static void \
 999 gen5_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
1000         GEN2_WRITE_HEADER; \
1001         ilk_dummy_write(dev_priv); \
1002         __raw_i915_write##x(dev_priv, reg, val); \
1003         GEN2_WRITE_FOOTER; \
1004 }
1005
1006 __gen5_write(8)
1007 __gen5_write(16)
1008 __gen5_write(32)
1009 __gen5_write(64)
1010 __gen2_write(8)
1011 __gen2_write(16)
1012 __gen2_write(32)
1013 __gen2_write(64)
1014
1015 #undef __gen5_write
1016 #undef __gen2_write
1017
1018 #undef GEN2_WRITE_FOOTER
1019 #undef GEN2_WRITE_HEADER
1020
1021 #define GEN6_WRITE_HEADER \
1022         u32 offset = i915_mmio_reg_offset(reg); \
1023         unsigned long irqflags; \
1024         trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
1025         assert_rpm_wakelock_held(dev_priv); \
1026         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); \
1027         unclaimed_reg_debug(dev_priv, reg, false, true)
1028
1029 #define GEN6_WRITE_FOOTER \
1030         unclaimed_reg_debug(dev_priv, reg, false, false); \
1031         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags)
1032
1033 #define __gen6_write(x) \
1034 static void \
1035 gen6_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
1036         u32 __fifo_ret = 0; \
1037         GEN6_WRITE_HEADER; \
1038         if (NEEDS_FORCE_WAKE(offset)) { \
1039                 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
1040         } \
1041         __raw_i915_write##x(dev_priv, reg, val); \
1042         if (unlikely(__fifo_ret)) { \
1043                 gen6_gt_check_fifodbg(dev_priv); \
1044         } \
1045         GEN6_WRITE_FOOTER; \
1046 }
1047
1048 #define __hsw_write(x) \
1049 static void \
1050 hsw_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
1051         u32 __fifo_ret = 0; \
1052         GEN6_WRITE_HEADER; \
1053         if (NEEDS_FORCE_WAKE(offset)) { \
1054                 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
1055         } \
1056         __raw_i915_write##x(dev_priv, reg, val); \
1057         if (unlikely(__fifo_ret)) { \
1058                 gen6_gt_check_fifodbg(dev_priv); \
1059         } \
1060         GEN6_WRITE_FOOTER; \
1061 }
1062
1063 #define __gen8_write(x) \
1064 static void \
1065 gen8_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
1066         enum forcewake_domains fw_engine; \
1067         GEN6_WRITE_HEADER; \
1068         fw_engine = __gen8_reg_write_fw_domains(offset); \
1069         if (fw_engine) \
1070                 __force_wake_auto(dev_priv, fw_engine); \
1071         __raw_i915_write##x(dev_priv, reg, val); \
1072         GEN6_WRITE_FOOTER; \
1073 }
1074
1075 #define __chv_write(x) \
1076 static void \
1077 chv_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
1078         enum forcewake_domains fw_engine; \
1079         GEN6_WRITE_HEADER; \
1080         fw_engine = __chv_reg_write_fw_domains(offset); \
1081         if (fw_engine) \
1082                 __force_wake_auto(dev_priv, fw_engine); \
1083         __raw_i915_write##x(dev_priv, reg, val); \
1084         GEN6_WRITE_FOOTER; \
1085 }
1086
1087 #define __gen9_write(x) \
1088 static void \
1089 gen9_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, \
1090                 bool trace) { \
1091         enum forcewake_domains fw_engine; \
1092         GEN6_WRITE_HEADER; \
1093         fw_engine = __gen9_reg_write_fw_domains(offset); \
1094         if (fw_engine) \
1095                 __force_wake_auto(dev_priv, fw_engine); \
1096         __raw_i915_write##x(dev_priv, reg, val); \
1097         GEN6_WRITE_FOOTER; \
1098 }
1099
1100 __gen9_write(8)
1101 __gen9_write(16)
1102 __gen9_write(32)
1103 __gen9_write(64)
1104 __chv_write(8)
1105 __chv_write(16)
1106 __chv_write(32)
1107 __chv_write(64)
1108 __gen8_write(8)
1109 __gen8_write(16)
1110 __gen8_write(32)
1111 __gen8_write(64)
1112 __hsw_write(8)
1113 __hsw_write(16)
1114 __hsw_write(32)
1115 __hsw_write(64)
1116 __gen6_write(8)
1117 __gen6_write(16)
1118 __gen6_write(32)
1119 __gen6_write(64)
1120
1121 #undef __gen9_write
1122 #undef __chv_write
1123 #undef __gen8_write
1124 #undef __hsw_write
1125 #undef __gen6_write
1126 #undef GEN6_WRITE_FOOTER
1127 #undef GEN6_WRITE_HEADER
1128
1129 #define VGPU_WRITE_HEADER \
1130         unsigned long irqflags; \
1131         trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
1132         assert_rpm_device_not_suspended(dev_priv); \
1133         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
1134
1135 #define VGPU_WRITE_FOOTER \
1136         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags)
1137
1138 #define __vgpu_write(x) \
1139 static void vgpu_write##x(struct drm_i915_private *dev_priv, \
1140                           i915_reg_t reg, u##x val, bool trace) { \
1141         VGPU_WRITE_HEADER; \
1142         __raw_i915_write##x(dev_priv, reg, val); \
1143         VGPU_WRITE_FOOTER; \
1144 }
1145
1146 __vgpu_write(8)
1147 __vgpu_write(16)
1148 __vgpu_write(32)
1149 __vgpu_write(64)
1150
1151 #undef __vgpu_write
1152 #undef VGPU_WRITE_FOOTER
1153 #undef VGPU_WRITE_HEADER
1154
1155 #define ASSIGN_WRITE_MMIO_VFUNCS(x) \
1156 do { \
1157         dev_priv->uncore.funcs.mmio_writeb = x##_write8; \
1158         dev_priv->uncore.funcs.mmio_writew = x##_write16; \
1159         dev_priv->uncore.funcs.mmio_writel = x##_write32; \
1160         dev_priv->uncore.funcs.mmio_writeq = x##_write64; \
1161 } while (0)
1162
1163 #define ASSIGN_READ_MMIO_VFUNCS(x) \
1164 do { \
1165         dev_priv->uncore.funcs.mmio_readb = x##_read8; \
1166         dev_priv->uncore.funcs.mmio_readw = x##_read16; \
1167         dev_priv->uncore.funcs.mmio_readl = x##_read32; \
1168         dev_priv->uncore.funcs.mmio_readq = x##_read64; \
1169 } while (0)
1170
1171
1172 static void fw_domain_init(struct drm_i915_private *dev_priv,
1173                            enum forcewake_domain_id domain_id,
1174                            i915_reg_t reg_set,
1175                            i915_reg_t reg_ack)
1176 {
1177         struct intel_uncore_forcewake_domain *d;
1178
1179         if (WARN_ON(domain_id >= FW_DOMAIN_ID_COUNT))
1180                 return;
1181
1182         d = &dev_priv->uncore.fw_domain[domain_id];
1183
1184         WARN_ON(d->wake_count);
1185
1186         d->wake_count = 0;
1187         d->reg_set = reg_set;
1188         d->reg_ack = reg_ack;
1189
1190         if (IS_GEN6(dev_priv)) {
1191                 d->val_reset = 0;
1192                 d->val_set = FORCEWAKE_KERNEL;
1193                 d->val_clear = 0;
1194         } else {
1195                 /* WaRsClearFWBitsAtReset:bdw,skl */
1196                 d->val_reset = _MASKED_BIT_DISABLE(0xffff);
1197                 d->val_set = _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL);
1198                 d->val_clear = _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL);
1199         }
1200
1201         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1202                 d->reg_post = FORCEWAKE_ACK_VLV;
1203         else if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv) || IS_GEN8(dev_priv))
1204                 d->reg_post = ECOBUS;
1205
1206         d->i915 = dev_priv;
1207         d->id = domain_id;
1208
1209         BUILD_BUG_ON(FORCEWAKE_RENDER != (1 << FW_DOMAIN_ID_RENDER));
1210         BUILD_BUG_ON(FORCEWAKE_BLITTER != (1 << FW_DOMAIN_ID_BLITTER));
1211         BUILD_BUG_ON(FORCEWAKE_MEDIA != (1 << FW_DOMAIN_ID_MEDIA));
1212
1213         d->mask = 1 << domain_id;
1214
1215         hrtimer_init(&d->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
1216         d->timer.function = intel_uncore_fw_release_timer;
1217
1218         dev_priv->uncore.fw_domains |= (1 << domain_id);
1219
1220         fw_domain_reset(d);
1221 }
1222
1223 static void intel_uncore_fw_domains_init(struct drm_device *dev)
1224 {
1225         struct drm_i915_private *dev_priv = dev->dev_private;
1226
1227         if (INTEL_INFO(dev_priv)->gen <= 5)
1228                 return;
1229
1230         if (IS_GEN9(dev)) {
1231                 dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
1232                 dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
1233                 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1234                                FORCEWAKE_RENDER_GEN9,
1235                                FORCEWAKE_ACK_RENDER_GEN9);
1236                 fw_domain_init(dev_priv, FW_DOMAIN_ID_BLITTER,
1237                                FORCEWAKE_BLITTER_GEN9,
1238                                FORCEWAKE_ACK_BLITTER_GEN9);
1239                 fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA,
1240                                FORCEWAKE_MEDIA_GEN9, FORCEWAKE_ACK_MEDIA_GEN9);
1241         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1242                 dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
1243                 if (!IS_CHERRYVIEW(dev))
1244                         dev_priv->uncore.funcs.force_wake_put =
1245                                 fw_domains_put_with_fifo;
1246                 else
1247                         dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
1248                 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1249                                FORCEWAKE_VLV, FORCEWAKE_ACK_VLV);
1250                 fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA,
1251                                FORCEWAKE_MEDIA_VLV, FORCEWAKE_ACK_MEDIA_VLV);
1252         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1253                 dev_priv->uncore.funcs.force_wake_get =
1254                         fw_domains_get_with_thread_status;
1255                 dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
1256                 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1257                                FORCEWAKE_MT, FORCEWAKE_ACK_HSW);
1258         } else if (IS_IVYBRIDGE(dev)) {
1259                 u32 ecobus;
1260
1261                 /* IVB configs may use multi-threaded forcewake */
1262
1263                 /* A small trick here - if the bios hasn't configured
1264                  * MT forcewake, and if the device is in RC6, then
1265                  * force_wake_mt_get will not wake the device and the
1266                  * ECOBUS read will return zero. Which will be
1267                  * (correctly) interpreted by the test below as MT
1268                  * forcewake being disabled.
1269                  */
1270                 dev_priv->uncore.funcs.force_wake_get =
1271                         fw_domains_get_with_thread_status;
1272                 dev_priv->uncore.funcs.force_wake_put =
1273                         fw_domains_put_with_fifo;
1274
1275                 /* We need to init first for ECOBUS access and then
1276                  * determine later if we want to reinit, in case of MT access is
1277                  * not working. In this stage we don't know which flavour this
1278                  * ivb is, so it is better to reset also the gen6 fw registers
1279                  * before the ecobus check.
1280                  */
1281
1282                 __raw_i915_write32(dev_priv, FORCEWAKE, 0);
1283                 __raw_posting_read(dev_priv, ECOBUS);
1284
1285                 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1286                                FORCEWAKE_MT, FORCEWAKE_MT_ACK);
1287
1288                 mutex_lock(&dev->struct_mutex);
1289                 fw_domains_get_with_thread_status(dev_priv, FORCEWAKE_ALL);
1290                 ecobus = __raw_i915_read32(dev_priv, ECOBUS);
1291                 fw_domains_put_with_fifo(dev_priv, FORCEWAKE_ALL);
1292                 mutex_unlock(&dev->struct_mutex);
1293
1294                 if (!(ecobus & FORCEWAKE_MT_ENABLE)) {
1295                         DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n");
1296                         DRM_INFO("when using vblank-synced partial screen updates.\n");
1297                         fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1298                                        FORCEWAKE, FORCEWAKE_ACK);
1299                 }
1300         } else if (IS_GEN6(dev)) {
1301                 dev_priv->uncore.funcs.force_wake_get =
1302                         fw_domains_get_with_thread_status;
1303                 dev_priv->uncore.funcs.force_wake_put =
1304                         fw_domains_put_with_fifo;
1305                 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1306                                FORCEWAKE, FORCEWAKE_ACK);
1307         }
1308
1309         /* All future platforms are expected to require complex power gating */
1310         WARN_ON(dev_priv->uncore.fw_domains == 0);
1311 }
1312
1313 void intel_uncore_init(struct drm_device *dev)
1314 {
1315         struct drm_i915_private *dev_priv = dev->dev_private;
1316
1317         i915_check_vgpu(dev);
1318
1319         intel_uncore_edram_detect(dev_priv);
1320         intel_uncore_fw_domains_init(dev);
1321         __intel_uncore_early_sanitize(dev, false);
1322
1323         dev_priv->uncore.unclaimed_mmio_check = 1;
1324
1325         switch (INTEL_INFO(dev)->gen) {
1326         default:
1327         case 9:
1328                 ASSIGN_WRITE_MMIO_VFUNCS(gen9);
1329                 ASSIGN_READ_MMIO_VFUNCS(gen9);
1330                 break;
1331         case 8:
1332                 if (IS_CHERRYVIEW(dev)) {
1333                         ASSIGN_WRITE_MMIO_VFUNCS(chv);
1334                         ASSIGN_READ_MMIO_VFUNCS(chv);
1335
1336                 } else {
1337                         ASSIGN_WRITE_MMIO_VFUNCS(gen8);
1338                         ASSIGN_READ_MMIO_VFUNCS(gen6);
1339                 }
1340                 break;
1341         case 7:
1342         case 6:
1343                 if (IS_HASWELL(dev)) {
1344                         ASSIGN_WRITE_MMIO_VFUNCS(hsw);
1345                 } else {
1346                         ASSIGN_WRITE_MMIO_VFUNCS(gen6);
1347                 }
1348
1349                 if (IS_VALLEYVIEW(dev)) {
1350                         ASSIGN_READ_MMIO_VFUNCS(vlv);
1351                 } else {
1352                         ASSIGN_READ_MMIO_VFUNCS(gen6);
1353                 }
1354                 break;
1355         case 5:
1356                 ASSIGN_WRITE_MMIO_VFUNCS(gen5);
1357                 ASSIGN_READ_MMIO_VFUNCS(gen5);
1358                 break;
1359         case 4:
1360         case 3:
1361         case 2:
1362                 ASSIGN_WRITE_MMIO_VFUNCS(gen2);
1363                 ASSIGN_READ_MMIO_VFUNCS(gen2);
1364                 break;
1365         }
1366
1367         if (intel_vgpu_active(dev)) {
1368                 ASSIGN_WRITE_MMIO_VFUNCS(vgpu);
1369                 ASSIGN_READ_MMIO_VFUNCS(vgpu);
1370         }
1371
1372         i915_check_and_clear_faults(dev);
1373 }
1374 #undef ASSIGN_WRITE_MMIO_VFUNCS
1375 #undef ASSIGN_READ_MMIO_VFUNCS
1376
1377 void intel_uncore_fini(struct drm_device *dev)
1378 {
1379         /* Paranoia: make sure we have disabled everything before we exit. */
1380         intel_uncore_sanitize(dev);
1381         intel_uncore_forcewake_reset(dev, false);
1382 }
1383
1384 #define GEN_RANGE(l, h) GENMASK(h, l)
1385
1386 static const struct register_whitelist {
1387         i915_reg_t offset_ldw, offset_udw;
1388         uint32_t size;
1389         /* supported gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
1390         uint32_t gen_bitmask;
1391 } whitelist[] = {
1392         { .offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE),
1393           .offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE),
1394           .size = 8, .gen_bitmask = GEN_RANGE(4, 9) },
1395 };
1396
1397 int i915_reg_read_ioctl(struct drm_device *dev,
1398                         void *data, struct drm_file *file)
1399 {
1400         struct drm_i915_private *dev_priv = dev->dev_private;
1401         struct drm_i915_reg_read *reg = data;
1402         struct register_whitelist const *entry = whitelist;
1403         unsigned size;
1404         i915_reg_t offset_ldw, offset_udw;
1405         int i, ret = 0;
1406
1407         for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) {
1408                 if (i915_mmio_reg_offset(entry->offset_ldw) == (reg->offset & -entry->size) &&
1409                     (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask))
1410                         break;
1411         }
1412
1413         if (i == ARRAY_SIZE(whitelist))
1414                 return -EINVAL;
1415
1416         /* We use the low bits to encode extra flags as the register should
1417          * be naturally aligned (and those that are not so aligned merely
1418          * limit the available flags for that register).
1419          */
1420         offset_ldw = entry->offset_ldw;
1421         offset_udw = entry->offset_udw;
1422         size = entry->size;
1423         size |= reg->offset ^ i915_mmio_reg_offset(offset_ldw);
1424
1425         intel_runtime_pm_get(dev_priv);
1426
1427         switch (size) {
1428         case 8 | 1:
1429                 reg->val = I915_READ64_2x32(offset_ldw, offset_udw);
1430                 break;
1431         case 8:
1432                 reg->val = I915_READ64(offset_ldw);
1433                 break;
1434         case 4:
1435                 reg->val = I915_READ(offset_ldw);
1436                 break;
1437         case 2:
1438                 reg->val = I915_READ16(offset_ldw);
1439                 break;
1440         case 1:
1441                 reg->val = I915_READ8(offset_ldw);
1442                 break;
1443         default:
1444                 ret = -EINVAL;
1445                 goto out;
1446         }
1447
1448 out:
1449         intel_runtime_pm_put(dev_priv);
1450         return ret;
1451 }
1452
1453 int i915_get_reset_stats_ioctl(struct drm_device *dev,
1454                                void *data, struct drm_file *file)
1455 {
1456         struct drm_i915_private *dev_priv = dev->dev_private;
1457         struct drm_i915_reset_stats *args = data;
1458         struct i915_ctx_hang_stats *hs;
1459         struct intel_context *ctx;
1460         int ret;
1461
1462         if (args->flags || args->pad)
1463                 return -EINVAL;
1464
1465         if (args->ctx_id == DEFAULT_CONTEXT_HANDLE && !capable(CAP_SYS_ADMIN))
1466                 return -EPERM;
1467
1468         ret = mutex_lock_interruptible(&dev->struct_mutex);
1469         if (ret)
1470                 return ret;
1471
1472         ctx = i915_gem_context_get(file->driver_priv, args->ctx_id);
1473         if (IS_ERR(ctx)) {
1474                 mutex_unlock(&dev->struct_mutex);
1475                 return PTR_ERR(ctx);
1476         }
1477         hs = &ctx->hang_stats;
1478
1479         if (capable(CAP_SYS_ADMIN))
1480                 args->reset_count = i915_reset_count(&dev_priv->gpu_error);
1481         else
1482                 args->reset_count = 0;
1483
1484         args->batch_active = hs->batch_active;
1485         args->batch_pending = hs->batch_pending;
1486
1487         mutex_unlock(&dev->struct_mutex);
1488
1489         return 0;
1490 }
1491
1492 static int i915_reset_complete(struct drm_device *dev)
1493 {
1494         u8 gdrst;
1495         pci_read_config_byte(dev->pdev, I915_GDRST, &gdrst);
1496         return (gdrst & GRDOM_RESET_STATUS) == 0;
1497 }
1498
1499 static int i915_do_reset(struct drm_device *dev, unsigned engine_mask)
1500 {
1501         /* assert reset for at least 20 usec */
1502         pci_write_config_byte(dev->pdev, I915_GDRST, GRDOM_RESET_ENABLE);
1503         udelay(20);
1504         pci_write_config_byte(dev->pdev, I915_GDRST, 0);
1505
1506         return wait_for(i915_reset_complete(dev), 500);
1507 }
1508
1509 static int g4x_reset_complete(struct drm_device *dev)
1510 {
1511         u8 gdrst;
1512         pci_read_config_byte(dev->pdev, I915_GDRST, &gdrst);
1513         return (gdrst & GRDOM_RESET_ENABLE) == 0;
1514 }
1515
1516 static int g33_do_reset(struct drm_device *dev, unsigned engine_mask)
1517 {
1518         pci_write_config_byte(dev->pdev, I915_GDRST, GRDOM_RESET_ENABLE);
1519         return wait_for(g4x_reset_complete(dev), 500);
1520 }
1521
1522 static int g4x_do_reset(struct drm_device *dev, unsigned engine_mask)
1523 {
1524         struct drm_i915_private *dev_priv = dev->dev_private;
1525         int ret;
1526
1527         pci_write_config_byte(dev->pdev, I915_GDRST,
1528                               GRDOM_RENDER | GRDOM_RESET_ENABLE);
1529         ret =  wait_for(g4x_reset_complete(dev), 500);
1530         if (ret)
1531                 return ret;
1532
1533         /* WaVcpClkGateDisableForMediaReset:ctg,elk */
1534         I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) | VCP_UNIT_CLOCK_GATE_DISABLE);
1535         POSTING_READ(VDECCLK_GATE_D);
1536
1537         pci_write_config_byte(dev->pdev, I915_GDRST,
1538                               GRDOM_MEDIA | GRDOM_RESET_ENABLE);
1539         ret =  wait_for(g4x_reset_complete(dev), 500);
1540         if (ret)
1541                 return ret;
1542
1543         /* WaVcpClkGateDisableForMediaReset:ctg,elk */
1544         I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) & ~VCP_UNIT_CLOCK_GATE_DISABLE);
1545         POSTING_READ(VDECCLK_GATE_D);
1546
1547         pci_write_config_byte(dev->pdev, I915_GDRST, 0);
1548
1549         return 0;
1550 }
1551
1552 static int ironlake_do_reset(struct drm_device *dev, unsigned engine_mask)
1553 {
1554         struct drm_i915_private *dev_priv = dev->dev_private;
1555         int ret;
1556
1557         I915_WRITE(ILK_GDSR,
1558                    ILK_GRDOM_RENDER | ILK_GRDOM_RESET_ENABLE);
1559         ret = wait_for((I915_READ(ILK_GDSR) &
1560                         ILK_GRDOM_RESET_ENABLE) == 0, 500);
1561         if (ret)
1562                 return ret;
1563
1564         I915_WRITE(ILK_GDSR,
1565                    ILK_GRDOM_MEDIA | ILK_GRDOM_RESET_ENABLE);
1566         ret = wait_for((I915_READ(ILK_GDSR) &
1567                         ILK_GRDOM_RESET_ENABLE) == 0, 500);
1568         if (ret)
1569                 return ret;
1570
1571         I915_WRITE(ILK_GDSR, 0);
1572
1573         return 0;
1574 }
1575
1576 /* Reset the hardware domains (GENX_GRDOM_*) specified by mask */
1577 static int gen6_hw_domain_reset(struct drm_i915_private *dev_priv,
1578                                 u32 hw_domain_mask)
1579 {
1580         int ret;
1581
1582         /* GEN6_GDRST is not in the gt power well, no need to check
1583          * for fifo space for the write or forcewake the chip for
1584          * the read
1585          */
1586         __raw_i915_write32(dev_priv, GEN6_GDRST, hw_domain_mask);
1587
1588 #define ACKED ((__raw_i915_read32(dev_priv, GEN6_GDRST) & hw_domain_mask) == 0)
1589         /* Spin waiting for the device to ack the reset requests */
1590         ret = wait_for(ACKED, 500);
1591 #undef ACKED
1592
1593         return ret;
1594 }
1595
1596 /**
1597  * gen6_reset_engines - reset individual engines
1598  * @dev: DRM device
1599  * @engine_mask: mask of intel_ring_flag() engines or ALL_ENGINES for full reset
1600  *
1601  * This function will reset the individual engines that are set in engine_mask.
1602  * If you provide ALL_ENGINES as mask, full global domain reset will be issued.
1603  *
1604  * Note: It is responsibility of the caller to handle the difference between
1605  * asking full domain reset versus reset for all available individual engines.
1606  *
1607  * Returns 0 on success, nonzero on error.
1608  */
1609 static int gen6_reset_engines(struct drm_device *dev, unsigned engine_mask)
1610 {
1611         struct drm_i915_private *dev_priv = dev->dev_private;
1612         struct intel_engine_cs *engine;
1613         const u32 hw_engine_mask[I915_NUM_ENGINES] = {
1614                 [RCS] = GEN6_GRDOM_RENDER,
1615                 [BCS] = GEN6_GRDOM_BLT,
1616                 [VCS] = GEN6_GRDOM_MEDIA,
1617                 [VCS2] = GEN8_GRDOM_MEDIA2,
1618                 [VECS] = GEN6_GRDOM_VECS,
1619         };
1620         u32 hw_mask;
1621         int ret;
1622
1623         if (engine_mask == ALL_ENGINES) {
1624                 hw_mask = GEN6_GRDOM_FULL;
1625         } else {
1626                 hw_mask = 0;
1627                 for_each_engine_masked(engine, dev_priv, engine_mask)
1628                         hw_mask |= hw_engine_mask[engine->id];
1629         }
1630
1631         ret = gen6_hw_domain_reset(dev_priv, hw_mask);
1632
1633         intel_uncore_forcewake_reset(dev, true);
1634
1635         return ret;
1636 }
1637
1638 static int wait_for_register_fw(struct drm_i915_private *dev_priv,
1639                                 i915_reg_t reg,
1640                                 const u32 mask,
1641                                 const u32 value,
1642                                 const unsigned long timeout_ms)
1643 {
1644         return wait_for((I915_READ_FW(reg) & mask) == value, timeout_ms);
1645 }
1646
1647 static int gen8_request_engine_reset(struct intel_engine_cs *engine)
1648 {
1649         int ret;
1650         struct drm_i915_private *dev_priv = engine->dev->dev_private;
1651
1652         I915_WRITE_FW(RING_RESET_CTL(engine->mmio_base),
1653                       _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET));
1654
1655         ret = wait_for_register_fw(dev_priv,
1656                                    RING_RESET_CTL(engine->mmio_base),
1657                                    RESET_CTL_READY_TO_RESET,
1658                                    RESET_CTL_READY_TO_RESET,
1659                                    700);
1660         if (ret)
1661                 DRM_ERROR("%s: reset request timeout\n", engine->name);
1662
1663         return ret;
1664 }
1665
1666 static void gen8_unrequest_engine_reset(struct intel_engine_cs *engine)
1667 {
1668         struct drm_i915_private *dev_priv = engine->dev->dev_private;
1669
1670         I915_WRITE_FW(RING_RESET_CTL(engine->mmio_base),
1671                       _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET));
1672 }
1673
1674 static int gen8_reset_engines(struct drm_device *dev, unsigned engine_mask)
1675 {
1676         struct drm_i915_private *dev_priv = dev->dev_private;
1677         struct intel_engine_cs *engine;
1678
1679         for_each_engine_masked(engine, dev_priv, engine_mask)
1680                 if (gen8_request_engine_reset(engine))
1681                         goto not_ready;
1682
1683         return gen6_reset_engines(dev, engine_mask);
1684
1685 not_ready:
1686         for_each_engine_masked(engine, dev_priv, engine_mask)
1687                 gen8_unrequest_engine_reset(engine);
1688
1689         return -EIO;
1690 }
1691
1692 static int (*intel_get_gpu_reset(struct drm_device *dev))(struct drm_device *,
1693                                                           unsigned engine_mask)
1694 {
1695         if (!i915.reset)
1696                 return NULL;
1697
1698         if (INTEL_INFO(dev)->gen >= 8)
1699                 return gen8_reset_engines;
1700         else if (INTEL_INFO(dev)->gen >= 6)
1701                 return gen6_reset_engines;
1702         else if (IS_GEN5(dev))
1703                 return ironlake_do_reset;
1704         else if (IS_G4X(dev))
1705                 return g4x_do_reset;
1706         else if (IS_G33(dev))
1707                 return g33_do_reset;
1708         else if (INTEL_INFO(dev)->gen >= 3)
1709                 return i915_do_reset;
1710         else
1711                 return NULL;
1712 }
1713
1714 int intel_gpu_reset(struct drm_device *dev, unsigned engine_mask)
1715 {
1716         struct drm_i915_private *dev_priv = to_i915(dev);
1717         int (*reset)(struct drm_device *, unsigned);
1718         int ret;
1719
1720         reset = intel_get_gpu_reset(dev);
1721         if (reset == NULL)
1722                 return -ENODEV;
1723
1724         /* If the power well sleeps during the reset, the reset
1725          * request may be dropped and never completes (causing -EIO).
1726          */
1727         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1728         ret = reset(dev, engine_mask);
1729         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1730
1731         return ret;
1732 }
1733
1734 bool intel_has_gpu_reset(struct drm_device *dev)
1735 {
1736         return intel_get_gpu_reset(dev) != NULL;
1737 }
1738
1739 int intel_guc_reset(struct drm_i915_private *dev_priv)
1740 {
1741         int ret;
1742         unsigned long irqflags;
1743
1744         if (!i915.enable_guc_submission)
1745                 return -EINVAL;
1746
1747         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1748         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
1749
1750         ret = gen6_hw_domain_reset(dev_priv, GEN9_GRDOM_GUC);
1751
1752         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
1753         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1754
1755         return ret;
1756 }
1757
1758 bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv)
1759 {
1760         return check_for_unclaimed_mmio(dev_priv);
1761 }
1762
1763 bool
1764 intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv)
1765 {
1766         if (unlikely(i915.mmio_debug ||
1767                      dev_priv->uncore.unclaimed_mmio_check <= 0))
1768                 return false;
1769
1770         if (unlikely(intel_uncore_unclaimed_mmio(dev_priv))) {
1771                 DRM_DEBUG("Unclaimed register detected, "
1772                           "enabling oneshot unclaimed register reporting. "
1773                           "Please use i915.mmio_debug=N for more information.\n");
1774                 i915.mmio_debug++;
1775                 dev_priv->uncore.unclaimed_mmio_check--;
1776                 return true;
1777         }
1778
1779         return false;
1780 }
1781
1782 static enum forcewake_domains
1783 intel_uncore_forcewake_for_read(struct drm_i915_private *dev_priv,
1784                                 i915_reg_t reg)
1785 {
1786         enum forcewake_domains fw_domains;
1787
1788         if (intel_vgpu_active(dev_priv->dev))
1789                 return 0;
1790
1791         switch (INTEL_INFO(dev_priv)->gen) {
1792         case 9:
1793                 fw_domains = __gen9_reg_read_fw_domains(i915_mmio_reg_offset(reg));
1794                 break;
1795         case 8:
1796                 if (IS_CHERRYVIEW(dev_priv))
1797                         fw_domains = __chv_reg_read_fw_domains(i915_mmio_reg_offset(reg));
1798                 else
1799                         fw_domains = __gen6_reg_read_fw_domains(i915_mmio_reg_offset(reg));
1800                 break;
1801         case 7:
1802         case 6:
1803                 if (IS_VALLEYVIEW(dev_priv))
1804                         fw_domains = __vlv_reg_read_fw_domains(i915_mmio_reg_offset(reg));
1805                 else
1806                         fw_domains = __gen6_reg_read_fw_domains(i915_mmio_reg_offset(reg));
1807                 break;
1808         default:
1809                 MISSING_CASE(INTEL_INFO(dev_priv)->gen);
1810         case 5: /* forcewake was introduced with gen6 */
1811         case 4:
1812         case 3:
1813         case 2:
1814                 return 0;
1815         }
1816
1817         WARN_ON(fw_domains & ~dev_priv->uncore.fw_domains);
1818
1819         return fw_domains;
1820 }
1821
1822 static enum forcewake_domains
1823 intel_uncore_forcewake_for_write(struct drm_i915_private *dev_priv,
1824                                  i915_reg_t reg)
1825 {
1826         enum forcewake_domains fw_domains;
1827
1828         if (intel_vgpu_active(dev_priv->dev))
1829                 return 0;
1830
1831         switch (INTEL_INFO(dev_priv)->gen) {
1832         case 9:
1833                 fw_domains = __gen9_reg_write_fw_domains(i915_mmio_reg_offset(reg));
1834                 break;
1835         case 8:
1836                 if (IS_CHERRYVIEW(dev_priv))
1837                         fw_domains = __chv_reg_write_fw_domains(i915_mmio_reg_offset(reg));
1838                 else
1839                         fw_domains = __gen8_reg_write_fw_domains(i915_mmio_reg_offset(reg));
1840                 break;
1841         case 7:
1842         case 6:
1843                 fw_domains = FORCEWAKE_RENDER;
1844                 break;
1845         default:
1846                 MISSING_CASE(INTEL_INFO(dev_priv)->gen);
1847         case 5:
1848         case 4:
1849         case 3:
1850         case 2:
1851                 return 0;
1852         }
1853
1854         WARN_ON(fw_domains & ~dev_priv->uncore.fw_domains);
1855
1856         return fw_domains;
1857 }
1858
1859 /**
1860  * intel_uncore_forcewake_for_reg - which forcewake domains are needed to access
1861  *                                  a register
1862  * @dev_priv: pointer to struct drm_i915_private
1863  * @reg: register in question
1864  * @op: operation bitmask of FW_REG_READ and/or FW_REG_WRITE
1865  *
1866  * Returns a set of forcewake domains required to be taken with for example
1867  * intel_uncore_forcewake_get for the specified register to be accessible in the
1868  * specified mode (read, write or read/write) with raw mmio accessors.
1869  *
1870  * NOTE: On Gen6 and Gen7 write forcewake domain (FORCEWAKE_RENDER) requires the
1871  * callers to do FIFO management on their own or risk losing writes.
1872  */
1873 enum forcewake_domains
1874 intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv,
1875                                i915_reg_t reg, unsigned int op)
1876 {
1877         enum forcewake_domains fw_domains = 0;
1878
1879         WARN_ON(!op);
1880
1881         if (op & FW_REG_READ)
1882                 fw_domains = intel_uncore_forcewake_for_read(dev_priv, reg);
1883
1884         if (op & FW_REG_WRITE)
1885                 fw_domains |= intel_uncore_forcewake_for_write(dev_priv, reg);
1886
1887         return fw_domains;
1888 }