drivers/gpu/drm/i915/intel_uncore.c

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "i915_drv.h"
  25 #include "intel_drv.h"
  26 #include "i915_vgpu.h"
  27
  28 #include <linux/pm_runtime.h>
  29
  30 #define FORCEWAKE_ACK_TIMEOUT_MS 50
  31
  32 #define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32((dev_priv__), (reg__))
  33
  34 static const char * const forcewake_domain_names[] = {
  35         "render",
  36         "blitter",
  37         "media",
  38 };
  39
  40 const char *
  41 intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id)
  42 {
  43         BUILD_BUG_ON(ARRAY_SIZE(forcewake_domain_names) != FW_DOMAIN_ID_COUNT);
  44
  45         if (id >= 0 && id < FW_DOMAIN_ID_COUNT)
  46                 return forcewake_domain_names[id];
  47
  48         WARN_ON(id);
  49
  50         return "unknown";
  51 }
  52
  53 static inline void
  54 fw_domain_reset(const struct intel_uncore_forcewake_domain *d)
  55 {
  56         WARN_ON(!i915_mmio_reg_valid(d->reg_set));
  57         __raw_i915_write32(d->i915, d->reg_set, d->val_reset);
  58 }
  59
  60 static inline void
  61 fw_domain_arm_timer(struct intel_uncore_forcewake_domain *d)
  62 {
  63         d->wake_count++;
  64         hrtimer_start_range_ns(&d->timer,
  65                                ktime_set(0, NSEC_PER_MSEC),
  66                                NSEC_PER_MSEC,
  67                                HRTIMER_MODE_REL);
  68 }
  69
  70 static inline void
  71 fw_domain_wait_ack_clear(const struct intel_uncore_forcewake_domain *d)
  72 {
  73         if (wait_for_atomic((__raw_i915_read32(d->i915, d->reg_ack) &
  74                              FORCEWAKE_KERNEL) == 0,
  75                             FORCEWAKE_ACK_TIMEOUT_MS))
  76                 DRM_ERROR("%s: timed out waiting for forcewake ack to clear.\n",
  77                           intel_uncore_forcewake_domain_to_str(d->id));
  78 }
  79
  80 static inline void
  81 fw_domain_get(const struct intel_uncore_forcewake_domain *d)
  82 {
  83         __raw_i915_write32(d->i915, d->reg_set, d->val_set);
  84 }
  85
  86 static inline void
  87 fw_domain_wait_ack(const struct intel_uncore_forcewake_domain *d)
  88 {
  89         if (wait_for_atomic((__raw_i915_read32(d->i915, d->reg_ack) &
  90                              FORCEWAKE_KERNEL),
  91                             FORCEWAKE_ACK_TIMEOUT_MS))
  92                 DRM_ERROR("%s: timed out waiting for forcewake ack request.\n",
  93                           intel_uncore_forcewake_domain_to_str(d->id));
  94 }
  95
  96 static inline void
  97 fw_domain_put(const struct intel_uncore_forcewake_domain *d)
  98 {
  99         __raw_i915_write32(d->i915, d->reg_set, d->val_clear);
 100 }
 101
 102 static inline void
 103 fw_domain_posting_read(const struct intel_uncore_forcewake_domain *d)
 104 {
 105         /* something from same cacheline, but not from the set register */
 106         if (i915_mmio_reg_valid(d->reg_post))
 107                 __raw_posting_read(d->i915, d->reg_post);
 108 }
 109
 110 static void
 111 fw_domains_get(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains)
 112 {
 113         struct intel_uncore_forcewake_domain *d;
 114
 115         for_each_fw_domain_masked(d, fw_domains, dev_priv) {
 116                 fw_domain_wait_ack_clear(d);
 117                 fw_domain_get(d);
 118         }
 119
 120         for_each_fw_domain_masked(d, fw_domains, dev_priv)
 121                 fw_domain_wait_ack(d);
 122 }
 123
 124 static void
 125 fw_domains_put(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains)
 126 {
 127         struct intel_uncore_forcewake_domain *d;
 128
 129         for_each_fw_domain_masked(d, fw_domains, dev_priv) {
 130                 fw_domain_put(d);
 131                 fw_domain_posting_read(d);
 132         }
 133 }
 134
 135 static void
 136 fw_domains_posting_read(struct drm_i915_private *dev_priv)
 137 {
 138         struct intel_uncore_forcewake_domain *d;
 139
 140         /* No need to do for all, just do for first found */
 141         for_each_fw_domain(d, dev_priv) {
 142                 fw_domain_posting_read(d);
 143                 break;
 144         }
 145 }
 146
 147 static void
 148 fw_domains_reset(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains)
 149 {
 150         struct intel_uncore_forcewake_domain *d;
 151
 152         if (dev_priv->uncore.fw_domains == 0)
 153                 return;
 154
 155         for_each_fw_domain_masked(d, fw_domains, dev_priv)
 156                 fw_domain_reset(d);
 157
 158         fw_domains_posting_read(dev_priv);
 159 }
 160
 161 static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
 162 {
 163         /* w/a for a sporadic read returning 0 by waiting for the GT
 164          * thread to wake up.
 165          */
 166         if (wait_for_atomic_us((__raw_i915_read32(dev_priv, GEN6_GT_THREAD_STATUS_REG) &
 167                                 GEN6_GT_THREAD_STATUS_CORE_MASK) == 0, 500))
 168                 DRM_ERROR("GT thread status wait timed out\n");
 169 }
 170
 171 static void fw_domains_get_with_thread_status(struct drm_i915_private *dev_priv,
 172                                               enum forcewake_domains fw_domains)
 173 {
 174         fw_domains_get(dev_priv, fw_domains);
 175
 176         /* WaRsForcewakeWaitTC0:snb,ivb,hsw,bdw,vlv */
 177         __gen6_gt_wait_for_thread_c0(dev_priv);
 178 }
 179
 180 static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
 181 {
 182         u32 gtfifodbg;
 183
 184         gtfifodbg = __raw_i915_read32(dev_priv, GTFIFODBG);
 185         if (WARN(gtfifodbg, "GT wake FIFO error 0x%x\n", gtfifodbg))
 186                 __raw_i915_write32(dev_priv, GTFIFODBG, gtfifodbg);
 187 }
 188
 189 static void fw_domains_put_with_fifo(struct drm_i915_private *dev_priv,
 190                                      enum forcewake_domains fw_domains)
 191 {
 192         fw_domains_put(dev_priv, fw_domains);
 193         gen6_gt_check_fifodbg(dev_priv);
 194 }
 195
 196 static inline u32 fifo_free_entries(struct drm_i915_private *dev_priv)
 197 {
 198         u32 count = __raw_i915_read32(dev_priv, GTFIFOCTL);
 199
 200         return count & GT_FIFO_FREE_ENTRIES_MASK;
 201 }
 202
 203 static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
 204 {
 205         int ret = 0;
 206
 207         /* On VLV, FIFO will be shared by both SW and HW.
 208          * So, we need to read the FREE_ENTRIES everytime */
 209         if (IS_VALLEYVIEW(dev_priv))
 210                 dev_priv->uncore.fifo_count = fifo_free_entries(dev_priv);
 211
 212         if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
 213                 int loop = 500;
 214                 u32 fifo = fifo_free_entries(dev_priv);
 215
 216                 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
 217                         udelay(10);
 218                         fifo = fifo_free_entries(dev_priv);
 219                 }
 220                 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
 221                         ++ret;
 222                 dev_priv->uncore.fifo_count = fifo;
 223         }
 224         dev_priv->uncore.fifo_count--;
 225
 226         return ret;
 227 }
 228
 229 static enum hrtimer_restart
 230 intel_uncore_fw_release_timer(struct hrtimer *timer)
 231 {
 232         struct intel_uncore_forcewake_domain *domain =
 233                container_of(timer, struct intel_uncore_forcewake_domain, timer);
 234         unsigned long irqflags;
 235
 236         assert_rpm_device_not_suspended(domain->i915);
 237
 238         spin_lock_irqsave(&domain->i915->uncore.lock, irqflags);
 239         if (WARN_ON(domain->wake_count == 0))
 240                 domain->wake_count++;
 241
 242         if (--domain->wake_count == 0)
 243                 domain->i915->uncore.funcs.force_wake_put(domain->i915,
 244                                                           1 << domain->id);
 245
 246         spin_unlock_irqrestore(&domain->i915->uncore.lock, irqflags);
 247
 248         return HRTIMER_NORESTART;
 249 }
 250
 251 void intel_uncore_forcewake_reset(struct drm_i915_private *dev_priv,
 252                                   bool restore)
 253 {
 254         unsigned long irqflags;
 255         struct intel_uncore_forcewake_domain *domain;
 256         int retry_count = 100;
 257         enum forcewake_domains fw = 0, active_domains;
 258
 259         /* Hold uncore.lock across reset to prevent any register access
 260          * with forcewake not set correctly. Wait until all pending
 261          * timers are run before holding.
 262          */
 263         while (1) {
 264                 active_domains = 0;
 265
 266                 for_each_fw_domain(domain, dev_priv) {
 267                         if (hrtimer_cancel(&domain->timer) == 0)
 268                                 continue;
 269
 270                         intel_uncore_fw_release_timer(&domain->timer);
 271                 }
 272
 273                 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 274
 275                 for_each_fw_domain(domain, dev_priv) {
 276                         if (hrtimer_active(&domain->timer))
 277                                 active_domains |= domain->mask;
 278                 }
 279
 280                 if (active_domains == 0)
 281                         break;
 282
 283                 if (--retry_count == 0) {
 284                         DRM_ERROR("Timed out waiting for forcewake timers to finish\n");
 285                         break;
 286                 }
 287
 288                 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 289                 cond_resched();
 290         }
 291
 292         WARN_ON(active_domains);
 293
 294         for_each_fw_domain(domain, dev_priv)
 295                 if (domain->wake_count)
 296                         fw |= domain->mask;
 297
 298         if (fw)
 299                 dev_priv->uncore.funcs.force_wake_put(dev_priv, fw);
 300
 301         fw_domains_reset(dev_priv, FORCEWAKE_ALL);
 302
 303         if (restore) { /* If reset with a user forcewake, try to restore */
 304                 if (fw)
 305                         dev_priv->uncore.funcs.force_wake_get(dev_priv, fw);
 306
 307                 if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv))
 308                         dev_priv->uncore.fifo_count =
 309                                 fifo_free_entries(dev_priv);
 310         }
 311
 312         if (!restore)
 313                 assert_forcewakes_inactive(dev_priv);
 314
 315         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 316 }
 317
 318 static u64 gen9_edram_size(struct drm_i915_private *dev_priv)
 319 {
 320         const unsigned int ways[8] = { 4, 8, 12, 16, 16, 16, 16, 16 };
 321         const unsigned int sets[4] = { 1, 1, 2, 2 };
 322         const u32 cap = dev_priv->edram_cap;
 323
 324         return EDRAM_NUM_BANKS(cap) *
 325                 ways[EDRAM_WAYS_IDX(cap)] *
 326                 sets[EDRAM_SETS_IDX(cap)] *
 327                 1024 * 1024;
 328 }
 329
 330 u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv)
 331 {
 332         if (!HAS_EDRAM(dev_priv))
 333                 return 0;
 334
 335         /* The needed capability bits for size calculation
 336          * are not there with pre gen9 so return 128MB always.
 337          */
 338         if (INTEL_GEN(dev_priv) < 9)
 339                 return 128 * 1024 * 1024;
 340
 341         return gen9_edram_size(dev_priv);
 342 }
 343
 344 static void intel_uncore_edram_detect(struct drm_i915_private *dev_priv)
 345 {
 346         if (IS_HASWELL(dev_priv) ||
 347             IS_BROADWELL(dev_priv) ||
 348             INTEL_GEN(dev_priv) >= 9) {
 349                 dev_priv->edram_cap = __raw_i915_read32(dev_priv,
 350                                                         HSW_EDRAM_CAP);
 351
 352                 /* NB: We can't write IDICR yet because we do not have gt funcs
 353                  * set up */
 354         } else {
 355                 dev_priv->edram_cap = 0;
 356         }
 357
 358         if (HAS_EDRAM(dev_priv))
 359                 DRM_INFO("Found %lluMB of eDRAM\n",
 360                          intel_uncore_edram_size(dev_priv) / (1024 * 1024));
 361 }
 362
 363 static bool
 364 fpga_check_for_unclaimed_mmio(struct drm_i915_private *dev_priv)
 365 {
 366         u32 dbg;
 367
 368         dbg = __raw_i915_read32(dev_priv, FPGA_DBG);
 369         if (likely(!(dbg & FPGA_DBG_RM_NOCLAIM)))
 370                 return false;
 371
 372         __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
 373
 374         return true;
 375 }
 376
 377 static bool
 378 vlv_check_for_unclaimed_mmio(struct drm_i915_private *dev_priv)
 379 {
 380         u32 cer;
 381
 382         cer = __raw_i915_read32(dev_priv, CLAIM_ER);
 383         if (likely(!(cer & (CLAIM_ER_OVERFLOW | CLAIM_ER_CTR_MASK))))
 384                 return false;
 385
 386         __raw_i915_write32(dev_priv, CLAIM_ER, CLAIM_ER_CLR);
 387
 388         return true;
 389 }
 390
 391 static bool
 392 check_for_unclaimed_mmio(struct drm_i915_private *dev_priv)
 393 {
 394         if (HAS_FPGA_DBG_UNCLAIMED(dev_priv))
 395                 return fpga_check_for_unclaimed_mmio(dev_priv);
 396
 397         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 398                 return vlv_check_for_unclaimed_mmio(dev_priv);
 399
 400         return false;
 401 }
 402
 403 static void __intel_uncore_early_sanitize(struct drm_i915_private *dev_priv,
 404                                           bool restore_forcewake)
 405 {
 406         /* clear out unclaimed reg detection bit */
 407         if (check_for_unclaimed_mmio(dev_priv))
 408                 DRM_DEBUG("unclaimed mmio detected on uncore init, clearing\n");
 409
 410         /* clear out old GT FIFO errors */
 411         if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv))
 412                 __raw_i915_write32(dev_priv, GTFIFODBG,
 413                                    __raw_i915_read32(dev_priv, GTFIFODBG));
 414
 415         /* WaDisableShadowRegForCpd:chv */
 416         if (IS_CHERRYVIEW(dev_priv)) {
 417                 __raw_i915_write32(dev_priv, GTFIFOCTL,
 418                                    __raw_i915_read32(dev_priv, GTFIFOCTL) |
 419                                    GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL |
 420                                    GT_FIFO_CTL_RC6_POLICY_STALL);
 421         }
 422
 423         intel_uncore_forcewake_reset(dev_priv, restore_forcewake);
 424 }
 425
 426 void intel_uncore_early_sanitize(struct drm_i915_private *dev_priv,
 427                                  bool restore_forcewake)
 428 {
 429         __intel_uncore_early_sanitize(dev_priv, restore_forcewake);
 430         i915_check_and_clear_faults(dev_priv);
 431 }
 432
 433 void intel_uncore_sanitize(struct drm_i915_private *dev_priv)
 434 {
 435         i915.enable_rc6 = sanitize_rc6_option(dev_priv, i915.enable_rc6);
 436
 437         /* BIOS often leaves RC6 enabled, but disable it for hw init */
 438         intel_sanitize_gt_powersave(dev_priv);
 439 }
 440
 441 static void __intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
 442                                          enum forcewake_domains fw_domains)
 443 {
 444         struct intel_uncore_forcewake_domain *domain;
 445
 446         if (!dev_priv->uncore.funcs.force_wake_get)
 447                 return;
 448
 449         fw_domains &= dev_priv->uncore.fw_domains;
 450
 451         for_each_fw_domain_masked(domain, fw_domains, dev_priv) {
 452                 if (domain->wake_count++)
 453                         fw_domains &= ~domain->mask;
 454         }
 455
 456         if (fw_domains)
 457                 dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains);
 458 }
 459
 460 /**
 461  * intel_uncore_forcewake_get - grab forcewake domain references
 462  * @dev_priv: i915 device instance
 463  * @fw_domains: forcewake domains to get reference on
 464  *
 465  * This function can be used get GT's forcewake domain references.
 466  * Normal register access will handle the forcewake domains automatically.
 467  * However if some sequence requires the GT to not power down a particular
 468  * forcewake domains this function should be called at the beginning of the
 469  * sequence. And subsequently the reference should be dropped by symmetric
 470  * call to intel_unforce_forcewake_put(). Usually caller wants all the domains
 471  * to be kept awake so the @fw_domains would be then FORCEWAKE_ALL.
 472  */
 473 void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
 474                                 enum forcewake_domains fw_domains)
 475 {
 476         unsigned long irqflags;
 477
 478         if (!dev_priv->uncore.funcs.force_wake_get)
 479                 return;
 480
 481         assert_rpm_wakelock_held(dev_priv);
 482
 483         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 484         __intel_uncore_forcewake_get(dev_priv, fw_domains);
 485         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 486 }
 487
 488 /**
 489  * intel_uncore_forcewake_get__locked - grab forcewake domain references
 490  * @dev_priv: i915 device instance
 491  * @fw_domains: forcewake domains to get reference on
 492  *
 493  * See intel_uncore_forcewake_get(). This variant places the onus
 494  * on the caller to explicitly handle the dev_priv->uncore.lock spinlock.
 495  */
 496 void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
 497                                         enum forcewake_domains fw_domains)
 498 {
 499         assert_spin_locked(&dev_priv->uncore.lock);
 500
 501         if (!dev_priv->uncore.funcs.force_wake_get)
 502                 return;
 503
 504         __intel_uncore_forcewake_get(dev_priv, fw_domains);
 505 }
 506
 507 static void __intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
 508                                          enum forcewake_domains fw_domains)
 509 {
 510         struct intel_uncore_forcewake_domain *domain;
 511
 512         if (!dev_priv->uncore.funcs.force_wake_put)
 513                 return;
 514
 515         fw_domains &= dev_priv->uncore.fw_domains;
 516
 517         for_each_fw_domain_masked(domain, fw_domains, dev_priv) {
 518                 if (WARN_ON(domain->wake_count == 0))
 519                         continue;
 520
 521                 if (--domain->wake_count)
 522                         continue;
 523
 524                 fw_domain_arm_timer(domain);
 525         }
 526 }
 527
 528 /**
 529  * intel_uncore_forcewake_put - release a forcewake domain reference
 530  * @dev_priv: i915 device instance
 531  * @fw_domains: forcewake domains to put references
 532  *
 533  * This function drops the device-level forcewakes for specified
 534  * domains obtained by intel_uncore_forcewake_get().
 535  */
 536 void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
 537                                 enum forcewake_domains fw_domains)
 538 {
 539         unsigned long irqflags;
 540
 541         if (!dev_priv->uncore.funcs.force_wake_put)
 542                 return;
 543
 544         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 545         __intel_uncore_forcewake_put(dev_priv, fw_domains);
 546         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 547 }
 548
 549 /**
 550  * intel_uncore_forcewake_put__locked - grab forcewake domain references
 551  * @dev_priv: i915 device instance
 552  * @fw_domains: forcewake domains to get reference on
 553  *
 554  * See intel_uncore_forcewake_put(). This variant places the onus
 555  * on the caller to explicitly handle the dev_priv->uncore.lock spinlock.
 556  */
 557 void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
 558                                         enum forcewake_domains fw_domains)
 559 {
 560         assert_spin_locked(&dev_priv->uncore.lock);
 561
 562         if (!dev_priv->uncore.funcs.force_wake_put)
 563                 return;
 564
 565         __intel_uncore_forcewake_put(dev_priv, fw_domains);
 566 }
 567
 568 void assert_forcewakes_inactive(struct drm_i915_private *dev_priv)
 569 {
 570         struct intel_uncore_forcewake_domain *domain;
 571
 572         if (!dev_priv->uncore.funcs.force_wake_get)
 573                 return;
 574
 575         for_each_fw_domain(domain, dev_priv)
 576                 WARN_ON(domain->wake_count);
 577 }
 578
 579 /* We give fast paths for the really cool registers */
 580 #define NEEDS_FORCE_WAKE(reg) ((reg) < 0x40000)
 581
 582 #define __gen6_reg_read_fw_domains(offset) \
 583 ({ \
 584         enum forcewake_domains __fwd; \
 585         if (NEEDS_FORCE_WAKE(offset)) \
 586                 __fwd = FORCEWAKE_RENDER; \
 587         else \
 588                 __fwd = 0; \
 589         __fwd; \
 590 })
 591
 592 #define REG_RANGE(reg, start, end) ((reg) >= (start) && (reg) < (end))
 593
 594 #define FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg) \
 595         (REG_RANGE((reg), 0x2000, 0x4000) || \
 596          REG_RANGE((reg), 0x5000, 0x8000) || \
 597          REG_RANGE((reg), 0xB000, 0x12000) || \
 598          REG_RANGE((reg), 0x2E000, 0x30000))
 599
 600 #define FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg) \
 601         (REG_RANGE((reg), 0x12000, 0x14000) || \
 602          REG_RANGE((reg), 0x22000, 0x24000) || \
 603          REG_RANGE((reg), 0x30000, 0x40000))
 604
 605 #define __vlv_reg_read_fw_domains(offset) \
 606 ({ \
 607         enum forcewake_domains __fwd = 0; \
 608         if (!NEEDS_FORCE_WAKE(offset)) \
 609                 __fwd = 0; \
 610         else if (FORCEWAKE_VLV_RENDER_RANGE_OFFSET(offset)) \
 611                 __fwd = FORCEWAKE_RENDER; \
 612         else if (FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(offset)) \
 613                 __fwd = FORCEWAKE_MEDIA; \
 614         __fwd; \
 615 })
 616
 617 static const i915_reg_t gen8_shadowed_regs[] = {
 618         GEN6_RPNSWREQ,
 619         GEN6_RC_VIDEO_FREQ,
 620         RING_TAIL(RENDER_RING_BASE),
 621         RING_TAIL(GEN6_BSD_RING_BASE),
 622         RING_TAIL(VEBOX_RING_BASE),
 623         RING_TAIL(BLT_RING_BASE),
 624         /* TODO: Other registers are not yet used */
 625 };
 626
 627 static bool is_gen8_shadowed(u32 offset)
 628 {
 629         int i;
 630         for (i = 0; i < ARRAY_SIZE(gen8_shadowed_regs); i++)
 631                 if (offset == gen8_shadowed_regs[i].reg)
 632                         return true;
 633
 634         return false;
 635 }
 636
 637 #define __gen8_reg_write_fw_domains(offset) \
 638 ({ \
 639         enum forcewake_domains __fwd; \
 640         if (NEEDS_FORCE_WAKE(offset) && !is_gen8_shadowed(offset)) \
 641                 __fwd = FORCEWAKE_RENDER; \
 642         else \
 643                 __fwd = 0; \
 644         __fwd; \
 645 })
 646
 647 #define FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg) \
 648         (REG_RANGE((reg), 0x2000, 0x4000) || \
 649          REG_RANGE((reg), 0x5200, 0x8000) || \
 650          REG_RANGE((reg), 0x8300, 0x8500) || \
 651          REG_RANGE((reg), 0xB000, 0xB480) || \
 652          REG_RANGE((reg), 0xE000, 0xE800))
 653
 654 #define FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg) \
 655         (REG_RANGE((reg), 0x8800, 0x8900) || \
 656          REG_RANGE((reg), 0xD000, 0xD800) || \
 657          REG_RANGE((reg), 0x12000, 0x14000) || \
 658          REG_RANGE((reg), 0x1A000, 0x1C000) || \
 659          REG_RANGE((reg), 0x1E800, 0x1EA00) || \
 660          REG_RANGE((reg), 0x30000, 0x38000))
 661
 662 #define FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg) \
 663         (REG_RANGE((reg), 0x4000, 0x5000) || \
 664          REG_RANGE((reg), 0x8000, 0x8300) || \
 665          REG_RANGE((reg), 0x8500, 0x8600) || \
 666          REG_RANGE((reg), 0x9000, 0xB000) || \
 667          REG_RANGE((reg), 0xF000, 0x10000))
 668
 669 #define __chv_reg_read_fw_domains(offset) \
 670 ({ \
 671         enum forcewake_domains __fwd = 0; \
 672         if (!NEEDS_FORCE_WAKE(offset)) \
 673                 __fwd = 0; \
 674         else if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(offset)) \
 675                 __fwd = FORCEWAKE_RENDER; \
 676         else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(offset)) \
 677                 __fwd = FORCEWAKE_MEDIA; \
 678         else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(offset)) \
 679                 __fwd = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \
 680         __fwd; \
 681 })
 682
 683 #define __chv_reg_write_fw_domains(offset) \
 684 ({ \
 685         enum forcewake_domains __fwd = 0; \
 686         if (!NEEDS_FORCE_WAKE(offset) || is_gen8_shadowed(offset)) \
 687                 __fwd = 0; \
 688         else if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(offset)) \
 689                 __fwd = FORCEWAKE_RENDER; \
 690         else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(offset)) \
 691                 __fwd = FORCEWAKE_MEDIA; \
 692         else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(offset)) \
 693                 __fwd = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \
 694         __fwd; \
 695 })
 696
 697 #define FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg) \
 698         REG_RANGE((reg), 0xB00,  0x2000)
 699
 700 #define FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg) \
 701         (REG_RANGE((reg), 0x2000, 0x2700) || \
 702          REG_RANGE((reg), 0x3000, 0x4000) || \
 703          REG_RANGE((reg), 0x5200, 0x8000) || \
 704          REG_RANGE((reg), 0x8140, 0x8160) || \
 705          REG_RANGE((reg), 0x8300, 0x8500) || \
 706          REG_RANGE((reg), 0x8C00, 0x8D00) || \
 707          REG_RANGE((reg), 0xB000, 0xB480) || \
 708          REG_RANGE((reg), 0xE000, 0xE900) || \
 709          REG_RANGE((reg), 0x24400, 0x24800))
 710
 711 #define FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg) \
 712         (REG_RANGE((reg), 0x8130, 0x8140) || \
 713          REG_RANGE((reg), 0x8800, 0x8A00) || \
 714          REG_RANGE((reg), 0xD000, 0xD800) || \
 715          REG_RANGE((reg), 0x12000, 0x14000) || \
 716          REG_RANGE((reg), 0x1A000, 0x1EA00) || \
 717          REG_RANGE((reg), 0x30000, 0x40000))
 718
 719 #define FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg) \
 720         REG_RANGE((reg), 0x9400, 0x9800)
 721
 722 #define FORCEWAKE_GEN9_BLITTER_RANGE_OFFSET(reg) \
 723         ((reg) < 0x40000 && \
 724          !FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg) && \
 725          !FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg) && \
 726          !FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg) && \
 727          !FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg))
 728
 729 #define SKL_NEEDS_FORCE_WAKE(reg) \
 730         ((reg) < 0x40000 && !FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg))
 731
 732 #define __gen9_reg_read_fw_domains(offset) \
 733 ({ \
 734         enum forcewake_domains __fwd; \
 735         if (!SKL_NEEDS_FORCE_WAKE(offset)) \
 736                 __fwd = 0; \
 737         else if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(offset)) \
 738                 __fwd = FORCEWAKE_RENDER; \
 739         else if (FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(offset)) \
 740                 __fwd = FORCEWAKE_MEDIA; \
 741         else if (FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(offset)) \
 742                 __fwd = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \
 743         else \
 744                 __fwd = FORCEWAKE_BLITTER; \
 745         __fwd; \
 746 })
 747
 748 static const i915_reg_t gen9_shadowed_regs[] = {
 749         RING_TAIL(RENDER_RING_BASE),
 750         RING_TAIL(GEN6_BSD_RING_BASE),
 751         RING_TAIL(VEBOX_RING_BASE),
 752         RING_TAIL(BLT_RING_BASE),
 753         GEN6_RPNSWREQ,
 754         GEN6_RC_VIDEO_FREQ,
 755         /* TODO: Other registers are not yet used */
 756 };
 757
 758 static bool is_gen9_shadowed(u32 offset)
 759 {
 760         int i;
 761         for (i = 0; i < ARRAY_SIZE(gen9_shadowed_regs); i++)
 762                 if (offset == gen9_shadowed_regs[i].reg)
 763                         return true;
 764
 765         return false;
 766 }
 767
 768 #define __gen9_reg_write_fw_domains(offset) \
 769 ({ \
 770         enum forcewake_domains __fwd; \
 771         if (!SKL_NEEDS_FORCE_WAKE(offset) || is_gen9_shadowed(offset)) \
 772                 __fwd = 0; \
 773         else if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(offset)) \
 774                 __fwd = FORCEWAKE_RENDER; \
 775         else if (FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(offset)) \
 776                 __fwd = FORCEWAKE_MEDIA; \
 777         else if (FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(offset)) \
 778                 __fwd = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \
 779         else \
 780                 __fwd = FORCEWAKE_BLITTER; \
 781         __fwd; \
 782 })
 783
 784 static void
 785 ilk_dummy_write(struct drm_i915_private *dev_priv)
 786 {
 787         /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up
 788          * the chip from rc6 before touching it for real. MI_MODE is masked,
 789          * hence harmless to write 0 into. */
 790         __raw_i915_write32(dev_priv, MI_MODE, 0);
 791 }
 792
 793 static void
 794 __unclaimed_reg_debug(struct drm_i915_private *dev_priv,
 795                       const i915_reg_t reg,
 796                       const bool read,
 797                       const bool before)
 798 {
 799         if (WARN(check_for_unclaimed_mmio(dev_priv),
 800                  "Unclaimed register detected %s %s register 0x%x\n",
 801                  before ? "before" : "after",
 802                  read ? "reading" : "writing to",
 803                  i915_mmio_reg_offset(reg)))
 804                 i915.mmio_debug--; /* Only report the first N failures */
 805 }
 806
 807 static inline void
 808 unclaimed_reg_debug(struct drm_i915_private *dev_priv,
 809                     const i915_reg_t reg,
 810                     const bool read,
 811                     const bool before)
 812 {
 813         if (likely(!i915.mmio_debug))
 814                 return;
 815
 816         __unclaimed_reg_debug(dev_priv, reg, read, before);
 817 }
 818
 819 #define GEN2_READ_HEADER(x) \
 820         u##x val = 0; \
 821         assert_rpm_wakelock_held(dev_priv);
 822
 823 #define GEN2_READ_FOOTER \
 824         trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
 825         return val
 826
 827 #define __gen2_read(x) \
 828 static u##x \
 829 gen2_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
 830         GEN2_READ_HEADER(x); \
 831         val = __raw_i915_read##x(dev_priv, reg); \
 832         GEN2_READ_FOOTER; \
 833 }
 834
 835 #define __gen5_read(x) \
 836 static u##x \
 837 gen5_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
 838         GEN2_READ_HEADER(x); \
 839         ilk_dummy_write(dev_priv); \
 840         val = __raw_i915_read##x(dev_priv, reg); \
 841         GEN2_READ_FOOTER; \
 842 }
 843
 844 __gen5_read(8)
 845 __gen5_read(16)
 846 __gen5_read(32)
 847 __gen5_read(64)
 848 __gen2_read(8)
 849 __gen2_read(16)
 850 __gen2_read(32)
 851 __gen2_read(64)
 852
 853 #undef __gen5_read
 854 #undef __gen2_read
 855
 856 #undef GEN2_READ_FOOTER
 857 #undef GEN2_READ_HEADER
 858
 859 #define GEN6_READ_HEADER(x) \
 860         u32 offset = i915_mmio_reg_offset(reg); \
 861         unsigned long irqflags; \
 862         u##x val = 0; \
 863         assert_rpm_wakelock_held(dev_priv); \
 864         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); \
 865         unclaimed_reg_debug(dev_priv, reg, true, true)
 866
 867 #define GEN6_READ_FOOTER \
 868         unclaimed_reg_debug(dev_priv, reg, true, false); \
 869         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
 870         trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
 871         return val
 872
 873 static inline void __force_wake_auto(struct drm_i915_private *dev_priv,
 874                                      enum forcewake_domains fw_domains)
 875 {
 876         struct intel_uncore_forcewake_domain *domain;
 877
 878         if (WARN_ON(!fw_domains))
 879                 return;
 880
 881         /* Ideally GCC would be constant-fold and eliminate this loop */
 882         for_each_fw_domain_masked(domain, fw_domains, dev_priv) {
 883                 if (domain->wake_count) {
 884                         fw_domains &= ~domain->mask;
 885                         continue;
 886                 }
 887
 888                 fw_domain_arm_timer(domain);
 889         }
 890
 891         if (fw_domains)
 892                 dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains);
 893 }
 894
 895 #define __gen6_read(x) \
 896 static u##x \
 897 gen6_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
 898         enum forcewake_domains fw_engine; \
 899         GEN6_READ_HEADER(x); \
 900         fw_engine = __gen6_reg_read_fw_domains(offset); \
 901         if (fw_engine) \
 902                 __force_wake_auto(dev_priv, fw_engine); \
 903         val = __raw_i915_read##x(dev_priv, reg); \
 904         GEN6_READ_FOOTER; \
 905 }
 906
 907 #define __vlv_read(x) \
 908 static u##x \
 909 vlv_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
 910         enum forcewake_domains fw_engine; \
 911         GEN6_READ_HEADER(x); \
 912         fw_engine = __vlv_reg_read_fw_domains(offset); \
 913         if (fw_engine) \
 914                 __force_wake_auto(dev_priv, fw_engine); \
 915         val = __raw_i915_read##x(dev_priv, reg); \
 916         GEN6_READ_FOOTER; \
 917 }
 918
 919 #define __chv_read(x) \
 920 static u##x \
 921 chv_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
 922         enum forcewake_domains fw_engine; \
 923         GEN6_READ_HEADER(x); \
 924         fw_engine = __chv_reg_read_fw_domains(offset); \
 925         if (fw_engine) \
 926                 __force_wake_auto(dev_priv, fw_engine); \
 927         val = __raw_i915_read##x(dev_priv, reg); \
 928         GEN6_READ_FOOTER; \
 929 }
 930
 931 #define __gen9_read(x) \
 932 static u##x \
 933 gen9_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
 934         enum forcewake_domains fw_engine; \
 935         GEN6_READ_HEADER(x); \
 936         fw_engine = __gen9_reg_read_fw_domains(offset); \
 937         if (fw_engine) \
 938                 __force_wake_auto(dev_priv, fw_engine); \
 939         val = __raw_i915_read##x(dev_priv, reg); \
 940         GEN6_READ_FOOTER; \
 941 }
 942
 943 __gen9_read(8)
 944 __gen9_read(16)
 945 __gen9_read(32)
 946 __gen9_read(64)
 947 __chv_read(8)
 948 __chv_read(16)
 949 __chv_read(32)
 950 __chv_read(64)
 951 __vlv_read(8)
 952 __vlv_read(16)
 953 __vlv_read(32)
 954 __vlv_read(64)
 955 __gen6_read(8)
 956 __gen6_read(16)
 957 __gen6_read(32)
 958 __gen6_read(64)
 959
 960 #undef __gen9_read
 961 #undef __chv_read
 962 #undef __vlv_read
 963 #undef __gen6_read
 964 #undef GEN6_READ_FOOTER
 965 #undef GEN6_READ_HEADER
 966
 967 #define VGPU_READ_HEADER(x) \
 968         unsigned long irqflags; \
 969         u##x val = 0; \
 970         assert_rpm_device_not_suspended(dev_priv); \
 971         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
 972
 973 #define VGPU_READ_FOOTER \
 974         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
 975         trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
 976         return val
 977
 978 #define __vgpu_read(x) \
 979 static u##x \
 980 vgpu_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
 981         VGPU_READ_HEADER(x); \
 982         val = __raw_i915_read##x(dev_priv, reg); \
 983         VGPU_READ_FOOTER; \
 984 }
 985
 986 __vgpu_read(8)
 987 __vgpu_read(16)
 988 __vgpu_read(32)
 989 __vgpu_read(64)
 990
 991 #undef __vgpu_read
 992 #undef VGPU_READ_FOOTER
 993 #undef VGPU_READ_HEADER
 994
 995 #define GEN2_WRITE_HEADER \
 996         trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
 997         assert_rpm_wakelock_held(dev_priv); \
 998
 999 #define GEN2_WRITE_FOOTER
1000
1001 #define __gen2_write(x) \
1002 static void \
1003 gen2_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
1004         GEN2_WRITE_HEADER; \
1005         __raw_i915_write##x(dev_priv, reg, val); \
1006         GEN2_WRITE_FOOTER; \
1007 }
1008
1009 #define __gen5_write(x) \
1010 static void \
1011 gen5_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
1012         GEN2_WRITE_HEADER; \
1013         ilk_dummy_write(dev_priv); \
1014         __raw_i915_write##x(dev_priv, reg, val); \
1015         GEN2_WRITE_FOOTER; \
1016 }
1017
1018 __gen5_write(8)
1019 __gen5_write(16)
1020 __gen5_write(32)
1021 __gen2_write(8)
1022 __gen2_write(16)
1023 __gen2_write(32)
1024
1025 #undef __gen5_write
1026 #undef __gen2_write
1027
1028 #undef GEN2_WRITE_FOOTER
1029 #undef GEN2_WRITE_HEADER
1030
1031 #define GEN6_WRITE_HEADER \
1032         u32 offset = i915_mmio_reg_offset(reg); \
1033         unsigned long irqflags; \
1034         trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
1035         assert_rpm_wakelock_held(dev_priv); \
1036         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); \
1037         unclaimed_reg_debug(dev_priv, reg, false, true)
1038
1039 #define GEN6_WRITE_FOOTER \
1040         unclaimed_reg_debug(dev_priv, reg, false, false); \
1041         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags)
1042
1043 #define __gen6_write(x) \
1044 static void \
1045 gen6_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
1046         u32 __fifo_ret = 0; \
1047         GEN6_WRITE_HEADER; \
1048         if (NEEDS_FORCE_WAKE(offset)) { \
1049                 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
1050         } \
1051         __raw_i915_write##x(dev_priv, reg, val); \
1052         if (unlikely(__fifo_ret)) { \
1053                 gen6_gt_check_fifodbg(dev_priv); \
1054         } \
1055         GEN6_WRITE_FOOTER; \
1056 }
1057
1058 #define __hsw_write(x) \
1059 static void \
1060 hsw_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
1061         u32 __fifo_ret = 0; \
1062         GEN6_WRITE_HEADER; \
1063         if (NEEDS_FORCE_WAKE(offset)) { \
1064                 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
1065         } \
1066         __raw_i915_write##x(dev_priv, reg, val); \
1067         if (unlikely(__fifo_ret)) { \
1068                 gen6_gt_check_fifodbg(dev_priv); \
1069         } \
1070         GEN6_WRITE_FOOTER; \
1071 }
1072
1073 #define __gen8_write(x) \
1074 static void \
1075 gen8_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
1076         enum forcewake_domains fw_engine; \
1077         GEN6_WRITE_HEADER; \
1078         fw_engine = __gen8_reg_write_fw_domains(offset); \
1079         if (fw_engine) \
1080                 __force_wake_auto(dev_priv, fw_engine); \
1081         __raw_i915_write##x(dev_priv, reg, val); \
1082         GEN6_WRITE_FOOTER; \
1083 }
1084
1085 #define __chv_write(x) \
1086 static void \
1087 chv_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
1088         enum forcewake_domains fw_engine; \
1089         GEN6_WRITE_HEADER; \
1090         fw_engine = __chv_reg_write_fw_domains(offset); \
1091         if (fw_engine) \
1092                 __force_wake_auto(dev_priv, fw_engine); \
1093         __raw_i915_write##x(dev_priv, reg, val); \
1094         GEN6_WRITE_FOOTER; \
1095 }
1096
1097 #define __gen9_write(x) \
1098 static void \
1099 gen9_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, \
1100                 bool trace) { \
1101         enum forcewake_domains fw_engine; \
1102         GEN6_WRITE_HEADER; \
1103         fw_engine = __gen9_reg_write_fw_domains(offset); \
1104         if (fw_engine) \
1105                 __force_wake_auto(dev_priv, fw_engine); \
1106         __raw_i915_write##x(dev_priv, reg, val); \
1107         GEN6_WRITE_FOOTER; \
1108 }
1109
1110 __gen9_write(8)
1111 __gen9_write(16)
1112 __gen9_write(32)
1113 __chv_write(8)
1114 __chv_write(16)
1115 __chv_write(32)
1116 __gen8_write(8)
1117 __gen8_write(16)
1118 __gen8_write(32)
1119 __hsw_write(8)
1120 __hsw_write(16)
1121 __hsw_write(32)
1122 __gen6_write(8)
1123 __gen6_write(16)
1124 __gen6_write(32)
1125
1126 #undef __gen9_write
1127 #undef __chv_write
1128 #undef __gen8_write
1129 #undef __hsw_write
1130 #undef __gen6_write
1131 #undef GEN6_WRITE_FOOTER
1132 #undef GEN6_WRITE_HEADER
1133
1134 #define VGPU_WRITE_HEADER \
1135         unsigned long irqflags; \
1136         trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
1137         assert_rpm_device_not_suspended(dev_priv); \
1138         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
1139
1140 #define VGPU_WRITE_FOOTER \
1141         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags)
1142
1143 #define __vgpu_write(x) \
1144 static void vgpu_write##x(struct drm_i915_private *dev_priv, \
1145                           i915_reg_t reg, u##x val, bool trace) { \
1146         VGPU_WRITE_HEADER; \
1147         __raw_i915_write##x(dev_priv, reg, val); \
1148         VGPU_WRITE_FOOTER; \
1149 }
1150
1151 __vgpu_write(8)
1152 __vgpu_write(16)
1153 __vgpu_write(32)
1154
1155 #undef __vgpu_write
1156 #undef VGPU_WRITE_FOOTER
1157 #undef VGPU_WRITE_HEADER
1158
1159 #define ASSIGN_WRITE_MMIO_VFUNCS(x) \
1160 do { \
1161         dev_priv->uncore.funcs.mmio_writeb = x##_write8; \
1162         dev_priv->uncore.funcs.mmio_writew = x##_write16; \
1163         dev_priv->uncore.funcs.mmio_writel = x##_write32; \
1164 } while (0)
1165
1166 #define ASSIGN_READ_MMIO_VFUNCS(x) \
1167 do { \
1168         dev_priv->uncore.funcs.mmio_readb = x##_read8; \
1169         dev_priv->uncore.funcs.mmio_readw = x##_read16; \
1170         dev_priv->uncore.funcs.mmio_readl = x##_read32; \
1171         dev_priv->uncore.funcs.mmio_readq = x##_read64; \
1172 } while (0)
1173
1174
1175 static void fw_domain_init(struct drm_i915_private *dev_priv,
1176                            enum forcewake_domain_id domain_id,
1177                            i915_reg_t reg_set,
1178                            i915_reg_t reg_ack)
1179 {
1180         struct intel_uncore_forcewake_domain *d;
1181
1182         if (WARN_ON(domain_id >= FW_DOMAIN_ID_COUNT))
1183                 return;
1184
1185         d = &dev_priv->uncore.fw_domain[domain_id];
1186
1187         WARN_ON(d->wake_count);
1188
1189         d->wake_count = 0;
1190         d->reg_set = reg_set;
1191         d->reg_ack = reg_ack;
1192
1193         if (IS_GEN6(dev_priv)) {
1194                 d->val_reset = 0;
1195                 d->val_set = FORCEWAKE_KERNEL;
1196                 d->val_clear = 0;
1197         } else {
1198                 /* WaRsClearFWBitsAtReset:bdw,skl */
1199                 d->val_reset = _MASKED_BIT_DISABLE(0xffff);
1200                 d->val_set = _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL);
1201                 d->val_clear = _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL);
1202         }
1203
1204         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1205                 d->reg_post = FORCEWAKE_ACK_VLV;
1206         else if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv) || IS_GEN8(dev_priv))
1207                 d->reg_post = ECOBUS;
1208
1209         d->i915 = dev_priv;
1210         d->id = domain_id;
1211
1212         BUILD_BUG_ON(FORCEWAKE_RENDER != (1 << FW_DOMAIN_ID_RENDER));
1213         BUILD_BUG_ON(FORCEWAKE_BLITTER != (1 << FW_DOMAIN_ID_BLITTER));
1214         BUILD_BUG_ON(FORCEWAKE_MEDIA != (1 << FW_DOMAIN_ID_MEDIA));
1215
1216         d->mask = 1 << domain_id;
1217
1218         hrtimer_init(&d->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
1219         d->timer.function = intel_uncore_fw_release_timer;
1220
1221         dev_priv->uncore.fw_domains |= (1 << domain_id);
1222
1223         fw_domain_reset(d);
1224 }
1225
1226 static void intel_uncore_fw_domains_init(struct drm_i915_private *dev_priv)
1227 {
1228         if (INTEL_INFO(dev_priv)->gen <= 5)
1229                 return;
1230
1231         if (IS_GEN9(dev_priv)) {
1232                 dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
1233                 dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
1234                 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1235                                FORCEWAKE_RENDER_GEN9,
1236                                FORCEWAKE_ACK_RENDER_GEN9);
1237                 fw_domain_init(dev_priv, FW_DOMAIN_ID_BLITTER,
1238                                FORCEWAKE_BLITTER_GEN9,
1239                                FORCEWAKE_ACK_BLITTER_GEN9);
1240                 fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA,
1241                                FORCEWAKE_MEDIA_GEN9, FORCEWAKE_ACK_MEDIA_GEN9);
1242         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1243                 dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
1244                 if (!IS_CHERRYVIEW(dev_priv))
1245                         dev_priv->uncore.funcs.force_wake_put =
1246                                 fw_domains_put_with_fifo;
1247                 else
1248                         dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
1249                 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1250                                FORCEWAKE_VLV, FORCEWAKE_ACK_VLV);
1251                 fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA,
1252                                FORCEWAKE_MEDIA_VLV, FORCEWAKE_ACK_MEDIA_VLV);
1253         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
1254                 dev_priv->uncore.funcs.force_wake_get =
1255                         fw_domains_get_with_thread_status;
1256                 if (IS_HASWELL(dev_priv))
1257                         dev_priv->uncore.funcs.force_wake_put =
1258                                 fw_domains_put_with_fifo;
1259                 else
1260                         dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
1261                 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1262                                FORCEWAKE_MT, FORCEWAKE_ACK_HSW);
1263         } else if (IS_IVYBRIDGE(dev_priv)) {
1264                 u32 ecobus;
1265
1266                 /* IVB configs may use multi-threaded forcewake */
1267
1268                 /* A small trick here - if the bios hasn't configured
1269                  * MT forcewake, and if the device is in RC6, then
1270                  * force_wake_mt_get will not wake the device and the
1271                  * ECOBUS read will return zero. Which will be
1272                  * (correctly) interpreted by the test below as MT
1273                  * forcewake being disabled.
1274                  */
1275                 dev_priv->uncore.funcs.force_wake_get =
1276                         fw_domains_get_with_thread_status;
1277                 dev_priv->uncore.funcs.force_wake_put =
1278                         fw_domains_put_with_fifo;
1279
1280                 /* We need to init first for ECOBUS access and then
1281                  * determine later if we want to reinit, in case of MT access is
1282                  * not working. In this stage we don't know which flavour this
1283                  * ivb is, so it is better to reset also the gen6 fw registers
1284                  * before the ecobus check.
1285                  */
1286
1287                 __raw_i915_write32(dev_priv, FORCEWAKE, 0);
1288                 __raw_posting_read(dev_priv, ECOBUS);
1289
1290                 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1291                                FORCEWAKE_MT, FORCEWAKE_MT_ACK);
1292
1293                 spin_lock_irq(&dev_priv->uncore.lock);
1294                 fw_domains_get_with_thread_status(dev_priv, FORCEWAKE_ALL);
1295                 ecobus = __raw_i915_read32(dev_priv, ECOBUS);
1296                 fw_domains_put_with_fifo(dev_priv, FORCEWAKE_ALL);
1297                 spin_unlock_irq(&dev_priv->uncore.lock);
1298
1299                 if (!(ecobus & FORCEWAKE_MT_ENABLE)) {
1300                         DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n");
1301                         DRM_INFO("when using vblank-synced partial screen updates.\n");
1302                         fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1303                                        FORCEWAKE, FORCEWAKE_ACK);
1304                 }
1305         } else if (IS_GEN6(dev_priv)) {
1306                 dev_priv->uncore.funcs.force_wake_get =
1307                         fw_domains_get_with_thread_status;
1308                 dev_priv->uncore.funcs.force_wake_put =
1309                         fw_domains_put_with_fifo;
1310                 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1311                                FORCEWAKE, FORCEWAKE_ACK);
1312         }
1313
1314         /* All future platforms are expected to require complex power gating */
1315         WARN_ON(dev_priv->uncore.fw_domains == 0);
1316 }
1317
1318 void intel_uncore_init(struct drm_i915_private *dev_priv)
1319 {
1320         i915_check_vgpu(dev_priv);
1321
1322         intel_uncore_edram_detect(dev_priv);
1323         intel_uncore_fw_domains_init(dev_priv);
1324         __intel_uncore_early_sanitize(dev_priv, false);
1325
1326         dev_priv->uncore.unclaimed_mmio_check = 1;
1327
1328         switch (INTEL_INFO(dev_priv)->gen) {
1329         default:
1330         case 9:
1331                 ASSIGN_WRITE_MMIO_VFUNCS(gen9);
1332                 ASSIGN_READ_MMIO_VFUNCS(gen9);
1333                 break;
1334         case 8:
1335                 if (IS_CHERRYVIEW(dev_priv)) {
1336                         ASSIGN_WRITE_MMIO_VFUNCS(chv);
1337                         ASSIGN_READ_MMIO_VFUNCS(chv);
1338
1339                 } else {
1340                         ASSIGN_WRITE_MMIO_VFUNCS(gen8);
1341                         ASSIGN_READ_MMIO_VFUNCS(gen6);
1342                 }
1343                 break;
1344         case 7:
1345         case 6:
1346                 if (IS_HASWELL(dev_priv)) {
1347                         ASSIGN_WRITE_MMIO_VFUNCS(hsw);
1348                 } else {
1349                         ASSIGN_WRITE_MMIO_VFUNCS(gen6);
1350                 }
1351
1352                 if (IS_VALLEYVIEW(dev_priv)) {
1353                         ASSIGN_READ_MMIO_VFUNCS(vlv);
1354                 } else {
1355                         ASSIGN_READ_MMIO_VFUNCS(gen6);
1356                 }
1357                 break;
1358         case 5:
1359                 ASSIGN_WRITE_MMIO_VFUNCS(gen5);
1360                 ASSIGN_READ_MMIO_VFUNCS(gen5);
1361                 break;
1362         case 4:
1363         case 3:
1364         case 2:
1365                 ASSIGN_WRITE_MMIO_VFUNCS(gen2);
1366                 ASSIGN_READ_MMIO_VFUNCS(gen2);
1367                 break;
1368         }
1369
1370         if (intel_vgpu_active(dev_priv)) {
1371                 ASSIGN_WRITE_MMIO_VFUNCS(vgpu);
1372                 ASSIGN_READ_MMIO_VFUNCS(vgpu);
1373         }
1374
1375         i915_check_and_clear_faults(dev_priv);
1376 }
1377 #undef ASSIGN_WRITE_MMIO_VFUNCS
1378 #undef ASSIGN_READ_MMIO_VFUNCS
1379
1380 void intel_uncore_fini(struct drm_i915_private *dev_priv)
1381 {
1382         /* Paranoia: make sure we have disabled everything before we exit. */
1383         intel_uncore_sanitize(dev_priv);
1384         intel_uncore_forcewake_reset(dev_priv, false);
1385 }
1386
1387 #define GEN_RANGE(l, h) GENMASK((h) - 1, (l) - 1)
1388
1389 static const struct register_whitelist {
1390         i915_reg_t offset_ldw, offset_udw;
1391         uint32_t size;
1392         /* supported gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
1393         uint32_t gen_bitmask;
1394 } whitelist[] = {
1395         { .offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE),
1396           .offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE),
1397           .size = 8, .gen_bitmask = GEN_RANGE(4, 9) },
1398 };
1399
1400 int i915_reg_read_ioctl(struct drm_device *dev,
1401                         void *data, struct drm_file *file)
1402 {
1403         struct drm_i915_private *dev_priv = to_i915(dev);
1404         struct drm_i915_reg_read *reg = data;
1405         struct register_whitelist const *entry = whitelist;
1406         unsigned size;
1407         i915_reg_t offset_ldw, offset_udw;
1408         int i, ret = 0;
1409
1410         for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) {
1411                 if (i915_mmio_reg_offset(entry->offset_ldw) == (reg->offset & -entry->size) &&
1412                     (INTEL_INFO(dev)->gen_mask & entry->gen_bitmask))
1413                         break;
1414         }
1415
1416         if (i == ARRAY_SIZE(whitelist))
1417                 return -EINVAL;
1418
1419         /* We use the low bits to encode extra flags as the register should
1420          * be naturally aligned (and those that are not so aligned merely
1421          * limit the available flags for that register).
1422          */
1423         offset_ldw = entry->offset_ldw;
1424         offset_udw = entry->offset_udw;
1425         size = entry->size;
1426         size |= reg->offset ^ i915_mmio_reg_offset(offset_ldw);
1427
1428         intel_runtime_pm_get(dev_priv);
1429
1430         switch (size) {
1431         case 8 | 1:
1432                 reg->val = I915_READ64_2x32(offset_ldw, offset_udw);
1433                 break;
1434         case 8:
1435                 reg->val = I915_READ64(offset_ldw);
1436                 break;
1437         case 4:
1438                 reg->val = I915_READ(offset_ldw);
1439                 break;
1440         case 2:
1441                 reg->val = I915_READ16(offset_ldw);
1442                 break;
1443         case 1:
1444                 reg->val = I915_READ8(offset_ldw);
1445                 break;
1446         default:
1447                 ret = -EINVAL;
1448                 goto out;
1449         }
1450
1451 out:
1452         intel_runtime_pm_put(dev_priv);
1453         return ret;
1454 }
1455
1456 static int i915_reset_complete(struct pci_dev *pdev)
1457 {
1458         u8 gdrst;
1459         pci_read_config_byte(pdev, I915_GDRST, &gdrst);
1460         return (gdrst & GRDOM_RESET_STATUS) == 0;
1461 }
1462
1463 static int i915_do_reset(struct drm_i915_private *dev_priv, unsigned engine_mask)
1464 {
1465         struct pci_dev *pdev = dev_priv->drm.pdev;
1466
1467         /* assert reset for at least 20 usec */
1468         pci_write_config_byte(pdev, I915_GDRST, GRDOM_RESET_ENABLE);
1469         udelay(20);
1470         pci_write_config_byte(pdev, I915_GDRST, 0);
1471
1472         return wait_for(i915_reset_complete(pdev), 500);
1473 }
1474
1475 static int g4x_reset_complete(struct pci_dev *pdev)
1476 {
1477         u8 gdrst;
1478         pci_read_config_byte(pdev, I915_GDRST, &gdrst);
1479         return (gdrst & GRDOM_RESET_ENABLE) == 0;
1480 }
1481
1482 static int g33_do_reset(struct drm_i915_private *dev_priv, unsigned engine_mask)
1483 {
1484         struct pci_dev *pdev = dev_priv->drm.pdev;
1485         pci_write_config_byte(pdev, I915_GDRST, GRDOM_RESET_ENABLE);
1486         return wait_for(g4x_reset_complete(pdev), 500);
1487 }
1488
1489 static int g4x_do_reset(struct drm_i915_private *dev_priv, unsigned engine_mask)
1490 {
1491         struct pci_dev *pdev = dev_priv->drm.pdev;
1492         int ret;
1493
1494         pci_write_config_byte(pdev, I915_GDRST,
1495                               GRDOM_RENDER | GRDOM_RESET_ENABLE);
1496         ret =  wait_for(g4x_reset_complete(pdev), 500);
1497         if (ret)
1498                 return ret;
1499
1500         /* WaVcpClkGateDisableForMediaReset:ctg,elk */
1501         I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) | VCP_UNIT_CLOCK_GATE_DISABLE);
1502         POSTING_READ(VDECCLK_GATE_D);
1503
1504         pci_write_config_byte(pdev, I915_GDRST,
1505                               GRDOM_MEDIA | GRDOM_RESET_ENABLE);
1506         ret =  wait_for(g4x_reset_complete(pdev), 500);
1507         if (ret)
1508                 return ret;
1509
1510         /* WaVcpClkGateDisableForMediaReset:ctg,elk */
1511         I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) & ~VCP_UNIT_CLOCK_GATE_DISABLE);
1512         POSTING_READ(VDECCLK_GATE_D);
1513
1514         pci_write_config_byte(pdev, I915_GDRST, 0);
1515
1516         return 0;
1517 }
1518
1519 static int ironlake_do_reset(struct drm_i915_private *dev_priv,
1520                              unsigned engine_mask)
1521 {
1522         int ret;
1523
1524         I915_WRITE(ILK_GDSR,
1525                    ILK_GRDOM_RENDER | ILK_GRDOM_RESET_ENABLE);
1526         ret = intel_wait_for_register(dev_priv,
1527                                       ILK_GDSR, ILK_GRDOM_RESET_ENABLE, 0,
1528                                       500);
1529         if (ret)
1530                 return ret;
1531
1532         I915_WRITE(ILK_GDSR,
1533                    ILK_GRDOM_MEDIA | ILK_GRDOM_RESET_ENABLE);
1534         ret = intel_wait_for_register(dev_priv,
1535                                       ILK_GDSR, ILK_GRDOM_RESET_ENABLE, 0,
1536                                       500);
1537         if (ret)
1538                 return ret;
1539
1540         I915_WRITE(ILK_GDSR, 0);
1541
1542         return 0;
1543 }
1544
1545 /* Reset the hardware domains (GENX_GRDOM_*) specified by mask */
1546 static int gen6_hw_domain_reset(struct drm_i915_private *dev_priv,
1547                                 u32 hw_domain_mask)
1548 {
1549         /* GEN6_GDRST is not in the gt power well, no need to check
1550          * for fifo space for the write or forcewake the chip for
1551          * the read
1552          */
1553         __raw_i915_write32(dev_priv, GEN6_GDRST, hw_domain_mask);
1554
1555         /* Spin waiting for the device to ack the reset requests */
1556         return intel_wait_for_register_fw(dev_priv,
1557                                           GEN6_GDRST, hw_domain_mask, 0,
1558                                           500);
1559 }
1560
1561 /**
1562  * gen6_reset_engines - reset individual engines
1563  * @dev_priv: i915 device
1564  * @engine_mask: mask of intel_ring_flag() engines or ALL_ENGINES for full reset
1565  *
1566  * This function will reset the individual engines that are set in engine_mask.
1567  * If you provide ALL_ENGINES as mask, full global domain reset will be issued.
1568  *
1569  * Note: It is responsibility of the caller to handle the difference between
1570  * asking full domain reset versus reset for all available individual engines.
1571  *
1572  * Returns 0 on success, nonzero on error.
1573  */
1574 static int gen6_reset_engines(struct drm_i915_private *dev_priv,
1575                               unsigned engine_mask)
1576 {
1577         struct intel_engine_cs *engine;
1578         const u32 hw_engine_mask[I915_NUM_ENGINES] = {
1579                 [RCS] = GEN6_GRDOM_RENDER,
1580                 [BCS] = GEN6_GRDOM_BLT,
1581                 [VCS] = GEN6_GRDOM_MEDIA,
1582                 [VCS2] = GEN8_GRDOM_MEDIA2,
1583                 [VECS] = GEN6_GRDOM_VECS,
1584         };
1585         u32 hw_mask;
1586         int ret;
1587
1588         if (engine_mask == ALL_ENGINES) {
1589                 hw_mask = GEN6_GRDOM_FULL;
1590         } else {
1591                 unsigned int tmp;
1592
1593                 hw_mask = 0;
1594                 for_each_engine_masked(engine, dev_priv, engine_mask, tmp)
1595                         hw_mask |= hw_engine_mask[engine->id];
1596         }
1597
1598         ret = gen6_hw_domain_reset(dev_priv, hw_mask);
1599
1600         intel_uncore_forcewake_reset(dev_priv, true);
1601
1602         return ret;
1603 }
1604
1605 /**
1606  * intel_wait_for_register_fw - wait until register matches expected state
1607  * @dev_priv: the i915 device
1608  * @reg: the register to read
1609  * @mask: mask to apply to register value
1610  * @value: expected value
1611  * @timeout_ms: timeout in millisecond
1612  *
1613  * This routine waits until the target register @reg contains the expected
1614  * @value after applying the @mask, i.e. it waits until ::
1615  *
1616  *     (I915_READ_FW(reg) & mask) == value
1617  *
1618  * Otherwise, the wait will timeout after @timeout_ms milliseconds.
1619  *
1620  * Note that this routine assumes the caller holds forcewake asserted, it is
1621  * not suitable for very long waits. See intel_wait_for_register() if you
1622  * wish to wait without holding forcewake for the duration (i.e. you expect
1623  * the wait to be slow).
1624  *
1625  * Returns 0 if the register matches the desired condition, or -ETIMEOUT.
1626  */
1627 int intel_wait_for_register_fw(struct drm_i915_private *dev_priv,
1628                                i915_reg_t reg,
1629                                const u32 mask,
1630                                const u32 value,
1631                                const unsigned long timeout_ms)
1632 {
1633 #define done ((I915_READ_FW(reg) & mask) == value)
1634         int ret = wait_for_us(done, 2);
1635         if (ret)
1636                 ret = wait_for(done, timeout_ms);
1637         return ret;
1638 #undef done
1639 }
1640
1641 /**
1642  * intel_wait_for_register - wait until register matches expected state
1643  * @dev_priv: the i915 device
1644  * @reg: the register to read
1645  * @mask: mask to apply to register value
1646  * @value: expected value
1647  * @timeout_ms: timeout in millisecond
1648  *
1649  * This routine waits until the target register @reg contains the expected
1650  * @value after applying the @mask, i.e. it waits until ::
1651  *
1652  *     (I915_READ(reg) & mask) == value
1653  *
1654  * Otherwise, the wait will timeout after @timeout_ms milliseconds.
1655  *
1656  * Returns 0 if the register matches the desired condition, or -ETIMEOUT.
1657  */
1658 int intel_wait_for_register(struct drm_i915_private *dev_priv,
1659                             i915_reg_t reg,
1660                             const u32 mask,
1661                             const u32 value,
1662                             const unsigned long timeout_ms)
1663 {
1664
1665         unsigned fw =
1666                 intel_uncore_forcewake_for_reg(dev_priv, reg, FW_REG_READ);
1667         int ret;
1668
1669         intel_uncore_forcewake_get(dev_priv, fw);
1670         ret = wait_for_us((I915_READ_FW(reg) & mask) == value, 2);
1671         intel_uncore_forcewake_put(dev_priv, fw);
1672         if (ret)
1673                 ret = wait_for((I915_READ_NOTRACE(reg) & mask) == value,
1674                                timeout_ms);
1675
1676         return ret;
1677 }
1678
1679 static int gen8_request_engine_reset(struct intel_engine_cs *engine)
1680 {
1681         struct drm_i915_private *dev_priv = engine->i915;
1682         int ret;
1683
1684         I915_WRITE_FW(RING_RESET_CTL(engine->mmio_base),
1685                       _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET));
1686
1687         ret = intel_wait_for_register_fw(dev_priv,
1688                                          RING_RESET_CTL(engine->mmio_base),
1689                                          RESET_CTL_READY_TO_RESET,
1690                                          RESET_CTL_READY_TO_RESET,
1691                                          700);
1692         if (ret)
1693                 DRM_ERROR("%s: reset request timeout\n", engine->name);
1694
1695         return ret;
1696 }
1697
1698 static void gen8_unrequest_engine_reset(struct intel_engine_cs *engine)
1699 {
1700         struct drm_i915_private *dev_priv = engine->i915;
1701
1702         I915_WRITE_FW(RING_RESET_CTL(engine->mmio_base),
1703                       _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET));
1704 }
1705
1706 static int gen8_reset_engines(struct drm_i915_private *dev_priv,
1707                               unsigned engine_mask)
1708 {
1709         struct intel_engine_cs *engine;
1710         unsigned int tmp;
1711
1712         for_each_engine_masked(engine, dev_priv, engine_mask, tmp)
1713                 if (gen8_request_engine_reset(engine))
1714                         goto not_ready;
1715
1716         return gen6_reset_engines(dev_priv, engine_mask);
1717
1718 not_ready:
1719         for_each_engine_masked(engine, dev_priv, engine_mask, tmp)
1720                 gen8_unrequest_engine_reset(engine);
1721
1722         return -EIO;
1723 }
1724
1725 typedef int (*reset_func)(struct drm_i915_private *, unsigned engine_mask);
1726
1727 static reset_func intel_get_gpu_reset(struct drm_i915_private *dev_priv)
1728 {
1729         if (!i915.reset)
1730                 return NULL;
1731
1732         if (INTEL_INFO(dev_priv)->gen >= 8)
1733                 return gen8_reset_engines;
1734         else if (INTEL_INFO(dev_priv)->gen >= 6)
1735                 return gen6_reset_engines;
1736         else if (IS_GEN5(dev_priv))
1737                 return ironlake_do_reset;
1738         else if (IS_G4X(dev_priv))
1739                 return g4x_do_reset;
1740         else if (IS_G33(dev_priv))
1741                 return g33_do_reset;
1742         else if (INTEL_INFO(dev_priv)->gen >= 3)
1743                 return i915_do_reset;
1744         else
1745                 return NULL;
1746 }
1747
1748 int intel_gpu_reset(struct drm_i915_private *dev_priv, unsigned engine_mask)
1749 {
1750         reset_func reset;
1751         int ret;
1752
1753         reset = intel_get_gpu_reset(dev_priv);
1754         if (reset == NULL)
1755                 return -ENODEV;
1756
1757         /* If the power well sleeps during the reset, the reset
1758          * request may be dropped and never completes (causing -EIO).
1759          */
1760         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1761         ret = reset(dev_priv, engine_mask);
1762         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1763
1764         return ret;
1765 }
1766
1767 bool intel_has_gpu_reset(struct drm_i915_private *dev_priv)
1768 {
1769         return intel_get_gpu_reset(dev_priv) != NULL;
1770 }
1771
1772 int intel_guc_reset(struct drm_i915_private *dev_priv)
1773 {
1774         int ret;
1775         unsigned long irqflags;
1776
1777         if (!HAS_GUC(dev_priv))
1778                 return -EINVAL;
1779
1780         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1781         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
1782
1783         ret = gen6_hw_domain_reset(dev_priv, GEN9_GRDOM_GUC);
1784
1785         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
1786         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1787
1788         return ret;
1789 }
1790
1791 bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv)
1792 {
1793         return check_for_unclaimed_mmio(dev_priv);
1794 }
1795
1796 bool
1797 intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv)
1798 {
1799         if (unlikely(i915.mmio_debug ||
1800                      dev_priv->uncore.unclaimed_mmio_check <= 0))
1801                 return false;
1802
1803         if (unlikely(intel_uncore_unclaimed_mmio(dev_priv))) {
1804                 DRM_DEBUG("Unclaimed register detected, "
1805                           "enabling oneshot unclaimed register reporting. "
1806                           "Please use i915.mmio_debug=N for more information.\n");
1807                 i915.mmio_debug++;
1808                 dev_priv->uncore.unclaimed_mmio_check--;
1809                 return true;
1810         }
1811
1812         return false;
1813 }
1814
1815 static enum forcewake_domains
1816 intel_uncore_forcewake_for_read(struct drm_i915_private *dev_priv,
1817                                 i915_reg_t reg)
1818 {
1819         enum forcewake_domains fw_domains;
1820
1821         if (intel_vgpu_active(dev_priv))
1822                 return 0;
1823
1824         switch (INTEL_GEN(dev_priv)) {
1825         case 9:
1826                 fw_domains = __gen9_reg_read_fw_domains(i915_mmio_reg_offset(reg));
1827                 break;
1828         case 8:
1829                 if (IS_CHERRYVIEW(dev_priv))
1830                         fw_domains = __chv_reg_read_fw_domains(i915_mmio_reg_offset(reg));
1831                 else
1832                         fw_domains = __gen6_reg_read_fw_domains(i915_mmio_reg_offset(reg));
1833                 break;
1834         case 7:
1835         case 6:
1836                 if (IS_VALLEYVIEW(dev_priv))
1837                         fw_domains = __vlv_reg_read_fw_domains(i915_mmio_reg_offset(reg));
1838                 else
1839                         fw_domains = __gen6_reg_read_fw_domains(i915_mmio_reg_offset(reg));
1840                 break;
1841         default:
1842                 MISSING_CASE(INTEL_INFO(dev_priv)->gen);
1843         case 5: /* forcewake was introduced with gen6 */
1844         case 4:
1845         case 3:
1846         case 2:
1847                 return 0;
1848         }
1849
1850         WARN_ON(fw_domains & ~dev_priv->uncore.fw_domains);
1851
1852         return fw_domains;
1853 }
1854
1855 static enum forcewake_domains
1856 intel_uncore_forcewake_for_write(struct drm_i915_private *dev_priv,
1857                                  i915_reg_t reg)
1858 {
1859         enum forcewake_domains fw_domains;
1860
1861         if (intel_vgpu_active(dev_priv))
1862                 return 0;
1863
1864         switch (INTEL_GEN(dev_priv)) {
1865         case 9:
1866                 fw_domains = __gen9_reg_write_fw_domains(i915_mmio_reg_offset(reg));
1867                 break;
1868         case 8:
1869                 if (IS_CHERRYVIEW(dev_priv))
1870                         fw_domains = __chv_reg_write_fw_domains(i915_mmio_reg_offset(reg));
1871                 else
1872                         fw_domains = __gen8_reg_write_fw_domains(i915_mmio_reg_offset(reg));
1873                 break;
1874         case 7:
1875         case 6:
1876                 fw_domains = FORCEWAKE_RENDER;
1877                 break;
1878         default:
1879                 MISSING_CASE(INTEL_INFO(dev_priv)->gen);
1880         case 5:
1881         case 4:
1882         case 3:
1883         case 2:
1884                 return 0;
1885         }
1886
1887         WARN_ON(fw_domains & ~dev_priv->uncore.fw_domains);
1888
1889         return fw_domains;
1890 }
1891
1892 /**
1893  * intel_uncore_forcewake_for_reg - which forcewake domains are needed to access
1894  *                                  a register
1895  * @dev_priv: pointer to struct drm_i915_private
1896  * @reg: register in question
1897  * @op: operation bitmask of FW_REG_READ and/or FW_REG_WRITE
1898  *
1899  * Returns a set of forcewake domains required to be taken with for example
1900  * intel_uncore_forcewake_get for the specified register to be accessible in the
1901  * specified mode (read, write or read/write) with raw mmio accessors.
1902  *
1903  * NOTE: On Gen6 and Gen7 write forcewake domain (FORCEWAKE_RENDER) requires the
1904  * callers to do FIFO management on their own or risk losing writes.
1905  */
1906 enum forcewake_domains
1907 intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv,
1908                                i915_reg_t reg, unsigned int op)
1909 {
1910         enum forcewake_domains fw_domains = 0;
1911
1912         WARN_ON(!op);
1913
1914         if (op & FW_REG_READ)
1915                 fw_domains = intel_uncore_forcewake_for_read(dev_priv, reg);
1916
1917         if (op & FW_REG_WRITE)
1918                 fw_domains |= intel_uncore_forcewake_for_write(dev_priv, reg);
1919
1920         return fw_domains;
1921 }