2 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/clk.h>
15 #include <linux/delay.h>
16 #include <linux/err.h>
17 #include <linux/gpio.h>
18 #include <linux/gpio/consumer.h>
19 #include <linux/interrupt.h>
20 #include <linux/of_device.h>
21 #include <linux/of_gpio.h>
22 #include <linux/of_irq.h>
23 #include <linux/pinctrl/consumer.h>
24 #include <linux/of_graph.h>
25 #include <linux/regulator/consumer.h>
26 #include <linux/spinlock.h>
27 #include <linux/mfd/syscon.h>
28 #include <linux/regmap.h>
29 #include <video/mipi_display.h>
36 static int dsi_get_version(const void __iomem *base, u32 *major, u32 *minor)
44 * From DSI6G(v3), addition of a 6G_HW_VERSION register at offset 0
45 * makes all other registers 4-byte shifted down.
47 * In order to identify between DSI6G(v3) and beyond, and DSIv2 and
48 * older, we read the DSI_VERSION register without any shift(offset
49 * 0x1f0). In the case of DSIv2, this hast to be a non-zero value. In
50 * the case of DSI6G, this has to be zero (the offset points to a
51 * scratch register which we never touch)
54 ver = msm_readl(base + REG_DSI_VERSION);
56 /* older dsi host, there is no register shift */
57 ver = FIELD(ver, DSI_VERSION_MAJOR);
58 if (ver <= MSM_DSI_VER_MAJOR_V2) {
68 * newer host, offset 0 has 6G_HW_VERSION, the rest of the
69 * registers are shifted down, read DSI_VERSION again with
72 ver = msm_readl(base + DSI_6G_REG_SHIFT + REG_DSI_VERSION);
73 ver = FIELD(ver, DSI_VERSION_MAJOR);
74 if (ver == MSM_DSI_VER_MAJOR_6G) {
77 *minor = msm_readl(base + REG_DSI_6G_HW_VERSION);
85 #define DSI_ERR_STATE_ACK 0x0000
86 #define DSI_ERR_STATE_TIMEOUT 0x0001
87 #define DSI_ERR_STATE_DLN0_PHY 0x0002
88 #define DSI_ERR_STATE_FIFO 0x0004
89 #define DSI_ERR_STATE_MDP_FIFO_UNDERFLOW 0x0008
90 #define DSI_ERR_STATE_INTERLEAVE_OP_CONTENTION 0x0010
91 #define DSI_ERR_STATE_PLL_UNLOCKED 0x0020
93 #define DSI_CLK_CTRL_ENABLE_CLKS \
94 (DSI_CLK_CTRL_AHBS_HCLK_ON | DSI_CLK_CTRL_AHBM_SCLK_ON | \
95 DSI_CLK_CTRL_PCLK_ON | DSI_CLK_CTRL_DSICLK_ON | \
96 DSI_CLK_CTRL_BYTECLK_ON | DSI_CLK_CTRL_ESCCLK_ON | \
97 DSI_CLK_CTRL_FORCE_ON_DYN_AHBM_HCLK)
100 struct mipi_dsi_host base;
102 struct platform_device *pdev;
103 struct drm_device *dev;
107 void __iomem *ctrl_base;
108 struct regulator_bulk_data supplies[DSI_DEV_REGULATOR_MAX];
110 struct clk *bus_clks[DSI_BUS_CLK_MAX];
112 struct clk *byte_clk;
114 struct clk *pixel_clk;
115 struct clk *byte_clk_src;
116 struct clk *pixel_clk_src;
121 /* DSI v2 specific clocks */
123 struct clk *esc_clk_src;
124 struct clk *dsi_clk_src;
128 struct gpio_desc *disp_en_gpio;
129 struct gpio_desc *te_gpio;
131 const struct msm_dsi_cfg_handler *cfg_hnd;
133 struct completion dma_comp;
134 struct completion video_comp;
135 struct mutex dev_mutex;
136 struct mutex cmd_mutex;
137 struct mutex clk_mutex;
138 spinlock_t intr_lock; /* Protect interrupt ctrl register */
141 struct work_struct err_work;
142 struct workqueue_struct *workqueue;
144 /* DSI 6G TX buffer*/
145 struct drm_gem_object *tx_gem_obj;
147 /* DSI v2 TX buffer */
149 dma_addr_t tx_buf_paddr;
157 struct drm_display_mode *mode;
159 /* connected device info */
160 struct device_node *device_node;
161 unsigned int channel;
163 enum mipi_dsi_pixel_format format;
164 unsigned long mode_flags;
166 /* lane data parsed via DT */
170 u32 dma_cmd_ctrl_restore;
177 static u32 dsi_get_bpp(const enum mipi_dsi_pixel_format fmt)
180 case MIPI_DSI_FMT_RGB565: return 16;
181 case MIPI_DSI_FMT_RGB666_PACKED: return 18;
182 case MIPI_DSI_FMT_RGB666:
183 case MIPI_DSI_FMT_RGB888:
188 static inline u32 dsi_read(struct msm_dsi_host *msm_host, u32 reg)
190 return msm_readl(msm_host->ctrl_base + reg);
192 static inline void dsi_write(struct msm_dsi_host *msm_host, u32 reg, u32 data)
194 msm_writel(data, msm_host->ctrl_base + reg);
197 static int dsi_host_regulator_enable(struct msm_dsi_host *msm_host);
198 static void dsi_host_regulator_disable(struct msm_dsi_host *msm_host);
200 static const struct msm_dsi_cfg_handler *dsi_get_config(
201 struct msm_dsi_host *msm_host)
203 const struct msm_dsi_cfg_handler *cfg_hnd = NULL;
204 struct device *dev = &msm_host->pdev->dev;
205 struct regulator *gdsc_reg;
208 u32 major = 0, minor = 0;
210 gdsc_reg = regulator_get(dev, "gdsc");
211 if (IS_ERR(gdsc_reg)) {
212 pr_err("%s: cannot get gdsc\n", __func__);
216 ahb_clk = clk_get(dev, "iface_clk");
217 if (IS_ERR(ahb_clk)) {
218 pr_err("%s: cannot get interface clock\n", __func__);
222 ret = regulator_enable(gdsc_reg);
224 pr_err("%s: unable to enable gdsc\n", __func__);
228 ret = clk_prepare_enable(ahb_clk);
230 pr_err("%s: unable to enable ahb_clk\n", __func__);
234 ret = dsi_get_version(msm_host->ctrl_base, &major, &minor);
236 pr_err("%s: Invalid version\n", __func__);
240 cfg_hnd = msm_dsi_cfg_get(major, minor);
242 DBG("%s: Version %x:%x\n", __func__, major, minor);
245 clk_disable_unprepare(ahb_clk);
247 regulator_disable(gdsc_reg);
251 regulator_put(gdsc_reg);
256 static inline struct msm_dsi_host *to_msm_dsi_host(struct mipi_dsi_host *host)
258 return container_of(host, struct msm_dsi_host, base);
261 static void dsi_host_regulator_disable(struct msm_dsi_host *msm_host)
263 struct regulator_bulk_data *s = msm_host->supplies;
264 const struct dsi_reg_entry *regs = msm_host->cfg_hnd->cfg->reg_cfg.regs;
265 int num = msm_host->cfg_hnd->cfg->reg_cfg.num;
269 for (i = num - 1; i >= 0; i--)
270 if (regs[i].disable_load >= 0)
271 regulator_set_load(s[i].consumer,
272 regs[i].disable_load);
274 regulator_bulk_disable(num, s);
277 static int dsi_host_regulator_enable(struct msm_dsi_host *msm_host)
279 struct regulator_bulk_data *s = msm_host->supplies;
280 const struct dsi_reg_entry *regs = msm_host->cfg_hnd->cfg->reg_cfg.regs;
281 int num = msm_host->cfg_hnd->cfg->reg_cfg.num;
285 for (i = 0; i < num; i++) {
286 if (regs[i].enable_load >= 0) {
287 ret = regulator_set_load(s[i].consumer,
288 regs[i].enable_load);
290 pr_err("regulator %d set op mode failed, %d\n",
297 ret = regulator_bulk_enable(num, s);
299 pr_err("regulator enable failed, %d\n", ret);
306 for (i--; i >= 0; i--)
307 regulator_set_load(s[i].consumer, regs[i].disable_load);
311 static int dsi_regulator_init(struct msm_dsi_host *msm_host)
313 struct regulator_bulk_data *s = msm_host->supplies;
314 const struct dsi_reg_entry *regs = msm_host->cfg_hnd->cfg->reg_cfg.regs;
315 int num = msm_host->cfg_hnd->cfg->reg_cfg.num;
318 for (i = 0; i < num; i++)
319 s[i].supply = regs[i].name;
321 ret = devm_regulator_bulk_get(&msm_host->pdev->dev, num, s);
323 pr_err("%s: failed to init regulator, ret=%d\n",
331 static int dsi_clk_init(struct msm_dsi_host *msm_host)
333 struct device *dev = &msm_host->pdev->dev;
334 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
335 const struct msm_dsi_config *cfg = cfg_hnd->cfg;
339 for (i = 0; i < cfg->num_bus_clks; i++) {
340 msm_host->bus_clks[i] = devm_clk_get(dev,
341 cfg->bus_clk_names[i]);
342 if (IS_ERR(msm_host->bus_clks[i])) {
343 ret = PTR_ERR(msm_host->bus_clks[i]);
344 pr_err("%s: Unable to get %s, ret = %d\n",
345 __func__, cfg->bus_clk_names[i], ret);
350 /* get link and source clocks */
351 msm_host->byte_clk = devm_clk_get(dev, "byte_clk");
352 if (IS_ERR(msm_host->byte_clk)) {
353 ret = PTR_ERR(msm_host->byte_clk);
354 pr_err("%s: can't find dsi_byte_clk. ret=%d\n",
356 msm_host->byte_clk = NULL;
360 msm_host->pixel_clk = devm_clk_get(dev, "pixel_clk");
361 if (IS_ERR(msm_host->pixel_clk)) {
362 ret = PTR_ERR(msm_host->pixel_clk);
363 pr_err("%s: can't find dsi_pixel_clk. ret=%d\n",
365 msm_host->pixel_clk = NULL;
369 msm_host->esc_clk = devm_clk_get(dev, "core_clk");
370 if (IS_ERR(msm_host->esc_clk)) {
371 ret = PTR_ERR(msm_host->esc_clk);
372 pr_err("%s: can't find dsi_esc_clk. ret=%d\n",
374 msm_host->esc_clk = NULL;
378 msm_host->byte_clk_src = clk_get_parent(msm_host->byte_clk);
379 if (!msm_host->byte_clk_src) {
381 pr_err("%s: can't find byte_clk_src. ret=%d\n", __func__, ret);
385 msm_host->pixel_clk_src = clk_get_parent(msm_host->pixel_clk);
386 if (!msm_host->pixel_clk_src) {
388 pr_err("%s: can't find pixel_clk_src. ret=%d\n", __func__, ret);
392 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_V2) {
393 msm_host->src_clk = devm_clk_get(dev, "src_clk");
394 if (IS_ERR(msm_host->src_clk)) {
395 ret = PTR_ERR(msm_host->src_clk);
396 pr_err("%s: can't find dsi_src_clk. ret=%d\n",
398 msm_host->src_clk = NULL;
402 msm_host->esc_clk_src = clk_get_parent(msm_host->esc_clk);
403 if (!msm_host->esc_clk_src) {
405 pr_err("%s: can't get esc_clk_src. ret=%d\n",
410 msm_host->dsi_clk_src = clk_get_parent(msm_host->src_clk);
411 if (!msm_host->dsi_clk_src) {
413 pr_err("%s: can't get dsi_clk_src. ret=%d\n",
421 static int dsi_bus_clk_enable(struct msm_dsi_host *msm_host)
423 const struct msm_dsi_config *cfg = msm_host->cfg_hnd->cfg;
426 DBG("id=%d", msm_host->id);
428 for (i = 0; i < cfg->num_bus_clks; i++) {
429 ret = clk_prepare_enable(msm_host->bus_clks[i]);
431 pr_err("%s: failed to enable bus clock %d ret %d\n",
440 clk_disable_unprepare(msm_host->bus_clks[i]);
445 static void dsi_bus_clk_disable(struct msm_dsi_host *msm_host)
447 const struct msm_dsi_config *cfg = msm_host->cfg_hnd->cfg;
452 for (i = cfg->num_bus_clks - 1; i >= 0; i--)
453 clk_disable_unprepare(msm_host->bus_clks[i]);
456 static int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host)
460 DBG("Set clk rates: pclk=%d, byteclk=%d",
461 msm_host->mode->clock, msm_host->byte_clk_rate);
463 ret = clk_set_rate(msm_host->byte_clk, msm_host->byte_clk_rate);
465 pr_err("%s: Failed to set rate byte clk, %d\n", __func__, ret);
469 ret = clk_set_rate(msm_host->pixel_clk, msm_host->mode->clock * 1000);
471 pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret);
475 ret = clk_prepare_enable(msm_host->esc_clk);
477 pr_err("%s: Failed to enable dsi esc clk\n", __func__);
481 ret = clk_prepare_enable(msm_host->byte_clk);
483 pr_err("%s: Failed to enable dsi byte clk\n", __func__);
487 ret = clk_prepare_enable(msm_host->pixel_clk);
489 pr_err("%s: Failed to enable dsi pixel clk\n", __func__);
496 clk_disable_unprepare(msm_host->byte_clk);
498 clk_disable_unprepare(msm_host->esc_clk);
503 static int dsi_link_clk_enable_v2(struct msm_dsi_host *msm_host)
507 DBG("Set clk rates: pclk=%d, byteclk=%d, esc_clk=%d, dsi_src_clk=%d",
508 msm_host->mode->clock, msm_host->byte_clk_rate,
509 msm_host->esc_clk_rate, msm_host->src_clk_rate);
511 ret = clk_set_rate(msm_host->byte_clk, msm_host->byte_clk_rate);
513 pr_err("%s: Failed to set rate byte clk, %d\n", __func__, ret);
517 ret = clk_set_rate(msm_host->esc_clk, msm_host->esc_clk_rate);
519 pr_err("%s: Failed to set rate esc clk, %d\n", __func__, ret);
523 ret = clk_set_rate(msm_host->src_clk, msm_host->src_clk_rate);
525 pr_err("%s: Failed to set rate src clk, %d\n", __func__, ret);
529 ret = clk_set_rate(msm_host->pixel_clk, msm_host->mode->clock * 1000);
531 pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret);
535 ret = clk_prepare_enable(msm_host->byte_clk);
537 pr_err("%s: Failed to enable dsi byte clk\n", __func__);
541 ret = clk_prepare_enable(msm_host->esc_clk);
543 pr_err("%s: Failed to enable dsi esc clk\n", __func__);
547 ret = clk_prepare_enable(msm_host->src_clk);
549 pr_err("%s: Failed to enable dsi src clk\n", __func__);
553 ret = clk_prepare_enable(msm_host->pixel_clk);
555 pr_err("%s: Failed to enable dsi pixel clk\n", __func__);
562 clk_disable_unprepare(msm_host->src_clk);
564 clk_disable_unprepare(msm_host->esc_clk);
566 clk_disable_unprepare(msm_host->byte_clk);
571 static int dsi_link_clk_enable(struct msm_dsi_host *msm_host)
573 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
575 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_6G)
576 return dsi_link_clk_enable_6g(msm_host);
578 return dsi_link_clk_enable_v2(msm_host);
581 static void dsi_link_clk_disable(struct msm_dsi_host *msm_host)
583 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
585 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) {
586 clk_disable_unprepare(msm_host->esc_clk);
587 clk_disable_unprepare(msm_host->pixel_clk);
588 clk_disable_unprepare(msm_host->byte_clk);
590 clk_disable_unprepare(msm_host->pixel_clk);
591 clk_disable_unprepare(msm_host->src_clk);
592 clk_disable_unprepare(msm_host->esc_clk);
593 clk_disable_unprepare(msm_host->byte_clk);
597 static int dsi_clk_ctrl(struct msm_dsi_host *msm_host, bool enable)
601 mutex_lock(&msm_host->clk_mutex);
603 ret = dsi_bus_clk_enable(msm_host);
605 pr_err("%s: Can not enable bus clk, %d\n",
609 ret = dsi_link_clk_enable(msm_host);
611 pr_err("%s: Can not enable link clk, %d\n",
613 dsi_bus_clk_disable(msm_host);
617 dsi_link_clk_disable(msm_host);
618 dsi_bus_clk_disable(msm_host);
622 mutex_unlock(&msm_host->clk_mutex);
626 static int dsi_calc_clk_rate(struct msm_dsi_host *msm_host)
628 struct drm_display_mode *mode = msm_host->mode;
629 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
630 u8 lanes = msm_host->lanes;
631 u32 bpp = dsi_get_bpp(msm_host->format);
635 pr_err("%s: mode not set\n", __func__);
639 pclk_rate = mode->clock * 1000;
641 msm_host->byte_clk_rate = (pclk_rate * bpp) / (8 * lanes);
643 pr_err("%s: forcing mdss_dsi lanes to 1\n", __func__);
644 msm_host->byte_clk_rate = (pclk_rate * bpp) / 8;
647 DBG("pclk=%d, bclk=%d", pclk_rate, msm_host->byte_clk_rate);
649 msm_host->esc_clk_rate = clk_get_rate(msm_host->esc_clk);
651 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_V2) {
652 unsigned int esc_mhz, esc_div;
653 unsigned long byte_mhz;
655 msm_host->src_clk_rate = (pclk_rate * bpp) / 8;
658 * esc clock is byte clock followed by a 4 bit divider,
659 * we need to find an escape clock frequency within the
660 * mipi DSI spec range within the maximum divider limit
661 * We iterate here between an escape clock frequencey
662 * between 20 Mhz to 5 Mhz and pick up the first one
663 * that can be supported by our divider
666 byte_mhz = msm_host->byte_clk_rate / 1000000;
668 for (esc_mhz = 20; esc_mhz >= 5; esc_mhz--) {
669 esc_div = DIV_ROUND_UP(byte_mhz, esc_mhz);
672 * TODO: Ideally, we shouldn't know what sort of divider
673 * is available in mmss_cc, we're just assuming that
674 * it'll always be a 4 bit divider. Need to come up with
677 if (esc_div >= 1 && esc_div <= 16)
684 msm_host->esc_clk_rate = msm_host->byte_clk_rate / esc_div;
686 DBG("esc=%d, src=%d", msm_host->esc_clk_rate,
687 msm_host->src_clk_rate);
693 static void dsi_phy_sw_reset(struct msm_dsi_host *msm_host)
696 dsi_write(msm_host, REG_DSI_PHY_RESET, DSI_PHY_RESET_RESET);
697 /* Make sure fully reset */
700 dsi_write(msm_host, REG_DSI_PHY_RESET, 0);
704 static void dsi_intr_ctrl(struct msm_dsi_host *msm_host, u32 mask, int enable)
709 spin_lock_irqsave(&msm_host->intr_lock, flags);
710 intr = dsi_read(msm_host, REG_DSI_INTR_CTRL);
717 DBG("intr=%x enable=%d", intr, enable);
719 dsi_write(msm_host, REG_DSI_INTR_CTRL, intr);
720 spin_unlock_irqrestore(&msm_host->intr_lock, flags);
723 static inline enum dsi_traffic_mode dsi_get_traffic_mode(const u32 mode_flags)
725 if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
727 else if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
728 return NON_BURST_SYNCH_PULSE;
730 return NON_BURST_SYNCH_EVENT;
733 static inline enum dsi_vid_dst_format dsi_get_vid_fmt(
734 const enum mipi_dsi_pixel_format mipi_fmt)
737 case MIPI_DSI_FMT_RGB888: return VID_DST_FORMAT_RGB888;
738 case MIPI_DSI_FMT_RGB666: return VID_DST_FORMAT_RGB666_LOOSE;
739 case MIPI_DSI_FMT_RGB666_PACKED: return VID_DST_FORMAT_RGB666;
740 case MIPI_DSI_FMT_RGB565: return VID_DST_FORMAT_RGB565;
741 default: return VID_DST_FORMAT_RGB888;
745 static inline enum dsi_cmd_dst_format dsi_get_cmd_fmt(
746 const enum mipi_dsi_pixel_format mipi_fmt)
749 case MIPI_DSI_FMT_RGB888: return CMD_DST_FORMAT_RGB888;
750 case MIPI_DSI_FMT_RGB666_PACKED:
751 case MIPI_DSI_FMT_RGB666: return VID_DST_FORMAT_RGB666;
752 case MIPI_DSI_FMT_RGB565: return CMD_DST_FORMAT_RGB565;
753 default: return CMD_DST_FORMAT_RGB888;
757 static void dsi_ctrl_config(struct msm_dsi_host *msm_host, bool enable,
758 u32 clk_pre, u32 clk_post)
760 u32 flags = msm_host->mode_flags;
761 enum mipi_dsi_pixel_format mipi_fmt = msm_host->format;
762 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
766 dsi_write(msm_host, REG_DSI_CTRL, 0);
770 if (flags & MIPI_DSI_MODE_VIDEO) {
771 if (flags & MIPI_DSI_MODE_VIDEO_HSE)
772 data |= DSI_VID_CFG0_PULSE_MODE_HSA_HE;
773 if (flags & MIPI_DSI_MODE_VIDEO_HFP)
774 data |= DSI_VID_CFG0_HFP_POWER_STOP;
775 if (flags & MIPI_DSI_MODE_VIDEO_HBP)
776 data |= DSI_VID_CFG0_HBP_POWER_STOP;
777 if (flags & MIPI_DSI_MODE_VIDEO_HSA)
778 data |= DSI_VID_CFG0_HSA_POWER_STOP;
779 /* Always set low power stop mode for BLLP
780 * to let command engine send packets
782 data |= DSI_VID_CFG0_EOF_BLLP_POWER_STOP |
783 DSI_VID_CFG0_BLLP_POWER_STOP;
784 data |= DSI_VID_CFG0_TRAFFIC_MODE(dsi_get_traffic_mode(flags));
785 data |= DSI_VID_CFG0_DST_FORMAT(dsi_get_vid_fmt(mipi_fmt));
786 data |= DSI_VID_CFG0_VIRT_CHANNEL(msm_host->channel);
787 dsi_write(msm_host, REG_DSI_VID_CFG0, data);
789 /* Do not swap RGB colors */
790 data = DSI_VID_CFG1_RGB_SWAP(SWAP_RGB);
791 dsi_write(msm_host, REG_DSI_VID_CFG1, 0);
793 /* Do not swap RGB colors */
794 data = DSI_CMD_CFG0_RGB_SWAP(SWAP_RGB);
795 data |= DSI_CMD_CFG0_DST_FORMAT(dsi_get_cmd_fmt(mipi_fmt));
796 dsi_write(msm_host, REG_DSI_CMD_CFG0, data);
798 data = DSI_CMD_CFG1_WR_MEM_START(MIPI_DCS_WRITE_MEMORY_START) |
799 DSI_CMD_CFG1_WR_MEM_CONTINUE(
800 MIPI_DCS_WRITE_MEMORY_CONTINUE);
801 /* Always insert DCS command */
802 data |= DSI_CMD_CFG1_INSERT_DCS_COMMAND;
803 dsi_write(msm_host, REG_DSI_CMD_CFG1, data);
806 dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL,
807 DSI_CMD_DMA_CTRL_FROM_FRAME_BUFFER |
808 DSI_CMD_DMA_CTRL_LOW_POWER);
811 /* Always assume dedicated TE pin */
812 data |= DSI_TRIG_CTRL_TE;
813 data |= DSI_TRIG_CTRL_MDP_TRIGGER(TRIGGER_NONE);
814 data |= DSI_TRIG_CTRL_DMA_TRIGGER(TRIGGER_SW);
815 data |= DSI_TRIG_CTRL_STREAM(msm_host->channel);
816 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) &&
817 (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_2))
818 data |= DSI_TRIG_CTRL_BLOCK_DMA_WITHIN_FRAME;
819 dsi_write(msm_host, REG_DSI_TRIG_CTRL, data);
821 data = DSI_CLKOUT_TIMING_CTRL_T_CLK_POST(clk_post) |
822 DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE(clk_pre);
823 dsi_write(msm_host, REG_DSI_CLKOUT_TIMING_CTRL, data);
826 if (!(flags & MIPI_DSI_MODE_EOT_PACKET))
827 data |= DSI_EOT_PACKET_CTRL_TX_EOT_APPEND;
828 dsi_write(msm_host, REG_DSI_EOT_PACKET_CTRL, data);
830 /* allow only ack-err-status to generate interrupt */
831 dsi_write(msm_host, REG_DSI_ERR_INT_MASK0, 0x13ff3fe0);
833 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 1);
835 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS);
837 data = DSI_CTRL_CLK_EN;
839 DBG("lane number=%d", msm_host->lanes);
840 data |= ((DSI_CTRL_LANE0 << msm_host->lanes) - DSI_CTRL_LANE0);
842 dsi_write(msm_host, REG_DSI_LANE_SWAP_CTRL,
843 DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(msm_host->dlane_swap));
845 if (!(flags & MIPI_DSI_CLOCK_NON_CONTINUOUS))
846 dsi_write(msm_host, REG_DSI_LANE_CTRL,
847 DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST);
849 data |= DSI_CTRL_ENABLE;
851 dsi_write(msm_host, REG_DSI_CTRL, data);
854 static void dsi_timing_setup(struct msm_dsi_host *msm_host)
856 struct drm_display_mode *mode = msm_host->mode;
857 u32 hs_start = 0, vs_start = 0; /* take sync start as 0 */
858 u32 h_total = mode->htotal;
859 u32 v_total = mode->vtotal;
860 u32 hs_end = mode->hsync_end - mode->hsync_start;
861 u32 vs_end = mode->vsync_end - mode->vsync_start;
862 u32 ha_start = h_total - mode->hsync_start;
863 u32 ha_end = ha_start + mode->hdisplay;
864 u32 va_start = v_total - mode->vsync_start;
865 u32 va_end = va_start + mode->vdisplay;
870 if (msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) {
871 dsi_write(msm_host, REG_DSI_ACTIVE_H,
872 DSI_ACTIVE_H_START(ha_start) |
873 DSI_ACTIVE_H_END(ha_end));
874 dsi_write(msm_host, REG_DSI_ACTIVE_V,
875 DSI_ACTIVE_V_START(va_start) |
876 DSI_ACTIVE_V_END(va_end));
877 dsi_write(msm_host, REG_DSI_TOTAL,
878 DSI_TOTAL_H_TOTAL(h_total - 1) |
879 DSI_TOTAL_V_TOTAL(v_total - 1));
881 dsi_write(msm_host, REG_DSI_ACTIVE_HSYNC,
882 DSI_ACTIVE_HSYNC_START(hs_start) |
883 DSI_ACTIVE_HSYNC_END(hs_end));
884 dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_HPOS, 0);
885 dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_VPOS,
886 DSI_ACTIVE_VSYNC_VPOS_START(vs_start) |
887 DSI_ACTIVE_VSYNC_VPOS_END(vs_end));
888 } else { /* command mode */
889 /* image data and 1 byte write_memory_start cmd */
890 wc = mode->hdisplay * dsi_get_bpp(msm_host->format) / 8 + 1;
892 dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM_CTRL,
893 DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT(wc) |
894 DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL(
896 DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE(
897 MIPI_DSI_DCS_LONG_WRITE));
899 dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM_TOTAL,
900 DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL(mode->hdisplay) |
901 DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL(mode->vdisplay));
905 static void dsi_sw_reset(struct msm_dsi_host *msm_host)
907 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS);
908 wmb(); /* clocks need to be enabled before reset */
910 dsi_write(msm_host, REG_DSI_RESET, 1);
911 wmb(); /* make sure reset happen */
912 dsi_write(msm_host, REG_DSI_RESET, 0);
915 static void dsi_op_mode_config(struct msm_dsi_host *msm_host,
916 bool video_mode, bool enable)
920 dsi_ctrl = dsi_read(msm_host, REG_DSI_CTRL);
923 dsi_ctrl &= ~(DSI_CTRL_ENABLE | DSI_CTRL_VID_MODE_EN |
924 DSI_CTRL_CMD_MODE_EN);
925 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_MDP_DONE |
926 DSI_IRQ_MASK_VIDEO_DONE, 0);
929 dsi_ctrl |= DSI_CTRL_VID_MODE_EN;
930 } else { /* command mode */
931 dsi_ctrl |= DSI_CTRL_CMD_MODE_EN;
932 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_MDP_DONE, 1);
934 dsi_ctrl |= DSI_CTRL_ENABLE;
937 dsi_write(msm_host, REG_DSI_CTRL, dsi_ctrl);
940 static void dsi_set_tx_power_mode(int mode, struct msm_dsi_host *msm_host)
944 data = dsi_read(msm_host, REG_DSI_CMD_DMA_CTRL);
947 data &= ~DSI_CMD_DMA_CTRL_LOW_POWER;
949 data |= DSI_CMD_DMA_CTRL_LOW_POWER;
951 dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL, data);
954 static void dsi_wait4video_done(struct msm_dsi_host *msm_host)
956 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 1);
958 reinit_completion(&msm_host->video_comp);
960 wait_for_completion_timeout(&msm_host->video_comp,
961 msecs_to_jiffies(70));
963 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 0);
966 static void dsi_wait4video_eng_busy(struct msm_dsi_host *msm_host)
968 if (!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO))
971 if (msm_host->power_on) {
972 dsi_wait4video_done(msm_host);
973 /* delay 4 ms to skip BLLP */
974 usleep_range(2000, 4000);
979 static int dsi_tx_buf_alloc(struct msm_dsi_host *msm_host, int size)
981 struct drm_device *dev = msm_host->dev;
982 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
986 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) {
987 mutex_lock(&dev->struct_mutex);
988 msm_host->tx_gem_obj = msm_gem_new(dev, size, MSM_BO_UNCACHED);
989 if (IS_ERR(msm_host->tx_gem_obj)) {
990 ret = PTR_ERR(msm_host->tx_gem_obj);
991 pr_err("%s: failed to allocate gem, %d\n",
993 msm_host->tx_gem_obj = NULL;
994 mutex_unlock(&dev->struct_mutex);
998 ret = msm_gem_get_iova_locked(msm_host->tx_gem_obj, 0, &iova);
999 mutex_unlock(&dev->struct_mutex);
1001 pr_err("%s: failed to get iova, %d\n", __func__, ret);
1006 pr_err("%s: buf NOT 8 bytes aligned\n", __func__);
1010 msm_host->tx_size = msm_host->tx_gem_obj->size;
1012 msm_host->tx_buf = dma_alloc_coherent(dev->dev, size,
1013 &msm_host->tx_buf_paddr, GFP_KERNEL);
1014 if (!msm_host->tx_buf) {
1016 pr_err("%s: failed to allocate tx buf, %d\n",
1021 msm_host->tx_size = size;
1027 static void dsi_tx_buf_free(struct msm_dsi_host *msm_host)
1029 struct drm_device *dev = msm_host->dev;
1031 if (msm_host->tx_gem_obj) {
1032 msm_gem_put_iova(msm_host->tx_gem_obj, 0);
1033 mutex_lock(&dev->struct_mutex);
1034 msm_gem_free_object(msm_host->tx_gem_obj);
1035 msm_host->tx_gem_obj = NULL;
1036 mutex_unlock(&dev->struct_mutex);
1039 if (msm_host->tx_buf)
1040 dma_free_coherent(dev->dev, msm_host->tx_size, msm_host->tx_buf,
1041 msm_host->tx_buf_paddr);
1045 * prepare cmd buffer to be txed
1047 static int dsi_cmd_dma_add(struct msm_dsi_host *msm_host,
1048 const struct mipi_dsi_msg *msg)
1050 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
1051 struct mipi_dsi_packet packet;
1056 ret = mipi_dsi_create_packet(&packet, msg);
1058 pr_err("%s: create packet failed, %d\n", __func__, ret);
1061 len = (packet.size + 3) & (~0x3);
1063 if (len > msm_host->tx_size) {
1064 pr_err("%s: packet size is too big\n", __func__);
1068 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) {
1069 data = msm_gem_vaddr(msm_host->tx_gem_obj);
1071 ret = PTR_ERR(data);
1072 pr_err("%s: get vaddr failed, %d\n", __func__, ret);
1076 data = msm_host->tx_buf;
1079 /* MSM specific command format in memory */
1080 data[0] = packet.header[1];
1081 data[1] = packet.header[2];
1082 data[2] = packet.header[0];
1083 data[3] = BIT(7); /* Last packet */
1084 if (mipi_dsi_packet_format_is_long(msg->type))
1086 if (msg->rx_buf && msg->rx_len)
1090 if (packet.payload && packet.payload_length)
1091 memcpy(data + 4, packet.payload, packet.payload_length);
1093 /* Append 0xff to the end */
1094 if (packet.size < len)
1095 memset(data + packet.size, 0xff, len - packet.size);
1101 * dsi_short_read1_resp: 1 parameter
1103 static int dsi_short_read1_resp(u8 *buf, const struct mipi_dsi_msg *msg)
1105 u8 *data = msg->rx_buf;
1106 if (data && (msg->rx_len >= 1)) {
1107 *data = buf[1]; /* strip out dcs type */
1110 pr_err("%s: read data does not match with rx_buf len %zu\n",
1111 __func__, msg->rx_len);
1117 * dsi_short_read2_resp: 2 parameter
1119 static int dsi_short_read2_resp(u8 *buf, const struct mipi_dsi_msg *msg)
1121 u8 *data = msg->rx_buf;
1122 if (data && (msg->rx_len >= 2)) {
1123 data[0] = buf[1]; /* strip out dcs type */
1127 pr_err("%s: read data does not match with rx_buf len %zu\n",
1128 __func__, msg->rx_len);
1133 static int dsi_long_read_resp(u8 *buf, const struct mipi_dsi_msg *msg)
1135 /* strip out 4 byte dcs header */
1136 if (msg->rx_buf && msg->rx_len)
1137 memcpy(msg->rx_buf, buf + 4, msg->rx_len);
1142 static int dsi_cmd_dma_tx(struct msm_dsi_host *msm_host, int len)
1144 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
1149 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) {
1150 ret = msm_gem_get_iova(msm_host->tx_gem_obj, 0, &dma_base);
1152 pr_err("%s: failed to get iova: %d\n", __func__, ret);
1156 dma_base = msm_host->tx_buf_paddr;
1159 reinit_completion(&msm_host->dma_comp);
1161 dsi_wait4video_eng_busy(msm_host);
1163 triggered = msm_dsi_manager_cmd_xfer_trigger(
1164 msm_host->id, dma_base, len);
1166 ret = wait_for_completion_timeout(&msm_host->dma_comp,
1167 msecs_to_jiffies(200));
1179 static int dsi_cmd_dma_rx(struct msm_dsi_host *msm_host,
1180 u8 *buf, int rx_byte, int pkt_size)
1182 u32 *lp, *temp, data;
1186 int repeated_bytes = 0;
1187 int buf_offset = buf - msm_host->rx_buf;
1191 cnt = (rx_byte + 3) >> 2;
1193 cnt = 4; /* 4 x 32 bits registers only */
1198 read_cnt = pkt_size + 6;
1201 * In case of multiple reads from the panel, after the first read, there
1202 * is possibility that there are some bytes in the payload repeating in
1203 * the RDBK_DATA registers. Since we read all the parameters from the
1204 * panel right from the first byte for every pass. We need to skip the
1205 * repeating bytes and then append the new parameters to the rx buffer.
1207 if (read_cnt > 16) {
1209 /* Any data more than 16 bytes will be shifted out.
1210 * The temp read buffer should already contain these bytes.
1211 * The remaining bytes in read buffer are the repeated bytes.
1213 bytes_shifted = read_cnt - 16;
1214 repeated_bytes = buf_offset - bytes_shifted;
1217 for (i = cnt - 1; i >= 0; i--) {
1218 data = dsi_read(msm_host, REG_DSI_RDBK_DATA(i));
1219 *temp++ = ntohl(data); /* to host byte order */
1220 DBG("data = 0x%x and ntohl(data) = 0x%x", data, ntohl(data));
1223 for (i = repeated_bytes; i < 16; i++)
1229 static int dsi_cmds2buf_tx(struct msm_dsi_host *msm_host,
1230 const struct mipi_dsi_msg *msg)
1233 int bllp_len = msm_host->mode->hdisplay *
1234 dsi_get_bpp(msm_host->format) / 8;
1236 len = dsi_cmd_dma_add(msm_host, msg);
1238 pr_err("%s: failed to add cmd type = 0x%x\n",
1239 __func__, msg->type);
1243 /* for video mode, do not send cmds more than
1244 * one pixel line, since it only transmit it
1247 /* TODO: if the command is sent in LP mode, the bit rate is only
1248 * half of esc clk rate. In this case, if the video is already
1249 * actively streaming, we need to check more carefully if the
1250 * command can be fit into one BLLP.
1252 if ((msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) && (len > bllp_len)) {
1253 pr_err("%s: cmd cannot fit into BLLP period, len=%d\n",
1258 ret = dsi_cmd_dma_tx(msm_host, len);
1260 pr_err("%s: cmd dma tx failed, type=0x%x, data0=0x%x, len=%d\n",
1261 __func__, msg->type, (*(u8 *)(msg->tx_buf)), len);
1268 static void dsi_sw_reset_restore(struct msm_dsi_host *msm_host)
1272 data0 = dsi_read(msm_host, REG_DSI_CTRL);
1274 data1 &= ~DSI_CTRL_ENABLE;
1275 dsi_write(msm_host, REG_DSI_CTRL, data1);
1277 * dsi controller need to be disabled before
1282 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS);
1283 wmb(); /* make sure clocks enabled */
1285 /* dsi controller can only be reset while clocks are running */
1286 dsi_write(msm_host, REG_DSI_RESET, 1);
1287 wmb(); /* make sure reset happen */
1288 dsi_write(msm_host, REG_DSI_RESET, 0);
1289 wmb(); /* controller out of reset */
1290 dsi_write(msm_host, REG_DSI_CTRL, data0);
1291 wmb(); /* make sure dsi controller enabled again */
1294 static void dsi_err_worker(struct work_struct *work)
1296 struct msm_dsi_host *msm_host =
1297 container_of(work, struct msm_dsi_host, err_work);
1298 u32 status = msm_host->err_work_state;
1300 pr_err_ratelimited("%s: status=%x\n", __func__, status);
1301 if (status & DSI_ERR_STATE_MDP_FIFO_UNDERFLOW)
1302 dsi_sw_reset_restore(msm_host);
1304 /* It is safe to clear here because error irq is disabled. */
1305 msm_host->err_work_state = 0;
1307 /* enable dsi error interrupt */
1308 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 1);
1311 static void dsi_ack_err_status(struct msm_dsi_host *msm_host)
1315 status = dsi_read(msm_host, REG_DSI_ACK_ERR_STATUS);
1318 dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, status);
1319 /* Writing of an extra 0 needed to clear error bits */
1320 dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, 0);
1321 msm_host->err_work_state |= DSI_ERR_STATE_ACK;
1325 static void dsi_timeout_status(struct msm_dsi_host *msm_host)
1329 status = dsi_read(msm_host, REG_DSI_TIMEOUT_STATUS);
1332 dsi_write(msm_host, REG_DSI_TIMEOUT_STATUS, status);
1333 msm_host->err_work_state |= DSI_ERR_STATE_TIMEOUT;
1337 static void dsi_dln0_phy_err(struct msm_dsi_host *msm_host)
1341 status = dsi_read(msm_host, REG_DSI_DLN0_PHY_ERR);
1343 if (status & (DSI_DLN0_PHY_ERR_DLN0_ERR_ESC |
1344 DSI_DLN0_PHY_ERR_DLN0_ERR_SYNC_ESC |
1345 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTROL |
1346 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP0 |
1347 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP1)) {
1348 dsi_write(msm_host, REG_DSI_DLN0_PHY_ERR, status);
1349 msm_host->err_work_state |= DSI_ERR_STATE_DLN0_PHY;
1353 static void dsi_fifo_status(struct msm_dsi_host *msm_host)
1357 status = dsi_read(msm_host, REG_DSI_FIFO_STATUS);
1359 /* fifo underflow, overflow */
1361 dsi_write(msm_host, REG_DSI_FIFO_STATUS, status);
1362 msm_host->err_work_state |= DSI_ERR_STATE_FIFO;
1363 if (status & DSI_FIFO_STATUS_CMD_MDP_FIFO_UNDERFLOW)
1364 msm_host->err_work_state |=
1365 DSI_ERR_STATE_MDP_FIFO_UNDERFLOW;
1369 static void dsi_status(struct msm_dsi_host *msm_host)
1373 status = dsi_read(msm_host, REG_DSI_STATUS0);
1375 if (status & DSI_STATUS0_INTERLEAVE_OP_CONTENTION) {
1376 dsi_write(msm_host, REG_DSI_STATUS0, status);
1377 msm_host->err_work_state |=
1378 DSI_ERR_STATE_INTERLEAVE_OP_CONTENTION;
1382 static void dsi_clk_status(struct msm_dsi_host *msm_host)
1386 status = dsi_read(msm_host, REG_DSI_CLK_STATUS);
1388 if (status & DSI_CLK_STATUS_PLL_UNLOCKED) {
1389 dsi_write(msm_host, REG_DSI_CLK_STATUS, status);
1390 msm_host->err_work_state |= DSI_ERR_STATE_PLL_UNLOCKED;
1394 static void dsi_error(struct msm_dsi_host *msm_host)
1396 /* disable dsi error interrupt */
1397 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 0);
1399 dsi_clk_status(msm_host);
1400 dsi_fifo_status(msm_host);
1401 dsi_ack_err_status(msm_host);
1402 dsi_timeout_status(msm_host);
1403 dsi_status(msm_host);
1404 dsi_dln0_phy_err(msm_host);
1406 queue_work(msm_host->workqueue, &msm_host->err_work);
1409 static irqreturn_t dsi_host_irq(int irq, void *ptr)
1411 struct msm_dsi_host *msm_host = ptr;
1413 unsigned long flags;
1415 if (!msm_host->ctrl_base)
1418 spin_lock_irqsave(&msm_host->intr_lock, flags);
1419 isr = dsi_read(msm_host, REG_DSI_INTR_CTRL);
1420 dsi_write(msm_host, REG_DSI_INTR_CTRL, isr);
1421 spin_unlock_irqrestore(&msm_host->intr_lock, flags);
1423 DBG("isr=0x%x, id=%d", isr, msm_host->id);
1425 if (isr & DSI_IRQ_ERROR)
1426 dsi_error(msm_host);
1428 if (isr & DSI_IRQ_VIDEO_DONE)
1429 complete(&msm_host->video_comp);
1431 if (isr & DSI_IRQ_CMD_DMA_DONE)
1432 complete(&msm_host->dma_comp);
1437 static int dsi_host_init_panel_gpios(struct msm_dsi_host *msm_host,
1438 struct device *panel_device)
1440 msm_host->disp_en_gpio = devm_gpiod_get_optional(panel_device,
1443 if (IS_ERR(msm_host->disp_en_gpio)) {
1444 DBG("cannot get disp-enable-gpios %ld",
1445 PTR_ERR(msm_host->disp_en_gpio));
1446 return PTR_ERR(msm_host->disp_en_gpio);
1449 msm_host->te_gpio = devm_gpiod_get_optional(panel_device, "disp-te",
1451 if (IS_ERR(msm_host->te_gpio)) {
1452 DBG("cannot get disp-te-gpios %ld", PTR_ERR(msm_host->te_gpio));
1453 return PTR_ERR(msm_host->te_gpio);
1459 static int dsi_host_attach(struct mipi_dsi_host *host,
1460 struct mipi_dsi_device *dsi)
1462 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1465 if (dsi->lanes > msm_host->num_data_lanes)
1468 msm_host->channel = dsi->channel;
1469 msm_host->lanes = dsi->lanes;
1470 msm_host->format = dsi->format;
1471 msm_host->mode_flags = dsi->mode_flags;
1473 /* Some gpios defined in panel DT need to be controlled by host */
1474 ret = dsi_host_init_panel_gpios(msm_host, &dsi->dev);
1478 DBG("id=%d", msm_host->id);
1480 drm_helper_hpd_irq_event(msm_host->dev);
1485 static int dsi_host_detach(struct mipi_dsi_host *host,
1486 struct mipi_dsi_device *dsi)
1488 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1490 msm_host->device_node = NULL;
1492 DBG("id=%d", msm_host->id);
1494 drm_helper_hpd_irq_event(msm_host->dev);
1499 static ssize_t dsi_host_transfer(struct mipi_dsi_host *host,
1500 const struct mipi_dsi_msg *msg)
1502 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1505 if (!msg || !msm_host->power_on)
1508 mutex_lock(&msm_host->cmd_mutex);
1509 ret = msm_dsi_manager_cmd_xfer(msm_host->id, msg);
1510 mutex_unlock(&msm_host->cmd_mutex);
1515 static struct mipi_dsi_host_ops dsi_host_ops = {
1516 .attach = dsi_host_attach,
1517 .detach = dsi_host_detach,
1518 .transfer = dsi_host_transfer,
1522 * List of supported physical to logical lane mappings.
1523 * For example, the 2nd entry represents the following mapping:
1525 * "3012": Logic 3->Phys 0; Logic 0->Phys 1; Logic 1->Phys 2; Logic 2->Phys 3;
1527 static const int supported_data_lane_swaps[][4] = {
1538 static int dsi_host_parse_lane_data(struct msm_dsi_host *msm_host,
1539 struct device_node *ep)
1541 struct device *dev = &msm_host->pdev->dev;
1542 struct property *prop;
1544 int ret, i, len, num_lanes;
1546 prop = of_find_property(ep, "qcom,data-lane-map", &len);
1548 dev_dbg(dev, "failed to find data lane mapping\n");
1552 num_lanes = len / sizeof(u32);
1554 if (num_lanes < 1 || num_lanes > 4) {
1555 dev_err(dev, "bad number of data lanes\n");
1559 msm_host->num_data_lanes = num_lanes;
1561 ret = of_property_read_u32_array(ep, "qcom,data-lane-map", lane_map,
1564 dev_err(dev, "failed to read lane data\n");
1569 * compare DT specified physical-logical lane mappings with the ones
1570 * supported by hardware
1572 for (i = 0; i < ARRAY_SIZE(supported_data_lane_swaps); i++) {
1573 const int *swap = supported_data_lane_swaps[i];
1576 for (j = 0; j < num_lanes; j++) {
1577 if (swap[j] != lane_map[j])
1581 if (j == num_lanes) {
1582 msm_host->dlane_swap = i;
1590 static int dsi_host_parse_dt(struct msm_dsi_host *msm_host)
1592 struct device *dev = &msm_host->pdev->dev;
1593 struct device_node *np = dev->of_node;
1594 struct device_node *endpoint, *device_node;
1597 ret = of_property_read_u32(np, "qcom,dsi-host-index", &msm_host->id);
1599 dev_err(dev, "%s: host index not specified, ret=%d\n",
1605 * Get the first endpoint node. In our case, dsi has one output port
1606 * to which the panel is connected. Don't return an error if a port
1607 * isn't defined. It's possible that there is nothing connected to
1610 endpoint = of_graph_get_next_endpoint(np, NULL);
1612 dev_dbg(dev, "%s: no endpoint\n", __func__);
1616 ret = dsi_host_parse_lane_data(msm_host, endpoint);
1618 dev_err(dev, "%s: invalid lane configuration %d\n",
1623 /* Get panel node from the output port's endpoint data */
1624 device_node = of_graph_get_remote_port_parent(endpoint);
1626 dev_err(dev, "%s: no valid device\n", __func__);
1631 msm_host->device_node = device_node;
1633 if (of_property_read_bool(np, "syscon-sfpb")) {
1634 msm_host->sfpb = syscon_regmap_lookup_by_phandle(np,
1636 if (IS_ERR(msm_host->sfpb)) {
1637 dev_err(dev, "%s: failed to get sfpb regmap\n",
1639 ret = PTR_ERR(msm_host->sfpb);
1643 of_node_put(device_node);
1646 of_node_put(endpoint);
1651 int msm_dsi_host_init(struct msm_dsi *msm_dsi)
1653 struct msm_dsi_host *msm_host = NULL;
1654 struct platform_device *pdev = msm_dsi->pdev;
1657 msm_host = devm_kzalloc(&pdev->dev, sizeof(*msm_host), GFP_KERNEL);
1659 pr_err("%s: FAILED: cannot alloc dsi host\n",
1665 msm_host->pdev = pdev;
1667 ret = dsi_host_parse_dt(msm_host);
1669 pr_err("%s: failed to parse dt\n", __func__);
1673 msm_host->ctrl_base = msm_ioremap(pdev, "dsi_ctrl", "DSI CTRL");
1674 if (IS_ERR(msm_host->ctrl_base)) {
1675 pr_err("%s: unable to map Dsi ctrl base\n", __func__);
1676 ret = PTR_ERR(msm_host->ctrl_base);
1680 msm_host->cfg_hnd = dsi_get_config(msm_host);
1681 if (!msm_host->cfg_hnd) {
1683 pr_err("%s: get config failed\n", __func__);
1687 /* fixup base address by io offset */
1688 msm_host->ctrl_base += msm_host->cfg_hnd->cfg->io_offset;
1690 ret = dsi_regulator_init(msm_host);
1692 pr_err("%s: regulator init failed\n", __func__);
1696 ret = dsi_clk_init(msm_host);
1698 pr_err("%s: unable to initialize dsi clks\n", __func__);
1702 msm_host->rx_buf = devm_kzalloc(&pdev->dev, SZ_4K, GFP_KERNEL);
1703 if (!msm_host->rx_buf) {
1704 pr_err("%s: alloc rx temp buf failed\n", __func__);
1708 init_completion(&msm_host->dma_comp);
1709 init_completion(&msm_host->video_comp);
1710 mutex_init(&msm_host->dev_mutex);
1711 mutex_init(&msm_host->cmd_mutex);
1712 mutex_init(&msm_host->clk_mutex);
1713 spin_lock_init(&msm_host->intr_lock);
1715 /* setup workqueue */
1716 msm_host->workqueue = alloc_ordered_workqueue("dsi_drm_work", 0);
1717 INIT_WORK(&msm_host->err_work, dsi_err_worker);
1719 msm_dsi->host = &msm_host->base;
1720 msm_dsi->id = msm_host->id;
1722 DBG("Dsi Host %d initialized", msm_host->id);
1729 void msm_dsi_host_destroy(struct mipi_dsi_host *host)
1731 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1734 dsi_tx_buf_free(msm_host);
1735 if (msm_host->workqueue) {
1736 flush_workqueue(msm_host->workqueue);
1737 destroy_workqueue(msm_host->workqueue);
1738 msm_host->workqueue = NULL;
1741 mutex_destroy(&msm_host->clk_mutex);
1742 mutex_destroy(&msm_host->cmd_mutex);
1743 mutex_destroy(&msm_host->dev_mutex);
1746 int msm_dsi_host_modeset_init(struct mipi_dsi_host *host,
1747 struct drm_device *dev)
1749 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1750 struct platform_device *pdev = msm_host->pdev;
1753 msm_host->irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
1754 if (msm_host->irq < 0) {
1755 ret = msm_host->irq;
1756 dev_err(dev->dev, "failed to get irq: %d\n", ret);
1760 ret = devm_request_irq(&pdev->dev, msm_host->irq,
1761 dsi_host_irq, IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
1762 "dsi_isr", msm_host);
1764 dev_err(&pdev->dev, "failed to request IRQ%u: %d\n",
1765 msm_host->irq, ret);
1769 msm_host->dev = dev;
1770 ret = dsi_tx_buf_alloc(msm_host, SZ_4K);
1772 pr_err("%s: alloc tx gem obj failed, %d\n", __func__, ret);
1779 int msm_dsi_host_register(struct mipi_dsi_host *host, bool check_defer)
1781 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1784 /* Register mipi dsi host */
1785 if (!msm_host->registered) {
1786 host->dev = &msm_host->pdev->dev;
1787 host->ops = &dsi_host_ops;
1788 ret = mipi_dsi_host_register(host);
1792 msm_host->registered = true;
1794 /* If the panel driver has not been probed after host register,
1795 * we should defer the host's probe.
1796 * It makes sure panel is connected when fbcon detects
1797 * connector status and gets the proper display mode to
1798 * create framebuffer.
1799 * Don't try to defer if there is nothing connected to the dsi
1802 if (check_defer && msm_host->device_node) {
1803 if (!of_drm_find_panel(msm_host->device_node))
1804 if (!of_drm_find_bridge(msm_host->device_node))
1805 return -EPROBE_DEFER;
1812 void msm_dsi_host_unregister(struct mipi_dsi_host *host)
1814 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1816 if (msm_host->registered) {
1817 mipi_dsi_host_unregister(host);
1820 msm_host->registered = false;
1824 int msm_dsi_host_xfer_prepare(struct mipi_dsi_host *host,
1825 const struct mipi_dsi_msg *msg)
1827 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1829 /* TODO: make sure dsi_cmd_mdp is idle.
1830 * Since DSI6G v1.2.0, we can set DSI_TRIG_CTRL.BLOCK_DMA_WITHIN_FRAME
1831 * to ask H/W to wait until cmd mdp is idle. S/W wait is not needed.
1832 * How to handle the old versions? Wait for mdp cmd done?
1836 * mdss interrupt is generated in mdp core clock domain
1837 * mdp clock need to be enabled to receive dsi interrupt
1839 dsi_clk_ctrl(msm_host, 1);
1841 /* TODO: vote for bus bandwidth */
1843 if (!(msg->flags & MIPI_DSI_MSG_USE_LPM))
1844 dsi_set_tx_power_mode(0, msm_host);
1846 msm_host->dma_cmd_ctrl_restore = dsi_read(msm_host, REG_DSI_CTRL);
1847 dsi_write(msm_host, REG_DSI_CTRL,
1848 msm_host->dma_cmd_ctrl_restore |
1849 DSI_CTRL_CMD_MODE_EN |
1851 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_DMA_DONE, 1);
1856 void msm_dsi_host_xfer_restore(struct mipi_dsi_host *host,
1857 const struct mipi_dsi_msg *msg)
1859 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1861 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_DMA_DONE, 0);
1862 dsi_write(msm_host, REG_DSI_CTRL, msm_host->dma_cmd_ctrl_restore);
1864 if (!(msg->flags & MIPI_DSI_MSG_USE_LPM))
1865 dsi_set_tx_power_mode(1, msm_host);
1867 /* TODO: unvote for bus bandwidth */
1869 dsi_clk_ctrl(msm_host, 0);
1872 int msm_dsi_host_cmd_tx(struct mipi_dsi_host *host,
1873 const struct mipi_dsi_msg *msg)
1875 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1877 return dsi_cmds2buf_tx(msm_host, msg);
1880 int msm_dsi_host_cmd_rx(struct mipi_dsi_host *host,
1881 const struct mipi_dsi_msg *msg)
1883 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1884 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
1885 int data_byte, rx_byte, dlen, end;
1886 int short_response, diff, pkt_size, ret = 0;
1888 int rlen = msg->rx_len;
1897 data_byte = 10; /* first read */
1898 if (rlen < data_byte)
1901 pkt_size = data_byte;
1902 rx_byte = data_byte + 6; /* 4 header + 2 crc */
1905 buf = msm_host->rx_buf;
1908 u8 tx[2] = {pkt_size & 0xff, pkt_size >> 8};
1909 struct mipi_dsi_msg max_pkt_size_msg = {
1910 .channel = msg->channel,
1911 .type = MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE,
1916 DBG("rlen=%d pkt_size=%d rx_byte=%d",
1917 rlen, pkt_size, rx_byte);
1919 ret = dsi_cmds2buf_tx(msm_host, &max_pkt_size_msg);
1921 pr_err("%s: Set max pkt size failed, %d\n",
1926 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) &&
1927 (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_1)) {
1928 /* Clear the RDBK_DATA registers */
1929 dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL,
1930 DSI_RDBK_DATA_CTRL_CLR);
1931 wmb(); /* make sure the RDBK registers are cleared */
1932 dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL, 0);
1933 wmb(); /* release cleared status before transfer */
1936 ret = dsi_cmds2buf_tx(msm_host, msg);
1937 if (ret < msg->tx_len) {
1938 pr_err("%s: Read cmd Tx failed, %d\n", __func__, ret);
1943 * once cmd_dma_done interrupt received,
1944 * return data from client is ready and stored
1945 * at RDBK_DATA register already
1946 * since rx fifo is 16 bytes, dcs header is kept at first loop,
1947 * after that dcs header lost during shift into registers
1949 dlen = dsi_cmd_dma_rx(msm_host, buf, rx_byte, pkt_size);
1957 if (rlen <= data_byte) {
1958 diff = data_byte - rlen;
1966 dlen -= 2; /* 2 crc */
1968 buf += dlen; /* next start position */
1969 data_byte = 14; /* NOT first read */
1970 if (rlen < data_byte)
1973 pkt_size += data_byte;
1974 DBG("buf=%p dlen=%d diff=%d", buf, dlen, diff);
1979 * For single Long read, if the requested rlen < 10,
1980 * we need to shift the start position of rx
1981 * data buffer to skip the bytes which are not
1984 if (pkt_size < 10 && !short_response)
1985 buf = msm_host->rx_buf + (10 - rlen);
1987 buf = msm_host->rx_buf;
1991 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
1992 pr_err("%s: rx ACK_ERR_PACLAGE\n", __func__);
1995 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:
1996 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
1997 ret = dsi_short_read1_resp(buf, msg);
1999 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:
2000 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
2001 ret = dsi_short_read2_resp(buf, msg);
2003 case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE:
2004 case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE:
2005 ret = dsi_long_read_resp(buf, msg);
2008 pr_warn("%s:Invalid response cmd\n", __func__);
2015 void msm_dsi_host_cmd_xfer_commit(struct mipi_dsi_host *host, u32 dma_base,
2018 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2020 dsi_write(msm_host, REG_DSI_DMA_BASE, dma_base);
2021 dsi_write(msm_host, REG_DSI_DMA_LEN, len);
2022 dsi_write(msm_host, REG_DSI_TRIG_DMA, 1);
2024 /* Make sure trigger happens */
2028 int msm_dsi_host_set_src_pll(struct mipi_dsi_host *host,
2029 struct msm_dsi_pll *src_pll)
2031 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2032 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
2033 struct clk *byte_clk_provider, *pixel_clk_provider;
2036 ret = msm_dsi_pll_get_clk_provider(src_pll,
2037 &byte_clk_provider, &pixel_clk_provider);
2039 pr_info("%s: can't get provider from pll, don't set parent\n",
2044 ret = clk_set_parent(msm_host->byte_clk_src, byte_clk_provider);
2046 pr_err("%s: can't set parent to byte_clk_src. ret=%d\n",
2051 ret = clk_set_parent(msm_host->pixel_clk_src, pixel_clk_provider);
2053 pr_err("%s: can't set parent to pixel_clk_src. ret=%d\n",
2058 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_V2) {
2059 ret = clk_set_parent(msm_host->dsi_clk_src, pixel_clk_provider);
2061 pr_err("%s: can't set parent to dsi_clk_src. ret=%d\n",
2066 ret = clk_set_parent(msm_host->esc_clk_src, byte_clk_provider);
2068 pr_err("%s: can't set parent to esc_clk_src. ret=%d\n",
2078 int msm_dsi_host_enable(struct mipi_dsi_host *host)
2080 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2082 dsi_op_mode_config(msm_host,
2083 !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO), true);
2085 /* TODO: clock should be turned off for command mode,
2086 * and only turned on before MDP START.
2087 * This part of code should be enabled once mdp driver support it.
2089 /* if (msm_panel->mode == MSM_DSI_CMD_MODE)
2090 dsi_clk_ctrl(msm_host, 0); */
2095 int msm_dsi_host_disable(struct mipi_dsi_host *host)
2097 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2099 dsi_op_mode_config(msm_host,
2100 !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO), false);
2102 /* Since we have disabled INTF, the video engine won't stop so that
2103 * the cmd engine will be blocked.
2104 * Reset to disable video engine so that we can send off cmd.
2106 dsi_sw_reset(msm_host);
2111 static void msm_dsi_sfpb_config(struct msm_dsi_host *msm_host, bool enable)
2113 enum sfpb_ahb_arb_master_port_en en;
2115 if (!msm_host->sfpb)
2118 en = enable ? SFPB_MASTER_PORT_ENABLE : SFPB_MASTER_PORT_DISABLE;
2120 regmap_update_bits(msm_host->sfpb, REG_SFPB_GPREG,
2121 SFPB_GPREG_MASTER_PORT_EN__MASK,
2122 SFPB_GPREG_MASTER_PORT_EN(en));
2125 int msm_dsi_host_power_on(struct mipi_dsi_host *host)
2127 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2128 u32 clk_pre = 0, clk_post = 0;
2131 mutex_lock(&msm_host->dev_mutex);
2132 if (msm_host->power_on) {
2133 DBG("dsi host already on");
2137 msm_dsi_sfpb_config(msm_host, true);
2139 ret = dsi_calc_clk_rate(msm_host);
2141 pr_err("%s: unable to calc clk rate, %d\n", __func__, ret);
2145 ret = dsi_host_regulator_enable(msm_host);
2147 pr_err("%s:Failed to enable vregs.ret=%d\n",
2152 ret = dsi_bus_clk_enable(msm_host);
2154 pr_err("%s: failed to enable bus clocks, %d\n", __func__, ret);
2155 goto fail_disable_reg;
2158 dsi_phy_sw_reset(msm_host);
2159 ret = msm_dsi_manager_phy_enable(msm_host->id,
2160 msm_host->byte_clk_rate * 8,
2161 msm_host->esc_clk_rate,
2162 &clk_pre, &clk_post);
2163 dsi_bus_clk_disable(msm_host);
2165 pr_err("%s: failed to enable phy, %d\n", __func__, ret);
2166 goto fail_disable_reg;
2169 ret = dsi_clk_ctrl(msm_host, 1);
2171 pr_err("%s: failed to enable clocks. ret=%d\n", __func__, ret);
2172 goto fail_disable_reg;
2175 ret = pinctrl_pm_select_default_state(&msm_host->pdev->dev);
2177 pr_err("%s: failed to set pinctrl default state, %d\n",
2179 goto fail_disable_clk;
2182 dsi_timing_setup(msm_host);
2183 dsi_sw_reset(msm_host);
2184 dsi_ctrl_config(msm_host, true, clk_pre, clk_post);
2186 if (msm_host->disp_en_gpio)
2187 gpiod_set_value(msm_host->disp_en_gpio, 1);
2189 msm_host->power_on = true;
2190 mutex_unlock(&msm_host->dev_mutex);
2195 dsi_clk_ctrl(msm_host, 0);
2197 dsi_host_regulator_disable(msm_host);
2199 mutex_unlock(&msm_host->dev_mutex);
2203 int msm_dsi_host_power_off(struct mipi_dsi_host *host)
2205 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2207 mutex_lock(&msm_host->dev_mutex);
2208 if (!msm_host->power_on) {
2209 DBG("dsi host already off");
2213 dsi_ctrl_config(msm_host, false, 0, 0);
2215 if (msm_host->disp_en_gpio)
2216 gpiod_set_value(msm_host->disp_en_gpio, 0);
2218 pinctrl_pm_select_sleep_state(&msm_host->pdev->dev);
2220 msm_dsi_manager_phy_disable(msm_host->id);
2222 dsi_clk_ctrl(msm_host, 0);
2224 dsi_host_regulator_disable(msm_host);
2226 msm_dsi_sfpb_config(msm_host, false);
2230 msm_host->power_on = false;
2233 mutex_unlock(&msm_host->dev_mutex);
2237 int msm_dsi_host_set_display_mode(struct mipi_dsi_host *host,
2238 struct drm_display_mode *mode)
2240 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2242 if (msm_host->mode) {
2243 drm_mode_destroy(msm_host->dev, msm_host->mode);
2244 msm_host->mode = NULL;
2247 msm_host->mode = drm_mode_duplicate(msm_host->dev, mode);
2248 if (IS_ERR(msm_host->mode)) {
2249 pr_err("%s: cannot duplicate mode\n", __func__);
2250 return PTR_ERR(msm_host->mode);
2256 struct drm_panel *msm_dsi_host_get_panel(struct mipi_dsi_host *host,
2257 unsigned long *panel_flags)
2259 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2260 struct drm_panel *panel;
2262 panel = of_drm_find_panel(msm_host->device_node);
2264 *panel_flags = msm_host->mode_flags;
2269 struct drm_bridge *msm_dsi_host_get_bridge(struct mipi_dsi_host *host)
2271 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2273 return of_drm_find_bridge(msm_host->device_node);