2 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/clk.h>
15 #include <linux/delay.h>
16 #include <linux/err.h>
17 #include <linux/gpio.h>
18 #include <linux/gpio/consumer.h>
19 #include <linux/interrupt.h>
20 #include <linux/of_device.h>
21 #include <linux/of_gpio.h>
22 #include <linux/of_irq.h>
23 #include <linux/pinctrl/consumer.h>
24 #include <linux/of_graph.h>
25 #include <linux/regulator/consumer.h>
26 #include <linux/spinlock.h>
27 #include <video/mipi_display.h>
33 static int dsi_get_version(const void __iomem *base, u32 *major, u32 *minor)
41 * From DSI6G(v3), addition of a 6G_HW_VERSION register at offset 0
42 * makes all other registers 4-byte shifted down.
44 * In order to identify between DSI6G(v3) and beyond, and DSIv2 and
45 * older, we read the DSI_VERSION register without any shift(offset
46 * 0x1f0). In the case of DSIv2, this hast to be a non-zero value. In
47 * the case of DSI6G, this has to be zero (the offset points to a
48 * scratch register which we never touch)
51 ver = msm_readl(base + REG_DSI_VERSION);
53 /* older dsi host, there is no register shift */
54 ver = FIELD(ver, DSI_VERSION_MAJOR);
55 if (ver <= MSM_DSI_VER_MAJOR_V2) {
65 * newer host, offset 0 has 6G_HW_VERSION, the rest of the
66 * registers are shifted down, read DSI_VERSION again with
69 ver = msm_readl(base + DSI_6G_REG_SHIFT + REG_DSI_VERSION);
70 ver = FIELD(ver, DSI_VERSION_MAJOR);
71 if (ver == MSM_DSI_VER_MAJOR_6G) {
74 *minor = msm_readl(base + REG_DSI_6G_HW_VERSION);
82 #define DSI_ERR_STATE_ACK 0x0000
83 #define DSI_ERR_STATE_TIMEOUT 0x0001
84 #define DSI_ERR_STATE_DLN0_PHY 0x0002
85 #define DSI_ERR_STATE_FIFO 0x0004
86 #define DSI_ERR_STATE_MDP_FIFO_UNDERFLOW 0x0008
87 #define DSI_ERR_STATE_INTERLEAVE_OP_CONTENTION 0x0010
88 #define DSI_ERR_STATE_PLL_UNLOCKED 0x0020
90 #define DSI_CLK_CTRL_ENABLE_CLKS \
91 (DSI_CLK_CTRL_AHBS_HCLK_ON | DSI_CLK_CTRL_AHBM_SCLK_ON | \
92 DSI_CLK_CTRL_PCLK_ON | DSI_CLK_CTRL_DSICLK_ON | \
93 DSI_CLK_CTRL_BYTECLK_ON | DSI_CLK_CTRL_ESCCLK_ON | \
94 DSI_CLK_CTRL_FORCE_ON_DYN_AHBM_HCLK)
97 struct mipi_dsi_host base;
99 struct platform_device *pdev;
100 struct drm_device *dev;
104 void __iomem *ctrl_base;
105 struct regulator_bulk_data supplies[DSI_DEV_REGULATOR_MAX];
107 struct clk *bus_clks[DSI_BUS_CLK_MAX];
109 struct clk *byte_clk;
111 struct clk *pixel_clk;
112 struct clk *byte_clk_src;
113 struct clk *pixel_clk_src;
118 /* DSI v2 specific clocks */
120 struct clk *esc_clk_src;
121 struct clk *dsi_clk_src;
125 struct gpio_desc *disp_en_gpio;
126 struct gpio_desc *te_gpio;
128 const struct msm_dsi_cfg_handler *cfg_hnd;
130 struct completion dma_comp;
131 struct completion video_comp;
132 struct mutex dev_mutex;
133 struct mutex cmd_mutex;
134 struct mutex clk_mutex;
135 spinlock_t intr_lock; /* Protect interrupt ctrl register */
138 struct work_struct err_work;
139 struct workqueue_struct *workqueue;
141 /* DSI 6G TX buffer*/
142 struct drm_gem_object *tx_gem_obj;
144 /* DSI v2 TX buffer */
146 dma_addr_t tx_buf_paddr;
152 struct drm_display_mode *mode;
154 /* connected device info */
155 struct device_node *device_node;
156 unsigned int channel;
158 enum mipi_dsi_pixel_format format;
159 unsigned long mode_flags;
161 u32 dma_cmd_ctrl_restore;
168 static u32 dsi_get_bpp(const enum mipi_dsi_pixel_format fmt)
171 case MIPI_DSI_FMT_RGB565: return 16;
172 case MIPI_DSI_FMT_RGB666_PACKED: return 18;
173 case MIPI_DSI_FMT_RGB666:
174 case MIPI_DSI_FMT_RGB888:
179 static inline u32 dsi_read(struct msm_dsi_host *msm_host, u32 reg)
181 return msm_readl(msm_host->ctrl_base + reg);
183 static inline void dsi_write(struct msm_dsi_host *msm_host, u32 reg, u32 data)
185 msm_writel(data, msm_host->ctrl_base + reg);
188 static int dsi_host_regulator_enable(struct msm_dsi_host *msm_host);
189 static void dsi_host_regulator_disable(struct msm_dsi_host *msm_host);
191 static const struct msm_dsi_cfg_handler *dsi_get_config(
192 struct msm_dsi_host *msm_host)
194 const struct msm_dsi_cfg_handler *cfg_hnd = NULL;
195 struct device *dev = &msm_host->pdev->dev;
196 struct regulator *gdsc_reg;
199 u32 major = 0, minor = 0;
201 gdsc_reg = regulator_get(dev, "gdsc");
202 if (IS_ERR(gdsc_reg)) {
203 pr_err("%s: cannot get gdsc\n", __func__);
207 ahb_clk = clk_get(dev, "iface_clk");
208 if (IS_ERR(ahb_clk)) {
209 pr_err("%s: cannot get interface clock\n", __func__);
213 ret = regulator_enable(gdsc_reg);
215 pr_err("%s: unable to enable gdsc\n", __func__);
219 ret = clk_prepare_enable(ahb_clk);
221 pr_err("%s: unable to enable ahb_clk\n", __func__);
225 ret = dsi_get_version(msm_host->ctrl_base, &major, &minor);
227 pr_err("%s: Invalid version\n", __func__);
231 cfg_hnd = msm_dsi_cfg_get(major, minor);
233 DBG("%s: Version %x:%x\n", __func__, major, minor);
236 clk_disable_unprepare(ahb_clk);
238 regulator_disable(gdsc_reg);
242 regulator_put(gdsc_reg);
247 static inline struct msm_dsi_host *to_msm_dsi_host(struct mipi_dsi_host *host)
249 return container_of(host, struct msm_dsi_host, base);
252 static void dsi_host_regulator_disable(struct msm_dsi_host *msm_host)
254 struct regulator_bulk_data *s = msm_host->supplies;
255 const struct dsi_reg_entry *regs = msm_host->cfg_hnd->cfg->reg_cfg.regs;
256 int num = msm_host->cfg_hnd->cfg->reg_cfg.num;
260 for (i = num - 1; i >= 0; i--)
261 if (regs[i].disable_load >= 0)
262 regulator_set_load(s[i].consumer,
263 regs[i].disable_load);
265 regulator_bulk_disable(num, s);
268 static int dsi_host_regulator_enable(struct msm_dsi_host *msm_host)
270 struct regulator_bulk_data *s = msm_host->supplies;
271 const struct dsi_reg_entry *regs = msm_host->cfg_hnd->cfg->reg_cfg.regs;
272 int num = msm_host->cfg_hnd->cfg->reg_cfg.num;
276 for (i = 0; i < num; i++) {
277 if (regs[i].enable_load >= 0) {
278 ret = regulator_set_load(s[i].consumer,
279 regs[i].enable_load);
281 pr_err("regulator %d set op mode failed, %d\n",
288 ret = regulator_bulk_enable(num, s);
290 pr_err("regulator enable failed, %d\n", ret);
297 for (i--; i >= 0; i--)
298 regulator_set_load(s[i].consumer, regs[i].disable_load);
302 static int dsi_regulator_init(struct msm_dsi_host *msm_host)
304 struct regulator_bulk_data *s = msm_host->supplies;
305 const struct dsi_reg_entry *regs = msm_host->cfg_hnd->cfg->reg_cfg.regs;
306 int num = msm_host->cfg_hnd->cfg->reg_cfg.num;
309 for (i = 0; i < num; i++)
310 s[i].supply = regs[i].name;
312 ret = devm_regulator_bulk_get(&msm_host->pdev->dev, num, s);
314 pr_err("%s: failed to init regulator, ret=%d\n",
319 for (i = 0; i < num; i++) {
320 if (regulator_can_change_voltage(s[i].consumer)) {
321 ret = regulator_set_voltage(s[i].consumer,
322 regs[i].min_voltage, regs[i].max_voltage);
324 pr_err("regulator %d set voltage failed, %d\n",
334 static int dsi_clk_init(struct msm_dsi_host *msm_host)
336 struct device *dev = &msm_host->pdev->dev;
337 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
338 const struct msm_dsi_config *cfg = cfg_hnd->cfg;
342 for (i = 0; i < cfg->num_bus_clks; i++) {
343 msm_host->bus_clks[i] = devm_clk_get(dev,
344 cfg->bus_clk_names[i]);
345 if (IS_ERR(msm_host->bus_clks[i])) {
346 ret = PTR_ERR(msm_host->bus_clks[i]);
347 pr_err("%s: Unable to get %s, ret = %d\n",
348 __func__, cfg->bus_clk_names[i], ret);
353 /* get link and source clocks */
354 msm_host->byte_clk = devm_clk_get(dev, "byte_clk");
355 if (IS_ERR(msm_host->byte_clk)) {
356 ret = PTR_ERR(msm_host->byte_clk);
357 pr_err("%s: can't find dsi_byte_clk. ret=%d\n",
359 msm_host->byte_clk = NULL;
363 msm_host->pixel_clk = devm_clk_get(dev, "pixel_clk");
364 if (IS_ERR(msm_host->pixel_clk)) {
365 ret = PTR_ERR(msm_host->pixel_clk);
366 pr_err("%s: can't find dsi_pixel_clk. ret=%d\n",
368 msm_host->pixel_clk = NULL;
372 msm_host->esc_clk = devm_clk_get(dev, "core_clk");
373 if (IS_ERR(msm_host->esc_clk)) {
374 ret = PTR_ERR(msm_host->esc_clk);
375 pr_err("%s: can't find dsi_esc_clk. ret=%d\n",
377 msm_host->esc_clk = NULL;
381 msm_host->byte_clk_src = clk_get_parent(msm_host->byte_clk);
382 if (!msm_host->byte_clk_src) {
384 pr_err("%s: can't find byte_clk_src. ret=%d\n", __func__, ret);
388 msm_host->pixel_clk_src = clk_get_parent(msm_host->pixel_clk);
389 if (!msm_host->pixel_clk_src) {
391 pr_err("%s: can't find pixel_clk_src. ret=%d\n", __func__, ret);
395 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_V2) {
396 msm_host->src_clk = devm_clk_get(dev, "src_clk");
397 if (IS_ERR(msm_host->src_clk)) {
398 ret = PTR_ERR(msm_host->src_clk);
399 pr_err("%s: can't find dsi_src_clk. ret=%d\n",
401 msm_host->src_clk = NULL;
405 msm_host->esc_clk_src = clk_get_parent(msm_host->esc_clk);
406 if (!msm_host->esc_clk_src) {
408 pr_err("%s: can't get esc_clk_src. ret=%d\n",
413 msm_host->dsi_clk_src = clk_get_parent(msm_host->src_clk);
414 if (!msm_host->dsi_clk_src) {
416 pr_err("%s: can't get dsi_clk_src. ret=%d\n",
424 static int dsi_bus_clk_enable(struct msm_dsi_host *msm_host)
426 const struct msm_dsi_config *cfg = msm_host->cfg_hnd->cfg;
429 DBG("id=%d", msm_host->id);
431 for (i = 0; i < cfg->num_bus_clks; i++) {
432 ret = clk_prepare_enable(msm_host->bus_clks[i]);
434 pr_err("%s: failed to enable bus clock %d ret %d\n",
443 clk_disable_unprepare(msm_host->bus_clks[i]);
448 static void dsi_bus_clk_disable(struct msm_dsi_host *msm_host)
450 const struct msm_dsi_config *cfg = msm_host->cfg_hnd->cfg;
455 for (i = cfg->num_bus_clks - 1; i >= 0; i--)
456 clk_disable_unprepare(msm_host->bus_clks[i]);
459 static int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host)
463 DBG("Set clk rates: pclk=%d, byteclk=%d",
464 msm_host->mode->clock, msm_host->byte_clk_rate);
466 ret = clk_set_rate(msm_host->byte_clk, msm_host->byte_clk_rate);
468 pr_err("%s: Failed to set rate byte clk, %d\n", __func__, ret);
472 ret = clk_set_rate(msm_host->pixel_clk, msm_host->mode->clock * 1000);
474 pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret);
478 ret = clk_prepare_enable(msm_host->esc_clk);
480 pr_err("%s: Failed to enable dsi esc clk\n", __func__);
484 ret = clk_prepare_enable(msm_host->byte_clk);
486 pr_err("%s: Failed to enable dsi byte clk\n", __func__);
490 ret = clk_prepare_enable(msm_host->pixel_clk);
492 pr_err("%s: Failed to enable dsi pixel clk\n", __func__);
499 clk_disable_unprepare(msm_host->byte_clk);
501 clk_disable_unprepare(msm_host->esc_clk);
506 static int dsi_link_clk_enable_v2(struct msm_dsi_host *msm_host)
510 DBG("Set clk rates: pclk=%d, byteclk=%d, esc_clk=%d, dsi_src_clk=%d",
511 msm_host->mode->clock, msm_host->byte_clk_rate,
512 msm_host->esc_clk_rate, msm_host->src_clk_rate);
514 ret = clk_set_rate(msm_host->byte_clk, msm_host->byte_clk_rate);
516 pr_err("%s: Failed to set rate byte clk, %d\n", __func__, ret);
520 ret = clk_set_rate(msm_host->esc_clk, msm_host->esc_clk_rate);
522 pr_err("%s: Failed to set rate esc clk, %d\n", __func__, ret);
526 ret = clk_set_rate(msm_host->src_clk, msm_host->src_clk_rate);
528 pr_err("%s: Failed to set rate src clk, %d\n", __func__, ret);
532 ret = clk_set_rate(msm_host->pixel_clk, msm_host->mode->clock * 1000);
534 pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret);
538 ret = clk_prepare_enable(msm_host->byte_clk);
540 pr_err("%s: Failed to enable dsi byte clk\n", __func__);
544 ret = clk_prepare_enable(msm_host->esc_clk);
546 pr_err("%s: Failed to enable dsi esc clk\n", __func__);
550 ret = clk_prepare_enable(msm_host->src_clk);
552 pr_err("%s: Failed to enable dsi src clk\n", __func__);
556 ret = clk_prepare_enable(msm_host->pixel_clk);
558 pr_err("%s: Failed to enable dsi pixel clk\n", __func__);
565 clk_disable_unprepare(msm_host->src_clk);
567 clk_disable_unprepare(msm_host->esc_clk);
569 clk_disable_unprepare(msm_host->byte_clk);
574 static int dsi_link_clk_enable(struct msm_dsi_host *msm_host)
576 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
578 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_6G)
579 return dsi_link_clk_enable_6g(msm_host);
581 return dsi_link_clk_enable_v2(msm_host);
584 static void dsi_link_clk_disable(struct msm_dsi_host *msm_host)
586 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
588 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) {
589 clk_disable_unprepare(msm_host->esc_clk);
590 clk_disable_unprepare(msm_host->pixel_clk);
591 clk_disable_unprepare(msm_host->byte_clk);
593 clk_disable_unprepare(msm_host->pixel_clk);
594 clk_disable_unprepare(msm_host->src_clk);
595 clk_disable_unprepare(msm_host->esc_clk);
596 clk_disable_unprepare(msm_host->byte_clk);
600 static int dsi_clk_ctrl(struct msm_dsi_host *msm_host, bool enable)
604 mutex_lock(&msm_host->clk_mutex);
606 ret = dsi_bus_clk_enable(msm_host);
608 pr_err("%s: Can not enable bus clk, %d\n",
612 ret = dsi_link_clk_enable(msm_host);
614 pr_err("%s: Can not enable link clk, %d\n",
616 dsi_bus_clk_disable(msm_host);
620 dsi_link_clk_disable(msm_host);
621 dsi_bus_clk_disable(msm_host);
625 mutex_unlock(&msm_host->clk_mutex);
629 static int dsi_calc_clk_rate(struct msm_dsi_host *msm_host)
631 struct drm_display_mode *mode = msm_host->mode;
632 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
633 u8 lanes = msm_host->lanes;
634 u32 bpp = dsi_get_bpp(msm_host->format);
638 pr_err("%s: mode not set\n", __func__);
642 pclk_rate = mode->clock * 1000;
644 msm_host->byte_clk_rate = (pclk_rate * bpp) / (8 * lanes);
646 pr_err("%s: forcing mdss_dsi lanes to 1\n", __func__);
647 msm_host->byte_clk_rate = (pclk_rate * bpp) / 8;
650 DBG("pclk=%d, bclk=%d", pclk_rate, msm_host->byte_clk_rate);
652 msm_host->esc_clk_rate = clk_get_rate(msm_host->esc_clk);
654 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_V2) {
655 unsigned int esc_mhz, esc_div;
656 unsigned long byte_mhz;
658 msm_host->src_clk_rate = (pclk_rate * bpp) / 8;
661 * esc clock is byte clock followed by a 4 bit divider,
662 * we need to find an escape clock frequency within the
663 * mipi DSI spec range within the maximum divider limit
664 * We iterate here between an escape clock frequencey
665 * between 20 Mhz to 5 Mhz and pick up the first one
666 * that can be supported by our divider
669 byte_mhz = msm_host->byte_clk_rate / 1000000;
671 for (esc_mhz = 20; esc_mhz >= 5; esc_mhz--) {
672 esc_div = DIV_ROUND_UP(byte_mhz, esc_mhz);
675 * TODO: Ideally, we shouldn't know what sort of divider
676 * is available in mmss_cc, we're just assuming that
677 * it'll always be a 4 bit divider. Need to come up with
680 if (esc_div >= 1 && esc_div <= 16)
687 msm_host->esc_clk_rate = msm_host->byte_clk_rate / esc_div;
689 DBG("esc=%d, src=%d", msm_host->esc_clk_rate,
690 msm_host->src_clk_rate);
696 static void dsi_phy_sw_reset(struct msm_dsi_host *msm_host)
699 dsi_write(msm_host, REG_DSI_PHY_RESET, DSI_PHY_RESET_RESET);
700 /* Make sure fully reset */
703 dsi_write(msm_host, REG_DSI_PHY_RESET, 0);
707 static void dsi_intr_ctrl(struct msm_dsi_host *msm_host, u32 mask, int enable)
712 spin_lock_irqsave(&msm_host->intr_lock, flags);
713 intr = dsi_read(msm_host, REG_DSI_INTR_CTRL);
720 DBG("intr=%x enable=%d", intr, enable);
722 dsi_write(msm_host, REG_DSI_INTR_CTRL, intr);
723 spin_unlock_irqrestore(&msm_host->intr_lock, flags);
726 static inline enum dsi_traffic_mode dsi_get_traffic_mode(const u32 mode_flags)
728 if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
730 else if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
731 return NON_BURST_SYNCH_PULSE;
733 return NON_BURST_SYNCH_EVENT;
736 static inline enum dsi_vid_dst_format dsi_get_vid_fmt(
737 const enum mipi_dsi_pixel_format mipi_fmt)
740 case MIPI_DSI_FMT_RGB888: return VID_DST_FORMAT_RGB888;
741 case MIPI_DSI_FMT_RGB666: return VID_DST_FORMAT_RGB666_LOOSE;
742 case MIPI_DSI_FMT_RGB666_PACKED: return VID_DST_FORMAT_RGB666;
743 case MIPI_DSI_FMT_RGB565: return VID_DST_FORMAT_RGB565;
744 default: return VID_DST_FORMAT_RGB888;
748 static inline enum dsi_cmd_dst_format dsi_get_cmd_fmt(
749 const enum mipi_dsi_pixel_format mipi_fmt)
752 case MIPI_DSI_FMT_RGB888: return CMD_DST_FORMAT_RGB888;
753 case MIPI_DSI_FMT_RGB666_PACKED:
754 case MIPI_DSI_FMT_RGB666: return VID_DST_FORMAT_RGB666;
755 case MIPI_DSI_FMT_RGB565: return CMD_DST_FORMAT_RGB565;
756 default: return CMD_DST_FORMAT_RGB888;
760 static void dsi_ctrl_config(struct msm_dsi_host *msm_host, bool enable,
761 u32 clk_pre, u32 clk_post)
763 u32 flags = msm_host->mode_flags;
764 enum mipi_dsi_pixel_format mipi_fmt = msm_host->format;
765 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
769 dsi_write(msm_host, REG_DSI_CTRL, 0);
773 if (flags & MIPI_DSI_MODE_VIDEO) {
774 if (flags & MIPI_DSI_MODE_VIDEO_HSE)
775 data |= DSI_VID_CFG0_PULSE_MODE_HSA_HE;
776 if (flags & MIPI_DSI_MODE_VIDEO_HFP)
777 data |= DSI_VID_CFG0_HFP_POWER_STOP;
778 if (flags & MIPI_DSI_MODE_VIDEO_HBP)
779 data |= DSI_VID_CFG0_HBP_POWER_STOP;
780 if (flags & MIPI_DSI_MODE_VIDEO_HSA)
781 data |= DSI_VID_CFG0_HSA_POWER_STOP;
782 /* Always set low power stop mode for BLLP
783 * to let command engine send packets
785 data |= DSI_VID_CFG0_EOF_BLLP_POWER_STOP |
786 DSI_VID_CFG0_BLLP_POWER_STOP;
787 data |= DSI_VID_CFG0_TRAFFIC_MODE(dsi_get_traffic_mode(flags));
788 data |= DSI_VID_CFG0_DST_FORMAT(dsi_get_vid_fmt(mipi_fmt));
789 data |= DSI_VID_CFG0_VIRT_CHANNEL(msm_host->channel);
790 dsi_write(msm_host, REG_DSI_VID_CFG0, data);
792 /* Do not swap RGB colors */
793 data = DSI_VID_CFG1_RGB_SWAP(SWAP_RGB);
794 dsi_write(msm_host, REG_DSI_VID_CFG1, 0);
796 /* Do not swap RGB colors */
797 data = DSI_CMD_CFG0_RGB_SWAP(SWAP_RGB);
798 data |= DSI_CMD_CFG0_DST_FORMAT(dsi_get_cmd_fmt(mipi_fmt));
799 dsi_write(msm_host, REG_DSI_CMD_CFG0, data);
801 data = DSI_CMD_CFG1_WR_MEM_START(MIPI_DCS_WRITE_MEMORY_START) |
802 DSI_CMD_CFG1_WR_MEM_CONTINUE(
803 MIPI_DCS_WRITE_MEMORY_CONTINUE);
804 /* Always insert DCS command */
805 data |= DSI_CMD_CFG1_INSERT_DCS_COMMAND;
806 dsi_write(msm_host, REG_DSI_CMD_CFG1, data);
809 dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL,
810 DSI_CMD_DMA_CTRL_FROM_FRAME_BUFFER |
811 DSI_CMD_DMA_CTRL_LOW_POWER);
814 /* Always assume dedicated TE pin */
815 data |= DSI_TRIG_CTRL_TE;
816 data |= DSI_TRIG_CTRL_MDP_TRIGGER(TRIGGER_NONE);
817 data |= DSI_TRIG_CTRL_DMA_TRIGGER(TRIGGER_SW);
818 data |= DSI_TRIG_CTRL_STREAM(msm_host->channel);
819 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) &&
820 (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_2))
821 data |= DSI_TRIG_CTRL_BLOCK_DMA_WITHIN_FRAME;
822 dsi_write(msm_host, REG_DSI_TRIG_CTRL, data);
824 data = DSI_CLKOUT_TIMING_CTRL_T_CLK_POST(clk_post) |
825 DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE(clk_pre);
826 dsi_write(msm_host, REG_DSI_CLKOUT_TIMING_CTRL, data);
829 if (!(flags & MIPI_DSI_MODE_EOT_PACKET))
830 data |= DSI_EOT_PACKET_CTRL_TX_EOT_APPEND;
831 dsi_write(msm_host, REG_DSI_EOT_PACKET_CTRL, data);
833 /* allow only ack-err-status to generate interrupt */
834 dsi_write(msm_host, REG_DSI_ERR_INT_MASK0, 0x13ff3fe0);
836 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 1);
838 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS);
840 data = DSI_CTRL_CLK_EN;
842 DBG("lane number=%d", msm_host->lanes);
843 if (msm_host->lanes == 2) {
844 data |= DSI_CTRL_LANE1 | DSI_CTRL_LANE2;
845 /* swap lanes for 2-lane panel for better performance */
846 dsi_write(msm_host, REG_DSI_LANE_SWAP_CTRL,
847 DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(LANE_SWAP_1230));
849 /* Take 4 lanes as default */
850 data |= DSI_CTRL_LANE0 | DSI_CTRL_LANE1 | DSI_CTRL_LANE2 |
852 /* Do not swap lanes for 4-lane panel */
853 dsi_write(msm_host, REG_DSI_LANE_SWAP_CTRL,
854 DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(LANE_SWAP_0123));
857 if (!(flags & MIPI_DSI_CLOCK_NON_CONTINUOUS))
858 dsi_write(msm_host, REG_DSI_LANE_CTRL,
859 DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST);
861 data |= DSI_CTRL_ENABLE;
863 dsi_write(msm_host, REG_DSI_CTRL, data);
866 static void dsi_timing_setup(struct msm_dsi_host *msm_host)
868 struct drm_display_mode *mode = msm_host->mode;
869 u32 hs_start = 0, vs_start = 0; /* take sync start as 0 */
870 u32 h_total = mode->htotal;
871 u32 v_total = mode->vtotal;
872 u32 hs_end = mode->hsync_end - mode->hsync_start;
873 u32 vs_end = mode->vsync_end - mode->vsync_start;
874 u32 ha_start = h_total - mode->hsync_start;
875 u32 ha_end = ha_start + mode->hdisplay;
876 u32 va_start = v_total - mode->vsync_start;
877 u32 va_end = va_start + mode->vdisplay;
882 if (msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) {
883 dsi_write(msm_host, REG_DSI_ACTIVE_H,
884 DSI_ACTIVE_H_START(ha_start) |
885 DSI_ACTIVE_H_END(ha_end));
886 dsi_write(msm_host, REG_DSI_ACTIVE_V,
887 DSI_ACTIVE_V_START(va_start) |
888 DSI_ACTIVE_V_END(va_end));
889 dsi_write(msm_host, REG_DSI_TOTAL,
890 DSI_TOTAL_H_TOTAL(h_total - 1) |
891 DSI_TOTAL_V_TOTAL(v_total - 1));
893 dsi_write(msm_host, REG_DSI_ACTIVE_HSYNC,
894 DSI_ACTIVE_HSYNC_START(hs_start) |
895 DSI_ACTIVE_HSYNC_END(hs_end));
896 dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_HPOS, 0);
897 dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_VPOS,
898 DSI_ACTIVE_VSYNC_VPOS_START(vs_start) |
899 DSI_ACTIVE_VSYNC_VPOS_END(vs_end));
900 } else { /* command mode */
901 /* image data and 1 byte write_memory_start cmd */
902 wc = mode->hdisplay * dsi_get_bpp(msm_host->format) / 8 + 1;
904 dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM_CTRL,
905 DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT(wc) |
906 DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL(
908 DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE(
909 MIPI_DSI_DCS_LONG_WRITE));
911 dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM_TOTAL,
912 DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL(mode->hdisplay) |
913 DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL(mode->vdisplay));
917 static void dsi_sw_reset(struct msm_dsi_host *msm_host)
919 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS);
920 wmb(); /* clocks need to be enabled before reset */
922 dsi_write(msm_host, REG_DSI_RESET, 1);
923 wmb(); /* make sure reset happen */
924 dsi_write(msm_host, REG_DSI_RESET, 0);
927 static void dsi_op_mode_config(struct msm_dsi_host *msm_host,
928 bool video_mode, bool enable)
932 dsi_ctrl = dsi_read(msm_host, REG_DSI_CTRL);
935 dsi_ctrl &= ~(DSI_CTRL_ENABLE | DSI_CTRL_VID_MODE_EN |
936 DSI_CTRL_CMD_MODE_EN);
937 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_MDP_DONE |
938 DSI_IRQ_MASK_VIDEO_DONE, 0);
941 dsi_ctrl |= DSI_CTRL_VID_MODE_EN;
942 } else { /* command mode */
943 dsi_ctrl |= DSI_CTRL_CMD_MODE_EN;
944 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_MDP_DONE, 1);
946 dsi_ctrl |= DSI_CTRL_ENABLE;
949 dsi_write(msm_host, REG_DSI_CTRL, dsi_ctrl);
952 static void dsi_set_tx_power_mode(int mode, struct msm_dsi_host *msm_host)
956 data = dsi_read(msm_host, REG_DSI_CMD_DMA_CTRL);
959 data &= ~DSI_CMD_DMA_CTRL_LOW_POWER;
961 data |= DSI_CMD_DMA_CTRL_LOW_POWER;
963 dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL, data);
966 static void dsi_wait4video_done(struct msm_dsi_host *msm_host)
968 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 1);
970 reinit_completion(&msm_host->video_comp);
972 wait_for_completion_timeout(&msm_host->video_comp,
973 msecs_to_jiffies(70));
975 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 0);
978 static void dsi_wait4video_eng_busy(struct msm_dsi_host *msm_host)
980 if (!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO))
983 if (msm_host->power_on) {
984 dsi_wait4video_done(msm_host);
985 /* delay 4 ms to skip BLLP */
986 usleep_range(2000, 4000);
991 static int dsi_tx_buf_alloc(struct msm_dsi_host *msm_host, int size)
993 struct drm_device *dev = msm_host->dev;
994 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
998 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) {
999 mutex_lock(&dev->struct_mutex);
1000 msm_host->tx_gem_obj = msm_gem_new(dev, size, MSM_BO_UNCACHED);
1001 if (IS_ERR(msm_host->tx_gem_obj)) {
1002 ret = PTR_ERR(msm_host->tx_gem_obj);
1003 pr_err("%s: failed to allocate gem, %d\n",
1005 msm_host->tx_gem_obj = NULL;
1006 mutex_unlock(&dev->struct_mutex);
1010 ret = msm_gem_get_iova_locked(msm_host->tx_gem_obj, 0, &iova);
1012 pr_err("%s: failed to get iova, %d\n", __func__, ret);
1015 mutex_unlock(&dev->struct_mutex);
1018 pr_err("%s: buf NOT 8 bytes aligned\n", __func__);
1022 msm_host->tx_size = msm_host->tx_gem_obj->size;
1024 msm_host->tx_buf = dma_alloc_coherent(dev->dev, size,
1025 &msm_host->tx_buf_paddr, GFP_KERNEL);
1026 if (!msm_host->tx_buf) {
1028 pr_err("%s: failed to allocate tx buf, %d\n",
1033 msm_host->tx_size = size;
1039 static void dsi_tx_buf_free(struct msm_dsi_host *msm_host)
1041 struct drm_device *dev = msm_host->dev;
1043 if (msm_host->tx_gem_obj) {
1044 msm_gem_put_iova(msm_host->tx_gem_obj, 0);
1045 mutex_lock(&dev->struct_mutex);
1046 msm_gem_free_object(msm_host->tx_gem_obj);
1047 msm_host->tx_gem_obj = NULL;
1048 mutex_unlock(&dev->struct_mutex);
1051 if (msm_host->tx_buf)
1052 dma_free_coherent(dev->dev, msm_host->tx_size, msm_host->tx_buf,
1053 msm_host->tx_buf_paddr);
1057 * prepare cmd buffer to be txed
1059 static int dsi_cmd_dma_add(struct msm_dsi_host *msm_host,
1060 const struct mipi_dsi_msg *msg)
1062 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
1063 struct mipi_dsi_packet packet;
1068 ret = mipi_dsi_create_packet(&packet, msg);
1070 pr_err("%s: create packet failed, %d\n", __func__, ret);
1073 len = (packet.size + 3) & (~0x3);
1075 if (len > msm_host->tx_size) {
1076 pr_err("%s: packet size is too big\n", __func__);
1080 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) {
1081 data = msm_gem_vaddr(msm_host->tx_gem_obj);
1083 ret = PTR_ERR(data);
1084 pr_err("%s: get vaddr failed, %d\n", __func__, ret);
1088 data = msm_host->tx_buf;
1091 /* MSM specific command format in memory */
1092 data[0] = packet.header[1];
1093 data[1] = packet.header[2];
1094 data[2] = packet.header[0];
1095 data[3] = BIT(7); /* Last packet */
1096 if (mipi_dsi_packet_format_is_long(msg->type))
1098 if (msg->rx_buf && msg->rx_len)
1102 if (packet.payload && packet.payload_length)
1103 memcpy(data + 4, packet.payload, packet.payload_length);
1105 /* Append 0xff to the end */
1106 if (packet.size < len)
1107 memset(data + packet.size, 0xff, len - packet.size);
1113 * dsi_short_read1_resp: 1 parameter
1115 static int dsi_short_read1_resp(u8 *buf, const struct mipi_dsi_msg *msg)
1117 u8 *data = msg->rx_buf;
1118 if (data && (msg->rx_len >= 1)) {
1119 *data = buf[1]; /* strip out dcs type */
1122 pr_err("%s: read data does not match with rx_buf len %zu\n",
1123 __func__, msg->rx_len);
1129 * dsi_short_read2_resp: 2 parameter
1131 static int dsi_short_read2_resp(u8 *buf, const struct mipi_dsi_msg *msg)
1133 u8 *data = msg->rx_buf;
1134 if (data && (msg->rx_len >= 2)) {
1135 data[0] = buf[1]; /* strip out dcs type */
1139 pr_err("%s: read data does not match with rx_buf len %zu\n",
1140 __func__, msg->rx_len);
1145 static int dsi_long_read_resp(u8 *buf, const struct mipi_dsi_msg *msg)
1147 /* strip out 4 byte dcs header */
1148 if (msg->rx_buf && msg->rx_len)
1149 memcpy(msg->rx_buf, buf + 4, msg->rx_len);
1154 static int dsi_cmd_dma_tx(struct msm_dsi_host *msm_host, int len)
1156 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
1161 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) {
1162 ret = msm_gem_get_iova(msm_host->tx_gem_obj, 0, &dma_base);
1164 pr_err("%s: failed to get iova: %d\n", __func__, ret);
1168 dma_base = msm_host->tx_buf_paddr;
1171 reinit_completion(&msm_host->dma_comp);
1173 dsi_wait4video_eng_busy(msm_host);
1175 triggered = msm_dsi_manager_cmd_xfer_trigger(
1176 msm_host->id, dma_base, len);
1178 ret = wait_for_completion_timeout(&msm_host->dma_comp,
1179 msecs_to_jiffies(200));
1191 static int dsi_cmd_dma_rx(struct msm_dsi_host *msm_host,
1192 u8 *buf, int rx_byte, int pkt_size)
1194 u32 *lp, *temp, data;
1198 int repeated_bytes = 0;
1199 int buf_offset = buf - msm_host->rx_buf;
1203 cnt = (rx_byte + 3) >> 2;
1205 cnt = 4; /* 4 x 32 bits registers only */
1210 read_cnt = pkt_size + 6;
1213 * In case of multiple reads from the panel, after the first read, there
1214 * is possibility that there are some bytes in the payload repeating in
1215 * the RDBK_DATA registers. Since we read all the parameters from the
1216 * panel right from the first byte for every pass. We need to skip the
1217 * repeating bytes and then append the new parameters to the rx buffer.
1219 if (read_cnt > 16) {
1221 /* Any data more than 16 bytes will be shifted out.
1222 * The temp read buffer should already contain these bytes.
1223 * The remaining bytes in read buffer are the repeated bytes.
1225 bytes_shifted = read_cnt - 16;
1226 repeated_bytes = buf_offset - bytes_shifted;
1229 for (i = cnt - 1; i >= 0; i--) {
1230 data = dsi_read(msm_host, REG_DSI_RDBK_DATA(i));
1231 *temp++ = ntohl(data); /* to host byte order */
1232 DBG("data = 0x%x and ntohl(data) = 0x%x", data, ntohl(data));
1235 for (i = repeated_bytes; i < 16; i++)
1241 static int dsi_cmds2buf_tx(struct msm_dsi_host *msm_host,
1242 const struct mipi_dsi_msg *msg)
1245 int bllp_len = msm_host->mode->hdisplay *
1246 dsi_get_bpp(msm_host->format) / 8;
1248 len = dsi_cmd_dma_add(msm_host, msg);
1250 pr_err("%s: failed to add cmd type = 0x%x\n",
1251 __func__, msg->type);
1255 /* for video mode, do not send cmds more than
1256 * one pixel line, since it only transmit it
1259 /* TODO: if the command is sent in LP mode, the bit rate is only
1260 * half of esc clk rate. In this case, if the video is already
1261 * actively streaming, we need to check more carefully if the
1262 * command can be fit into one BLLP.
1264 if ((msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) && (len > bllp_len)) {
1265 pr_err("%s: cmd cannot fit into BLLP period, len=%d\n",
1270 ret = dsi_cmd_dma_tx(msm_host, len);
1272 pr_err("%s: cmd dma tx failed, type=0x%x, data0=0x%x, len=%d\n",
1273 __func__, msg->type, (*(u8 *)(msg->tx_buf)), len);
1280 static void dsi_sw_reset_restore(struct msm_dsi_host *msm_host)
1284 data0 = dsi_read(msm_host, REG_DSI_CTRL);
1286 data1 &= ~DSI_CTRL_ENABLE;
1287 dsi_write(msm_host, REG_DSI_CTRL, data1);
1289 * dsi controller need to be disabled before
1294 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS);
1295 wmb(); /* make sure clocks enabled */
1297 /* dsi controller can only be reset while clocks are running */
1298 dsi_write(msm_host, REG_DSI_RESET, 1);
1299 wmb(); /* make sure reset happen */
1300 dsi_write(msm_host, REG_DSI_RESET, 0);
1301 wmb(); /* controller out of reset */
1302 dsi_write(msm_host, REG_DSI_CTRL, data0);
1303 wmb(); /* make sure dsi controller enabled again */
1306 static void dsi_err_worker(struct work_struct *work)
1308 struct msm_dsi_host *msm_host =
1309 container_of(work, struct msm_dsi_host, err_work);
1310 u32 status = msm_host->err_work_state;
1312 pr_err_ratelimited("%s: status=%x\n", __func__, status);
1313 if (status & DSI_ERR_STATE_MDP_FIFO_UNDERFLOW)
1314 dsi_sw_reset_restore(msm_host);
1316 /* It is safe to clear here because error irq is disabled. */
1317 msm_host->err_work_state = 0;
1319 /* enable dsi error interrupt */
1320 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 1);
1323 static void dsi_ack_err_status(struct msm_dsi_host *msm_host)
1327 status = dsi_read(msm_host, REG_DSI_ACK_ERR_STATUS);
1330 dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, status);
1331 /* Writing of an extra 0 needed to clear error bits */
1332 dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, 0);
1333 msm_host->err_work_state |= DSI_ERR_STATE_ACK;
1337 static void dsi_timeout_status(struct msm_dsi_host *msm_host)
1341 status = dsi_read(msm_host, REG_DSI_TIMEOUT_STATUS);
1344 dsi_write(msm_host, REG_DSI_TIMEOUT_STATUS, status);
1345 msm_host->err_work_state |= DSI_ERR_STATE_TIMEOUT;
1349 static void dsi_dln0_phy_err(struct msm_dsi_host *msm_host)
1353 status = dsi_read(msm_host, REG_DSI_DLN0_PHY_ERR);
1355 if (status & (DSI_DLN0_PHY_ERR_DLN0_ERR_ESC |
1356 DSI_DLN0_PHY_ERR_DLN0_ERR_SYNC_ESC |
1357 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTROL |
1358 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP0 |
1359 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP1)) {
1360 dsi_write(msm_host, REG_DSI_DLN0_PHY_ERR, status);
1361 msm_host->err_work_state |= DSI_ERR_STATE_DLN0_PHY;
1365 static void dsi_fifo_status(struct msm_dsi_host *msm_host)
1369 status = dsi_read(msm_host, REG_DSI_FIFO_STATUS);
1371 /* fifo underflow, overflow */
1373 dsi_write(msm_host, REG_DSI_FIFO_STATUS, status);
1374 msm_host->err_work_state |= DSI_ERR_STATE_FIFO;
1375 if (status & DSI_FIFO_STATUS_CMD_MDP_FIFO_UNDERFLOW)
1376 msm_host->err_work_state |=
1377 DSI_ERR_STATE_MDP_FIFO_UNDERFLOW;
1381 static void dsi_status(struct msm_dsi_host *msm_host)
1385 status = dsi_read(msm_host, REG_DSI_STATUS0);
1387 if (status & DSI_STATUS0_INTERLEAVE_OP_CONTENTION) {
1388 dsi_write(msm_host, REG_DSI_STATUS0, status);
1389 msm_host->err_work_state |=
1390 DSI_ERR_STATE_INTERLEAVE_OP_CONTENTION;
1394 static void dsi_clk_status(struct msm_dsi_host *msm_host)
1398 status = dsi_read(msm_host, REG_DSI_CLK_STATUS);
1400 if (status & DSI_CLK_STATUS_PLL_UNLOCKED) {
1401 dsi_write(msm_host, REG_DSI_CLK_STATUS, status);
1402 msm_host->err_work_state |= DSI_ERR_STATE_PLL_UNLOCKED;
1406 static void dsi_error(struct msm_dsi_host *msm_host)
1408 /* disable dsi error interrupt */
1409 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 0);
1411 dsi_clk_status(msm_host);
1412 dsi_fifo_status(msm_host);
1413 dsi_ack_err_status(msm_host);
1414 dsi_timeout_status(msm_host);
1415 dsi_status(msm_host);
1416 dsi_dln0_phy_err(msm_host);
1418 queue_work(msm_host->workqueue, &msm_host->err_work);
1421 static irqreturn_t dsi_host_irq(int irq, void *ptr)
1423 struct msm_dsi_host *msm_host = ptr;
1425 unsigned long flags;
1427 if (!msm_host->ctrl_base)
1430 spin_lock_irqsave(&msm_host->intr_lock, flags);
1431 isr = dsi_read(msm_host, REG_DSI_INTR_CTRL);
1432 dsi_write(msm_host, REG_DSI_INTR_CTRL, isr);
1433 spin_unlock_irqrestore(&msm_host->intr_lock, flags);
1435 DBG("isr=0x%x, id=%d", isr, msm_host->id);
1437 if (isr & DSI_IRQ_ERROR)
1438 dsi_error(msm_host);
1440 if (isr & DSI_IRQ_VIDEO_DONE)
1441 complete(&msm_host->video_comp);
1443 if (isr & DSI_IRQ_CMD_DMA_DONE)
1444 complete(&msm_host->dma_comp);
1449 static int dsi_host_init_panel_gpios(struct msm_dsi_host *msm_host,
1450 struct device *panel_device)
1452 msm_host->disp_en_gpio = devm_gpiod_get_optional(panel_device,
1455 if (IS_ERR(msm_host->disp_en_gpio)) {
1456 DBG("cannot get disp-enable-gpios %ld",
1457 PTR_ERR(msm_host->disp_en_gpio));
1458 return PTR_ERR(msm_host->disp_en_gpio);
1461 msm_host->te_gpio = devm_gpiod_get_optional(panel_device, "disp-te",
1463 if (IS_ERR(msm_host->te_gpio)) {
1464 DBG("cannot get disp-te-gpios %ld", PTR_ERR(msm_host->te_gpio));
1465 return PTR_ERR(msm_host->te_gpio);
1471 static int dsi_host_attach(struct mipi_dsi_host *host,
1472 struct mipi_dsi_device *dsi)
1474 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1477 msm_host->channel = dsi->channel;
1478 msm_host->lanes = dsi->lanes;
1479 msm_host->format = dsi->format;
1480 msm_host->mode_flags = dsi->mode_flags;
1482 WARN_ON(dsi->dev.of_node != msm_host->device_node);
1484 /* Some gpios defined in panel DT need to be controlled by host */
1485 ret = dsi_host_init_panel_gpios(msm_host, &dsi->dev);
1489 DBG("id=%d", msm_host->id);
1491 drm_helper_hpd_irq_event(msm_host->dev);
1496 static int dsi_host_detach(struct mipi_dsi_host *host,
1497 struct mipi_dsi_device *dsi)
1499 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1501 msm_host->device_node = NULL;
1503 DBG("id=%d", msm_host->id);
1505 drm_helper_hpd_irq_event(msm_host->dev);
1510 static ssize_t dsi_host_transfer(struct mipi_dsi_host *host,
1511 const struct mipi_dsi_msg *msg)
1513 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1516 if (!msg || !msm_host->power_on)
1519 mutex_lock(&msm_host->cmd_mutex);
1520 ret = msm_dsi_manager_cmd_xfer(msm_host->id, msg);
1521 mutex_unlock(&msm_host->cmd_mutex);
1526 static struct mipi_dsi_host_ops dsi_host_ops = {
1527 .attach = dsi_host_attach,
1528 .detach = dsi_host_detach,
1529 .transfer = dsi_host_transfer,
1532 static int dsi_host_parse_dt(struct msm_dsi_host *msm_host)
1534 struct device *dev = &msm_host->pdev->dev;
1535 struct device_node *np = dev->of_node;
1536 struct device_node *endpoint, *device_node;
1539 ret = of_property_read_u32(np, "qcom,dsi-host-index", &msm_host->id);
1541 dev_err(dev, "%s: host index not specified, ret=%d\n",
1547 * Get the first endpoint node. In our case, dsi has one output port
1548 * to which the panel is connected. Don't return an error if a port
1549 * isn't defined. It's possible that there is nothing connected to
1552 endpoint = of_graph_get_next_endpoint(np, NULL);
1554 dev_dbg(dev, "%s: no endpoint\n", __func__);
1558 /* Get panel node from the output port's endpoint data */
1559 device_node = of_graph_get_remote_port_parent(endpoint);
1561 dev_err(dev, "%s: no valid device\n", __func__);
1562 of_node_put(endpoint);
1566 of_node_put(endpoint);
1567 of_node_put(device_node);
1569 msm_host->device_node = device_node;
1574 int msm_dsi_host_init(struct msm_dsi *msm_dsi)
1576 struct msm_dsi_host *msm_host = NULL;
1577 struct platform_device *pdev = msm_dsi->pdev;
1580 msm_host = devm_kzalloc(&pdev->dev, sizeof(*msm_host), GFP_KERNEL);
1582 pr_err("%s: FAILED: cannot alloc dsi host\n",
1588 msm_host->pdev = pdev;
1590 ret = dsi_host_parse_dt(msm_host);
1592 pr_err("%s: failed to parse dt\n", __func__);
1596 msm_host->ctrl_base = msm_ioremap(pdev, "dsi_ctrl", "DSI CTRL");
1597 if (IS_ERR(msm_host->ctrl_base)) {
1598 pr_err("%s: unable to map Dsi ctrl base\n", __func__);
1599 ret = PTR_ERR(msm_host->ctrl_base);
1603 msm_host->cfg_hnd = dsi_get_config(msm_host);
1604 if (!msm_host->cfg_hnd) {
1606 pr_err("%s: get config failed\n", __func__);
1610 /* fixup base address by io offset */
1611 msm_host->ctrl_base += msm_host->cfg_hnd->cfg->io_offset;
1613 ret = dsi_regulator_init(msm_host);
1615 pr_err("%s: regulator init failed\n", __func__);
1619 ret = dsi_clk_init(msm_host);
1621 pr_err("%s: unable to initialize dsi clks\n", __func__);
1625 msm_host->rx_buf = devm_kzalloc(&pdev->dev, SZ_4K, GFP_KERNEL);
1626 if (!msm_host->rx_buf) {
1627 pr_err("%s: alloc rx temp buf failed\n", __func__);
1631 init_completion(&msm_host->dma_comp);
1632 init_completion(&msm_host->video_comp);
1633 mutex_init(&msm_host->dev_mutex);
1634 mutex_init(&msm_host->cmd_mutex);
1635 mutex_init(&msm_host->clk_mutex);
1636 spin_lock_init(&msm_host->intr_lock);
1638 /* setup workqueue */
1639 msm_host->workqueue = alloc_ordered_workqueue("dsi_drm_work", 0);
1640 INIT_WORK(&msm_host->err_work, dsi_err_worker);
1642 msm_dsi->host = &msm_host->base;
1643 msm_dsi->id = msm_host->id;
1645 DBG("Dsi Host %d initialized", msm_host->id);
1652 void msm_dsi_host_destroy(struct mipi_dsi_host *host)
1654 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1657 dsi_tx_buf_free(msm_host);
1658 if (msm_host->workqueue) {
1659 flush_workqueue(msm_host->workqueue);
1660 destroy_workqueue(msm_host->workqueue);
1661 msm_host->workqueue = NULL;
1664 mutex_destroy(&msm_host->clk_mutex);
1665 mutex_destroy(&msm_host->cmd_mutex);
1666 mutex_destroy(&msm_host->dev_mutex);
1669 int msm_dsi_host_modeset_init(struct mipi_dsi_host *host,
1670 struct drm_device *dev)
1672 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1673 struct platform_device *pdev = msm_host->pdev;
1676 msm_host->irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
1677 if (msm_host->irq < 0) {
1678 ret = msm_host->irq;
1679 dev_err(dev->dev, "failed to get irq: %d\n", ret);
1683 ret = devm_request_irq(&pdev->dev, msm_host->irq,
1684 dsi_host_irq, IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
1685 "dsi_isr", msm_host);
1687 dev_err(&pdev->dev, "failed to request IRQ%u: %d\n",
1688 msm_host->irq, ret);
1692 msm_host->dev = dev;
1693 ret = dsi_tx_buf_alloc(msm_host, SZ_4K);
1695 pr_err("%s: alloc tx gem obj failed, %d\n", __func__, ret);
1702 int msm_dsi_host_register(struct mipi_dsi_host *host, bool check_defer)
1704 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1707 /* Register mipi dsi host */
1708 if (!msm_host->registered) {
1709 host->dev = &msm_host->pdev->dev;
1710 host->ops = &dsi_host_ops;
1711 ret = mipi_dsi_host_register(host);
1715 msm_host->registered = true;
1717 /* If the panel driver has not been probed after host register,
1718 * we should defer the host's probe.
1719 * It makes sure panel is connected when fbcon detects
1720 * connector status and gets the proper display mode to
1721 * create framebuffer.
1722 * Don't try to defer if there is nothing connected to the dsi
1725 if (check_defer && msm_host->device_node) {
1726 if (!of_drm_find_panel(msm_host->device_node))
1727 if (!of_drm_find_bridge(msm_host->device_node))
1728 return -EPROBE_DEFER;
1735 void msm_dsi_host_unregister(struct mipi_dsi_host *host)
1737 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1739 if (msm_host->registered) {
1740 mipi_dsi_host_unregister(host);
1743 msm_host->registered = false;
1747 int msm_dsi_host_xfer_prepare(struct mipi_dsi_host *host,
1748 const struct mipi_dsi_msg *msg)
1750 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1752 /* TODO: make sure dsi_cmd_mdp is idle.
1753 * Since DSI6G v1.2.0, we can set DSI_TRIG_CTRL.BLOCK_DMA_WITHIN_FRAME
1754 * to ask H/W to wait until cmd mdp is idle. S/W wait is not needed.
1755 * How to handle the old versions? Wait for mdp cmd done?
1759 * mdss interrupt is generated in mdp core clock domain
1760 * mdp clock need to be enabled to receive dsi interrupt
1762 dsi_clk_ctrl(msm_host, 1);
1764 /* TODO: vote for bus bandwidth */
1766 if (!(msg->flags & MIPI_DSI_MSG_USE_LPM))
1767 dsi_set_tx_power_mode(0, msm_host);
1769 msm_host->dma_cmd_ctrl_restore = dsi_read(msm_host, REG_DSI_CTRL);
1770 dsi_write(msm_host, REG_DSI_CTRL,
1771 msm_host->dma_cmd_ctrl_restore |
1772 DSI_CTRL_CMD_MODE_EN |
1774 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_DMA_DONE, 1);
1779 void msm_dsi_host_xfer_restore(struct mipi_dsi_host *host,
1780 const struct mipi_dsi_msg *msg)
1782 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1784 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_DMA_DONE, 0);
1785 dsi_write(msm_host, REG_DSI_CTRL, msm_host->dma_cmd_ctrl_restore);
1787 if (!(msg->flags & MIPI_DSI_MSG_USE_LPM))
1788 dsi_set_tx_power_mode(1, msm_host);
1790 /* TODO: unvote for bus bandwidth */
1792 dsi_clk_ctrl(msm_host, 0);
1795 int msm_dsi_host_cmd_tx(struct mipi_dsi_host *host,
1796 const struct mipi_dsi_msg *msg)
1798 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1800 return dsi_cmds2buf_tx(msm_host, msg);
1803 int msm_dsi_host_cmd_rx(struct mipi_dsi_host *host,
1804 const struct mipi_dsi_msg *msg)
1806 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1807 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
1808 int data_byte, rx_byte, dlen, end;
1809 int short_response, diff, pkt_size, ret = 0;
1811 int rlen = msg->rx_len;
1820 data_byte = 10; /* first read */
1821 if (rlen < data_byte)
1824 pkt_size = data_byte;
1825 rx_byte = data_byte + 6; /* 4 header + 2 crc */
1828 buf = msm_host->rx_buf;
1831 u8 tx[2] = {pkt_size & 0xff, pkt_size >> 8};
1832 struct mipi_dsi_msg max_pkt_size_msg = {
1833 .channel = msg->channel,
1834 .type = MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE,
1839 DBG("rlen=%d pkt_size=%d rx_byte=%d",
1840 rlen, pkt_size, rx_byte);
1842 ret = dsi_cmds2buf_tx(msm_host, &max_pkt_size_msg);
1844 pr_err("%s: Set max pkt size failed, %d\n",
1849 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) &&
1850 (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_1)) {
1851 /* Clear the RDBK_DATA registers */
1852 dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL,
1853 DSI_RDBK_DATA_CTRL_CLR);
1854 wmb(); /* make sure the RDBK registers are cleared */
1855 dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL, 0);
1856 wmb(); /* release cleared status before transfer */
1859 ret = dsi_cmds2buf_tx(msm_host, msg);
1860 if (ret < msg->tx_len) {
1861 pr_err("%s: Read cmd Tx failed, %d\n", __func__, ret);
1866 * once cmd_dma_done interrupt received,
1867 * return data from client is ready and stored
1868 * at RDBK_DATA register already
1869 * since rx fifo is 16 bytes, dcs header is kept at first loop,
1870 * after that dcs header lost during shift into registers
1872 dlen = dsi_cmd_dma_rx(msm_host, buf, rx_byte, pkt_size);
1880 if (rlen <= data_byte) {
1881 diff = data_byte - rlen;
1889 dlen -= 2; /* 2 crc */
1891 buf += dlen; /* next start position */
1892 data_byte = 14; /* NOT first read */
1893 if (rlen < data_byte)
1896 pkt_size += data_byte;
1897 DBG("buf=%p dlen=%d diff=%d", buf, dlen, diff);
1902 * For single Long read, if the requested rlen < 10,
1903 * we need to shift the start position of rx
1904 * data buffer to skip the bytes which are not
1907 if (pkt_size < 10 && !short_response)
1908 buf = msm_host->rx_buf + (10 - rlen);
1910 buf = msm_host->rx_buf;
1914 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
1915 pr_err("%s: rx ACK_ERR_PACLAGE\n", __func__);
1918 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:
1919 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
1920 ret = dsi_short_read1_resp(buf, msg);
1922 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:
1923 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
1924 ret = dsi_short_read2_resp(buf, msg);
1926 case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE:
1927 case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE:
1928 ret = dsi_long_read_resp(buf, msg);
1931 pr_warn("%s:Invalid response cmd\n", __func__);
1938 void msm_dsi_host_cmd_xfer_commit(struct mipi_dsi_host *host, u32 dma_base,
1941 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1943 dsi_write(msm_host, REG_DSI_DMA_BASE, dma_base);
1944 dsi_write(msm_host, REG_DSI_DMA_LEN, len);
1945 dsi_write(msm_host, REG_DSI_TRIG_DMA, 1);
1947 /* Make sure trigger happens */
1951 int msm_dsi_host_set_src_pll(struct mipi_dsi_host *host,
1952 struct msm_dsi_pll *src_pll)
1954 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1955 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
1956 struct clk *byte_clk_provider, *pixel_clk_provider;
1959 ret = msm_dsi_pll_get_clk_provider(src_pll,
1960 &byte_clk_provider, &pixel_clk_provider);
1962 pr_info("%s: can't get provider from pll, don't set parent\n",
1967 ret = clk_set_parent(msm_host->byte_clk_src, byte_clk_provider);
1969 pr_err("%s: can't set parent to byte_clk_src. ret=%d\n",
1974 ret = clk_set_parent(msm_host->pixel_clk_src, pixel_clk_provider);
1976 pr_err("%s: can't set parent to pixel_clk_src. ret=%d\n",
1981 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_V2) {
1982 ret = clk_set_parent(msm_host->dsi_clk_src, pixel_clk_provider);
1984 pr_err("%s: can't set parent to dsi_clk_src. ret=%d\n",
1989 ret = clk_set_parent(msm_host->esc_clk_src, byte_clk_provider);
1991 pr_err("%s: can't set parent to esc_clk_src. ret=%d\n",
2001 int msm_dsi_host_enable(struct mipi_dsi_host *host)
2003 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2005 dsi_op_mode_config(msm_host,
2006 !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO), true);
2008 /* TODO: clock should be turned off for command mode,
2009 * and only turned on before MDP START.
2010 * This part of code should be enabled once mdp driver support it.
2012 /* if (msm_panel->mode == MSM_DSI_CMD_MODE)
2013 dsi_clk_ctrl(msm_host, 0); */
2018 int msm_dsi_host_disable(struct mipi_dsi_host *host)
2020 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2022 dsi_op_mode_config(msm_host,
2023 !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO), false);
2025 /* Since we have disabled INTF, the video engine won't stop so that
2026 * the cmd engine will be blocked.
2027 * Reset to disable video engine so that we can send off cmd.
2029 dsi_sw_reset(msm_host);
2034 int msm_dsi_host_power_on(struct mipi_dsi_host *host)
2036 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2037 u32 clk_pre = 0, clk_post = 0;
2040 mutex_lock(&msm_host->dev_mutex);
2041 if (msm_host->power_on) {
2042 DBG("dsi host already on");
2046 ret = dsi_calc_clk_rate(msm_host);
2048 pr_err("%s: unable to calc clk rate, %d\n", __func__, ret);
2052 ret = dsi_host_regulator_enable(msm_host);
2054 pr_err("%s:Failed to enable vregs.ret=%d\n",
2059 ret = dsi_bus_clk_enable(msm_host);
2061 pr_err("%s: failed to enable bus clocks, %d\n", __func__, ret);
2062 goto fail_disable_reg;
2065 dsi_phy_sw_reset(msm_host);
2066 ret = msm_dsi_manager_phy_enable(msm_host->id,
2067 msm_host->byte_clk_rate * 8,
2068 msm_host->esc_clk_rate,
2069 &clk_pre, &clk_post);
2070 dsi_bus_clk_disable(msm_host);
2072 pr_err("%s: failed to enable phy, %d\n", __func__, ret);
2073 goto fail_disable_reg;
2076 ret = dsi_clk_ctrl(msm_host, 1);
2078 pr_err("%s: failed to enable clocks. ret=%d\n", __func__, ret);
2079 goto fail_disable_reg;
2082 ret = pinctrl_pm_select_default_state(&msm_host->pdev->dev);
2084 pr_err("%s: failed to set pinctrl default state, %d\n",
2086 goto fail_disable_clk;
2089 dsi_timing_setup(msm_host);
2090 dsi_sw_reset(msm_host);
2091 dsi_ctrl_config(msm_host, true, clk_pre, clk_post);
2093 if (msm_host->disp_en_gpio)
2094 gpiod_set_value(msm_host->disp_en_gpio, 1);
2096 msm_host->power_on = true;
2097 mutex_unlock(&msm_host->dev_mutex);
2102 dsi_clk_ctrl(msm_host, 0);
2104 dsi_host_regulator_disable(msm_host);
2106 mutex_unlock(&msm_host->dev_mutex);
2110 int msm_dsi_host_power_off(struct mipi_dsi_host *host)
2112 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2114 mutex_lock(&msm_host->dev_mutex);
2115 if (!msm_host->power_on) {
2116 DBG("dsi host already off");
2120 dsi_ctrl_config(msm_host, false, 0, 0);
2122 if (msm_host->disp_en_gpio)
2123 gpiod_set_value(msm_host->disp_en_gpio, 0);
2125 pinctrl_pm_select_sleep_state(&msm_host->pdev->dev);
2127 msm_dsi_manager_phy_disable(msm_host->id);
2129 dsi_clk_ctrl(msm_host, 0);
2131 dsi_host_regulator_disable(msm_host);
2135 msm_host->power_on = false;
2138 mutex_unlock(&msm_host->dev_mutex);
2142 int msm_dsi_host_set_display_mode(struct mipi_dsi_host *host,
2143 struct drm_display_mode *mode)
2145 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2147 if (msm_host->mode) {
2148 drm_mode_destroy(msm_host->dev, msm_host->mode);
2149 msm_host->mode = NULL;
2152 msm_host->mode = drm_mode_duplicate(msm_host->dev, mode);
2153 if (IS_ERR(msm_host->mode)) {
2154 pr_err("%s: cannot duplicate mode\n", __func__);
2155 return PTR_ERR(msm_host->mode);
2161 struct drm_panel *msm_dsi_host_get_panel(struct mipi_dsi_host *host,
2162 unsigned long *panel_flags)
2164 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2165 struct drm_panel *panel;
2167 panel = of_drm_find_panel(msm_host->device_node);
2169 *panel_flags = msm_host->mode_flags;
2174 struct drm_bridge *msm_dsi_host_get_bridge(struct mipi_dsi_host *host)
2176 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2178 return of_drm_find_bridge(msm_host->device_node);