drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c

   1 /*
   2  * Copyright (C) 2013 Red Hat
   3  * Author: Rob Clark <robdclark@gmail.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published by
   7  * the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18
  19 #include "msm_drv.h"
  20 #include "msm_mmu.h"
  21 #include "mdp4_kms.h"
  22
  23 static struct mdp4_platform_config *mdp4_get_config(struct platform_device *dev);
  24
  25 static int mdp4_hw_init(struct msm_kms *kms)
  26 {
  27         struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
  28         struct drm_device *dev = mdp4_kms->dev;
  29         uint32_t version, major, minor, dmap_cfg, vg_cfg;
  30         unsigned long clk;
  31         int ret = 0;
  32
  33         pm_runtime_get_sync(dev->dev);
  34
  35         mdp4_enable(mdp4_kms);
  36         version = mdp4_read(mdp4_kms, REG_MDP4_VERSION);
  37         mdp4_disable(mdp4_kms);
  38
  39         major = FIELD(version, MDP4_VERSION_MAJOR);
  40         minor = FIELD(version, MDP4_VERSION_MINOR);
  41
  42         DBG("found MDP4 version v%d.%d", major, minor);
  43
  44         if (major != 4) {
  45                 dev_err(dev->dev, "unexpected MDP version: v%d.%d\n",
  46                                 major, minor);
  47                 ret = -ENXIO;
  48                 goto out;
  49         }
  50
  51         mdp4_kms->rev = minor;
  52
  53         if (mdp4_kms->dsi_pll_vdda) {
  54                 if ((mdp4_kms->rev == 2) || (mdp4_kms->rev == 4)) {
  55                         ret = regulator_set_voltage(mdp4_kms->dsi_pll_vdda,
  56                                         1200000, 1200000);
  57                         if (ret) {
  58                                 dev_err(dev->dev,
  59                                         "failed to set dsi_pll_vdda voltage: %d\n", ret);
  60                                 goto out;
  61                         }
  62                 }
  63         }
  64
  65         if (mdp4_kms->dsi_pll_vddio) {
  66                 if (mdp4_kms->rev == 2) {
  67                         ret = regulator_set_voltage(mdp4_kms->dsi_pll_vddio,
  68                                         1800000, 1800000);
  69                         if (ret) {
  70                                 dev_err(dev->dev,
  71                                         "failed to set dsi_pll_vddio voltage: %d\n", ret);
  72                                 goto out;
  73                         }
  74                 }
  75         }
  76
  77         if (mdp4_kms->rev > 1) {
  78                 mdp4_write(mdp4_kms, REG_MDP4_CS_CONTROLLER0, 0x0707ffff);
  79                 mdp4_write(mdp4_kms, REG_MDP4_CS_CONTROLLER1, 0x03073f3f);
  80         }
  81
  82         mdp4_write(mdp4_kms, REG_MDP4_PORTMAP_MODE, 0x3);
  83
  84         /* max read pending cmd config, 3 pending requests: */
  85         mdp4_write(mdp4_kms, REG_MDP4_READ_CNFG, 0x02222);
  86
  87         clk = clk_get_rate(mdp4_kms->clk);
  88
  89         if ((mdp4_kms->rev >= 1) || (clk >= 90000000)) {
  90                 dmap_cfg = 0x47;     /* 16 bytes-burst x 8 req */
  91                 vg_cfg = 0x47;       /* 16 bytes-burs x 8 req */
  92         } else {
  93                 dmap_cfg = 0x27;     /* 8 bytes-burst x 8 req */
  94                 vg_cfg = 0x43;       /* 16 bytes-burst x 4 req */
  95         }
  96
  97         DBG("fetch config: dmap=%02x, vg=%02x", dmap_cfg, vg_cfg);
  98
  99         mdp4_write(mdp4_kms, REG_MDP4_DMA_FETCH_CONFIG(DMA_P), dmap_cfg);
 100         mdp4_write(mdp4_kms, REG_MDP4_DMA_FETCH_CONFIG(DMA_E), dmap_cfg);
 101
 102         mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(VG1), vg_cfg);
 103         mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(VG2), vg_cfg);
 104         mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(RGB1), vg_cfg);
 105         mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(RGB2), vg_cfg);
 106
 107         if (mdp4_kms->rev >= 2)
 108                 mdp4_write(mdp4_kms, REG_MDP4_LAYERMIXER_IN_CFG_UPDATE_METHOD, 1);
 109         mdp4_write(mdp4_kms, REG_MDP4_LAYERMIXER_IN_CFG, 0);
 110
 111         /* disable CSC matrix / YUV by default: */
 112         mdp4_write(mdp4_kms, REG_MDP4_PIPE_OP_MODE(VG1), 0);
 113         mdp4_write(mdp4_kms, REG_MDP4_PIPE_OP_MODE(VG2), 0);
 114         mdp4_write(mdp4_kms, REG_MDP4_DMA_P_OP_MODE, 0);
 115         mdp4_write(mdp4_kms, REG_MDP4_DMA_S_OP_MODE, 0);
 116         mdp4_write(mdp4_kms, REG_MDP4_OVLP_CSC_CONFIG(1), 0);
 117         mdp4_write(mdp4_kms, REG_MDP4_OVLP_CSC_CONFIG(2), 0);
 118
 119         if (mdp4_kms->rev > 1)
 120                 mdp4_write(mdp4_kms, REG_MDP4_RESET_STATUS, 1);
 121
 122         dev->mode_config.allow_fb_modifiers = true;
 123
 124 out:
 125         pm_runtime_put_sync(dev->dev);
 126
 127         return ret;
 128 }
 129
 130 static void mdp4_prepare_commit(struct msm_kms *kms, struct drm_atomic_state *state)
 131 {
 132         struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
 133         int i, ncrtcs = state->dev->mode_config.num_crtc;
 134
 135         mdp4_enable(mdp4_kms);
 136
 137         /* see 119ecb7fd */
 138         for (i = 0; i < ncrtcs; i++) {
 139                 struct drm_crtc *crtc = state->crtcs[i];
 140                 if (!crtc)
 141                         continue;
 142                 drm_crtc_vblank_get(crtc);
 143         }
 144 }
 145
 146 static void mdp4_complete_commit(struct msm_kms *kms, struct drm_atomic_state *state)
 147 {
 148         struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
 149         int i, ncrtcs = state->dev->mode_config.num_crtc;
 150
 151         /* see 119ecb7fd */
 152         for (i = 0; i < ncrtcs; i++) {
 153                 struct drm_crtc *crtc = state->crtcs[i];
 154                 if (!crtc)
 155                         continue;
 156                 drm_crtc_vblank_put(crtc);
 157         }
 158
 159         mdp4_disable(mdp4_kms);
 160 }
 161
 162 static void mdp4_wait_for_crtc_commit_done(struct msm_kms *kms,
 163                                                 struct drm_crtc *crtc)
 164 {
 165         mdp4_crtc_wait_for_commit_done(crtc);
 166 }
 167
 168 static long mdp4_round_pixclk(struct msm_kms *kms, unsigned long rate,
 169                 struct drm_encoder *encoder)
 170 {
 171         /* if we had >1 encoder, we'd need something more clever: */
 172         switch (encoder->encoder_type) {
 173         case DRM_MODE_ENCODER_TMDS:
 174                 return mdp4_dtv_round_pixclk(encoder, rate);
 175         case DRM_MODE_ENCODER_LVDS:
 176         case DRM_MODE_ENCODER_DSI:
 177         default:
 178                 return rate;
 179         }
 180 }
 181
 182 static const char * const iommu_ports[] = {
 183         "mdp_port0_cb0", "mdp_port1_cb0",
 184 };
 185
 186 static void mdp4_destroy(struct msm_kms *kms)
 187 {
 188         struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
 189         struct msm_mmu *mmu = mdp4_kms->mmu;
 190
 191         if (mmu) {
 192                 mmu->funcs->detach(mmu, iommu_ports, ARRAY_SIZE(iommu_ports));
 193                 mmu->funcs->destroy(mmu);
 194         }
 195
 196         if (mdp4_kms->blank_cursor_iova)
 197                 msm_gem_put_iova(mdp4_kms->blank_cursor_bo, mdp4_kms->id);
 198         if (mdp4_kms->blank_cursor_bo)
 199                 drm_gem_object_unreference_unlocked(mdp4_kms->blank_cursor_bo);
 200         kfree(mdp4_kms);
 201 }
 202
 203 static const struct mdp_kms_funcs kms_funcs = {
 204         .base = {
 205                 .hw_init         = mdp4_hw_init,
 206                 .irq_preinstall  = mdp4_irq_preinstall,
 207                 .irq_postinstall = mdp4_irq_postinstall,
 208                 .irq_uninstall   = mdp4_irq_uninstall,
 209                 .irq             = mdp4_irq,
 210                 .enable_vblank   = mdp4_enable_vblank,
 211                 .disable_vblank  = mdp4_disable_vblank,
 212                 .prepare_commit  = mdp4_prepare_commit,
 213                 .complete_commit = mdp4_complete_commit,
 214                 .wait_for_crtc_commit_done = mdp4_wait_for_crtc_commit_done,
 215                 .get_format      = mdp_get_format,
 216                 .round_pixclk    = mdp4_round_pixclk,
 217                 .destroy         = mdp4_destroy,
 218         },
 219         .set_irqmask         = mdp4_set_irqmask,
 220 };
 221
 222 int mdp4_disable(struct mdp4_kms *mdp4_kms)
 223 {
 224         DBG("");
 225
 226         clk_disable_unprepare(mdp4_kms->clk);
 227         if (mdp4_kms->pclk)
 228                 clk_disable_unprepare(mdp4_kms->pclk);
 229         clk_disable_unprepare(mdp4_kms->lut_clk);
 230         if (mdp4_kms->axi_clk)
 231                 clk_disable_unprepare(mdp4_kms->axi_clk);
 232
 233         return 0;
 234 }
 235
 236 int mdp4_enable(struct mdp4_kms *mdp4_kms)
 237 {
 238         DBG("");
 239
 240         clk_prepare_enable(mdp4_kms->clk);
 241         if (mdp4_kms->pclk)
 242                 clk_prepare_enable(mdp4_kms->pclk);
 243         clk_prepare_enable(mdp4_kms->lut_clk);
 244         if (mdp4_kms->axi_clk)
 245                 clk_prepare_enable(mdp4_kms->axi_clk);
 246
 247         return 0;
 248 }
 249
 250 static struct device_node *mdp4_detect_lcdc_panel(struct drm_device *dev)
 251 {
 252         struct device_node *endpoint, *panel_node;
 253         struct device_node *np = dev->dev->of_node;
 254
 255         endpoint = of_graph_get_next_endpoint(np, NULL);
 256         if (!endpoint) {
 257                 DBG("no endpoint in MDP4 to fetch LVDS panel\n");
 258                 return NULL;
 259         }
 260
 261         /* don't proceed if we have an endpoint but no panel_node tied to it */
 262         panel_node = of_graph_get_remote_port_parent(endpoint);
 263         if (!panel_node) {
 264                 dev_err(dev->dev, "no valid panel node\n");
 265                 of_node_put(endpoint);
 266                 return ERR_PTR(-ENODEV);
 267         }
 268
 269         of_node_put(endpoint);
 270
 271         return panel_node;
 272 }
 273
 274 static int mdp4_modeset_init_intf(struct mdp4_kms *mdp4_kms,
 275                                   int intf_type)
 276 {
 277         struct drm_device *dev = mdp4_kms->dev;
 278         struct msm_drm_private *priv = dev->dev_private;
 279         struct drm_encoder *encoder;
 280         struct drm_connector *connector;
 281         struct device_node *panel_node;
 282         struct drm_encoder *dsi_encs[MSM_DSI_ENCODER_NUM];
 283         int i, dsi_id;
 284         int ret;
 285
 286         switch (intf_type) {
 287         case DRM_MODE_ENCODER_LVDS:
 288                 /*
 289                  * bail out early if:
 290                  * - there is no panel node (no need to initialize lcdc
 291                  *   encoder and lvds connector), or
 292                  * - panel node is a bad pointer
 293                  */
 294                 panel_node = mdp4_detect_lcdc_panel(dev);
 295                 if (IS_ERR_OR_NULL(panel_node))
 296                         return PTR_ERR(panel_node);
 297
 298                 encoder = mdp4_lcdc_encoder_init(dev, panel_node);
 299                 if (IS_ERR(encoder)) {
 300                         dev_err(dev->dev, "failed to construct LCDC encoder\n");
 301                         return PTR_ERR(encoder);
 302                 }
 303
 304                 /* LCDC can be hooked to DMA_P (TODO: Add DMA_S later?) */
 305                 encoder->possible_crtcs = 1 << DMA_P;
 306
 307                 connector = mdp4_lvds_connector_init(dev, panel_node, encoder);
 308                 if (IS_ERR(connector)) {
 309                         dev_err(dev->dev, "failed to initialize LVDS connector\n");
 310                         return PTR_ERR(connector);
 311                 }
 312
 313                 priv->encoders[priv->num_encoders++] = encoder;
 314                 priv->connectors[priv->num_connectors++] = connector;
 315
 316                 break;
 317         case DRM_MODE_ENCODER_TMDS:
 318                 encoder = mdp4_dtv_encoder_init(dev);
 319                 if (IS_ERR(encoder)) {
 320                         dev_err(dev->dev, "failed to construct DTV encoder\n");
 321                         return PTR_ERR(encoder);
 322                 }
 323
 324                 /* DTV can be hooked to DMA_E: */
 325                 encoder->possible_crtcs = 1 << 1;
 326
 327                 if (priv->hdmi) {
 328                         /* Construct bridge/connector for HDMI: */
 329                         ret = msm_hdmi_modeset_init(priv->hdmi, dev, encoder);
 330                         if (ret) {
 331                                 dev_err(dev->dev, "failed to initialize HDMI: %d\n", ret);
 332                                 return ret;
 333                         }
 334                 }
 335
 336                 priv->encoders[priv->num_encoders++] = encoder;
 337
 338                 break;
 339         case DRM_MODE_ENCODER_DSI:
 340                 /* only DSI1 supported for now */
 341                 dsi_id = 0;
 342
 343                 if (!priv->dsi[dsi_id])
 344                         break;
 345
 346                 for (i = 0; i < MSM_DSI_ENCODER_NUM; i++) {
 347                         dsi_encs[i] = mdp4_dsi_encoder_init(dev);
 348                         if (IS_ERR(dsi_encs[i])) {
 349                                 ret = PTR_ERR(dsi_encs[i]);
 350                                 dev_err(dev->dev,
 351                                         "failed to construct DSI encoder: %d\n",
 352                                         ret);
 353                                 return ret;
 354                         }
 355
 356                         /* TODO: Add DMA_S later? */
 357                         dsi_encs[i]->possible_crtcs = 1 << DMA_P;
 358                         priv->encoders[priv->num_encoders++] = dsi_encs[i];
 359                 }
 360
 361                 ret = msm_dsi_modeset_init(priv->dsi[dsi_id], dev, dsi_encs);
 362                 if (ret) {
 363                         dev_err(dev->dev, "failed to initialize DSI: %d\n",
 364                                 ret);
 365                         return ret;
 366                 }
 367
 368                 break;
 369         default:
 370                 dev_err(dev->dev, "Invalid or unsupported interface\n");
 371                 return -EINVAL;
 372         }
 373
 374         return 0;
 375 }
 376
 377 static int modeset_init(struct mdp4_kms *mdp4_kms)
 378 {
 379         struct drm_device *dev = mdp4_kms->dev;
 380         struct msm_drm_private *priv = dev->dev_private;
 381         struct drm_plane *plane;
 382         struct drm_crtc *crtc;
 383         int i, ret;
 384         static const enum mdp4_pipe rgb_planes[] = {
 385                 RGB1, RGB2,
 386         };
 387         static const enum mdp4_pipe vg_planes[] = {
 388                 VG1, VG2,
 389         };
 390         static const enum mdp4_dma mdp4_crtcs[] = {
 391                 DMA_P, DMA_E,
 392         };
 393         static const char * const mdp4_crtc_names[] = {
 394                 "DMA_P", "DMA_E",
 395         };
 396         static const int mdp4_intfs[] = {
 397                 DRM_MODE_ENCODER_LVDS,
 398                 DRM_MODE_ENCODER_DSI,
 399                 DRM_MODE_ENCODER_TMDS,
 400         };
 401
 402         /* construct non-private planes: */
 403         for (i = 0; i < ARRAY_SIZE(vg_planes); i++) {
 404                 plane = mdp4_plane_init(dev, vg_planes[i], false);
 405                 if (IS_ERR(plane)) {
 406                         dev_err(dev->dev,
 407                                 "failed to construct plane for VG%d\n", i + 1);
 408                         ret = PTR_ERR(plane);
 409                         goto fail;
 410                 }
 411                 priv->planes[priv->num_planes++] = plane;
 412         }
 413
 414         for (i = 0; i < ARRAY_SIZE(mdp4_crtcs); i++) {
 415                 plane = mdp4_plane_init(dev, rgb_planes[i], true);
 416                 if (IS_ERR(plane)) {
 417                         dev_err(dev->dev,
 418                                 "failed to construct plane for RGB%d\n", i + 1);
 419                         ret = PTR_ERR(plane);
 420                         goto fail;
 421                 }
 422
 423                 crtc  = mdp4_crtc_init(dev, plane, priv->num_crtcs, i,
 424                                 mdp4_crtcs[i]);
 425                 if (IS_ERR(crtc)) {
 426                         dev_err(dev->dev, "failed to construct crtc for %s\n",
 427                                 mdp4_crtc_names[i]);
 428                         ret = PTR_ERR(crtc);
 429                         goto fail;
 430                 }
 431
 432                 priv->crtcs[priv->num_crtcs++] = crtc;
 433         }
 434
 435         /*
 436          * we currently set up two relatively fixed paths:
 437          *
 438          * LCDC/LVDS path: RGB1 -> DMA_P -> LCDC -> LVDS
 439          *                      or
 440          * DSI path: RGB1 -> DMA_P -> DSI1 -> DSI Panel
 441          *
 442          * DTV/HDMI path: RGB2 -> DMA_E -> DTV -> HDMI
 443          */
 444
 445         for (i = 0; i < ARRAY_SIZE(mdp4_intfs); i++) {
 446                 ret = mdp4_modeset_init_intf(mdp4_kms, mdp4_intfs[i]);
 447                 if (ret) {
 448                         dev_err(dev->dev, "failed to initialize intf: %d, %d\n",
 449                                 i, ret);
 450                         goto fail;
 451                 }
 452         }
 453
 454         return 0;
 455
 456 fail:
 457         return ret;
 458 }
 459
 460 struct msm_kms *mdp4_kms_init(struct drm_device *dev)
 461 {
 462         struct platform_device *pdev = dev->platformdev;
 463         struct mdp4_platform_config *config = mdp4_get_config(pdev);
 464         struct mdp4_kms *mdp4_kms;
 465         struct msm_kms *kms = NULL;
 466         struct msm_mmu *mmu;
 467         int ret;
 468
 469         mdp4_kms = kzalloc(sizeof(*mdp4_kms), GFP_KERNEL);
 470         if (!mdp4_kms) {
 471                 dev_err(dev->dev, "failed to allocate kms\n");
 472                 ret = -ENOMEM;
 473                 goto fail;
 474         }
 475
 476         mdp_kms_init(&mdp4_kms->base, &kms_funcs);
 477
 478         kms = &mdp4_kms->base.base;
 479
 480         mdp4_kms->dev = dev;
 481
 482         mdp4_kms->mmio = msm_ioremap(pdev, NULL, "MDP4");
 483         if (IS_ERR(mdp4_kms->mmio)) {
 484                 ret = PTR_ERR(mdp4_kms->mmio);
 485                 goto fail;
 486         }
 487
 488         mdp4_kms->dsi_pll_vdda =
 489                         devm_regulator_get_optional(&pdev->dev, "dsi_pll_vdda");
 490         if (IS_ERR(mdp4_kms->dsi_pll_vdda))
 491                 mdp4_kms->dsi_pll_vdda = NULL;
 492
 493         mdp4_kms->dsi_pll_vddio =
 494                         devm_regulator_get_optional(&pdev->dev, "dsi_pll_vddio");
 495         if (IS_ERR(mdp4_kms->dsi_pll_vddio))
 496                 mdp4_kms->dsi_pll_vddio = NULL;
 497
 498         /* NOTE: driver for this regulator still missing upstream.. use
 499          * _get_exclusive() and ignore the error if it does not exist
 500          * (and hope that the bootloader left it on for us)
 501          */
 502         mdp4_kms->vdd = devm_regulator_get_exclusive(&pdev->dev, "vdd");
 503         if (IS_ERR(mdp4_kms->vdd))
 504                 mdp4_kms->vdd = NULL;
 505
 506         if (mdp4_kms->vdd) {
 507                 ret = regulator_enable(mdp4_kms->vdd);
 508                 if (ret) {
 509                         dev_err(dev->dev, "failed to enable regulator vdd: %d\n", ret);
 510                         goto fail;
 511                 }
 512         }
 513
 514         mdp4_kms->clk = devm_clk_get(&pdev->dev, "core_clk");
 515         if (IS_ERR(mdp4_kms->clk)) {
 516                 dev_err(dev->dev, "failed to get core_clk\n");
 517                 ret = PTR_ERR(mdp4_kms->clk);
 518                 goto fail;
 519         }
 520
 521         mdp4_kms->pclk = devm_clk_get(&pdev->dev, "iface_clk");
 522         if (IS_ERR(mdp4_kms->pclk))
 523                 mdp4_kms->pclk = NULL;
 524
 525         // XXX if (rev >= MDP_REV_42) { ???
 526         mdp4_kms->lut_clk = devm_clk_get(&pdev->dev, "lut_clk");
 527         if (IS_ERR(mdp4_kms->lut_clk)) {
 528                 dev_err(dev->dev, "failed to get lut_clk\n");
 529                 ret = PTR_ERR(mdp4_kms->lut_clk);
 530                 goto fail;
 531         }
 532
 533         mdp4_kms->axi_clk = devm_clk_get(&pdev->dev, "mdp_axi_clk");
 534         if (IS_ERR(mdp4_kms->axi_clk)) {
 535                 dev_err(dev->dev, "failed to get axi_clk\n");
 536                 ret = PTR_ERR(mdp4_kms->axi_clk);
 537                 goto fail;
 538         }
 539
 540         clk_set_rate(mdp4_kms->clk, config->max_clk);
 541         clk_set_rate(mdp4_kms->lut_clk, config->max_clk);
 542
 543         /* make sure things are off before attaching iommu (bootloader could
 544          * have left things on, in which case we'll start getting faults if
 545          * we don't disable):
 546          */
 547         mdp4_enable(mdp4_kms);
 548         mdp4_write(mdp4_kms, REG_MDP4_DTV_ENABLE, 0);
 549         mdp4_write(mdp4_kms, REG_MDP4_LCDC_ENABLE, 0);
 550         mdp4_write(mdp4_kms, REG_MDP4_DSI_ENABLE, 0);
 551         mdp4_disable(mdp4_kms);
 552         mdelay(16);
 553
 554         if (config->iommu) {
 555                 mmu = msm_iommu_new(&pdev->dev, config->iommu);
 556                 if (IS_ERR(mmu)) {
 557                         ret = PTR_ERR(mmu);
 558                         goto fail;
 559                 }
 560                 ret = mmu->funcs->attach(mmu, iommu_ports,
 561                                 ARRAY_SIZE(iommu_ports));
 562                 if (ret)
 563                         goto fail;
 564
 565                 mdp4_kms->mmu = mmu;
 566         } else {
 567                 dev_info(dev->dev, "no iommu, fallback to phys "
 568                                 "contig buffers for scanout\n");
 569                 mmu = NULL;
 570         }
 571
 572         mdp4_kms->id = msm_register_mmu(dev, mmu);
 573         if (mdp4_kms->id < 0) {
 574                 ret = mdp4_kms->id;
 575                 dev_err(dev->dev, "failed to register mdp4 iommu: %d\n", ret);
 576                 goto fail;
 577         }
 578
 579         ret = modeset_init(mdp4_kms);
 580         if (ret) {
 581                 dev_err(dev->dev, "modeset_init failed: %d\n", ret);
 582                 goto fail;
 583         }
 584
 585         mutex_lock(&dev->struct_mutex);
 586         mdp4_kms->blank_cursor_bo = msm_gem_new(dev, SZ_16K, MSM_BO_WC);
 587         mutex_unlock(&dev->struct_mutex);
 588         if (IS_ERR(mdp4_kms->blank_cursor_bo)) {
 589                 ret = PTR_ERR(mdp4_kms->blank_cursor_bo);
 590                 dev_err(dev->dev, "could not allocate blank-cursor bo: %d\n", ret);
 591                 mdp4_kms->blank_cursor_bo = NULL;
 592                 goto fail;
 593         }
 594
 595         ret = msm_gem_get_iova(mdp4_kms->blank_cursor_bo, mdp4_kms->id,
 596                         &mdp4_kms->blank_cursor_iova);
 597         if (ret) {
 598                 dev_err(dev->dev, "could not pin blank-cursor bo: %d\n", ret);
 599                 goto fail;
 600         }
 601
 602         dev->mode_config.min_width = 0;
 603         dev->mode_config.min_height = 0;
 604         dev->mode_config.max_width = 2048;
 605         dev->mode_config.max_height = 2048;
 606
 607         return kms;
 608
 609 fail:
 610         if (kms)
 611                 mdp4_destroy(kms);
 612         return ERR_PTR(ret);
 613 }
 614
 615 static struct mdp4_platform_config *mdp4_get_config(struct platform_device *dev)
 616 {
 617         static struct mdp4_platform_config config = {};
 618
 619         /* TODO: Chips that aren't apq8064 have a 200 Mhz max_clk */
 620         config.max_clk = 266667000;
 621         config.iommu = iommu_domain_alloc(&platform_bus_type);
 622
 623         return &config;
 624 }