2 * Copyright (C) 2013 Red Hat
3 * Author: Rob Clark <robdclark@gmail.com>
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
23 static struct mdp4_platform_config *mdp4_get_config(struct platform_device *dev);
25 static int mdp4_hw_init(struct msm_kms *kms)
27 struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
28 struct drm_device *dev = mdp4_kms->dev;
29 uint32_t version, major, minor, dmap_cfg, vg_cfg;
33 pm_runtime_get_sync(dev->dev);
35 mdp4_enable(mdp4_kms);
36 version = mdp4_read(mdp4_kms, REG_MDP4_VERSION);
37 mdp4_disable(mdp4_kms);
39 major = FIELD(version, MDP4_VERSION_MAJOR);
40 minor = FIELD(version, MDP4_VERSION_MINOR);
42 DBG("found MDP4 version v%d.%d", major, minor);
45 dev_err(dev->dev, "unexpected MDP version: v%d.%d\n",
51 mdp4_kms->rev = minor;
53 if (mdp4_kms->dsi_pll_vdda) {
54 if ((mdp4_kms->rev == 2) || (mdp4_kms->rev == 4)) {
55 ret = regulator_set_voltage(mdp4_kms->dsi_pll_vdda,
59 "failed to set dsi_pll_vdda voltage: %d\n", ret);
65 if (mdp4_kms->dsi_pll_vddio) {
66 if (mdp4_kms->rev == 2) {
67 ret = regulator_set_voltage(mdp4_kms->dsi_pll_vddio,
71 "failed to set dsi_pll_vddio voltage: %d\n", ret);
77 if (mdp4_kms->rev > 1) {
78 mdp4_write(mdp4_kms, REG_MDP4_CS_CONTROLLER0, 0x0707ffff);
79 mdp4_write(mdp4_kms, REG_MDP4_CS_CONTROLLER1, 0x03073f3f);
82 mdp4_write(mdp4_kms, REG_MDP4_PORTMAP_MODE, 0x3);
84 /* max read pending cmd config, 3 pending requests: */
85 mdp4_write(mdp4_kms, REG_MDP4_READ_CNFG, 0x02222);
87 clk = clk_get_rate(mdp4_kms->clk);
89 if ((mdp4_kms->rev >= 1) || (clk >= 90000000)) {
90 dmap_cfg = 0x47; /* 16 bytes-burst x 8 req */
91 vg_cfg = 0x47; /* 16 bytes-burs x 8 req */
93 dmap_cfg = 0x27; /* 8 bytes-burst x 8 req */
94 vg_cfg = 0x43; /* 16 bytes-burst x 4 req */
97 DBG("fetch config: dmap=%02x, vg=%02x", dmap_cfg, vg_cfg);
99 mdp4_write(mdp4_kms, REG_MDP4_DMA_FETCH_CONFIG(DMA_P), dmap_cfg);
100 mdp4_write(mdp4_kms, REG_MDP4_DMA_FETCH_CONFIG(DMA_E), dmap_cfg);
102 mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(VG1), vg_cfg);
103 mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(VG2), vg_cfg);
104 mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(RGB1), vg_cfg);
105 mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(RGB2), vg_cfg);
107 if (mdp4_kms->rev >= 2)
108 mdp4_write(mdp4_kms, REG_MDP4_LAYERMIXER_IN_CFG_UPDATE_METHOD, 1);
109 mdp4_write(mdp4_kms, REG_MDP4_LAYERMIXER_IN_CFG, 0);
111 /* disable CSC matrix / YUV by default: */
112 mdp4_write(mdp4_kms, REG_MDP4_PIPE_OP_MODE(VG1), 0);
113 mdp4_write(mdp4_kms, REG_MDP4_PIPE_OP_MODE(VG2), 0);
114 mdp4_write(mdp4_kms, REG_MDP4_DMA_P_OP_MODE, 0);
115 mdp4_write(mdp4_kms, REG_MDP4_DMA_S_OP_MODE, 0);
116 mdp4_write(mdp4_kms, REG_MDP4_OVLP_CSC_CONFIG(1), 0);
117 mdp4_write(mdp4_kms, REG_MDP4_OVLP_CSC_CONFIG(2), 0);
119 if (mdp4_kms->rev > 1)
120 mdp4_write(mdp4_kms, REG_MDP4_RESET_STATUS, 1);
122 dev->mode_config.allow_fb_modifiers = true;
125 pm_runtime_put_sync(dev->dev);
130 static void mdp4_prepare_commit(struct msm_kms *kms, struct drm_atomic_state *state)
132 struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
133 int i, ncrtcs = state->dev->mode_config.num_crtc;
135 mdp4_enable(mdp4_kms);
138 for (i = 0; i < ncrtcs; i++) {
139 struct drm_crtc *crtc = state->crtcs[i];
142 drm_crtc_vblank_get(crtc);
146 static void mdp4_complete_commit(struct msm_kms *kms, struct drm_atomic_state *state)
148 struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
149 int i, ncrtcs = state->dev->mode_config.num_crtc;
152 for (i = 0; i < ncrtcs; i++) {
153 struct drm_crtc *crtc = state->crtcs[i];
156 drm_crtc_vblank_put(crtc);
159 mdp4_disable(mdp4_kms);
162 static void mdp4_wait_for_crtc_commit_done(struct msm_kms *kms,
163 struct drm_crtc *crtc)
165 mdp4_crtc_wait_for_commit_done(crtc);
168 static long mdp4_round_pixclk(struct msm_kms *kms, unsigned long rate,
169 struct drm_encoder *encoder)
171 /* if we had >1 encoder, we'd need something more clever: */
172 switch (encoder->encoder_type) {
173 case DRM_MODE_ENCODER_TMDS:
174 return mdp4_dtv_round_pixclk(encoder, rate);
175 case DRM_MODE_ENCODER_LVDS:
176 case DRM_MODE_ENCODER_DSI:
182 static const char * const iommu_ports[] = {
183 "mdp_port0_cb0", "mdp_port1_cb0",
186 static void mdp4_destroy(struct msm_kms *kms)
188 struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
189 struct msm_mmu *mmu = mdp4_kms->mmu;
192 mmu->funcs->detach(mmu, iommu_ports, ARRAY_SIZE(iommu_ports));
193 mmu->funcs->destroy(mmu);
196 if (mdp4_kms->blank_cursor_iova)
197 msm_gem_put_iova(mdp4_kms->blank_cursor_bo, mdp4_kms->id);
198 if (mdp4_kms->blank_cursor_bo)
199 drm_gem_object_unreference_unlocked(mdp4_kms->blank_cursor_bo);
203 static const struct mdp_kms_funcs kms_funcs = {
205 .hw_init = mdp4_hw_init,
206 .irq_preinstall = mdp4_irq_preinstall,
207 .irq_postinstall = mdp4_irq_postinstall,
208 .irq_uninstall = mdp4_irq_uninstall,
210 .enable_vblank = mdp4_enable_vblank,
211 .disable_vblank = mdp4_disable_vblank,
212 .prepare_commit = mdp4_prepare_commit,
213 .complete_commit = mdp4_complete_commit,
214 .wait_for_crtc_commit_done = mdp4_wait_for_crtc_commit_done,
215 .get_format = mdp_get_format,
216 .round_pixclk = mdp4_round_pixclk,
217 .destroy = mdp4_destroy,
219 .set_irqmask = mdp4_set_irqmask,
222 int mdp4_disable(struct mdp4_kms *mdp4_kms)
226 clk_disable_unprepare(mdp4_kms->clk);
228 clk_disable_unprepare(mdp4_kms->pclk);
229 clk_disable_unprepare(mdp4_kms->lut_clk);
230 if (mdp4_kms->axi_clk)
231 clk_disable_unprepare(mdp4_kms->axi_clk);
236 int mdp4_enable(struct mdp4_kms *mdp4_kms)
240 clk_prepare_enable(mdp4_kms->clk);
242 clk_prepare_enable(mdp4_kms->pclk);
243 clk_prepare_enable(mdp4_kms->lut_clk);
244 if (mdp4_kms->axi_clk)
245 clk_prepare_enable(mdp4_kms->axi_clk);
250 static struct device_node *mdp4_detect_lcdc_panel(struct drm_device *dev)
252 struct device_node *endpoint, *panel_node;
253 struct device_node *np = dev->dev->of_node;
255 endpoint = of_graph_get_next_endpoint(np, NULL);
257 DBG("no endpoint in MDP4 to fetch LVDS panel\n");
261 /* don't proceed if we have an endpoint but no panel_node tied to it */
262 panel_node = of_graph_get_remote_port_parent(endpoint);
264 dev_err(dev->dev, "no valid panel node\n");
265 of_node_put(endpoint);
266 return ERR_PTR(-ENODEV);
269 of_node_put(endpoint);
274 static int mdp4_modeset_init_intf(struct mdp4_kms *mdp4_kms,
277 struct drm_device *dev = mdp4_kms->dev;
278 struct msm_drm_private *priv = dev->dev_private;
279 struct drm_encoder *encoder;
280 struct drm_connector *connector;
281 struct device_node *panel_node;
282 struct drm_encoder *dsi_encs[MSM_DSI_ENCODER_NUM];
287 case DRM_MODE_ENCODER_LVDS:
290 * - there is no panel node (no need to initialize lcdc
291 * encoder and lvds connector), or
292 * - panel node is a bad pointer
294 panel_node = mdp4_detect_lcdc_panel(dev);
295 if (IS_ERR_OR_NULL(panel_node))
296 return PTR_ERR(panel_node);
298 encoder = mdp4_lcdc_encoder_init(dev, panel_node);
299 if (IS_ERR(encoder)) {
300 dev_err(dev->dev, "failed to construct LCDC encoder\n");
301 return PTR_ERR(encoder);
304 /* LCDC can be hooked to DMA_P (TODO: Add DMA_S later?) */
305 encoder->possible_crtcs = 1 << DMA_P;
307 connector = mdp4_lvds_connector_init(dev, panel_node, encoder);
308 if (IS_ERR(connector)) {
309 dev_err(dev->dev, "failed to initialize LVDS connector\n");
310 return PTR_ERR(connector);
313 priv->encoders[priv->num_encoders++] = encoder;
314 priv->connectors[priv->num_connectors++] = connector;
317 case DRM_MODE_ENCODER_TMDS:
318 encoder = mdp4_dtv_encoder_init(dev);
319 if (IS_ERR(encoder)) {
320 dev_err(dev->dev, "failed to construct DTV encoder\n");
321 return PTR_ERR(encoder);
324 /* DTV can be hooked to DMA_E: */
325 encoder->possible_crtcs = 1 << 1;
328 /* Construct bridge/connector for HDMI: */
329 ret = msm_hdmi_modeset_init(priv->hdmi, dev, encoder);
331 dev_err(dev->dev, "failed to initialize HDMI: %d\n", ret);
336 priv->encoders[priv->num_encoders++] = encoder;
339 case DRM_MODE_ENCODER_DSI:
340 /* only DSI1 supported for now */
343 if (!priv->dsi[dsi_id])
346 for (i = 0; i < MSM_DSI_ENCODER_NUM; i++) {
347 dsi_encs[i] = mdp4_dsi_encoder_init(dev);
348 if (IS_ERR(dsi_encs[i])) {
349 ret = PTR_ERR(dsi_encs[i]);
351 "failed to construct DSI encoder: %d\n",
356 /* TODO: Add DMA_S later? */
357 dsi_encs[i]->possible_crtcs = 1 << DMA_P;
358 priv->encoders[priv->num_encoders++] = dsi_encs[i];
361 ret = msm_dsi_modeset_init(priv->dsi[dsi_id], dev, dsi_encs);
363 dev_err(dev->dev, "failed to initialize DSI: %d\n",
370 dev_err(dev->dev, "Invalid or unsupported interface\n");
377 static int modeset_init(struct mdp4_kms *mdp4_kms)
379 struct drm_device *dev = mdp4_kms->dev;
380 struct msm_drm_private *priv = dev->dev_private;
381 struct drm_plane *plane;
382 struct drm_crtc *crtc;
384 static const enum mdp4_pipe rgb_planes[] = {
387 static const enum mdp4_pipe vg_planes[] = {
390 static const enum mdp4_dma mdp4_crtcs[] = {
393 static const char * const mdp4_crtc_names[] = {
396 static const int mdp4_intfs[] = {
397 DRM_MODE_ENCODER_LVDS,
398 DRM_MODE_ENCODER_DSI,
399 DRM_MODE_ENCODER_TMDS,
402 /* construct non-private planes: */
403 for (i = 0; i < ARRAY_SIZE(vg_planes); i++) {
404 plane = mdp4_plane_init(dev, vg_planes[i], false);
407 "failed to construct plane for VG%d\n", i + 1);
408 ret = PTR_ERR(plane);
411 priv->planes[priv->num_planes++] = plane;
414 for (i = 0; i < ARRAY_SIZE(mdp4_crtcs); i++) {
415 plane = mdp4_plane_init(dev, rgb_planes[i], true);
418 "failed to construct plane for RGB%d\n", i + 1);
419 ret = PTR_ERR(plane);
423 crtc = mdp4_crtc_init(dev, plane, priv->num_crtcs, i,
426 dev_err(dev->dev, "failed to construct crtc for %s\n",
432 priv->crtcs[priv->num_crtcs++] = crtc;
436 * we currently set up two relatively fixed paths:
438 * LCDC/LVDS path: RGB1 -> DMA_P -> LCDC -> LVDS
440 * DSI path: RGB1 -> DMA_P -> DSI1 -> DSI Panel
442 * DTV/HDMI path: RGB2 -> DMA_E -> DTV -> HDMI
445 for (i = 0; i < ARRAY_SIZE(mdp4_intfs); i++) {
446 ret = mdp4_modeset_init_intf(mdp4_kms, mdp4_intfs[i]);
448 dev_err(dev->dev, "failed to initialize intf: %d, %d\n",
460 struct msm_kms *mdp4_kms_init(struct drm_device *dev)
462 struct platform_device *pdev = dev->platformdev;
463 struct mdp4_platform_config *config = mdp4_get_config(pdev);
464 struct mdp4_kms *mdp4_kms;
465 struct msm_kms *kms = NULL;
469 mdp4_kms = kzalloc(sizeof(*mdp4_kms), GFP_KERNEL);
471 dev_err(dev->dev, "failed to allocate kms\n");
476 mdp_kms_init(&mdp4_kms->base, &kms_funcs);
478 kms = &mdp4_kms->base.base;
482 mdp4_kms->mmio = msm_ioremap(pdev, NULL, "MDP4");
483 if (IS_ERR(mdp4_kms->mmio)) {
484 ret = PTR_ERR(mdp4_kms->mmio);
488 mdp4_kms->dsi_pll_vdda =
489 devm_regulator_get_optional(&pdev->dev, "dsi_pll_vdda");
490 if (IS_ERR(mdp4_kms->dsi_pll_vdda))
491 mdp4_kms->dsi_pll_vdda = NULL;
493 mdp4_kms->dsi_pll_vddio =
494 devm_regulator_get_optional(&pdev->dev, "dsi_pll_vddio");
495 if (IS_ERR(mdp4_kms->dsi_pll_vddio))
496 mdp4_kms->dsi_pll_vddio = NULL;
498 /* NOTE: driver for this regulator still missing upstream.. use
499 * _get_exclusive() and ignore the error if it does not exist
500 * (and hope that the bootloader left it on for us)
502 mdp4_kms->vdd = devm_regulator_get_exclusive(&pdev->dev, "vdd");
503 if (IS_ERR(mdp4_kms->vdd))
504 mdp4_kms->vdd = NULL;
507 ret = regulator_enable(mdp4_kms->vdd);
509 dev_err(dev->dev, "failed to enable regulator vdd: %d\n", ret);
514 mdp4_kms->clk = devm_clk_get(&pdev->dev, "core_clk");
515 if (IS_ERR(mdp4_kms->clk)) {
516 dev_err(dev->dev, "failed to get core_clk\n");
517 ret = PTR_ERR(mdp4_kms->clk);
521 mdp4_kms->pclk = devm_clk_get(&pdev->dev, "iface_clk");
522 if (IS_ERR(mdp4_kms->pclk))
523 mdp4_kms->pclk = NULL;
525 // XXX if (rev >= MDP_REV_42) { ???
526 mdp4_kms->lut_clk = devm_clk_get(&pdev->dev, "lut_clk");
527 if (IS_ERR(mdp4_kms->lut_clk)) {
528 dev_err(dev->dev, "failed to get lut_clk\n");
529 ret = PTR_ERR(mdp4_kms->lut_clk);
533 mdp4_kms->axi_clk = devm_clk_get(&pdev->dev, "mdp_axi_clk");
534 if (IS_ERR(mdp4_kms->axi_clk)) {
535 dev_err(dev->dev, "failed to get axi_clk\n");
536 ret = PTR_ERR(mdp4_kms->axi_clk);
540 clk_set_rate(mdp4_kms->clk, config->max_clk);
541 clk_set_rate(mdp4_kms->lut_clk, config->max_clk);
543 /* make sure things are off before attaching iommu (bootloader could
544 * have left things on, in which case we'll start getting faults if
547 mdp4_enable(mdp4_kms);
548 mdp4_write(mdp4_kms, REG_MDP4_DTV_ENABLE, 0);
549 mdp4_write(mdp4_kms, REG_MDP4_LCDC_ENABLE, 0);
550 mdp4_write(mdp4_kms, REG_MDP4_DSI_ENABLE, 0);
551 mdp4_disable(mdp4_kms);
555 mmu = msm_iommu_new(&pdev->dev, config->iommu);
560 ret = mmu->funcs->attach(mmu, iommu_ports,
561 ARRAY_SIZE(iommu_ports));
567 dev_info(dev->dev, "no iommu, fallback to phys "
568 "contig buffers for scanout\n");
572 mdp4_kms->id = msm_register_mmu(dev, mmu);
573 if (mdp4_kms->id < 0) {
575 dev_err(dev->dev, "failed to register mdp4 iommu: %d\n", ret);
579 ret = modeset_init(mdp4_kms);
581 dev_err(dev->dev, "modeset_init failed: %d\n", ret);
585 mutex_lock(&dev->struct_mutex);
586 mdp4_kms->blank_cursor_bo = msm_gem_new(dev, SZ_16K, MSM_BO_WC);
587 mutex_unlock(&dev->struct_mutex);
588 if (IS_ERR(mdp4_kms->blank_cursor_bo)) {
589 ret = PTR_ERR(mdp4_kms->blank_cursor_bo);
590 dev_err(dev->dev, "could not allocate blank-cursor bo: %d\n", ret);
591 mdp4_kms->blank_cursor_bo = NULL;
595 ret = msm_gem_get_iova(mdp4_kms->blank_cursor_bo, mdp4_kms->id,
596 &mdp4_kms->blank_cursor_iova);
598 dev_err(dev->dev, "could not pin blank-cursor bo: %d\n", ret);
602 dev->mode_config.min_width = 0;
603 dev->mode_config.min_height = 0;
604 dev->mode_config.max_width = 2048;
605 dev->mode_config.max_height = 2048;
615 static struct mdp4_platform_config *mdp4_get_config(struct platform_device *dev)
617 static struct mdp4_platform_config config = {};
619 /* TODO: Chips that aren't apq8064 have a 200 Mhz max_clk */
620 config.max_clk = 266667000;
621 config.iommu = iommu_domain_alloc(&platform_bus_type);